From cff8c546dbecfd78b520128d8b028a7301e62170 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 11 Nov 2022 19:54:38 +0100 Subject: [PATCH] ipq806x: fix non working switch for eax500 devices It seems on Linksys EA7500/EA8500 devices gpio63 that in reference board is used for reset of pcie2, is repurposed as swtich reset. On old kernel it was used an hack to set it low at boot time and enable pcie2 to make the switch work. In new kernel it seems pcie code changed and now the pcie line is helf in reset if nothing is connected. Try to address this correctly by removing the gpio from pcie2 reset and correctly set it as switch reset. This is based on an old commit and all the info based here [0] [0] https://github.com/openwrt/openwrt/pull/2047 Signed-off-by: Christian Marangi --- .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi index adf5192ac8..b69133e6d4 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -12,6 +12,17 @@ }; }; +&qcom_pinmux { + switch_reset: switch_reset_pins { + mux { + pins = "gpio63"; + function = "gpio"; + drive-strength = <12>; + bias-pull-up; + }; + }; +}; + &hs_phy_0 { status = "okay"; }; @@ -46,8 +57,12 @@ status = "okay"; }; +/delete-node/ &pcie2_pins; + &pcie2 { - status = "okay"; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpio; }; &nand { @@ -173,6 +188,9 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; + reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + reset-duration = <10>; + phy0: ethernet-phy@0 { reg = <0>; qca,ar8327-initvals = < -- 2.30.2