From f78d5da6e7bd500df734bd1d5260f99ceee9d01f Mon Sep 17 00:00:00 2001 From: Radhakrishna Sripada Date: Thu, 9 Jan 2020 14:37:27 -0800 Subject: [PATCH] drm/i915/tgl: Add Wa_1409825376 to tgl Workaround database indicates we should disable VRH clockgating in pre-production hardware. V2: - Use REG_BIT macro - Update reference in commit message(Matt) Bspec: 52890 Bspec: 49424 Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e5071af4a3b3..5e5949edf2a8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4124,6 +4124,9 @@ enum { #define PWM2_GATING_DIS (1 << 14) #define PWM1_GATING_DIS (1 << 13) +#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) +#define TGL_VRH_GATING_DIS REG_BIT(31) + #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) #define BXT_GMBUS_GATING_DIS (1 << 14) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bd2d30ecc030..8e5f08c58b0c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6663,6 +6663,11 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(POWERGATE_ENABLE, I915_READ(POWERGATE_ENABLE) | vd_pg_enable); + + /* Wa_1409825376:tgl (pre-prod)*/ + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) + I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | + TGL_VRH_GATING_DIS); } static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.30.2