From ed25e3ac02d9193d7cba89563a88b8bccc4b4513 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Mon, 19 Nov 2018 00:07:01 +0800 Subject: [PATCH] ramips: fix some clocks in mt7621.dtsi As the cpu clock calculation has been fixed, the clock for gic and spi should be also fixed. Signed-off-by: Weijie Gao --- target/linux/ramips/dts/mt7621.dtsi | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 89f3f6fe2d14..3c610e49d50a 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -41,14 +41,6 @@ clock-output-names = "cpu", "bus"; }; - cpuclock: cpuclock { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - sysclock: sysclock { #clock-cells = <0>; compatible = "fixed-clock"; @@ -176,7 +168,6 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; clock-frequency = <50000000>; interrupt-parent = <&gic>; @@ -193,7 +184,7 @@ compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_BUS>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -402,7 +393,7 @@ timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; -- 2.30.2