From e8adb3a0f74cf568030b7bd1f77d877e6f308d17 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Aug 2019 15:45:10 +0200 Subject: [PATCH] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The .set_rate() callback for the SD clocks is always called with a valid clock rate, returned by .round_rate(). Hence there is no need to iterate through the divider table twice: once to repeat the work done by .round_rate(), and a second time to find the corresponding divider entry. Just iterate once, looking for the divider that matches the passed clock rate. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be --- drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index c594bc067c3b..0866be30dc72 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { struct sd_clock *clock = to_sd_clock(hw); - unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); unsigned int i; for (i = 0; i < clock->div_num; i++) - if (div == clock->div_table[i].div) + if (rate == DIV_ROUND_CLOSEST(parent_rate, + clock->div_table[i].div)) break; if (i >= clock->div_num) -- 2.30.2