From e1abd5600b0ddc3f821b0c8c3fae45d530583a85 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 17 Apr 2019 13:47:07 +0200 Subject: [PATCH] arch: add some defines for generic timer registers Those defines are used in STM32MP1 clock driver. It is better to put them altogether with already defined registers. Change-Id: I6f8ad8c2477b947af6f76283a4ef5c40212d0027 Signed-off-by: Yann Gautier --- drivers/st/clk/stm32mp1_clk.c | 3 --- include/arch/aarch32/arch.h | 4 ++++ include/arch/aarch64/arch.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 11fd6667..eb252872 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1516,9 +1516,6 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) } } -#define CNTCVL_OFF 0x008 -#define CNTCVU_OFF 0x00C - static void stm32mp1_stgen_config(void) { uintptr_t stgen; diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 44044d40..0db41458 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -81,6 +81,10 @@ * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF U(0x000) +/* Counter Count Value Lower register */ +#define CNTCVL_OFF U(0x008) +/* Counter Count Value Upper register */ +#define CNTCVU_OFF U(0x00C) #define CNTFID_OFF U(0x020) #define CNTCR_EN (U(1) << 0) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index d23d89e3..502b8681 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -99,6 +99,7 @@ * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF U(0x000) +#define CNTCV_OFF U(0x008) #define CNTFID_OFF U(0x020) #define CNTCR_EN (U(1) << 0) -- 2.30.2