From dce3b0057b986ab3278392607433b862e2865416 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 23 Mar 2017 09:18:42 +0100 Subject: [PATCH] ramips: fix mt7621 boot on v4.9 v4.9 CM code has a few bugs on this HW. Disable the GCR register access during boot. This caused a cpu stall. Signed-off-by: John Crispin --- .../ramips/patches-4.9/0098-disable_cm.patch | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 target/linux/ramips/patches-4.9/0098-disable_cm.patch diff --git a/target/linux/ramips/patches-4.9/0098-disable_cm.patch b/target/linux/ramips/patches-4.9/0098-disable_cm.patch new file mode 100644 index 00000000000..6ea4909851d --- /dev/null +++ b/target/linux/ramips/patches-4.9/0098-disable_cm.patch @@ -0,0 +1,21 @@ +Index: linux-4.9.14/arch/mips/kernel/mips-cm.c +=================================================================== +--- linux-4.9.14.orig/arch/mips/kernel/mips-cm.c ++++ linux-4.9.14/arch/mips/kernel/mips-cm.c +@@ -239,6 +239,7 @@ int mips_cm_probe(void) + + /* disable CM regions */ + write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); ++ /* + write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); +@@ -246,7 +247,7 @@ int mips_cm_probe(void) + write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); +- ++*/ + /* probe for an L2-only sync region */ + mips_cm_probe_l2sync(); + -- 2.30.2