From da9971d1b3bdb554d4a4ac948119f8b2616bbcce Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 26 Jun 2015 19:42:24 +0100 Subject: [PATCH] Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell Conflicts: include/configs/sun6i.h include/configs/sun8i.h --- arch/arm/cpu/armv7/sunxi/board.c | 14 +- arch/arm/include/asm/arch-sunxi/gpio.h | 2 - arch/arm/include/asm/arch-sunxi/nand.h | 67 ------ board/sunxi/Kconfig | 12 -- board/sunxi/board.c | 18 -- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/sunxi_nand_spl.c | 273 ------------------------- include/configs/sun4i.h | 1 - include/configs/sun5i.h | 3 - include/configs/sun6i.h | 2 - include/configs/sun7i.h | 2 - include/configs/sun8i.h | 2 - include/configs/sunxi-common.h | 20 -- 13 files changed, 2 insertions(+), 415 deletions(-) delete mode 100644 arch/arm/include/asm/arch-sunxi/nand.h delete mode 100644 drivers/mtd/nand/sunxi_nand_spl.c diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 8a4770b438..03443629bc 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -119,20 +119,11 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD /* The sunxi internal brom will try to loader external bootloader * from mmc0, nand flash, mmc2. - * - * Unfortunately we can't check how SPL was loaded so assume it's - * always the first SD/MMC controller, unless it was explicitly - * stated that SPL is on nand flash. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller */ u32 spl_boot_device(void) { -#if defined(CONFIG_SPL_NAND_SUPPORT) - /* - * This is compile time configuration informing SPL, that it - * was loaded from nand flash. - */ - return BOOT_DEVICE_NAND; -#else /* * When booting from the SD card, the "eGON.BT0" signature is expected * to be found in memory at the address 0x0004 (see the "mksunxiboot" @@ -153,7 +144,6 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; else return BOOT_DEVICE_BOARD; -#endif } /* No confirmation data available in SPL yet. Hardcode bootmode */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b628fee3ea..496295d357 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -157,8 +157,6 @@ enum sunxi_gpio_number { #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 -#define SUNXI_GPC_NAND 2 - #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/arch/arm/include/asm/arch-sunxi/nand.h b/arch/arm/include/asm/arch-sunxi/nand.h deleted file mode 100644 index 22844d84b8..0000000000 --- a/arch/arm/include/asm/arch-sunxi/nand.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2015 Roy Spliet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_NAND_H -#define _SUNXI_NAND_H - -#include - -struct sunxi_nand -{ - u32 ctl; /* 0x000 Configure and control */ - u32 st; /* 0x004 Status information */ - u32 intr; /* 0x008 Interrupt control */ - u32 timing_ctl; /* 0x00C Timing control */ - u32 timing_cfg; /* 0x010 Timing configure */ - u32 addr_low; /* 0x014 Low word address */ - u32 addr_high; /* 0x018 High word address */ - u32 block_num; /* 0x01C Data block number */ - u32 data_cnt; /* 0x020 Data counter for transfer */ - u32 cmd; /* 0x024 NDFC commands */ - u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */ - u32 wcmd_set; /* 0x02C Write command set */ - u32 io_data; /* 0x030 IO data */ - u32 ecc_ctl; /* 0x034 ECC configure and control */ - u32 ecc_st; /* 0x038 ECC status and operation info */ - u32 efr; /* 0x03C Enhanced feature */ - u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */ - u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */ - u32 user_data[16]; /* 0x050[16] User data field */ - u32 efnand_st; /* 0x090 EFNAND status */ - u32 res0[3]; - u32 spare_area; /* 0x0A0 Spare area configure */ - u32 pat_id; /* 0x0A4 Pattern ID register */ - u32 rdata_sta_ctl; /* 0x0A8 Read data status control */ - u32 rdata_sta_0; /* 0x0AC Read data status 0 */ - u32 rdata_sta_1; /* 0x0B0 Read data status 1 */ - u32 res1[3]; - u32 mdma_addr; /* 0x0C0 MBUS DMA Address */ - u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */ -}; - -#define SUNXI_NAND_CTL_EN (1 << 0) -#define SUNXI_NAND_CTL_RST (1 << 1) -#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8) -#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14) - -#define SUNXI_NAND_ST_CMD_INT (1 << 1) -#define SUNXI_NAND_ST_DMA_INT (1 << 2) -#define SUNXI_NAND_ST_FIFO_FULL (1 << 3) - -#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16); -#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22) -#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23) -#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0 -#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25) - -#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0) -#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3) -#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5) -#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9) -#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12) -#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16) - -#endif /* _SUNXI_NAND_H */ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index aa44f50b32..2a1cd3cf3b 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -280,18 +280,6 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config SPL_NAND_SUPPORT - bool "SPL/NAND mode support" - depends on SPL - default n - ---help--- - This enables support for booting from NAND internal - memory. U-Boot SPL doesn't detect where is it load from, - therefore this option is needed to properly load image from - flash. Option also disables MMC functionality on U-Boot due to - initialization errors encountered, when both controllers are - enabled. - config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default "" diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f27967bbf4..ed60e74808 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -22,9 +22,6 @@ #ifdef CONFIG_AXP221_POWER #include #endif -#ifdef CONFIG_NAND_SUNXI -#include -#endif #include #include #include @@ -318,21 +315,6 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_NAND -void board_nand_init(void) -{ - unsigned int pin; - static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS; - - /* Configure AHB muxes to connect output pins with NAND controller */ - for (pin = 0; pin < 16; pin++) - sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND); - - for (pin = 0; pin < ARRAY_SIZE(ports); pin++) - sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND); -} -#endif - void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index a0cf4d5fe4..347ea62e0b 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -73,6 +73,5 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o -obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o endif # drivers diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c deleted file mode 100644 index 75982f54cc..0000000000 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2014, Antmicro Ltd - * Copyright (c) 2015, Turtle Solutions - * Copyright (c) 2015, Roy Spliet - * - * SPDX-License-Identifier: GPL-2.0+ - * - * \todo Detect chip parameters (page size, ECC mode, randomisation...) - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void -nand_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE; - u32 val; - - board_nand_init(); - - /* "un-gate" NAND clock and clock source - * This assumes that the clock was already correctly configured by - * BootROM */ - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); -#ifdef CONFIG_MACH_SUN9I - setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); -#else - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); -#endif - setbits_le32(&ccm->nand0_clk_cfg, 0x80000000); - - val = readl(&nand->ctl); - val |= SUNXI_NAND_CTL_RST; - writel(val, &nand->ctl); - - /* Wait until reset pin is deasserted */ - do { - val = readl(&nand->ctl); - if (!(val & SUNXI_NAND_CTL_RST)) - break; - } while (1); - - /** \todo Chip select, currently kind of static */ - val = readl(&nand->ctl); - val &= 0xf0fff0f2; - val |= SUNXI_NAND_CTL_EN; - val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE); - writel(val, &nand->ctl); - - writel(0x100, &nand->timing_ctl); - writel(0x7ff, &nand->timing_cfg); - - /* reset CMD */ - val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG | - NAND_CMD_RESET; - writel(val, &nand->cmd); - do { - val = readl(&nand->st); - if (val & (1<<1)) - break; - udelay(1000); - } while (1); - - printf("Nand initialised\n"); -} - -int -nand_wait_timeout(u32 *reg, u32 mask, u32 val) -{ - unsigned long tmo = timer_get_us() + 1000000; /* 1s */ - - while ((readl(reg) & mask) != val) { - if (timer_get_us() > tmo) - return -ETIMEDOUT; - } - - return 0; -} - -/* random seed */ -static const uint16_t random_seed[128] = { - 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72, - 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436, - 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d, - 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130, - 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56, - 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55, - 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb, - 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17, - 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62, - 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064, - 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126, - 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e, - 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3, - 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b, - 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d, - 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db, -}; - -uint32_t ecc_errors = 0; - -static void -nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome) -{ - static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64}; - int i; - uint32_t ecc_mode; - u32 ecc; - u16 seed = 0; - - for (i = 0; i < ARRAY_SIZE(strength); i++) { - if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) { - ecc_mode = i; - break; - } - } - - if (i == ARRAY_SIZE(strength)) { - printf("ECC strength unsupported\n"); - return; - } - - ecc = SUNXI_NAND_ECC_CTL_ECC_EN | - SUNXI_NAND_ECC_CTL_PIPELINE | - SUNXI_NAND_ECC_CTL_RND_EN | - SUNXI_NAND_ECC_CTL_MODE(ecc_mode); - - if (CONFIG_NAND_SUNXI_ECC_STEP == 512) - ecc |= SUNXI_NAND_ECC_CTL_BS_512B; - - if (syndrome) - seed = 0x4A80; - else - seed = random_seed[page % ARRAY_SIZE(random_seed)]; - - ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed); - - writel(ecc, &nand->ecc_ctl); -} - -/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */ -void -nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst, - int syndrome) -{ - struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE; - struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0]; - - uint32_t shift; - uint32_t page; - uint32_t addr; - uint32_t oob_offset; - uint32_t ecc_bytes; - u32 val; - u32 cmd; - - page = src / CONFIG_NAND_SUNXI_PAGE_SIZE; - if (page > 0xFFFF) { - /* TODO: currently this is not supported */ - printf("Reading from address >= %08X is not allowed.\n", - 0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE); - return; - } - - shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE; - writel(0, &nand->ecc_st); - - /* ECC_CTL, randomization */ - ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH * - fls(CONFIG_NAND_SUNXI_ECC_STEP * 8); - ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8); - ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */ - ecc_bytes += 4; - - nand_config_ecc(nand, page, syndrome); - if (syndrome) { - /* shift every 1kB in syndrome */ - shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes; - oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift; - } else { - oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE + - (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes; - } - - addr = (page << 16) | shift; - - /* DMA */ - val = readl(&nand->ctl); - writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl); - - writel(oob_offset, &nand->spare_area); - - /* DMAC - * \todo Separate this into a tidy driver */ - writel(0x0, &dma->irq_en); /* clear dma interrupts */ - writel((uint32_t) &nand->io_data , &dma_cfg->src_addr); - writel(dst , &dma_cfg->dst_addr); - writel(0x00007F0F , &dma_cfg->ddma_para); - writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc); - - val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) | - SUNXI_DMA_CTL_MODE_IO | - SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 | - SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) | - SUNXI_DMA_CTL_DST_DATA_WIDTH_32 | - SUNXI_DMA_CTL_TRIGGER; - writel(val, &dma_cfg->ctl); - - writel(0x00E00530, &nand->rcmd_set); - nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0); - - writel(1 , &nand->block_num); - writel(addr, &nand->addr_low); - writel(0 , &nand->addr_high); - - /* CMD (PAGE READ) */ - cmd = 0x85E80000; - cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES); - cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ : - SUNXI_NAND_CMD_ORDER_INTERLEAVE); - writel(cmd, &nand->cmd); - - if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT, - SUNXI_NAND_ST_DMA_INT)) { - printf("NAND timeout reading data\n"); - return; - } - - if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) { - printf("NAND timeout reading data\n"); - return; - } - - if (readl(&nand->ecc_st)) - ecc_errors++; -} - -int -nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) -{ - struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE; - dma_addr_t dst_block; - dma_addr_t dst_end; - phys_addr_t addr = offs; - - dst_end = ((dma_addr_t) dest) + size; - - memset((void *)dest, 0x0, size); - ecc_errors = 0; - for (dst_block = (dma_addr_t) dest; dst_block < dst_end; - dst_block += CONFIG_NAND_SUNXI_ECC_STEP, - addr += CONFIG_NAND_SUNXI_ECC_STEP) { - /* syndrome read first 4MiB to match Allwinner BootROM */ - nand_read_block(nand, addr, dst_block, addr < 0x400000); - } - - if (ecc_errors) - printf("Error: %d ECC failures detected\n", ecc_errors); - return ecc_errors == 0; -} - -void -nand_deselect(void) -{} diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index a3c9408518..ea079eb5f7 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -18,7 +18,6 @@ #endif #define CONFIG_SUNXI_USB_PHYS 3 -#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24} /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 8e13df58bd..d257659903 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -19,9 +19,6 @@ #define CONFIG_SUNXI_USB_PHYS 2 -/* \todo A13 only defines port 19, whereas A10s requires each of these */ -#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19} - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index a0ebc7e977..93863b59bc 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -27,8 +27,6 @@ #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_TIMER_CLK_FREQ 24000000 -#define CONFIG_NAND_SUNXI_GPC_PORTS {24, 25, 26} - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 3d26ce8d4a..56101a9ffc 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -24,8 +24,6 @@ #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_TIMER_CLK_FREQ 24000000 -#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24} - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index fe8c511448..4fc6365008 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -23,10 +23,8 @@ #define CONFIG_ARMV7_PSCI 1 #if defined(CONFIG_MACH_SUN8I_A23) #define CONFIG_ARMV7_PSCI_NR_CPUS 2 -#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18} #elif defined(CONFIG_MACH_SUN8I_A33) #define CONFIG_ARMV7_PSCI_NR_CPUS 4 -#define CONFIG_NAND_SUNXI_GPC_PORTS {16} #else #error Unsupported sun8i variant #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index aed040b0eb..9576bc1a20 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -146,10 +146,8 @@ #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI #define CONFIG_MMC_SUNXI_SLOT 0 -#if !defined(CONFIG_SPL_NAND_SUPPORT) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ -#endif /* CONFIG_SPL_NAND_SUPPORT */ #endif /* 4MB of malloc() pool */ @@ -351,24 +349,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_NAND -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_NAND_SUNXI -#define CONFIG_CMD_SPL_WRITE_SIZE 0x000400 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x008000 - -/* \todo Make these parameterisable in kernel config ? */ -#define CONFIG_NAND_SUNXI_PAGE_SIZE 8192 -#define CONFIG_NAND_SUNXI_ECC_STEP 1024 -#define CONFIG_NAND_SUNXI_ECC_STRENGTH 40 -#define CONFIG_NAND_SUNXI_ADDR_CYCLES 5 - -#ifndef CONFIG_NAND_SUNXI_GPC_PORTS -#error "No NAND GPC ports defined, NAND unsupported" -#endif -#endif /* CONFIG_SPL_NAND_SUPPORT */ - #define CONFIG_MISC_INIT_R #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- 2.30.2