From d8d5fdb7b2ab9154beee2936082bfb65bf4d9209 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Tue, 26 Feb 2019 13:18:32 +0200 Subject: [PATCH] fsl_sec: fix register layout on Layerscape architectures On Layerscape architectures the SEC memory map is 1MB and the register blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure currently assumes. Fix the layout of the structure for these architectures. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Reviewed-by: Bharat Bhushan Reviewed-by: Prabhakar Kushwaha --- include/fsl_sec.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 16e3fcb5a1..be08a2b88b 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -121,10 +121,18 @@ typedef struct ccsr_sec { u32 chanum_ls; /* CHA Number Register, LS */ u32 secvid_ms; /* SEC Version ID Register, MS */ u32 secvid_ls; /* SEC Version ID Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res9[0x6f020]; +#else u8 res9[0x6020]; +#endif u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res10[0x8ffd8]; +#else u8 res10[0x8fd8]; +#endif } ccsr_sec_t; #define SEC_CTPR_MS_AXI_LIODN 0x08000000 -- 2.30.2