From d19f3187147ac29dd68b41e3a89c120c0e5fa2d0 Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Fri, 18 Feb 2011 09:25:59 +0000 Subject: [PATCH] [toolchain/gcc/4.3.5]: combine all avr32 patches into a single one SVN-Revision: 25566 --- .../gcc/patches/4.3.5/930-avr32_support.patch | 100 +++++++++++++----- .../4.3.5/939-avr32_fix_linux_build.patch | 25 ----- .../4.3.5/940-avr32_fix_f32_to_f64.patch | 10 -- .../patches/4.3.5/941-avr32_fix_f64_add.patch | 10 -- .../4.3.5/942-avr32_fix_32bit_div.patch | 34 ------ .../patches/4.3.5/943-avr32_fix_f64_cmp.patch | 66 ------------ .../patches/4.3.5/944-avr32_fix_f64_div.patch | 20 ---- .../4.3.5/945-avr32_fix_f64_to_f32.patch | 11 -- .../4.3.5/946-avr32_fix_32bit_div_2.patch | 27 ----- .../948-avr32_fix_reorg_opt_bug11763.patch | 32 ------ .../4.3.5/949-avr32_nan_by_zero_div.patch | 15 --- 11 files changed, 72 insertions(+), 278 deletions(-) delete mode 100644 toolchain/gcc/patches/4.3.5/939-avr32_fix_linux_build.patch delete mode 100644 toolchain/gcc/patches/4.3.5/940-avr32_fix_f32_to_f64.patch delete mode 100644 toolchain/gcc/patches/4.3.5/941-avr32_fix_f64_add.patch delete mode 100644 toolchain/gcc/patches/4.3.5/942-avr32_fix_32bit_div.patch delete mode 100644 toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch delete mode 100644 toolchain/gcc/patches/4.3.5/944-avr32_fix_f64_div.patch delete mode 100644 toolchain/gcc/patches/4.3.5/945-avr32_fix_f64_to_f32.patch delete mode 100644 toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch delete mode 100644 toolchain/gcc/patches/4.3.5/948-avr32_fix_reorg_opt_bug11763.patch delete mode 100644 toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch diff --git a/toolchain/gcc/patches/4.3.5/930-avr32_support.patch b/toolchain/gcc/patches/4.3.5/930-avr32_support.patch index 29d749f7aa..0613f3fea7 100644 --- a/toolchain/gcc/patches/4.3.5/930-avr32_support.patch +++ b/toolchain/gcc/patches/4.3.5/930-avr32_support.patch @@ -22,7 +22,7 @@ must do it earlier where we know the signedness of the arg. */ --- /dev/null +++ b/gcc/config/avr32/avr32.c -@@ -0,0 +1,7858 @@ +@@ -0,0 +1,7869 @@ +/* + Target hooks and helper functions for AVR32. + Copyright 2003-2006 Atmel Corporation. @@ -6526,12 +6526,23 @@ + continue; + + set = single_set (scan); -+ if (set && rtx_equal_p (src_reg, SET_DEST (set))) -+ { -+ link = scan; -+ break; -+ } -+ ++ // Fix for bug #11763 : the following if condition ++ // has been modified and else part is included to ++ // set the link to NULL_RTX. ++ // if (set && rtx_equal_p (src_reg, SET_DEST (set))) ++ if (set && (REGNO(src_reg) == REGNO(SET_DEST(set)))) ++ { ++ if (rtx_equal_p (src_reg, SET_DEST (set))) ++ { ++ link = scan; ++ break; ++ } ++ else ++ { ++ link = NULL_RTX; ++ break; ++ } ++ } + } + + @@ -17204,7 +17215,7 @@ + (set_attr "cc" "none")]) --- /dev/null +++ b/gcc/config/avr32/lib1funcs.S -@@ -0,0 +1,2874 @@ +@@ -0,0 +1,2902 @@ +/* Macro for moving immediate value to register. */ +.macro mov_imm reg, imm +.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm)) @@ -18243,6 +18254,7 @@ + brne __avr32_f64_add_return_nan + mov r10, 0 /* Generate Inf in r11, r10 */ + mov_imm r11, 0x7ff00000 ++ or r11, r12 /* Put sign bit back */ + ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */ +__avr32_f64_add_return_nan: + mov r10, -1 /* Generate NaN in r11, r10 */ @@ -18595,25 +18607,30 @@ +#endif + + /* compare magnitude of op1 and op2 */ ++ st.w --sp, lr ++ st.w --sp, r7 + lsl r11,1 /* Remove sign bit of op1 */ + srcs r12 /* Sign op1 to lsb of r12*/ -+ subfeq r10, 0 -+ breq 3f /* op1 zero */ + lsl r9,1 /* Remove sign bit of op2 */ ++ srcs r7 + rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/ + + + /* Check for Nan */ -+ pushm lr -+ mov_imm lr, 0xffe00000 ++ mov_imm lr, 0xffe00000 + cp.w r10,0 + cpc r11,lr + brhi 0f /* We have NaN */ + cp.w r8,0 + cpc r9,lr + brhi 0f /* We have NaN */ -+ popm lr -+ ++ ++ cp.w r11, 0 ++ subfeq r10, 0 ++ breq 3f /* op1 zero */ ++ ld.w r7, sp++ ++ ld.w lr, sp++ ++ + cp.w r12,3 /* both operands negative ?*/ + breq 1f + @@ -18659,18 +18676,22 @@ +#endif + +0: ++ ld.w r7, sp++ + popm pc, r12=0 +#endif + +3: -+ lsl r9,1 /* Remove sign bit of op1 */ ++ cp.w r7, 1 /* Check sign bit from r9 */ +#ifdef L_avr32_f64_cmp_ge -+ srcs r12 /* If op2 is negative then op1 >= op2. */ ++ sreq r12 /* If op2 is negative then op1 >= op2. */ +#endif +#ifdef L_avr32_f64_cmp_lt -+ srcc r12 /* If op2 is positve then op1 <= op2. */ ++ srne r12 /* If op2 is positve then op1 <= op2. */ +#endif -+ subfeq r8, 0 ++ cp.w r9, 0 ++ subfeq r8, 0 ++ ld.w r7, sp++ ++ ld.w lr, sp++ +#ifdef L_avr32_f64_cmp_ge + reteq 1 /* Both operands are zero. Return true. */ +#endif @@ -18930,7 +18951,7 @@ + brne 16f /* Return NaN if op1 is NaN */ + /* Op1 is inf check op2 */ + lsr r6, r9, 20 /* Extract exponent */ -+ cbr r6, 8 /* Clear sign bit */ ++ cbr r6, 11 /* Clear sign bit */ + cp r6, 0x7ff + brne 17f /* Inf/number gives inf, return inf */ + rjmp 16f /* The rest gives NaN*/ @@ -19046,10 +19067,14 @@ + +16: /* Return NaN. */ + mov r11, -1 -+ mov r10, -1 ++ mov r10, 0 + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc + -+17: /* Return INF. */ ++17: ++ /* Check if op1 is zero. */ ++ or r4, r10, r11 ++ breq __avr32_f64_div_op1_zero ++ /* Return INF. */ + mov r11, lr /*Get correct sign*/ + andh r11, 0x8000, COH + orh r11, 0x7ff0 @@ -19463,10 +19488,13 @@ + + /* Unpack */ + lsl r12,1 -+ reteq 0 /* Return zero if op1 is zero */ + lsl r11,1 + breq 4f /* Check op2 for zero */ -+ ++ ++ tst r12, r12 ++ moveq r9, 0 ++ breq 12f ++ + /* Unpack op1*/ + /* exp: r9 */ + /* sf: r12 */ @@ -19485,9 +19513,14 @@ + breq 13f /*If number is subnormal*/ + cp r10, 0xff + brhs 3f /* Check op2 for NaN or Inf */ -+ + lsl r11,7 + sbr r11, 31 /*Implicit bit*/ ++ ++ cp.w r9, 0 ++ subfeq r12, 0 ++ reteq 0 /* op1 is zero and op2 is not zero */ ++ /* or NaN so return zero */ ++ +14: + + /* For UC3, store with predecrement is faster than stm */ @@ -19656,9 +19689,14 @@ + reteq 0 /* Return zero if number/inf*/ + ret -1 /* Return NaN*/ +4: -+ /* Op2 is zero ? */ ++ /* Op1 is zero ? */ + tst r12,r12 + reteq -1 /* 0.0/0.0 is NaN */ ++ /* Op1 is Nan? */ ++ lsr r9, r12, 24 ++ breq 11f /*If number is subnormal*/ ++ cp r9, 0xff ++ brhs 2b /* Check op1 for NaN or Inf */ + /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/ + mov_imm r12, 0xff000000 + rjmp __divsf_return_op1 @@ -20007,6 +20045,7 @@ + lsl r11,8 /* check mantissa */ + movne r11, -1 /* Return NaN */ + moveq r11, r10 /* Return inf */ ++ mov r10, 0 + rjmp __extendsfdf_return_op1 +#endif + @@ -20054,7 +20093,7 @@ + /* NaN or inf */ + cbr r12,31 /* clear implicit bit */ + retne -1 /* Return NaN if mantissa not zero */ -+ mov_imm r12, 0xff000000 ++ mov_imm r12, 0x7f800000 + ret r12 /* Return inf */ + +3: /* Result is subnormal. Adjust it.*/ @@ -21297,7 +21336,7 @@ ;; +avr32*-*-linux*) + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h " -+ tmake_file="t-linux avr32/t-avr32 avr32/t-elf" ++ tmake_file="t-linux avr32/t-avr32-linux" + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" + extra_modes=avr32/avr32-modes.def + gnu_ld=yes @@ -22294,10 +22333,15 @@ // different sentry variables for construction and destruction. --- a/libgcc/config.host +++ b/libgcc/config.host -@@ -240,6 +240,8 @@ arm-*-pe*) +@@ -240,6 +240,13 @@ arm-*-pe*) ;; arm*-*-kaos*) ;; ++avr32-*-linux*) ++ # No need to build crtbeginT.o on uClibc systems. Should probably be ++ # moved to the OS specific section above. ++ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" ++ ;; +avr32-*-*) + ;; avr-*-rtems*) diff --git a/toolchain/gcc/patches/4.3.5/939-avr32_fix_linux_build.patch b/toolchain/gcc/patches/4.3.5/939-avr32_fix_linux_build.patch deleted file mode 100644 index 1569592360..0000000000 --- a/toolchain/gcc/patches/4.3.5/939-avr32_fix_linux_build.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -836,7 +836,7 @@ avr-*-*) - ;; - avr32*-*-linux*) - tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h " -- tmake_file="t-linux avr32/t-avr32 avr32/t-elf" -+ tmake_file="t-linux avr32/t-avr32-linux" - extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" - extra_modes=avr32/avr32-modes.def - gnu_ld=yes ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -240,6 +240,11 @@ arm-*-pe*) - ;; - arm*-*-kaos*) - ;; -+avr32-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably be -+ # moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - avr32-*-*) - ;; - avr-*-rtems*) diff --git a/toolchain/gcc/patches/4.3.5/940-avr32_fix_f32_to_f64.patch b/toolchain/gcc/patches/4.3.5/940-avr32_fix_f32_to_f64.patch deleted file mode 100644 index b19f84e29d..0000000000 --- a/toolchain/gcc/patches/4.3.5/940-avr32_fix_f32_to_f64.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -2800,6 +2800,7 @@ __extendsfdf_return_op1: - lsl r11,8 /* check mantissa */ - movne r11, -1 /* Return NaN */ - moveq r11, r10 /* Return inf */ -+ mov r10, 0 - rjmp __extendsfdf_return_op1 - #endif - diff --git a/toolchain/gcc/patches/4.3.5/941-avr32_fix_f64_add.patch b/toolchain/gcc/patches/4.3.5/941-avr32_fix_f64_add.patch deleted file mode 100644 index b3322cb946..0000000000 --- a/toolchain/gcc/patches/4.3.5/941-avr32_fix_f64_add.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -1036,6 +1036,7 @@ __avr32_f64_add_opL_nan_or_inf: - brne __avr32_f64_add_return_nan - mov r10, 0 /* Generate Inf in r11, r10 */ - mov_imm r11, 0x7ff00000 -+ or r11, r12 /* Put sign bit back */ - ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */ - __avr32_f64_add_return_nan: - mov r10, -1 /* Generate NaN in r11, r10 */ diff --git a/toolchain/gcc/patches/4.3.5/942-avr32_fix_32bit_div.patch b/toolchain/gcc/patches/4.3.5/942-avr32_fix_32bit_div.patch deleted file mode 100644 index af66a6d500..0000000000 --- a/toolchain/gcc/patches/4.3.5/942-avr32_fix_32bit_div.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -2257,10 +2257,13 @@ __avr32_f32_div: - - /* Unpack */ - lsl r12,1 -- reteq 0 /* Return zero if op1 is zero */ - lsl r11,1 - breq 4f /* Check op2 for zero */ -- -+ -+ tst r12, r12 -+ moveq r9, 0 -+ breq 12 -+ - /* Unpack op1*/ - /* exp: r9 */ - /* sf: r12 */ -@@ -2279,9 +2282,14 @@ __avr32_f32_div: - breq 13f /*If number is subnormal*/ - cp r10, 0xff - brhs 3f /* Check op2 for NaN or Inf */ -- - lsl r11,7 - sbr r11, 31 /*Implicit bit*/ -+ -+ cp.w r9, 0 -+ subfeq r12, 0 -+ reteq 0 /* op1 is zero and op2 is not zero */ -+ /* or NaN so return zero */ -+ - 14: - - /* For UC3, store with predecrement is faster than stm */ diff --git a/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch b/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch deleted file mode 100644 index b5d526c2a6..0000000000 --- a/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch +++ /dev/null @@ -1,66 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -1389,25 +1389,30 @@ __avr32_f64_cmp_lt: - #endif - - /* compare magnitude of op1 and op2 */ -+ st.w --sp, lr -+ st.w --sp, r7 - lsl r11,1 /* Remove sign bit of op1 */ - srcs r12 /* Sign op1 to lsb of r12*/ -- subfeq r10, 0 -- breq 3f /* op1 zero */ - lsl r9,1 /* Remove sign bit of op2 */ -+ srcs r7 - rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/ - - - /* Check for Nan */ -- pushm lr -- mov_imm lr, 0xffe00000 -+ mov_imm lr, 0xffe00000 - cp.w r10,0 - cpc r11,lr - brhi 0f /* We have NaN */ - cp.w r8,0 - cpc r9,lr - brhi 0f /* We have NaN */ -- popm lr -- -+ -+ cp.w r11, 0 -+ subfeq r10, 0 -+ breq 3f /* op1 zero */ -+ ld.w r7, sp++ -+ ld.w lr, sp++ -+ - cp.w r12,3 /* both operands negative ?*/ - breq 1f - -@@ -1453,18 +1458,22 @@ __avr32_f64_cmp_lt: - #endif - - 0: -+ ld.w r7, sp++ - popm pc, r12=0 - #endif - - 3: -- lsl r9,1 /* Remove sign bit of op1 */ -+ cp.w r7, 1 /* Check sign bit from r9 */ - #ifdef L_avr32_f64_cmp_ge -- srcs r12 /* If op2 is negative then op1 >= op2. */ -+ sreq r12 /* If op2 is negative then op1 >= op2. */ - #endif - #ifdef L_avr32_f64_cmp_lt -- srcc r12 /* If op2 is positve then op1 <= op2. */ -+ srne r12 /* If op2 is positve then op1 <= op2. */ - #endif -- subfeq r8, 0 -+ cp.w r9, 0 -+ subfeq r8, 0 -+ ld.w r7, sp++ -+ ld.w lr, sp++ - #ifdef L_avr32_f64_cmp_ge - reteq 1 /* Both operands are zero. Return true. */ - #endif diff --git a/toolchain/gcc/patches/4.3.5/944-avr32_fix_f64_div.patch b/toolchain/gcc/patches/4.3.5/944-avr32_fix_f64_div.patch deleted file mode 100644 index 24a973f687..0000000000 --- a/toolchain/gcc/patches/4.3.5/944-avr32_fix_f64_div.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -1733,7 +1733,7 @@ __avr32_f64_div_round_subnormal: - brne 16f /* Return NaN if op1 is NaN */ - /* Op1 is inf check op2 */ - lsr r6, r9, 20 /* Extract exponent */ -- cbr r6, 8 /* Clear sign bit */ -+ cbr r6, 11 /* Clear sign bit */ - cp r6, 0x7ff - brne 17f /* Inf/number gives inf, return inf */ - rjmp 16f /* The rest gives NaN*/ -@@ -1849,7 +1849,7 @@ __avr32_f64_div_res_subnormal:/* Divide - - 16: /* Return NaN. */ - mov r11, -1 -- mov r10, -1 -+ mov r10, 0 - ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc - - 17: /* Return INF. */ diff --git a/toolchain/gcc/patches/4.3.5/945-avr32_fix_f64_to_f32.patch b/toolchain/gcc/patches/4.3.5/945-avr32_fix_f64_to_f32.patch deleted file mode 100644 index 3d22b3924b..0000000000 --- a/toolchain/gcc/patches/4.3.5/945-avr32_fix_f64_to_f32.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -2866,7 +2866,7 @@ __truncdfsf_return_op1: - /* NaN or inf */ - cbr r12,31 /* clear implicit bit */ - retne -1 /* Return NaN if mantissa not zero */ -- mov_imm r12, 0xff000000 -+ mov_imm r12, 0x7f800000 - ret r12 /* Return inf */ - - 3: /* Result is subnormal. Adjust it.*/ diff --git a/toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch b/toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch deleted file mode 100644 index 3f2bfb35c3..0000000000 --- a/toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -2271,7 +2271,7 @@ __avr32_f32_div: - - tst r12, r12 - moveq r9, 0 -- breq 12 -+ breq 12f - - /* Unpack op1*/ - /* exp: r9 */ -@@ -2467,9 +2467,14 @@ __divsf_return_op1: - reteq 0 /* Return zero if number/inf*/ - ret -1 /* Return NaN*/ - 4: -- /* Op2 is zero ? */ -+ /* Op1 is zero ? */ - tst r12,r12 - reteq -1 /* 0.0/0.0 is NaN */ -+ /* Op1 is Nan? */ -+ lsr r9, r12, 24 -+ breq 11f /*If number is subnormal*/ -+ cp r9, 0xff -+ brhs 2b /* Check op1 for NaN or Inf */ - /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/ - mov_imm r12, 0xff000000 - rjmp __divsf_return_op1 diff --git a/toolchain/gcc/patches/4.3.5/948-avr32_fix_reorg_opt_bug11763.patch b/toolchain/gcc/patches/4.3.5/948-avr32_fix_reorg_opt_bug11763.patch deleted file mode 100644 index 6616640045..0000000000 --- a/toolchain/gcc/patches/4.3.5/948-avr32_fix_reorg_opt_bug11763.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/gcc/config/avr32/avr32.c -+++ b/gcc/config/avr32/avr32.c -@@ -6501,12 +6501,23 @@ avr32_reorg_optimization (void) - continue; - - set = single_set (scan); -- if (set && rtx_equal_p (src_reg, SET_DEST (set))) -- { -- link = scan; -- break; -- } -- -+ // Fix for bug #11763 : the following if condition -+ // has been modified and else part is included to -+ // set the link to NULL_RTX. -+ // if (set && rtx_equal_p (src_reg, SET_DEST (set))) -+ if (set && (REGNO(src_reg) == REGNO(SET_DEST(set)))) -+ { -+ if (rtx_equal_p (src_reg, SET_DEST (set))) -+ { -+ link = scan; -+ break; -+ } -+ else -+ { -+ link = NULL_RTX; -+ break; -+ } -+ } - } - - diff --git a/toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch b/toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch deleted file mode 100644 index c5f880668a..0000000000 --- a/toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/gcc/config/avr32/lib1funcs.S -+++ b/gcc/config/avr32/lib1funcs.S -@@ -1852,7 +1852,11 @@ __avr32_f64_div_res_subnormal:/* Divide - mov r10, 0 - ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc - --17: /* Return INF. */ -+17: -+ /* Check if op1 is zero. */ -+ or r4, r10, r11 -+ breq __avr32_f64_div_op1_zero -+ /* Return INF. */ - mov r11, lr /*Get correct sign*/ - andh r11, 0x8000, COH - orh r11, 0x7ff0 -- 2.30.2