From cd6cfd7311a385144a2f9c74f692ae2df3ae033f Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 22 Feb 2014 14:52:48 +0100 Subject: [PATCH] ath9k: do not set half/quarter channel flags in AR_PHY_MODE 5/10 MHz channel bandwidth is configured via the PLL clock, instead of the AR_PHY_MODE register. Using that register is AR93xx specific, and makes the mode incompatible with earlier chipsets. In some early versions, these flags were apparently applied at the wrong point in time and thus did not cause connectivity issues, however now they are causing problems, as pointed out in this OpenWrt ticket: https://dev.openwrt.org/ticket/14916 Signed-off-by: Felix Fietkau Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath9k/ar9003_phy.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 09facba1dc6d..8927fc34d84c 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c @@ -868,10 +868,6 @@ static void ar9003_hw_set_rfmode(struct ath_hw *ah, if (IS_CHAN_A_FAST_CLOCK(ah, chan)) rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); - if (IS_CHAN_QUARTER_RATE(chan)) - rfMode |= AR_PHY_MODE_QUARTER; - if (IS_CHAN_HALF_RATE(chan)) - rfMode |= AR_PHY_MODE_HALF; if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF)) REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, -- 2.30.2