From cd2c68501c2444566a157f2a1bfecff65c49fdcb Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 29 Aug 2011 21:23:46 +0000 Subject: [PATCH] ar71xx: fix ethernet PLL setting on ar7242 SVN-Revision: 28124 --- target/linux/ar71xx/files/arch/mips/ar71xx/devices.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c index 74d9495c30b7..4c901681cad4 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c @@ -265,9 +265,11 @@ static void ar724x_set_pll_ge1(int speed) static void ar7242_set_pll_ge0(int speed) { u32 val = ar71xx_get_eth_pll(0, speed); + void __iomem *base; - ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK, - val, AR71XX_ETH0_PLL_SHIFT); + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK); + iounmap(base); } static void ar91xx_set_pll_ge0(int speed) @@ -410,7 +412,7 @@ struct platform_device ar71xx_eth1_device = { #define AR724X_PLL_VAL_100 0x00001099 #define AR724X_PLL_VAL_10 0x00991099 -#define AR7242_PLL_VAL_1000 0x1c000000 +#define AR7242_PLL_VAL_1000 0x16000000 #define AR7242_PLL_VAL_100 0x00000101 #define AR7242_PLL_VAL_10 0x00001616 -- 2.30.2