From cc9df2da0dcbc6bd0b7d91b7bdc6a02456e75119 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Tue, 4 Jun 2024 19:22:45 +0100 Subject: [PATCH] rockchip: add NanoPi R6S support Add patches for the nanopi r6s board, backporting from 6.9 where basic support is landing. Signed-off-by: Ben Whitten Link: https://github.com/openwrt/openwrt/pull/15607 Signed-off-by: Hauke Mehrtens --- target/linux/rockchip/armv8/config-6.6 | 14 + target/linux/rockchip/image/armv8.mk | 8 + .../linux/rockchip/image/default.bootscript | 2 + ...-rockchip-Add-support-for-NanoPi-R6S.patch | 792 ++++++++++++++++++ ...ve-rk3588-serial-aliases-to-soc-dtsi.patch | 129 +++ ...p-add-rk3588-i2c-aliases-to-soc-dtsi.patch | 38 + ...-add-rk3588-gpio-aliases-to-soc-dtsi.patch | 34 + ...p-add-rk3588-spi-aliases-to-soc-dtsi.patch | 34 + ...probe-to-defer-if-clock-is-not-ready.patch | 25 + 9 files changed, 1076 insertions(+) create mode 100644 target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch create mode 100644 target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch create mode 100644 target/linux/rockchip/patches-6.6/302-mmc-allow-probe-to-defer-if-clock-is-not-ready.patch diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 index fb57fc6260..be87f7e52c 100644 --- a/target/linux/rockchip/armv8/config-6.6 +++ b/target/linux/rockchip/armv8/config-6.6 @@ -24,11 +24,20 @@ CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y CONFIG_ARM64_CNP=y CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1530923=y CONFIG_ARM64_ERRATUM_2051678=y CONFIG_ARM64_ERRATUM_2054223=y CONFIG_ARM64_ERRATUM_2067961=y CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2441007=y +CONFIG_ARM64_ERRATUM_2441009=y CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_3117295=y CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_826319=y @@ -52,6 +61,9 @@ CONFIG_ARM64_VA_BITS=48 # CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y @@ -163,6 +175,7 @@ CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_ISOLATION=y CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y @@ -567,6 +580,7 @@ CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y CONFIG_RFS_ACCEL=y +CONFIG_ROCKCHIP_ERRATUM_3588001=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ROCKCHIP_IOMMU=y diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index c92a8ba4f7..efae3285b3 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -81,6 +81,14 @@ define Device/friendlyarm_nanopi-r5s endef TARGET_DEVICES += friendlyarm_nanopi-r5s +define Device/friendlyarm_nanopi-r6s + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R6S + SOC := rk3588s + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += friendlyarm_nanopi-r6s + define Device/pine64_rock64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := Rock64 diff --git a/target/linux/rockchip/image/default.bootscript b/target/linux/rockchip/image/default.bootscript index cca0b8d4ac..10ca93ceda 100644 --- a/target/linux/rockchip/image/default.bootscript +++ b/target/linux/rockchip/image/default.bootscript @@ -2,6 +2,8 @@ part uuid ${devtype} ${devnum}:2 uuid if test $stdout = 'serial@fe660000' ; then serial_addr=',0xfe660000'; +elif test $stdout = 'serial@feb50000' ; +then serial_addr=',0xfeb50000'; elif test $stdout = 'serial@ff130000' ; then serial_addr=',0xff130000'; elif test $stdout = 'serial@ff1a0000' ; diff --git a/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch new file mode 100644 index 0000000000..e5afbb4f40 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch @@ -0,0 +1,792 @@ +From f1b11f43b3e983b26d8010fc43ba6c2b979826f2 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Sat, 30 Dec 2023 14:18:00 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6S + +Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC +support. + +Signed-off-by: Muhammed Efe Cetin +Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++++++++++++++ + 2 files changed, 765 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -104,4 +104,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts +@@ -0,0 +1,764 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R6S"; ++ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdmmc; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-maskrom { ++ label = "Maskrom"; ++ linux,code = ; ++ press-threshold-microvolt = <1800>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key1_pin>; ++ ++ button-user { ++ label = "User"; ++ linux,code = ; ++ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ sys_led: led-0 { ++ label = "sys_led"; ++ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sys_led_pin>; ++ }; ++ ++ wan_led: led-1 { ++ label = "wan_led"; ++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wan_led_pin>; ++ }; ++ ++ lan1_led: led-2 { ++ label = "lan1_led"; ++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>; ++ }; ++ ++ lan2_led: led-3 { ++ label = "lan2_led"; ++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan2_led_pin>; ++ }; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_3v3_s0: vcc-3v3-s0-regulator { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s0"; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sd_s0_pwr>; ++ regulator-name = "vcc_3v3_sd_s0"; ++ regulator-boot-on; ++ regulator-max-microvolt = <3000000>; ++ regulator-min-microvolt = <3000000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_pcie20"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ regulator-name = "vcc5v0_usb_otg0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_host_20: vcc5v0-host-20-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host20_en>; ++ regulator-name = "vcc5v0_host_20"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gmac1 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-rxid"; ++ pinctrl-0 = <&gmac1_miim ++ &gmac1_tx_bus2 ++ &gmac1_rx_bus2 ++ &gmac1_rgmii_clk ++ &gmac1_rgmii_bus>; ++ pinctrl-names = "default"; ++ tx_delay = <0x42>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ clock-frequency = <200000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8211f_rst>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1l1 { ++ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc_3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-key { ++ key1_pin: key1-pin { ++ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = ++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = ++ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = ++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = ++ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ rtc_int: rtc-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdmmc { ++ sd_s0_pwr: sd-s0-pwr { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_host20_en: vcc5v0-host20-en { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rtl8211f { ++ rtl8211f_rst: rtl8211f-rst { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ no-mmc; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_sd_s0>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ avcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "avcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ avdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "avdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ avdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "avdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vcc5v0_host_20>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..88919893a3 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-v6.8-arm64-dts-rockchip-move-rk3588-serial-aliases-to-soc-dtsi.patch @@ -0,0 +1,129 @@ +From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:39 +0100 +Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi + +The serial ports on rk3588 are named uart0 - uart9. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. + +To prevent each board repeating their list of serial aliases, move them +to the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de +--- + .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ---- + .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ---- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 - + .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 -- + .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 - + .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 - + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++ + 13 files changed, 13 insertions(+), 19 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6a-io", + "edgeble,neural-compute-module-6a", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts +@@ -12,10 +12,6 @@ + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + +- aliases { +- serial2 = &uart2; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -16,7 +16,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts +@@ -19,7 +19,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +@@ -15,7 +15,6 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +@@ -12,7 +12,6 @@ + + aliases { + mmc0 = &sdhci; +- serial2 = &uart2; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -14,7 +14,6 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; +- serial2 = &uart2; + }; + + analog-sound { +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -18,6 +18,19 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..2daaec3953 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/033-v6.8-arm64-dts-rockchip-add-rk3588-i2c-aliases-to-soc-dtsi.patch @@ -0,0 +1,38 @@ +From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:40 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi + +The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace i2c access is a thing afterall. + +To prevent each board repeating their list of i2c aliases, define them +in the soc dtsi, as all previous Rockchip soc do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,15 @@ + #size-cells = <2>; + + aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c7 = &i2c7; ++ i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; diff --git a/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..19e6c6a4f5 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/034-v6.8-arm64-dts-rockchip-add-rk3588-gpio-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:41 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi + +The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace gpio access is a thing afterall. + +To prevent each board repeating their list of gpio aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -19,6 +19,11 @@ + #size-cells = <2>; + + aliases { ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ gpio2 = &gpio2; ++ gpio3 = &gpio3; ++ gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; diff --git a/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch b/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch new file mode 100644 index 0000000000..6a66d99668 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/035-v6.8-arm64-dts-rockchip-add-rk3588-spi-aliases-to-soc-dtsi.patch @@ -0,0 +1,34 @@ +From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 5 Dec 2023 17:48:42 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi + +The spi controllers on rk3588 are named spi0 - spi4. Board schematics +also use these exact numbers and we want those names to also reflect +in the OS devices because everything else would just cause confusion. +Userspace spi access is a thing afterall. + +To prevent each board repeating their list of spi aliases, define them +in the soc dtsi, as previous Rockchip soc like the rk356x do already. + +Signed-off-by: Heiko Stuebner +Reviewed-by: Dragan Simic +Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -43,6 +43,11 @@ + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; + }; + + cpus { diff --git a/target/linux/rockchip/patches-6.6/302-mmc-allow-probe-to-defer-if-clock-is-not-ready.patch b/target/linux/rockchip/patches-6.6/302-mmc-allow-probe-to-defer-if-clock-is-not-ready.patch new file mode 100644 index 0000000000..468cc3a307 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/302-mmc-allow-probe-to-defer-if-clock-is-not-ready.patch @@ -0,0 +1,25 @@ +--- a/drivers/mmc/host/dw_mmc.c ++++ b/drivers/mmc/host/dw_mmc.c +@@ -3294,6 +3294,10 @@ int dw_mci_probe(struct dw_mci *host) + host->biu_clk = devm_clk_get(host->dev, "biu"); + if (IS_ERR(host->biu_clk)) { + dev_dbg(host->dev, "biu clock not available\n"); ++ ret = PTR_ERR(host->biu_clk); ++ if (ret == -EPROBE_DEFER) { ++ return ret; ++ } + } else { + ret = clk_prepare_enable(host->biu_clk); + if (ret) { +@@ -3305,6 +3309,11 @@ int dw_mci_probe(struct dw_mci *host) + host->ciu_clk = devm_clk_get(host->dev, "ciu"); + if (IS_ERR(host->ciu_clk)) { + dev_dbg(host->dev, "ciu clock not available\n"); ++ ret = PTR_ERR(host->ciu_clk); ++ if (ret == -EPROBE_DEFER) { ++ goto err_clk_biu; ++ } ++ + host->bus_hz = host->pdata->bus_hz; + } else { + ret = clk_prepare_enable(host->ciu_clk); -- 2.30.2