From c30267f5023aef44d4367c631c42f217a2ec37f6 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 3 Mar 2017 15:16:03 -0500 Subject: [PATCH] drm/amd/display: TPS4 logic typo fix Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Wenjing Liu Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 37efa40a9bca..80002795adc2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -921,8 +921,8 @@ static inline bool perform_link_training_int( * If the upstream DPTX and downstream DPRX both support TPS4, * TPS4 must be used instead of POST_LT_ADJ_REQ. */ - if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 && - get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4) + if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 || + get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4) return status; if (status && -- 2.30.2