From c10bd2ce69e54a8c71fa773810e130fc465c03ac Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 12 Nov 2013 16:41:16 +0000 Subject: [PATCH] Move generic architectural setup out of blx_plat_arch_setup(). blx_plat_arch_setup() should only perform platform-specific architectural setup, e.g. enabling the MMU. This patch moves generic architectural setup code out of blx_plat_arch_setup(). Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6 --- arch/aarch64/cpu/cpu_helpers.S | 11 +---------- bl1/aarch64/bl1_entrypoint.S | 18 ++++++++++++++++++ bl2/aarch64/bl2_entrypoint.S | 18 ++++++++++++++++++ bl31/aarch64/bl31_entrypoint.S | 26 ++++++++++++++++++++++++-- plat/fvp/bl2_plat_setup.c | 15 --------------- plat/fvp/bl31_plat_setup.c | 8 -------- 6 files changed, 61 insertions(+), 35 deletions(-) diff --git a/arch/aarch64/cpu/cpu_helpers.S b/arch/aarch64/cpu/cpu_helpers.S index 600b72fb..76edaa3b 100644 --- a/arch/aarch64/cpu/cpu_helpers.S +++ b/arch/aarch64/cpu/cpu_helpers.S @@ -39,14 +39,9 @@ cpu_reset_handler:; .type cpu_reset_handler, %function mov x19, x30 // lr /* --------------------------------------------- - * As a bare minimal enable the SMP bit and the - * I$ for all aarch64 processors. Also set the - * exception vector to something sane. + * As a bare minimal enable the SMP bit. * --------------------------------------------- */ - adr x0, early_exceptions - bl write_vbar - bl read_midr lsr x0, x0, #MIDR_PN_SHIFT and x0, x0, #MIDR_PN_MASK @@ -59,8 +54,4 @@ smp_setup_begin: orr x0, x0, #CPUECTLR_SMP_BIT bl write_cpuectlr smp_setup_end: - bl read_sctlr - orr x0, x0, #SCTLR_I_BIT - bl write_sctlr - ret x19 diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index f5ccc655..9db2bdf0 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -28,6 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include .globl reset_handler @@ -49,6 +50,23 @@ reset_handler:; .type reset_handler, %function */ bl cpu_reset_handler + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, early_exceptions + msr vbar_el3, x0 + + /* --------------------------------------------- + * Enable the instruction cache. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + orr x0, x0, #SCTLR_I_BIT + msr sctlr_el3, x0 + + isb + _wait_for_entrypoint: /* --------------------------------------------- * Find the type of reset and jump to handler diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index bade0991..4b989a69 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -29,6 +29,7 @@ */ #include +#include .globl bl2_entrypoint @@ -59,6 +60,23 @@ bl2_entrypoint:; .type bl2_entrypoint, %function bl platform_is_primary_cpu cbz x0, _panic + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, early_exceptions + msr vbar_el1, x0 + + /* --------------------------------------------- + * Enable the instruction cache. + * --------------------------------------------- + */ + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_I_BIT + msr sctlr_el1, x0 + + isb + /* -------------------------------------------- * Give ourselves a small coherent stack to * ease the pain of initializing the MMU diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 3a850e6a..3922840d 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -31,6 +31,7 @@ #include #include #include +#include .globl bl31_entrypoint @@ -50,8 +51,29 @@ bl31_entrypoint:; .type bl31_entrypoint, %function * indicating BL31 should be run, memory layout * of the trusted SRAM available to BL31 and * information about running the non-trusted - * software already loaded by BL2. Check the - * opcode out of paranoia. + * software already loaded by BL2. + * --------------------------------------------- + */ + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x1, runtime_exceptions + msr vbar_el3, x1 + + /* --------------------------------------------- + * Enable the instruction cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + orr x1, x1, #SCTLR_I_BIT + msr sctlr_el3, x1 + + isb + + /* --------------------------------------------- + * Check the opcodes out of paranoia. * --------------------------------------------- */ mov x19, #RUN_IMAGE diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index e38f00bd..4bb10157 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -124,24 +124,9 @@ void bl2_platform_setup() ******************************************************************************/ void bl2_plat_arch_setup() { - unsigned long sctlr; - - /* Enable instruction cache. */ - sctlr = read_sctlr(); - sctlr |= SCTLR_I_BIT; - write_sctlr(sctlr); - - /* - * Very simple exception vectors which assert if any exception other - * than a single SMC call from BL2 to pass control to BL31 in EL3 is - * received. - */ - write_vbar((unsigned long) early_exceptions); - configure_mmu(&bl2_tzram_layout, (unsigned long) &BL2_RO_BASE, (unsigned long) &BL2_STACKS_BASE, (unsigned long) &BL2_COHERENT_RAM_BASE, (unsigned long) &BL2_RW_BASE); - return; } diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c index 6c8635fa..7aa1182d 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_plat_setup.c @@ -166,14 +166,6 @@ void bl31_platform_setup() ******************************************************************************/ void bl31_plat_arch_setup() { - unsigned long sctlr; - - /* Enable instruction cache. */ - sctlr = read_sctlr(); - sctlr |= SCTLR_I_BIT; - write_sctlr(sctlr); - - write_vbar((unsigned long) runtime_exceptions); configure_mmu(&bl31_tzram_layout, (unsigned long) &BL31_RO_BASE, (unsigned long) &BL31_STACKS_BASE, -- 2.30.2