From bf92384b6d729b22916ba832b4a225ca196e98ba Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 2 Nov 2016 16:43:24 -0700 Subject: [PATCH] clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused Rockchip RK3399 PLLs can be used in two separate modes: integral and fractional. We can select between these two modes with the unambiguously named DSMPD bit. During boot, we check all PLL settings to confirm that they match our PLL table for that frequency, and reinitialize the PLLs where they don't. The settings checked for this include the fractional divider field that is only used in fractional mode, even if we're in integral mode (DSMPD = 1) and that field has no effect. This patch changes the check to only compare the fractional divider if we're actually in fractional mode. This way, we won't reinitialize the PLL in cases where there's absolutely no reason for that, which may avoid glitching child clocks that should better not be glitched (e.g. PWM regulators). Signed-off-by: Julius Werner [cloned the fix to the pretty similar rk3036 pll] Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 9c1373e81683..6ed605776abd 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -319,7 +319,8 @@ static void rockchip_rk3036_pll_init(struct clk_hw *hw) if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || - rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { struct clk *parent = clk_get_parent(hw->clk); if (!parent) { @@ -795,7 +796,8 @@ static void rockchip_rk3399_pll_init(struct clk_hw *hw) if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || - rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { struct clk *parent = clk_get_parent(hw->clk); if (!parent) { -- 2.30.2