From bc5c30073e1ec28407e22727848df1adda433636 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Thu, 4 May 2017 16:02:45 +0800 Subject: [PATCH] rockchip: add pmusram section the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang Signed-off-by: Caesar Wang --- .../rockchip/common/aarch64/platform_common.c | 2 +- plat/rockchip/common/bl31_plat_setup.c | 2 - plat/rockchip/common/include/plat_private.h | 15 ++-- plat/rockchip/common/pmusram/pmu_sram.c | 57 --------------- plat/rockchip/common/pmusram/pmu_sram.h | 53 -------------- .../common/pmusram/pmu_sram_cpus_on.S | 59 +++++----------- plat/rockchip/rk3328/drivers/pmu/pmu.c | 70 +++++-------------- plat/rockchip/rk3328/include/plat.ld.S | 44 +++++------- plat/rockchip/rk3328/include/platform_def.h | 2 + plat/rockchip/rk3328/platform.mk | 1 - plat/rockchip/rk3368/drivers/pmu/pmu.c | 56 +++------------ plat/rockchip/rk3368/include/plat.ld.S | 37 ++++++++++ plat/rockchip/rk3368/include/platform_def.h | 2 + plat/rockchip/rk3368/platform.mk | 3 +- plat/rockchip/rk3399/drivers/pmu/pmu.c | 62 ++++++++-------- plat/rockchip/rk3399/include/plat.ld.S | 28 ++++++++ plat/rockchip/rk3399/include/platform_def.h | 1 + plat/rockchip/rk3399/platform.mk | 1 - 18 files changed, 175 insertions(+), 320 deletions(-) delete mode 100644 plat/rockchip/common/pmusram/pmu_sram.c delete mode 100644 plat/rockchip/common/pmusram/pmu_sram.h create mode 100644 plat/rockchip/rk3368/include/plat.ld.S diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c index 9c68b3bc..a756f40d 100644 --- a/plat/rockchip/common/aarch64/platform_common.c +++ b/plat/rockchip/common/aarch64/platform_common.c @@ -44,7 +44,7 @@ static const int cci_map[] = { coh_limit - coh_start, \ MT_DEVICE | MT_RW | MT_SECURE); \ mmap_add(plat_rk_mmap); \ - rockchip_plat_sram_mmu_el##_el(); \ + rockchip_plat_mmu_el##_el(); \ init_xlat_tables(); \ \ enable_mmu_el ## _el(0); \ diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 71d66c97..f7564e81 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -83,8 +83,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, bl32_ep_info = *from_bl2->bl32_ep_info; bl33_ep_info = *from_bl2->bl33_ep_info; - plat_rockchip_pmusram_prepare(); - /* there may have some board sepcific message need to initialize */ params_early_setup(plat_params_from_bl2); } diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index 867d9add..f0aee087 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -15,11 +15,15 @@ #define __sramdata __attribute__((section(".sram.data"))) #define __sramconst __attribute__((section(".sram.rodata"))) -#define __sramfunc __attribute__((section(".sram.text"))) \ - __attribute__((noinline)) +#define __sramfunc __attribute__((section(".sram.text"))) + +#define __pmusramdata __attribute__((section(".pmusram.data"))) +#define __pmusramconst __attribute__((section(".pmusram.rodata"))) +#define __pmusramfunc __attribute__((section(".pmusram.text"))) extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; +extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; extern uint32_t __sram_incbin_start, __sram_incbin_end; @@ -73,7 +77,6 @@ void plat_rockchip_gic_cpuif_enable(void); void plat_rockchip_gic_cpuif_disable(void); void plat_rockchip_gic_pcpu_init(void); -void plat_rockchip_pmusram_prepare(void); void plat_rockchip_pmu_init(void); void plat_rockchip_soc_init(void); uintptr_t plat_get_sec_entrypoint(void); @@ -110,15 +113,13 @@ void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); extern const unsigned char rockchip_power_domain_tree_desc[]; -extern void *pmu_cpuson_entrypoint_start; -extern void *pmu_cpuson_entrypoint_end; +extern void *pmu_cpuson_entrypoint; extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; extern const mmap_region_t plat_rk_mmap[]; -void rockchip_plat_sram_mmu_el3(void); -void plat_rockchip_mem_prepare(void); +void rockchip_plat_mmu_el3(void); #endif /* __ASSEMBLY__ */ diff --git a/plat/rockchip/common/pmusram/pmu_sram.c b/plat/rockchip/common/pmusram/pmu_sram.c deleted file mode 100644 index 05ee762e..00000000 --- a/plat/rockchip/common/pmusram/pmu_sram.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -/***************************************************************************** - * sram only surpport 32-bits access - ******************************************************************************/ -void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes) -{ - uint32_t i; - - for (i = 0; i < bytes; i++) - dst[i] = src[i]; -} - -void rockchip_plat_sram_mmu_el3(void) -{ -#ifdef PLAT_EXTRA_LD_SCRIPT - size_t sram_size; - - /* sram.text size */ - sram_size = (char *)&__bl31_sram_text_end - - (char *)&__bl31_sram_text_start; - mmap_add_region((unsigned long)&__bl31_sram_text_start, - (unsigned long)&__bl31_sram_text_start, - sram_size, MT_MEMORY | MT_RO | MT_SECURE); - - /* sram.data size */ - sram_size = (char *)&__bl31_sram_data_end - - (char *)&__bl31_sram_data_start; - mmap_add_region((unsigned long)&__bl31_sram_data_start, - (unsigned long)&__bl31_sram_data_start, - sram_size, MT_MEMORY | MT_RW | MT_SECURE); - - /* sram.incbin size */ - sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start; - mmap_add_region((unsigned long)&__sram_incbin_start, - (unsigned long)&__sram_incbin_start, - sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE); -#else - /* TODO: Support other SoCs, Just support RK3399 now */ - return; -#endif -} - -void plat_rockchip_mem_prepare(void) -{ - /* The code for resuming cpu from suspend must be excuted in pmusram */ - plat_rockchip_pmusram_prepare(); -} diff --git a/plat/rockchip/common/pmusram/pmu_sram.h b/plat/rockchip/common/pmusram/pmu_sram.h deleted file mode 100644 index 24a1c25e..00000000 --- a/plat/rockchip/common/pmusram/pmu_sram.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PMU_SRAM_H__ -#define __PMU_SRAM_H__ - -/***************************************************************************** - * define data offset in struct psram_data - *****************************************************************************/ -#define PSRAM_DT_SP 0x0 -#define PSRAM_DT_DDR_FUNC 0x8 -#define PSRAM_DT_DDR_DATA 0x10 -#define PSRAM_DT_DDRFLAG 0x18 -#define PSRAM_DT_MPIDR 0x1c -#define PSRAM_DT_END 0x20 -/****************************************************************************** - * Allocate data region for struct psram_data_t in pmusram - ******************************************************************************/ -/* Needed aligned 16 bytes for sp stack top */ -#define PSRAM_DT_SIZE (((PSRAM_DT_END + 16) / 16) * 16) -#define PSRAM_DT_BASE ((PMUSRAM_BASE + PMUSRAM_RSIZE) - PSRAM_DT_SIZE) -#define PSRAM_SP_TOP PSRAM_DT_BASE - -#ifndef __ASSEMBLY__ - -struct psram_data_t { - uint64_t sp; - uint64_t ddr_func; - uint64_t ddr_data; - uint32_t ddr_flag; - uint32_t boot_mpidr; -}; - -CASSERT(sizeof(struct psram_data_t) <= PSRAM_DT_SIZE, - assert_psram_dt_size_mismatch); -CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP, - assert_psram_dt_sp_offset_mistmatch); -CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC, - assert_psram_dt_ddr_func_offset_mistmatch); -CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA, - assert_psram_dt_ddr_data_offset_mistmatch); -CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG, - assert_psram_dt_ddr_flag_offset_mistmatch); -CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, - assert_psram_dt_mpidr_offset_mistmatch); -void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes); - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S index 8f175c3c..64261ac0 100644 --- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S +++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S @@ -7,50 +7,25 @@ #include #include #include -#include - .globl pmu_cpuson_entrypoint_start - .globl pmu_cpuson_entrypoint_end + .globl pmu_cpuson_entrypoint + .macro pmusram_entry_func _name + .section .pmusram.entry, "ax" + .type \_name, %function + .func \_name + .cfi_startproc + \_name: + .endm -func pmu_cpuson_entrypoint -pmu_cpuson_entrypoint_start: - ldr x5, psram_data -check_wake_cpus: - mrs x0, MPIDR_EL1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - orr x0, x0, x1 - /* primary_cpu */ - ldr w1, [x5, #PSRAM_DT_MPIDR] - cmp w0, w1 - b.eq sys_wakeup - /* - * If the core is not the primary cpu, - * force the core into wfe. - */ -wfe_loop: - wfe - b wfe_loop -sys_wakeup: - /* check ddr flag for resume ddr */ - ldr w2, [x5, #PSRAM_DT_DDRFLAG] - cmp w2, #0x0 - b.eq sys_resume +pmusram_entry_func pmu_cpuson_entrypoint + +#if PSRAM_DO_DDR_RESUME ddr_resume: - ldr x2, [x5, #PSRAM_DT_SP] - mov sp, x2 - ldr x1, [x5, #PSRAM_DT_DDR_FUNC] - ldr x0, [x5, #PSRAM_DT_DDR_DATA] - blr x1 -sys_resume: - ldr x1, sys_wakeup_entry - br x1 + ldr x2, =__bl31_sram_stack_end + mov sp, x2 + bl dmc_restore +#endif - .align 3 -psram_data: - .quad PSRAM_DT_BASE -sys_wakeup_entry: - .quad psci_entrypoint -pmu_cpuson_entrypoint_end: - .word 0 +sys_resume: + bl psci_entrypoint endfunc pmu_cpuson_entrypoint diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index 59d399be..60f36d31 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -16,16 +16,12 @@ #include #include #include -#include #include #include #include DEFINE_BAKERY_LOCK(rockchip_pd_lock); -static struct psram_data_t *psram_sleep_cfg = - (struct psram_data_t *)PSRAM_DT_BASE; - static struct rk3328_sleep_ddr_data ddr_data; static __sramdata struct rk3328_sleep_sram_data sram_data; @@ -34,22 +30,6 @@ static uint32_t cpu_warm_boot_addr; #pragma weak rk3328_pmic_suspend #pragma weak rk3328_pmic_resume -void plat_rockchip_pmusram_prepare(void) -{ - uint32_t *sram_dst, *sram_src; - size_t sram_size = 2; - /* - * pmu sram code and data prepare - */ - sram_dst = (uint32_t *)PMUSRAM_BASE; - sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; - sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - - (uint32_t *)sram_src; - u32_align_cpy(sram_dst, sram_src, sram_size); - - psram_sleep_cfg->sp = PSRAM_DT_BASE; -} - static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) { uint32_t pd_reg, apm_reg; @@ -140,6 +120,16 @@ static void nonboot_cpus_off(void) } } +void sram_save(void) +{ + /* TODO: support the sdram save for rk3328 SoCs*/ +} + +void sram_restore(void) +{ + /* TODO: support the sdram restore for rk3328 SoCs */ +} + int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) { uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); @@ -495,11 +485,6 @@ __sramfunc void rk3328_pmic_resume(void) sram_udelay(100); } -static inline void rockchip_set_sram_sp(uint64_t set_sp) -{ - __asm volatile("mov sp, %0\n"::"r" (set_sp) : "sp"); -} - static __sramfunc void ddr_suspend(void) { sram_data.pd_sr_idle_save = mmio_read_32(DDR_UPCTL_BASE + @@ -538,7 +523,7 @@ static __sramfunc void ddr_suspend(void) dpll_suspend(); } -static __sramfunc void ddr_resume(void) +__sramfunc void dmc_restore(void) { dpll_resume(); @@ -574,7 +559,7 @@ static __sramfunc void sram_dbg_uart_suspend(void) mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004); } -static __sramfunc void sram_dbg_uart_resume(void) +__sramfunc void sram_dbg_uart_resume(void) { /* restore uart clk and reset fifo */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000); @@ -610,7 +595,7 @@ __sramfunc void sram_suspend(void) disable_mmu_icache_el3(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | + ((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); /* ddr self-refresh and gating phy */ @@ -623,28 +608,8 @@ __sramfunc void sram_suspend(void) sram_soc_enter_lp(); } -static __sramfunc void sys_resume_first(void) -{ - sram_dbg_uart_resume(); - - rk3328_pmic_resume(); - - /* ddr self-refresh exit */ - ddr_resume(); - - /* disable apm cfg */ - mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(0), CORES_PM_DISABLE); - - /* the warm booting address of cpus */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | - CPU_BOOT_ADDR_WMASK); -} - void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) { - rockchip_set_sram_sp(PSRAM_DT_BASE); - sram_suspend(); /* should never reach here */ @@ -671,6 +636,11 @@ int rockchip_soc_sys_pwr_dm_resume(void) return 0; } +void rockchip_plat_mmu_el3(void) +{ + /* TODO: support the el3 for rk3328 SoCs */ +} + void plat_rockchip_pmu_init(void) { uint32_t cpu; @@ -679,10 +649,6 @@ void plat_rockchip_pmu_init(void) cpuson_flags[cpu] = 0; cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; - psram_sleep_cfg->ddr_func = (uint64_t)sys_resume_first; - psram_sleep_cfg->ddr_data = 0x00; - psram_sleep_cfg->ddr_flag = 0x01; - psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; /* the warm booting address of cpus */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), diff --git a/plat/rockchip/rk3328/include/plat.ld.S b/plat/rockchip/rk3328/include/plat.ld.S index ff17572d..b3559b20 100644 --- a/plat/rockchip/rk3328/include/plat.ld.S +++ b/plat/rockchip/rk3328/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,39 +7,31 @@ #define __ROCKCHIP_PLAT_LD_S__ MEMORY { - SRAM (rwx): ORIGIN = SRAM_LDS_BASE, LENGTH = SRAM_LDS_SIZE + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE } SECTIONS { - . = SRAM_LDS_BASE; - ASSERT(. == ALIGN(4096), - "SRAM_BASE address is not aligned on a page boundary.") + . = PMUSRAM_BASE; /* - * The SRAM space allocation for RK3328 - * ---------------- - * | sram text - * ---------------- - * | sram data - * ---------------- + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram */ - .text_sram : ALIGN(4096) { - __bl31_sram_text_start = .; - *(.sram.text) - *(.sram.rodata) - . = ALIGN(4096); - __bl31_sram_text_end = .; - } >SRAM + .text_pmusram : { + ASSERT(. == ALIGN(64 * 1024), + ".pmusram.entry request 64K aligned."); + *(.pmusram.entry) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_end = .; - .data_sram : ALIGN(4096) { - __bl31_sram_data_start = .; - *(.sram.data) - . = ALIGN(4096); - __bl31_sram_data_end = .; - } >SRAM - __sram_incbin_start = .; - __sram_incbin_end = .; + } >PMUSRAM } #endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 1f49fcdc..9b192884 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -120,4 +120,6 @@ #define PLAT_RK_PRIMARY_CPU 0x0 +#define PSRAM_DO_DDR_RESUME 0 + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index b81d746b..8863fb4f 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -41,7 +41,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ ${RK_PLAT_COMMON}/plat_pm.c \ ${RK_PLAT_COMMON}/plat_topology.c \ diff --git a/plat/rockchip/rk3368/drivers/pmu/pmu.c b/plat/rockchip/rk3368/drivers/pmu/pmu.c index e5e68051..ad0b5ffe 100644 --- a/plat/rockchip/rk3368/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3368/drivers/pmu/pmu.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -22,9 +21,6 @@ DEFINE_BAKERY_LOCK(rockchip_pd_lock); -static struct psram_data_t *psram_sleep_cfg = - (struct psram_data_t *)PSRAM_DT_BASE; - static uint32_t cpu_warm_boot_addr; void rk3368_flash_l2_b(void) @@ -223,54 +219,19 @@ static void pmu_sleep_mode_config(void) dsb(); } -static void ddr_suspend_save(void) -{ - ddr_reg_save(1, psram_sleep_cfg->ddr_data); -} - static void pmu_set_sleep_mode(void) { - ddr_suspend_save(); pmu_sleep_mode_config(); soc_sleep_config(); regs_updata_bit_set(PMU_BASE + PMU_PWRMD_CORE, pmu_mdcr_global_int_dis); regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_glbl_int_dis_b); pmu_scu_b_pwrdn(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | - CPU_BOOT_ADDR_WMASK); + ((uintptr_t)&pmu_cpuson_entrypoint >> + CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), - (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | - CPU_BOOT_ADDR_WMASK); -} - -void plat_rockchip_pmusram_prepare(void) -{ - uint32_t *sram_dst, *sram_src; - size_t sram_size = 2; - uint32_t code_size; - - /* pmu sram code and data prepare */ - sram_dst = (uint32_t *)PMUSRAM_BASE; - sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; - sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - - (uint32_t *)sram_src; - u32_align_cpy(sram_dst, sram_src, sram_size); - - /* ddr code */ - sram_dst += sram_size; - sram_src = ddr_get_resume_code_base(); - code_size = ddr_get_resume_code_size(); - u32_align_cpy(sram_dst, sram_src, code_size / 4); - psram_sleep_cfg->ddr_func = (uint64_t)sram_dst; - - /* ddr data */ - sram_dst += (code_size / 4); - psram_sleep_cfg->ddr_data = (uint64_t)sram_dst; - - assert((uint64_t)(sram_dst + ddr_get_resume_data_size() / 4) - < PSRAM_SP_BOTTOM); - psram_sleep_cfg->sp = PSRAM_SP_TOP; + ((uintptr_t)&pmu_cpuson_entrypoint >> + CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); } static int cpus_id_power_domain(uint32_t cluster, @@ -375,11 +336,14 @@ int rockchip_soc_sys_pwr_dm_suspend(void) nonboot_cpus_off(); pmu_set_sleep_mode(); - psram_sleep_cfg->ddr_flag = 0; - return 0; } +void rockchip_plat_mmu_el3(void) +{ + /* TODO: support the el3 for rk3368 SoCs */ +} + void plat_rockchip_pmu_init(void) { uint32_t cpu; @@ -390,8 +354,6 @@ void plat_rockchip_pmu_init(void) for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) cpuson_flags[cpu] = 0; - psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; - nonboot_cpus_off(); INFO("%s(%d): pd status %x\n", __func__, __LINE__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); diff --git a/plat/rockchip/rk3368/include/plat.ld.S b/plat/rockchip/rk3368/include/plat.ld.S new file mode 100644 index 00000000..b3559b20 --- /dev/null +++ b/plat/rockchip/rk3368/include/plat.ld.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __ROCKCHIP_PLAT_LD_S__ +#define __ROCKCHIP_PLAT_LD_S__ + +MEMORY { + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE +} + +SECTIONS +{ + . = PMUSRAM_BASE; + + /* + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram + */ + .text_pmusram : { + ASSERT(. == ALIGN(64 * 1024), + ".pmusram.entry request 64K aligned."); + *(.pmusram.entry) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_end = .; + + } >PMUSRAM +} + +#endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 053f6fe3..4ad3445d 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -122,4 +122,6 @@ #define PLAT_RK_PRIMARY_CPU 0x0 +#define PSRAM_DO_DDR_RESUME 0 + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk index 7837af98..f6960cf4 100644 --- a/plat/rockchip/rk3368/platform.mk +++ b/plat/rockchip/rk3368/platform.mk @@ -39,7 +39,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ ${RK_PLAT_COMMON}/params_setup.c \ ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ ${RK_PLAT_COMMON}/plat_pm.c \ ${RK_PLAT_COMMON}/plat_topology.c \ ${RK_PLAT_COMMON}/aarch64/platform_common.c \ @@ -50,3 +49,5 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \ ENABLE_PLAT_COMPAT := 0 + +$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 9c0a29c1..cf1ea48d 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -30,9 +29,6 @@ DEFINE_BAKERY_LOCK(rockchip_pd_lock); -static struct psram_data_t *psram_sleep_cfg = - (struct psram_data_t *)PSRAM_DT_BASE; - static uint32_t cpu_warm_boot_addr; /* @@ -411,24 +407,6 @@ static void pmu_scu_b_pwrup(void) mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); } -void plat_rockchip_pmusram_prepare(void) -{ - uint32_t *sram_dst, *sram_src; - size_t sram_size; - - /* - * pmu sram code and data prepare - */ - sram_dst = (uint32_t *)PMUSRAM_BASE; - sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; - sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - - (uint32_t *)sram_src; - - u32_align_cpy(sram_dst, sram_src, sram_size); - - psram_sleep_cfg->sp = PSRAM_DT_BASE; -} - static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) { assert(cpu_id < PLATFORM_CORE_COUNT); @@ -1077,8 +1055,8 @@ int rockchip_soc_sys_pwr_dm_suspend(void) pmu_sgrf_rst_hld(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | - CPU_BOOT_ADDR_WMASK); + ((uintptr_t)&pmu_cpuson_entrypoint >> + CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); mmio_write_32(PMU_BASE + PMU_ADB400_CON, BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | @@ -1245,6 +1223,36 @@ void __dead2 rockchip_soc_system_off(void) ; } +void rockchip_plat_mmu_el3(void) +{ + size_t sram_size; + + /* sram.text size */ + sram_size = (char *)&__bl31_sram_text_end - + (char *)&__bl31_sram_text_start; + mmap_add_region((unsigned long)&__bl31_sram_text_start, + (unsigned long)&__bl31_sram_text_start, + sram_size, MT_MEMORY | MT_RO | MT_SECURE); + + /* sram.data size */ + sram_size = (char *)&__bl31_sram_data_end - + (char *)&__bl31_sram_data_start; + mmap_add_region((unsigned long)&__bl31_sram_data_start, + (unsigned long)&__bl31_sram_data_start, + sram_size, MT_MEMORY | MT_RW | MT_SECURE); + + sram_size = (char *)&__bl31_sram_stack_end - + (char *)&__bl31_sram_stack_start; + mmap_add_region((unsigned long)&__bl31_sram_stack_start, + (unsigned long)&__bl31_sram_stack_start, + sram_size, MT_MEMORY | MT_RW | MT_SECURE); + + sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start; + mmap_add_region((unsigned long)&__sram_incbin_start, + (unsigned long)&__sram_incbin_start, + sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE); +} + void plat_rockchip_pmu_init(void) { uint32_t cpu; @@ -1260,12 +1268,6 @@ void plat_rockchip_pmu_init(void) for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++) clst_warmboot_data[cpu] = 0; - psram_sleep_cfg->ddr_func = (uint64_t)dmc_restore; - psram_sleep_cfg->ddr_data = (uint64_t)&sdram_config; - psram_sleep_cfg->ddr_flag = 0x01; - - psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; - /* config cpu's warm boot address */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | diff --git a/plat/rockchip/rk3399/include/plat.ld.S b/plat/rockchip/rk3399/include/plat.ld.S index 49206bea..86ca0494 100644 --- a/plat/rockchip/rk3399/include/plat.ld.S +++ b/plat/rockchip/rk3399/include/plat.ld.S @@ -8,6 +8,7 @@ MEMORY { SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE } SECTIONS @@ -47,6 +48,33 @@ SECTIONS . = ALIGN(4096); __bl31_sram_data_end = .; } >SRAM + + .stack_sram : ALIGN(4096) { + __bl31_sram_stack_start = .; + . += 4096; + __bl31_sram_stack_end = .; + } >SRAM + + . = PMUSRAM_BASE; + + /* + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram + */ + .pmusram : { + ASSERT(. == ALIGN(64 * 1024), + ".pmusram.entry request 64K aligned."); + *(.pmusram.entry) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_end = .; + + } >PMUSRAM } #endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index f4427d01..49372298 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -107,4 +107,5 @@ #define PLAT_RK_PRIMARY_CPU 0x0 +#define PSRAM_DO_DDR_RESUME 1 #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index be3e11b9..cb7999b5 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -44,7 +44,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ ${RK_PLAT_COMMON}/params_setup.c \ ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ ${RK_PLAT_COMMON}/plat_pm.c \ ${RK_PLAT_COMMON}/plat_topology.c \ ${RK_PLAT_COMMON}/aarch64/platform_common.c \ -- 2.30.2