From b6f68b1ecbffc0aec1704c731c3b99acbe3becfd Mon Sep 17 00:00:00 2001 From: Sujith Manoharan Date: Mon, 2 Feb 2015 18:21:11 +0530 Subject: [PATCH] ath9k: Program AR_WA correctly Setting the required configuration in the PCIE WorkAround register needs to be done after all the WoW parameters have been set. Signed-off-by: Sujith Manoharan Signed-off-by: Kalle Valo --- drivers/net/wireless/ath/ath9k/ar9003_wow.c | 39 ++++++++++++--------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_wow.c b/drivers/net/wireless/ath/ath9k/ar9003_wow.c index 6ffa0e0d028c..cf45b91f0a60 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_wow.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c @@ -219,30 +219,33 @@ u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) } EXPORT_SYMBOL(ath9k_hw_wow_wakeup); +static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah) +{ + u32 wa_reg; + + if (!ah->is_pciexpress) + return; + + /* + * We need to untie the internal POR (power-on-reset) + * to the external PCI-E reset. We also need to tie + * the PCI-E Phy reset to the PCI-E reset. + */ + wa_reg = REG_READ(ah, AR_WA); + wa_reg &= ~AR_WA_UNTIE_RESET_EN; + wa_reg |= AR_WA_RESET_EN; + wa_reg |= AR_WA_POR_SHORT; + + REG_WRITE(ah, AR_WA, wa_reg); +} + void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) { u32 wow_event_mask; u32 keep_alive, magic_pattern, host_pm_ctrl; - u32 set, clr; wow_event_mask = ah->wow.wow_event_mask; - /* - * Untie Power-on-Reset from the PCI-E-Reset. When we are in - * WOW sleep, we do want the Reset from the PCI-E to disturb - * our hw state - */ - if (ah->is_pciexpress) { - /* - * we need to untie the internal POR (power-on-reset) - * to the external PCI-E reset. We also need to tie - * the PCI-E Phy reset to the PCI-E reset. - */ - set = AR_WA_RESET_EN | AR_WA_POR_SHORT; - clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE; - REG_RMW(ah, AR_WA, set, clr); - } - /* * AR_PMCTRL_HOST_PME_EN - Override PME enable in configuration * space and allow MAC to generate WoW anyway. @@ -390,6 +393,8 @@ void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) /* To bring down WOW power low margin */ REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); + ath9k_hw_wow_set_arwr_reg(ah); + /* HW WoW */ REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); -- 2.30.2