From b5c8753fa173d6372d86dcd11f83ef23c911b0de Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Feb 2011 02:03:29 -0600 Subject: [PATCH] powerpc/85xx: Fixup determining PME, FMan freq On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/speed.c | 38 +++++++++++++++++------ arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++ 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index faca451cc1..f26de6cd3e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,25 +107,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0529632567..4228161c62 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -243,6 +243,7 @@ #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -252,6 +253,7 @@ #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -262,12 +264,14 @@ #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -290,6 +294,7 @@ /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -300,6 +305,7 @@ #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 -- 2.30.2