From b2bd0199a845281ca1c097d84caab022e98c2c59 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Fri, 21 May 2021 23:20:43 +0900 Subject: [PATCH] realtek: drop platform irq driver from 5.10 To use backported irq driver, drop old irq driver from realtek target and call irqchip_init() in setup.c. Signed-off-by: INAGAKI Hiroshi --- .../arch/mips/include/asm/mach-rtl838x/irq.h | 93 ------- .../files-5.10/arch/mips/rtl838x/Makefile | 2 +- .../files-5.10/arch/mips/rtl838x/irq.c | 226 ------------------ .../files-5.10/arch/mips/rtl838x/setup.c | 6 + 4 files changed, 7 insertions(+), 320 deletions(-) delete mode 100644 target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/irq.h delete mode 100644 target/linux/realtek/files-5.10/arch/mips/rtl838x/irq.c diff --git a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/irq.h b/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/irq.h deleted file mode 100644 index a4e95ab511..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/irq.h +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#ifndef _RTL83XX_IRQ_H_ -#define _RTL83XX_IRQ_H_ - -#define NR_IRQS 32 -#include_next - -/* Global Interrupt Mask Register */ -#define RTL83XX_ICTL_GIMR 0x00 -/* Global Interrupt Status Register */ -#define RTL83XX_ICTL_GISR 0x04 - -#define RTL83XX_IRQ_CPU_BASE 0 -#define RTL83XX_IRQ_CPU_NUM 8 -#define RTL83XX_IRQ_ICTL_BASE (RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM) -#define RTL83XX_IRQ_ICTL_NUM 32 - -/* Cascaded interrupts */ -#define RTL83XX_ICTL1_IRQ (RTL83XX_IRQ_CPU_BASE + 2) -#define RTL83XX_ICTL2_IRQ (RTL83XX_IRQ_CPU_BASE + 3) -#define RTL83XX_ICTL3_IRQ (RTL83XX_IRQ_CPU_BASE + 4) -#define RTL83XX_ICTL4_IRQ (RTL83XX_IRQ_CPU_BASE + 5) -#define RTL83XX_ICTL5_IRQ (RTL83XX_IRQ_CPU_BASE + 6) - -/* Interrupt routing register */ -#define RTL83XX_IRR0 0x08 -#define RTL83XX_IRR1 0x0c -#define RTL83XX_IRR2 0x10 -#define RTL83XX_IRR3 0x14 - -/* Cascade map */ -#define UART0_CASCADE 2 -#define UART1_CASCADE 1 -#define TC0_CASCADE 5 -#define TC1_CASCADE 1 -#define TC2_CASCADE 1 -#define TC3_CASCADE 1 -#define TC4_CASCADE 1 -#define OCPTO_CASCADE 1 -#define HLXTO_CASCADE 1 -#define SLXTO_CASCADE 1 -#define NIC_CASCADE 4 -#define GPIO_ABCD_CASCADE 4 -#define GPIO_EFGH_CASCADE 4 -#define RTC_CASCADE 4 -#define SWCORE_CASCADE 3 -#define WDT_IP1_CASCADE 4 -#define WDT_IP2_CASCADE 5 -#define USB_H2_CASCADE 1 - -/* Pack cascade map into interrupt routing registers */ -#define RTL83XX_IRR0_SETTING (\ - (UART0_CASCADE << 28) | \ - (UART1_CASCADE << 24) | \ - (TC0_CASCADE << 20) | \ - (TC1_CASCADE << 16) | \ - (OCPTO_CASCADE << 12) | \ - (HLXTO_CASCADE << 8) | \ - (SLXTO_CASCADE << 4) | \ - (NIC_CASCADE << 0)) -#define RTL83XX_IRR1_SETTING (\ - (GPIO_ABCD_CASCADE << 28) | \ - (GPIO_EFGH_CASCADE << 24) | \ - (RTC_CASCADE << 20) | \ - (SWCORE_CASCADE << 16)) -#define RTL83XX_IRR2_SETTING 0 -#define RTL83XX_IRR3_SETTING 0 - -/* On the RTL8390 there is no GPIO_EFGH and RTC IRQ */ -#define RTL8390_IRR1_SETTING (\ - (GPIO_ABCD_CASCADE << 28) | \ - (SWCORE_CASCADE << 16)) - -/* The RTL9300 has a different external IRQ numbering scheme */ -#define RTL9300_IRR0_SETTING (\ - (UART1_CASCADE << 28) | \ - (UART0_CASCADE << 24) | \ - (USB_H2_CASCADE << 16) | \ - (NIC_CASCADE << 0)) -#define RTL9300_IRR1_SETTING (\ - (SWCORE_CASCADE << 28)) -#define RTL9300_IRR2_SETTING (\ - (GPIO_ABCD_CASCADE << 20) | \ - (TC4_CASCADE << 12) | \ - (TC3_CASCADE << 8) | \ - (TC2_CASCADE << 4) | \ - (TC1_CASCADE << 0)) -#define RTL9300_IRR3_SETTING (\ - (TC0_CASCADE << 28) | \ - (WDT_IP1_CASCADE << 20)) - -#endif /* _RTL83XX_IRQ_H_ */ diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile index 8212dc3f48..a9d1666d46 100644 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile +++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile @@ -2,4 +2,4 @@ # Makefile for the rtl838x specific parts of the kernel # -obj-y := setup.o prom.o irq.o +obj-y := setup.o prom.o diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/irq.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/irq.c deleted file mode 100644 index c0dd2f608c..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/irq.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Realtek RTL83XX architecture specific IRQ handling - * - * based on the original BSP - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * Copyright (C) 2020 B. Koblitz - * Copyright (C) 2020 Bert Vermeulen - * Copyright (C) 2020 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include -#include "irq.h" - -#define REALTEK_CPU_IRQ_SHARED0 (MIPS_CPU_IRQ_BASE + 2) -#define REALTEK_CPU_IRQ_UART (MIPS_CPU_IRQ_BASE + 3) -#define REALTEK_CPU_IRQ_SWITCH (MIPS_CPU_IRQ_BASE + 4) -#define REALTEK_CPU_IRQ_SHARED1 (MIPS_CPU_IRQ_BASE + 5) -#define REALTEK_CPU_IRQ_EXTERNAL (MIPS_CPU_IRQ_BASE + 6) -#define REALTEK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) - -#define REG(x) (rtl83xx_ictl_base + x) - -extern struct rtl83xx_soc_info soc_info; - -static DEFINE_RAW_SPINLOCK(irq_lock); -static void __iomem *rtl83xx_ictl_base; - -static void rtl83xx_ictl_enable_irq(struct irq_data *i) -{ - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)); - value |= BIT(i->hwirq); - rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); -} - -static void rtl83xx_ictl_disable_irq(struct irq_data *i) -{ - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)); - value &= ~BIT(i->hwirq); - rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); -} - -static struct irq_chip rtl83xx_ictl_irq = { - .name = "RTL83xx", - .irq_enable = rtl83xx_ictl_enable_irq, - .irq_disable = rtl83xx_ictl_disable_irq, - .irq_ack = rtl83xx_ictl_disable_irq, - .irq_mask = rtl83xx_ictl_disable_irq, - .irq_unmask = rtl83xx_ictl_enable_irq, - .irq_eoi = rtl83xx_ictl_enable_irq, -}; - -static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -{ - irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq); - - return 0; -} - -static const struct irq_domain_ops irq_domain_ops = { - .map = intc_map, - .xlate = irq_domain_xlate_onecell, -}; - -static void rtl838x_irq_dispatch(struct irq_desc *desc) -{ - unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) & - rtl83xx_r32(REG(RTL83XX_ICTL_GISR)); - - if (pending) { - struct irq_domain *domain = irq_desc_get_handler_data(desc); - generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); - } else { - spurious_interrupt(); - } -} - -asmlinkage void plat_rtl83xx_irq_dispatch(void) -{ - unsigned int pending; - - pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(REALTEK_CPU_IRQ_COUNTER); - - else if (pending & CAUSEF_IP6) - do_IRQ(REALTEK_CPU_IRQ_EXTERNAL); - - else if (pending & CAUSEF_IP5) - do_IRQ(REALTEK_CPU_IRQ_SHARED1); - - else if (pending & CAUSEF_IP4) - do_IRQ(REALTEK_CPU_IRQ_SWITCH); - - else if (pending & CAUSEF_IP3) - do_IRQ(REALTEK_CPU_IRQ_UART); - - else if (pending & CAUSEF_IP2) - do_IRQ(REALTEK_CPU_IRQ_SHARED0); - - else - spurious_interrupt(); -} - -static int icu_setup_domain(struct device_node *node) -{ - struct irq_domain *domain; - - domain = irq_domain_add_simple(node, 32, 0, - &irq_domain_ops, NULL); - irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain); - irq_set_chained_handler_and_data(3, rtl838x_irq_dispatch, domain); - irq_set_chained_handler_and_data(4, rtl838x_irq_dispatch, domain); - irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain); - - rtl83xx_ictl_base = of_iomap(node, 0); - if (!rtl83xx_ictl_base) - return -EINVAL; - - return 0; -} - -static void __init rtl8380_icu_of_init(struct device_node *node, struct device_node *parent) -{ - if (icu_setup_domain(node)) - return; - - /* Disable all cascaded interrupts */ - rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR)); - - /* Set up interrupt routing */ - rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0)); - rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1)); - rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2)); - rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3)); - - /* Clear timer interrupt */ - write_c0_compare(0); - - /* Enable all CPU interrupts */ - write_c0_status(read_c0_status() | ST0_IM); - - /* Enable timer0 and uart0 interrupts */ - rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR)); -} - -static void __init rtl8390_icu_of_init(struct device_node *node, struct device_node *parent) -{ - if (icu_setup_domain(node)) - return; - - /* Disable all cascaded interrupts */ - rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR)); - - /* Set up interrupt routing */ - rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0)); - rtl83xx_w32(RTL8390_IRR1_SETTING, REG(RTL83XX_IRR1)); - rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2)); - rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3)); - - /* Clear timer interrupt */ - write_c0_compare(0); - - /* Enable all CPU interrupts */ - write_c0_status(read_c0_status() | ST0_IM); - - /* Enable timer0 and uart0 interrupts */ - rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR)); -} - -static void __init rtl9300_icu_of_init(struct device_node *node, struct device_node *parent) -{ - pr_info("RTL9300: Setting up IRQs\n"); - if (icu_setup_domain(node)) - return; - - /* Disable all cascaded interrupts */ - rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR)); - - /* Set up interrupt routing */ - rtl83xx_w32(RTL9300_IRR0_SETTING, REG(RTL83XX_IRR0)); - rtl83xx_w32(RTL9300_IRR1_SETTING, REG(RTL83XX_IRR1)); - rtl83xx_w32(RTL9300_IRR2_SETTING, REG(RTL83XX_IRR2)); - rtl83xx_w32(RTL9300_IRR3_SETTING, REG(RTL83XX_IRR3)); - - /* Clear timer interrupt */ - write_c0_compare(0); - - /* Enable all CPU interrupts */ - write_c0_status(read_c0_status() | ST0_IM); -} - -static struct of_device_id __initdata of_irq_ids[] = { - { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, - { .compatible = "realtek,rt8380-intc", .data = rtl8380_icu_of_init }, - { .compatible = "realtek,rt8390-intc", .data = rtl8390_icu_of_init }, - { .compatible = "realtek,rt9300-intc", .data = rtl9300_icu_of_init }, - {}, -}; - -void __init arch_init_irq(void) -{ - of_irq_init(of_irq_ids); -} diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c index ef97d485e1..752a856437 100644 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c +++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -193,3 +194,8 @@ void __init plat_time_init(void) mips_hpt_frequency = freq / 2; } + +void __init arch_init_irq(void) +{ + irqchip_init(); +} -- 2.30.2