From ae8578c0194695bd37435249dfed720769a6bbf3 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 27 Jan 2009 19:13:12 -0700 Subject: [PATCH] [ARM] OMAP: Make dpll4_m4_ck programmable with clk_set_rate() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Filling the set_rate and round_rate fields of dpll4_m4_ck makes this clock programmable through clk_set_rate(). This is needed to give omapfb control over the dss1_alwon_fck rate. This patch includes a fix from Tomi Valkeinen . linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and 9d211b761b3cdf7736602ecf7e68f8a298c13278. Signed-off-by: Måns Rullgård Signed-off-by: Tomi Valkeinen Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock34xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index c265cdcc86aa..65929cc37406 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -811,6 +811,8 @@ static struct clk dpll4_m4_ck = { .clksel = div16_dpll4_clksel, .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ -- 2.30.2