From a32a7708ae8b01c191768d503c1af33b85b369d0 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Mon, 25 Sep 2017 18:06:11 -0400 Subject: [PATCH] drm/amd/display: add option to disable DCC for DCC 128b request 1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 11 ++++++++--- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 18 ++++++++---------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 622488efa9e6..d7afbcfb33ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -56,11 +56,10 @@ struct dc_caps { uint32_t max_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; - unsigned int max_cursor_size; + bool dcc_const_color; }; - struct dc_dcc_surface_param { struct dc_size surface_size; enum surface_pixel_format format; @@ -162,6 +161,12 @@ struct dc_config { bool disable_disp_pll_sharing; }; +enum dcc_option { + DCC_ENABLE = 0, + DCC_DISABLE = 1, + DCC_HALF_REQ_DISALBE = 2, +}; + enum pipe_split_policy { MPC_SPLIT_DYNAMIC = 0, MPC_SPLIT_AVOID = 1, @@ -177,7 +182,7 @@ struct dc_debug { bool clock_trace; bool validation_trace; bool disable_stutter; - bool disable_dcc; + enum dcc_option disable_dcc; bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index bd7c86e5800e..30c275e05796 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -414,7 +414,6 @@ static const struct resource_caps res_cap = { }; static const struct dc_debug debug_defaults_drv = { - .disable_dcc = false, .sanity_checks = true, .disable_dmcu = true, .force_abm_enable = false, @@ -428,6 +427,7 @@ static const struct dc_debug debug_defaults_drv = { .use_dml_wm = false, .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, + .disable_dcc = DCC_ENABLE, }; static const struct dc_debug debug_defaults_diags = { @@ -1080,7 +1080,7 @@ static bool get_dcc_compression_cap(const struct dc *dc, memset(output, 0, sizeof(*output)); - if (dc->debug.disable_dcc) + if (dc->debug.disable_dcc == DCC_DISABLE) return false; if (!dcc_support_pixel_format(input->format, @@ -1124,32 +1124,30 @@ static bool get_dcc_compression_cap(const struct dc *dc, dcc_control = dcc_control__128_128_xxx; } + if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && + dcc_control != dcc_control__256_256_xxx) + return false; + switch (dcc_control) { case dcc_control__256_256_xxx: output->grph.rgb.max_uncompressed_blk_size = 256; output->grph.rgb.max_compressed_blk_size = 256; output->grph.rgb.independent_64b_blks = false; - output->capable = true; - output->const_color_support = false; break; case dcc_control__128_128_xxx: output->grph.rgb.max_uncompressed_blk_size = 128; output->grph.rgb.max_compressed_blk_size = 128; output->grph.rgb.independent_64b_blks = false; - /*temp: not allow dcc on high res*/ - output->capable = false; - output->const_color_support = false; break; case dcc_control__256_64_64: output->grph.rgb.max_uncompressed_blk_size = 256; output->grph.rgb.max_compressed_blk_size = 64; output->grph.rgb.independent_64b_blks = true; - /*temp: not allow dcc on high res*/ - output->capable = false; - output->const_color_support = false; break; } + output->capable = true; + output->const_color_support = false; return true; } -- 2.30.2