From a1584957ffe17a43fb6b6a825187bc01b4fa22bd Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 9 Oct 2018 16:46:53 -0400 Subject: [PATCH] drm/amdgpu/vcn:Move SPG mode mc resume after MPC control Move Static Power Gate mode mc resume after MPC control Signed-off-by: James Zhu Acked-by: Leo Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 29f711b57506..3275eaff6fba 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -780,8 +780,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) /* disable clock gating */ vcn_v1_0_disable_clock_gating(adev); - vcn_v1_0_mc_resume_spg_mode(adev); - /* disable interupt */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, ~UVD_MASTINT_EN__VCPU_EN_MASK); @@ -840,6 +838,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); + vcn_v1_0_mc_resume_spg_mode(adev); + /* take all subblocks out of reset, except VCPU */ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); -- 2.30.2