From 9e4066748bf7bf13b04312f9b1c42d2a6cc77f66 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Mon, 25 Nov 2019 14:59:05 +0100 Subject: [PATCH] clk: qcom: hfpll: register as clock provider Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd Link: https://lkml.kernel.org/r/20191125135910.679310-4-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd --- drivers/clk/qcom/hfpll.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index a6de7101430c..e64c0fd82fe4 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -57,6 +57,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) .num_parents = 1, .ops = &clk_ops_hfpll, }; + int ret; h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); if (!h) @@ -79,7 +80,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev) h->clkr.hw.init = &init; spin_lock_init(&h->lock); - return devm_clk_register_regmap(&pdev->dev, &h->clkr); + ret = devm_clk_register_regmap(dev, &h->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &h->clkr.hw); } static struct platform_driver qcom_hfpll_driver = { -- 2.30.2