From 9dc8fef2583f23ca6a99c6f5e709a8b80018364f Mon Sep 17 00:00:00 2001 From: Mike Dunn Date: Fri, 21 Jun 2013 09:12:28 -0700 Subject: [PATCH] pxa: fix memory coherency problem after relocation On the xscale, the icache must be invalidated and the write buffers drained after writing code over the data bus, even if the caches are disabled. Tested on the pxa270. Signed-off-by: Mike Dunn --- arch/arm/lib/relocate.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 949b9e8025..cd2bab6cde 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -70,6 +70,15 @@ fixnext: relocate_done: +#ifdef __XSCALE__ + /* + * On xscale, icache must be invalidated and write buffers drained, + * even with cache disabled - 4.2.7 of xscale core developer's manual + */ + mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ +#endif + /* ARMv4- don't know bx lr but the assembler fails to see that */ #ifdef __ARM_ARCH_4__ -- 2.30.2