From 9c54ea95852a920720868d0e18bb4e9d645ea007 Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 11 Sep 2007 15:24:12 -0700 Subject: [PATCH] Subject: [PATCH] Intel FB pixel clock calculation fix Intel framebuffer mis-calculated pixel clocks. The pixel clock (and thus both H and V sync) will be slower than requested, so if you set the minimum allowed the display may not sync. In case of really old CRT display it could theoretically damage it. I'm using it with PAL TV (using RGB input - SCART connector) and the bug prevented it from working at all (TV requirements are more strict and made the bug visible). Signed-off-by: Krzysztof Halasa Cc: "Antonino A. Daplas" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/intelfb/intelfbhw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c index 16bc8d75e36e..b21d0dec9283 100644 --- a/drivers/video/intelfb/intelfbhw.c +++ b/drivers/video/intelfb/intelfbhw.c @@ -924,10 +924,10 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re if (m > pll->max_m) m = pll->max_m - 1; for (testm = m - 1; testm <= m; testm++) { - f_out = calc_vclock3(index, m, n, p); + f_out = calc_vclock3(index, testm, n, p); if (splitm(index, testm, &m1, &m2)) { - WRN_MSG("cannot split m = %d\n", m); - n++; + WRN_MSG("cannot split m = %d\n", + testm); continue; } if (clock > f_out) -- 2.30.2