From 9801d61c4a1f63cd3ca540f88814f195094d8c35 Mon Sep 17 00:00:00 2001 From: Serge Vasilugin Date: Mon, 16 Mar 2020 16:28:38 +0800 Subject: [PATCH] kernel: rtl8367b: add configuration for extif2 Both rtl8367b and rtl8367s have two extended interface rtl8367rb: 5 port + 2*RGMII/MII rtl8367s: 5 port + SGMII/HSGMI + RGMII/MII (?)rtl8367sb: 5 port + 2*RGMII/MII These interfaces correspond to EXT1 and EXT2 (ports 6 and 7 respectivly). This patch allow to configure EXT2 in dts-file: rtl8367rb { compatible = "realtek,rtl8367b"; cpu_port = <7>; realtek,extif2 = <1 0 1 1 1 1 1 1 2>; mii-bus = <&mdio0>; phy_id = <29>; }; Signed-off-by: Serge Vasilugin [fix indent, replace magic value, alter commit message] Signed-off-by: Chuanhong Guo --- .../generic/files/drivers/net/phy/rtl8367b.c | 47 +++++++++++++++++-- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index ede8b21a64..e7fe79302a 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -148,19 +148,36 @@ GENMASK(2 + (_x) * 8, (_x) * 8) #define RTL8367B_DEBUG1_DP_SHIFT(_x) ((_x) * 8) +#define RTL8367B_CHIP_DEBUG2_REG 0x13e2 +#define RTL8367B_DEBUG2_RG2_DN_MASK GENMASK(8, 6) +#define RTL8367B_DEBUG2_RG2_DN_SHIFT 6 +#define RTL8367B_DEBUG2_RG2_DP_MASK GENMASK(5, 3) +#define RTL8367B_DEBUG2_RG2_DP_SHIFT 3 +#define RTL8367B_DEBUG2_DRI_EXT2_RG BIT(2) +#define RTL8367B_DEBUG2_DRI_EXT2 BIT(1) +#define RTL8367B_DEBUG2_SLR_EXT2 BIT(0) + #define RTL8367B_DIS_REG 0x1305 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x)) #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x)) #define RTL8367B_DIS_RGMII_MASK 0x7 -#define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x)) +#define RTL8367B_DIS2_REG 0x13c3 +#define RTL8367B_DIS2_SKIP_MII_RXER_SHIFT 4 +#define RTL8367B_DIS2_SKIP_MII_RXER 0x10 +#define RTL8367B_DIS2_RGMII_SHIFT 0 +#define RTL8367B_DIS2_RGMII_MASK 0xf + +#define RTL8367B_EXT_RGMXF_REG(_x) \ + ((_x) == 2 ? 0x13c5 : 0x1306 + (_x)) #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7 -#define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x)) +#define RTL8367B_DI_FORCE_REG(_x) \ + ((_x) == 2 ? 0x13c4 : 0x1310 + (_x)) #define RTL8367B_DI_FORCE_MODE BIT(12) #define RTL8367B_DI_FORCE_NWAY BIT(7) #define RTL8367B_DI_FORCE_TXPAUSE BIT(6) @@ -780,6 +797,17 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, RTL8367B_DEBUG1_DP_MASK(id), (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) | (7 << RTL8367B_DEBUG1_DP_SHIFT(id))); + } else { + REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG, + RTL8367B_DEBUG2_DRI_EXT2 | + RTL8367B_DEBUG2_DRI_EXT2_RG | + RTL8367B_DEBUG2_SLR_EXT2 | + RTL8367B_DEBUG2_RG2_DN_MASK | + RTL8367B_DEBUG2_RG2_DP_MASK, + RTL8367B_DEBUG2_DRI_EXT2_RG | + RTL8367B_DEBUG2_SLR_EXT2 | + (7 << RTL8367B_DEBUG2_RG2_DN_SHIFT) | + (7 << RTL8367B_DEBUG2_RG2_DP_SHIFT)); } break; @@ -810,9 +838,14 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, return -EINVAL; } - REG_RMW(smi, RTL8367B_DIS_REG, - RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id), - mode << RTL8367B_DIS_RGMII_SHIFT(id)); + if (id <= 1) + REG_RMW(smi, RTL8367B_DIS_REG, + RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id), + mode << RTL8367B_DIS_RGMII_SHIFT(id)); + else + REG_RMW(smi, RTL8367B_DIS2_REG, + RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT, + mode << RTL8367B_DIS2_RGMII_SHIFT); return 0; } @@ -956,6 +989,10 @@ static int rtl8367b_setup(struct rtl8366_smi *smi) err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1"); if (err) return err; + + err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2"); + if (err) + return err; } else { err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg); if (err) -- 2.30.2