From 901bda1b936ca9bceb6ae9f9ff192a1d871e6393 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 15 Nov 2008 23:15:58 +0000 Subject: [PATCH] Add 2.6.27 support to rb532, nand is not recognized, needs to be sorted out SVN-Revision: 13224 --- target/linux/rb532/config-2.6.27 | 244 ++++++ .../rb532/patches-2.6.27/001-git_diffs.patch | 743 ++++++++++++++++++ .../patches-2.6.27/002-pci_io_map_base.patch | 42 + .../patches-2.6.27/003-gpio_bit_setting.patch | 35 + .../004-fix_pata_rb532_cf.patch | 84 ++ .../005-pata_rb532_cf_4bytes_rw.patch | 68 ++ .../006-pata_rb532_cf_fix_prototype.patch | 35 + .../patches-2.6.27/007-cmdline_hack.patch | 15 + .../patches-2.6.27/008-korina_fixes.patch | 245 ++++++ .../patches-2.6.27/009-rc32434_res_name.patch | 12 + 10 files changed, 1523 insertions(+) create mode 100644 target/linux/rb532/config-2.6.27 create mode 100644 target/linux/rb532/patches-2.6.27/001-git_diffs.patch create mode 100644 target/linux/rb532/patches-2.6.27/002-pci_io_map_base.patch create mode 100644 target/linux/rb532/patches-2.6.27/003-gpio_bit_setting.patch create mode 100644 target/linux/rb532/patches-2.6.27/004-fix_pata_rb532_cf.patch create mode 100644 target/linux/rb532/patches-2.6.27/005-pata_rb532_cf_4bytes_rw.patch create mode 100644 target/linux/rb532/patches-2.6.27/006-pata_rb532_cf_fix_prototype.patch create mode 100644 target/linux/rb532/patches-2.6.27/007-cmdline_hack.patch create mode 100644 target/linux/rb532/patches-2.6.27/008-korina_fixes.patch create mode 100644 target/linux/rb532/patches-2.6.27/009-rc32434_res_name.patch diff --git a/target/linux/rb532/config-2.6.27 b/target/linux/rb532/config-2.6.27 new file mode 100644 index 0000000000..8fd10702d9 --- /dev/null +++ b/target/linux/rb532/config-2.6.27 @@ -0,0 +1,244 @@ +CONFIG_32BIT=y +# CONFIG_64BIT is not set +# CONFIG_8139TOO is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_PIIX is not set +CONFIG_ATA_SFF=y +# CONFIG_ATM is not set +# CONFIG_AX25 is not set +CONFIG_BASE_SMALL=0 +# CONFIG_BCM47XX is not set +CONFIG_BITREVERSE=y +CONFIG_BOOT_RAW=y +# CONFIG_BT is not set +CONFIG_CEVT_R4K=y +CONFIG_CLASSIC_RCU=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR1=y +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_VR41XX is not set +CONFIG_CSRC_R4K=y +# CONFIG_DEBUG_FS is not set +CONFIG_DEVPORT=y +# CONFIG_DM9000 is not set +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_EXT2_FS=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_SYSFS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_CLK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_IDE=y +# CONFIG_HAVE_IOREMAP_PROT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_I2C is not set +# CONFIG_IDE is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_KEXEC=y +CONFIG_KMOD=y +CONFIG_KORINA=y +# CONFIG_LEDS_ALIX is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_TMIO is not set +CONFIG_MIKROTIK_RB532=y +CONFIG_MINI_FO=m +CONFIG_MIPS=y +# CONFIG_MIPS_COBALT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=4 +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MISDN is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=3 +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_START=0x8000000 +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_NATSEMI is not set +# CONFIG_NET_SCH_ESFQ_NFCT is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CT_ACCT=y +# CONFIG_NO_IOPORT is not set +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PAGE_SIZE_16KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_RB532=y +# CONFIG_PATA_SCH is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCSPKR_PLATFORM=y +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_R6040 is not set +CONFIG_RC32434_WDT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RTC_LIB=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCSI=y +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SOUND is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SSB_POSSIBLE=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +# CONFIG_TC35815 is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_TICK_ONESHOT is not set +CONFIG_TRAD_SIGNALS=y +# CONFIG_VGASTATE is not set +CONFIG_VIA_RHINE=y +# CONFIG_VIA_RHINE_MMIO is not set +CONFIG_VIDEO_MEDIA=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_COMMON=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/rb532/patches-2.6.27/001-git_diffs.patch b/target/linux/rb532/patches-2.6.27/001-git_diffs.patch new file mode 100644 index 0000000000..d6c244b294 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/001-git_diffs.patch @@ -0,0 +1,743 @@ +diff -urN a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c +--- a/arch/mips/rb532/devices.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/devices.c 2008-11-15 17:43:28.000000000 +0100 +@@ -34,21 +34,11 @@ + #include + #include + #include +- +-#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) +-#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) +-#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) +-#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) ++#include + + #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) + #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) + +-/* NAND definitions */ +-#define GPIO_RDY (1 << 0x08) +-#define GPIO_WPX (1 << 0x09) +-#define GPIO_ALE (1 << 0x0a) +-#define GPIO_CLE (1 << 0x0b) +- + static struct resource korina_dev0_res[] = { + { + .name = "korina_regs", +@@ -94,15 +84,13 @@ + }; + + static struct platform_device korina_dev0 = { +- .id = 0, ++ .id = -1, + .name = "korina", + .dev.platform_data = &korina_dev0_data, + .resource = korina_dev0_res, + .num_resources = ARRAY_SIZE(korina_dev0_res), + }; + +-#define CF_GPIO_NUM 13 +- + static struct resource cf_slot0_res[] = { + { + .name = "cf_membase", +@@ -116,11 +104,11 @@ + }; + + static struct cf_device cf_slot0_data = { +- .gpio_pin = 13 ++ .gpio_pin = CF_GPIO_NUM + }; + + static struct platform_device cf_slot0 = { +- .id = 0, ++ .id = -1, + .name = "pata-rb532-cf", + .dev.platform_data = &cf_slot0_data, + .resource = cf_slot0_res, +@@ -130,7 +118,7 @@ + /* Resources and device for NAND */ + static int rb532_dev_ready(struct mtd_info *mtd) + { +- return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; ++ return gpio_get_value(GPIO_RDY); + } + + static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +@@ -185,7 +173,7 @@ + + static struct platform_device rb532_led = { + .name = "rb532-led", +- .id = 0, ++ .id = -1, + }; + + static struct gpio_keys_button rb532_gpio_btn[] = { +@@ -292,7 +280,7 @@ + { + /* Look for the CF card reader */ + if (!readl(IDT434_REG_BASE + DEV1MASK)) +- rb532_devs[1] = NULL; ++ rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ + else { + cf_slot0_res[0].start = + readl(IDT434_REG_BASE + DEV1BASE); +diff -urN a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c +--- a/arch/mips/rb532/gpio.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/gpio.c 2008-11-15 17:43:28.000000000 +0100 +@@ -27,28 +27,27 @@ + */ + + #include +-#include + #include + #include +-#include + #include +-#include + #include +- +-#include ++#include + + #include ++#include + +-struct rb532_gpio_reg __iomem *rb532_gpio_reg0; +-EXPORT_SYMBOL(rb532_gpio_reg0); ++struct rb532_gpio_chip { ++ struct gpio_chip chip; ++ void __iomem *regbase; ++}; + + struct mpmc_device dev3; + + static struct resource rb532_gpio_reg0_res[] = { + { + .name = "gpio_reg0", +- .start = (u32)(IDT434_REG_BASE + GPIOBASE), +- .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)), ++ .start = REGBASE + GPIOBASE, ++ .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1, + .flags = IORESOURCE_MEM, + } + }; +@@ -56,8 +55,8 @@ + static struct resource rb532_dev3_ctl_res[] = { + { + .name = "dev3_ctl", +- .start = (u32)(IDT434_REG_BASE + DEV3BASE), +- .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)), ++ .start = REGBASE + DEV3BASE, ++ .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1, + .flags = IORESOURCE_MEM, + } + }; +@@ -70,7 +69,7 @@ + + spin_lock_irqsave(&dev3.lock, flags); + +- data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs); ++ data = readl(IDT434_REG_BASE + reg_offs); + for (i = 0; i != len; ++i) { + if (val & (1 << i)) + data |= (1 << (i + bit)); +@@ -108,114 +107,166 @@ + } + EXPORT_SYMBOL(get_latch_u5); + +-int rb532_gpio_get_value(unsigned gpio) ++/* rb532_set_bit - sanely set a bit ++ * ++ * bitval: new value for the bit ++ * offset: bit index in the 4 byte address range ++ * ioaddr: 4 byte aligned address being altered ++ */ ++static inline void rb532_set_bit(unsigned bitval, ++ unsigned offset, void __iomem *ioaddr) + { +- return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio); +-} +-EXPORT_SYMBOL(rb532_gpio_get_value); ++ unsigned long flags; ++ u32 val; + +-void rb532_gpio_set_value(unsigned gpio, int value) +-{ +- unsigned tmp; ++ bitval = !!bitval; /* map parameter to {0,1} */ ++ ++ local_irq_save(flags); + +- tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio); +- if (value) +- tmp |= 1 << gpio; ++ val = readl(ioaddr); ++ val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ ++ val |= ( bitval << offset ); /* set bit if bitval == 1 */ ++ writel(val, ioaddr); + +- writel(tmp, (void *)&rb532_gpio_reg0->gpiod); ++ local_irq_restore(flags); + } +-EXPORT_SYMBOL(rb532_gpio_set_value); + +-int rb532_gpio_direction_input(unsigned gpio) ++/* rb532_get_bit - read a bit ++ * ++ * returns the boolean state of the bit, which may be > 1 ++ */ ++static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) + { +- writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio), +- (void *)&rb532_gpio_reg0->gpiocfg); +- +- return 0; ++ return (readl(ioaddr) & (1 << offset)); + } +-EXPORT_SYMBOL(rb532_gpio_direction_input); + +-int rb532_gpio_direction_output(unsigned gpio, int value) ++/* ++ * Return GPIO level */ ++static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) + { +- gpio_set_value(gpio, value); +- writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio), +- (void *)&rb532_gpio_reg0->gpiocfg); ++ struct rb532_gpio_chip *gpch; + +- return 0; ++ gpch = container_of(chip, struct rb532_gpio_chip, chip); ++ return rb532_get_bit(offset, gpch->regbase + GPIOD); + } +-EXPORT_SYMBOL(rb532_gpio_direction_output); + +-void rb532_gpio_set_int_level(unsigned gpio, int value) ++/* ++ * Set output GPIO level ++ */ ++static void rb532_gpio_set(struct gpio_chip *chip, ++ unsigned offset, int value) + { +- unsigned tmp; ++ struct rb532_gpio_chip *gpch; + +- tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio); +- if (value) +- tmp |= 1 << gpio; +- writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel); ++ gpch = container_of(chip, struct rb532_gpio_chip, chip); ++ rb532_set_bit(value, offset, gpch->regbase + GPIOD); + } +-EXPORT_SYMBOL(rb532_gpio_set_int_level); + +-int rb532_gpio_get_int_level(unsigned gpio) ++/* ++ * Set GPIO direction to input ++ */ ++static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) + { +- return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio); ++ struct rb532_gpio_chip *gpch; ++ ++ gpch = container_of(chip, struct rb532_gpio_chip, chip); ++ ++ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) ++ return 1; /* alternate function, GPIOCFG is ignored */ ++ ++ rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); ++ return 0; + } +-EXPORT_SYMBOL(rb532_gpio_get_int_level); + +-void rb532_gpio_set_int_status(unsigned gpio, int value) ++/* ++ * Set GPIO direction to output ++ */ ++static int rb532_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) + { +- unsigned tmp; ++ struct rb532_gpio_chip *gpch; ++ ++ gpch = container_of(chip, struct rb532_gpio_chip, chip); + +- tmp = readl(&rb532_gpio_reg0->gpioistat); +- if (value) +- tmp |= 1 << gpio; +- writel(tmp, (void *)&rb532_gpio_reg0->gpioistat); ++ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) ++ return 1; /* alternate function, GPIOCFG is ignored */ ++ ++ /* set the initial output value */ ++ rb532_set_bit(value, offset, gpch->regbase + GPIOD); ++ ++ rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); ++ return 0; + } +-EXPORT_SYMBOL(rb532_gpio_set_int_status); + +-int rb532_gpio_get_int_status(unsigned gpio) ++static struct rb532_gpio_chip rb532_gpio_chip[] = { ++ [0] = { ++ .chip = { ++ .label = "gpio0", ++ .direction_input = rb532_gpio_direction_input, ++ .direction_output = rb532_gpio_direction_output, ++ .get = rb532_gpio_get, ++ .set = rb532_gpio_set, ++ .base = 0, ++ .ngpio = 32, ++ }, ++ }, ++}; ++ ++/* ++ * Set GPIO interrupt level ++ */ ++void rb532_gpio_set_ilevel(int bit, unsigned gpio) + { +- return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio); ++ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); + } +-EXPORT_SYMBOL(rb532_gpio_get_int_status); ++EXPORT_SYMBOL(rb532_gpio_set_ilevel); + +-void rb532_gpio_set_func(unsigned gpio, int value) ++/* ++ * Set GPIO interrupt status ++ */ ++void rb532_gpio_set_istat(int bit, unsigned gpio) + { +- unsigned tmp; +- +- tmp = readl(&rb532_gpio_reg0->gpiofunc); +- if (value) +- tmp |= 1 << gpio; +- writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc); ++ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); + } +-EXPORT_SYMBOL(rb532_gpio_set_func); ++EXPORT_SYMBOL(rb532_gpio_set_istat); + +-int rb532_gpio_get_func(unsigned gpio) ++/* ++ * Configure GPIO alternate function ++ */ ++static void rb532_gpio_set_func(int bit, unsigned gpio) + { +- return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio); ++ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); + } +-EXPORT_SYMBOL(rb532_gpio_get_func); + + int __init rb532_gpio_init(void) + { +- rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start, +- rb532_gpio_reg0_res[0].end - +- rb532_gpio_reg0_res[0].start); ++ struct resource *r; ++ ++ r = rb532_gpio_reg0_res; ++ rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start); + +- if (!rb532_gpio_reg0) { ++ if (!rb532_gpio_chip->regbase) { + printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); + return -ENXIO; + } + +- dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, +- rb532_dev3_ctl_res[0].end - +- rb532_dev3_ctl_res[0].start); ++ /* Register our GPIO chip */ ++ gpiochip_add(&rb532_gpio_chip->chip); ++ ++ r = rb532_dev3_ctl_res; ++ dev3.base = ioremap_nocache(r->start, r->end - r->start); + + if (!dev3.base) { + printk(KERN_ERR "rb532: cannot remap device controller 3\n"); + return -ENXIO; + } + ++ /* configure CF_GPIO_NUM as CFRDY IRQ source */ ++ rb532_gpio_set_func(0, CF_GPIO_NUM); ++ rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); ++ rb532_gpio_set_ilevel(1, CF_GPIO_NUM); ++ rb532_gpio_set_istat(0, CF_GPIO_NUM); ++ + return 0; + } + arch_initcall(rb532_gpio_init); +diff -urN a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c +--- a/arch/mips/rb532/irq.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/irq.c 2008-11-15 17:43:28.000000000 +0100 +@@ -45,7 +45,7 @@ + #include + #include + +-#include ++#include + + struct intr_group { + u32 mask; /* mask of valid bits in pending/mask registers */ +diff -urN a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c +--- a/arch/mips/rb532/prom.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/prom.c 2008-11-15 17:43:28.000000000 +0100 +@@ -37,12 +37,8 @@ + #include + #include + +-extern void __init setup_serial_port(void); +- + unsigned int idt_cpu_freq = 132000000; + EXPORT_SYMBOL(idt_cpu_freq); +-unsigned int gpio_bootup_state; +-EXPORT_SYMBOL(gpio_bootup_state); + + static struct resource ddr_reg[] = { + { +@@ -108,9 +104,6 @@ + mips_machtype = MACH_MIKROTIK_RB532; + } + +- if (match_tag(prom_argv[i], GPIO_TAG)) +- gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG); +- + strcpy(cp, prom_argv[i]); + cp += strlen(prom_argv[i]); + } +@@ -122,11 +115,6 @@ + strcpy(cp, arcs_cmdline); + cp += strlen(arcs_cmdline); + } +- if (gpio_bootup_state & 0x02) +- strcpy(cp, GPIO_INIT_NOBUTTON); +- else +- strcpy(cp, GPIO_INIT_BUTTON); +- + cmd_line[CL_SIZE-1] = '\0'; + + strcpy(arcs_cmdline, cmd_line); +diff -urN a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c +--- a/arch/mips/rb532/serial.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/serial.c 2008-11-15 17:43:28.000000000 +0100 +@@ -31,16 +31,16 @@ + #include + + #include +-#include ++#include + + extern unsigned int idt_cpu_freq; + + static struct uart_port rb532_uart = { + .type = PORT_16550A, + .line = 0, +- .irq = RC32434_UART0_IRQ, ++ .irq = UART0_IRQ, + .iotype = UPIO_MEM, +- .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE), ++ .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), + .regshift = 2 + }; + +diff -urN a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c +--- a/arch/mips/rb532/setup.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/setup.c 2008-11-15 17:43:28.000000000 +0100 +@@ -9,7 +9,7 @@ + #include + #include + +-#include ++#include + #include + + struct pci_reg __iomem *pci_reg; +@@ -27,7 +27,7 @@ + static void rb_machine_restart(char *command) + { + /* just jump to the reset vector */ +- writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST)); ++ writel(0x80000001, IDT434_REG_BASE + RST); + ((void (*)(void)) KSEG1ADDR(0x1FC00000u))(); + } + +diff -urN a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c +--- a/arch/mips/rb532/time.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/rb532/time.c 2008-11-15 17:43:28.000000000 +0100 +@@ -28,7 +28,6 @@ + #include + + #include +-#include + #include + #include + +diff -urN linux-2.6.27.5/arch/mips/Kconfig linux-2.6.27.5.new/arch/mips/Kconfig +--- linux-2.6.27.5/arch/mips/Kconfig 2008-11-07 18:55:34.000000000 +0100 ++++ linux-2.6.27.5.new/arch/mips/Kconfig 2008-11-15 17:50:42.000000000 +0100 +@@ -568,7 +568,7 @@ + select SYS_SUPPORTS_LITTLE_ENDIAN + select SWAP_IO_SPACE + select BOOT_RAW +- select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB + help + Support the Mikrotik(tm) RouterBoard 532 series, + based on the IDT RC32434 SoC. +diff -urN a/include/asm-mips/mach-rc32434/gpio.h b/include-mips/asm/mach-rc32434/gpio.h +--- a/include/asm-mips/mach-rc32434/gpio.h 2008-11-07 18:55:34.000000000 +0100 ++++ b/include/asm-mips/mach-rc32434/gpio.h 2008-11-15 17:43:28.000000000 +0100 +@@ -14,6 +14,16 @@ + #define _RC32434_GPIO_H_ + + #include ++#include ++ ++#define NR_BUILTIN_GPIO 32 ++ ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value ++#define gpio_cansleep __gpio_cansleep ++ ++#define gpio_to_irq(gpio) (8 + 4 * 32 + gpio) ++#define irq_to_gpio(irq) (irq - (8 + 4 * 32)) + + struct rb532_gpio_reg { + u32 gpiofunc; /* GPIO Function Register +@@ -61,66 +71,20 @@ + /* PCI messaging unit */ + #define RC32434_PCI_MSU_GPIO (1 << 13) + ++/* NAND GPIO signals */ ++#define GPIO_RDY 8 ++#define GPIO_WPX 9 ++#define GPIO_ALE 10 ++#define GPIO_CLE 11 ++ ++/* Compact Flash GPIO pin */ ++#define CF_GPIO_NUM 13 + + extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); + extern unsigned get_434_reg(unsigned reg_offs); + extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); + extern unsigned char get_latch_u5(void); +- +-extern int rb532_gpio_get_value(unsigned gpio); +-extern void rb532_gpio_set_value(unsigned gpio, int value); +-extern int rb532_gpio_direction_input(unsigned gpio); +-extern int rb532_gpio_direction_output(unsigned gpio, int value); +-extern void rb532_gpio_set_int_level(unsigned gpio, int value); +-extern int rb532_gpio_get_int_level(unsigned gpio); +-extern void rb532_gpio_set_int_status(unsigned gpio, int value); +-extern int rb532_gpio_get_int_status(unsigned gpio); +- +- +-/* Wrappers for the arch-neutral GPIO API */ +- +-static inline int gpio_request(unsigned gpio, const char *label) +-{ +- /* Not yet implemented */ +- return 0; +-} +- +-static inline void gpio_free(unsigned gpio) +-{ +- /* Not yet implemented */ +-} +- +-static inline int gpio_direction_input(unsigned gpio) +-{ +- return rb532_gpio_direction_input(gpio); +-} +- +-static inline int gpio_direction_output(unsigned gpio, int value) +-{ +- return rb532_gpio_direction_output(gpio, value); +-} +- +-static inline int gpio_get_value(unsigned gpio) +-{ +- return rb532_gpio_get_value(gpio); +-} +- +-static inline void gpio_set_value(unsigned gpio, int value) +-{ +- rb532_gpio_set_value(gpio, value); +-} +- +-static inline int gpio_to_irq(unsigned gpio) +-{ +- return gpio; +-} +- +-static inline int irq_to_gpio(unsigned irq) +-{ +- return irq; +-} +- +-/* For cansleep */ +-#include ++extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); ++extern void rb532_gpio_set_istat(int bit, unsigned gpio); + + #endif /* _RC32434_GPIO_H_ */ +diff -urN a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h +--- a/include/asm-mips/mach-rc32434/irq.h 2008-11-07 18:55:34.000000000 +0100 ++++ b/include/asm-mips/mach-rc32434/irq.h 2008-11-15 17:43:28.000000000 +0100 +@@ -4,5 +4,30 @@ + #define NR_IRQS 256 + + #include ++#include ++ ++/* Interrupt Controller */ ++#define IC_GROUP0_PEND (REGBASE + 0x38000) ++#define IC_GROUP0_MASK (REGBASE + 0x38008) ++#define IC_GROUP_OFFSET 0x0C ++ ++#define NUM_INTR_GROUPS 5 ++ ++/* 16550 UARTs */ ++#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ ++ /* GRP3 IRQ numbers start here */ ++#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) ++ /* GRP4 IRQ numbers start here */ ++#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) ++ /* GRP5 IRQ numbers start here */ ++#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) ++#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) ++ ++#define UART0_IRQ (GROUP3_IRQ_BASE + 0) ++ ++#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) ++#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) ++#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) ++#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) + + #endif /* __ASM_RC32434_IRQ_H */ +diff -urN a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h +--- a/include/asm-mips/mach-rc32434/prom.h 2008-11-07 18:55:34.000000000 +0100 ++++ b/include/asm-mips/mach-rc32434/prom.h 2008-11-15 17:43:28.000000000 +0100 +@@ -28,14 +28,10 @@ + + #define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8)) + +-#define GPIO_INIT_NOBUTTON "" +-#define GPIO_INIT_BUTTON " 2" +- + #define SR_NMI 0x00180000 + #define SERIAL_SPEED_ENTRY 0x00000001 + + #define FREQ_TAG "HZ=" +-#define GPIO_TAG "gpio=" + #define KMAC_TAG "kmac=" + #define MEM_TAG "mem=" + #define BOARD_TAG "board=" +diff -urN a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h +--- a/include/asm-mips/mach-rc32434/rb.h 2008-11-07 18:55:34.000000000 +0100 ++++ b/include/asm-mips/mach-rc32434/rb.h 2008-11-15 17:43:28.000000000 +0100 +@@ -17,7 +17,10 @@ + + #include + +-#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000)) ++#define REGBASE 0x18000000 ++#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) ++#define UART0BASE 0x58000 ++#define RST (1 << 15) + #define DEV0BASE 0x010000 + #define DEV0MASK 0x010004 + #define DEV0C 0x010008 +@@ -37,12 +40,14 @@ + #define BTCS 0x010040 + #define BTCOMPARE 0x010044 + #define GPIOBASE 0x050000 +-#define GPIOCFG 0x050004 +-#define GPIOD 0x050008 +-#define GPIOILEVEL 0x05000C +-#define GPIOISTAT 0x050010 +-#define GPIONMIEN 0x050014 +-#define IMASK6 0x038038 ++/* Offsets relative to GPIOBASE */ ++#define GPIOFUNC 0x00 ++#define GPIOCFG 0x04 ++#define GPIOD 0x08 ++#define GPIOILEVEL 0x0C ++#define GPIOISTAT 0x10 ++#define GPIONMIEN 0x14 ++#define IMASK6 0x38 + #define LO_WPX (1 << 0) + #define LO_ALE (1 << 1) + #define LO_CLE (1 << 2) +diff -urN a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h +--- a/include/asm-mips/mach-rc32434/rc32434.h 2008-11-07 18:55:34.000000000 +0100 ++++ b/include/asm-mips/mach-rc32434/rc32434.h 2008-11-15 17:43:28.000000000 +0100 +@@ -8,37 +8,7 @@ + #include + #include + +-#define RC32434_REG_BASE 0x18000000 +-#define RC32434_RST (1 << 15) +- + #define IDT_CLOCK_MULT 2 +-#define MIPS_CPU_TIMER_IRQ 7 +- +-/* Interrupt Controller */ +-#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000) +-#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008) +-#define IC_GROUP_OFFSET 0x0C +- +-#define NUM_INTR_GROUPS 5 +- +-/* 16550 UARTs */ +-#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ +- /* GRP3 IRQ numbers start here */ +-#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) +- /* GRP4 IRQ numbers start here */ +-#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) +- /* GRP5 IRQ numbers start here */ +-#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) +-#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) +- +- +-#ifdef __MIPSEB__ +-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003) +-#else +-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000) +-#endif +- +-#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0) + + /* cpu pipeline flush */ + static inline void rc32434_sync(void) +@@ -46,16 +16,4 @@ + __asm__ volatile ("sync"); + } + +-static inline void rc32434_sync_udelay(int us) +-{ +- __asm__ volatile ("sync"); +- udelay(us); +-} +- +-static inline void rc32434_sync_delay(int ms) +-{ +- __asm__ volatile ("sync"); +- mdelay(ms); +-} +- + #endif /* _ASM_RC32434_RC32434_H_ */ +--- a/arch/mips/pci/fixup-rc32434.c 2008-11-07 18:55:34.000000000 +0100 ++++ b/arch/mips/pci/fixup-rc32434.c 2008-11-15 17:43:28.000000000 +0100 +@@ -30,6 +30,7 @@ + #include + + #include ++#include + + static int __devinitdata irq_map[2][12] = { + {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1}, diff --git a/target/linux/rb532/patches-2.6.27/002-pci_io_map_base.patch b/target/linux/rb532/patches-2.6.27/002-pci_io_map_base.patch new file mode 100644 index 0000000000..5786803e47 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/002-pci_io_map_base.patch @@ -0,0 +1,42 @@ +The code is rather based on trial-and-error than knowledge. Verified Via +Rhine functionality in PIO as well as MMIO mode. + +Signed-off-by: Phil Sutter +Tested-by: Florian Fainelli +--- + arch/mips/pci/pci-rc32434.c | 11 +++++++++++ + 1 files changed, 11 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c +index 1c2821e..71f7d27 100644 +--- a/arch/mips/pci/pci-rc32434.c ++++ b/arch/mips/pci/pci-rc32434.c +@@ -205,6 +205,8 @@ static int __init rc32434_pcibridge_init(void) + + static int __init rc32434_pci_init(void) + { ++ void __iomem *io_map_base; ++ + pr_info("PCI: Initializing PCI\n"); + + ioport_resource.start = rc32434_res_pci_io1.start; +@@ -212,6 +214,15 @@ static int __init rc32434_pci_init(void) + + rc32434_pcibridge_init(); + ++ io_map_base = ioremap(rc32434_res_pci_io1.start, ++ rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1); ++ ++ if (!io_map_base) ++ return -ENOMEM; ++ ++ rc32434_controller.io_map_base = ++ (unsigned long)io_map_base - rc32434_res_pci_io1.start; ++ + register_pci_controller(&rc32434_controller); + rc32434_sync(); + +-- +1.5.6.4 + + diff --git a/target/linux/rb532/patches-2.6.27/003-gpio_bit_setting.patch b/target/linux/rb532/patches-2.6.27/003-gpio_bit_setting.patch new file mode 100644 index 0000000000..49f9f4b3b5 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/003-gpio_bit_setting.patch @@ -0,0 +1,35 @@ +The algorithm works unconditionally. If bitval is one, the first line is +a no op and the second line sets the bit at offset position. Vice versa, +if bitval is zero, the first line clears the bit at offset position and +the second line is a no op. + +Signed-off-by: Phil Sutter +--- + arch/mips/rb532/gpio.c | 6 ++---- + 1 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c +index 0e84c8a..e35cb75 100644 +--- a/arch/mips/rb532/gpio.c ++++ b/arch/mips/rb532/gpio.c +@@ -119,13 +119,11 @@ static inline void rb532_set_bit(unsigned bitval, + unsigned long flags; + u32 val; + +- bitval = !!bitval; /* map parameter to {0,1} */ +- + local_irq_save(flags); + + val = readl(ioaddr); +- val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ +- val |= ( bitval << offset ); /* set bit if bitval == 1 */ ++ val &= ~(!bitval << offset); /* unset bit if bitval == 0 */ ++ val |= (!!bitval << offset); /* set bit if bitval == 1 */ + writel(val, ioaddr); + + local_irq_restore(flags); +-- +1.5.6.4 + + + diff --git a/target/linux/rb532/patches-2.6.27/004-fix_pata_rb532_cf.patch b/target/linux/rb532/patches-2.6.27/004-fix_pata_rb532_cf.patch new file mode 100644 index 0000000000..50dedefbe7 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/004-fix_pata_rb532_cf.patch @@ -0,0 +1,84 @@ +After applying the following changes I could verify functionality by +mounting a filesystem on the cfdisk and reading/writing files in it. + +The set_irq_type() function must be wrong, as there is no set_type() +function defined for the rb532 IRQ chip. But as the used IRQ actually is +being triggered by a GPIO, setting it's interrupt level should be the +right alternative. Also to clear a GPIO triggered IRQ, the source has to +be cleared. This is being done at the end of rb532_pata_irq_handler. + +Signed-off-by: Phil Sutter +Acked-by: Florian Fainelli +--- + drivers/ata/pata_rb532_cf.c | 15 ++++++++++----- + 1 files changed, 10 insertions(+), 5 deletions(-) + +diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c +index f8b3ffc..7b11f40 100644 +--- a/drivers/ata/pata_rb532_cf.c ++++ b/drivers/ata/pata_rb532_cf.c +@@ -31,6 +31,7 @@ + #include + + #include ++#include + + #define DRV_NAME "pata-rb532-cf" + #define DRV_VERSION "0.1.0" +@@ -39,7 +40,8 @@ + #define RB500_CF_MAXPORTS 1 + #define RB500_CF_IO_DELAY 400 + +-#define RB500_CF_REG_CMD 0x0800 ++#define RB500_CF_REG_BASE 0x0800 ++#define RB500_CF_REG_ERR 0x080D + #define RB500_CF_REG_CTRL 0x080E + #define RB500_CF_REG_DATA 0x0C00 + +@@ -62,7 +64,7 @@ static inline void rb532_pata_finish_io(struct ata_port *ap) + ata_sff_dma_pause(ap); + ndelay(RB500_CF_IO_DELAY); + +- set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH); ++ rb532_gpio_set_ilevel(1, info->gpio_line); + } + + static void rb532_pata_exec_command(struct ata_port *ap, +@@ -109,13 +111,15 @@ static irqreturn_t rb532_pata_irq_handler(int irq, void *dev_instance) + struct rb532_cf_info *info = ah->private_data; + + if (gpio_get_value(info->gpio_line)) { +- set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW); ++ rb532_gpio_set_ilevel(0, info->gpio_line); + if (!info->frozen) + ata_sff_interrupt(info->irq, dev_instance); + } else { +- set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH); ++ rb532_gpio_set_ilevel(1, info->gpio_line); + } + ++ rb532_gpio_set_istat(0, info->gpio_line); ++ + return IRQ_HANDLED; + } + +@@ -146,13 +150,14 @@ static void rb532_pata_setup_ports(struct ata_host *ah) + ap->pio_mask = 0x1f; /* PIO4 */ + ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO; + +- ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_CMD; ++ ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_BASE; + ap->ioaddr.ctl_addr = info->iobase + RB500_CF_REG_CTRL; + ap->ioaddr.altstatus_addr = info->iobase + RB500_CF_REG_CTRL; + + ata_sff_std_ports(&ap->ioaddr); + + ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DATA; ++ ap->ioaddr.error_addr = info->iobase + RB500_CF_REG_ERR; + } + + static __devinit int rb532_pata_driver_probe(struct platform_device *pdev) +-- +1.5.6.4 + + diff --git a/target/linux/rb532/patches-2.6.27/005-pata_rb532_cf_4bytes_rw.patch b/target/linux/rb532/patches-2.6.27/005-pata_rb532_cf_4bytes_rw.patch new file mode 100644 index 0000000000..c8e682014c --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/005-pata_rb532_cf_4bytes_rw.patch @@ -0,0 +1,68 @@ +* rename the offset definition to avoid abiguity with the standard ATA + IO address +* read and write four bytes at once like the original driver does +* use writesl() and readsl() which implicitly iterate over the data + +This patch assumes buflen to be a multiple of four, which is true for +ATA devices. ATAPI support is not known, though unlikely, as the +original driver always transfers 512 Bytes at once. + +Signed-off-by: Phil Sutter +Acked-by: Sergei Shtyltov +--- + drivers/ata/pata_rb532_cf.c | 20 +++++++++----------- + 1 files changed, 9 insertions(+), 11 deletions(-) + +diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c +index 7b11f40..b919012 100644 +--- a/drivers/ata/pata_rb532_cf.c ++++ b/drivers/ata/pata_rb532_cf.c +@@ -43,7 +43,8 @@ + #define RB500_CF_REG_BASE 0x0800 + #define RB500_CF_REG_ERR 0x080D + #define RB500_CF_REG_CTRL 0x080E +-#define RB500_CF_REG_DATA 0x0C00 ++/* 32bit buffered data register offset */ ++#define RB500_CF_REG_DBUF32 0x0C00 + + struct rb532_cf_info { + void __iomem *iobase; +@@ -74,19 +75,16 @@ static void rb532_pata_exec_command(struct ata_port *ap, + rb532_pata_finish_io(ap); + } + +-static void rb532_pata_data_xfer(struct ata_device *adev, unsigned char *buf, +- unsigned int buflen, int write_data) ++static void rb532_pata_data_xfer(struct ata_device *adev, ++ unsigned char *buf, unsigned int buflen, int write_data) + { + struct ata_port *ap = adev->link->ap; + void __iomem *ioaddr = ap->ioaddr.data_addr; + +- if (write_data) { +- for (; buflen > 0; buflen--, buf++) +- writeb(*buf, ioaddr); +- } else { +- for (; buflen > 0; buflen--, buf++) +- *buf = readb(ioaddr); +- } ++ if (write_data) ++ writesl(ioaddr, buf, buflen / sizeof(u32)); ++ else ++ readsl(ioaddr, buf, buflen / sizeof(u32)); + + rb532_pata_finish_io(adev->link->ap); + } +@@ -156,7 +154,7 @@ static void rb532_pata_setup_ports(struct ata_host *ah) + + ata_sff_std_ports(&ap->ioaddr); + +- ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DATA; ++ ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DBUF32; + ap->ioaddr.error_addr = info->iobase + RB500_CF_REG_ERR; + } + +-- +1.5.6.4 + + diff --git a/target/linux/rb532/patches-2.6.27/006-pata_rb532_cf_fix_prototype.patch b/target/linux/rb532/patches-2.6.27/006-pata_rb532_cf_fix_prototype.patch new file mode 100644 index 0000000000..1a7cbd0ef3 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/006-pata_rb532_cf_fix_prototype.patch @@ -0,0 +1,35 @@ +Per definition, this function should return the number of bytes +consumed. Also take care of the unlikely case when buflen is not a +multiple of four; while transferring, the division cuts the remaining +bytes, so alter the return value accordingly. + +Signed-off-by: Phil Sutter +--- + drivers/ata/pata_rb532_cf.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c +index b919012..95a0d66 100644 +--- a/drivers/ata/pata_rb532_cf.c ++++ b/drivers/ata/pata_rb532_cf.c +@@ -75,7 +75,7 @@ static void rb532_pata_exec_command(struct ata_port *ap, + rb532_pata_finish_io(ap); + } + +-static void rb532_pata_data_xfer(struct ata_device *adev, ++static unsigned int rb532_pata_data_xfer(struct ata_device *adev, + unsigned char *buf, unsigned int buflen, int write_data) + { + struct ata_port *ap = adev->link->ap; +@@ -87,6 +87,7 @@ static void rb532_pata_data_xfer(struct ata_device *adev, + readsl(ioaddr, buf, buflen / sizeof(u32)); + + rb532_pata_finish_io(adev->link->ap); ++ return buflen - (buflen % sizeof(u32)); + } + + static void rb532_pata_freeze(struct ata_port *ap) +-- +1.5.6.4 + + diff --git a/target/linux/rb532/patches-2.6.27/007-cmdline_hack.patch b/target/linux/rb532/patches-2.6.27/007-cmdline_hack.patch new file mode 100644 index 0000000000..5f2ed2f2f0 --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/007-cmdline_hack.patch @@ -0,0 +1,15 @@ +diff -urN linux-2.6.27.5/arch/mips/kernel/head.S linux-2.6.27.5.new/arch/mips/kernel/head.S +--- linux-2.6.27.5/arch/mips/kernel/head.S 2008-11-15 19:24:03.000000000 +0100 ++++ linux-2.6.27.5.new/arch/mips/kernel/head.S 2008-11-15 19:24:55.000000000 +0100 +@@ -123,6 +123,11 @@ + + j kernel_entry + nop ++ ++ ++EXPORT(_image_cmdline) ++ .ascii "CMDLINE:" ++ + #ifndef CONFIG_NO_EXCEPT_FILL + /* + * Reserved space for exception handlers. diff --git a/target/linux/rb532/patches-2.6.27/008-korina_fixes.patch b/target/linux/rb532/patches-2.6.27/008-korina_fixes.patch new file mode 100644 index 0000000000..69483010bb --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/008-korina_fixes.patch @@ -0,0 +1,245 @@ +--- linux-2.6.27.5/drivers/net/korina.c 2008-11-07 18:55:34.000000000 +0100 ++++ ../build_dir/linux-rb532/linux-2.6.27.5/drivers/net/korina.c 2008-11-16 00:38:19.000000000 +0100 +@@ -327,12 +327,11 @@ + + dmas = readl(&lp->rx_dma_regs->dmas); + if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) { +- netif_rx_schedule_prep(dev, &lp->napi); +- + dmasm = readl(&lp->rx_dma_regs->dmasm); + writel(dmasm | (DMA_STAT_DONE | + DMA_STAT_HALT | DMA_STAT_ERR), + &lp->rx_dma_regs->dmasm); ++ netif_rx_schedule(dev, &lp->napi); + + if (dmas & DMA_STAT_ERR) + printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name); +@@ -350,14 +349,24 @@ + struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done]; + struct sk_buff *skb, *skb_new; + u8 *pkt_buf; +- u32 devcs, pkt_len, dmas, rx_free_desc; ++ u32 devcs, pkt_len, dmas, pktuncrc_len; + int count; + + dma_cache_inv((u32)rd, sizeof(*rd)); + + for (count = 0; count < limit; count++) { +- ++ skb_new = NULL; + devcs = rd->devcs; ++ pkt_len = RCVPKT_LENGTH(devcs); ++ skb = lp->rx_skb[lp->rx_next_done]; ++ ++ if ((devcs & ETH_RX_LD) != ETH_RX_LD) { ++ /* check that this is a whole packet ++ * WARNING: DMA_FD bit incorrectly set ++ * in Rc32434 (errata ref #077) */ ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ } + + /* Update statistics counters */ + if (devcs & ETH_RX_CRC) +@@ -375,75 +384,79 @@ + if (devcs & ETH_RX_MP) + dev->stats.multicast++; + +- if ((devcs & ETH_RX_LD) != ETH_RX_LD) { +- /* check that this is a whole packet +- * WARNING: DMA_FD bit incorrectly set +- * in Rc32434 (errata ref #077) */ +- dev->stats.rx_errors++; +- dev->stats.rx_dropped++; +- } +- +- while ((rx_free_desc = KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) { +- /* init the var. used for the later +- * operations within the while loop */ +- skb_new = NULL; +- pkt_len = RCVPKT_LENGTH(devcs); +- skb = lp->rx_skb[lp->rx_next_done]; +- +- if ((devcs & ETH_RX_ROK)) { +- /* must be the (first and) last +- * descriptor then */ +- pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data; ++ else if ((devcs & ETH_RX_ROK)) { ++ /* must be the (first and) last ++ * descriptor then */ ++ pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data; ++ pktuncrc_len = pkt_len - 4; + +- /* invalidate the cache */ +- dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4); ++ /* invalidate the cache */ ++ dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len); + +- /* Malloc up new buffer. */ +- skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2); ++ /* Malloc up new buffer. */ ++ skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2); + +- if (!skb_new) +- break; ++ if (skb_new) { + /* Do not count the CRC */ +- skb_put(skb, pkt_len - 4); ++ skb_put(skb, pktuncrc_len); + skb->protocol = eth_type_trans(skb, dev); + + /* Pass the packet to upper layers */ + netif_receive_skb(skb); ++ + dev->last_rx = jiffies; + dev->stats.rx_packets++; +- dev->stats.rx_bytes += pkt_len; +- +- /* Update the mcast stats */ +- if (devcs & ETH_RX_MP) +- dev->stats.multicast++; +- ++ dev->stats.rx_bytes += pktuncrc_len; ++ + lp->rx_skb[lp->rx_next_done] = skb_new; ++ } else { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; + } ++ } else { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* Update statistics counters */ ++ if (devcs & ETH_RX_CRC) ++ dev->stats.rx_crc_errors++; ++ else if (devcs & ETH_RX_LOR) ++ dev->stats.rx_length_errors++; ++ else if (devcs & ETH_RX_LE) ++ dev->stats.rx_length_errors++; ++ else if (devcs & ETH_RX_OVR) ++ dev->stats.rx_over_errors++; ++ else if (devcs & ETH_RX_CV) ++ dev->stats.rx_frame_errors++; ++ else if (devcs & ETH_RX_CES) ++ dev->stats.rx_length_errors++; ++ else if (devcs & ETH_RX_MP) ++ dev->stats.multicast++; ++ } + +- rd->devcs = 0; ++ rd->devcs = 0; + +- /* Restore descriptor's curr_addr */ +- if (skb_new) +- rd->ca = CPHYSADDR(skb_new->data); +- else +- rd->ca = CPHYSADDR(skb->data); ++ /* Restore descriptor's curr_addr */ ++ if (skb_new) ++ rd->ca = CPHYSADDR(skb_new->data); ++ else ++ rd->ca = CPHYSADDR(skb->data); + +- rd->control = DMA_COUNT(KORINA_RBSIZE) | ++ rd->control = DMA_COUNT(KORINA_RBSIZE) | + DMA_DESC_COD | DMA_DESC_IOD; +- lp->rd_ring[(lp->rx_next_done - 1) & +- KORINA_RDS_MASK].control &= +- ~DMA_DESC_COD; +- +- lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK; +- dma_cache_wback((u32)rd, sizeof(*rd)); +- rd = &lp->rd_ring[lp->rx_next_done]; +- writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); +- } ++ lp->rd_ring[(lp->rx_next_done - 1) & ++ KORINA_RDS_MASK].control &= ~DMA_DESC_COD; ++ ++ lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK; ++ dma_cache_wback((u32)rd, sizeof(*rd)); ++ rd = &lp->rd_ring[lp->rx_next_done]; ++ writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); + } + + dmas = readl(&lp->rx_dma_regs->dmas); + + if (dmas & DMA_STAT_HALT) { ++ /* Mask off halt and errors bits */ + writel(~(DMA_STAT_HALT | DMA_STAT_ERR), + &lp->rx_dma_regs->dmas); + +@@ -469,8 +482,9 @@ + if (work_done < budget) { + netif_rx_complete(dev, napi); + ++ /* Mask off interrupts */ + writel(readl(&lp->rx_dma_regs->dmasm) & +- ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), ++ (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), + &lp->rx_dma_regs->dmasm); + } + return work_done; +@@ -534,10 +548,11 @@ + { + struct korina_private *lp = netdev_priv(dev); + struct dma_desc *td = &lp->td_ring[lp->tx_next_done]; ++ unsigned long flags; + u32 devcs; + u32 dmas; + +- spin_lock(&lp->lock); ++ spin_lock_irqsave(&lp->lock, flags); + + /* Process all desc that are done */ + while (IS_DMA_FINISHED(td->control)) { +@@ -610,7 +625,7 @@ + ~(DMA_STAT_FINI | DMA_STAT_ERR), + &lp->tx_dma_regs->dmasm); + +- spin_unlock(&lp->lock); ++ spin_unlock_irqrestore(&lp->lock, flags); + } + + static irqreturn_t +@@ -624,11 +639,10 @@ + dmas = readl(&lp->tx_dma_regs->dmas); + + if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) { +- korina_tx(dev); +- + dmasm = readl(&lp->tx_dma_regs->dmasm); + writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), + &lp->tx_dma_regs->dmasm); ++ korina_tx(dev); + + if (lp->tx_chain_status == desc_filled && + (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { +@@ -1078,11 +1092,18 @@ + + static int korina_probe(struct platform_device *pdev) + { +- struct korina_device *bif = platform_get_drvdata(pdev); ++ struct korina_device *bif; + struct korina_private *lp; + struct net_device *dev; + struct resource *r; + int rc; ++ DECLARE_MAC_BUF(mac); ++ ++ bif = (struct korina_device *)pdev->dev.platform_data; ++ if (!bif) { ++ printk(KERN_ERR DRV_NAME ": missing platform_data\n"); ++ return -ENODEV; ++ } + + dev = alloc_etherdev(sizeof(struct korina_private)); + if (!dev) { +@@ -1172,6 +1193,7 @@ + ": cannot register net device %d\n", rc); + goto probe_err_register; + } ++ printk(KERN_INFO DRV_NAME ": registered %s, IRQ %d MAC %s\n", dev->name, dev->irq, print_mac(mac, dev->dev_addr)); + out: + return rc; + diff --git a/target/linux/rb532/patches-2.6.27/009-rc32434_res_name.patch b/target/linux/rb532/patches-2.6.27/009-rc32434_res_name.patch new file mode 100644 index 0000000000..e61ec8330a --- /dev/null +++ b/target/linux/rb532/patches-2.6.27/009-rc32434_res_name.patch @@ -0,0 +1,12 @@ +diff -urN linux-2.6.27.5/drivers/watchdog/rc32434_wdt.c linux-2.6.27.5.new/drivers/watchdog/rc32434_wdt.c +--- linux-2.6.27.5/drivers/watchdog/rc32434_wdt.c 2008-11-07 18:55:34.000000000 +0100 ++++ linux-2.6.27.5.new/drivers/watchdog/rc32434_wdt.c 2008-11-15 22:06:28.000000000 +0100 +@@ -261,7 +261,7 @@ + int ret; + struct resource *r; + +- r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb500_wdt_res"); ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res"); + if (!r) { + printk(KERN_ERR KBUILD_MODNAME + "failed to retrieve resources\n"); -- 2.30.2