From 8a78ca9ea57e019869ddac2ef10a15593f211997 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 27 Sep 2014 01:18:29 +0200 Subject: [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Pavel Machek Cc: Stefan Roese Reviewed-by: Jagannadha Sutradharudu Teki --- include/configs/socfpga_common.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f7b314d3ca..c213082be0 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -78,6 +78,25 @@ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +/* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 + */ +#endif + /* * Ethernet on SoC (EMAC) */ -- 2.30.2