From 87fec0514f613f8ac43c01b0bc0bc7072c5d10ae Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 23 Sep 2013 12:04:38 +1000 Subject: [PATCH] powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers in little endian builds FPRs overlap the high 64bits of the first 32 VSX registers. The ptrace FP read/write code assumes big endian ordering and grabs the lowest 64 bits. Fix this by using the TS_FPR macro which does the right thing. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/ptrace.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 9a0d24c390a3..8d5d4e921a5e 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1554,8 +1554,8 @@ long arch_ptrace(struct task_struct *child, long request, flush_fp_to_thread(child); if (fpidx < (PT_FPSCR - PT_FPR0)) - tmp = ((unsigned long *)child->thread.fpr) - [fpidx * TS_FPRWIDTH]; + memcpy(&tmp, &child->thread.TS_FPR(fpidx), + sizeof(long)); else tmp = child->thread.fpscr.val; } @@ -1587,8 +1587,8 @@ long arch_ptrace(struct task_struct *child, long request, flush_fp_to_thread(child); if (fpidx < (PT_FPSCR - PT_FPR0)) - ((unsigned long *)child->thread.fpr) - [fpidx * TS_FPRWIDTH] = data; + memcpy(&child->thread.TS_FPR(fpidx), &data, + sizeof(long)); else child->thread.fpscr.val = data; ret = 0; -- 2.30.2