From 82054678aeb66907acd63df7d1d5f9556e29a5cc Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Wed, 12 Feb 2020 15:38:51 -0500 Subject: [PATCH] drm/amd/display: Link training TPS1 workaround [Why] Previously implemented early_cr_pattern was link level but the whole asic should be affected. [How] - change old link flag to dc level - new bit in dc->work_arounds set by DM Signed-off-by: Martin Leung Reviewed-by: Joshua Aberback Acked-by: Rodrigo Siqueira Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_link.h | 1 - 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 8de9d6f9a477..93127bc90f3c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -973,7 +973,7 @@ static enum link_training_result perform_clock_recovery_sequence( retries_cr = 0; retry_count = 0; - if (!link->wa_flags.dp_early_cr_pattern) + if (!link->ctx->dc->work_arounds.lt_early_cr_pattern) dp_set_hw_training_pattern(link, tr_pattern, offset); /* najeeb - The synaptics MST hub can put the LT in @@ -1446,11 +1446,11 @@ enum link_training_result dc_link_dp_perform_link_training( &link->preferred_training_settings, <_settings); - if (link->wa_flags.dp_early_cr_pattern) - start_clock_recovery_pattern_early(link, <_settings, DPRX); - /* 1. set link rate, lane count and spread. */ - dpcd_set_link_settings(link, <_settings); + if (link->ctx->dc->work_arounds.lt_early_cr_pattern) + start_clock_recovery_pattern_early(link, <_settings, DPRX); + else + dpcd_set_link_settings(link, <_settings); if (link->preferred_training_settings.fec_enable != NULL) fec_enable = *link->preferred_training_settings.fec_enable; @@ -1669,11 +1669,11 @@ enum link_training_result dc_link_dp_sync_lt_attempt( dp_set_panel_mode(link, panel_mode); /* Attempt to train with given link training settings */ - if (link->wa_flags.dp_early_cr_pattern) - start_clock_recovery_pattern_early(link, <_settings, DPRX); - /* Set link rate, lane count and spread. */ - dpcd_set_link_settings(link, <_settings); + if (link->ctx->dc->work_arounds.lt_early_cr_pattern) + start_clock_recovery_pattern_early(link, <_settings, DPRX); + else + dpcd_set_link_settings(link, <_settings); /* 2. perform link training (set link training done * to false is done as well) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b3f6311d3564..72298520a303 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -126,6 +126,7 @@ struct dc_bug_wa { bool no_connect_phy_config; bool dedcn20_305_wa; bool skip_clock_update; + bool lt_early_cr_pattern; }; struct dc_dcc_surface_param { diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index 6344de3ca979..5f341e960506 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -135,7 +135,6 @@ struct dc_link { bool dp_keep_receiver_powered; bool dp_skip_DID2; bool dp_skip_reset_segment; - bool dp_early_cr_pattern; } wa_flags; struct link_mst_stream_allocation_table mst_stream_alloc_table; -- 2.30.2