From 80e80ec817f161560b4159608fb41bd289abede3 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 3 Oct 2017 13:53:51 -0400 Subject: [PATCH] drm/amd/display: Fix underscan not using proper scaling fix underscan not being set correctly Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4df5bf750257..12aeb6d83f42 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1362,7 +1362,7 @@ void dc_commit_updates_for_stream(struct dc *dc, enum surface_update_type update_type; struct dc_state *context; struct dc_context *dc_ctx = dc->ctx; - int i; + int i, j; stream_status = dc_stream_get_status(stream); context = dc->current_state; @@ -1396,8 +1396,17 @@ void dc_commit_updates_for_stream(struct dc *dc, if (srf_updates[i].flip_addr) surface->address = srf_updates[i].flip_addr->address; - } + if (update_type >= UPDATE_TYPE_MED) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + + if (pipe_ctx->plane_state != surface) + continue; + resource_build_scaling_params(pipe_ctx); + } + } + } commit_planes_for_stream( dc, -- 2.30.2