From 7d5f8315f13315dfbec625bbd4af8296b51398a7 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Tue, 16 Nov 2021 16:40:45 +0100 Subject: [PATCH] uboot-sunxid1: add new package Add a D1-variant of u-boot for the RISC-V SoCs. The generated u-boot image is called "TOC1" which is a mesh of an OpenSBI, a DTB and an u-boot-nodtb binary. Signed-off-by: Zoltan HERPAI --- package/boot/uboot-sunxid1/Makefile | 58 + .../boot/uboot-sunxid1/files/sunxi_toc1.cfg | 9 + .../patches/001-uboot-2021.10-nezha.diff | 129985 +++++++++++++++ ...-spl-remove-dtoc-of-pdata-generation.patch | 28 + ...-environment-for-dtc-binary-location.patch | 35 + .../patches/102-disable-libcrypto.diff | 32 + .../103-increate-bootm-size-to-32M.patch | 12 + ...un20i-d1.dtsi-adjust-plic-compatible.patch | 36 + package/boot/uboot-sunxid1/uEnv-default.txt | 4 + 9 files changed, 130199 insertions(+) create mode 100644 package/boot/uboot-sunxid1/Makefile create mode 100644 package/boot/uboot-sunxid1/files/sunxi_toc1.cfg create mode 100644 package/boot/uboot-sunxid1/patches/001-uboot-2021.10-nezha.diff create mode 100644 package/boot/uboot-sunxid1/patches/002-spl-remove-dtoc-of-pdata-generation.patch create mode 100644 package/boot/uboot-sunxid1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch create mode 100644 package/boot/uboot-sunxid1/patches/102-disable-libcrypto.diff create mode 100644 package/boot/uboot-sunxid1/patches/103-increate-bootm-size-to-32M.patch create mode 100644 package/boot/uboot-sunxid1/patches/104-arch-riscv-dts-sun20i-d1.dtsi-adjust-plic-compatible.patch create mode 100644 package/boot/uboot-sunxid1/uEnv-default.txt diff --git a/package/boot/uboot-sunxid1/Makefile b/package/boot/uboot-sunxid1/Makefile new file mode 100644 index 0000000000..782b9b780d --- /dev/null +++ b/package/boot/uboot-sunxid1/Makefile @@ -0,0 +1,58 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_RELEASE:=1 + +PKG_VERSION:=2021.10 +PKG_HASH:=cde723e19262e646f2670d25e5ec4b1b368490de950d4e26275a988c36df0bd4 + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk + +define U-Boot/Default + BUILD_TARGET:=sunxid1 + BUILD_DEVICES=$(1) + UBOOT_IMAGE:=u-boot.toc1 + DTS_DIR:=arch/riscv/dts + UBOOT_DTS:=sun20i-d1-nezha.dtb + UENV:=default + DEFAULT:=y +endef + +define U-Boot/nezha + NAME:=Nezha D1 + OPENSBI:=generic + DEPENDS:=+opensbi-d1_generic +sun20spl + BUILD_DEVICES:=nezha +endef + +UBOOT_TARGETS := \ + nezha + +UBOOT_MAKE_FLAGS += \ + OPENSBI=$(STAGING_DIR_IMAGE)/fw_dynamic-${OPENSBI}.bin + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS) + + $(CP) ./files/sunxi_toc1.cfg $(STAGING_DIR_IMAGE) + sed -i "s:|OPENSBI|:$(STAGING_DIR_IMAGE)/fw_dynamic-$(OPENSBI).bin:" $(STAGING_DIR_IMAGE)/sunxi_toc1.cfg + sed -i "s:|UBOOTDTB|:$(STAGING_DIR_IMAGE)/$(UBOOT_DTS):" $(STAGING_DIR_IMAGE)/sunxi_toc1.cfg + sed -i "s:|UBOOTNODTBBIN|:$(PKG_BUILD_DIR)/u-boot-nodtb.bin:" $(STAGING_DIR_IMAGE)/sunxi_toc1.cfg + $(PKG_BUILD_DIR)/tools/mkimage -T sunxi_toc1 -d $(STAGING_DIR_IMAGE)/sunxi_toc1.cfg $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) + + $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE) + + mkimage -C none -A riscv -T script -d uEnv-$(UENV).txt \ + $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-sunxid1/files/sunxi_toc1.cfg b/package/boot/uboot-sunxid1/files/sunxi_toc1.cfg new file mode 100644 index 0000000000..545c095d35 --- /dev/null +++ b/package/boot/uboot-sunxid1/files/sunxi_toc1.cfg @@ -0,0 +1,9 @@ +[opensbi] +file = |OPENSBI| +addr = 0x40000000 +[dtb] +file = |UBOOTDTB| +addr = 0x44000000 +[u-boot] +file = |UBOOTNODTBBIN| +addr = 0x4a000000 diff --git a/package/boot/uboot-sunxid1/patches/001-uboot-2021.10-nezha.diff b/package/boot/uboot-sunxid1/patches/001-uboot-2021.10-nezha.diff new file mode 100644 index 0000000000..c4d70b842b --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/001-uboot-2021.10-nezha.diff @@ -0,0 +1,129985 @@ +diff -ruN u-boot-2021.10/api/Kconfig u-boot/api/Kconfig +--- u-boot-2021.10/api/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/api/Kconfig 2021-11-01 17:10:13.542965197 +0100 +@@ -2,7 +2,6 @@ + + config API + bool "Enable U-Boot API" +- default n + help + This option enables the U-Boot API. See api/README for more information. + +diff -ruN u-boot-2021.10/arch/arc/include/asm/cache.h u-boot/arch/arc/include/asm/cache.h +--- u-boot-2021.10/arch/arc/include/asm/cache.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arc/include/asm/cache.h 2021-11-01 17:10:13.542965197 +0100 +@@ -16,9 +16,6 @@ + */ + #define ARCH_DMA_MINALIGN 128 + +-/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */ +-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN +- + #if defined(ARC_MMU_ABSENT) + #define CONFIG_ARC_MMU_VER 0 + #elif defined(CONFIG_ARC_MMU_V2) +diff -ruN u-boot-2021.10/arch/arc/Kconfig u-boot/arch/arc/Kconfig +--- u-boot-2021.10/arch/arc/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arc/Kconfig 2021-11-01 17:10:13.542965197 +0100 +@@ -104,13 +104,11 @@ + + config CPU_BIG_ENDIAN + bool "Enable Big Endian Mode" +- default n + help + Build kernel for Big Endian Mode of ARC CPU + + config SYS_ICACHE_OFF + bool "Do not enable icache" +- default n + help + Do not enable instruction cache in U-Boot. + +@@ -123,7 +121,6 @@ + + config SYS_DCACHE_OFF + bool "Do not enable dcache" +- default n + help + Do not enable data cache in U-Boot. + +@@ -136,14 +133,12 @@ + + menuconfig ARC_DBG + bool "ARC debugging" +- default n + + if ARC_DBG + + config ARC_DBG_IOC_ENABLE + bool "Enable IO coherency unit" + depends on CPU_ARCHS38 +- default n + help + Enable IO coherency unit to debug problems with caches and + DMA peripherals. +diff -ruN u-boot-2021.10/arch/arc/lib/bootm.c u-boot/arch/arc/lib/bootm.c +--- u-boot-2021.10/arch/arc/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arc/lib/bootm.c 2021-11-01 17:10:13.542965197 +0100 +@@ -8,42 +8,12 @@ + #include + #include + #include +-#include + #include + #include + #include + + DECLARE_GLOBAL_DATA_PTR; + +-static ulong get_sp(void) +-{ +- ulong ret; +- +- asm("mov %0, sp" : "=r"(ret) : ); +- return ret; +-} +- +-void arch_lmb_reserve(struct lmb *lmb) +-{ +- ulong sp; +- +- /* +- * Booting a (Linux) kernel image +- * +- * Allocate space for command line and board info - the +- * address should be as high as possible within the reach of +- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused +- * memory, which means far enough below the current stack +- * pointer. +- */ +- sp = get_sp(); +- debug("## Current stack ends at 0x%08lx ", sp); +- +- /* adjust sp by 4K to be safe */ +- sp -= 4096; +- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); +-} +- + static int cleanup_before_linux(void) + { + disable_interrupts(); +diff -ruN u-boot-2021.10/arch/arc/lib/cache.c u-boot/arch/arc/lib/cache.c +--- u-boot-2021.10/arch/arc/lib/cache.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arc/lib/cache.c 2021-11-01 17:10:13.542965197 +0100 +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -820,3 +821,16 @@ + + __ic_entire_invalidate(); + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mov %0, sp" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/arc/lib/libgcc2.h u-boot/arch/arc/lib/libgcc2.h +--- u-boot-2021.10/arch/arc/lib/libgcc2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arc/lib/libgcc2.h 2021-11-01 17:10:13.546298348 +0100 +@@ -35,7 +35,7 @@ + typedef unsigned int UHItype __attribute__ ((mode (HI))); + #if MIN_UNITS_PER_WORD > 1 + /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */ +-typedef int SItype __attribute__ ((mode (SI))); ++typedef int SItype __attribute__ ((mode (SI))); + typedef unsigned int USItype __attribute__ ((mode (SI))); + #if __SIZEOF_LONG_LONG__ > 4 + /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */ +diff -ruN u-boot-2021.10/arch/arm/config.mk u-boot/arch/arm/config.mk +--- u-boot-2021.10/arch/arm/config.mk 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/config.mk 2021-11-01 17:10:13.546298348 +0100 +@@ -25,6 +25,7 @@ + + PLATFORM_RELFLAGS += -fno-common -ffixed-r9 + PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ ++ $(call cc-option,-mgeneral-regs-only) \ + $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) + + # LLVM support +@@ -158,7 +159,8 @@ + OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel + endif + +-ifneq ($(CONFIG_IMX_CONFIG),) ++ifdef CONFIG_MACH_IMX ++ifneq ($(CONFIG_IMX_CONFIG),"") + ifdef CONFIG_SPL + ifndef CONFIG_SPL_BUILD + INPUTS-y += SPL +@@ -174,6 +176,7 @@ + INPUTS-y += u-boot.vyb + endif + endif ++endif + + EFI_LDS := elf_arm_efi.lds + EFI_CRT0 := crt0_arm_efi.o +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/Makefile u-boot/arch/arm/cpu/arm1136/Makefile +--- u-boot-2021.10/arch/arm/cpu/arm1136/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/Makefile 2021-11-01 17:10:13.546298348 +0100 +@@ -7,4 +7,3 @@ + + obj-y += ../arm11/ + obj-$(CONFIG_MX31) += mx31/ +-obj-$(CONFIG_MX35) += mx35/ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/mx35/generic.c u-boot/arch/arm/cpu/arm1136/mx35/generic.c +--- u-boot-2021.10/arch/arm/cpu/arm1136/mx35/generic.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/mx35/generic.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,530 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2007 +- * Sascha Hauer, Pengutronix +- * +- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#ifdef CONFIG_FSL_ESDHC_IMX +-#include +-#endif +-#include +-#include +- +-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +-#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +-#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +-#define CLK_CODE_PATH(c) ((c) & 0xFF) +- +-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) +- +-#ifdef CONFIG_FSL_ESDHC_IMX +-DECLARE_GLOBAL_DATA_PTR; +-#endif +- +-static int g_clk_mux_auto[8] = { +- CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, +- CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +-}; +- +-static int g_clk_mux_consumer[16] = { +- CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, +- -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), +- CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, +- -1, -1, CLK_CODE(4, 2, 0), -1, +-}; +- +-static int hsp_div_table[3][16] = { +- {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, +- {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, +- {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +-}; +- +-u32 get_cpu_rev(void) +-{ +- int reg; +- struct iim_regs *iim = +- (struct iim_regs *)IIM_BASE_ADDR; +- reg = readl(&iim->iim_srev); +- if (!reg) { +- reg = readw(ROMPATCH_REV); +- reg <<= 4; +- } else { +- reg += CHIP_REV_1_0; +- } +- +- return 0x35000 + (reg & 0xFF); +-} +- +-static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) +-{ +- int *pclk_mux; +- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { +- pclk_mux = g_clk_mux_consumer + +- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> +- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); +- } else { +- pclk_mux = g_clk_mux_auto + +- ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> +- MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); +- } +- +- if ((*pclk_mux) == -1) +- return -1; +- +- if (fi && fd) { +- if (!CLK_CODE_PATH(*pclk_mux)) { +- *fi = *fd = 1; +- return CLK_CODE_ARM(*pclk_mux); +- } +- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { +- *fi = 3; +- *fd = 4; +- } else { +- *fi = 2; +- *fd = 3; +- } +- } +- return CLK_CODE_ARM(*pclk_mux); +-} +- +-static int get_ahb_div(u32 pdr0) +-{ +- int *pclk_mux; +- +- pclk_mux = g_clk_mux_consumer + +- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> +- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); +- +- if ((*pclk_mux) == -1) +- return -1; +- +- return CLK_CODE_AHB(*pclk_mux); +-} +- +-static u32 decode_pll(u32 reg, u32 infreq) +-{ +- u32 mfi = (reg >> 10) & 0xf; +- s32 mfn = reg & 0x3ff; +- u32 mfd = (reg >> 16) & 0x3ff; +- u32 pd = (reg >> 26) & 0xf; +- +- mfi = mfi <= 5 ? 5 : mfi; +- mfn = mfn >= 512 ? mfn - 1024 : mfn; +- mfd += 1; +- pd += 1; +- +- return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), +- mfd * pd); +-} +- +-static u32 get_mcu_main_clk(void) +-{ +- u32 arm_div = 0, fi = 0, fd = 0; +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); +- fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); +- return fi / (arm_div * fd); +-} +- +-static u32 get_ipg_clk(void) +-{ +- u32 freq = get_mcu_main_clk(); +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- u32 pdr0 = readl(&ccm->pdr0); +- +- return freq / (get_ahb_div(pdr0) * 2); +-} +- +-static u32 get_ipg_per_clk(void) +-{ +- u32 freq = get_mcu_main_clk(); +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- u32 pdr0 = readl(&ccm->pdr0); +- u32 pdr4 = readl(&ccm->pdr4); +- u32 div; +- if (pdr0 & MXC_CCM_PDR0_PER_SEL) { +- div = CCM_GET_DIVIDER(pdr4, +- MXC_CCM_PDR4_PER0_PODF_MASK, +- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; +- } else { +- div = CCM_GET_DIVIDER(pdr0, +- MXC_CCM_PDR0_PER_PODF_MASK, +- MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; +- div *= get_ahb_div(pdr0); +- } +- return freq / div; +-} +- +-u32 imx_get_uartclk(void) +-{ +- u32 freq; +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- u32 pdr4 = readl(&ccm->pdr4); +- +- if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) +- freq = get_mcu_main_clk(); +- else +- freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); +- freq /= CCM_GET_DIVIDER(pdr4, +- MXC_CCM_PDR4_UART_PODF_MASK, +- MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; +- return freq; +-} +- +-unsigned int mxc_get_main_clock(enum mxc_main_clock clk) +-{ +- u32 nfc_pdf, hsp_podf; +- u32 pll, ret_val = 0, usb_podf; +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- +- u32 reg = readl(&ccm->pdr0); +- u32 reg4 = readl(&ccm->pdr4); +- +- reg |= 0x1; +- +- switch (clk) { +- case CPU_CLK: +- ret_val = get_mcu_main_clk(); +- break; +- case AHB_CLK: +- ret_val = get_mcu_main_clk(); +- break; +- case HSP_CLK: +- if (reg & CLKMODE_CONSUMER) { +- hsp_podf = (reg >> 20) & 0x3; +- pll = get_mcu_main_clk(); +- hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; +- if (hsp_podf > 0) { +- ret_val = pll / hsp_podf; +- } else { +- puts("mismatch HSP with ARM clock setting\n"); +- ret_val = 0; +- } +- } else { +- ret_val = get_mcu_main_clk(); +- } +- break; +- case IPG_CLK: +- ret_val = get_ipg_clk(); +- break; +- case IPG_PER_CLK: +- ret_val = get_ipg_per_clk(); +- break; +- case NFC_CLK: +- nfc_pdf = (reg4 >> 28) & 0xF; +- pll = get_mcu_main_clk(); +- /* AHB/nfc_pdf */ +- ret_val = pll / (nfc_pdf + 1); +- break; +- case USB_CLK: +- usb_podf = (reg4 >> 22) & 0x3F; +- if (reg4 & 0x200) +- pll = get_mcu_main_clk(); +- else +- pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); +- +- ret_val = pll / (usb_podf + 1); +- break; +- default: +- printf("Unknown clock: %d\n", clk); +- break; +- } +- +- return ret_val; +-} +-unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) +-{ +- u32 ret_val = 0, pdf, pre_pdf, clk_sel; +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- u32 mpdr2 = readl(&ccm->pdr2); +- u32 mpdr3 = readl(&ccm->pdr3); +- u32 mpdr4 = readl(&ccm->pdr4); +- +- switch (clk) { +- case UART1_BAUD: +- case UART2_BAUD: +- case UART3_BAUD: +- clk_sel = mpdr3 & (1 << 14); +- pdf = (mpdr4 >> 10) & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); +- break; +- case SSI1_BAUD: +- pre_pdf = (mpdr2 >> 24) & 0x7; +- pdf = mpdr2 & 0x3F; +- clk_sel = mpdr2 & (1 << 6); +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / +- ((pre_pdf + 1) * (pdf + 1)); +- break; +- case SSI2_BAUD: +- pre_pdf = (mpdr2 >> 27) & 0x7; +- pdf = (mpdr2 >> 8) & 0x3F; +- clk_sel = mpdr2 & (1 << 6); +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / +- ((pre_pdf + 1) * (pdf + 1)); +- break; +- case CSI_BAUD: +- clk_sel = mpdr2 & (1 << 7); +- pdf = (mpdr2 >> 16) & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); +- break; +- case MSHC_CLK: +- pre_pdf = readl(&ccm->pdr1); +- clk_sel = (pre_pdf & 0x80); +- pdf = (pre_pdf >> 22) & 0x3F; +- pre_pdf = (pre_pdf >> 28) & 0x7; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / +- ((pre_pdf + 1) * (pdf + 1)); +- break; +- case ESDHC1_CLK: +- clk_sel = mpdr3 & 0x40; +- pdf = mpdr3 & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); +- break; +- case ESDHC2_CLK: +- clk_sel = mpdr3 & 0x40; +- pdf = (mpdr3 >> 8) & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); +- break; +- case ESDHC3_CLK: +- clk_sel = mpdr3 & 0x40; +- pdf = (mpdr3 >> 16) & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); +- break; +- case SPDIF_CLK: +- clk_sel = mpdr3 & 0x400000; +- pre_pdf = (mpdr3 >> 29) & 0x7; +- pdf = (mpdr3 >> 23) & 0x3F; +- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : +- decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / +- ((pre_pdf + 1) * (pdf + 1)); +- break; +- default: +- printf("%s(): This clock: %d not supported yet\n", +- __func__, clk); +- break; +- } +- +- return ret_val; +-} +- +-unsigned int mxc_get_clock(enum mxc_clock clk) +-{ +- switch (clk) { +- case MXC_ARM_CLK: +- return get_mcu_main_clk(); +- case MXC_AHB_CLK: +- break; +- case MXC_IPG_CLK: +- return get_ipg_clk(); +- case MXC_IPG_PERCLK: +- case MXC_I2C_CLK: +- return get_ipg_per_clk(); +- case MXC_UART_CLK: +- return imx_get_uartclk(); +- case MXC_ESDHC1_CLK: +- return mxc_get_peri_clock(ESDHC1_CLK); +- case MXC_ESDHC2_CLK: +- return mxc_get_peri_clock(ESDHC2_CLK); +- case MXC_ESDHC3_CLK: +- return mxc_get_peri_clock(ESDHC3_CLK); +- case MXC_USB_CLK: +- return mxc_get_main_clock(USB_CLK); +- case MXC_FEC_CLK: +- return get_ipg_clk(); +- case MXC_CSPI_CLK: +- return get_ipg_clk(); +- } +- return -1; +-} +- +-#ifdef CONFIG_FEC_MXC +-/* +- * The MX35 has no fuse for MAC, return a NULL MAC +- */ +-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +-{ +- memset(mac, 0, 6); +-} +- +-u32 imx_get_fecclk(void) +-{ +- return mxc_get_clock(MXC_IPG_CLK); +-} +-#endif +- +-int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, +- char *const argv[]) +-{ +- u32 cpufreq = get_mcu_main_clk(); +- printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); +- printf("ipg clock : %dHz\n", get_ipg_clk()); +- printf("ipg per clock : %dHz\n", get_ipg_per_clk()); +- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); +- +- return 0; +-} +- +-U_BOOT_CMD( +- clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, +- "display clocks", +- "" +-); +- +-#if defined(CONFIG_DISPLAY_CPUINFO) +-static char *get_reset_cause(void) +-{ +- /* read RCSR register from CCM module */ +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- +- u32 cause = readl(&ccm->rcsr) & 0x0F; +- +- switch (cause) { +- case 0x0000: +- return "POR"; +- case 0x0002: +- return "JTAG"; +- case 0x0004: +- return "RST"; +- case 0x0008: +- return "WDOG"; +- default: +- return "unknown reset"; +- } +-} +- +-int print_cpuinfo(void) +-{ +- u32 srev = get_cpu_rev(); +- +- printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", +- (srev & 0xF0) >> 4, (srev & 0x0F), +- get_mcu_main_clk() / 1000000); +- +- printf("Reset cause: %s\n", get_reset_cause()); +- +- return 0; +-} +-#endif +- +-/* +- * Initializes on-chip ethernet controllers. +- * to override, implement board_eth_init() +- */ +-int cpu_eth_init(struct bd_info *bis) +-{ +- int rc = -ENODEV; +- +-#if defined(CONFIG_FEC_MXC) +- rc = fecmxc_initialize(bis); +-#endif +- +- return rc; +-} +- +-#ifdef CONFIG_FSL_ESDHC_IMX +-/* +- * Initializes on-chip MMC controllers. +- * to override, implement board_mmc_init() +- */ +-int cpu_mmc_init(struct bd_info *bis) +-{ +- return fsl_esdhc_mmc_init(bis); +-} +-#endif +- +-int get_clocks(void) +-{ +-#ifdef CONFIG_FSL_ESDHC_IMX +-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR +- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR +- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); +-#else +- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); +-#endif +-#endif +- return 0; +-} +- +-#define RCSR_MEM_CTL_WEIM 0 +-#define RCSR_MEM_CTL_NAND 1 +-#define RCSR_MEM_CTL_ATA 2 +-#define RCSR_MEM_CTL_EXPANSION 3 +-#define RCSR_MEM_TYPE_NOR 0 +-#define RCSR_MEM_TYPE_ONENAND 2 +-#define RCSR_MEM_TYPE_SD 0 +-#define RCSR_MEM_TYPE_I2C 2 +-#define RCSR_MEM_TYPE_SPI 3 +- +-u32 spl_boot_device(void) +-{ +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- +- u32 rcsr = readl(&ccm->rcsr); +- u32 mem_type, mem_ctl; +- +- /* In external mode, no boot device is returned */ +- if ((rcsr >> 10) & 0x03) +- return BOOT_DEVICE_NONE; +- +- mem_ctl = (rcsr >> 25) & 0x03; +- mem_type = (rcsr >> 23) & 0x03; +- +- switch (mem_ctl) { +- case RCSR_MEM_CTL_WEIM: +- switch (mem_type) { +- case RCSR_MEM_TYPE_NOR: +- return BOOT_DEVICE_NOR; +- case RCSR_MEM_TYPE_ONENAND: +- return BOOT_DEVICE_ONENAND; +- default: +- return BOOT_DEVICE_NONE; +- } +- case RCSR_MEM_CTL_NAND: +- return BOOT_DEVICE_NAND; +- case RCSR_MEM_CTL_EXPANSION: +- switch (mem_type) { +- case RCSR_MEM_TYPE_SD: +- return BOOT_DEVICE_MMC1; +- case RCSR_MEM_TYPE_I2C: +- return BOOT_DEVICE_I2C; +- case RCSR_MEM_TYPE_SPI: +- return BOOT_DEVICE_SPI; +- default: +- return BOOT_DEVICE_NONE; +- } +- } +- +- return BOOT_DEVICE_NONE; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/mx35/Makefile u-boot/arch/arm/cpu/arm1136/mx35/Makefile +--- u-boot-2021.10/arch/arm/cpu/arm1136/mx35/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/mx35/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,11 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2000-2006 +-# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +-# +-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +- +-obj-y += generic.o +-obj-y += timer.o +-obj-y += mx35_sdram.o +-obj-y += relocate.o +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/mx35/mx35_sdram.c u-boot/arch/arm/cpu/arm1136/mx35/mx35_sdram.c +--- u-boot-2021.10/arch/arm/cpu/arm1136/mx35/mx35_sdram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/mx35/mx35_sdram.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,120 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2012, Stefano Babic +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#define ESDCTL_DDR2_EMR2 0x04000000 +-#define ESDCTL_DDR2_EMR3 0x06000000 +-#define ESDCTL_PRECHARGE 0x00000400 +-#define ESDCTL_DDR2_EN_DLL 0x02000400 +-#define ESDCTL_DDR2_RESET_DLL 0x00000333 +-#define ESDCTL_DDR2_MR 0x00000233 +-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 +- +-enum { +- SMODE_NORMAL = 0, +- SMODE_PRECHARGE, +- SMODE_AUTO_REFRESH, +- SMODE_LOAD_REG, +- SMODE_MANUAL_REFRESH +-}; +- +-#define set_mode(x, en, m) (x | (en << 31) | (m << 28)) +- +-static inline void dram_wait(unsigned int count) +-{ +- volatile unsigned int wait = count; +- +- while (wait--) +- ; +- +-} +- +-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, +- u32 row, u32 col, u32 dsize, u32 refresh) +-{ +- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; +- u32 *cfg_reg, *ctl_reg; +- u32 val; +- u32 ctlval; +- +- switch (start_address) { +- case CSD0_BASE_ADDR: +- cfg_reg = &esdc->esdcfg0; +- ctl_reg = &esdc->esdctl0; +- break; +- case CSD1_BASE_ADDR: +- cfg_reg = &esdc->esdcfg1; +- ctl_reg = &esdc->esdctl1; +- break; +- default: +- return; +- } +- +- /* The MX35 supports 11 up to 14 rows */ +- if (row < 11 || row > 14 || col < 8 || col > 10) +- return; +- ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16); +- +- /* Initialize MISC register for DDR2 */ +- val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST | +- ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN; +- writel(val, &esdc->esdmisc); +- val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST); +- writel(val, &esdc->esdmisc); +- +- /* +- * according to DDR2 specs, wait a while before +- * the PRECHARGE_ALL command +- */ +- dram_wait(0x20000); +- +- /* Load DDR2 config and timing */ +- writel(ddr2_config, cfg_reg); +- +- /* Precharge ALL */ +- writel(set_mode(ctlval, 1, SMODE_PRECHARGE), +- ctl_reg); +- writel(0xda, start_address + ESDCTL_PRECHARGE); +- +- /* Load mode */ +- writel(set_mode(ctlval, 1, SMODE_LOAD_REG), +- ctl_reg); +- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ +- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ +- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ +- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ +- +- /* Precharge ALL */ +- writel(set_mode(ctlval, 1, SMODE_PRECHARGE), +- ctl_reg); +- writel(0xda, start_address + ESDCTL_PRECHARGE); +- +- /* Set mode auto refresh : at least two refresh are required */ +- writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH), +- ctl_reg); +- writel(0xda, start_address); +- writel(0xda, start_address); +- +- writel(set_mode(ctlval, 1, SMODE_LOAD_REG), +- ctl_reg); +- writeb(0xda, start_address + ESDCTL_DDR2_MR); +- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); +- +- /* OCD mode exit */ +- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ +- +- /* Set normal mode */ +- writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh, +- ctl_reg); +- +- dram_wait(0x20000); +- +- /* Do not set delay lines, only for MDDR */ +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/mx35/relocate.S u-boot/arch/arm/cpu/arm1136/mx35/relocate.S +--- u-boot-2021.10/arch/arm/cpu/arm1136/mx35/relocate.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/mx35/relocate.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * relocate - i.MX35-specific vector relocation +- * +- * Copyright (c) 2013 Albert ARIBAUD +- */ +- +-#include +- +-/* +- * The i.MX35 SoC is very specific with respect to exceptions: it +- * does not provide RAM at the high vectors address (0xFFFF0000), +- * thus only the low address (0x00000000) is useable; but that is +- * in ROM, so let's avoid relocating the vectors. +- */ +- .section .text.relocate_vectors,"ax",%progbits +- +-ENTRY(relocate_vectors) +- +- bx lr +- +-ENDPROC(relocate_vectors) +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/mx35/timer.c u-boot/arch/arm/cpu/arm1136/mx35/timer.c +--- u-boot-2021.10/arch/arm/cpu/arm1136/mx35/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/mx35/timer.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,46 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2007 +- * Sascha Hauer, Pengutronix +- * +- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* General purpose timers bitfields */ +-#define GPTCR_SWR (1<<15) /* Software reset */ +-#define GPTCR_FRR (1<<9) /* Freerun / restart */ +-#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ +-#define GPTCR_TEN (1) /* Timer enable */ +- +-/* +- * nothing really to do with interrupts, just starts up a counter. +- * The 32KHz 32-bit timer overruns in 134217 seconds +- */ +-int timer_init(void) +-{ +- int i; +- struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; +- struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; +- +- /* setup GP Timer 1 */ +- writel(GPTCR_SWR, &gpt->ctrl); +- +- writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); +- +- for (i = 0; i < 100; i++) +- writel(0, &gpt->ctrl); /* We have no udelay by now */ +- writel(0, &gpt->pre); /* prescaler = 1 */ +- /* Freerun Mode, 32KHz input */ +- writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, +- &gpt->ctrl); +- writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); +- +- return 0; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm1136/start.S u-boot/arch/arm/cpu/arm1136/start.S +--- u-boot-2021.10/arch/arm/cpu/arm1136/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm1136/start.S 2021-11-01 17:10:13.546298348 +0100 +@@ -39,7 +39,7 @@ + msr cpsr,r0 + + /* the mask ROM code should have PLL and others stable */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -62,7 +62,7 @@ + * + ************************************************************************* + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + cpu_init_crit: + /* + * flush v4 I/D caches +@@ -81,7 +81,7 @@ + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. +@@ -91,4 +91,4 @@ + mov lr, ip /* restore link */ + #endif + mov pc, lr /* back to my caller */ +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm720t/start.S u-boot/arch/arm/cpu/arm720t/start.S +--- u-boot-2021.10/arch/arm/cpu/arm720t/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm720t/start.S 2021-11-01 17:10:13.546298348 +0100 +@@ -37,8 +37,8 @@ + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ +- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ ++ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + bl cpu_init_crit + #endif + +@@ -62,8 +62,8 @@ + ************************************************************************* + */ + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ +- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ ++ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + cpu_init_crit: + + mov ip, lr +@@ -76,4 +76,4 @@ + mov lr, ip + + mov pc, lr +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm920t/start.S u-boot/arch/arm/cpu/arm920t/start.S +--- u-boot-2021.10/arch/arm/cpu/arm920t/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm920t/start.S 2021-11-01 17:10:13.546298348 +0100 +@@ -35,25 +35,11 @@ + orr r0, r0, #0xd3 + msr cpsr, r0 + +-#if defined(CONFIG_AT91RM9200DK) +- /* +- * relocate exception table +- */ +- ldr r0, =_start +- ldr r1, =0x0 +- mov r2, #16 +-copyex: +- subs r2, r2, #1 +- ldr r3, [r0], #4 +- str r3, [r1], #4 +- bne copyex +-#endif +- + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -78,7 +64,7 @@ + */ + + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + cpu_init_crit: + /* + * flush v4 I/D caches +@@ -97,7 +83,7 @@ + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will +@@ -109,4 +95,4 @@ + mov lr, ip + #endif + mov pc, lr +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/cpu.c u-boot/arch/arm/cpu/arm926ejs/armada100/cpu.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/armada100/cpu.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,93 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar +- * Contributor: Mahavir Jain +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) +-#define SET_MRVL_ID (1<<8) +-#define L2C_RAM_SEL (1<<4) +- +-int arch_cpu_init(void) +-{ +- u32 val; +- struct armd1cpu_registers *cpuregs = +- (struct armd1cpu_registers *) ARMD1_CPU_BASE; +- +- struct armd1apb1_registers *apb1clkres = +- (struct armd1apb1_registers *) ARMD1_APBC1_BASE; +- +- struct armd1mpmu_registers *mpmu = +- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; +- +- /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */ +- val = readl(&cpuregs->cpu_conf); +- val = val | SET_MRVL_ID; +- writel(val, &cpuregs->cpu_conf); +- +- /* Enable Clocks for all hardware units */ +- writel(0xFFFFFFFF, &mpmu->acgr); +- +- /* Turn on AIB and AIB-APB Functional clock */ +- writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib); +- +- /* ensure L2 cache is not mapped as SRAM */ +- val = readl(&cpuregs->cpu_conf); +- val = val & ~(L2C_RAM_SEL); +- writel(val, &cpuregs->cpu_conf); +- +- /* Enable GPIO clock */ +- writel(APBC_APBCLK, &apb1clkres->gpio); +- +-#ifdef CONFIG_I2C_MV +- /* Enable general I2C clock */ +- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); +- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); +- +- /* Enable power I2C clock */ +- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); +- writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); +-#endif +- +- /* +- * Enable Functional and APB clock at 14.7456MHz +- * for configured UART console +- */ +-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE) +- writel(UARTCLK14745KHZ, &apb1clkres->uart3); +-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE) +- writel(UARTCLK14745KHZ, &apb1clkres->uart2); +-#else +- writel(UARTCLK14745KHZ, &apb1clkres->uart1); +-#endif +- icache_enable(); +- +- return 0; +-} +- +-#if defined(CONFIG_DISPLAY_CPUINFO) +-int print_cpuinfo(void) +-{ +- u32 id; +- struct armd1cpu_registers *cpuregs = +- (struct armd1cpu_registers *) ARMD1_CPU_BASE; +- +- id = readl(&cpuregs->chip_id); +- printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); +- return 0; +-} +-#endif +- +-#ifdef CONFIG_I2C_MV +-void i2c_clk_enable(void) +-{ +-} +-#endif +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/dram.c u-boot/arch/arm/cpu/arm926ejs/armada100/dram.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/dram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/armada100/dram.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,117 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar , +- * Contributor: Mahavir Jain +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-DECLARE_GLOBAL_DATA_PTR; +- +-/* +- * ARMADA100 DRAM controller supports upto 8 banks +- * for chip select 0 and 1 +- */ +- +-/* +- * DDR Memory Control Registers +- * Refer Datasheet Appendix A.17 +- */ +-struct armd1ddr_map_registers { +- u32 cs; /* Memory Address Map Register -CS */ +- u32 pad[3]; +-}; +- +-struct armd1ddr_registers { +- u8 pad[0x100 - 0x000]; +- struct armd1ddr_map_registers mmap[2]; +-}; +- +-/* +- * armd1_sdram_base - reads SDRAM Base Address Register +- */ +-u32 armd1_sdram_base(int chip_sel) +-{ +- struct armd1ddr_registers *ddr_regs = +- (struct armd1ddr_registers *)ARMD1_DRAM_BASE; +- u32 result = 0; +- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); +- +- if (!CS_valid) +- return 0; +- +- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; +- return result; +-} +- +-/* +- * armd1_sdram_size - reads SDRAM size +- */ +-u32 armd1_sdram_size(int chip_sel) +-{ +- struct armd1ddr_registers *ddr_regs = +- (struct armd1ddr_registers *)ARMD1_DRAM_BASE; +- u32 result = 0; +- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); +- +- if (!CS_valid) +- return 0; +- +- result = readl(&ddr_regs->mmap[chip_sel].cs); +- result = (result >> 16) & 0xF; +- if (result < 0x7) { +- printf("Unknown DRAM Size\n"); +- return -1; +- } else { +- return ((0x8 << (result - 0x7)) * 1024 * 1024); +- } +-} +- +-int dram_init(void) +-{ +- int i; +- +- gd->ram_size = 0; +- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { +- gd->bd->bi_dram[i].start = armd1_sdram_base(i); +- gd->bd->bi_dram[i].size = armd1_sdram_size(i); +- /* +- * It is assumed that all memory banks are consecutive +- * and without gaps. +- * If the gap is found, ram_size will be reported for +- * consecutive memory only +- */ +- if (gd->bd->bi_dram[i].start != gd->ram_size) +- break; +- +- gd->ram_size += gd->bd->bi_dram[i].size; +- +- } +- +- for (; i < CONFIG_NR_DRAM_BANKS; i++) { +- /* If above loop terminated prematurely, we need to set +- * remaining banks' start address & size as 0. Otherwise other +- * u-boot functions and Linux kernel gets wrong values which +- * could result in crash */ +- gd->bd->bi_dram[i].start = 0; +- gd->bd->bi_dram[i].size = 0; +- } +- return 0; +-} +- +-/* +- * If this function is not defined here, +- * board.c alters dram bank zero configuration defined above. +- */ +-int dram_init_banksize(void) +-{ +- dram_init(); +- +- return 0; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/Makefile u-boot/arch/arm/cpu/arm926ejs/armada100/Makefile +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/armada100/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,7 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2010 +-# Marvell Semiconductor +-# Written-by: Prafulla Wadaskar +- +-obj-y = cpu.o timer.o dram.o +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/timer.c u-boot/arch/arm/cpu/arm926ejs/armada100/timer.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/armada100/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/armada100/timer.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,198 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar +- * Contributor: Mahavir Jain +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* +- * Timer registers +- * Refer Section A.6 in Datasheet +- */ +-struct armd1tmr_registers { +- u32 clk_ctrl; /* Timer clk control reg */ +- u32 match[9]; /* Timer match registers */ +- u32 count[3]; /* Timer count registers */ +- u32 status[3]; +- u32 ie[3]; +- u32 preload[3]; /* Timer preload value */ +- u32 preload_ctrl[3]; +- u32 wdt_match_en; +- u32 wdt_match_r; +- u32 wdt_val; +- u32 wdt_sts; +- u32 icr[3]; +- u32 wdt_icr; +- u32 cer; /* Timer count enable reg */ +- u32 cmr; +- u32 ilr[3]; +- u32 wcr; +- u32 wfar; +- u32 wsar; +- u32 cvwr; +-}; +- +-#define TIMER 0 /* Use TIMER 0 */ +-/* Each timer has 3 match registers */ +-#define MATCH_CMP(x) ((3 * TIMER) + x) +-#define TIMER_LOAD_VAL 0xffffffff +-#define COUNT_RD_REQ 0x1 +- +-DECLARE_GLOBAL_DATA_PTR; +-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ +- +-/* For preventing risk of instability in reading counter value, +- * first set read request to register cvwr and then read same +- * register after it captures counter value. +- */ +-ulong read_timer(void) +-{ +- struct armd1tmr_registers *armd1timers = +- (struct armd1tmr_registers *) ARMD1_TIMER_BASE; +- volatile int loop=100; +- +- writel(COUNT_RD_REQ, &armd1timers->cvwr); +- while (loop--); +- return(readl(&armd1timers->cvwr)); +-} +- +-static ulong get_timer_masked(void) +-{ +- ulong now = read_timer(); +- +- if (now >= gd->arch.tbl) { +- /* normal mode */ +- gd->arch.tbu += now - gd->arch.tbl; +- } else { +- /* we have an overflow ... */ +- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; +- } +- gd->arch.tbl = now; +- +- return gd->arch.tbu; +-} +- +-ulong get_timer(ulong base) +-{ +- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - +- base); +-} +- +-void __udelay(unsigned long usec) +-{ +- ulong delayticks; +- ulong endtime; +- +- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); +- endtime = get_timer_masked() + delayticks; +- +- while (get_timer_masked() < endtime); +-} +- +-/* +- * init the Timer +- */ +-int timer_init(void) +-{ +- struct armd1apb1_registers *apb1clkres = +- (struct armd1apb1_registers *) ARMD1_APBC1_BASE; +- struct armd1tmr_registers *armd1timers = +- (struct armd1tmr_registers *) ARMD1_TIMER_BASE; +- +- /* Enable Timer clock at 3.25 MHZ */ +- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); +- +- /* load value into timer */ +- writel(0x0, &armd1timers->clk_ctrl); +- /* Use Timer 0 Match Resiger 0 */ +- writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); +- /* Preload value is 0 */ +- writel(0x0, &armd1timers->preload[TIMER]); +- /* Enable match comparator 0 for Timer 0 */ +- writel(0x1, &armd1timers->preload_ctrl[TIMER]); +- +- /* Enable timer 0 */ +- writel(0x1, &armd1timers->cer); +- /* init the gd->arch.tbu and gd->arch.tbl value */ +- gd->arch.tbl = read_timer(); +- gd->arch.tbu = 0; +- +- return 0; +-} +- +-#define MPMU_APRR_WDTR (1<<4) +-#define TMR_WFAR 0xbaba /* WDT Register First key */ +-#define TMP_WSAR 0xeb10 /* WDT Register Second key */ +- +-/* +- * This function uses internal Watchdog Timer +- * based reset mechanism. +- * Steps to write watchdog registers (protected access) +- * 1. Write key value to TMR_WFAR reg. +- * 2. Write key value to TMP_WSAR reg. +- * 3. Perform write operation. +- */ +-void reset_cpu(void) +-{ +- struct armd1mpmu_registers *mpmu = +- (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; +- struct armd1tmr_registers *armd1timers = +- (struct armd1tmr_registers *) ARMD1_TIMER_BASE; +- u32 val; +- +- /* negate hardware reset to the WDT after system reset */ +- val = readl(&mpmu->aprr); +- val = val | MPMU_APRR_WDTR; +- writel(val, &mpmu->aprr); +- +- /* reset/enable WDT clock */ +- writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); +- readl(&mpmu->wdtpcr); +- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); +- readl(&mpmu->wdtpcr); +- +- /* clear previous WDT status */ +- writel(TMR_WFAR, &armd1timers->wfar); +- writel(TMP_WSAR, &armd1timers->wsar); +- writel(0, &armd1timers->wdt_sts); +- +- /* set match counter */ +- writel(TMR_WFAR, &armd1timers->wfar); +- writel(TMP_WSAR, &armd1timers->wsar); +- writel(0xf, &armd1timers->wdt_match_r); +- +- /* enable WDT reset */ +- writel(TMR_WFAR, &armd1timers->wfar); +- writel(TMP_WSAR, &armd1timers->wsar); +- writel(0x3, &armd1timers->wdt_match_en); +- +- while(1); +-} +- +-/* +- * This function is derived from PowerPC code (read timebase as long long). +- * On ARM it just returns the timer value. +- */ +-unsigned long long get_ticks(void) +-{ +- return get_timer(0); +-} +- +-/* +- * This function is derived from PowerPC code (timebase clock frequency). +- * On ARM it returns the number of timer ticks per second. +- */ +-ulong get_tbclk(void) +-{ +- return (ulong)CONFIG_SYS_HZ; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/cache.c u-boot/arch/arm/cpu/arm926ejs/cache.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/cache.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/cache.c 2021-11-01 17:10:13.546298348 +0100 +@@ -89,4 +89,3 @@ + dcache_enable(); + #endif + } +- +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/Makefile u-boot/arch/arm/cpu/arm926ejs/Makefile +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/Makefile 2021-11-01 17:10:13.546298348 +0100 +@@ -12,8 +12,6 @@ + endif + endif + +-obj-$(CONFIG_ARMADA100) += armada100/ +-obj-$(CONFIG_MX25) += mx25/ + obj-$(CONFIG_MX27) += mx27/ + obj-$(if $(filter mxs,$(SOC)),y) += mxs/ + obj-$(if $(filter spear,$(SOC)),y) += spear/ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/generic.c u-boot/arch/arm/cpu/arm926ejs/mx25/generic.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/generic.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mx25/generic.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,274 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2009 DENX Software Engineering +- * Author: John Rigby +- * +- * Based on mx27/generic.c: +- * Copyright (c) 2008 Eric Jarrige +- * Copyright (c) 2009 Ilya Yanok +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#ifdef CONFIG_FSL_ESDHC_IMX +-#include +- +-DECLARE_GLOBAL_DATA_PTR; +-#endif +- +-/* +- * get the system pll clock in Hz +- * +- * mfi + mfn / (mfd +1) +- * f = 2 * f_ref * -------------------- +- * pd + 1 +- */ +-static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) +-{ +- unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) +- & CCM_PLL_MFI_MASK; +- int mfn = (pll >> CCM_PLL_MFN_SHIFT) +- & CCM_PLL_MFN_MASK; +- unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) +- & CCM_PLL_MFD_MASK; +- unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) +- & CCM_PLL_PD_MASK; +- +- mfi = mfi <= 5 ? 5 : mfi; +- mfn = mfn >= 512 ? mfn - 1024 : mfn; +- mfd += 1; +- pd += 1; +- +- return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn), +- mfd * pd); +-} +- +-static ulong imx_get_mpllclk(void) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong fref = MXC_HCLK; +- +- return imx_decode_pll(readl(&ccm->mpctl), fref); +-} +- +-static ulong imx_get_upllclk(void) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong fref = MXC_HCLK; +- +- return imx_decode_pll(readl(&ccm->upctl), fref); +-} +- +-static ulong imx_get_armclk(void) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong cctl = readl(&ccm->cctl); +- ulong fref = imx_get_mpllclk(); +- ulong div; +- +- if (cctl & CCM_CCTL_ARM_SRC) +- fref = lldiv((u64) fref * 3, 4); +- +- div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) +- & CCM_CCTL_ARM_DIV_MASK) + 1; +- +- return fref / div; +-} +- +-static ulong imx_get_ahbclk(void) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong cctl = readl(&ccm->cctl); +- ulong fref = imx_get_armclk(); +- ulong div; +- +- div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) +- & CCM_CCTL_AHB_DIV_MASK) + 1; +- +- return fref / div; +-} +- +-static ulong imx_get_ipgclk(void) +-{ +- return imx_get_ahbclk() / 2; +-} +- +-static ulong imx_get_perclk(int clk) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : +- imx_get_ahbclk(); +- ulong div; +- +- div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); +- div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; +- +- return fref / div; +-} +- +-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk(); +- ulong div = (fref + freq - 1) / freq; +- +- if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK) +- return -EINVAL; +- +- clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)], +- CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk), +- div << CCM_PERCLK_SHIFT(clk)); +- if (from_upll) +- setbits_le32(&ccm->mcr, 1 << clk); +- else +- clrbits_le32(&ccm->mcr, 1 << clk); +- return 0; +-} +- +-unsigned int mxc_get_clock(enum mxc_clock clk) +-{ +- if (clk >= MXC_CLK_NUM) +- return -1; +- switch (clk) { +- case MXC_ARM_CLK: +- return imx_get_armclk(); +- case MXC_AHB_CLK: +- return imx_get_ahbclk(); +- case MXC_IPG_CLK: +- case MXC_CSPI_CLK: +- case MXC_FEC_CLK: +- return imx_get_ipgclk(); +- default: +- return imx_get_perclk(clk); +- } +-} +- +-u32 get_cpu_rev(void) +-{ +- u32 srev; +- u32 system_rev = 0x25000; +- +- /* read SREV register from IIM module */ +- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; +- srev = readl(&iim->iim_srev); +- +- switch (srev) { +- case 0x00: +- system_rev |= CHIP_REV_1_0; +- break; +- case 0x01: +- system_rev |= CHIP_REV_1_1; +- break; +- case 0x02: +- system_rev |= CHIP_REV_1_2; +- break; +- default: +- system_rev |= 0x8000; +- break; +- } +- +- return system_rev; +-} +- +-#if defined(CONFIG_DISPLAY_CPUINFO) +-static char *get_reset_cause(void) +-{ +- /* read RCSR register from CCM module */ +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- +- u32 cause = readl(&ccm->rcsr) & 0x0f; +- +- if (cause == 0) +- return "POR"; +- else if (cause == 1) +- return "RST"; +- else if ((cause & 2) == 2) +- return "WDOG"; +- else if ((cause & 4) == 4) +- return "SW RESET"; +- else if ((cause & 8) == 8) +- return "JTAG"; +- else +- return "unknown reset"; +- +-} +- +-int print_cpuinfo(void) +-{ +- char buf[32]; +- u32 cpurev = get_cpu_rev(); +- +- printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", +- (cpurev & 0xF0) >> 4, (cpurev & 0x0F), +- ((cpurev & 0x8000) ? " unknown" : ""), +- strmhz(buf, imx_get_armclk())); +- printf("Reset cause: %s\n", get_reset_cause()); +- return 0; +-} +-#endif +- +-#if defined(CONFIG_FEC_MXC) +-/* +- * Initializes on-chip ethernet controllers. +- * to override, implement board_eth_init() +- */ +-int cpu_eth_init(struct bd_info *bis) +-{ +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- ulong val; +- +- val = readl(&ccm->cgr0); +- val |= (1 << 23); +- writel(val, &ccm->cgr0); +- return fecmxc_initialize(bis); +-} +-#endif +- +-int get_clocks(void) +-{ +-#ifdef CONFIG_FSL_ESDHC_IMX +-#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE +- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +-#else +- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); +-#endif +-#endif +- return 0; +-} +- +-#ifdef CONFIG_FSL_ESDHC_IMX +-/* +- * Initializes on-chip MMC controllers. +- * to override, implement board_mmc_init() +- */ +-int cpu_mmc_init(struct bd_info *bis) +-{ +- return fsl_esdhc_mmc_init(bis); +-} +-#endif +- +-#ifdef CONFIG_FEC_MXC +-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +-{ +- int i; +- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; +- struct fuse_bank *bank = &iim->bank[0]; +- struct fuse_bank0_regs *fuse = +- (struct fuse_bank0_regs *)bank->fuse_regs; +- +- for (i = 0; i < 6; i++) +- mac[i] = readl(&fuse->mac_addr[i]) & 0xff; +-} +-#endif /* CONFIG_FEC_MXC */ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/Makefile u-boot/arch/arm/cpu/arm926ejs/mx25/Makefile +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mx25/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,7 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2000-2006 +-# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +-# +- +-obj-y += generic.o timer.o reset.o relocate.o +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/relocate.S u-boot/arch/arm/cpu/arm926ejs/mx25/relocate.S +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/relocate.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mx25/relocate.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1,22 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * relocate - i.MX25-specific vector relocation +- * +- * Copyright (c) 2013 Albert ARIBAUD +- */ +- +-#include +- +-/* +- * The i.MX25 SoC is very specific with respect to exceptions: it +- * does not provide RAM at the high vectors address (0xFFFF0000), +- * thus only the low address (0x00000000) is useable; but that is +- * in ROM, so let's avoid relocating the vectors. +- */ +- .section .text.relocate_vectors,"ax",%progbits +- +-ENTRY(relocate_vectors) +- +- bx lr +- +-ENDPROC(relocate_vectors) +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/reset.c u-boot/arch/arm/cpu/arm926ejs/mx25/reset.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/reset.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mx25/reset.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,40 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2002 +- * Sysgo Real-Time Solutions, GmbH +- * Marius Groeger +- * +- * (C) Copyright 2002 +- * Sysgo Real-Time Solutions, GmbH +- * Alex Zuepke +- * +- * (C) Copyright 2002 +- * Gary Jennejohn, DENX Software Engineering, +- * +- * (C) Copyright 2009 +- * Ilya Yanok, Emcraft Systems Ltd, +- */ +- +-#include +-#include +-#include +-#include +- +-/* +- * Reset the cpu by setting up the watchdog timer and let it time out +- */ +-void reset_cpu(void) +-{ +- struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; +- /* Disable watchdog and set Time-Out field to 0 */ +- writew(0, ®s->wcr); +- +- /* Write Service Sequence */ +- writew(WSR_UNLOCK1, ®s->wsr); +- writew(WSR_UNLOCK2, ®s->wsr); +- +- /* Enable watchdog */ +- writew(WCR_WDE, ®s->wcr); +- +- while (1) ; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/timer.c u-boot/arch/arm/cpu/arm926ejs/mx25/timer.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mx25/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mx25/timer.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,50 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2002 +- * Sysgo Real-Time Solutions, GmbH +- * Marius Groeger +- * +- * (C) Copyright 2002 +- * Sysgo Real-Time Solutions, GmbH +- * Alex Zuepke +- * +- * (C) Copyright 2002 +- * Gary Jennejohn, DENX Software Engineering, +- * +- * (C) Copyright 2009 +- * Ilya Yanok, Emcraft Systems Ltd, +- * +- * (C) Copyright 2009 DENX Software Engineering +- * Author: John Rigby +- * Add support for MX25 +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-/* nothing really to do with interrupts, just starts up a counter. */ +-/* The 32KHz 32-bit timer overruns in 134217 seconds */ +-int timer_init(void) +-{ +- int i; +- struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; +- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; +- +- /* setup GP Timer 1 */ +- writel(GPT_CTRL_SWR, &gpt->ctrl); +- +- writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1); +- +- for (i = 0; i < 100; i++) +- writel(0, &gpt->ctrl); /* We have no udelay by now */ +- writel(0, &gpt->pre); /* prescaler = 1 */ +- /* Freerun Mode, 32KHz input */ +- writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, +- &gpt->ctrl); +- writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); +- +- return 0; +-} +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/mxs/spl_boot.c u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/mxs/spl_boot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c 2021-11-01 17:10:13.549631499 +0100 +@@ -23,7 +23,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + static gd_t gdata __section(".data"); +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + static struct bd_info bdata __section(".data"); + #endif + +@@ -108,7 +108,7 @@ + + static void mxs_spl_console_init(void) + { +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + gd->bd = &bdata; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); +diff -ruN u-boot-2021.10/arch/arm/cpu/arm926ejs/start.S u-boot/arch/arm/cpu/arm926ejs/start.S +--- u-boot-2021.10/arch/arm/cpu/arm926ejs/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm926ejs/start.S 2021-11-01 17:10:13.549631499 +0100 +@@ -46,7 +46,7 @@ + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -69,7 +69,7 @@ + * + ************************************************************************* + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + cpu_init_crit: + /* + * flush D cache before disabling it +@@ -100,7 +100,7 @@ + #endif + mcr p15, 0, r0, c1, c0, 0 + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /* + * Go setup Memory and board specific bits prior to relocation. + */ +@@ -109,4 +109,4 @@ + mov lr, r4 /* restore link */ + #endif + mov pc, lr /* back to my caller */ +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/cpu/arm946es/start.S u-boot/arch/arm/cpu/arm946es/start.S +--- u-boot-2021.10/arch/arm/cpu/arm946es/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/arm946es/start.S 2021-11-01 17:10:13.549631499 +0100 +@@ -45,7 +45,7 @@ + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -70,7 +70,7 @@ + */ + + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + cpu_init_crit: + /* + * flush v4 I/D caches +@@ -89,7 +89,7 @@ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /* + * Go setup Memory and board specific bits prior to relocation. + */ +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/clock.c u-boot/arch/arm/cpu/armv7/ls102xa/clock.c +--- u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/clock.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/ls102xa/clock.c 2021-11-01 17:10:13.549631499 +0100 +@@ -42,8 +42,8 @@ + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sys_info->freq_systembus = sysclk; +-#ifdef CONFIG_DDR_CLK_FREQ +- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) ++ sys_info->freq_ddrbus = get_board_ddr_clk(); + #else + sys_info->freq_ddrbus = sysclk; + #endif +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/Kconfig u-boot/arch/arm/cpu/armv7/ls102xa/Kconfig +--- u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/ls102xa/Kconfig 2021-11-01 17:10:13.549631499 +0100 +@@ -20,6 +20,7 @@ + select SYS_FSL_SEC_LE + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES ++ select SYS_I2C_MXC + imply CMD_PCI + imply SCSI + imply SCSI_AHCI +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/spl.c u-boot/arch/arm/cpu/armv7/ls102xa/spl.c +--- u-boot-2021.10/arch/arm/cpu/armv7/ls102xa/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/ls102xa/spl.c 2021-11-01 17:10:13.552964650 +0100 +@@ -8,7 +8,7 @@ + + u32 spl_boot_device(void) + { +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + return BOOT_DEVICE_MMC1; + #endif + return BOOT_DEVICE_NAND; +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/Makefile u-boot/arch/arm/cpu/armv7/Makefile +--- u-boot-2021.10/arch/arm/cpu/armv7/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/Makefile 2021-11-01 17:10:13.549631499 +0100 +@@ -17,7 +17,7 @@ + obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o + endif + +-ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) ++ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) + obj-y += lowlevel_init.o + endif + +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/psci-common.c u-boot/arch/arm/cpu/armv7/psci-common.c +--- u-boot-2021.10/arch/arm/cpu/armv7/psci-common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/psci-common.c 2021-11-01 17:10:13.552964650 +0100 +@@ -43,4 +43,3 @@ + { + return psci_context_id[cpu]; + } +- +diff -ruN u-boot-2021.10/arch/arm/cpu/armv7/start.S u-boot/arch/arm/cpu/armv7/start.S +--- u-boot-2021.10/arch/arm/cpu/armv7/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv7/start.S 2021-11-01 17:10:13.552964650 +0100 +@@ -39,6 +39,42 @@ + /* Allow the board to save important registers */ + b save_boot_params + save_boot_params_ret: ++#ifdef CONFIG_POSITION_INDEPENDENT ++ /* ++ * Fix .rela.dyn relocations. This allows U-Boot to loaded to and ++ * executed at a different address than it was linked at. ++ */ ++pie_fixup: ++ adr r0, reset /* r0 <- Runtime value of reset label */ ++ ldr r1, =reset /* r1 <- Linked value of reset label */ ++ subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */ ++ beq pie_fixup_done ++ ++ adr r0, pie_fixup ++ ldr r1, _rel_dyn_start_ofs ++ add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */ ++ ldr r1, _rel_dyn_end_ofs ++ add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */ ++ ++pie_fix_loop: ++ ldr r0, [r2] /* r0 <- Link location */ ++ ldr r1, [r2, #4] /* r1 <- fixup */ ++ cmp r1, #23 /* relative fixup? */ ++ bne pie_skip_reloc ++ ++ /* relative fix: increase location by offset */ ++ add r0, r4 ++ ldr r1, [r0] ++ add r1, r4 ++ str r1, [r0] ++ str r0, [r2] ++ add r2, #8 ++pie_skip_reloc: ++ cmp r2, r3 ++ blo pie_fix_loop ++pie_fixup_done: ++#endif ++ + #ifdef CONFIG_ARMV7_LPAE + /* + * check for Hypervisor support +@@ -80,11 +116,11 @@ + #endif + + /* the mask ROM code should have PLL and others stable */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + #ifdef CONFIG_CPU_V7A + bl cpu_init_cp15 + #endif +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + bl cpu_init_crit + #endif + #endif +@@ -320,8 +356,8 @@ + mov pc, r5 @ back to my caller + ENDPROC(cpu_init_cp15) + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ +- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ ++ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /************************************************************************* + * + * CPU_init_critical registers +@@ -340,3 +376,10 @@ + b lowlevel_init @ go setup pll,mux,memory + ENDPROC(cpu_init_crit) + #endif ++ ++#if CONFIG_POSITION_INDEPENDENT ++_rel_dyn_start_ofs: ++ .word __rel_dyn_start - pie_fixup ++_rel_dyn_end_ofs: ++ .word __rel_dyn_end - pie_fixup ++#endif +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/cache.S u-boot/arch/arm/cpu/armv8/cache.S +--- u-boot-2021.10/arch/arm/cpu/armv8/cache.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/cache.S 2021-11-01 17:10:13.556297801 +0100 +@@ -27,13 +27,11 @@ + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ +- and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ ++ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ ++ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ ++ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ +- mov x3, #0x3ff +- and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ +- mov x4, #0x7fff +- and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ +@@ -72,8 +70,7 @@ + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ +- lsr x11, x10, #24 +- and x11, x11, #0x7 /* x11 <- loc */ ++ ubfx x11, x10, #24, #3 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ +@@ -83,8 +80,7 @@ + /* x15 <- return address */ + + loop_level: +- lsl x12, x0, #1 +- add x12, x12, x0 /* x0 <- tripled cache level */ ++ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 +@@ -131,8 +127,7 @@ + .pushsection .text.__asm_flush_dcache_range, "ax" + ENTRY(__asm_flush_dcache_range) + mrs x3, ctr_el0 +- lsr x3, x3, #16 +- and x3, x3, #0xf ++ ubfx x3, x3, #16, #4 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + +@@ -158,7 +153,7 @@ + .pushsection .text.__asm_invalidate_dcache_range, "ax" + ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 +- ubfm x3, x3, #16, #19 ++ ubfx x3, x3, #16, #4 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fel_utils.S u-boot/arch/arm/cpu/armv8/fel_utils.S +--- u-boot-2021.10/arch/arm/cpu/armv8/fel_utils.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fel_utils.S 2021-11-01 17:10:13.556297801 +0100 +@@ -64,18 +64,18 @@ + + /* AArch32 code to restore the state from fel_stash and return back to FEL. */ + back_in_32: +- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address +- .word 0xe5901008 // ldr r1, [r0, #8] +- .word 0xe129f001 // msr CPSR_fc, r1 ++ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address ++ .word 0xe5901008 // ldr r1, [r0, #8] ++ .word 0xe129f001 // msr CPSR_fc, r1 + .word 0xf57ff06f // isb +- .word 0xe590d000 // ldr sp, [r0] +- .word 0xe590e004 // ldr lr, [r0, #4] +- .word 0xe5901010 // ldr r1, [r0, #16] +- .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR +- .word 0xe590100c // ldr r1, [r0, #12] +- .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR ++ .word 0xe590d000 // ldr sp, [r0] ++ .word 0xe590e004 // ldr lr, [r0, #4] ++ .word 0xe5901010 // ldr r1, [r0, #16] ++ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR ++ .word 0xe590100c // ldr r1, [r0, #12] ++ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR + .word 0xf57ff06f // isb +- .word 0xe12fff1e // bx lr ; return to FEL ++ .word 0xe12fff1e // bx lr ; return to FEL + fel_stash_addr: + .word 0x00000000 // receives fel_stash addr, by AA64 code above + ENDPROC(return_to_fel) +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/cpu.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 2021-11-01 17:10:13.556297801 +0100 +@@ -1147,7 +1147,7 @@ + #endif + #ifdef CONFIG_SYS_FSL_HAS_RGMII + /* some dpmacs in armv8a based freescale layerscape SOCs can be +- * configured via both serdes(sgmii, xfi, xlaui etc) bits and via ++ * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via + * EC*_PMUX(rgmii) bits in RCW. + * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from + * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 2021-11-01 17:10:13.556297801 +0100 +@@ -42,22 +42,22 @@ + pre-silicon platforms (simulator and emulator): + + ------------------------- +- | FIT Image | ++ | FIT Image | + | (linux + DTB + RFS) | + ------------------------- ----> 0x0120_0000 +- | Debug Server FW | ++ | Debug Server FW | + ------------------------- ----> 0x00C0_0000 +- | AIOP FW | ++ | AIOP FW | + ------------------------- ----> 0x0070_0000 +- | MC FW | ++ | MC FW | + ------------------------- ----> 0x006C_0000 +- | MC DPL Blob | ++ | MC DPL Blob | + ------------------------- ----> 0x0020_0000 +- | BootLoader + Env| ++ | BootLoader + Env| + ------------------------- ----> 0x0000_1000 +- | PBI | ++ | PBI | + ------------------------- ----> 0x0000_0080 +- | RCW | ++ | RCW | + ------------------------- ----> 0x0000_0000 + + 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) +@@ -70,45 +70,45 @@ + ----------------------------------------- ----> 0x5_8790_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8510_0000 | +- | PHY firmware (2M) | | ++ | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_84F0_0000 | 64K + | Debug Server FW (2M) | | Alt + ----------------------------------------- ----> 0x5_84D0_0000 | Bank + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8490_0000 (vbank4) +- | MC DPC Blob (1M) | | ++ | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8480_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8470_0000 | +- | MC FW (4M) | | ++ | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8430_0000 | +- | BootLoader Environment (1M) | | ++ | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8420_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8410_0000 | +- | RCW and PBI (1M) | | ++ | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8400_0000 --- + | .. Unused .. (7M) | | + ----------------------------------------- ----> 0x5_8390_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8110_0000 | +- | PHY firmware (2M) | | ++ | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_80F0_0000 | 64K + | Debug Server FW (2M) | | Bank + ----------------------------------------- ----> 0x5_80D0_0000 | + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8090_0000 (vbank0) +- | MC DPC Blob (1M) | | ++ | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8080_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8070_0000 | +- | MC FW (4M) | | ++ | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8030_0000 | +- | BootLoader Environment (1M) | | ++ | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8020_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8010_0000 | +- | RCW and PBI (1M) | | ++ | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8000_0000 --- + + 128-MB NOR flash layout for QDS and RDB boards +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 2021-11-01 17:10:13.556297801 +0100 +@@ -31,7 +31,7 @@ + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan +- - Up to 1 x XFI supporting 10G interface ++ - Up to 1 x 10GBase-R supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps +@@ -190,7 +190,7 @@ + - Two PLLs per four-lane SerDes + - Support for 10G operation + - Ethernet interfaces by FMan +- - Up to 2 x XFI supporting 10G interface (MAC 9, 10) ++ - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) + - Up to 1 x QSGMII (MAC 5, 6, 10, 1) + - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) + - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) +@@ -295,7 +295,7 @@ + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) +- Support for XFI (and 10GBase-KR) ++ Support for 10GBase-R (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. +@@ -400,7 +400,7 @@ + Ethernet interfaces + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) +- Support for XFI (and 10GBase-KR) ++ Support for 10GBase-R (and 10GBase-KR) + Support for CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 2021-11-01 17:10:13.556297801 +0100 +@@ -61,8 +61,8 @@ + #endif + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; + +-#ifdef CONFIG_DDR_CLK_FREQ +- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) ++ sys_info->freq_ddrbus = get_board_ddr_clk(); + #else + sys_info->freq_ddrbus = sysclk; + #endif +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 2021-11-01 17:10:13.556297801 +0100 +@@ -78,10 +78,10 @@ + void *offset; + + sys_info->freq_systembus = sysclk; +-#ifdef CONFIG_DDR_CLK_FREQ +- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) ++ sys_info->freq_ddrbus = get_board_ddr_clk(); + #ifdef CONFIG_SYS_FSL_HAS_DP_DDR +- sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; ++ sys_info->freq_ddrbus2 = get_board_ddr_clk(); + #endif + #else + sys_info->freq_ddrbus = sysclk; +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/Kconfig u-boot/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 2021-11-01 17:10:13.556297801 +0100 +@@ -4,6 +4,8 @@ + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE + select FSL_LSCH2 ++ select GICV2 ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR_BE +@@ -25,6 +27,7 @@ + select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE + select FSL_LSCH3 ++ select GICV3 + select NXP_LSCH3_2 + select SYS_FSL_HAS_CCI400 + select SYS_FSL_SRDS_1 +@@ -58,7 +61,9 @@ + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE + select FSL_LSCH2 ++ select GICV2 + select HAS_FSL_XHCI_USB if USB_HOST ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR +@@ -84,13 +89,16 @@ + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C + imply CMD_PCI ++ imply ID_EEPROM + + config ARCH_LS1046A + bool + select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE + select FSL_LSCH2 ++ select GICV2 + select HAS_FSL_XHCI_USB if USB_HOST ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR +@@ -117,8 +125,10 @@ + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C ++ imply ID_EEPROM + imply SCSI + imply SCSI_AHCI ++ imply SPL_SYS_I2C_LEGACY + + config ARCH_LS1088A + bool +@@ -126,6 +136,8 @@ + select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE + select FSL_LSCH3 ++ select GICV3 ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR +@@ -158,7 +170,9 @@ + select SYS_I2C_MXC_I2C3 if !TFABOOT + select SYS_I2C_MXC_I2C4 if !TFABOOT + select RESV_RAM if GIC_V3_ITS ++ imply ID_EEPROM + imply SCSI ++ imply SPL_SYS_I2C_LEGACY + imply PANIC_HANG + + config ARCH_LS2080A +@@ -170,6 +184,8 @@ + select ARM_ERRATA_833471 + select FSL_LAYERSCAPE + select FSL_LSCH3 ++ select GICV3 ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR +@@ -210,12 +226,15 @@ + select SYS_I2C_MXC_I2C4 if !TFABOOT + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS ++ imply ID_EEPROM + imply PANIC_HANG ++ imply SPL_SYS_I2C_LEGACY + + config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 ++ select GICV3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 +@@ -242,11 +261,13 @@ + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI ++ imply SPL_SYS_I2C_LEGACY + + config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 ++ select GICV3 + select HAS_FSL_XHCI_USB if USB_HOST + select NXP_LSCH3_2 + select SYS_HAS_SERDES +@@ -272,12 +293,15 @@ + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS ++ imply ID_EEPROM + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI ++ imply SPL_SYS_I2C_LEGACY + + config FSL_LSCH2 + bool ++ select SKIP_LOWLEVEL_INIT + select SYS_FSL_HAS_CCI400 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 +@@ -429,7 +453,6 @@ + + config FSPI_AHB_EN_4BYTE + bool "Enable 4-byte Fast Read command for AHB mode" +- default n + help + The default setting for FlexSPI AHB bus just supports 3-byte addressing. + But some FlexSPI flash sizes are up to 64MBytes. +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S u-boot/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 2021-11-01 17:10:13.556297801 +0100 +@@ -250,7 +250,7 @@ + * b. We use only Region0 whose NSAID write/read is EN + * + * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just +- * placeholders. ++ * placeholders. + */ + + .macro tzasc_prog, xreg +@@ -259,7 +259,7 @@ + mov x16, #0x10000 + mul x14, \xreg, x16 + add x14, x14,x12 +- mov x1, #0x8 ++ mov x1, #0x8 + add x1, x1, x14 + + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c 2021-11-01 17:10:13.556297801 +0100 +@@ -100,7 +100,7 @@ + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + /* +- * LS1044A/1048A support only one XFI port ++ * LS1044A/1048A support only one 10GBase-R port + * Disable MAC1 for LS1044A/1048A + */ + if (serdes == FSL_SRDS_1 && lane == 2) { +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/soc.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/soc.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/soc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/soc.c 2021-11-01 17:10:13.559630952 +0100 +@@ -329,7 +329,7 @@ + #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 + static void erratum_a009203(void) + { +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + u8 __iomem *ptr; + #ifdef I2C1_BASE_ADDR + ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/spintable.S u-boot/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/spintable.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/spintable.S 2021-11-01 17:10:13.559630952 +0100 +@@ -93,7 +93,7 @@ + 4: + #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + switch_el x7, _dead_loop, 0f, _dead_loop +-0: armv8_switch_to_el1_m x4, x6, x7 ++0: armv8_switch_to_el1_m x4, x6, x7, x9 + #else + switch_el x7, 0f, _dead_loop, _dead_loop + 0: armv8_switch_to_el2_m x4, x6, x7 +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/spl.c u-boot/arch/arm/cpu/armv8/fsl-layerscape/spl.c +--- u-boot-2021.10/arch/arm/cpu/armv8/fsl-layerscape/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/fsl-layerscape/spl.c 2021-11-01 17:10:13.559630952 +0100 +@@ -27,7 +27,7 @@ + + u32 spl_boot_device(void) + { +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + return BOOT_DEVICE_MMC1; + #endif + #ifdef CONFIG_SPL_NAND_SUPPORT +@@ -88,7 +88,7 @@ + preloader_console_init(); + spl_set_bd(); + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + #ifdef CONFIG_SPL_I2C + i2c_init_all(); + #endif +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/hisilicon/pinmux.c u-boot/arch/arm/cpu/armv8/hisilicon/pinmux.c +--- u-boot-2021.10/arch/arm/cpu/armv8/hisilicon/pinmux.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/hisilicon/pinmux.c 2021-11-01 17:10:13.559630952 +0100 +@@ -181,5 +181,3 @@ + + return 0; + } +- +- +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/Kconfig u-boot/arch/arm/cpu/armv8/Kconfig +--- u-boot-2021.10/arch/arm/cpu/armv8/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/Kconfig 2021-11-01 17:10:13.552964650 +0100 +@@ -3,7 +3,6 @@ + config ARMV8_SPL_EXCEPTION_VECTORS + bool "Install crash dump exception vectors" + depends on SPL +- default n + help + The default exception vector table is only used for the crash + dump, but still takes quite a lot of space in the image size. +@@ -128,7 +127,6 @@ + + config ARMV8_PSCI + bool "Enable PSCI support" if EXPERT +- default n + help + PSCI is Power State Coordination Interface defined by ARM. + The PSCI in U-boot provides a general framework and each platform +@@ -156,7 +154,6 @@ + + config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" +- default n + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/transition.S u-boot/arch/arm/cpu/armv8/transition.S +--- u-boot-2021.10/arch/arm/cpu/armv8/transition.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/transition.S 2021-11-01 17:10:13.559630952 +0100 +@@ -40,7 +40,7 @@ + * now, jump to the address saved in x4. + */ + br x4 +-1: armv8_switch_to_el1_m x4, x5, x6 ++1: armv8_switch_to_el1_m x4, x5, x6, x7 + ENDPROC(armv8_switch_to_el1) + .popsection + +diff -ruN u-boot-2021.10/arch/arm/cpu/armv8/xen/hypercall.S u-boot/arch/arm/cpu/armv8/xen/hypercall.S +--- u-boot-2021.10/arch/arm/cpu/armv8/xen/hypercall.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/armv8/xen/hypercall.S 2021-11-01 17:10:13.559630952 +0100 +@@ -76,4 +76,3 @@ + HYPERCALL2(event_channel_op); + HYPERCALL2(hvm_op); + HYPERCALL2(memory_op); +- +diff -ruN u-boot-2021.10/arch/arm/cpu/pxa/start.S u-boot/arch/arm/cpu/pxa/start.S +--- u-boot-2021.10/arch/arm/cpu/pxa/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/pxa/start.S 2021-11-01 17:10:13.559630952 +0100 +@@ -45,7 +45,7 @@ + orr r0,r0,#0xd3 + msr cpsr,r0 + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -92,7 +92,7 @@ + * + ************************************************************************* + */ +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) + cpu_init_crit: + /* + * flush v4 I/D caches +@@ -111,7 +111,7 @@ + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr /* back to my caller */ +-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ ++#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ + + /* + * Enable MMU to use DCache as DRAM. +diff -ruN u-boot-2021.10/arch/arm/cpu/sa1100/start.S u-boot/arch/arm/cpu/sa1100/start.S +--- u-boot-2021.10/arch/arm/cpu/sa1100/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/cpu/sa1100/start.S 2021-11-01 17:10:13.559630952 +0100 +@@ -39,7 +39,7 @@ + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + bl cpu_init_crit + #endif + +@@ -95,7 +95,7 @@ + ldr r1, cpuspeed + str r1, [r0, #PPCR] + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will +diff -ruN u-boot-2021.10/arch/arm/dts/ast2600.dtsi u-boot/arch/arm/dts/ast2600.dtsi +--- u-boot-2021.10/arch/arm/dts/ast2600.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ast2600.dtsi 2021-11-01 17:10:13.572963556 +0100 +@@ -474,21 +474,25 @@ + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785000 0x40>; ++ status = "disabled"; + }; + + wdt2: watchdog@1e785040 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785040 0x40>; ++ status = "disabled"; + }; + + wdt3: watchdog@1e785080 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785080 0x40>; ++ status = "disabled"; + }; + + wdt4: watchdog@1e7850C0 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e7850C0 0x40>; ++ status = "disabled"; + }; + + lpc: lpc@1e789000 { +diff -ruN u-boot-2021.10/arch/arm/dts/at91-sama5d27_som1_ek.dts u-boot/arch/arm/dts/at91-sama5d27_som1_ek.dts +--- u-boot-2021.10/arch/arm/dts/at91-sama5d27_som1_ek.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/at91-sama5d27_som1_ek.dts 2021-11-01 17:10:13.572963556 +0100 +@@ -68,7 +68,7 @@ + }; + + ahb { +- usb1: ohci@00400000 { ++ usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 42 0>; + pinctrl-names = "default"; +@@ -76,7 +76,7 @@ + status = "okay"; + }; + +- usb2: ehci@00500000 { ++ usb2: ehci@500000 { + status = "okay"; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/at91-sama5d2_icp.dts u-boot/arch/arm/dts/at91-sama5d2_icp.dts +--- u-boot-2021.10/arch/arm/dts/at91-sama5d2_icp.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/at91-sama5d2_icp.dts 2021-11-01 17:10:13.572963556 +0100 +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0+ OR MIT + /* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board +- * SAMA5D2 Industrial Connectivity Board ++ * SAMA5D2 Industrial Connectivity Platform + * + * Copyright (c) 2018, Microchip Technology Inc. + * 2018, Eugen Hristev +@@ -33,10 +33,19 @@ + }; + + apb { +- uart0: serial@f801c000 { /* mikrobus1 uart */ ++ ++ qspi1: spi@f0024000 { + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_mikrobus1_uart>; ++ pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>; + status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <83000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ }; + }; + + macb0: ethernet@f8008000 { +@@ -46,6 +55,12 @@ + status = "okay"; + }; + ++ uart0: serial@f801c000 { /* mikrobus1 uart */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mikrobus1_uart>; ++ status = "okay"; ++ }; ++ + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; +@@ -70,6 +85,7 @@ + pagesize = <16>; + }; + }; ++ + pioA: gpio@fc038000 { + status = "okay"; + pinctrl { +@@ -109,6 +125,26 @@ + bias-pull-up; + }; + ++ pinctrl_mikrobus1_uart: mikrobus1_uart { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { ++ pinmux = , ++ ; ++ bias-disable; ++ }; ++ ++ pinctrl_qspi1_dat_default: qspi1_dat_default { ++ pinmux = , ++ , ++ , ++ ; ++ bias-pull-up; ++ }; ++ + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = , + , +@@ -119,12 +155,6 @@ + ; + bias-disable; + }; +- +- pinctrl_mikrobus1_uart: mikrobus1_uart { +- pinmux = , +- ; +- bias-disable; +- }; + }; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi u-boot/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi 2021-11-01 17:10:13.572963556 +0100 +@@ -13,11 +13,15 @@ + }; + }; + +-&sdmmc0 { ++&pinctrl_mikrobus1_uart { + u-boot,dm-pre-reloc; + }; + +-&uart0 { /* mikrobus1 uart */ ++&pinctrl_qspi1_sck_cs_default { ++ u-boot,dm-pre-reloc; ++}; ++ ++&pinctrl_qspi1_dat_default { + u-boot,dm-pre-reloc; + }; + +@@ -25,6 +29,19 @@ + u-boot,dm-pre-reloc; + }; + +-&pinctrl_mikrobus1_uart { ++&qspi1 { ++ u-boot,dm-pre-reloc; ++ ++ flash@0 { ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&sdmmc0 { + u-boot,dm-pre-reloc; + }; ++ ++&uart0 { /* mikrobus1 uart */ ++ u-boot,dm-pre-reloc; ++}; ++ +diff -ruN u-boot-2021.10/arch/arm/dts/at91-sama5d2_ptc_ek.dts u-boot/arch/arm/dts/at91-sama5d2_ptc_ek.dts +--- u-boot-2021.10/arch/arm/dts/at91-sama5d2_ptc_ek.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/at91-sama5d2_ptc_ek.dts 2021-11-01 17:10:13.572963556 +0100 +@@ -76,7 +76,7 @@ + status = "okay"; + }; + +- usb1: ohci@00400000 { ++ usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH +@@ -87,7 +87,7 @@ + status = "okay"; + }; + +- usb2: ehci@00500000 { ++ usb2: ehci@500000 { + status = "okay"; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/at91-sama5d2_xplained.dts u-boot/arch/arm/dts/at91-sama5d2_xplained.dts +--- u-boot-2021.10/arch/arm/dts/at91-sama5d2_xplained.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/at91-sama5d2_xplained.dts 2021-11-01 17:10:13.572963556 +0100 +@@ -12,6 +12,10 @@ + stdout-path = &uart1; + }; + ++ memory { ++ reg = <0x20000000 0x20000000>; ++ }; ++ + onewire_tm: onewire { + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; +@@ -25,7 +29,7 @@ + }; + + ahb { +- usb1: ohci@00400000 { ++ usb1: ohci@400000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 42 0>; + pinctrl-names = "default"; +@@ -33,7 +37,7 @@ + status = "okay"; + }; + +- usb2: ehci@00500000 { ++ usb2: ehci@500000 { + status = "okay"; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/axp22x.dtsi u-boot/arch/arm/dts/axp22x.dtsi +--- u-boot-2021.10/arch/arm/dts/axp22x.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/axp22x.dtsi 2021-11-01 17:10:13.576296707 +0100 +@@ -62,6 +62,12 @@ + status = "disabled"; + }; + ++ axp_gpio: gpio { ++ compatible = "x-powers,axp221-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; +diff -ruN u-boot-2021.10/arch/arm/dts/axp809.dtsi u-boot/arch/arm/dts/axp809.dtsi +--- u-boot-2021.10/arch/arm/dts/axp809.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/axp809.dtsi 2021-11-01 17:10:13.576296707 +0100 +@@ -50,4 +50,11 @@ + compatible = "x-powers,axp809"; + interrupt-controller; + #interrupt-cells = <1>; ++ ++ axp_gpio: gpio { ++ compatible = "x-powers,axp809-gpio", ++ "x-powers,axp221-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/axp81x.dtsi u-boot/arch/arm/dts/axp81x.dtsi +--- u-boot-2021.10/arch/arm/dts/axp81x.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/axp81x.dtsi 2021-11-01 17:10:13.576296707 +0100 +@@ -166,4 +166,8 @@ + status = "disabled"; + }; + }; ++ ++ usb_power_supply: usb-power-supply { ++ compatible = "x-powers,axp813-usb-power-supply"; ++ }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 1xxx + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 6xxx + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +@@ -14,6 +14,6 @@ + + &enetc0 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +@@ -30,25 +30,25 @@ + + &mscc_felix_port0 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; + }; + + &mscc_felix_port1 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; + }; + + &mscc_felix_port2 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + }; + + &mscc_felix_port3 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 7xx7 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + &slot1 { +@@ -19,13 +19,13 @@ + + &mscc_felix_port0 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + }; + + &mscc_felix_port3 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 8xxx + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + * + */ + +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW x3xx + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW x5xx + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + &slot2 { +@@ -19,7 +19,7 @@ + + &mscc_felix_port1 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi u-boot/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -2,7 +2,7 @@ + /* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + &slot3 { +@@ -19,7 +19,7 @@ + + &mscc_felix_port2 { + status = "okay"; +- phy-mode = "sgmii-2500"; ++ phy-mode = "2500base-x"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi u-boot/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -9,12 +9,12 @@ + + &dpmac1 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac2 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac4 { +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi u-boot/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -9,10 +9,10 @@ + + &dpmac1 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac2 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi u-boot/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi 2021-11-01 17:10:13.586296160 +0100 +@@ -9,40 +9,40 @@ + + &dpmac1 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac2 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac3 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac4 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac5 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac6 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac7 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac8 { + status = "okay"; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts u-boot/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +--- u-boot-2021.10/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts 2021-11-01 17:10:13.586296160 +0100 +@@ -24,49 +24,49 @@ + &dpmac1 { + status = "okay"; + phy-handle = <&mdio1_phy1>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac2 { + status = "okay"; + phy-handle = <&mdio1_phy2>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac3 { + status = "okay"; + phy-handle = <&mdio1_phy3>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac4 { + status = "okay"; + phy-handle = <&mdio1_phy4>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac5 { + status = "okay"; + phy-handle = <&mdio2_phy1>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac6 { + status = "okay"; + phy-handle = <&mdio2_phy2>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac7 { + status = "okay"; + phy-handle = <&mdio2_phy3>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &dpmac8 { + status = "okay"; + phy-handle = <&mdio2_phy4>; +- phy-connection-type = "xfi"; ++ phy-connection-type = "10gbase-r"; + }; + + &emdio1 { +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-sch-24801.dtsi u-boot/arch/arm/dts/fsl-sch-24801.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-sch-24801.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-sch-24801.dtsi 2021-11-01 17:10:13.589629311 +0100 +@@ -2,7 +2,7 @@ + /* + * Device tree fragment for RCW SCH-24801 card + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-sch-28021.dtsi u-boot/arch/arm/dts/fsl-sch-28021.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-sch-28021.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-sch-28021.dtsi 2021-11-01 17:10:13.589629311 +0100 +@@ -2,7 +2,7 @@ + /* + * Device tree fragment for RCW SCH-28021 card + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-sch-30841.dtsi u-boot/arch/arm/dts/fsl-sch-30841.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-sch-30841.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-sch-30841.dtsi 2021-11-01 17:10:13.589629311 +0100 +@@ -2,14 +2,14 @@ + /* + * Device tree fragment for RCW SCH-30841 card + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* + * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. + * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed + * together on a single lane or mapped 1:1 to serdes lanes. +- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. ++ * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R. + * PHY addresses are 0x00 - 0x03. + * On the card the first port is the bottom port (closest to PEX connector). + */ +diff -ruN u-boot-2021.10/arch/arm/dts/fsl-sch-30842.dtsi u-boot/arch/arm/dts/fsl-sch-30842.dtsi +--- u-boot-2021.10/arch/arm/dts/fsl-sch-30842.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/fsl-sch-30842.dtsi 2021-11-01 17:10:13.589629311 +0100 +@@ -2,13 +2,13 @@ + /* + * Device tree fragment for RCW SCH-30842 card + * +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + /* + * SCH-30842 is a single port add-on card used with various FSL QDS boards. + * It integrates a AQR112 PHY, which supports several protocols - SGMII, +- * SGMII-2500, USXGMII, XFI. ++ * 2500base-x, USXGMII, 10GBase-R. + * PHY address is 0x02. + */ + phy@02 { +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/arm/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/arm/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/arm/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/arm/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/arm/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/arm/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/arm/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/leds/common.h u-boot/arch/arm/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/arm/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/arm/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/arm/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/arm/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/arm/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/arm/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/arm/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/arm/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am642-evm.dts u-boot/arch/arm/dts/k3-am642-evm.dts +--- u-boot-2021.10/arch/arm/dts/k3-am642-evm.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am642-evm.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -5,6 +5,8 @@ + + /dts-v1/; + ++#include ++#include + #include + #include + #include +@@ -36,6 +38,60 @@ + alignment = <0x1000>; + no-map; + }; ++ ++ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_memory_region: r5f-memory@a1100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core0_memory_region: r5f-memory@a2100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ rtos_ipc_memory_region: ipc-memories@a5000000 { ++ reg = <0x00 0xa5000000 0x00 0x00800000>; ++ alignment = <0x1000>; ++ no-map; ++ }; + }; + + evm_12v0: fixedregulator-evm12v0 { +@@ -154,6 +210,15 @@ + >; + }; + ++ main_spi0_pins_default: main-spi0-pins-default { ++ pinctrl-single,pins = < ++ AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ ++ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ ++ AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ ++ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ ++ >; ++ }; ++ + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ +@@ -207,6 +272,22 @@ + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; ++ ++ ospi0_pins_default: ospi0-pins-default { ++ pinctrl-single,pins = < ++ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ ++ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ ++ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ ++ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ ++ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ ++ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ ++ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ ++ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ ++ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ ++ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ ++ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ ++ >; ++ }; + }; + + &main_uart0 { +@@ -285,6 +366,11 @@ + }; + }; + ++/* mcu_gpio0 is reserved for mcu firmware usage */ ++&mcu_gpio0 { ++ status = "reserved"; ++}; ++ + &mcu_i2c0 { + status = "disabled"; + }; +@@ -301,28 +387,16 @@ + status = "disabled"; + }; + +-&cpsw3g { ++&main_spi0 { + pinctrl-names = "default"; +- pinctrl-0 = <&mdio1_pins_default +- &rgmii1_pins_default +- &rgmii2_pins_default>; +-}; +- +-&cpsw_port1 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy0>; +-}; +- +-&cpsw_port2 { +- phy-mode = "rgmii-rxid"; +- phy-handle = <&cpsw3g_phy3>; +-}; +- +-&cpsw3g_mdio { +- cpsw3g_phy0: ethernet-phy@0 { ++ pinctrl-0 = <&main_spi0_pins_default>; ++ ti,pindir-d0-out-d1-in; ++ eeprom@0 { ++ compatible = "microchip,93lc46b"; + reg = <0>; +- ti,rx-internal-delay = ; +- ti,fifo-depth = ; ++ spi-max-frequency = <1000000>; ++ spi-cs-high; ++ data-size = <16>; + }; + }; + +@@ -355,3 +429,148 @@ + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; + }; ++ ++&cpsw3g { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mdio1_pins_default ++ &rgmii1_pins_default ++ &rgmii2_pins_default>; ++}; ++ ++&cpsw_port1 { ++ phy-mode = "rgmii-rxid"; ++ phy-handle = <&cpsw3g_phy0>; ++}; ++ ++&cpsw_port2 { ++ phy-mode = "rgmii-rxid"; ++ phy-handle = <&cpsw3g_phy3>; ++}; ++ ++&cpsw3g_mdio { ++ cpsw3g_phy0: ethernet-phy@0 { ++ reg = <0>; ++ ti,rx-internal-delay = ; ++ ti,fifo-depth = ; ++ }; ++}; ++ ++&tscadc0 { ++ /* ADC is reserved for R5 usage */ ++ status = "reserved"; ++}; ++ ++&ospi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ospi0_pins_default>; ++ ++ flash@0{ ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-tx-bus-width = <8>; ++ spi-rx-bus-width = <8>; ++ spi-max-frequency = <25000000>; ++ cdns,tshsl-ns = <60>; ++ cdns,tsd2d-ns = <60>; ++ cdns,tchsh-ns = <60>; ++ cdns,tslch-ns = <60>; ++ cdns,read-delay = <4>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; ++ ++&mailbox0_cluster2 { ++ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++ ++ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { ++ ti,mbox-rx = <2 0 2>; ++ ti,mbox-tx = <3 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster3 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster4 { ++ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++ ++ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { ++ ti,mbox-rx = <2 0 2>; ++ ti,mbox-tx = <3 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster5 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster6 { ++ mbox_m4_0: mbox-m4-0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster7 { ++ status = "disabled"; ++}; ++ ++&main_r5fss0_core0 { ++ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; ++ memory-region = <&main_r5fss0_core0_dma_memory_region>, ++ <&main_r5fss0_core0_memory_region>; ++}; ++ ++&main_r5fss0_core1 { ++ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; ++ memory-region = <&main_r5fss0_core1_dma_memory_region>, ++ <&main_r5fss0_core1_memory_region>; ++}; ++ ++&main_r5fss1_core0 { ++ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; ++ memory-region = <&main_r5fss1_core0_dma_memory_region>, ++ <&main_r5fss1_core0_memory_region>; ++}; ++ ++&main_r5fss1_core1 { ++ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; ++ memory-region = <&main_r5fss1_core1_dma_memory_region>, ++ <&main_r5fss1_core1_memory_region>; ++}; ++ ++&serdes_ln_ctrl { ++ idle-states = ; ++}; ++ ++&serdes0 { ++ serdes0_pcie_link: phy@0 { ++ reg = <0>; ++ cdns,num-lanes = <1>; ++ #phy-cells = <0>; ++ cdns,phy-type = ; ++ resets = <&serdes_wiz0 1>; ++ }; ++}; ++ ++&pcie0_rc { ++ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; ++ phys = <&serdes0_pcie_link>; ++ phy-names = "pcie-phy"; ++ num-lanes = <1>; ++}; ++ ++&pcie0_ep { ++ phys = <&serdes0_pcie_link>; ++ phy-names = "pcie-phy"; ++ num-lanes = <1>; ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am642-sk.dts u-boot/arch/arm/dts/k3-am642-sk.dts +--- u-boot-2021.10/arch/arm/dts/k3-am642-sk.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am642-sk.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -5,6 +5,8 @@ + + /dts-v1/; + ++#include ++#include + #include + #include + #include "k3-am642.dtsi" +@@ -35,6 +37,93 @@ + alignment = <0x1000>; + no-map; + }; ++ ++ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_memory_region: r5f-memory@a1100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core0_memory_region: r5f-memory@a2100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ rtos_ipc_memory_region: ipc-memories@a5000000 { ++ reg = <0x00 0xa5000000 0x00 0x00800000>; ++ alignment = <0x1000>; ++ no-map; ++ }; ++ }; ++ ++ vusb_main: fixed-regulator-vusb-main5v0 { ++ /* USB MAIN INPUT 5V DC */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vusb_main5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc_3v3_sys: fixedregulator-vcc-3v3-sys { ++ /* output of LP8733xx */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_sys"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vusb_main>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_mmc1: fixed-regulator-sd { ++ /* TPS2051BD */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_mmc1"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ vin-supply = <&vcc_3v3_sys>; ++ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + }; + +@@ -52,6 +141,12 @@ + >; + }; + ++ main_usb0_pins_default: main-usb0-pins-default { ++ pinctrl-single,pins = < ++ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ ++ >; ++ }; ++ + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ +@@ -99,6 +194,30 @@ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; ++ ++ ospi0_pins_default: ospi0-pins-default { ++ pinctrl-single,pins = < ++ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ ++ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ ++ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ ++ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ ++ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ ++ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ ++ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ ++ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ ++ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ ++ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ ++ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ ++ >; ++ }; ++}; ++ ++&mcu_uart0 { ++ status = "disabled"; ++}; ++ ++&mcu_uart1 { ++ status = "disabled"; + }; + + &main_uart1 { +@@ -126,8 +245,51 @@ + status = "disabled"; + }; + ++&mcu_i2c0 { ++ status = "disabled"; ++}; ++ ++&mcu_i2c1 { ++ status = "disabled"; ++}; ++ ++&main_i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_i2c1_pins_default>; ++ clock-frequency = <400000>; ++ ++ exp1: gpio@70 { ++ compatible = "nxp,pca9538"; ++ reg = <0x70>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", ++ "PRU_DETECT", "MMC1_SD_EN", ++ "VPP_LDO_EN", "RPI_PS_3V3_En", ++ "RPI_PS_5V0_En", "RPI_HAT_DETECT"; ++ }; ++}; ++ ++&main_i2c3 { ++ status = "disabled"; ++}; ++ ++&mcu_spi0 { ++ status = "disabled"; ++}; ++ ++&mcu_spi1 { ++ status = "disabled"; ++}; ++ ++/* mcu_gpio0 is reserved for mcu firmware usage */ ++&mcu_gpio0 { ++ status = "reserved"; ++}; ++ + &sdhci1 { + /* SD/MMC */ ++ vmmc-supply = <&vdd_mmc1>; + pinctrl-names = "default"; + bus-width = <4>; + pinctrl-0 = <&main_mmc1_pins_default>; +@@ -135,6 +297,33 @@ + disable-wp; + }; + ++&serdes_ln_ctrl { ++ idle-states = ; ++}; ++ ++&serdes0 { ++ serdes0_usb_link: phy@0 { ++ reg = <0>; ++ cdns,num-lanes = <1>; ++ #phy-cells = <0>; ++ cdns,phy-type = ; ++ resets = <&serdes_wiz0 1>; ++ }; ++}; ++ ++&usbss0 { ++ ti,vbus-divider; ++}; ++ ++&usb0 { ++ dr_mode = "host"; ++ maximum-speed = "super-speed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_usb0_pins_default>; ++ phys = <&serdes0_usb_link>; ++ phy-names = "cdns3,usb3-phy"; ++}; ++ + &cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default +@@ -147,10 +336,120 @@ + phy-handle = <&cpsw3g_phy0>; + }; + ++&cpsw_port2 { ++ phy-mode = "rgmii-rxid"; ++ phy-handle = <&cpsw3g_phy1>; ++}; ++ + &cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; ++ ++ cpsw3g_phy1: ethernet-phy@1 { ++ reg = <1>; ++ ti,rx-internal-delay = ; ++ ti,fifo-depth = ; ++ }; ++}; ++ ++&tscadc0 { ++ status = "disabled"; ++}; ++ ++&ospi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ospi0_pins_default>; ++ ++ flash@0{ ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-tx-bus-width = <8>; ++ spi-rx-bus-width = <8>; ++ spi-max-frequency = <25000000>; ++ cdns,tshsl-ns = <60>; ++ cdns,tsd2d-ns = <60>; ++ cdns,tchsh-ns = <60>; ++ cdns,tslch-ns = <60>; ++ cdns,read-delay = <4>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; ++ ++&mailbox0_cluster2 { ++ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++ ++ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { ++ ti,mbox-rx = <2 0 2>; ++ ti,mbox-tx = <3 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster3 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster4 { ++ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++ ++ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { ++ ti,mbox-rx = <2 0 2>; ++ ti,mbox-tx = <3 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster5 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster6 { ++ mbox_m4_0: mbox-m4-0 { ++ ti,mbox-rx = <0 0 2>; ++ ti,mbox-tx = <1 0 2>; ++ }; ++}; ++ ++&mailbox0_cluster7 { ++ status = "disabled"; ++}; ++ ++&main_r5fss0_core0 { ++ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; ++ memory-region = <&main_r5fss0_core0_dma_memory_region>, ++ <&main_r5fss0_core0_memory_region>; ++}; ++ ++&main_r5fss0_core1 { ++ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; ++ memory-region = <&main_r5fss0_core1_dma_memory_region>, ++ <&main_r5fss0_core1_memory_region>; ++}; ++ ++&main_r5fss1_core0 { ++ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; ++ memory-region = <&main_r5fss1_core0_dma_memory_region>, ++ <&main_r5fss1_core0_memory_region>; ++}; ++ ++&main_r5fss1_core1 { ++ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; ++ memory-region = <&main_r5fss1_core1_dma_memory_region>, ++ <&main_r5fss1_core1_memory_region>; ++}; ++ ++&pcie0_rc { ++ status = "disabled"; ++}; ++ ++&pcie0_ep { ++ status = "disabled"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am64.dtsi u-boot/arch/arm/dts/k3-am64.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am64.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am64.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -28,8 +28,6 @@ + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; +- i2c0 = &main_i2c0; +- i2c1 = &main_i2c1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am64-main.dtsi u-boot/arch/arm/dts/k3-am64-main.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am64-main.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am64-main.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -5,6 +5,17 @@ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + ++#include ++#include ++ ++/ { ++ serdes_refclk: clock-cmnrefclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++}; ++ + &cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; +@@ -26,6 +37,20 @@ + }; + }; + ++ main_conf: syscon@43000000 { ++ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; ++ reg = <0x0 0x43000000 0x0 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x43000000 0x20000>; ++ ++ serdes_ln_ctrl: mux-controller { ++ compatible = "mmio-mux"; ++ #mux-control-cells = <1>; ++ mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ ++ }; ++ }; ++ + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; +@@ -50,12 +75,12 @@ + }; + }; + +- dmss: dmss { ++ dmss: bus@48000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; +- ranges; ++ ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + +@@ -142,7 +167,7 @@ + }; + }; + +- dmsc: dmsc@44043000 { ++ dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; +@@ -156,7 +181,7 @@ + #power-domain-cells = <2>; + }; + +- k3_clks: clocks { ++ k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; +@@ -197,8 +222,6 @@ + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -210,8 +233,6 @@ + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -223,8 +244,6 @@ + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -236,8 +255,6 @@ + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -249,8 +266,6 @@ + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -262,8 +277,6 @@ + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -275,8 +288,6 @@ + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -381,6 +392,52 @@ + clocks = <&k3_clks 145 0>; + }; + ++ main_gpio_intr: interrupt-controller@a00000 { ++ compatible = "ti,sci-intr"; ++ reg = <0x00 0x00a00000 0x00 0x800>; ++ ti,intr-trigger-type = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic500>; ++ #interrupt-cells = <1>; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <3>; ++ ti,interrupt-ranges = <0 32 16>; ++ }; ++ ++ main_gpio0: gpio@600000 { ++ compatible = "ti,am64-gpio", "ti,keystone-gpio"; ++ reg = <0x0 0x00600000 0x0 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <190>, <191>, <192>, ++ <193>, <194>, <195>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <87>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 77 0>; ++ clock-names = "gpio"; ++ }; ++ ++ main_gpio1: gpio@601000 { ++ compatible = "ti,am64-gpio", "ti,keystone-gpio"; ++ reg = <0x0 0x00601000 0x0 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <180>, <181>, <182>, ++ <183>, <184>, <185>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <88>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 78 0>; ++ clock-names = "gpio"; ++ }; ++ + sdhci0: mmc@fa10000 { + compatible = "ti,am64-sdhci-8bit"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; +@@ -451,7 +508,8 @@ + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; +- mac-address = [00 00 de ad be ef]; ++ mac-address = [00 00 00 00 00 00]; ++ ti,syscon-efuse = <&main_conf 0x200>; + }; + + cpsw_port2: port@2 { +@@ -459,7 +517,7 @@ + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; +- mac-address = [00 01 de ad be ef]; ++ mac-address = [00 00 00 00 00 00]; + }; + }; + +@@ -485,30 +543,23 @@ + }; + }; + +- main_gpio0: gpio@600000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00600000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <77 0 IRQ_TYPE_EDGE_RISING>, +- <77 1 IRQ_TYPE_EDGE_RISING>, +- <77 2 IRQ_TYPE_EDGE_RISING>, +- <77 3 IRQ_TYPE_EDGE_RISING>, +- <77 4 IRQ_TYPE_EDGE_RISING>, +- <77 5 IRQ_TYPE_EDGE_RISING>, +- <77 6 IRQ_TYPE_EDGE_RISING>, +- <77 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 77 0>; +- clock-names = "gpio"; ++ cpts@39000000 { ++ compatible = "ti,j721e-cpts"; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ reg-names = "cpts"; ++ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 84 0>; ++ clock-names = "cpts"; ++ assigned-clocks = <&k3_clks 84 0>; ++ assigned-clock-parents = <&k3_clks 84 8>; ++ interrupts = ; ++ interrupt-names = "cpts"; ++ ti,cpts-periodic-outputs = <6>; ++ ti,cpts-ext-ts-inputs = <8>; + }; + + usbss0: cdns-usb@f900000{ +- compatible = "ti,am64-usb", "ti,j721e-usb"; ++ compatible = "ti,am64-usb"; + reg = <0x00 0xf900000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; +@@ -537,69 +588,275 @@ + }; + }; + +- main_gpio1: gpio@601000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x00 0x00601000 0x00 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <78 0 IRQ_TYPE_EDGE_RISING>, +- <78 1 IRQ_TYPE_EDGE_RISING>, +- <78 2 IRQ_TYPE_EDGE_RISING>, +- <78 3 IRQ_TYPE_EDGE_RISING>, +- <78 4 IRQ_TYPE_EDGE_RISING>, +- <78 5 IRQ_TYPE_EDGE_RISING>, +- <78 6 IRQ_TYPE_EDGE_RISING>, +- <78 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 78 0>; +- clock-names = "gpio"; ++ tscadc0: tscadc@28001000 { ++ compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; ++ reg = <0x00 0x28001000 0x00 0x1000>; ++ interrupts = ; ++ power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 0 0>; ++ assigned-clocks = <&k3_clks 0 0>; ++ assigned-clock-parents = <&k3_clks 0 3>; ++ assigned-clock-rates = <60000000>; ++ clock-names = "adc_tsc_fck"; ++ ++ adc { ++ #io-channel-cells = <1>; ++ compatible = "ti,am654-adc", "ti,am3359-adc"; ++ }; + }; + +- main_i2c0: i2c@20000000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x20000000 0x0 0x100>; +- interrupts = ; ++ fss: bus@fc00000 { ++ compatible = "simple-bus"; ++ reg = <0x00 0x0fc00000 0x00 0x70000>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ ospi0: spi@fc40000 { ++ compatible = "ti,am654-ospi", "cdns,qspi-nor"; ++ reg = <0x00 0x0fc40000 0x00 0x100>, ++ <0x05 0x00000000 0x01 0x00000000>; ++ interrupts = ; ++ cdns,fifo-depth = <256>; ++ cdns,fifo-width = <4>; ++ cdns,trigger-address = <0x0>; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ clocks = <&k3_clks 75 6>; ++ assigned-clocks = <&k3_clks 75 6>; ++ assigned-clock-parents = <&k3_clks 75 7>; ++ assigned-clock-rates = <166666666>; ++ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; ++ }; ++ }; ++ ++ hwspinlock: spinlock@2a000000 { ++ compatible = "ti,am64-hwspinlock"; ++ reg = <0x00 0x2a000000 0x00 0x1000>; ++ #hwlock-cells = <1>; ++ }; ++ ++ mailbox0_cluster2: mailbox@29020000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29020000 0x00 0x200>; ++ interrupts = , ++ ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ mailbox0_cluster3: mailbox@29030000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29030000 0x00 0x200>; ++ interrupts = , ++ ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ mailbox0_cluster4: mailbox@29040000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29040000 0x00 0x200>; ++ interrupts = , ++ ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ mailbox0_cluster5: mailbox@29050000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29050000 0x00 0x200>; ++ interrupts = , ++ ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ mailbox0_cluster6: mailbox@29060000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29060000 0x00 0x200>; ++ interrupts = ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ mailbox0_cluster7: mailbox@29070000 { ++ compatible = "ti,am64-mailbox"; ++ reg = <0x00 0x29070000 0x00 0x200>; ++ interrupts = ; ++ #mbox-cells = <1>; ++ ti,mbox-num-users = <4>; ++ ti,mbox-num-fifos = <16>; ++ }; ++ ++ main_r5fss0: r5fss@78000000 { ++ compatible = "ti,am64-r5fss"; ++ ti,cluster-mode = <0>; + #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 102 2>; +- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; ++ #size-cells = <1>; ++ ranges = <0x78000000 0x00 0x78000000 0x10000>, ++ <0x78100000 0x00 0x78100000 0x10000>, ++ <0x78200000 0x00 0x78200000 0x08000>, ++ <0x78300000 0x00 0x78300000 0x08000>; ++ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; ++ ++ main_r5fss0_core0: r5f@78000000 { ++ compatible = "ti,am64-r5f"; ++ reg = <0x78000000 0x00010000>, ++ <0x78100000 0x00010000>; ++ reg-names = "atcm", "btcm"; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <121>; ++ ti,sci-proc-ids = <0x01 0xff>; ++ resets = <&k3_reset 121 1>; ++ firmware-name = "am64-main-r5f0_0-fw"; ++ ti,atcm-enable = <1>; ++ ti,btcm-enable = <1>; ++ ti,loczrama = <1>; ++ }; ++ ++ main_r5fss0_core1: r5f@78200000 { ++ compatible = "ti,am64-r5f"; ++ reg = <0x78200000 0x00008000>, ++ <0x78300000 0x00008000>; ++ reg-names = "atcm", "btcm"; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <122>; ++ ti,sci-proc-ids = <0x02 0xff>; ++ resets = <&k3_reset 122 1>; ++ firmware-name = "am64-main-r5f0_1-fw"; ++ ti,atcm-enable = <1>; ++ ti,btcm-enable = <1>; ++ ti,loczrama = <1>; ++ }; + }; + +- main_i2c1: i2c@20010000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x0 0x20010000 0x0 0x100>; +- interrupts = ; ++ main_r5fss1: r5fss@78400000 { ++ compatible = "ti,am64-r5fss"; ++ ti,cluster-mode = <0>; + #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 103 2>; +- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; ++ #size-cells = <1>; ++ ranges = <0x78400000 0x00 0x78400000 0x10000>, ++ <0x78500000 0x00 0x78500000 0x10000>, ++ <0x78600000 0x00 0x78600000 0x08000>, ++ <0x78700000 0x00 0x78700000 0x08000>; ++ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; ++ ++ main_r5fss1_core0: r5f@78400000 { ++ compatible = "ti,am64-r5f"; ++ reg = <0x78400000 0x00010000>, ++ <0x78500000 0x00010000>; ++ reg-names = "atcm", "btcm"; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <123>; ++ ti,sci-proc-ids = <0x06 0xff>; ++ resets = <&k3_reset 123 1>; ++ firmware-name = "am64-main-r5f1_0-fw"; ++ ti,atcm-enable = <1>; ++ ti,btcm-enable = <1>; ++ ti,loczrama = <1>; ++ }; ++ ++ main_r5fss1_core1: r5f@78600000 { ++ compatible = "ti,am64-r5f"; ++ reg = <0x78600000 0x00008000>, ++ <0x78700000 0x00008000>; ++ reg-names = "atcm", "btcm"; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <124>; ++ ti,sci-proc-ids = <0x07 0xff>; ++ resets = <&k3_reset 124 1>; ++ firmware-name = "am64-main-r5f1_1-fw"; ++ ti,atcm-enable = <1>; ++ ti,btcm-enable = <1>; ++ ti,loczrama = <1>; ++ }; + }; + +- main_i2c2: i2c@20020000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20020000 0x0 0x100>; +- interrupts = ; ++ serdes_wiz0: wiz@f000000 { ++ compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; +- #size-cells = <0>; +- clock-names = "fck"; +- clocks = <&k3_clks 104 2>; +- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; ++ #size-cells = <1>; ++ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; ++ clock-names = "fck", "core_ref_clk", "ext_ref_clk"; ++ num-lanes = <1>; ++ #reset-cells = <1>; ++ #clock-cells = <1>; ++ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; ++ ++ assigned-clocks = <&k3_clks 162 1>; ++ assigned-clock-parents = <&k3_clks 162 5>; ++ ++ serdes0: serdes@f000000 { ++ compatible = "ti,j721e-serdes-10g"; ++ reg = <0x0f000000 0x00010000>; ++ reg-names = "torrent_phy"; ++ resets = <&serdes_wiz0 0>; ++ reset-names = "torrent_reset"; ++ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, ++ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; ++ clock-names = "refclk", "phy_en_refclk"; ++ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, ++ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, ++ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; ++ assigned-clock-parents = <&k3_clks 162 1>, ++ <&k3_clks 162 1>, ++ <&k3_clks 162 1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <1>; ++ }; + }; + +- main_i2c3: i2c@20030000 { +- compatible = "ti,am64-i2c", "ti,omap4-i2c"; +- reg = <0x00 0x20030000 0x0 0x100>; +- interrupts = ; +- #address-cells = <1>; +- #size-cells = <0>; ++ pcie0_rc: pcie@f102000 { ++ compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; ++ reg = <0x00 0x0f102000 0x00 0x1000>, ++ <0x00 0x0f100000 0x00 0x400>, ++ <0x00 0x0d000000 0x00 0x00800000>, ++ <0x00 0x68000000 0x00 0x00001000>; ++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; ++ interrupt-names = "link_state"; ++ interrupts = ; ++ device_type = "pci"; ++ ti,syscon-pcie-ctrl = <&main_conf 0x4070>; ++ max-link-speed = <2>; ++ num-lanes = <1>; ++ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; ++ clock-names = "fck", "pcie_refclk"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xff>; ++ cdns,no-bar-match-nbits = <64>; ++ vendor-id = <0x104c>; ++ device-id = <0xb010>; ++ msi-map = <0x0 &gic_its 0x0 0x10000>; ++ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, ++ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; ++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; ++ }; ++ ++ pcie0_ep: pcie-ep@f102000 { ++ compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; ++ reg = <0x00 0x0f102000 0x00 0x1000>, ++ <0x00 0x0f100000 0x00 0x400>, ++ <0x00 0x0d000000 0x00 0x00800000>, ++ <0x00 0x68000000 0x00 0x08000000>; ++ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; ++ interrupt-names = "link_state"; ++ interrupts = ; ++ ti,syscon-pcie-ctrl = <&main_conf 0x4070>; ++ max-link-speed = <2>; ++ num-lanes = <1>; ++ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 114 0>; + clock-names = "fck"; +- clocks = <&k3_clks 105 2>; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; ++ max-functions = /bits/ 8 <1>; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am64-mcu.dtsi u-boot/arch/arm/dts/k3-am64-mcu.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am64-mcu.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am64-mcu.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -9,8 +9,6 @@ + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -22,8 +20,6 @@ + mcu_uart1: serial@4a10000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a10000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -73,4 +69,32 @@ + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + }; ++ ++ mcu_gpio_intr: interrupt-controller@4210000 { ++ compatible = "ti,sci-intr"; ++ reg = <0x00 0x04210000 0x00 0x200>; ++ ti,intr-trigger-type = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic500>; ++ #interrupt-cells = <1>; ++ ti,sci = <&dmsc>; ++ ti,sci-dev-id = <5>; ++ ti,interrupt-ranges = <0 104 4>; ++ }; ++ ++ mcu_gpio0: gpio@4201000 { ++ compatible = "ti,am64-gpio", "ti,keystone-gpio"; ++ reg = <0x0 0x4201000 0x0 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&mcu_gpio_intr>; ++ interrupts = <30>, <31>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <23>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 79 0>; ++ clock-names = "gpio"; ++ }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi u-boot/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,63 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * Common bits of the IOT2050 Basic variant, PG1 and PG2 ++ */ ++ ++#include "k3-am65-iot2050-common.dtsi" ++ ++#include "k3-am65-iot2050-common-u-boot.dtsi" ++#include "k3-am65-iot2050-boot-image.dtsi" ++ ++/ { ++ memory@80000000 { ++ device_type = "memory"; ++ /* 1G RAM */ ++ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; ++ }; ++ ++ cpus { ++ cpu-map { ++ /delete-node/ cluster1; ++ }; ++ /delete-node/ cpu@100; ++ /delete-node/ cpu@101; ++ }; ++ ++ /delete-node/ l2-cache1; ++}; ++ ++/* eMMC */ ++&sdhci0 { ++ status = "disabled"; ++}; ++ ++&main_pmx0 { ++ main_uart0_pins_default: main-uart0-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ ++ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ ++ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ ++ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ ++ AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */ ++ AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */ ++ AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */ ++ AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */ ++ >; ++ }; ++}; ++ ++&main_uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_uart0_pins_default>; ++}; ++ ++&mcu_r5fss0 { ++ /* lock-step mode not supported on Basic boards */ ++ ti,cluster-mode = <0>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic.dts u-boot/arch/arm/dts/k3-am6528-iot2050-basic.dts +--- u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6528-iot2050-basic.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,24 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1 ++ * 1 GB RAM, no eMMC, main_uart0 on connector X30 ++ * ++ * Product homepage: ++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am6528-iot2050-basic-common.dtsi" ++#include "k3-am65-iot2050-common-pg1.dtsi" ++ ++/ { ++ compatible = "siemens,iot2050-basic", "ti,am654"; ++ model = "SIMATIC IOT2050 Basic"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts u-boot/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts +--- u-boot-2021.10/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,24 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2 ++ * 1 GB RAM, no eMMC, main_uart0 on connector X30 ++ * ++ * Product homepage: ++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am6528-iot2050-basic-common.dtsi" ++#include "k3-am65-iot2050-common-pg2.dtsi" ++ ++/ { ++ compatible = "siemens,iot2050-basic-pg2", "ti,am654"; ++ model = "SIMATIC IOT2050 Basic PG2"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi u-boot/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,59 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * Common bits of the IOT2050 Advanced variant, PG1 and PG2 ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am65-iot2050-common.dtsi" ++ ++#include "k3-am65-iot2050-common-u-boot.dtsi" ++#include "k3-am65-iot2050-boot-image.dtsi" ++ ++/ { ++ memory@80000000 { ++ device_type = "memory"; ++ /* 2G RAM */ ++ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; ++ }; ++}; ++ ++&main_pmx0 { ++ main_mmc0_pins_default: main-mmc0-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ ++ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ ++ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ ++ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ ++ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ ++ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ ++ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ ++ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ ++ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ ++ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ ++ AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */ ++ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ ++ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ ++ >; ++ }; ++}; ++ ++/* eMMC */ ++&sdhci0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc0_pins_default>; ++ bus-width = <8>; ++ non-removable; ++ ti,driver-strength-ohm = <50>; ++ disable-wp; ++}; ++ ++&main_uart0 { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced.dts u-boot/arch/arm/dts/k3-am6548-iot2050-advanced.dts +--- u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6548-iot2050-advanced.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,24 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1 ++ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 ++ * ++ * Product homepage: ++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am6548-iot2050-advanced-common.dtsi" ++#include "k3-am65-iot2050-common-pg1.dtsi" ++ ++/ { ++ compatible = "siemens,iot2050-advanced", "ti,am654"; ++ model = "SIMATIC IOT2050 Advanced"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts u-boot/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts +--- u-boot-2021.10/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2 ++ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 ++ * ++ * Product homepage: ++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am6548-iot2050-advanced-common.dtsi" ++#include "k3-am65-iot2050-common-pg2.dtsi" ++ ++/ { ++ compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; ++ model = "SIMATIC IOT2050 Advanced PG2"; ++}; ++ ++&mcu_r5fss0 { ++ /* lock-step mode not supported on this board */ ++ ti,cluster-mode = <0>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am654-base-board.dts u-boot/arch/arm/dts/k3-am654-base-board.dts +--- u-boot-2021.10/arch/arm/dts/k3-am654-base-board.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am654-base-board.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -86,10 +86,36 @@ + }; + }; + +- clk_ov5640_fixed: clock { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <24000000>; ++ evm_12v0: fixedregulator-evm12v0 { ++ /* main supply */ ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_12v0"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc3v3_io: fixedregulator-vcc3v3io { ++ /* Output of TPS54334 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&evm_12v0>; ++ }; ++ ++ vdd_mmc1_sd: fixedregulator-sd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_mmc1_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ vin-supply = <&vcc3v3_io>; ++ gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; + }; + }; + +@@ -142,7 +168,7 @@ + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ +- AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ ++ AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ + AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ + >; + }; +@@ -287,23 +313,6 @@ + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +- +- ov5640: camera@3c { +- compatible = "ovti,ov5640"; +- reg = <0x3c>; +- +- clocks = <&clk_ov5640_fixed>; +- clock-names = "xclk"; +- +- port { +- csi2_cam0: endpoint { +- remote-endpoint = <&csi2_phy0>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- }; +- + }; + + &main_i2c2 { +@@ -322,7 +331,7 @@ + pinctrl-0 = <&main_spi0_pins_default>; + #address-cells = <1>; + #size-cells= <0>; +- ti,pindir-d0-out-d1-in = <1>; ++ ti,pindir-d0-out-d1-in; + + flash@0{ + compatible = "jedec,spi-nor"; +@@ -350,10 +359,10 @@ + * disable sdhci1 + */ + &sdhci1 { ++ vmmc-supply = <&vdd_mmc1_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; +- sdhci-caps-mask = <0x7 0x0>; + disable-wp; + }; + +@@ -484,9 +493,9 @@ + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; +- spi-tx-bus-width = <1>; ++ spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; +- spi-max-frequency = <40000000>; ++ spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; +@@ -497,14 +506,6 @@ + }; + }; + +-&csi2_0 { +- csi2_phy0: endpoint { +- remote-endpoint = <&csi2_cam0>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +-}; +- + &mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +@@ -538,3 +539,15 @@ + &dss { + status = "disabled"; + }; ++ ++&icssg0_mdio { ++ status = "disabled"; ++}; ++ ++&icssg1_mdio { ++ status = "disabled"; ++}; ++ ++&icssg2_mdio { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi u-boot/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -23,7 +23,7 @@ + + &cbass_main{ + u-boot,dm-spl; +- main-navss { ++ main_navss: bus@30800000 { + u-boot,dm-spl; + }; + }; +@@ -31,7 +31,7 @@ + &cbass_mcu { + u-boot,dm-spl; + +- mcu-navss { ++ mcu_navss: bus@28380000 { + u-boot,dm-spl; + + ringacc@2b800000 { +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65.dtsi u-boot/arch/arm/dts/k3-am65.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am65.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -56,7 +56,7 @@ + }; + + pmu: pmu { +- compatible = "arm,armv8-pmuv3"; ++ compatible = "arm,cortex-a53-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi u-boot/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2020-2021 ++ * ++ * Authors: ++ * Jan Kiszka ++ * Chao Zeng ++ */ ++ ++#include ++ ++/ { ++ binman { ++ filename = "flash.bin"; ++ pad-byte = <0xff>; ++ size = <0x8c0000>; ++ ++ blob-ext@0x000000 { ++ offset = <0x000000>; ++ filename = "tiboot3.bin"; ++ }; ++ ++ blob@0x080000 { ++ offset = <0x080000>; ++ filename = "tispl.bin"; ++ }; ++ ++ fit@0x280000 { ++ description = "U-Boot for IOT2050"; ++ offset = <0x280000>; ++ images { ++ u-boot { ++ description = "U-Boot"; ++ type = "standalone"; ++ arch = "arm64"; ++ os = "u-boot"; ++ compression = "none"; ++ load = <0x80800000>; ++ entry = <0x80800000>; ++ u-boot-nodtb { ++ }; ++ }; ++ ++ fdt-iot2050-basic { ++ description = "k3-am6528-iot2050-basic.dtb"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ blob { ++ filename = "arch/arm/dts/k3-am6528-iot2050-basic.dtb"; ++ }; ++ }; ++ ++ fdt-iot2050-basic-pg2 { ++ description = "k3-am6528-iot2050-basic-pg2.dtb"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ blob { ++ filename = "arch/arm/dts/k3-am6528-iot2050-basic-pg2.dtb"; ++ }; ++ }; ++ ++ fdt-iot2050-advanced { ++ description = "k3-am6548-iot2050-advanced.dtb"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ blob { ++ filename = "arch/arm/dts/k3-am6548-iot2050-advanced.dtb"; ++ }; ++ }; ++ ++ fdt-iot2050-advanced-pg2 { ++ description = "k3-am6548-iot2050-advanced-pg2.dtb"; ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ blob { ++ filename = "arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dtb"; ++ }; ++ }; ++ ++#ifdef CONFIG_WDT_K3_RTI_FW_FILE ++ k3-rti-wdt-firmware { ++ type = "firmware"; ++ load = <0x82000000>; ++ arch = "arm"; ++ compression = "none"; ++ blob-ext { ++ filename = CONFIG_WDT_K3_RTI_FW_FILE; ++ missing-msg = "k3-rti-wdt-firmware"; ++ }; ++ }; ++#endif ++ }; ++ ++ configurations { ++ default = "conf-iot2050-basic"; ++ ++ conf-iot2050-basic { ++ description = "iot2050-basic"; ++ firmware = "u-boot"; ++ fdt = "fdt-iot2050-basic"; ++#ifdef CONFIG_WDT_K3_RTI_FW_FILE ++ loadables = "k3-rti-wdt-firmware"; ++#endif ++ }; ++ ++ conf-iot2050-basic-pg2 { ++ description = "iot2050-basic-pg2"; ++ firmware = "u-boot"; ++ fdt = "fdt-iot2050-basic-pg2"; ++#ifdef CONFIG_WDT_K3_RTI_FW_FILE ++ loadables = "k3-rti-wdt-firmware"; ++#endif ++ }; ++ ++ conf-iot2050-advanced { ++ description = "iot2050-advanced"; ++ firmware = "u-boot"; ++ fdt = "fdt-iot2050-advanced"; ++#ifdef CONFIG_WDT_K3_RTI_FW_FILE ++ loadables = "k3-rti-wdt-firmware"; ++#endif ++ }; ++ ++ conf-iot2050-advanced-pg2 { ++ description = "iot2050-advanced-pg2"; ++ firmware = "u-boot"; ++ fdt = "fdt-iot2050-advanced-pg2"; ++#ifdef CONFIG_WDT_K3_RTI_FW_FILE ++ loadables = "k3-rti-wdt-firmware"; ++#endif ++ }; ++ }; ++ }; ++ ++ /* primary env */ ++ fill@0x680000 { ++ offset = <0x680000>; ++ size = <0x020000>; ++ fill-byte = [00]; ++ }; ++ /* secondary env */ ++ fill@0x6a0000 { ++ offset = <0x6a0000>; ++ size = <0x020000>; ++ fill-byte = [00]; ++ }; ++ ++ /* PG1 sysfw, basic variant */ ++ blob-ext@0x6c0000 { ++ offset = <0x6c0000>; ++ filename = "sysfw.itb"; ++ }; ++ /* PG1 sysfw, advanced variant */ ++ blob-ext@0x740000 { ++ offset = <0x740000>; ++ filename = "sysfw.itb_HS"; ++ }; ++ /* PG2 sysfw, basic variant */ ++ blob-ext@0x7c0000 { ++ offset = <0x7c0000>; ++ filename = "sysfw_sr2.itb"; ++ }; ++ /* PG2 sysfw, advanced variant */ ++ blob-ext@0x840000 { ++ offset = <0x840000>; ++ filename = "sysfw_sr2.itb_HS"; ++ }; ++ }; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common.dtsi u-boot/arch/arm/dts/k3-am65-iot2050-common.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-common.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,733 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 ++ */ ++ ++#include "k3-am654.dtsi" ++#include ++ ++/ { ++ aliases { ++ spi0 = &mcu_spi0; ++ mmc0 = &sdhci1; ++ mmc1 = &sdhci0; ++ }; ++ ++ chosen { ++ stdout-path = "serial3:115200n8"; ++ bootargs = "earlycon=ns16550a,mmio32,0x02810000"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ secure_ddr: secure-ddr@9e800000 { ++ reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ ++ alignment = <0x1000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0 0xa0000000 0 0x100000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0 0xa0100000 0 0xf00000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0 0xa1000000 0 0x100000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0 0xa1100000 0 0xf00000>; ++ no-map; ++ }; ++ ++ rtos_ipc_memory_region: ipc-memories@a2000000 { ++ reg = <0x00 0xa2000000 0x00 0x00200000>; ++ alignment = <0x1000>; ++ no-map; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_pins_default>; ++ ++ status-led-red { ++ gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; ++ panic-indicator; ++ }; ++ ++ status-led-green { ++ gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user-led1-red { ++ gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user-led1-green { ++ gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user-led2-red { ++ gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user-led2-green { ++ gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ dp_refclk: clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <19200000>; ++ }; ++}; ++ ++&wkup_pmx0 { ++ wkup_i2c0_pins_default: wkup-i2c0-pins-default { ++ pinctrl-single,pins = < ++ /* (AC7) WKUP_I2C0_SCL */ ++ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) ++ /* (AD6) WKUP_I2C0_SDA */ ++ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) ++ >; ++ }; ++ ++ mcu_i2c0_pins_default: mcu-i2c0-pins-default { ++ pinctrl-single,pins = < ++ /* (AD8) MCU_I2C0_SCL */ ++ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) ++ /* (AD7) MCU_I2C0_SDA */ ++ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) ++ >; ++ }; ++ ++ arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { ++ pinctrl-single,pins = < ++ /* (R2) WKUP_GPIO0_21 */ ++ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) ++ >; ++ }; ++ ++ push_button_pins_default: push-button-pins-default { ++ pinctrl-single,pins = < ++ /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ ++ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) ++ >; ++ }; ++ ++ arduino_uart_pins_default: arduino-uart-pins-default { ++ pinctrl-single,pins = < ++ /* (P4) MCU_UART0_RXD */ ++ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) ++ /* (P5) MCU_UART0_TXD */ ++ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) ++ >; ++ }; ++ ++ arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { ++ pinctrl-single,pins = < ++ /* (P1) WKUP_GPIO0_31 */ ++ AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) ++ /* (N3) WKUP_GPIO0_33 */ ++ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) ++ >; ++ }; ++ ++ arduino_io_oe_pins_default: arduino-io-oe-pins-default { ++ pinctrl-single,pins = < ++ /* (N4) WKUP_GPIO0_34 */ ++ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) ++ /* (M2) WKUP_GPIO0_36 */ ++ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) ++ /* (M3) WKUP_GPIO0_37 */ ++ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) ++ /* (M4) WKUP_GPIO0_38 */ ++ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) ++ /* (M1) WKUP_GPIO0_41 */ ++ AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) ++ >; ++ }; ++ ++ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { ++ pinctrl-single,pins = < ++ /* (V1) MCU_OSPI0_CLK */ ++ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) ++ /* (U2) MCU_OSPI0_DQS */ ++ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) ++ /* (U4) MCU_OSPI0_D0 */ ++ AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) ++ /* (U5) MCU_OSPI0_D1 */ ++ AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) ++ /* (R4) MCU_OSPI0_CSn0 */ ++ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) ++ >; ++ }; ++ ++ db9_com_mode_pins_default: db9-com-mode-pins-default { ++ pinctrl-single,pins = < ++ /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ ++ AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) ++ /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */ ++ AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7) ++ /* (AC1) WKUP_GPIO0_7, used as uart0 term */ ++ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7) ++ /* (AC2) WKUP_GPIO0_6, used as uart0 en */ ++ AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) ++ >; ++ }; ++ ++ leds_pins_default: leds-pins-default { ++ pinctrl-single,pins = < ++ /* (T2) WKUP_GPIO0_17, used as user led1 red */ ++ AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) ++ /* (R3) WKUP_GPIO0_22, used as user led1 green */ ++ AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7) ++ /* (R5) WKUP_GPIO0_24, used as status led red */ ++ AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7) ++ /* (N2) WKUP_GPIO0_32, used as status led green */ ++ AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7) ++ >; ++ }; ++ ++ mcu_spi0_pins_default: mcu-spi0-pins-default { ++ pinctrl-single,pins = < ++ /* (Y1) MCU_SPI0_CLK */ ++ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) ++ /* (Y3) MCU_SPI0_D0 */ ++ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) ++ /* (Y2) MCU_SPI0_D1 */ ++ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) ++ /* (Y4) MCU_SPI0_CS0 */ ++ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) ++ >; ++ }; ++ ++ minipcie_pins_default: minipcie-pins-default { ++ pinctrl-single,pins = < ++ /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ ++ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) ++ >; ++ }; ++}; ++ ++&main_pmx0 { ++ main_uart1_pins_default: main-uart1-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ ++ AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ ++ AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */ ++ AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */ ++ >; ++ }; ++ ++ main_i2c3_pins_default: main-i2c3-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ ++ AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ ++ >; ++ }; ++ ++ main_mmc1_pins_default: main-mmc1-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ ++ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ ++ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ ++ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ ++ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ ++ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ ++ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ ++ AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */ ++ >; ++ }; ++ ++ usb0_pins_default: usb0-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ ++ >; ++ }; ++ ++ usb1_pins_default: usb1-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ ++ >; ++ }; ++ ++ arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ ++ AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ ++ AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */ ++ AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */ ++ AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */ ++ AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ ++ >; ++ }; ++ ++ dss_vout1_pins_default: dss-vout1-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ ++ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ ++ AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ ++ AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ ++ AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ ++ AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ ++ AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ ++ AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ ++ AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ ++ AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ ++ AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ ++ AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ ++ AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ ++ AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ ++ AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ ++ AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ ++ AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ ++ AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ ++ AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ ++ AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ ++ AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ ++ AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ ++ AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ ++ AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ ++ AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ ++ AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ ++ AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ ++ AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ ++ >; ++ }; ++ ++ dp_pins_default: dp-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ ++ >; ++ }; ++ ++ main_i2c2_pins_default: main-i2c2-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ ++ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ ++ >; ++ }; ++}; ++ ++&main_pmx1 { ++ main_i2c0_pins_default: main-i2c0-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ ++ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ ++ >; ++ }; ++ ++ main_i2c1_pins_default: main-i2c1-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ ++ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ ++ >; ++ }; ++ ++ ecap0_pins_default: ecap0-pins-default { ++ pinctrl-single,pins = < ++ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ ++ >; ++ }; ++}; ++ ++&wkup_uart0 { ++ /* Wakeup UART is used by System firmware */ ++ status = "reserved"; ++}; ++ ++&main_uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_uart1_pins_default>; ++}; ++ ++&main_uart2 { ++ status = "disabled"; ++}; ++ ++&mcu_uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&arduino_uart_pins_default>; ++}; ++ ++&main_gpio0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>; ++ gpio-line-names = ++ "main_gpio0-base", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "IO4", "", "IO5", "", "", "IO6", "", ++ "", "", "", "IO7", "", "", "", "", "IO8", "", ++ "", "IO9"; ++}; ++ ++&wkup_gpio0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = < ++ &arduino_io_d2_to_d3_pins_default ++ &arduino_i2c_aio_switch_pins_default ++ &arduino_io_oe_pins_default ++ &push_button_pins_default ++ &db9_com_mode_pins_default ++ >; ++ gpio-line-names = ++ /* 0..9 */ ++ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", ++ "UART0-enable", "UART0-terminate", "", "WIFI-disable", ++ /* 10..19 */ ++ "", "", "", "", "", "", "", "", "", "", ++ /* 20..29 */ ++ "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", ++ /* 30..39 */ ++ "IO1", "IO2", "", "IO3", "IO17-direction", "A5", ++ "IO16-direction", "IO15-direction", "IO14-direction", "A3", ++ /* 40..49 */ ++ "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", ++ "IO11", ++ /* 50..51 */ ++ "IO12", "IO10"; ++}; ++ ++&wkup_i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wkup_i2c0_pins_default>; ++ clock-frequency = <400000>; ++}; ++ ++&mcu_i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcu_i2c0_pins_default>; ++ clock-frequency = <400000>; ++ ++ psu: regulator@60 { ++ compatible = "ti,tps62363"; ++ reg = <0x60>; ++ regulator-name = "tps62363-vout"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-boot-on; ++ ti,vsel0-state-high; ++ ti,vsel1-state-high; ++ ti,enable-vout-discharge; ++ }; ++ ++ /* D4200 */ ++ pcal9535_1: gpio@20 { ++ compatible = "nxp,pcal9535"; ++ reg = <0x20>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-line-names = ++ "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", ++ "A5-pull", "", "", ++ "IO14-enable", "IO15-enable", "IO16-enable", ++ "IO17-enable", "IO18-enable", "IO19-enable"; ++ }; ++ ++ /* D4201 */ ++ pcal9535_2: gpio@21 { ++ compatible = "nxp,pcal9535"; ++ reg = <0x21>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-line-names = ++ "IO0-direction", "IO1-direction", "IO2-direction", ++ "IO3-direction", "IO4-direction", "IO5-direction", ++ "IO6-direction", "IO7-direction", ++ "IO8-direction", "IO9-direction", "IO10-direction", ++ "IO11-direction", "IO12-direction", "IO13-direction", ++ "IO19-direction"; ++ }; ++ ++ /* D4202 */ ++ pcal9535_3: gpio@25 { ++ compatible = "nxp,pcal9535"; ++ reg = <0x25>; ++ #gpio-cells = <2>; ++ gpio-controller; ++ gpio-line-names = ++ "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", ++ "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", ++ "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", ++ "IO12-pull", "IO13-pull"; ++ }; ++}; ++ ++&main_i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_i2c0_pins_default>; ++ clock-frequency = <400000>; ++ ++ rtc: rtc8564@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ }; ++ ++ eeprom: eeprom@54 { ++ compatible = "atmel,24c08"; ++ reg = <0x54>; ++ pagesize = <16>; ++ }; ++}; ++ ++&main_i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_i2c1_pins_default>; ++ clock-frequency = <400000>; ++}; ++ ++&main_i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_i2c2_pins_default>; ++ clock-frequency = <400000>; ++}; ++ ++&main_i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_i2c3_pins_default>; ++ clock-frequency = <400000>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ edp-bridge@f { ++ compatible = "toshiba,tc358767"; ++ reg = <0x0f>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dp_pins_default>; ++ reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; ++ ++ clock-names = "ref"; ++ clocks = <&dp_refclk>; ++ ++ toshiba,hpd-pin = <0>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ bridge_in: endpoint { ++ remote-endpoint = <&dpi_out>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&mcu_cpsw { ++ status = "disabled"; ++}; ++ ++&ecap0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ecap0_pins_default>; ++}; ++ ++&sdhci1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc1_pins_default>; ++ ti,driver-strength-ohm = <50>; ++ disable-wp; ++}; ++ ++&usb0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb0_pins_default>; ++ dr_mode = "host"; ++}; ++ ++&usb1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb1_pins_default>; ++ dr_mode = "host"; ++}; ++ ++&mcu_spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcu_spi0_pins_default>; ++ ++ #address-cells = <1>; ++ #size-cells= <0>; ++ ti,pindir-d0-out-d1-in; ++}; ++ ++&tscadc0 { ++ status = "disabled"; ++}; ++ ++&tscadc1 { ++ adc { ++ ti,adc-channels = <0 1 2 3 4 5>; ++ }; ++}; ++ ++&ospi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ spi-max-frequency = <50000000>; ++ cdns,tshsl-ns = <60>; ++ cdns,tsd2d-ns = <60>; ++ cdns,tchsh-ns = <60>; ++ cdns,tslch-ns = <60>; ++ cdns,read-delay = <2>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; ++ ++&dss { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dss_vout1_pins_default>; ++ ++ assigned-clocks = <&k3_clks 67 2>; ++ assigned-clock-parents = <&k3_clks 67 5>; ++}; ++ ++&dss_ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@1 { ++ reg = <1>; ++ ++ dpi_out: endpoint { ++ remote-endpoint = <&bridge_in>; ++ }; ++ }; ++}; ++ ++&pcie0_rc { ++ status = "disabled"; ++}; ++ ++&pcie0_ep { ++ status = "disabled"; ++}; ++ ++&pcie1_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_pins_default>; ++ ++ num-lanes = <1>; ++ phys = <&serdes1 PHY_TYPE_PCIE 0>; ++ phy-names = "pcie-phy0"; ++ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; ++}; ++ ++&pcie1_ep { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster0 { ++ interrupts = <436>; ++ ++ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { ++ ti,mbox-tx = <1 0 0>; ++ ti,mbox-rx = <0 0 0>; ++ }; ++}; ++ ++&mailbox0_cluster1 { ++ interrupts = <432>; ++ ++ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { ++ ti,mbox-tx = <1 0 0>; ++ ti,mbox-rx = <0 0 0>; ++ }; ++}; ++ ++&mailbox0_cluster2 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster3 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster4 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster5 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster6 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster7 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster8 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster9 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster10 { ++ status = "disabled"; ++}; ++ ++&mailbox0_cluster11 { ++ status = "disabled"; ++}; ++ ++&mcu_r5fss0_core0 { ++ memory-region = <&mcu_r5fss0_core0_dma_memory_region>, ++ <&mcu_r5fss0_core0_memory_region>; ++ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; ++}; ++ ++&mcu_r5fss0_core1 { ++ memory-region = <&mcu_r5fss0_core1_dma_memory_region>, ++ <&mcu_r5fss0_core1_memory_region>; ++ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; ++}; ++ ++&icssg0_mdio { ++ status = "disabled"; ++}; ++ ++&icssg1_mdio { ++ status = "disabled"; ++}; ++ ++&icssg2_mdio { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi u-boot/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,46 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2021 ++ * ++ * Authors: ++ * Jan Kiszka ++ * ++ * Common bits of the IOT2050 Basic and Advanced variants, PG1 ++ */ ++ ++&dss { ++ assigned-clocks = <&k3_clks 67 2>; ++ assigned-clock-parents = <&k3_clks 67 5>; ++}; ++ ++&serdes0 { ++ status = "disabled"; ++}; ++ ++&sdhci1 { ++ no-1-8-v; ++}; ++ ++&tx_pru0_0 { ++ status = "disabled"; ++}; ++ ++&tx_pru0_1 { ++ status = "disabled"; ++}; ++ ++&tx_pru1_0 { ++ status = "disabled"; ++}; ++ ++&tx_pru1_1 { ++ status = "disabled"; ++}; ++ ++&tx_pru2_0 { ++ status = "disabled"; ++}; ++ ++&tx_pru2_1 { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi u-boot/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2021 ++ * ++ * Authors: ++ * Chao Zeng ++ * Jan Kiszka ++ * ++ * Common bits of the IOT2050 Basic and Advanced variants, PG2 ++ */ ++ ++&main_pmx0 { ++ cp2102n_reset_pin_default: cp2102n-reset-pin-default { ++ pinctrl-single,pins = < ++ /* (AF12) GPIO1_24, used as cp2102 reset */ ++ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) ++ >; ++ }; ++}; ++ ++&main_gpio1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp2102n_reset_pin_default>; ++ gpio-line-names = ++ "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", "", "", ++ "", "", "", "", "CP2102N-RESET"; ++}; ++ ++&dss { ++ /* Workaround needed to get DP clock of 154Mhz */ ++ assigned-clocks = <&k3_clks 67 0>; ++}; ++ ++&serdes0 { ++ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; ++ assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; ++}; ++ ++&dwc3_0 { ++ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ ++ <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ ++ phys = <&serdes0 PHY_TYPE_USB3 0>; ++ phy-names = "usb3-phy"; ++}; ++ ++&usb0_phy { ++ maximum-speed = "super-speed"; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi u-boot/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,99 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ * ++ * Common U-Boot bits of the IOT2050 Basic and Advanced variants ++ */ ++ ++/ { ++ aliases { ++ spi0 = &ospi0; ++ }; ++ ++ leds { ++ u-boot,dm-spl; ++ status-led-red { ++ u-boot,dm-spl; ++ }; ++ status-led-green { ++ u-boot,dm-spl; ++ }; ++ }; ++}; ++ ++&cbass_mcu { ++ u-boot,dm-spl; ++}; ++ ++&cbass_wakeup { ++ u-boot,dm-spl; ++}; ++ ++&cbass_main { ++ u-boot,dm-spl; ++ main-navss { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&wkup_pmx0 { ++ u-boot,dm-spl; ++ mcu-fss0-ospi0-pins-default { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&main_pmx0 { ++ u-boot,dm-spl; ++ main-uart1-pins-default { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&main_uart1 { ++ u-boot,dm-spl; ++ current-speed = <115200>; ++}; ++ ++&wkup_gpio0 { ++ u-boot,dm-spl; ++}; ++ ++&ospi0 { ++ u-boot,dm-spl; ++ flash@0 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&secure_proxy_main { ++ u-boot,dm-spl; ++}; ++ ++&dmsc { ++ u-boot,dm-spl; ++ k3_sysreset: sysreset-controller { ++ compatible = "ti,sci-sysreset"; ++ u-boot,dm-spl; ++ }; ++}; ++ ++&k3_pds { ++ u-boot,dm-spl; ++}; ++ ++&k3_clks { ++ u-boot,dm-spl; ++}; ++ ++&k3_reset { ++ u-boot,dm-spl; ++}; ++ ++&fss { ++ u-boot,dm-spl; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-spl.dts u-boot/arch/arm/dts/k3-am65-iot2050-spl.dts +--- u-boot-2021.10/arch/arm/dts/k3-am65-iot2050-spl.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/k3-am65-iot2050-spl.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Jan Kiszka ++ */ ++ ++/dts-v1/; ++ ++#include "k3-am65-iot2050-common.dtsi" ++#include "k3-am65-iot2050-common-u-boot.dtsi" ++ ++/ { ++ compatible = "siemens,iot2050", "ti,am654"; ++ model = "Siemens IOT2050"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-main.dtsi u-boot/arch/arm/dts/k3-am65-main.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-main.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am65-main.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -84,8 +84,6 @@ + main_uart0: serial@2800000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -95,8 +93,6 @@ + main_uart1: serial@2810000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; +@@ -105,8 +101,6 @@ + main_uart2: serial@2820000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; +@@ -256,7 +250,7 @@ + #size-cells = <0>; + }; + +- sdhci0: sdhci@4f80000 { ++ sdhci0: mmc@4f80000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; + power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; +@@ -271,21 +265,16 @@ + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; +- ti,otap-del-sel-sdr104 = <0x5>; ++ ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x5>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,otap-del-sel-hs400 = <0x0>; +- ti,itap-del-sel-legacy = <0xa>; +- ti,itap-del-sel-mmc-hs = <0x1>; +- ti,itap-del-sel-sdr12 = <0xa>; +- ti,itap-del-sel-sdr25 = <0x1>; +- ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; + }; + +- sdhci1: sdhci@4fa0000 { ++ sdhci1: mmc@4fa0000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; +@@ -302,11 +291,8 @@ + ti,otap-del-sel-ddr50 = <0x4>; + ti,otap-del-sel-ddr52 = <0x4>; + ti,otap-del-sel-hs200 = <0x7>; +- ti,itap-del-sel-legacy = <0xa>; +- ti,itap-del-sel-mmc-hs = <0x1>; +- ti,itap-del-sel-sdr12 = <0xa>; +- ti,itap-del-sel-sdr25 = <0x1>; + ti,clkbuf-sel = <0x7>; ++ ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; + dma-coherent; + }; +@@ -440,8 +426,9 @@ + #phy-cells = <0>; + }; + +- intr_main_gpio: interrupt-controller0 { ++ intr_main_gpio: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; ++ reg = <0x0 0x00a00000 0x0 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -451,18 +438,19 @@ + ti,interrupt-ranges = <0 392 32>; + }; + +- main-navss { ++ main_navss: bus@30800000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; +- ranges; ++ ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <118>; + +- intr_main_navss: interrupt-controller1 { ++ intr_main_navss: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; ++ reg = <0x0 0x310e0000 0x0 0x2000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -714,6 +702,7 @@ + dma-coherent; + interrupts = ; + msi-map = <0x0 &gic_its 0x0 0x10000>; ++ device_type = "pci"; + }; + + pcie0_ep: pcie-ep@5500000 { +@@ -746,6 +735,7 @@ + dma-coherent; + interrupts = ; + msi-map = <0x0 &gic_its 0x10000 0x10000>; ++ device_type = "pci"; + }; + + pcie1_ep: pcie-ep@5600000 { +@@ -974,18 +964,6 @@ + }; + }; + +- icssg0_iep0: iep@2e000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2e000 0x1000>; +- clocks = <&icssg0_iepclk_mux>; +- }; +- +- icssg0_iep1: iep@2f000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2f000 0x1000>; +- clocks = <&icssg0_iepclk_mux>; +- }; +- + icssg0_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; +@@ -1077,7 +1055,6 @@ + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; +- status = "disabled"; + }; + }; + +@@ -1128,18 +1105,6 @@ + }; + }; + +- icssg1_iep0: iep@2e000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2e000 0x1000>; +- clocks = <&icssg1_iepclk_mux>; +- }; +- +- icssg1_iep1: iep@2f000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2f000 0x1000>; +- clocks = <&icssg1_iepclk_mux>; +- }; +- + icssg1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; +@@ -1231,7 +1196,6 @@ + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; +- status = "disabled"; + }; + }; + +@@ -1282,18 +1246,6 @@ + }; + }; + +- icssg2_iep0: iep@2e000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2e000 0x1000>; +- clocks = <&icssg2_iepclk_mux>; +- }; +- +- icssg2_iep1: iep@2f000 { +- compatible = "ti,am654-icss-iep"; +- reg = <0x2f000 0x1000>; +- clocks = <&icssg2_iepclk_mux>; +- }; +- + icssg2_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; +@@ -1385,8 +1337,6 @@ + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; +- status = "disabled"; + }; + }; +- + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-mcu.dtsi u-boot/arch/arm/dts/k3-am65-mcu.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-mcu.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am65-mcu.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -23,8 +23,6 @@ + mcu_uart0: serial@40a00000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; +@@ -116,11 +114,11 @@ + }; + }; + +- mcu-navss { ++ mcu_navss: bus@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; +- ranges; ++ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + +@@ -308,4 +306,13 @@ + ti,loczrama = <1>; + }; + }; ++ ++ mcu_rti1: watchdog@40610000 { ++ compatible = "ti,j7-rti-wdt"; ++ reg = <0x0 0x40610000 0x0 0x100>; ++ clocks = <&k3_clks 135 0>; ++ power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; ++ assigned-clocks = <&k3_clks 135 0>; ++ assigned-clock-parents = <&k3_clks 135 4>; ++ }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-am65-wakeup.dtsi u-boot/arch/arm/dts/k3-am65-wakeup.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-am65-wakeup.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-am65-wakeup.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -6,24 +6,24 @@ + */ + + &cbass_wakeup { +- dmsc: dmsc { ++ dmsc: system-controller@44083000 { + compatible = "ti,am654-sci"; + ti,host-id = <12>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + ++ reg-names = "debug_messages"; ++ reg = <0x44083000 0x1000>; ++ + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + +- k3_clks: clocks { ++ k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; +@@ -50,8 +50,6 @@ + wkup_uart0: serial@42300000 { + compatible = "ti,am654-uart"; + reg = <0x42300000 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -69,8 +67,9 @@ + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + }; + +- intr_wkup_gpio: interrupt-controller2 { ++ intr_wkup_gpio: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; ++ reg = <0x42200000 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200-common-proc-board.dts u-boot/arch/arm/dts/k3-j7200-common-proc-board.dts +--- u-boot-2021.10/arch/arm/dts/k3-j7200-common-proc-board.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200-common-proc-board.dts 2021-11-01 17:10:13.619627671 +0100 +@@ -17,51 +17,67 @@ + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + +- aliases { +- remoteproc0 = &mcu_r5fss0_core0; +- remoteproc1 = &mcu_r5fss0_core1; +- remoteproc2 = &main_r5fss0_core0; +- remoteproc3 = &main_r5fss0_core1; ++ evm_12v0: fixedregulator-evm12v0 { ++ /* main supply */ ++ compatible = "regulator-fixed"; ++ regulator-name = "evm_12v0"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vsys_3v3: fixedregulator-vsys3v3 { ++ /* Output of LM5140 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys_3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&evm_12v0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vsys_5v0: fixedregulator-vsys5v0 { ++ /* Output of LM5140 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vsys_5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&evm_12v0>; ++ regulator-always-on; ++ regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { ++ /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; ++ vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + +- vdd_sd_dv: gpio-regulator-vdd-sd-dv { ++ vdd_sd_dv: gpio-regulator-TLV71033 { ++ /* Output of TLV71033 */ + compatible = "regulator-gpio"; +- regulator-name = "vdd_sd_dv"; ++ regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; ++ vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x0 +- 3300000 0x1>; ++ states = <1800000 0x0>, ++ <3300000 0x1>; + }; + }; + + &wkup_pmx0 { +- wkup_i2c0_pins_default: wkup-i2c0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ +- J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ +- >; +- }; +- +- wkup_gpio_pins_default: wkup-gpio-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ +- >; +- }; +- + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ +@@ -74,7 +90,7 @@ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ +- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ ++ J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; +@@ -115,15 +131,15 @@ + >; + }; + +- vdd_sd_dv_pins_default: vdd_sd_dv_pins_default { ++ main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < +- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ ++ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + >; + }; + +- main_usbss0_pins_default: main-usbss0-pins-default { ++ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < +- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ ++ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + >; + }; + }; +@@ -178,6 +194,22 @@ + status = "disabled"; + }; + ++&main_gpio2 { ++ status = "disabled"; ++}; ++ ++&main_gpio4 { ++ status = "disabled"; ++}; ++ ++&main_gpio6 { ++ status = "disabled"; ++}; ++ ++&wkup_gpio1 { ++ status = "disabled"; ++}; ++ + &mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +@@ -288,7 +320,7 @@ + }; + + &serdes0 { +- serdes0_pcie_link: link@0 { ++ serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; +@@ -296,7 +328,7 @@ + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + +- serdes0_qsgmii_link: link@1 { ++ serdes0_qsgmii_link: phy@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; +@@ -304,3 +336,17 @@ + resets = <&serdes_wiz0 3>; + }; + }; ++ ++&pcie1_rc { ++ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; ++ phys = <&serdes0_pcie_link>; ++ phy-names = "pcie-phy"; ++ num-lanes = <2>; ++}; ++ ++&pcie1_ep { ++ phys = <&serdes0_pcie_link>; ++ phy-names = "pcie-phy"; ++ num-lanes = <2>; ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi u-boot/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi 2021-11-01 17:10:13.619627671 +0100 +@@ -41,7 +41,7 @@ + u-boot,dm-spl; + }; + +- mcu-navss{ ++ mcu_navss: bus@28380000 { + u-boot,dm-spl; + #address-cells = <2>; + #size-cells = <2>; +@@ -118,10 +118,6 @@ + u-boot,dm-spl; + }; + +-&wkup_i2c0_pins_default { +- u-boot,dm-spl; +-}; +- + &wkup_i2c0 { + u-boot,dm-spl; + }; +@@ -165,10 +161,6 @@ + u-boot,dm-spl; + }; + +-&wkup_gpio_pins_default { +- u-boot,dm-spl; +-}; +- + &mcu_fss0_hpb0_pins_default { + u-boot,dm-spl; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200.dtsi u-boot/arch/arm/dts/k3-j7200.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j7200.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -114,7 +114,7 @@ + }; + + pmu: pmu { +- compatible = "arm,armv8-pmuv3"; ++ compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200-main.dtsi u-boot/arch/arm/dts/k3-j7200-main.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j7200-main.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200-main.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -2,7 +2,7 @@ + /* + * Device Tree Source for J7200 SoC Family Main Domain peripherals + * +- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ ++ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + + / { +@@ -68,8 +68,9 @@ + }; + }; + +- main_gpio_intr: interrupt-controller0 { ++ main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; ++ reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -85,9 +86,12 @@ + #size-cells = <2>; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <199>; ++ dma-coherent; ++ dma-ranges; + +- main_navss_intr: interrupt-controller1 { ++ main_navss_intr: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; ++ reg = <0x00 0x310e0000 0x00 0x4000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -297,8 +301,6 @@ + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -310,8 +312,6 @@ + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -323,8 +323,6 @@ + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -336,8 +334,6 @@ + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -349,8 +345,6 @@ + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -362,8 +356,6 @@ + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -375,8 +367,6 @@ + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -388,8 +378,6 @@ + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -401,8 +389,6 @@ + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -414,8 +400,6 @@ + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -424,53 +408,6 @@ + clock-names = "fclk"; + }; + +- main_sdhci0: sdhci@4f80000 { +- compatible = "ti,j721e-sdhci-8bit"; +- reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-mmc-hs = <0x0>; +- ti,otap-del-sel-ddr52 = <0x6>; +- ti,otap-del-sel-hs200 = <0x8>; +- ti,otap-del-sel-hs400 = <0x5>; +- ti,itap-del-sel-legacy = <0x10>; +- ti,itap-del-sel-mmc-hs = <0xa>; +- ti,strobe-sel = <0x77>; +- ti,clkbuf-sel = <0x7>; +- ti,trm-icp = <0x8>; +- bus-width = <8>; +- mmc-hs400-1_8v; +- mmc-hs200-1_8v; +- mmc-ddr-1_8v; +- dma-coherent; +- }; +- +- main_sdhci1: sdhci@4fb0000 { +- compatible = "ti,j721e-sdhci-4bit"; +- reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>; +- interrupts = ; +- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; +- ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; +- ti,otap-del-sel-sdr12 = <0xf>; +- ti,otap-del-sel-sdr25 = <0xf>; +- ti,otap-del-sel-sdr50 = <0xc>; +- ti,otap-del-sel-sdr104 = <0x5>; +- ti,otap-del-sel-ddr50 = <0xc>; +- ti,itap-del-sel-legacy = <0x0>; +- ti,itap-del-sel-sd-hs = <0x0>; +- ti,itap-del-sel-sdr12 = <0x0>; +- ti,itap-del-sel-sdr25 = <0x0>; +- ti,clkbuf-sel = <0x7>; +- ti,trm-icp = <0x8>; +- dma-coherent; +- }; +- + main_i2c0: i2c@2000000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2000000 0x00 0x100>; +@@ -548,26 +485,51 @@ + power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + }; + +- main_gpio0: gpio@600000 { +- compatible = "ti,j721e-gpio", "ti,keystone-gpio"; +- reg = <0x0 0x00600000 0x0 0x100>; +- gpio-controller; +- #gpio-cells = <2>; +- interrupts = <105 0 IRQ_TYPE_EDGE_RISING>, +- <105 1 IRQ_TYPE_EDGE_RISING>, +- <105 2 IRQ_TYPE_EDGE_RISING>, +- <105 3 IRQ_TYPE_EDGE_RISING>, +- <105 4 IRQ_TYPE_EDGE_RISING>, +- <105 5 IRQ_TYPE_EDGE_RISING>, +- <105 6 IRQ_TYPE_EDGE_RISING>, +- <105 7 IRQ_TYPE_EDGE_RISING>; +- interrupt-controller; +- #interrupt-cells = <2>; +- ti,ngpio = <69>; +- ti,davinci-gpio-unbanked = <0>; +- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 105 0>; +- clock-names = "gpio"; ++ main_sdhci0: mmc@4f80000 { ++ compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; ++ reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; ++ interrupts = ; ++ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; ++ clock-names = "clk_ahb", "clk_xin"; ++ clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; ++ ti,otap-del-sel-legacy = <0x0>; ++ ti,otap-del-sel-mmc-hs = <0x0>; ++ ti,otap-del-sel-ddr52 = <0x6>; ++ ti,otap-del-sel-hs200 = <0x8>; ++ ti,otap-del-sel-hs400 = <0x5>; ++ ti,itap-del-sel-legacy = <0x10>; ++ ti,itap-del-sel-mmc-hs = <0xa>; ++ ti,strobe-sel = <0x77>; ++ ti,clkbuf-sel = <0x7>; ++ ti,trm-icp = <0x8>; ++ bus-width = <8>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ dma-coherent; ++ }; ++ ++ main_sdhci1: mmc@4fb0000 { ++ compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; ++ reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; ++ interrupts = ; ++ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; ++ clock-names = "clk_ahb", "clk_xin"; ++ clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; ++ ti,otap-del-sel-legacy = <0x0>; ++ ti,otap-del-sel-sd-hs = <0x0>; ++ ti,otap-del-sel-sdr12 = <0xf>; ++ ti,otap-del-sel-sdr25 = <0xf>; ++ ti,otap-del-sel-sdr50 = <0xc>; ++ ti,otap-del-sel-sdr104 = <0x5>; ++ ti,otap-del-sel-ddr50 = <0xc>; ++ ti,itap-del-sel-legacy = <0x0>; ++ ti,itap-del-sel-sd-hs = <0x0>; ++ ti,itap-del-sel-sdr12 = <0x0>; ++ ti,itap-del-sel-sdr25 = <0x0>; ++ ti,clkbuf-sel = <0x7>; ++ ti,trm-icp = <0x8>; ++ dma-coherent; + }; + + serdes_wiz0: wiz@5060000 { +@@ -626,6 +588,54 @@ + }; + }; + ++ pcie1_rc: pcie@2910000 { ++ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; ++ reg = <0x00 0x02910000 0x00 0x1000>, ++ <0x00 0x02917000 0x00 0x400>, ++ <0x00 0x0d800000 0x00 0x00800000>, ++ <0x00 0x18000000 0x00 0x00001000>; ++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; ++ interrupt-names = "link_state"; ++ interrupts = ; ++ device_type = "pci"; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; ++ max-link-speed = <3>; ++ num-lanes = <4>; ++ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 240 6>; ++ clock-names = "fck"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ cdns,no-bar-match-nbits = <64>; ++ vendor-id = /bits/ 16 <0x104c>; ++ device-id = /bits/ 16 <0xb00f>; ++ msi-map = <0x0 &gic_its 0x0 0x10000>; ++ dma-coherent; ++ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, ++ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; ++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; ++ }; ++ ++ pcie1_ep: pcie-ep@2910000 { ++ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; ++ reg = <0x00 0x02910000 0x00 0x1000>, ++ <0x00 0x02917000 0x00 0x400>, ++ <0x00 0x0d800000 0x00 0x00800000>, ++ <0x00 0x18000000 0x00 0x08000000>; ++ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; ++ interrupt-names = "link_state"; ++ interrupts = ; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; ++ max-link-speed = <3>; ++ num-lanes = <4>; ++ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 240 6>; ++ clock-names = "fck"; ++ max-functions = /bits/ 8 <6>; ++ dma-coherent; ++ }; ++ + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; +@@ -653,12 +663,81 @@ + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; ++ cdns,phyrst-a-enable; + }; + }; + ++ main_gpio0: gpio@600000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x00600000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <145>, <146>, <147>, <148>, ++ <149>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <69>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 105 0>; ++ clock-names = "gpio"; ++ }; ++ ++ main_gpio2: gpio@610000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x00610000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <154>, <155>, <156>, <157>, ++ <158>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <69>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 107 0>; ++ clock-names = "gpio"; ++ }; ++ ++ main_gpio4: gpio@620000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x00620000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <163>, <164>, <165>, <166>, ++ <167>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <69>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 109 0>; ++ clock-names = "gpio"; ++ }; ++ ++ main_gpio6: gpio@630000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x00630000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&main_gpio_intr>; ++ interrupts = <172>, <173>, <174>, <175>, ++ <176>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <69>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 111 0>; ++ clock-names = "gpio"; ++ }; ++ + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j7200-r5fss"; +- ti,cluster-mode = <0>; ++ ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, +@@ -672,7 +751,7 @@ + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; +- ti,sci-proc-ids = <0x06 0xFF>; ++ ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "j7200-main-r5f0_0-fw"; + ti,atcm-enable = <1>; +@@ -687,7 +766,7 @@ + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <246>; +- ti,sci-proc-ids = <0x07 0xFF>; ++ ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 246 1>; + firmware-name = "j7200-main-r5f0_1-fw"; + ti,atcm-enable = <1>; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi u-boot/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -2,11 +2,11 @@ + /* + * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals + * +- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ ++ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + + &cbass_mcu_wakeup { +- dmsc: dmsc@44083000 { ++ dmsc: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + +@@ -23,7 +23,7 @@ + #power-domain-cells = <2>; + }; + +- k3_clks: clocks { ++ k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; +@@ -73,8 +73,6 @@ + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -86,8 +84,6 @@ + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; +@@ -96,8 +92,9 @@ + clock-names = "fclk"; + }; + +- wkup_gpio_intr: interrupt-controller2 { ++ wkup_gpio_intr: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; ++ reg = <0x00 0x42200000 0x00 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -107,6 +104,38 @@ + ti,interrupt-ranges = <16 960 16>; + }; + ++ wkup_gpio0: gpio@42110000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x42110000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&wkup_gpio_intr>; ++ interrupts = <103>, <104>, <105>, <106>, <107>, <108>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <85>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 113 0>; ++ clock-names = "gpio"; ++ }; ++ ++ wkup_gpio1: gpio@42100000 { ++ compatible = "ti,j721e-gpio", "ti,keystone-gpio"; ++ reg = <0x00 0x42100000 0x00 0x100>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-parent = <&wkup_gpio_intr>; ++ interrupts = <112>, <113>, <114>, <115>, <116>, <117>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ti,ngpio = <85>; ++ ti,davinci-gpio-unbanked = <0>; ++ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; ++ clocks = <&k3_clks 114 0>; ++ clock-names = "gpio"; ++ }; ++ + mcu_navss: bus@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; +@@ -269,6 +298,23 @@ + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + }; ++ ++ ospi0: spi@47040000 { ++ compatible = "ti,am654-ospi", "cdns,qspi-nor"; ++ reg = <0x0 0x47040000 0x0 0x100>, ++ <0x5 0x00000000 0x1 0x0000000>; ++ interrupts = ; ++ cdns,fifo-depth = <256>; ++ cdns,fifo-width = <4>; ++ cdns,trigger-address = <0x0>; ++ clocks = <&k3_clks 103 0>; ++ assigned-clocks = <&k3_clks 103 0>; ++ assigned-clock-parents = <&k3_clks 103 2>; ++ assigned-clock-rates = <166666666>; ++ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; + }; + + tscadc0: tscadc@40200000 { +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j7200-som-p0.dtsi u-boot/arch/arm/dts/k3-j7200-som-p0.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j7200-som-p0.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j7200-som-p0.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ ++ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + + /dts-v1/; +@@ -25,6 +25,60 @@ + alignment = <0x1000>; + no-map; + }; ++ ++ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa0100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa1100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core0_memory_region: r5f-memory@a2100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa2100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3000000 0x00 0x100000>; ++ no-map; ++ }; ++ ++ main_r5fss0_core1_memory_region: r5f-memory@a3100000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x00 0xa3100000 0x00 0xf00000>; ++ no-map; ++ }; ++ ++ rtos_ipc_memory_region: ipc-memories@a4000000 { ++ reg = <0x00 0xa4000000 0x00 0x00800000>; ++ alignment = <0x1000>; ++ no-map; ++ }; + }; + }; + +@@ -46,6 +100,22 @@ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; ++ ++ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { ++ pinctrl-single,pins = < ++ J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ ++ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ ++ J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ ++ J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ ++ J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ ++ J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ ++ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ ++ J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ ++ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ ++ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ ++ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ ++ >; ++ }; + }; + + &main_pmx0 { +@@ -141,6 +211,30 @@ + status = "disabled"; + }; + ++&mcu_r5fss0_core0 { ++ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; ++ memory-region = <&mcu_r5fss0_core0_dma_memory_region>, ++ <&mcu_r5fss0_core0_memory_region>; ++}; ++ ++&mcu_r5fss0_core1 { ++ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; ++ memory-region = <&mcu_r5fss0_core1_dma_memory_region>, ++ <&mcu_r5fss0_core1_memory_region>; ++}; ++ ++&main_r5fss0_core0 { ++ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; ++ memory-region = <&main_r5fss0_core0_dma_memory_region>, ++ <&main_r5fss0_core0_memory_region>; ++}; ++ ++&main_r5fss0_core1 { ++ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; ++ memory-region = <&main_r5fss0_core1_dma_memory_region>, ++ <&main_r5fss0_core1_memory_region>; ++}; ++ + &main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; +@@ -157,3 +251,23 @@ + "GPIO_LIN_EN", "CAN_STB"; + }; + }; ++ ++&ospi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; ++ ++ flash@0{ ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-tx-bus-width = <8>; ++ spi-rx-bus-width = <8>; ++ spi-max-frequency = <25000000>; ++ cdns,tshsl-ns = <60>; ++ cdns,tsd2d-ns = <60>; ++ cdns,tchsh-ns = <60>; ++ cdns,tslch-ns = <60>; ++ cdns,read-delay = <4>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e-common-proc-board.dts u-boot/arch/arm/dts/k3-j721e-common-proc-board.dts +--- u-boot-2021.10/arch/arm/dts/k3-j721e-common-proc-board.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e-common-proc-board.dts 2021-11-01 17:10:13.622960822 +0100 +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + / { + chosen { +@@ -237,7 +238,7 @@ + J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ +- J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ ++ J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; +@@ -358,7 +359,7 @@ + }; + + &serdes3 { +- serdes3_usb_link: link@0 { ++ serdes3_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; +@@ -635,8 +636,45 @@ + status = "disabled"; + }; + ++&cmn_refclk1 { ++ clock-frequency = <100000000>; ++}; ++ ++&wiz0_pll1_refclk { ++ assigned-clocks = <&wiz0_pll1_refclk>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ ++&wiz0_refclk_dig { ++ assigned-clocks = <&wiz0_refclk_dig>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ ++&wiz1_pll1_refclk { ++ assigned-clocks = <&wiz1_pll1_refclk>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ ++&wiz1_refclk_dig { ++ assigned-clocks = <&wiz1_refclk_dig>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ ++&wiz2_pll1_refclk { ++ assigned-clocks = <&wiz2_pll1_refclk>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ ++&wiz2_refclk_dig { ++ assigned-clocks = <&wiz2_refclk_dig>; ++ assigned-clock-parents = <&cmn_refclk1>; ++}; ++ + &serdes0 { +- serdes0_pcie_link: link@0 { ++ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; ++ assigned-clock-parents = <&wiz0_pll1_refclk>; ++ ++ serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; +@@ -646,7 +684,10 @@ + }; + + &serdes1 { +- serdes1_pcie_link: link@0 { ++ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; ++ assigned-clock-parents = <&wiz1_pll1_refclk>; ++ ++ serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; +@@ -656,7 +697,10 @@ + }; + + &serdes2 { +- serdes2_pcie_link: link@0 { ++ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; ++ assigned-clock-parents = <&wiz2_pll1_refclk>; ++ ++ serdes2_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; +@@ -718,3 +762,11 @@ + &dss { + status = "disabled"; + }; ++ ++&icssg0_mdio { ++ status = "disabled"; ++}; ++ ++&icssg1_mdio { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi u-boot/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -34,7 +34,7 @@ + &cbass_main{ + u-boot,dm-spl; + +- main-navss { ++ main_navss: bus@30000000 { + u-boot,dm-spl; + }; + }; +@@ -50,7 +50,7 @@ + u-boot,dm-spl; + }; + +- mcu-navss { ++ mcu_navss: bus@28380000 { + u-boot,dm-spl; + + ringacc@2b800000 { +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e.dtsi u-boot/arch/arm/dts/k3-j721e.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j721e.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -115,7 +115,7 @@ + }; + + pmu: pmu { +- compatible = "arm,armv8-pmuv3"; ++ compatible = "arm,cortex-a72-pmu"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; +@@ -126,7 +126,6 @@ + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ +- <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ + <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e-main.dtsi u-boot/arch/arm/dts/k3-j721e-main.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j721e-main.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e-main.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -8,6 +8,20 @@ + #include + #include + ++/ { ++ cmn_refclk: clock-cmnrefclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ cmn_refclk1: clock-cmnrefclk1 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++}; ++ + &cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; +@@ -28,38 +42,6 @@ + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + +- pcie0_ctrl: syscon@4070 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x00004070 0x4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x4070 0x4070 0x4>; +- }; +- +- pcie1_ctrl: syscon@4074 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x00004074 0x4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x4074 0x4074 0x4>; +- }; +- +- pcie2_ctrl: syscon@4078 { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x00004078 0x4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x4078 0x4078 0x4>; +- }; +- +- pcie3_ctrl: syscon@407c { +- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; +- reg = <0x0000407c 0x4>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0x407c 0x407c 0x4>; +- }; +- + serdes_ln_ctrl: mux@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x50>; +@@ -108,8 +90,9 @@ + }; + }; + +- main_gpio_intr: interrupt-controller0 { ++ main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; ++ reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -119,18 +102,19 @@ + ti,interrupt-ranges = <8 392 56>; + }; + +- main-navss { ++ main_navss: bus@30000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; +- ranges; ++ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <199>; + +- main_navss_intr: interrupt-controller1 { ++ main_navss_intr: interrupt-controller@310e0000 { + compatible = "ti,sci-intr"; ++ reg = <0x0 0x310e0000 0x0 0x4000>; + ti,intr-trigger-type = <4>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -368,24 +352,12 @@ + pinctrl-single,function-mask = <0xffffffff>; + }; + +- dummy_cmn_refclk: dummy-cmn-refclk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- }; +- +- dummy_cmn_refclk1: dummy-cmn-refclk1 { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <100000000>; +- }; +- + serdes_wiz0: wiz@5000000 { + compatible = "ti,j721e-wiz-16g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; + assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; +@@ -394,21 +366,21 @@ + ranges = <0x5000000 0x0 0x5000000 0x10000>; + + wiz0_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 292 11>, <&cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 11>; + }; + + wiz0_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 292 0>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 0>; + }; + + wiz0_refclk_dig: refclk-dig { +- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 11>; +@@ -430,10 +402,13 @@ + reg = <0x5000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; ++ #clock-cells = <1>; + resets = <&serdes_wiz0 0>; + reset-names = "sierra_reset"; +- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; ++ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, ++ <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; ++ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", ++ "pll0_refclk", "pll1_refclk"; + }; + }; + +@@ -442,7 +417,7 @@ + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; + assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; +@@ -451,21 +426,21 @@ + ranges = <0x5010000 0x0 0x5010000 0x10000>; + + wiz1_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 293 13>, <&cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll0_refclk>; + assigned-clock-parents = <&k3_clks 293 13>; + }; + + wiz1_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 293 0>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&k3_clks 293 0>; + }; + + wiz1_refclk_dig: refclk-dig { +- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&k3_clks 293 13>; +@@ -487,10 +462,13 @@ + reg = <0x5010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; ++ #clock-cells = <1>; + resets = <&serdes_wiz1 0>; + reset-names = "sierra_reset"; +- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; ++ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, ++ <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; ++ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", ++ "pll0_refclk", "pll1_refclk"; + }; + }; + +@@ -499,7 +477,7 @@ + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; + assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; +@@ -508,21 +486,21 @@ + ranges = <0x5020000 0x0 0x5020000 0x10000>; + + wiz2_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 294 11>, <&cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_pll0_refclk>; + assigned-clock-parents = <&k3_clks 294 11>; + }; + + wiz2_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 294 0>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&k3_clks 294 0>; + }; + + wiz2_refclk_dig: refclk-dig { +- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&k3_clks 294 11>; +@@ -544,10 +522,13 @@ + reg = <0x5020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; ++ #clock-cells = <1>; + resets = <&serdes_wiz2 0>; + reset-names = "sierra_reset"; +- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; ++ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, ++ <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; ++ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", ++ "pll0_refclk", "pll1_refclk"; + }; + }; + +@@ -556,7 +537,7 @@ + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; +- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; + assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; +@@ -565,21 +546,21 @@ + ranges = <0x5030000 0x0 0x5030000 0x10000>; + + wiz3_pll0_refclk: pll0-refclk { +- clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; ++ clocks = <&k3_clks 295 9>, <&cmn_refclk>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 9>; + }; + + wiz3_pll1_refclk: pll1-refclk { +- clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 295 0>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_pll1_refclk>; + assigned-clock-parents = <&k3_clks 295 0>; + }; + + wiz3_refclk_dig: refclk-dig { +- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; ++ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; + #clock-cells = <0>; + assigned-clocks = <&wiz3_refclk_dig>; + assigned-clock-parents = <&k3_clks 295 9>; +@@ -601,10 +582,13 @@ + reg = <0x5030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; ++ #clock-cells = <1>; + resets = <&serdes_wiz3 0>; + reset-names = "sierra_reset"; +- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; +- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; ++ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, ++ <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; ++ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", ++ "pll0_refclk", "pll1_refclk"; + }; + }; + +@@ -618,7 +602,7 @@ + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; +- ti,syscon-pcie-ctrl = <&pcie0_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; +@@ -645,13 +629,12 @@ + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; +- ti,syscon-pcie-ctrl = <&pcie0_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; +- cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; +@@ -667,7 +650,7 @@ + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; +- ti,syscon-pcie-ctrl = <&pcie1_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; +@@ -694,13 +677,12 @@ + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; +- ti,syscon-pcie-ctrl = <&pcie1_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; +- cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; +@@ -716,7 +698,7 @@ + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; +- ti,syscon-pcie-ctrl = <&pcie2_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; +@@ -743,13 +725,12 @@ + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; +- ti,syscon-pcie-ctrl = <&pcie2_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; +- cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; +@@ -765,7 +746,7 @@ + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; +- ti,syscon-pcie-ctrl = <&pcie3_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; +@@ -792,13 +773,12 @@ + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; +- ti,syscon-pcie-ctrl = <&pcie3_ctrl>; ++ ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; +- cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; +@@ -809,8 +789,6 @@ + main_uart0: serial@2800000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -822,8 +800,6 @@ + main_uart1: serial@2810000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -835,8 +811,6 @@ + main_uart2: serial@2820000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -848,8 +822,6 @@ + main_uart3: serial@2830000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -861,8 +833,6 @@ + main_uart4: serial@2840000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -874,8 +844,6 @@ + main_uart5: serial@2850000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -887,8 +855,6 @@ + main_uart6: serial@2860000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -900,8 +866,6 @@ + main_uart7: serial@2870000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02870000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -913,8 +877,6 @@ + main_uart8: serial@2880000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02880000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -926,8 +888,6 @@ + main_uart9: serial@2890000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x02890000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -1068,13 +1028,13 @@ + clock-names = "gpio"; + }; + +- main_sdhci0: sdhci@4f80000 { ++ main_sdhci0: mmc@4f80000 { + compatible = "ti,j721e-sdhci-8bit"; + reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; + interrupts = ; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; ++ clock-names = "clk_ahb", "clk_xin"; ++ clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; + assigned-clocks = <&k3_clks 91 1>; + assigned-clock-parents = <&k3_clks 91 2>; + bus-width = <8>; +@@ -1084,24 +1044,26 @@ + ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x6>; ++ ti,otap-del-sel-hs400 = <0x0>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; + ti,trm-icp = <0x8>; ++ ti,strobe-sel = <0x77>; + dma-coherent; + }; + +- main_sdhci1: sdhci@4fb0000 { ++ main_sdhci1: mmc@4fb0000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; + interrupts = ; + power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; ++ clock-names = "clk_ahb", "clk_xin"; ++ clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; + assigned-clocks = <&k3_clks 92 0>; + assigned-clock-parents = <&k3_clks 92 1>; + ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; ++ ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; +@@ -1117,17 +1079,17 @@ + sdhci-caps-mask = <0x2 0x0>; + }; + +- main_sdhci2: sdhci@4f98000 { ++ main_sdhci2: mmc@4f98000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; + interrupts = ; + power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; +- clock-names = "clk_xin", "clk_ahb"; +- clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; ++ clock-names = "clk_ahb", "clk_xin"; ++ clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; + assigned-clocks = <&k3_clks 93 0>; + assigned-clock-parents = <&k3_clks 93 1>; + ti,otap-del-sel-legacy = <0x0>; +- ti,otap-del-sel-sd-hs = <0x0>; ++ ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; +@@ -1696,4 +1658,286 @@ + resets = <&k3_reset 15 1>; + firmware-name = "j7-c71_0-fw"; + }; ++ ++ icssg0: icssg@b000000 { ++ compatible = "ti,j721e-icssg"; ++ reg = <0x00 0xb000000 0x00 0x80000>; ++ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x00 0x0b000000 0x100000>; ++ ++ icssg0_mem: memories@0 { ++ reg = <0x0 0x2000>, ++ <0x2000 0x2000>, ++ <0x10000 0x10000>; ++ reg-names = "dram0", "dram1", ++ "shrdram2"; ++ }; ++ ++ icssg0_cfg: cfg@26000 { ++ compatible = "ti,pruss-cfg", "syscon"; ++ reg = <0x26000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x26000 0x2000>; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ icssg0_coreclk_mux: coreclk-mux@3c { ++ reg = <0x3c>; ++ #clock-cells = <0>; ++ clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ ++ <&k3_clks 119 1>; /* icssg0_iclk */ ++ assigned-clocks = <&icssg0_coreclk_mux>; ++ assigned-clock-parents = <&k3_clks 119 1>; ++ }; ++ ++ icssg0_iepclk_mux: iepclk-mux@30 { ++ reg = <0x30>; ++ #clock-cells = <0>; ++ clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ ++ <&icssg0_coreclk_mux>; /* core_clk */ ++ assigned-clocks = <&icssg0_iepclk_mux>; ++ assigned-clock-parents = <&icssg0_coreclk_mux>; ++ }; ++ }; ++ }; ++ ++ icssg0_mii_rt: mii-rt@32000 { ++ compatible = "ti,pruss-mii", "syscon"; ++ reg = <0x32000 0x100>; ++ }; ++ ++ icssg0_mii_g_rt: mii-g-rt@33000 { ++ compatible = "ti,pruss-mii-g", "syscon"; ++ reg = <0x33000 0x1000>; ++ }; ++ ++ icssg0_intc: interrupt-controller@20000 { ++ compatible = "ti,icssg-intc"; ++ reg = <0x20000 0x2000>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "host_intr0", "host_intr1", ++ "host_intr2", "host_intr3", ++ "host_intr4", "host_intr5", ++ "host_intr6", "host_intr7"; ++ }; ++ ++ pru0_0: pru@34000 { ++ compatible = "ti,j721e-pru"; ++ reg = <0x34000 0x3000>, ++ <0x22000 0x100>, ++ <0x22400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-pru0_0-fw"; ++ }; ++ ++ rtu0_0: rtu@4000 { ++ compatible = "ti,j721e-rtu"; ++ reg = <0x4000 0x2000>, ++ <0x23000 0x100>, ++ <0x23400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-rtu0_0-fw"; ++ }; ++ ++ tx_pru0_0: txpru@a000 { ++ compatible = "ti,j721e-tx-pru"; ++ reg = <0xa000 0x1800>, ++ <0x25000 0x100>, ++ <0x25400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-txpru0_0-fw"; ++ }; ++ ++ pru0_1: pru@38000 { ++ compatible = "ti,j721e-pru"; ++ reg = <0x38000 0x3000>, ++ <0x24000 0x100>, ++ <0x24400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-pru0_1-fw"; ++ }; ++ ++ rtu0_1: rtu@6000 { ++ compatible = "ti,j721e-rtu"; ++ reg = <0x6000 0x2000>, ++ <0x23800 0x100>, ++ <0x23c00 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-rtu0_1-fw"; ++ }; ++ ++ tx_pru0_1: txpru@c000 { ++ compatible = "ti,j721e-tx-pru"; ++ reg = <0xc000 0x1800>, ++ <0x25800 0x100>, ++ <0x25c00 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-txpru0_1-fw"; ++ }; ++ ++ icssg0_mdio: mdio@32400 { ++ compatible = "ti,davinci_mdio"; ++ reg = <0x32400 0x100>; ++ clocks = <&k3_clks 119 1>; ++ clock-names = "fck"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus_freq = <1000000>; ++ }; ++ }; ++ ++ icssg1: icssg@b100000 { ++ compatible = "ti,j721e-icssg"; ++ reg = <0x00 0xb100000 0x00 0x80000>; ++ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x00 0x0b100000 0x100000>; ++ ++ icssg1_mem: memories@b100000 { ++ reg = <0x0 0x2000>, ++ <0x2000 0x2000>, ++ <0x10000 0x10000>; ++ reg-names = "dram0", "dram1", ++ "shrdram2"; ++ }; ++ ++ icssg1_cfg: cfg@26000 { ++ compatible = "ti,pruss-cfg", "syscon"; ++ reg = <0x26000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x26000 0x2000>; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ icssg1_coreclk_mux: coreclk-mux@3c { ++ reg = <0x3c>; ++ #clock-cells = <0>; ++ clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ ++ <&k3_clks 120 4>; /* icssg1_iclk */ ++ assigned-clocks = <&icssg1_coreclk_mux>; ++ assigned-clock-parents = <&k3_clks 120 4>; ++ }; ++ ++ icssg1_iepclk_mux: iepclk-mux@30 { ++ reg = <0x30>; ++ #clock-cells = <0>; ++ clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ ++ <&icssg1_coreclk_mux>; /* core_clk */ ++ assigned-clocks = <&icssg1_iepclk_mux>; ++ assigned-clock-parents = <&icssg1_coreclk_mux>; ++ }; ++ }; ++ }; ++ ++ icssg1_mii_rt: mii-rt@32000 { ++ compatible = "ti,pruss-mii", "syscon"; ++ reg = <0x32000 0x100>; ++ }; ++ ++ icssg1_mii_g_rt: mii-g-rt@33000 { ++ compatible = "ti,pruss-mii-g", "syscon"; ++ reg = <0x33000 0x1000>; ++ }; ++ ++ icssg1_intc: interrupt-controller@20000 { ++ compatible = "ti,icssg-intc"; ++ reg = <0x20000 0x2000>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "host_intr0", "host_intr1", ++ "host_intr2", "host_intr3", ++ "host_intr4", "host_intr5", ++ "host_intr6", "host_intr7"; ++ }; ++ ++ pru1_0: pru@34000 { ++ compatible = "ti,j721e-pru"; ++ reg = <0x34000 0x4000>, ++ <0x22000 0x100>, ++ <0x22400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-pru1_0-fw"; ++ }; ++ ++ rtu1_0: rtu@4000 { ++ compatible = "ti,j721e-rtu"; ++ reg = <0x4000 0x2000>, ++ <0x23000 0x100>, ++ <0x23400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-rtu1_0-fw"; ++ }; ++ ++ tx_pru1_0: txpru@a000 { ++ compatible = "ti,j721e-tx-pru"; ++ reg = <0xa000 0x1800>, ++ <0x25000 0x100>, ++ <0x25400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-txpru1_0-fw"; ++ }; ++ ++ pru1_1: pru@38000 { ++ compatible = "ti,j721e-pru"; ++ reg = <0x38000 0x4000>, ++ <0x24000 0x100>, ++ <0x24400 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-pru1_1-fw"; ++ }; ++ ++ rtu1_1: rtu@6000 { ++ compatible = "ti,j721e-rtu"; ++ reg = <0x6000 0x2000>, ++ <0x23800 0x100>, ++ <0x23c00 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-rtu1_1-fw"; ++ }; ++ ++ tx_pru1_1: txpru@c000 { ++ compatible = "ti,j721e-tx-pru"; ++ reg = <0xc000 0x1800>, ++ <0x25800 0x100>, ++ <0x25c00 0x100>; ++ reg-names = "iram", "control", "debug"; ++ firmware-name = "j7-txpru1_1-fw"; ++ }; ++ ++ icssg1_mdio: mdio@32400 { ++ compatible = "ti,davinci_mdio"; ++ reg = <0x32400 0x100>; ++ clocks = <&k3_clks 120 4>; ++ clock-names = "fck"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus_freq = <1000000>; ++ }; ++ }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi u-boot/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -6,7 +6,7 @@ + */ + + &cbass_mcu_wakeup { +- dmsc: dmsc@44083000 { ++ dmsc: system-controller@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + +@@ -23,7 +23,7 @@ + #power-domain-cells = <2>; + }; + +- k3_clks: clocks { ++ k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; +@@ -73,8 +73,6 @@ + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; +@@ -86,8 +84,6 @@ + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; +- reg-shift = <2>; +- reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; +@@ -96,8 +92,9 @@ + clock-names = "fclk"; + }; + +- wkup_gpio_intr: interrupt-controller2 { ++ wkup_gpio_intr: interrupt-controller@42200000 { + compatible = "ti,sci-intr"; ++ reg = <0x00 0x42200000 0x00 0x400>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; +@@ -179,26 +176,8 @@ + #size-cells = <2>; + ranges; + +- hbmc_mux: hbmc-mux { +- compatible = "mmio-mux"; +- #mux-control-cells = <1>; +- mux-reg-masks = <0x4 0x2>; /* HBMC select */ +- }; +- +- hbmc: hyperbus@47034000 { +- compatible = "ti,j721e-hbmc", "ti,am654-hbmc"; +- reg = <0x0 0x47034000 0x0 0x100>, +- <0x5 0x00000000 0x1 0x0000000>; +- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; +- #address-cells = <2>; +- #size-cells = <1>; +- mux-controls = <&hbmc_mux 0>; +- assigned-clocks = <&k3_clks 102 0>; +- assigned-clock-rates = <250000000>; +- }; +- + ospi0: spi@47040000 { +- compatible = "ti,am654-ospi"; ++ compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x0 0x47040000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + interrupts = ; +@@ -215,7 +194,7 @@ + }; + + ospi1: spi@47050000 { +- compatible = "ti,am654-ospi"; ++ compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x0 0x47050000 0x0 0x100>, + <0x7 0x00000000 0x1 0x00000000>; + interrupts = ; +@@ -267,11 +246,11 @@ + }; + }; + +- mcu-navss { ++ mcu_navss: bus@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; +- ranges; ++ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + +diff -ruN u-boot-2021.10/arch/arm/dts/k3-j721e-som-p0.dtsi u-boot/arch/arm/dts/k3-j721e-som-p0.dtsi +--- u-boot-2021.10/arch/arm/dts/k3-j721e-som-p0.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/k3-j721e-som-p0.dtsi 2021-11-01 17:10:13.622960822 +0100 +@@ -150,25 +150,6 @@ + >; + }; + +- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { +- pinctrl-single,pins = < +- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ +- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ +- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ +- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ +- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ +- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ +- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ +- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ +- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ +- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ +- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ +- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ +- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ +- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ +- >; +- }; +- + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ +@@ -186,19 +167,6 @@ + }; + }; + +-&hbmc { +- status = "disabled"; +- pinctrl-names = "default"; +- pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; +- ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */ +- <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */ +- +- flash@0,0 { +- compatible = "cypress,hyperflash", "cfi-flash"; +- reg = <0x0 0x0 0x4000000>; +- }; +-}; +- + &ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; +@@ -206,9 +174,9 @@ + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; +- spi-tx-bus-width = <1>; ++ spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; +- spi-max-frequency = <40000000>; ++ spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; +diff -ruN u-boot-2021.10/arch/arm/dts/ls1021a-tsn.dts u-boot/arch/arm/dts/ls1021a-tsn.dts +--- u-boot-2021.10/arch/arm/dts/ls1021a-tsn.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ls1021a-tsn.dts 2021-11-01 17:10:13.626293972 +0100 +@@ -1,5 +1,5 @@ + // SPDX-License-Identifier: GPL-2.0 +-/* Copyright 2016-2018 NXP Semiconductors ++/* Copyright 2016-2018 NXP + * Copyright 2019 Vladimir Oltean + */ + +diff -ruN u-boot-2021.10/arch/arm/dts/Makefile u-boot/arch/arm/dts/Makefile +--- u-boot-2021.10/arch/arm/dts/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/Makefile 2021-11-01 17:10:13.559630952 +0100 +@@ -158,30 +158,36 @@ + s5p4418-nanopi2.dtb + + dtb-$(CONFIG_ARCH_MESON) += \ ++ meson-axg-s400.dtb \ ++ meson-axg-jethome-jethub-j100.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-odroidc2.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-p200.dtb \ + meson-gxbb-p201.dtb \ +- meson-gxl-s905x-p212.dtb \ + meson-gxl-s805x-libretech-ac.dtb \ ++ meson-gxl-s905d-libretech-pc.dtb \ ++ meson-gxl-s905w-jethome-jethub-j80.dtb \ ++ meson-gxl-s905x-khadas-vim.dtb \ + meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-libretech-cc-v2.dtb \ +- meson-gxl-s905x-khadas-vim.dtb \ +- meson-gxl-s905d-libretech-pc.dtb \ ++ meson-gxl-s905x-p212.dtb \ + meson-gxm-khadas-vim2.dtb \ + meson-gxm-s912-libretech-pc.dtb \ + meson-gxm-wetek-core2.dtb \ +- meson-axg-s400.dtb \ +- meson-g12a-u200.dtb \ ++ meson-g12a-radxa-zero.dtb \ + meson-g12a-sei510.dtb \ ++ meson-g12a-u200.dtb \ ++ meson-g12b-a311d-khadas-vim3.dtb \ + meson-g12b-gtking.dtb \ + meson-g12b-gtking-pro.dtb \ ++ meson-g12b-gsking-x.dtb \ + meson-g12b-odroid-n2.dtb \ + meson-g12b-odroid-n2-plus.dtb \ +- meson-g12b-a311d-khadas-vim3.dtb \ ++ meson-sm1-bananapi-m5.dtb \ + meson-sm1-khadas-vim3l.dtb \ + meson-sm1-odroid-c4.dtb \ ++ meson-sm1-odroid-hc4.dtb \ + meson-sm1-sei610.dtb + dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ +@@ -642,6 +648,7 @@ + sun50i-h6-orangepi-lite2.dtb \ + sun50i-h6-orangepi-one-plus.dtb \ + sun50i-h6-pine-h64.dtb \ ++ sun50i-h6-pine-h64-model-b.dtb \ + sun50i-h6-tanix-tx6.dtb + dtb-$(CONFIG_MACH_SUN50I_H616) += \ + sun50i-h616-orangepi-zero2.dtb +@@ -929,7 +936,7 @@ + dtb-$(CONFIG_RZA1) += \ + r7s72100-gr-peach-u-boot.dtb + +-dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ ++dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb \ +@@ -1090,7 +1097,14 @@ + stm32mp15xx-dhcom-picoitx.dtb \ + stm32mp15xx-dhcor-avenger96.dtb + +-dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb ++dtb-$(CONFIG_SOC_K3_AM6) += \ ++ k3-am654-base-board.dtb \ ++ k3-am654-r5-base-board.dtb \ ++ k3-am65-iot2050-spl.dtb \ ++ k3-am6528-iot2050-basic.dtb \ ++ k3-am6528-iot2050-basic-pg2.dtb \ ++ k3-am6548-iot2050-advanced.dtb \ ++ k3-am6548-iot2050-advanced-pg2.dtb + dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ + k3-j721e-r5-common-proc-board.dtb \ + k3-j7200-common-proc-board.dtb \ +@@ -1120,6 +1134,8 @@ + dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb + dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb + ++dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb ++ + dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb + + dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +diff -ruN u-boot-2021.10/arch/arm/dts/meson-axg.dtsi u-boot/arch/arm/dts/meson-axg.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-axg.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-axg.dtsi 2021-11-01 17:10:13.626293972 +0100 +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + / { + compatible = "amlogic,meson-axg"; +@@ -171,6 +172,98 @@ + #size-cells = <2>; + ranges; + ++ pcieA: pcie@f9800000 { ++ compatible = "amlogic,axg-pcie", "snps,dw-pcie"; ++ reg = <0x0 0xf9800000 0x0 0x400000>, ++ <0x0 0xff646000 0x0 0x2000>, ++ <0x0 0xf9f00000 0x0 0x100000>; ++ reg-names = "elbi", "cfg", "config"; ++ interrupts = ; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; ++ bus-range = <0x0 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; ++ ++ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; ++ clock-names = "general", "pclk", "port"; ++ resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; ++ reset-names = "port", "apb"; ++ num-lanes = <1>; ++ phys = <&pcie_phy>; ++ phy-names = "pcie"; ++ status = "disabled"; ++ }; ++ ++ pcieB: pcie@fa000000 { ++ compatible = "amlogic,axg-pcie", "snps,dw-pcie"; ++ reg = <0x0 0xfa000000 0x0 0x400000>, ++ <0x0 0xff648000 0x0 0x2000>, ++ <0x0 0xfa400000 0x0 0x100000>; ++ reg-names = "elbi", "cfg", "config"; ++ interrupts = ; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; ++ bus-range = <0x0 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; ++ ++ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; ++ clock-names = "general", "pclk", "port"; ++ resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; ++ reset-names = "port", "apb"; ++ num-lanes = <1>; ++ phys = <&pcie_phy>; ++ phy-names = "pcie"; ++ status = "disabled"; ++ }; ++ ++ usb: usb@ffe09080 { ++ compatible = "amlogic,meson-axg-usb-ctrl"; ++ reg = <0x0 0xffe09080 0x0 0x20>; ++ interrupts = ; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; ++ clock-names = "usb_ctrl", "ddr"; ++ resets = <&reset RESET_USB_OTG>; ++ ++ dr_mode = "otg"; ++ ++ phys = <&usb2_phy1>; ++ phy-names = "usb2-phy1"; ++ ++ dwc2: usb@ff400000 { ++ compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; ++ reg = <0x0 0xff400000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&clkc CLKID_USB1>; ++ clock-names = "otg"; ++ phys = <&usb2_phy1>; ++ dr_mode = "peripheral"; ++ g-rx-fifo-size = <192>; ++ g-np-tx-fifo-size = <128>; ++ g-tx-fifo-size = <128 128 16 16 16>; ++ }; ++ ++ dwc3: usb@ff500000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0xff500000 0x0 0x100000>; ++ interrupts = ; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ snps,dis_u2_susphy_quirk; ++ }; ++ }; ++ + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", +@@ -187,9 +280,19 @@ + "timing-adjustment"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; ++ power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; + status = "disabled"; + }; + ++ pcie_phy: phy@ff644000 { ++ compatible = "amlogic,axg-pcie-phy"; ++ reg = <0x0 0xff644000 0x0 0x1c>; ++ resets = <&reset RESET_PCIE_PHY>; ++ phys = <&mipi_pcie_analog_dphy>; ++ phy-names = "analog"; ++ #phy-cells = <0>; ++ }; ++ + pdm: audio-controller@ff632000 { + compatible = "amlogic,axg-pdm"; + reg = <0x0 0xff632000 0x0 0x34>; +@@ -1117,6 +1220,52 @@ + clocks = <&xtal>; + clock-names = "xtal"; + }; ++ ++ pwrc: power-controller { ++ compatible = "amlogic,meson-axg-pwrc"; ++ #power-domain-cells = <1>; ++ amlogic,ao-sysctrl = <&sysctrl_AO>; ++ resets = <&reset RESET_VIU>, ++ <&reset RESET_VENC>, ++ <&reset RESET_VCBUS>, ++ <&reset RESET_VENCL>, ++ <&reset RESET_VID_LOCK>; ++ reset-names = "viu", "venc", "vcbus", ++ "vencl", "vid_lock"; ++ clocks = <&clkc CLKID_VPU>, ++ <&clkc CLKID_VAPB>; ++ clock-names = "vpu", "vapb"; ++ /* ++ * VPU clocking is provided by two identical clock paths ++ * VPU_0 and VPU_1 muxed to a single clock by a glitch ++ * free mux to safely change frequency while running. ++ * Same for VAPB but with a final gate after the glitch free mux. ++ */ ++ assigned-clocks = <&clkc CLKID_VPU_0_SEL>, ++ <&clkc CLKID_VPU_0>, ++ <&clkc CLKID_VPU>, /* Glitch free mux */ ++ <&clkc CLKID_VAPB_0_SEL>, ++ <&clkc CLKID_VAPB_0>, ++ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ ++ assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, ++ <0>, /* Do Nothing */ ++ <&clkc CLKID_VPU_0>, ++ <&clkc CLKID_FCLK_DIV4>, ++ <0>, /* Do Nothing */ ++ <&clkc CLKID_VAPB_0>; ++ assigned-clock-rates = <0>, /* Do Nothing */ ++ <250000000>, ++ <0>, /* Do Nothing */ ++ <0>, /* Do Nothing */ ++ <250000000>, ++ <0>; /* Do Nothing */ ++ }; ++ ++ mipi_pcie_analog_dphy: phy { ++ compatible = "amlogic,axg-mipi-pcie-analog-phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; + }; + }; + +@@ -1129,6 +1278,19 @@ + #mbox-cells = <1>; + }; + ++ mipi_dphy: phy@ff640000 { ++ compatible = "amlogic,axg-mipi-dphy"; ++ reg = <0x0 0xff640000 0x0 0x100>; ++ clocks = <&clkc CLKID_MIPI_DSI_PHY>; ++ clock-names = "pclk"; ++ resets = <&reset RESET_MIPI_PHY>; ++ reset-names = "phy"; ++ phys = <&mipi_pcie_analog_dphy>; ++ phy-names = "analog"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; +@@ -1563,6 +1725,14 @@ + }; + }; + ++ ge2d: ge2d@ff940000 { ++ compatible = "amlogic,axg-ge2d"; ++ reg = <0x0 0xff940000 0x0 0x10000>; ++ interrupts = ; ++ clocks = <&clkc CLKID_VAPB>; ++ resets = <&reset RESET_GE2D>; ++ }; ++ + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, +@@ -1701,6 +1871,7 @@ + status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; ++ fifo-size = <128>; + }; + }; + +@@ -1734,6 +1905,16 @@ + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; ++ ++ usb2_phy1: phy@9020 { ++ compatible = "amlogic,meson-gxl-usb2-phy"; ++ #phy-cells = <0>; ++ reg = <0x0 0x9020 0x0 0x20>; ++ clocks = <&clkc CLKID_USB>; ++ clock-names = "phy"; ++ resets = <&reset RESET_USB_OTG>; ++ reset-names = "phy"; ++ }; + }; + + sram: sram@fffc0000 { +diff -ruN u-boot-2021.10/arch/arm/dts/meson-axg-jethome-jethub-j100.dts u-boot/arch/arm/dts/meson-axg-jethome-jethub-j100.dts +--- u-boot-2021.10/arch/arm/dts/meson-axg-jethome-jethub-j100.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-axg-jethome-jethub-j100.dts 2021-11-01 17:10:13.626293972 +0100 +@@ -0,0 +1,361 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Vyacheslav Bocharov ++ * Copyright (c) 2020 JetHome ++ * Author: Aleksandr Kazantsev ++ * Author: Alexey Shevelkin ++ * Author: Vyacheslav Bocharov ++ */ ++ ++/dts-v1/; ++ ++#include "meson-axg.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg"; ++ model = "JetHome JetHub J100"; ++ aliases { ++ serial0 = &uart_AO; /* Console */ ++ serial1 = &uart_AO_B; /* External UART (Wireless Module) */ ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* 1024MB RAM */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ reserved-memory { ++ linux,cma { ++ size = <0x0 0x400000>; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_5v: regulator-vcc_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ vddio_ao18: regulator-vddio_ao18 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddio_boot: regulator-vddio_boot { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_BOOT"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ usb_pwr: regulator-usb_pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB_PWR"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v>; ++ regulator-always-on; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&scpi_sensors 0>; ++ trips { ++ cpu_passive: cpu-passive { ++ temperature = <70000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <80000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "hot"; ++ }; ++ ++ cpu_critical: cpu-critical { ++ temperature = <100000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cpu_cooling_maps: cooling-maps { ++ map0 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ onewire { ++ compatible = "w1-gpio"; ++ gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; ++ #gpio-cells = <1>; ++ }; ++}; ++ ++&efuse { ++ sn: sn@32 { ++ reg = <0x32 0x20>; ++ }; ++ ++ eth_mac: eth_mac@0 { ++ reg = <0x0 0x6>; ++ }; ++ ++ bt_mac: bt_mac@6 { ++ reg = <0x6 0x6>; ++ }; ++ ++ wifi_mac: wifi_mac@c { ++ reg = <0xc 0x6>; ++ }; ++ ++ bid: bid@12 { ++ reg = <0x12 0x20>; ++ }; ++}; ++ ++ðmac { ++ status = "okay"; ++ pinctrl-0 = <ð_rmii_x_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <ð_phy0>; ++ phy-mode = "rmii"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */ ++ eth_phy0: ethernet-phy@0 { ++ /* compatible = "ethernet-phy-id0243.0c54";*/ ++ max-speed = <100>; ++ reg = <0>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++/* Internal I2C bus (on CPU module) */ ++&i2c1 { ++ status = "okay"; ++ pinctrl-0 = <&i2c1_z_pins>; ++ pinctrl-names = "default"; ++ ++ /* RTC */ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "okay"; ++ }; ++}; ++ ++/* Peripheral I2C bus (on motherboard) */ ++&i2c_AO { ++ status = "okay"; ++ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_ab { ++ status = "okay"; ++ pinctrl-0 = <&pwm_a_x20_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* wifi module */ ++&sd_emmc_b { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* emmc storage */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* UART Bluetooth */ ++&uart_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/* UART Console */ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* UART Wireless module */ ++&uart_AO_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_b_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ phy-supply = <&usb_pwr>; ++}; ++ ++&spicc1 { ++ status = "okay"; ++ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ "", "", "", "", "", // 0 - 4 ++ "", "", "", "", "", // 5 - 9 ++ "UserButton", "", "", "", "", // 10 - 14 ++ "", "", "", "", "", // 15 - 19 ++ "", "", "", "", "", // 20 - 24 ++ "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29 ++ "Output1", "", "", "", "", // 30 - 34 ++ "", "ZigBeeBOOT", "", "", "", // 35 - 39 ++ "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44 ++ "Input2", "Input1", "", "", "", // 45 - 49 ++ "", "", "", "", "", // 50 - 54 ++ "", "", "", "", "", // 55 - 59 ++ "", "", "", "", "", // 60 - 64 ++ "", "", "", "", "", // 65 - 69 ++ "", "", "", "", "", // 70 - 74 ++ "", "", "", "", "", // 75 - 79 ++ "", "", "", "", "", // 80 - 84 ++ "", ""; // 85-86 ++}; ++ ++&cpu0 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu1 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu2 { ++ #cooling-cells = <2>; ++}; ++ ++&cpu3 { ++ #cooling-cells = <2>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-axg-s400.dts u-boot/arch/arm/dts/meson-axg-s400.dts +--- u-boot-2021.10/arch/arm/dts/meson-axg-s400.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-axg-s400.dts 2021-11-01 17:10:13.626293972 +0100 +@@ -441,6 +441,16 @@ + status = "okay"; + }; + ++&pcieA { ++ reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcieB { ++ reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ status = "okay"; ++}; ++ + &pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_x20_pins>; +@@ -584,3 +594,9 @@ + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; + }; ++ ++&usb { ++ status = "okay"; ++ dr_mode = "otg"; ++ vbus-supply = <&usb_pwr>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-axg-s400-u-boot.dtsi u-boot/arch/arm/dts/meson-axg-s400-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-axg-s400-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-axg-s400-u-boot.dtsi 2021-11-01 17:10:13.626293972 +0100 +@@ -3,8 +3,6 @@ + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +-#include "meson-axg-u-boot.dtsi" +- + /* wifi module */ + &sd_emmc_b { + status = "disabled"; +@@ -15,12 +13,6 @@ + status = "okay"; + }; + +-&usb { +- status = "okay"; +- dr_mode = "otg"; +- vbus-supply = <&usb_pwr>; +-}; +- + &usb2_phy1 { + phy-supply = <&vcc_5v>; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-axg-u-boot.dtsi u-boot/arch/arm/dts/meson-axg-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-axg-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-axg-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 +@@ -1,62 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Copyright (c) 2020 BayLibre, SAS. +- * Author: Neil Armstrong +- */ +- +-/ { +- soc { +- usb: usb@ffe09080 { +- compatible = "amlogic,meson-gxl-usb-ctrl"; +- reg = <0x0 0xffe09080 0x0 0x20>; +- interrupts = ; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; +- clock-names = "usb_ctrl", "ddr"; +- resets = <&reset RESET_USB_OTG>; +- +- dr_mode = "otg"; +- +- phys = <&usb2_phy1>; +- phy-names = "usb2-phy1"; +- +- dwc2: usb@ff400000 { +- compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; +- reg = <0x0 0xff400000 0x0 0x40000>; +- interrupts = ; +- clocks = <&clkc CLKID_USB1>; +- clock-names = "otg"; +- phys = <&usb2_phy1>; +- dr_mode = "peripheral"; +- g-rx-fifo-size = <192>; +- g-np-tx-fifo-size = <128>; +- g-tx-fifo-size = <128 128 16 16 16>; +- }; +- +- dwc3: usb@ff500000 { +- compatible = "snps,dwc3"; +- reg = <0x0 0xff500000 0x0 0x100000>; +- interrupts = ; +- dr_mode = "host"; +- maximum-speed = "high-speed"; +- snps,dis_u2_susphy_quirk; +- }; +- }; +- }; +-}; +- +-&apb { +- usb2_phy1: phy@9020 { +- compatible = "amlogic,meson-gxl-usb2-phy"; +- #phy-cells = <0>; +- reg = <0x0 0x9020 0x0 0x20>; +- clocks = <&clkc CLKID_USB>; +- clock-names = "phy"; +- resets = <&reset RESET_USB_OTG>; +- reset-names = "phy"; +- status = "okay"; +- }; +-}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12a-radxa-zero.dts u-boot/arch/arm/dts/meson-g12a-radxa-zero.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12a-radxa-zero.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-g12a-radxa-zero.dts 2021-11-01 17:10:13.626293972 +0100 +@@ -0,0 +1,405 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 BayLibre SAS. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "meson-g12a.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "radxa,zero", "amlogic,g12a"; ++ model = "Radxa Zero"; ++ ++ aliases { ++ serial0 = &uart_AO; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ cvbs-connector { ++ status = "disabled"; ++ compatible = "composite-video-connector"; ++ ++ port { ++ cvbs_connector_in: endpoint { ++ remote-endpoint = <&cvbs_vdac_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ ao_5v: regulator-ao_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "AO_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vcc_1v8: regulator-vcc_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ hdmi_pw: regulator-hdmi_pw { ++ compatible = "regulator-fixed"; ++ regulator-name = "HDMI_PW"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++ ++ vddao_1v8: regulator-vddao_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++ ++ vddcpu: regulator-vddcpu { ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU"; ++ regulator-min-microvolt = <721000>; ++ regulator-max-microvolt = <1022000>; ++ ++ vin-supply = <&ao_5v>; ++ ++ pwms = <&pwm_AO_cd 1 1250 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "RADXA-ZERO"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ ++ }; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&cec_AO { ++ pinctrl-0 = <&cec_ao_a_h_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&cecb_AO { ++ pinctrl-0 = <&cec_ao_b_h_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cvbs_vdac_port { ++ cvbs_vdac_out: endpoint { ++ remote-endpoint = <&cvbs_connector_in>; ++ }; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&hdmi_pw>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&ir { ++ status = "disabled"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_AO_cd { ++ pinctrl-0 = <&pwm_ao_d_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin1"; ++ status = "okay"; ++}; ++ ++&pwm_ef { ++ status = "okay"; ++ pinctrl-0 = <&pwm_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin0"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddao_1v8>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ status = "okay"; ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr50; ++ max-frequency = <100000000>; ++ ++ non-removable; ++ disable-wp; ++ ++ /* WiFi firmware requires power to be kept while in suspend */ ++ keep-power-in-suspend; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddao_1v8>; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_c_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_c_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <100000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddao_3v3>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ max-frequency = <200000000>; ++ disable-wp; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; ++ max-speed = <2000000>; ++ clocks = <&wifi32k>; ++ clock-names = "lpo"; ++ }; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ dr_mode = "host"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi u-boot/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi 2021-11-01 17:10:13.626293972 +0100 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS. ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-g12-common-u-boot.dtsi" +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12a-sei510.dts u-boot/arch/arm/dts/meson-g12a-sei510.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12a-sei510.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12a-sei510.dts 2021-11-01 17:10:13.626293972 +0100 +@@ -181,7 +181,7 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "G12A-SEI510"; ++ model = "SEI510"; + audio-aux-devs = <&tdmout_a>, <&tdmout_b>, + <&tdmin_a>, <&tdmin_b>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b.dtsi u-boot/arch/arm/dts/meson-g12b.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12b.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -135,3 +135,7 @@ + }; + }; + }; ++ ++&mali { ++ dma-coherent; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-gsking-x.dts u-boot/arch/arm/dts/meson-g12b-gsking-x.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12b-gsking-x.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-g12b-gsking-x.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -0,0 +1,133 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS ++ * Author: Neil Armstrong ++ * Copyright (c) 2019 Christian Hewitt ++ */ ++ ++/dts-v1/; ++ ++#include "meson-g12b-w400.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b"; ++ model = "Beelink GS-King X"; ++ ++ aliases { ++ rtc0 = &rtc; ++ rtc1 = &vrtc; ++ }; ++ ++ gpio-keys-polled { ++ compatible = "gpio-keys-polled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ poll-interval = <100>; ++ ++ power-button { ++ label = "power"; ++ linux,code = ; ++ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "GSKING-X"; ++ audio-aux-devs = <&tdmout_a>; ++ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_A IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_A IN 2", "FRDDR_C OUT 1", ++ "TDM_A Playback", "TDMOUT_A OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_a>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; ++ }; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; ++ pinctrl-names = "default"; ++ ++ rtc: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ wakeup-source; ++ }; ++}; ++ ++&tdmif_a { ++ status = "okay"; ++}; ++ ++&tdmout_a { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi u-boot/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS. ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-g12-common-u-boot.dtsi" +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-gtking.dts u-boot/arch/arm/dts/meson-g12b-gtking.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12b-gtking.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b-gtking.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -11,9 +11,14 @@ + #include + + / { +- compatible = "azw,gtking", "amlogic,g12b"; ++ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; + model = "Beelink GT-King"; + ++ aliases { ++ rtc0 = &rtc; ++ rtc1 = &vrtc; ++ }; ++ + spdif_dit: audio-codec-1 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; +@@ -23,7 +28,7 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "G12B-GTKING"; ++ model = "GTKING"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", +@@ -122,6 +127,19 @@ + status = "okay"; + }; + ++ ++&i2c3 { ++ status = "okay"; ++ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; ++ pinctrl-names = "default"; ++ ++ rtc: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ wakeup-source; ++ }; ++}; ++ + &spdifout { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-gtking-pro.dts u-boot/arch/arm/dts/meson-g12b-gtking-pro.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12b-gtking-pro.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b-gtking-pro.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -11,9 +11,14 @@ + #include + + / { +- compatible = "azw,gtking", "amlogic,g12b"; ++ compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; + model = "Beelink GT-King Pro"; + ++ aliases { ++ rtc0 = &rtc; ++ rtc1 = &vrtc; ++ }; ++ + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; +@@ -30,7 +35,7 @@ + leds { + compatible = "gpio-leds"; + +- white { ++ led-white { + label = "power:white"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state = "on"; +@@ -39,7 +44,7 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "G12B-GTKING-PRO"; ++ model = "GTKING-PRO"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", +@@ -112,6 +117,18 @@ + status = "okay"; + }; + ++&i2c3 { ++ status = "okay"; ++ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; ++ pinctrl-names = "default"; ++ ++ rtc: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ wakeup-source; ++ }; ++}; ++ + &tdmif_b { + status = "okay"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-odroid-n2.dtsi u-boot/arch/arm/dts/meson-g12b-odroid-n2.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12b-odroid-n2.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b-odroid-n2.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -13,6 +13,8 @@ + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; ++ rtc0 = &rtc; ++ rtc1 = &vrtc; + }; + + dioo2133: audio-amplifier-0 { +@@ -40,7 +42,7 @@ + leds { + compatible = "gpio-leds"; + +- blue { ++ led-blue { + label = "n2:blue"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; +@@ -211,7 +213,7 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "G12B-ODROID-N2"; ++ model = "ODROID-N2"; + audio-widgets = "Line", "Lineout"; + audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, + <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, +@@ -408,12 +410,12 @@ + + &ext_mdio { + external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ ++ /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; +- reset-deassert-us = <30000>; ++ reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; +@@ -444,13 +446,58 @@ + }; + + &gpio { ++ gpio-line-names = ++ /* GPIOZ */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ /* GPIOH */ ++ "", "", "", "", "", "", "", "", ++ "", ++ /* BOOT */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ /* GPIOC */ ++ "", "", "", "", "", "", "", "", ++ /* GPIOA */ ++ "PIN_44", /* GPIOA_0 */ ++ "PIN_46", /* GPIOA_1 */ ++ "PIN_45", /* GPIOA_2 */ ++ "PIN_47", /* GPIOA_3 */ ++ "PIN_26", /* GPIOA_4 */ ++ "", "", "", "", "", "", ++ "PIN_42", /* GPIOA_11 */ ++ "PIN_32", /* GPIOA_12 */ ++ "PIN_7", /* GPIOA_13 */ ++ "PIN_27", /* GPIOA_14 */ ++ "PIN_28", /* GPIOA_15 */ ++ /* GPIOX */ ++ "PIN_16", /* GPIOX_0 */ ++ "PIN_18", /* GPIOX_1 */ ++ "PIN_22", /* GPIOX_2 */ ++ "PIN_11", /* GPIOX_3 */ ++ "PIN_13", /* GPIOX_4 */ ++ "PIN_33", /* GPIOX_5 */ ++ "PIN_35", /* GPIOX_6 */ ++ "PIN_15", /* GPIOX_7 */ ++ "PIN_19", /* GPIOX_8 */ ++ "PIN_21", /* GPIOX_9 */ ++ "PIN_24", /* GPIOX_10 */ ++ "PIN_23", /* GPIOX_11 */ ++ "PIN_8", /* GPIOX_12 */ ++ "PIN_10", /* GPIOX_13 */ ++ "PIN_29", /* GPIOX_14 */ ++ "PIN_31", /* GPIOX_15 */ ++ "PIN_12", /* GPIOX_16 */ ++ "PIN_3", /* GPIOX_17 */ ++ "PIN_5", /* GPIOX_18 */ ++ "PIN_36"; /* GPIOX_19 */ + /* + * WARNING: The USB Hub on the Odroid-N2 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ +- usb-hub { ++ hog-0 { + gpio-hog; + gpios = ; + output-high; +@@ -478,6 +525,18 @@ + linux,rc-map-name = "rc-odroid"; + }; + ++&i2c3 { ++ status = "okay"; ++ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; ++ pinctrl-names = "default"; ++ ++ rtc: rtc@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ wakeup-source; ++ }; ++}; ++ + &pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; +@@ -494,6 +553,11 @@ + status = "okay"; + }; + ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddao_1v8>; ++}; ++ + /* SD card */ + &sd_emmc_b { + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-odroid-n2-plus.dts u-boot/arch/arm/dts/meson-g12b-odroid-n2-plus.dts +--- u-boot-2021.10/arch/arm/dts/meson-g12b-odroid-n2-plus.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b-odroid-n2-plus.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -19,7 +19,7 @@ + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + +- pwms = <&pwm_AO_cd 1 1500 0>; ++ pwms = <&pwm_ab 0 1500 0>; + }; + + &vddcpu_b { +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12b-w400.dtsi u-boot/arch/arm/dts/meson-g12b-w400.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12b-w400.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12b-w400.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -264,7 +264,7 @@ + max-speed = <1000>; + + reset-assert-us = <10000>; +- reset-deassert-us = <30000>; ++ reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12-common.dtsi u-boot/arch/arm/dts/meson-g12-common.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12-common.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12-common.dtsi 2021-11-01 17:10:13.626293972 +0100 +@@ -17,6 +17,12 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ mmc0 = &sd_emmc_b; /* SD card */ ++ mmc1 = &sd_emmc_c; /* eMMC */ ++ mmc2 = &sd_emmc_a; /* SDIO */ ++ }; ++ + chosen { + #address-cells = <2>; + #size-cells = <2>; +@@ -122,9 +128,9 @@ + + pcie: pcie@fc000000 { + compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; +- reg = <0x0 0xfc000000 0x0 0x400000 +- 0x0 0xff648000 0x0 0x2000 +- 0x0 0xfc400000 0x0 0x200000>; ++ reg = <0x0 0xfc000000 0x0 0x400000>, ++ <0x0 0xff648000 0x0 0x2000>, ++ <0x0 0xfc400000 0x0 0x200000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; +@@ -134,8 +140,8 @@ + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; +- ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 +- 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; ++ ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, ++ <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; + + clocks = <&clkc CLKID_PCIE_PHY + &clkc CLKID_PCIE_COMB +@@ -209,7 +215,7 @@ + }; + + ethmac: ethernet@ff3f0000 { +- compatible = "amlogic,meson-axg-dwmac", ++ compatible = "amlogic,meson-g12a-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000>, +@@ -282,6 +288,8 @@ + hwrng: rng@218 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x218 0x0 0x4>; ++ clocks = <&clkc CLKID_RNG0>; ++ clock-names = "core"; + }; + }; + +@@ -2001,7 +2009,7 @@ + }; + }; + +- vrtc: rtc@0a8 { ++ vrtc: rtc@a8 { + compatible = "amlogic,meson-vrtc"; + reg = <0x0 0x000a8 0x0 0x4>; + }; +@@ -2179,6 +2187,12 @@ + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; + ++ watchdog: watchdog@f0d0 { ++ compatible = "amlogic,meson-gxbb-wdt"; ++ reg = <0x0 0xf0d0 0x0 0x10>; ++ clocks = <&xtal>; ++ }; ++ + spicc0: spi@13000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x13000 0x0 0x44>; +@@ -2303,6 +2317,7 @@ + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; ++ fifo-size = <128>; + }; + }; + +@@ -2380,7 +2395,7 @@ + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; +- snps,quirk-frame-length-adjustment; ++ snps,quirk-frame-length-adjustment = <0x20>; + snps,parkmode-disable-ss-quirk; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-g12-common-u-boot.dtsi u-boot/arch/arm/dts/meson-g12-common-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-g12-common-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-g12-common-u-boot.dtsi 2021-11-01 17:10:13.626293972 +0100 +@@ -5,6 +5,13 @@ + */ + + / { ++ /* Keep HW order from U-boot */ ++ aliases { ++ /delete-property/ mmc0; ++ /delete-property/ mmc1; ++ /delete-property/ mmc2; ++ }; ++ + soc { + u-boot,dm-pre-reloc; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxbb-nanopi-k2.dts u-boot/arch/arm/dts/meson-gxbb-nanopi-k2.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxbb-nanopi-k2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxbb-nanopi-k2.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -7,6 +7,7 @@ + + #include "meson-gxbb.dtsi" + #include ++#include + + / { + compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; +@@ -130,6 +131,45 @@ + }; + }; + }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "NANOPI-K2"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; + }; + + &cec_AO { +@@ -165,7 +205,7 @@ + reg = <0>; + + reset-assert-us = <10000>; +- reset-deassert-us = <30000>; ++ reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxbb-odroidc2.dts u-boot/arch/arm/dts/meson-gxbb-odroidc2.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxbb-odroidc2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxbb-odroidc2.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -9,6 +9,7 @@ + + #include "meson-gxbb.dtsi" + #include ++#include + + / { + compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; +@@ -172,6 +173,45 @@ + }; + }; + }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "ODROID-C2"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; + }; + + &cec_AO { +@@ -200,7 +240,7 @@ + reg = <0>; + + reset-assert-us = <10000>; +- reset-deassert-us = <30000>; ++ reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; +@@ -217,7 +257,7 @@ + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ +- usb-hub { ++ hog-0 { + gpio-hog; + gpios = ; + output-high; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gx.dtsi u-boot/arch/arm/dts/meson-gx.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-gx.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gx.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -20,6 +20,12 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ aliases { ++ mmc0 = &sd_emmc_b; /* SD card */ ++ mmc1 = &sd_emmc_c; /* eMMC */ ++ mmc2 = &sd_emmc_a; /* SDIO */ ++ }; ++ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; +@@ -295,6 +301,7 @@ + reg = <0x0 0x84c0 0x0 0x18>; + interrupts = ; + status = "disabled"; ++ fifo-size = <128>; + }; + + uart_B: serial@84dc { +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gx-libretech-pc.dtsi u-boot/arch/arm/dts/meson-gx-libretech-pc.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-gx-libretech-pc.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gx-libretech-pc.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -186,7 +186,7 @@ + + sound { + compatible = "amlogic,gx-sound-card"; +- model = "GXL-LIBRETECH-S9XX-PC"; ++ model = "LIBRETECH-PC"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Speaker", "7J4-14 LEFT", + "Speaker", "7J4-11 RIGHT"; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts u-boot/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -118,7 +118,7 @@ + + sound { + compatible = "amlogic,gx-sound-card"; +- model = "GXL-LIBRETECH-S805X-AC"; ++ model = "LIBRETECH-AC"; + audio-widgets = "Speaker", "9J5-3 LEFT", + "Speaker", "9J5-2 RIGHT"; + audio-routing = "9J5-3 LEFT", "ACODEC LOLN", +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts u-boot/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -0,0 +1,241 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Vyacheslav Bocharov ++ * Copyright (c) 2020 JetHome ++ * Author: Aleksandr Kazantsev ++ * Author: Alexey Shevelkin ++ * Author: Vyacheslav Bocharov ++ */ ++ ++/dts-v1/; ++ ++#include "meson-gxl.dtsi" ++ ++/ { ++ compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl"; ++ model = "JetHome JetHub J80"; ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ reserved-memory { ++ linux,cma { ++ size = <0x0 0x1000000>; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart_AO; /* Console */ ++ serial1 = &uart_A; /* Bluetooth */ ++ serial2 = &uart_AO_B; /* Wireless module 1 */ ++ serial3 = &uart_C; /* Wireless module 2 */ ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ vddio_ao18: regulator-vddio_ao18 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ vddio_boot: regulator-vddio_boot { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_BOOT"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++}; ++ ++&efuse { ++ bt_mac: bt_mac@6 { ++ reg = <0x6 0x6>; ++ }; ++ ++ wifi_mac: wifi_mac@C { ++ reg = <0xc 0x6>; ++ }; ++}; ++ ++&sn { ++ reg = <0x32 0x20>; ++}; ++ ++ð_mac { ++ reg = <0x0 0x6>; ++}; ++ ++&bid { ++ reg = <0x12 0x20>; ++}; ++ ++&usb { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&pwm_ef { ++ status = "okay"; ++ pinctrl-0 = <&pwm_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&clkc CLKID_FCLK_DIV4>; ++ clock-names = "clkin0"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddio_ao18>; ++}; ++ ++/* Wireless SDIO Module */ ++&sd_emmc_a { ++ status = "okay"; ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <50000000>; ++ ++ non-removable; ++ disable-wp; ++ ++ /* WiFi firmware requires power to be kept while in suspend */ ++ keep-power-in-suspend; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <50000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vddio_boot>; ++}; ++ ++/* Console UART */ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/* S905W only has access to its internal PHY */ ++ðmac { ++ status = "okay"; ++ phy-mode = "rmii"; ++ phy-handle = <&internal_phy>; ++}; ++ ++&internal_phy { ++ status = "okay"; ++ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++}; ++ ++&uart_C { ++ status = "okay"; ++ pinctrl-0 = <&uart_c_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart_AO_B { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++}; ++ ++&i2c_B { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_b_pins>; ++ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "okay"; ++ }; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts u-boot/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -5,9 +5,9 @@ + + /dts-v1/; + +-#include +- + #include "meson-gxl-s905x-p212.dtsi" ++#include ++#include + + / { + compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; +@@ -42,10 +42,10 @@ + }; + }; + +- pwmleds { ++ led-controller { + compatible = "pwm-leds"; + +- power { ++ led-1 { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; +@@ -63,6 +63,45 @@ + }; + }; + }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "KHADAS-VIM"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; + }; + + &cec_AO { +@@ -97,8 +136,7 @@ + pinctrl-names = "default"; + + rtc: rtc@51 { +- /* has to be enabled manually when a battery is connected: */ +- status = "disabled"; ++ status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts u-boot/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -135,7 +135,7 @@ + + sound { + compatible = "amlogic,gx-sound-card"; +- model = "GXL-LIBRETECH-S905X-CC"; ++ model = "LIBRETECH-CC"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLN", +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts u-boot/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -84,7 +84,6 @@ + regulator-always-on; + }; + +- + vcck: regulator-vcck { + compatible = "regulator-fixed"; + regulator-name = "VCCK"; +@@ -124,7 +123,6 @@ + regulator-always-on; + }; + +- + vddio_card: regulator-vddio-card { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_CARD"; +@@ -161,7 +159,7 @@ + + sound { + compatible = "amlogic,gx-sound-card"; +- model = "GXL-LIBRETECH-S905X-CC-V2"; ++ model = "LIBRETECH-CC-V2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; +@@ -195,7 +193,6 @@ + }; + }; + +- + &aiu { + status = "okay"; + }; +@@ -207,7 +204,6 @@ + hdmi-phandle = <&hdmi_tx>; + }; + +- + ðmac { + status = "okay"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxm.dtsi u-boot/arch/arm/dts/meson-gxm.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-gxm.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxm.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -42,11 +42,28 @@ + }; + }; + ++ cpu0: cpu@0 { ++ capacity-dmips-mhz = <1024>; ++ }; ++ ++ cpu1: cpu@1 { ++ capacity-dmips-mhz = <1024>; ++ }; ++ ++ cpu2: cpu@2 { ++ capacity-dmips-mhz = <1024>; ++ }; ++ ++ cpu3: cpu@3 { ++ capacity-dmips-mhz = <1024>; ++ }; ++ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; + #cooling-cells = <2>; +@@ -57,6 +74,7 @@ + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; + #cooling-cells = <2>; +@@ -67,6 +85,7 @@ + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; + #cooling-cells = <2>; +@@ -77,6 +96,7 @@ + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; + #cooling-cells = <2>; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxm-khadas-vim2.dts u-boot/arch/arm/dts/meson-gxm-khadas-vim2.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxm-khadas-vim2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxm-khadas-vim2.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -7,9 +7,9 @@ + + /dts-v1/; + +-#include +- + #include "meson-gxm.dtsi" ++#include ++#include + + / { + compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; +@@ -81,10 +81,10 @@ + }; + }; + +- pwmleds { ++ led-controller { + compatible = "pwm-leds"; + +- power { ++ led-1 { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; +@@ -145,6 +145,45 @@ + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; ++ ++ sound { ++ compatible = "amlogic,gx-sound-card"; ++ model = "KHADAS-VIM2"; ++ assigned-clocks = <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>, ++ <&clkc CLKID_MPLL2>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; ++ }; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; ++ ++ codec-0 { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&aiu { ++ status = "okay"; + }; + + &cec_AO { +@@ -154,7 +193,6 @@ + hdmi-phandle = <&hdmi_tx>; + }; + +- + &cpu_cooling_maps { + map0 { + cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; +@@ -194,7 +232,7 @@ + reg = <0>; + + reset-assert-us = <10000>; +- reset-deassert-us = <30000>; ++ reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; +@@ -228,8 +266,7 @@ + pinctrl-names = "default"; + + rtc: rtc@51 { +- /* has to be enabled manually when a battery is connected: */ +- status = "disabled"; ++ status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; +@@ -341,7 +378,7 @@ + #size-cells = <1>; + compatible = "winbond,w25q16", "jedec,spi-nor"; + reg = <0>; +- spi-max-frequency = <3000000>; ++ spi-max-frequency = <104000000>; + }; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gxm-wetek-core2.dts u-boot/arch/arm/dts/meson-gxm-wetek-core2.dts +--- u-boot-2021.10/arch/arm/dts/meson-gxm-wetek-core2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gxm-wetek-core2.dts 2021-11-01 17:10:13.629627124 +0100 +@@ -22,7 +22,7 @@ + leds { + compatible = "gpio-leds"; + +- blue { ++ led-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gx-p23x-q20x.dtsi u-boot/arch/arm/dts/meson-gx-p23x-q20x.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-gx-p23x-q20x.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gx-p23x-q20x.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -121,7 +121,7 @@ + + sound { + compatible = "amlogic,gx-sound-card"; +- model = "GX-P230-Q200"; ++ model = "P230-Q200"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLP", +diff -ruN u-boot-2021.10/arch/arm/dts/meson-gx-u-boot.dtsi u-boot/arch/arm/dts/meson-gx-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-gx-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-gx-u-boot.dtsi 2021-11-01 17:10:13.629627124 +0100 +@@ -5,6 +5,13 @@ + */ + + / { ++ /* Keep HW order from U-boot */ ++ aliases { ++ /delete-property/ mmc0; ++ /delete-property/ mmc1; ++ /delete-property/ mmc2; ++ }; ++ + soc { + u-boot,dm-pre-reloc; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-khadas-vim3.dtsi u-boot/arch/arm/dts/meson-khadas-vim3.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-khadas-vim3.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-khadas-vim3.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -6,6 +6,7 @@ + */ + + #include ++#include + #include + #include + +@@ -13,6 +14,8 @@ + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; ++ rtc0 = &rtc; ++ rtc1 = &vrtc; + }; + + chosen { +@@ -41,13 +44,15 @@ + compatible = "gpio-leds"; + + led-white { +- label = "vim3:white:sys"; ++ color = ; ++ function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-red { +- label = "vim3:red"; ++ color = ; ++ function = LED_FUNCTION_STATUS; + gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; + }; + }; +@@ -165,12 +170,17 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "G12B-KHADAS-VIM3"; +- audio-aux-devs = <&tdmout_a>; ++ model = "KHADAS-VIM3"; ++ audio-aux-devs = <&tdmin_a>, <&tdmout_a>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", +- "TDM_A Playback", "TDMOUT_A OUT"; ++ "TDM_A Playback", "TDMOUT_A OUT", ++ "TDMIN_A IN 0", "TDM_A Capture", ++ "TDMIN_A IN 3", "TDM_A Loopback", ++ "TODDR_A IN 0", "TDMIN_A OUT", ++ "TODDR_B IN 0", "TDMIN_A OUT", ++ "TODDR_C IN 0", "TDMIN_A OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, +@@ -193,8 +203,20 @@ + sound-dai = <&frddr_c>; + }; + +- /* 8ch hdmi interface */ + dai-link-3 { ++ sound-dai = <&toddr_a>; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&toddr_b>; ++ }; ++ ++ dai-link-5 { ++ sound-dai = <&toddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-6 { + sound-dai = <&tdmif_a>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; +@@ -209,7 +231,7 @@ + }; + + /* hdmi glue */ +- dai-link-4 { ++ dai-link-7 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { +@@ -278,12 +300,12 @@ + }; + + ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii"; ++ phy-handle = <&external_phy>; ++ amlogic,tx-delay-ns = <2>; + }; + + &frddr_a { +@@ -330,7 +352,7 @@ + #gpio-cells = <2>; + }; + +- rtc@51 { ++ rtc: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; +@@ -349,9 +371,9 @@ + }; + + &pwm_ef { +- status = "okay"; +- pinctrl-0 = <&pwm_e_pins>; +- pinctrl-names = "default"; ++ status = "okay"; ++ pinctrl-0 = <&pwm_e_pins>; ++ pinctrl-names = "default"; + }; + + &saradc { +@@ -445,15 +467,30 @@ + }; + }; + +- + &tdmif_a { + status = "okay"; + }; + ++&tdmin_a { ++ status = "okay"; ++}; ++ + &tdmout_a { + status = "okay"; + }; + ++&toddr_a { ++ status = "okay"; ++}; ++ ++&toddr_b { ++ status = "okay"; ++}; ++ ++&toddr_c { ++ status = "okay"; ++}; ++ + &tohdmitx { + status = "okay"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-bananapi-m5.dts u-boot/arch/arm/dts/meson-sm1-bananapi-m5.dts +--- u-boot-2021.10/arch/arm/dts/meson-sm1-bananapi-m5.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-sm1-bananapi-m5.dts 2021-11-01 17:10:13.632960275 +0100 +@@ -0,0 +1,646 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 BayLibre SAS ++ * Author: Neil Armstrong ++ */ ++ ++/dts-v1/; ++ ++#include "meson-sm1.dtsi" ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "bananapi,bpi-m5", "amlogic,sm1"; ++ model = "Banana Pi BPI-M5"; ++ ++ adc_keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 2>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ ++ key { ++ label = "SW3"; ++ linux,code = ; ++ press-threshold-microvolt = <1700000>; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart_AO; ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* TOFIX: handle CVBS_DET on SARADC channel 0 */ ++ cvbs-connector { ++ compatible = "composite-video-connector"; ++ ++ port { ++ cvbs_connector_in: endpoint { ++ remote-endpoint = <&cvbs_vdac_out>; ++ }; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key { ++ label = "SW1"; ++ linux,code = ; ++ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; ++ interrupt-parent = <&gpio_intc>; ++ interrupts = <3 IRQ_TYPE_EDGE_BOTH>; ++ }; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ green { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ blue { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ emmc_1v8: regulator-emmc_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "EMMC_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ dc_in: regulator-dc_in { ++ compatible = "regulator-fixed"; ++ regulator-name = "DC_IN"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vddio_c: regulator-vddio_c { ++ compatible = "regulator-gpio"; ++ regulator-name = "VDDIO_C"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ ++ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; ++ gpios-states = <1>; ++ ++ states = <1800000 0>, ++ <3300000 1>; ++ }; ++ ++ tflash_vdd: regulator-tflash_vdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "TFLASH_VDD"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_in>; ++ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ vddao_1v8: regulator-vddao_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_in>; ++ regulator-always-on; ++ }; ++ ++ vddcpu: regulator-vddcpu { ++ /* ++ * SY8120B1ABC DC/DC Regulator. ++ */ ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU"; ++ regulator-min-microvolt = <690000>; ++ regulator-max-microvolt = <1050000>; ++ ++ vin-supply = <&dc_in>; ++ ++ pwms = <&pwm_AO_cd 1 1250 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* USB Hub Power Enable */ ++ vl_pwr_en: regulator-vl_pwr_en { ++ compatible = "regulator-fixed"; ++ regulator-name = "VL_PWR_EN"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_in>; ++ ++ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "BPI-M5"; ++ audio-widgets = "Line", "Lineout"; ++ audio-aux-devs = <&tdmout_b>, <&tdmout_c>, ++ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT", ++ "TDMOUT_C IN 0", "FRDDR_A OUT 2", ++ "TDMOUT_C IN 1", "FRDDR_B OUT 2", ++ "TDMOUT_C IN 2", "FRDDR_C OUT 2", ++ "TDM_C Playback", "TDMOUT_C OUT", ++ "TDMIN_A IN 4", "TDM_B Loopback", ++ "TDMIN_B IN 4", "TDM_B Loopback", ++ "TDMIN_C IN 4", "TDM_B Loopback", ++ "TDMIN_A IN 5", "TDM_C Loopback", ++ "TDMIN_B IN 5", "TDM_C Loopback", ++ "TDMIN_C IN 5", "TDM_C Loopback", ++ "TODDR_A IN 0", "TDMIN_A OUT", ++ "TODDR_B IN 0", "TDMIN_A OUT", ++ "TODDR_C IN 0", "TDMIN_A OUT", ++ "TODDR_A IN 1", "TDMIN_B OUT", ++ "TODDR_B IN 1", "TDMIN_B OUT", ++ "TODDR_C IN 1", "TDMIN_B OUT", ++ "TODDR_A IN 2", "TDMIN_C OUT", ++ "TODDR_B IN 2", "TDMIN_C OUT", ++ "TODDR_C IN 2", "TDMIN_C OUT", ++ "Lineout", "ACODEC LOLP", ++ "Lineout", "ACODEC LORP"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ dai-link-3 { ++ sound-dai = <&toddr_a>; ++ }; ++ ++ dai-link-4 { ++ sound-dai = <&toddr_b>; ++ }; ++ ++ dai-link-5 { ++ sound-dai = <&toddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-6 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ ++ codec-1 { ++ sound-dai = <&toacodec TOACODEC_IN_B>; ++ }; ++ }; ++ ++ /* i2s jack output interface */ ++ dai-link-7 { ++ sound-dai = <&tdmif_c>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec-0 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; ++ }; ++ ++ codec-1 { ++ sound-dai = <&toacodec TOACODEC_IN_C>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-8 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ ++ /* acodec glue */ ++ dai-link-9 { ++ sound-dai = <&toacodec TOACODEC_OUT>; ++ ++ codec { ++ sound-dai = <&acodec>; ++ }; ++ }; ++ }; ++}; ++ ++&acodec { ++ AVDD-supply = <&vddao_1v8>; ++ status = "okay"; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU1_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU2_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU3_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cvbs_vdac_port { ++ cvbs_vdac_out: endpoint { ++ remote-endpoint = <&cvbs_connector_in>; ++ }; ++}; ++ ++&ext_mdio { ++ external_phy: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ max-speed = <1000>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_14 */ ++ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++ðmac { ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-txid"; ++ phy-handle = <&external_phy>; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ /* GPIOZ */ ++ "ETH_MDIO", /* GPIOZ_0 */ ++ "ETH_MDC", /* GPIOZ_1 */ ++ "ETH_RXCLK", /* GPIOZ_2 */ ++ "ETH_RX_DV", /* GPIOZ_3 */ ++ "ETH_RXD0", /* GPIOZ_4 */ ++ "ETH_RXD1", /* GPIOZ_5 */ ++ "ETH_RXD2", /* GPIOZ_6 */ ++ "ETH_RXD3", /* GPIOZ_7 */ ++ "ETH_TXCLK", /* GPIOZ_8 */ ++ "ETH_TXEN", /* GPIOZ_9 */ ++ "ETH_TXD0", /* GPIOZ_10 */ ++ "ETH_TXD1", /* GPIOZ_11 */ ++ "ETH_TXD2", /* GPIOZ_12 */ ++ "ETH_TXD3", /* GPIOZ_13 */ ++ "ETH_INTR", /* GPIOZ_14 */ ++ "ETH_NRST", /* GPIOZ_15 */ ++ /* GPIOH */ ++ "HDMI_SDA", /* GPIOH_0 */ ++ "HDMI_SCL", /* GPIOH_1 */ ++ "HDMI_HPD", /* GPIOH_2 */ ++ "HDMI_CEC", /* GPIOH_3 */ ++ "VL-RST_N", /* GPIOH_4 */ ++ "CON1-P36", /* GPIOH_5 */ ++ "VL-PWREN", /* GPIOH_6 */ ++ "WiFi_3V3_1V8", /* GPIOH_7 */ ++ "TFLASH_VDD_EN", /* GPIOH_8 */ ++ /* BOOT */ ++ "eMMC_D0", /* BOOT_0 */ ++ "eMMC_D1", /* BOOT_1 */ ++ "eMMC_D2", /* BOOT_2 */ ++ "eMMC_D3", /* BOOT_3 */ ++ "eMMC_D4", /* BOOT_4 */ ++ "eMMC_D5", /* BOOT_5 */ ++ "eMMC_D6", /* BOOT_6 */ ++ "eMMC_D7", /* BOOT_7 */ ++ "eMMC_CLK", /* BOOT_8 */ ++ "", ++ "eMMC_CMD", /* BOOT_10 */ ++ "", ++ "eMMC_RST#", /* BOOT_12 */ ++ "eMMC_DS", /* BOOT_13 */ ++ /* GPIOC */ ++ "SD_D0_B", /* GPIOC_0 */ ++ "SD_D1_B", /* GPIOC_1 */ ++ "SD_D2_B", /* GPIOC_2 */ ++ "SD_D3_B", /* GPIOC_3 */ ++ "SD_CLK_B", /* GPIOC_4 */ ++ "SD_CMD_B", /* GPIOC_5 */ ++ "CARD_EN_DET", /* GPIOC_6 */ ++ "", ++ /* GPIOA */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", ++ "CON1-P27", /* GPIOA_14 */ ++ "CON1-P28", /* GPIOA_15 */ ++ /* GPIOX */ ++ "CON1-P16", /* GPIOX_0 */ ++ "CON1-P18", /* GPIOX_1 */ ++ "CON1-P22", /* GPIOX_2 */ ++ "CON1-P11", /* GPIOX_3 */ ++ "CON1-P13", /* GPIOX_4 */ ++ "CON1-P07", /* GPIOX_5 */ ++ "CON1-P33", /* GPIOX_6 */ ++ "CON1-P15", /* GPIOX_7 */ ++ "CON1-P19", /* GPIOX_8 */ ++ "CON1-P21", /* GPIOX_9 */ ++ "CON1-P24", /* GPIOX_10 */ ++ "CON1-P23", /* GPIOX_11 */ ++ "CON1-P08", /* GPIOX_12 */ ++ "CON1-P10", /* GPIOX_13 */ ++ "CON1-P29", /* GPIOX_14 */ ++ "CON1-P31", /* GPIOX_15 */ ++ "CON1-P26", /* GPIOX_16 */ ++ "CON1-P03", /* GPIOX_17 */ ++ "CON1-P05", /* GPIOX_18 */ ++ "CON1-P32"; /* GPIOX_19 */ ++ ++ /* ++ * WARNING: The USB Hub on the BPI-M5 needs a reset signal ++ * to be turned high in order to be detected by the USB Controller ++ * This signal should be handled by a USB specific power sequence ++ * in order to reset the Hub when USB bus is powered down. ++ */ ++ usb-hub { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "usb-hub-reset"; ++ }; ++}; ++ ++&gpio_ao { ++ gpio-line-names = ++ /* GPIOAO */ ++ "DEBUG TX", /* GPIOAO_0 */ ++ "DEBUG RX", /* GPIOAO_1 */ ++ "SYS_LED2", /* GPIOAO_2 */ ++ "UPDATE_KEY", /* GPIOAO_3 */ ++ "CON1-P40", /* GPIOAO_4 */ ++ "IR_IN", /* GPIOAO_5 */ ++ "TF_3V3N_1V8_EN", /* GPIOAO_6 */ ++ "CON1-P35", /* GPIOAO_7 */ ++ "CON1-P12", /* GPIOAO_8 */ ++ "CON1-P37", /* GPIOAO_9 */ ++ "CON1-P38", /* GPIOAO_10 */ ++ "SYS_LED", /* GPIOAO_11 */ ++ /* GPIOE */ ++ "VDDEE_PWM", /* GPIOE_0 */ ++ "VDDCPU_PWM", /* GPIOE_1 */ ++ "TF_PWR_EN"; /* GPIOE_2 */ ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&dc_in>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&ir { ++ status = "okay"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_AO_cd { ++ pinctrl-0 = <&pwm_ao_d_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin1"; ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddao_1v8>; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_c_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_c_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <50000000>; ++ disable-wp; ++ ++ /* TOFIX: SD card is barely usable in SDR modes */ ++ ++ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <&tflash_vdd>; ++ vqmmc-supply = <&vddio_c>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ max-frequency = <200000000>; ++ disable-wp; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&emmc_1v8>; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmif_c { ++ status = "okay"; ++}; ++ ++&tdmin_a { ++ status = "okay"; ++}; ++ ++&tdmin_b { ++ status = "okay"; ++}; ++ ++&tdmin_c { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tdmout_c { ++ status = "okay"; ++}; ++ ++&toacodec { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&toddr_a { ++ status = "okay"; ++}; ++ ++&toddr_b { ++ status = "okay"; ++}; ++ ++&toddr_c { ++ status = "okay"; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++}; ++ ++&usb2_phy0 { ++ phy-supply = <&dc_in>; ++}; ++ ++&usb2_phy1 { ++ /* Enable the hub which is connected to this port */ ++ phy-supply = <&vl_pwr_en>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi u-boot/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 BayLibre, SAS ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-sm1-u-boot.dtsi" ++ ++ðmac { ++ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ snps,reset-delays-us = <0 10000 1000000>; ++ snps,reset-active-low; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1.dtsi u-boot/arch/arm/dts/meson-sm1.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-sm1.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-sm1.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -130,7 +130,7 @@ + opp-microvolt = <790000>; + }; + +- opp-1512000000 { ++ opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <800000>; + }; +@@ -401,6 +401,16 @@ + status = "disabled"; + }; + ++ toacodec: audio-controller@740 { ++ compatible = "amlogic,sm1-toacodec", ++ "amlogic,g12a-toacodec"; ++ reg = <0x0 0x740 0x0 0x4>; ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "TOACODEC"; ++ resets = <&clkc_audio AUD_RESET_TOACODEC>; ++ status = "disabled"; ++ }; ++ + tohdmitx: audio-controller@744 { + compatible = "amlogic,sm1-tohdmitx", + "amlogic,g12a-tohdmitx"; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-khadas-vim3l.dts u-boot/arch/arm/dts/meson-sm1-khadas-vim3l.dts +--- u-boot-2021.10/arch/arm/dts/meson-sm1-khadas-vim3l.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-sm1-khadas-vim3l.dts 2021-11-01 17:10:13.632960275 +0100 +@@ -32,6 +32,19 @@ + regulator-boot-on; + regulator-always-on; + }; ++ ++ sound { ++ model = "G12B-KHADAS-VIM3L"; ++ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", ++ "TDMOUT_A IN 1", "FRDDR_B OUT 0", ++ "TDMOUT_A IN 2", "FRDDR_C OUT 0", ++ "TDM_A Playback", "TDMOUT_A OUT", ++ "TDMIN_A IN 0", "TDM_A Capture", ++ "TDMIN_A IN 13", "TDM_A Loopback", ++ "TODDR_A IN 0", "TDMIN_A OUT", ++ "TODDR_B IN 0", "TDMIN_A OUT", ++ "TODDR_C IN 0", "TDMIN_A OUT"; ++ }; + }; + + &cpu0 { +@@ -89,13 +102,12 @@ + status = "okay"; + }; + +-&sd_emmc_a { +- sd-uhs-sdr50; +-}; +- + &usb { + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; + }; + */ + ++&sd_emmc_a { ++ sd-uhs-sdr50; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-c4.dts u-boot/arch/arm/dts/meson-sm1-odroid-c4.dts +--- u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-c4.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-sm1-odroid-c4.dts 2021-11-01 17:10:13.632960275 +0100 +@@ -5,34 +5,12 @@ + + /dts-v1/; + +-#include "meson-sm1.dtsi" +-#include +-#include +-#include ++#include "meson-sm1-odroid.dtsi" + + / { + compatible = "hardkernel,odroid-c4", "amlogic,sm1"; + model = "Hardkernel ODROID-C4"; + +- aliases { +- serial0 = &uart_AO; +- ethernet0 = ðmac; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory@0 { +- device_type = "memory"; +- reg = <0x0 0x0 0x0 0x40000000>; +- }; +- +- emmc_pwrseq: emmc-pwrseq { +- compatible = "mmc-pwrseq-emmc"; +- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; +- }; +- + leds { + compatible = "gpio-leds"; + +@@ -45,324 +23,19 @@ + }; + }; + +- tflash_vdd: regulator-tflash_vdd { +- compatible = "regulator-fixed"; +- +- regulator-name = "TFLASH_VDD"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- +- gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- regulator-always-on; +- }; +- +- tf_io: gpio-regulator-tf_io { +- compatible = "regulator-gpio"; +- +- regulator-name = "TF_IO"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- +- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; +- gpios-states = <0>; +- +- states = <3300000 0>, +- <1800000 1>; +- }; +- +- flash_1v8: regulator-flash_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "FLASH_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- main_12v: regulator-main_12v { +- compatible = "regulator-fixed"; +- regulator-name = "12V"; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- regulator-always-on; +- }; +- +- vcc_5v: regulator-vcc_5v { +- compatible = "regulator-fixed"; +- regulator-name = "5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- regulator-always-on; +- vin-supply = <&main_12v>; +- }; +- +- vcc_1v8: regulator-vcc_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_3v3>; +- regulator-always-on; +- }; +- +- vcc_3v3: regulator-vcc_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VCC_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- /* FIXME: actually controlled by VDDCPU_B_EN */ +- }; +- +- vddcpu: regulator-vddcpu { +- /* +- * MP8756GD Regulator. +- */ +- compatible = "pwm-regulator"; +- +- regulator-name = "VDDCPU"; +- regulator-min-microvolt = <721000>; +- regulator-max-microvolt = <1022000>; +- +- vin-supply = <&main_12v>; +- +- pwms = <&pwm_AO_cd 1 1250 0>; +- pwm-dutycycle-range = <100 0>; +- +- regulator-boot-on; +- regulator-always-on; +- }; +- +- hub_5v: regulator-hub_5v { +- compatible = "regulator-fixed"; +- regulator-name = "HUB_5V"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to the Hub CHIPENABLE, LOW sets low power state */ +- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- usb_pwr_en: regulator-usb_pwr_en { +- compatible = "regulator-fixed"; +- regulator-name = "USB_PWR_EN"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc_5v>; +- +- /* Connected to the microUSB port power enable */ +- gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; +- enable-active-high; +- }; +- +- vddao_1v8: regulator-vddao_1v8 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_1V8"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vddao_3v3>; +- regulator-always-on; +- }; +- +- vddao_3v3: regulator-vddao_3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "VDDAO_3V3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <&main_12v>; +- regulator-always-on; +- }; +- +- hdmi-connector { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi_connector_in: endpoint { +- remote-endpoint = <&hdmi_tx_tmds_out>; +- }; +- }; +- }; +- + sound { +- compatible = "amlogic,axg-sound-card"; +- model = "SM1-ODROID-C4"; +- audio-aux-devs = <&tdmout_b>; +- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", +- "TDMOUT_B IN 1", "FRDDR_B OUT 1", +- "TDMOUT_B IN 2", "FRDDR_C OUT 1", +- "TDM_B Playback", "TDMOUT_B OUT"; +- +- assigned-clocks = <&clkc CLKID_MPLL2>, +- <&clkc CLKID_MPLL0>, +- <&clkc CLKID_MPLL1>; +- assigned-clock-parents = <0>, <0>, <0>; +- assigned-clock-rates = <294912000>, +- <270950400>, +- <393216000>; +- status = "okay"; +- +- dai-link-0 { +- sound-dai = <&frddr_a>; +- }; +- +- dai-link-1 { +- sound-dai = <&frddr_b>; +- }; +- +- dai-link-2 { +- sound-dai = <&frddr_c>; +- }; +- +- /* 8ch hdmi interface */ +- dai-link-3 { +- sound-dai = <&tdmif_b>; +- dai-format = "i2s"; +- dai-tdm-slot-tx-mask-0 = <1 1>; +- dai-tdm-slot-tx-mask-1 = <1 1>; +- dai-tdm-slot-tx-mask-2 = <1 1>; +- dai-tdm-slot-tx-mask-3 = <1 1>; +- mclk-fs = <256>; +- +- codec { +- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; +- }; +- }; +- +- /* hdmi glue */ +- dai-link-4 { +- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; +- +- codec { +- sound-dai = <&hdmi_tx>; +- }; +- }; +- }; +-}; +- +-&arb { +- status = "okay"; +-}; +- +-&clkc_audio { +- status = "okay"; +-}; +- +-&cpu0 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu1 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU1_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu2 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU2_CLK>; +- clock-latency = <50000>; +-}; +- +-&cpu3 { +- cpu-supply = <&vddcpu>; +- operating-points-v2 = <&cpu_opp_table>; +- clocks = <&clkc CLKID_CPU3_CLK>; +- clock-latency = <50000>; +-}; +- +-&ext_mdio { +- external_phy: ethernet-phy@0 { +- /* Realtek RTL8211F (0x001cc916) */ +- reg = <0>; +- max-speed = <1000>; +- +- interrupt-parent = <&gpio_intc>; +- /* MAC_INTR on GPIOZ_14 */ +- interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ model = "ODROID-C4"; + }; + }; + +-ðmac { +- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- phy-mode = "rgmii"; +- phy-handle = <&external_phy>; +- amlogic,tx-delay-ns = <2>; +-}; +- +-&frddr_a { +- status = "okay"; +-}; +- +-&frddr_b { +- status = "okay"; +-}; +- +-&frddr_c { +- status = "okay"; +-}; +- + &gpio { +- gpio-line-names = +- /* GPIOZ */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOH */ +- "", "", "", "", "", +- "PIN_36", /* GPIOH_5 */ +- "PIN_26", /* GPIOH_6 */ +- "PIN_32", /* GPIOH_7 */ +- "", +- /* BOOT */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", "", "", +- /* GPIOC */ +- "", "", "", "", "", "", "", "", +- /* GPIOA */ +- "", "", "", "", "", "", "", "", +- "", "", "", "", "", "", +- "PIN_27", /* GPIOA_14 */ +- "PIN_28", /* GPIOA_15 */ +- /* GPIOX */ +- "PIN_16", /* GPIOX_0 */ +- "PIN_18", /* GPIOX_1 */ +- "PIN_22", /* GPIOX_2 */ +- "PIN_11", /* GPIOX_3 */ +- "PIN_13", /* GPIOX_4 */ +- "PIN_7", /* GPIOX_5 */ +- "PIN_33", /* GPIOX_6 */ +- "PIN_15", /* GPIOX_7 */ +- "PIN_19", /* GPIOX_8 */ +- "PIN_21", /* GPIOX_9 */ +- "PIN_24", /* GPIOX_10 */ +- "PIN_23", /* GPIOX_11 */ +- "PIN_8", /* GPIOX_12 */ +- "PIN_10", /* GPIOX_13 */ +- "PIN_29", /* GPIOX_14 */ +- "PIN_31", /* GPIOX_15 */ +- "PIN_12", /* GPIOX_16 */ +- "PIN_3", /* GPIOX_17 */ +- "PIN_5", /* GPIOX_18 */ +- "PIN_35"; /* GPIOX_19 */ +- + /* + * WARNING: The USB Hub on the Odroid-C4 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ +- usb-hub { ++ hog-0 { + gpio-hog; + gpios = ; + output-high; +@@ -370,121 +43,6 @@ + }; + }; + +-&gpio_ao { +- gpio-line-names = +- /* GPIOAO */ +- "", "", "", "", +- "PIN_47", /* GPIOAO_4 */ +- "", "", +- "PIN_45", /* GPIOAO_7 */ +- "PIN_46", /* GPIOAO_8 */ +- "PIN_44", /* GPIOAO_9 */ +- "PIN_42", /* GPIOAO_10 */ +- "", +- /* GPIOE */ +- "", "", ""; +-}; +- +-&hdmi_tx { +- status = "okay"; +- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; +- pinctrl-names = "default"; +- hdmi-supply = <&vcc_5v>; +-}; +- +-&hdmi_tx_tmds_port { +- hdmi_tx_tmds_out: endpoint { +- remote-endpoint = <&hdmi_connector_in>; +- }; +-}; +- + &ir { +- status = "okay"; +- pinctrl-0 = <&remote_input_ao_pins>; +- pinctrl-names = "default"; + linux,rc-map-name = "rc-odroid"; + }; +- +-&pwm_AO_cd { +- pinctrl-0 = <&pwm_ao_d_e_pins>; +- pinctrl-names = "default"; +- clocks = <&xtal>; +- clock-names = "clkin1"; +- status = "okay"; +-}; +- +-&saradc { +- status = "okay"; +-}; +- +-/* SD card */ +-&sd_emmc_b { +- status = "okay"; +- pinctrl-0 = <&sdcard_c_pins>; +- pinctrl-1 = <&sdcard_clk_gate_c_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <4>; +- cap-sd-highspeed; +- max-frequency = <200000000>; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; +- sd-uhs-sdr104; +- disable-wp; +- +- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; +- vmmc-supply = <&tflash_vdd>; +- vqmmc-supply = <&tf_io>; +-}; +- +-/* eMMC */ +-&sd_emmc_c { +- status = "okay"; +- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; +- pinctrl-1 = <&emmc_clk_gate_pins>; +- pinctrl-names = "default", "clk-gate"; +- +- bus-width = <8>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- max-frequency = <200000000>; +- disable-wp; +- +- mmc-pwrseq = <&emmc_pwrseq>; +- vmmc-supply = <&vcc_3v3>; +- vqmmc-supply = <&flash_1v8>; +-}; +- +-&tdmif_b { +- status = "okay"; +-}; +- +-&tdmout_b { +- status = "okay"; +-}; +- +-&tohdmitx { +- status = "okay"; +-}; +- +-&uart_AO { +- status = "okay"; +- pinctrl-0 = <&uart_ao_a_pins>; +- pinctrl-names = "default"; +-}; +- +-&usb { +- status = "okay"; +- vbus-supply = <&usb_pwr_en>; +-}; +- +-&usb2_phy0 { +- phy-supply = <&vcc_5v>; +-}; +- +-&usb2_phy1 { +- /* Enable the hub which is connected to this port */ +- phy-supply = <&hub_5v>; +-}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-odroid.dtsi u-boot/arch/arm/dts/meson-sm1-odroid.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-sm1-odroid.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-sm1-odroid.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -0,0 +1,449 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Dongjin Kim ++ */ ++ ++#include "meson-sm1.dtsi" ++#include ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart_AO; ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ tflash_vdd: regulator-tflash_vdd { ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "TFLASH_VDD"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ tf_io: gpio-regulator-tf_io { ++ compatible = "regulator-gpio"; ++ ++ regulator-name = "TF_IO"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v>; ++ ++ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ ++ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; ++ gpios-states = <0>; ++ ++ states = <3300000 0>, ++ <1800000 1>; ++ }; ++ ++ flash_1v8: regulator-flash_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "FLASH_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_3v3>; ++ regulator-always-on; ++ }; ++ ++ main_12v: regulator-main_12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "12V"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-always-on; ++ }; ++ ++ vcc_5v: regulator-vcc_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <&main_12v>; ++ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; ++ enable-active-high; ++ }; ++ ++ vcc_1v8: regulator-vcc_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ /* FIXME: actually controlled by VDDCPU_B_EN */ ++ }; ++ ++ vddcpu: regulator-vddcpu { ++ /* ++ * MP8756GD Regulator. ++ */ ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU"; ++ regulator-min-microvolt = <721000>; ++ regulator-max-microvolt = <1022000>; ++ ++ vin-supply = <&main_12v>; ++ ++ pwms = <&pwm_AO_cd 1 1250 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ usb_pwr_en: regulator-usb_pwr_en { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB_PWR_EN"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v>; ++ ++ /* Connected to the microUSB port power enable */ ++ gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vddao_1v8: regulator-vddao_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&main_12v>; ++ regulator-always-on; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU1_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU2_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU3_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&ext_mdio { ++ external_phy: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ max-speed = <1000>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_14 */ ++ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++ðmac { ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii"; ++ phy-handle = <&external_phy>; ++ amlogic,tx-delay-ns = <2>; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ /* GPIOZ */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ /* GPIOH */ ++ "", "", "", "", "", ++ "PIN_36", /* GPIOH_5 */ ++ "PIN_26", /* GPIOH_6 */ ++ "PIN_32", /* GPIOH_7 */ ++ "", ++ /* BOOT */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", "", "", ++ /* GPIOC */ ++ "", "", "", "", "", "", "", "", ++ /* GPIOA */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "", "", ++ "PIN_27", /* GPIOA_14 */ ++ "PIN_28", /* GPIOA_15 */ ++ /* GPIOX */ ++ "PIN_16", /* GPIOX_0 */ ++ "PIN_18", /* GPIOX_1 */ ++ "PIN_22", /* GPIOX_2 */ ++ "PIN_11", /* GPIOX_3 */ ++ "PIN_13", /* GPIOX_4 */ ++ "PIN_7", /* GPIOX_5 */ ++ "PIN_33", /* GPIOX_6 */ ++ "PIN_15", /* GPIOX_7 */ ++ "PIN_19", /* GPIOX_8 */ ++ "PIN_21", /* GPIOX_9 */ ++ "PIN_24", /* GPIOX_10 */ ++ "PIN_23", /* GPIOX_11 */ ++ "PIN_8", /* GPIOX_12 */ ++ "PIN_10", /* GPIOX_13 */ ++ "PIN_29", /* GPIOX_14 */ ++ "PIN_31", /* GPIOX_15 */ ++ "PIN_12", /* GPIOX_16 */ ++ "PIN_3", /* GPIOX_17 */ ++ "PIN_5", /* GPIOX_18 */ ++ "PIN_35"; /* GPIOX_19 */ ++}; ++ ++&gpio_ao { ++ gpio-line-names = ++ /* GPIOAO */ ++ "", "", "", "", ++ "PIN_47", /* GPIOAO_4 */ ++ "", "", ++ "PIN_45", /* GPIOAO_7 */ ++ "PIN_46", /* GPIOAO_8 */ ++ "PIN_44", /* GPIOAO_9 */ ++ "PIN_42", /* GPIOAO_10 */ ++ "", ++ /* GPIOE */ ++ "", "", ""; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&vcc_5v>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&ir { ++ status = "okay"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_AO_cd { ++ pinctrl-0 = <&pwm_ao_d_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin1"; ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_c_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_c_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <200000000>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ disable-wp; ++ ++ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <&tflash_vdd>; ++ vqmmc-supply = <&tf_io>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ max-frequency = <200000000>; ++ disable-wp; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&flash_1v8>; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ vbus-supply = <&usb_pwr_en>; ++}; ++ ++&usb2_phy0 { ++ phy-supply = <&vcc_5v>; ++}; ++ +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-hc4.dts u-boot/arch/arm/dts/meson-sm1-odroid-hc4.dts +--- u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-hc4.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-sm1-odroid-hc4.dts 2021-11-01 17:10:13.632960275 +0100 +@@ -0,0 +1,140 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Dongjin Kim ++ */ ++ ++/dts-v1/; ++ ++#include "meson-sm1-odroid.dtsi" ++ ++/ { ++ compatible = "hardkernel,odroid-hc4", "amlogic,sm1"; ++ model = "Hardkernel ODROID-HC4"; ++ ++ aliases { ++ rtc0 = &rtc; ++ rtc1 = &vrtc; ++ }; ++ ++ fan0: pwm-fan { ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ cooling-levels = <0 120 170 220>; ++ pwms = <&pwm_cd 1 40000 0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-blue { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ panic-indicator; ++ }; ++ ++ led-red { ++ color = ; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ ++ p12v_0: regulator-p12v_0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "P12V_0"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&main_12v>; ++ ++ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ ++ p12v_1: regulator-p12v_1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "P12V_1"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&main_12v>; ++ ++ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ sound { ++ model = "ODROID-HC4"; ++ }; ++}; ++ ++&cpu_thermal { ++ cooling-maps { ++ map { ++ trip = <&cpu_passive>; ++ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&ir { ++ linux,rc-map-name = "rc-odroid"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; ++ pinctrl-names = "default"; ++ ++ rtc: rtc@51 { ++ status = "okay"; ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ wakeup-source; ++ }; ++}; ++ ++&pcie { ++ status = "okay"; ++ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; ++}; ++ ++&pwm_cd { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_d_x6_pins>; ++}; ++ ++&sd_emmc_c { ++ status = "disabled"; ++}; ++ ++&spifc { ++ status = "okay"; ++ pinctrl-0 = <&nor_pins>; ++ pinctrl-names = "default"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ }; ++}; ++ ++&usb { ++ phys = <&usb2_phy1>; ++ phy-names = "usb2-phy1"; ++}; ++ ++&usb2_phy0 { ++ status = "disabled"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi u-boot/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi 2021-11-01 17:10:13.632960275 +0100 +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 BayLibre, SAS ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-sm1-u-boot.dtsi" ++ ++ðmac { ++ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ snps,reset-delays-us = <0 10000 1000000>; ++ snps,reset-active-low; ++}; ++ ++/* SARADC is needed for proper board variant detection */ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddao_1v8>; ++}; ++ ++&tflash_vdd { ++ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/meson-sm1-sei610.dts u-boot/arch/arm/dts/meson-sm1-sei610.dts +--- u-boot-2021.10/arch/arm/dts/meson-sm1-sei610.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/meson-sm1-sei610.dts 2021-11-01 17:10:13.632960275 +0100 +@@ -101,20 +101,20 @@ + }; + }; + +- leds { ++ led-controller-1 { + compatible = "gpio-leds"; + +- led-bluetooth { ++ led-1 { + label = "sei610:blue:bt"; + gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + default-state = "off"; + }; + }; + +- pwmleds { ++ led-controller-2 { + compatible = "pwm-leds"; + +- power { ++ led-2 { + label = "sei610:red:power"; + pwms = <&pwm_AO_ab 0 30518 0>; + max-brightness = <255>; +@@ -220,7 +220,7 @@ + + sound { + compatible = "amlogic,axg-sound-card"; +- model = "SM1-SEI610"; ++ model = "SEI610"; + audio-aux-devs = <&tdmout_a>, <&tdmout_b>, + <&tdmin_a>, <&tdmin_b>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", +diff -ruN u-boot-2021.10/arch/arm/dts/sam9x60.dtsi u-boot/arch/arm/dts/sam9x60.dtsi +--- u-boot-2021.10/arch/arm/dts/sam9x60.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sam9x60.dtsi 2021-11-01 17:10:13.659625483 +0100 +@@ -50,6 +50,18 @@ + }; + }; + ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ARM9260_0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,arm926ej-s"; ++ clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>; ++ clock-names = "cpu", "master", "xtal"; ++ }; ++ }; ++ + ahb { + compatible = "simple-bus"; + #address-cells = <1>; +diff -ruN u-boot-2021.10/arch/arm/dts/sam9x60ek.dts u-boot/arch/arm/dts/sam9x60ek.dts +--- u-boot-2021.10/arch/arm/dts/sam9x60ek.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sam9x60ek.dts 2021-11-01 17:10:13.659625483 +0100 +@@ -7,6 +7,7 @@ + * Author: Sandeep Sheriker M + */ + /dts-v1/; ++#include + #include "sam9x60.dtsi" + + / { +@@ -57,7 +58,7 @@ + }; + + flx0: flexcom@f801c600 { +- atmel,flexcom-mode = <3>; ++ atmel,flexcom-mode = ; + status = "okay"; + + i2c@600 { +diff -ruN u-boot-2021.10/arch/arm/dts/sama5d2.dtsi u-boot/arch/arm/dts/sama5d2.dtsi +--- u-boot-2021.10/arch/arm/dts/sama5d2.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sama5d2.dtsi 2021-11-01 17:10:13.659625483 +0100 +@@ -32,7 +32,7 @@ + #size-cells = <1>; + u-boot,dm-pre-reloc; + +- usb1: ohci@00400000 { ++ usb1: ohci@400000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; +@@ -40,7 +40,7 @@ + status = "disabled"; + }; + +- usb2: ehci@00500000 { ++ usb2: ehci@500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + clocks = <&utmi>, <&uhphs_clk>; +diff -ruN u-boot-2021.10/arch/arm/dts/sama7g5ek.dts u-boot/arch/arm/dts/sama7g5ek.dts +--- u-boot-2021.10/arch/arm/dts/sama7g5ek.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sama7g5ek.dts 2021-11-01 17:10:13.659625483 +0100 +@@ -8,6 +8,7 @@ + * 2020, Claudiu Beznea + */ + /dts-v1/; ++#include + #include "sama7g5.dtsi" + #include "sama7g5-pinfunc.h" + +@@ -64,7 +65,7 @@ + }; + + &flx1 { +- atmel,flexcom-mode = <3>; ++ atmel,flexcom-mode = ; + status = "okay"; + }; + +diff -ruN u-boot-2021.10/arch/arm/dts/sama7g5-pinfunc.h u-boot/arch/arm/dts/sama7g5-pinfunc.h +--- u-boot-2021.10/arch/arm/dts/sama7g5-pinfunc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sama7g5-pinfunc.h 2021-11-01 17:10:13.659625483 +0100 +@@ -921,4 +921,3 @@ + #define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) + #define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) + #define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) +- +diff -ruN u-boot-2021.10/arch/arm/dts/ste-ab8500.dtsi u-boot/arch/arm/dts/ste-ab8500.dtsi +--- u-boot-2021.10/arch/arm/dts/ste-ab8500.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ste-ab8500.dtsi 2021-11-01 17:10:13.662958634 +0100 +@@ -42,15 +42,15 @@ + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH +- 18 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, ++ <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH +- 39 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, ++ <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + #address-cells = <1>; +@@ -122,9 +122,11 @@ + + ab8500_temp { + compatible = "stericsson,abx500-temp"; ++ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "ABX500_TEMP_WARM"; + io-channels = <&gpadc 0x06>, + <&gpadc 0x07>; +- io-channel-name = "aux1", "aux2"; ++ io-channel-names = "aux1", "aux2"; + }; + + ab8500_battery: ab8500_battery { +@@ -134,29 +136,77 @@ + + ab8500_fg { + compatible = "stericsson,ab8500-fg"; +- battery = <&ab8500_battery>; ++ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, ++ <8 IRQ_TYPE_LEVEL_HIGH>, ++ <28 IRQ_TYPE_LEVEL_HIGH>, ++ <27 IRQ_TYPE_LEVEL_HIGH>, ++ <26 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "NCONV_ACCU", ++ "BATT_OVV", ++ "LOW_BAT_F", ++ "CC_INT_CALIB", ++ "CCEOC"; ++ battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; +- io-channel-name = "main_bat_v"; ++ io-channel-names = "main_bat_v"; + }; + + ab8500_btemp { + compatible = "stericsson,ab8500-btemp"; +- battery = <&ab8500_battery>; ++ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, ++ <80 IRQ_TYPE_LEVEL_HIGH>, ++ <83 IRQ_TYPE_LEVEL_HIGH>, ++ <81 IRQ_TYPE_LEVEL_HIGH>, ++ <82 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "BAT_CTRL_INDB", ++ "BTEMP_LOW", ++ "BTEMP_HIGH", ++ "BTEMP_LOW_MEDIUM", ++ "BTEMP_MEDIUM_HIGH"; ++ battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; +- io-channel-name = "btemp_ball", ++ io-channel-names = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { +- compatible = "stericsson,ab8500-charger"; ++ compatible = "stericsson,ab8500-charger"; ++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, ++ <11 IRQ_TYPE_LEVEL_HIGH>, ++ <0 IRQ_TYPE_LEVEL_HIGH>, ++ <107 IRQ_TYPE_LEVEL_HIGH>, ++ <106 IRQ_TYPE_LEVEL_HIGH>, ++ <14 IRQ_TYPE_LEVEL_HIGH>, ++ <15 IRQ_TYPE_LEVEL_HIGH>, ++ <79 IRQ_TYPE_LEVEL_HIGH>, ++ <105 IRQ_TYPE_LEVEL_HIGH>, ++ <104 IRQ_TYPE_LEVEL_HIGH>, ++ <89 IRQ_TYPE_LEVEL_HIGH>, ++ <22 IRQ_TYPE_LEVEL_HIGH>, ++ <21 IRQ_TYPE_LEVEL_HIGH>, ++ <16 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "MAIN_CH_UNPLUG_DET", ++ "MAIN_CHARGE_PLUG_DET", ++ "MAIN_EXT_CH_NOT_OK", ++ "MAIN_CH_TH_PROT_R", ++ "MAIN_CH_TH_PROT_F", ++ "VBUS_DET_F", ++ "VBUS_DET_R", ++ "USB_LINK_STATUS", ++ "USB_CH_TH_PROT_R", ++ "USB_CH_TH_PROT_F", ++ "USB_CHARGER_NOT_OKR", ++ "VBUS_OVV", ++ "CH_WD_EXP", ++ "VBUS_CH_DROP_END"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + io-channels = <&gpadc 0x03>, + <&gpadc 0x0a>, + <&gpadc 0x09>, + <&gpadc 0x0b>; +- io-channel-name = "main_charger_v", ++ io-channel-names = "main_charger_v", + "main_charger_c", + "vbus_v", + "usb_charger_c"; +@@ -167,15 +217,15 @@ + battery = <&ab8500_battery>; + }; + +- ab8500_usb { ++ ab8500_usb: ab8500_usb { + compatible = "stericsson,ab8500-usb"; +- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH +- 96 IRQ_TYPE_LEVEL_HIGH +- 14 IRQ_TYPE_LEVEL_HIGH +- 15 IRQ_TYPE_LEVEL_HIGH +- 79 IRQ_TYPE_LEVEL_HIGH +- 74 IRQ_TYPE_LEVEL_HIGH +- 75 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, ++ <96 IRQ_TYPE_LEVEL_HIGH>, ++ <14 IRQ_TYPE_LEVEL_HIGH>, ++ <15 IRQ_TYPE_LEVEL_HIGH>, ++ <79 IRQ_TYPE_LEVEL_HIGH>, ++ <74 IRQ_TYPE_LEVEL_HIGH>, ++ <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", +@@ -188,12 +238,13 @@ + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; ++ #phy-cells = <0>; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH +- 7 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, ++ <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + +@@ -201,7 +252,19 @@ + compatible = "stericsson,ab8500-sysctrl"; + }; + +- ab8500-pwm { ++ ab8500-pwm-1 { ++ compatible = "stericsson,ab8500-pwm"; ++ clocks = <&ab8500_clock AB8500_SYSCLK_INT>; ++ clock-names = "intclk"; ++ }; ++ ++ ab8500-pwm-2 { ++ compatible = "stericsson,ab8500-pwm"; ++ clocks = <&ab8500_clock AB8500_SYSCLK_INT>; ++ clock-names = "intclk"; ++ }; ++ ++ ab8500-pwm-3 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; +@@ -255,8 +318,8 @@ + + // supplies to the display/camera + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { +- regulator-min-microvolt = <2500000>; +- regulator-max-microvolt = <2900000>; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <3300000>; + regulator-boot-on; + /* BUG: If turned off MMC will be affected. */ + regulator-always-on; +@@ -324,5 +387,10 @@ + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; ++ ++ usb_per5@a03e0000 { ++ phys = <&ab8500_usb>; ++ phy-names = "usb"; ++ }; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/ste-ab8505.dtsi u-boot/arch/arm/dts/ste-ab8505.dtsi +--- u-boot-2021.10/arch/arm/dts/ste-ab8505.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ste-ab8505.dtsi 2021-11-01 17:10:13.662958634 +0100 +@@ -13,7 +13,8 @@ + <&gpadc 0x08>, /* Main battery voltage */ + <&gpadc 0x09>, /* VBUS */ + <&gpadc 0x0b>, /* Charger current */ +- <&gpadc 0x0c>; /* Backup battery voltage */ ++ <&gpadc 0x0c>, /* Backup battery voltage */ ++ <&gpadc 0x0d>; /* Die temperature */ + }; + + soc { +@@ -38,16 +39,15 @@ + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; +- interrupts = <17 IRQ_TYPE_LEVEL_HIGH +- 18 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, ++ <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "60S", "ALARM"; + }; + + gpadc: ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; +- interrupts = <32 IRQ_TYPE_LEVEL_HIGH +- 39 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "HW_CONV_END", "SW_CONV_END"; ++ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_adc_reg>; + #address-cells = <1>; + #size-cells = <0>; +@@ -84,42 +84,93 @@ + bk_bat_v: channel@0c { + reg = <0x0c>; + }; ++ die_temp: channel@0d { ++ reg = <0x0d>; ++ }; + usb_id: channel@0e { + reg = <0x0e>; + }; + }; + + ab8500_battery: ab8500_battery { +- status = "disabled"; ++ stericsson,battery-type = "LIPO"; + thermistor-on-batctrl; + }; + + ab8500_fg { + status = "disabled"; + compatible = "stericsson,ab8500-fg"; ++ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, ++ <8 IRQ_TYPE_LEVEL_HIGH>, ++ <28 IRQ_TYPE_LEVEL_HIGH>, ++ <27 IRQ_TYPE_LEVEL_HIGH>, ++ <26 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "NCONV_ACCU", ++ "BATT_OVV", ++ "LOW_BAT_F", ++ "CC_INT_CALIB", ++ "CCEOC"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x08>; +- io-channel-name = "main_bat_v"; ++ io-channel-names = "main_bat_v"; + }; + + ab8500_btemp { + status = "disabled"; + compatible = "stericsson,ab8500-btemp"; ++ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, ++ <80 IRQ_TYPE_LEVEL_HIGH>, ++ <83 IRQ_TYPE_LEVEL_HIGH>, ++ <81 IRQ_TYPE_LEVEL_HIGH>, ++ <82 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "BAT_CTRL_INDB", ++ "BTEMP_LOW", ++ "BTEMP_HIGH", ++ "BTEMP_LOW_MEDIUM", ++ "BTEMP_MEDIUM_HIGH"; + battery = <&ab8500_battery>; + io-channels = <&gpadc 0x02>, + <&gpadc 0x01>; +- io-channel-name = "btemp_ball", ++ io-channel-names = "btemp_ball", + "bat_ctrl"; + }; + + ab8500_charger { + status = "disabled"; + compatible = "stericsson,ab8500-charger"; ++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, ++ <11 IRQ_TYPE_LEVEL_HIGH>, ++ <0 IRQ_TYPE_LEVEL_HIGH>, ++ <107 IRQ_TYPE_LEVEL_HIGH>, ++ <106 IRQ_TYPE_LEVEL_HIGH>, ++ <14 IRQ_TYPE_LEVEL_HIGH>, ++ <15 IRQ_TYPE_LEVEL_HIGH>, ++ <79 IRQ_TYPE_LEVEL_HIGH>, ++ <105 IRQ_TYPE_LEVEL_HIGH>, ++ <104 IRQ_TYPE_LEVEL_HIGH>, ++ <89 IRQ_TYPE_LEVEL_HIGH>, ++ <22 IRQ_TYPE_LEVEL_HIGH>, ++ <21 IRQ_TYPE_LEVEL_HIGH>, ++ <16 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "MAIN_CH_UNPLUG_DET", ++ "MAIN_CHARGE_PLUG_DET", ++ "MAIN_EXT_CH_NOT_OK", ++ "MAIN_CH_TH_PROT_R", ++ "MAIN_CH_TH_PROT_F", ++ "VBUS_DET_F", ++ "VBUS_DET_R", ++ "USB_LINK_STATUS", ++ "USB_CH_TH_PROT_R", ++ "USB_CH_TH_PROT_F", ++ "USB_CHARGER_NOT_OKR", ++ "VBUS_OVV", ++ "CH_WD_EXP", ++ "VBUS_CH_DROP_END"; + battery = <&ab8500_battery>; + vddadc-supply = <&ab8500_ldo_adc_reg>; + io-channels = <&gpadc 0x09>, + <&gpadc 0x0b>; +- io-channel-name = "vbus_v", ++ io-channel-names = "vbus_v", + "usb_charger_c"; + }; + +@@ -131,13 +182,13 @@ + + ab8500_usb: ab8500_usb { + compatible = "stericsson,ab8500-usb"; +- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH +- 96 IRQ_TYPE_LEVEL_HIGH +- 14 IRQ_TYPE_LEVEL_HIGH +- 15 IRQ_TYPE_LEVEL_HIGH +- 79 IRQ_TYPE_LEVEL_HIGH +- 74 IRQ_TYPE_LEVEL_HIGH +- 75 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, ++ <96 IRQ_TYPE_LEVEL_HIGH>, ++ <14 IRQ_TYPE_LEVEL_HIGH>, ++ <15 IRQ_TYPE_LEVEL_HIGH>, ++ <79 IRQ_TYPE_LEVEL_HIGH>, ++ <74 IRQ_TYPE_LEVEL_HIGH>, ++ <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", +@@ -150,12 +201,13 @@ + musb_1v8-supply = <&db8500_vsmps2_reg>; + clocks = <&prcmu_clk PRCMU_SYSCLK>; + clock-names = "sysclk"; ++ #phy-cells = <0>; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-poweron-key"; +- interrupts = <6 IRQ_TYPE_LEVEL_HIGH +- 7 IRQ_TYPE_LEVEL_HIGH>; ++ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, ++ <7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + +@@ -271,5 +323,10 @@ + vana-supply = <&ab8500_ldo_ana_reg>; + }; + }; ++ ++ usb_per5@a03e0000 { ++ phys = <&ab8500_usb>; ++ phy-names = "usb"; ++ }; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/ste-dbx5x0.dtsi u-boot/arch/arm/dts/ste-dbx5x0.dtsi +--- u-boot-2021.10/arch/arm/dts/ste-dbx5x0.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ste-dbx5x0.dtsi 2021-11-01 17:10:13.662958634 +0100 +@@ -260,7 +260,7 @@ + reg = <0x80150000 0x2000>; + }; + +- L2: l2-cache { ++ L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = ; +@@ -883,7 +883,7 @@ + status = "disabled"; + }; + +- sdi0_per1@80126000 { ++ mmc@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = ; +@@ -899,7 +899,7 @@ + status = "disabled"; + }; + +- sdi1_per2@80118000 { ++ mmc@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = ; +@@ -915,7 +915,7 @@ + status = "disabled"; + }; + +- sdi2_per3@80005000 { ++ mmc@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = ; +@@ -931,7 +931,7 @@ + status = "disabled"; + }; + +- sdi3_per2@80119000 { ++ mmc@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = ; +@@ -947,7 +947,7 @@ + status = "disabled"; + }; + +- sdi4_per2@80114000 { ++ mmc@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = ; +@@ -963,7 +963,7 @@ + status = "disabled"; + }; + +- sdi5_per3@80008000 { ++ mmc@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80008000 0x1000>; + interrupts = ; +diff -ruN u-boot-2021.10/arch/arm/dts/ste-dbx5x0-u-boot.dtsi u-boot/arch/arm/dts/ste-dbx5x0-u-boot.dtsi +--- u-boot-2021.10/arch/arm/dts/ste-dbx5x0-u-boot.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ste-dbx5x0-u-boot.dtsi 2021-11-01 17:10:13.662958634 +0100 +@@ -4,8 +4,14 @@ + #include "ste-dbx5x0.dtsi" + + / { ++ /* FIXME: Remove this when clk driver is implemented */ ++ sdmmcclk: sdmmcclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ }; ++ + soc { +- /* FIXME: Remove this when clk driver is implemented */ + mtu@a03c6000 { + clock-frequency = <133000000>; + }; +@@ -18,6 +24,9 @@ + uart@80007000 { + clock = <38400000>; + }; ++ mmc@80005000 { ++ clocks = <&sdmmcclk>; ++ }; + }; + + reboot { +diff -ruN u-boot-2021.10/arch/arm/dts/ste-ux500-samsung-stemmy.dts u-boot/arch/arm/dts/ste-ux500-samsung-stemmy.dts +--- u-boot-2021.10/arch/arm/dts/ste-ux500-samsung-stemmy.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/ste-ux500-samsung-stemmy.dts 2021-11-01 17:10:13.662958634 +0100 +@@ -12,9 +12,25 @@ + }; + + soc { ++ /* eMMC */ ++ mmc@80005000 { ++ status = "okay"; ++ ++ arm,primecell-periphid = <0x10480180>; ++ max-frequency = <100000000>; ++ bus-width = <8>; ++ ++ non-removable; ++ cap-mmc-highspeed; ++ }; ++ + /* Debugging console UART */ + uart@80007000 { + status = "okay"; + }; ++ ++ mcde@a0350000 { ++ status = "okay"; ++ }; + }; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts u-boot/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -167,8 +167,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts u-boot/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -225,8 +225,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-inet1.dts u-boot/arch/arm/dts/sun4i-a10-inet1.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-inet1.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-inet1.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -235,8 +235,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-inet97fv2.dts u-boot/arch/arm/dts/sun4i-a10-inet97fv2.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-inet97fv2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-inet97fv2.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -211,8 +211,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-inet9f-rev03.dts u-boot/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-inet9f-rev03.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-inet9f-rev03.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -379,8 +379,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts u-boot/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts +--- u-boot-2021.10/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts 2021-11-01 17:10:13.669624936 +0100 +@@ -213,8 +213,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ +- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun50i-h616.dtsi u-boot/arch/arm/dts/sun50i-h616.dtsi +--- u-boot-2021.10/arch/arm/dts/sun50i-h616.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun50i-h616.dtsi 2021-11-01 17:10:13.672958087 +0100 +@@ -122,7 +122,6 @@ + reg = <0x030090a0 0x20>; + interrupts = ; + clocks = <&osc24M>; +- status = "disabled"; + }; + + pio: pinctrl@300b000 { +diff -ruN u-boot-2021.10/arch/arm/dts/sun50i-h6-pine-h64.dts u-boot/arch/arm/dts/sun50i-h6-pine-h64.dts +--- u-boot-2021.10/arch/arm/dts/sun50i-h6-pine-h64.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun50i-h6-pine-h64.dts 2021-11-01 17:10:13.672958087 +0100 +@@ -89,6 +89,10 @@ + status = "okay"; + }; + ++&dwc3 { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +@@ -332,3 +336,7 @@ + usb3_vbus-supply = <®_usb_vbus>; + status = "okay"; + }; ++ ++&usb3phy { ++ status = "okay"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts u-boot/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts +--- u-boot-2021.10/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts 2021-11-01 17:10:13.672958087 +0100 +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2019 Corentin LABBE ++ */ ++ ++#include "sun50i-h6-pine-h64.dts" ++ ++/ { ++ model = "Pine H64 model B"; ++ compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; ++ ++ /delete-node/ reg_gmac_3v3; ++}; ++ ++&hdmi_connector { ++ /delete-property/ ddc-en-gpios; ++}; ++ ++&emac { ++ phy-supply = <®_aldo2>; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/sun5i-a13-ampe-a76.dts u-boot/arch/arm/dts/sun5i-a13-ampe-a76.dts +--- u-boot-2021.10/arch/arm/dts/sun5i-a13-ampe-a76.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun5i-a13-ampe-a76.dts 2021-11-01 17:10:13.672958087 +0100 +@@ -26,3 +26,7 @@ + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; + }; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts u-boot/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts +--- u-boot-2021.10/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts 2021-11-01 17:10:13.672958087 +0100 +@@ -209,8 +209,8 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; +- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ +- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ ++ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ ++ usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun6i-a31-mixtile-loftq.dts u-boot/arch/arm/dts/sun6i-a31-mixtile-loftq.dts +--- u-boot-2021.10/arch/arm/dts/sun6i-a31-mixtile-loftq.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun6i-a31-mixtile-loftq.dts 2021-11-01 17:10:13.676291238 +0100 +@@ -6,6 +6,9 @@ + */ + + /dts-v1/; ++ ++#include ++ + #include "sun6i-a31.dtsi" + + / { +@@ -19,6 +22,15 @@ + chosen { + stdout-path = "serial0:115200n8"; + }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ ++ }; + }; + + &ehci0 { +@@ -54,3 +66,8 @@ + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts u-boot/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +--- u-boot-2021.10/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts 2021-11-01 17:10:13.676291238 +0100 +@@ -194,6 +194,7 @@ + }; + + &usbphy { ++ usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb1_vbus-supply = <®_dldo1>; + usb2_vbus-supply = <®_dc1sw>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun7i-a20-wexler-tab7200.dts u-boot/arch/arm/dts/sun7i-a20-wexler-tab7200.dts +--- u-boot-2021.10/arch/arm/dts/sun7i-a20-wexler-tab7200.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun7i-a20-wexler-tab7200.dts 2021-11-01 17:10:13.676291238 +0100 +@@ -225,7 +225,7 @@ + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; +- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; +diff -ruN u-boot-2021.10/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts u-boot/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts +--- u-boot-2021.10/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts 2021-11-01 17:10:13.679624389 +0100 +@@ -289,5 +289,6 @@ + + &usbphy { + status = "okay"; ++ usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ + }; +diff -ruN u-boot-2021.10/arch/arm/dts/sun8i-a83t-bananapi-m3.dts u-boot/arch/arm/dts/sun8i-a83t-bananapi-m3.dts +--- u-boot-2021.10/arch/arm/dts/sun8i-a83t-bananapi-m3.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun8i-a83t-bananapi-m3.dts 2021-11-01 17:10:13.679624389 +0100 +@@ -355,6 +355,9 @@ + }; + + &usbphy { ++ usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; ++ usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; +diff -ruN u-boot-2021.10/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts u-boot/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +--- u-boot-2021.10/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts 2021-11-01 17:10:13.679624389 +0100 +@@ -391,6 +391,9 @@ + }; + + &usbphy { ++ usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; ++ usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +diff -ruN u-boot-2021.10/arch/arm/dts/sun8i-a83t-tbs-a711.dts u-boot/arch/arm/dts/sun8i-a83t-tbs-a711.dts +--- u-boot-2021.10/arch/arm/dts/sun8i-a83t-tbs-a711.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun8i-a83t-tbs-a711.dts 2021-11-01 17:10:13.679624389 +0100 +@@ -416,6 +416,7 @@ + + &usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus_supply = <®_vmain>; + usb2_vbus_supply = <®_vmain>; +diff -ruN u-boot-2021.10/arch/arm/dts/sun9i-a80-cubieboard4.dts u-boot/arch/arm/dts/sun9i-a80-cubieboard4.dts +--- u-boot-2021.10/arch/arm/dts/sun9i-a80-cubieboard4.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/sun9i-a80-cubieboard4.dts 2021-11-01 17:10:13.682957540 +0100 +@@ -475,3 +475,7 @@ + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; + }; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/vexpress-v2m.dtsi u-boot/arch/arm/dts/vexpress-v2m.dtsi +--- u-boot-2021.10/arch/arm/dts/vexpress-v2m.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/vexpress-v2m.dtsi 2021-11-01 17:10:13.689623842 +0100 +@@ -0,0 +1,427 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * ARM Ltd. Versatile Express ++ * ++ * Motherboard Express uATX ++ * V2M-P1 ++ * ++ * HBI-0190D ++ * ++ * Original memory map ("Legacy memory map" in the board's ++ * Technical Reference Manual) ++ * ++ * WARNING! The hardware described in this file is independent from the ++ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong ++ * correspondence between the two configurations. ++ * ++ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT ++ * CHANGES TO vexpress-v2m-rs1.dtsi! ++ */ ++ ++/ { ++ smb@4000000 { ++ motherboard { ++ model = "V2M-P1"; ++ arm,hbi = <0x190>; ++ arm,vexpress,site = <0>; ++ compatible = "arm,vexpress,v2m-p1", "simple-bus"; ++ #address-cells = <2>; /* SMB chipselect number and offset */ ++ #size-cells = <1>; ++ #interrupt-cells = <1>; ++ ranges; ++ ++ flash@0,00000000 { ++ compatible = "arm,vexpress-flash", "cfi-flash"; ++ reg = <0 0x00000000 0x04000000>, ++ <1 0x00000000 0x04000000>; ++ bank-width = <4>; ++ }; ++ ++ psram@2,00000000 { ++ compatible = "arm,vexpress-psram", "mtd-ram"; ++ reg = <2 0x00000000 0x02000000>; ++ bank-width = <4>; ++ }; ++ ++ ethernet@3,02000000 { ++ compatible = "smsc,lan9118", "smsc,lan9115"; ++ reg = <3 0x02000000 0x10000>; ++ interrupts = <15>; ++ phy-mode = "mii"; ++ reg-io-width = <4>; ++ smsc,irq-active-high; ++ smsc,irq-push-pull; ++ vdd33a-supply = <&v2m_fixed_3v3>; ++ vddvario-supply = <&v2m_fixed_3v3>; ++ }; ++ ++ usb@3,03000000 { ++ compatible = "nxp,usb-isp1761"; ++ reg = <3 0x03000000 0x20000>; ++ interrupts = <16>; ++ port1-otg; ++ }; ++ ++ iofpga@7,00000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 7 0 0x20000>; ++ ++ v2m_sysreg: sysreg@0 { ++ compatible = "arm,vexpress-sysreg"; ++ reg = <0x00000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0x1000>; ++ ++ v2m_led_gpios: gpio@8 { ++ compatible = "arm,vexpress-sysreg,sys_led"; ++ reg = <0x008 4>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ v2m_mmc_gpios: gpio@48 { ++ compatible = "arm,vexpress-sysreg,sys_mci"; ++ reg = <0x048 4>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ v2m_flash_gpios: gpio@4c { ++ compatible = "arm,vexpress-sysreg,sys_flash"; ++ reg = <0x04c 4>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ }; ++ ++ v2m_sysctl: sysctl@1000 { ++ compatible = "arm,sp810", "arm,primecell"; ++ reg = <0x01000 0x1000>; ++ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; ++ clock-names = "refclk", "timclk", "apb_pclk"; ++ #clock-cells = <1>; ++ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; ++ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; ++ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; ++ }; ++ ++ /* PCI-E I2C bus */ ++ v2m_i2c_pcie: i2c@2000 { ++ compatible = "arm,versatile-i2c"; ++ reg = <0x02000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcie-switch@60 { ++ compatible = "idt,89hpes32h8"; ++ reg = <0x60>; ++ }; ++ }; ++ ++ aaci@4000 { ++ compatible = "arm,pl041", "arm,primecell"; ++ reg = <0x04000 0x1000>; ++ interrupts = <11>; ++ clocks = <&smbclk>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ mmc0: mmci@5000 { ++ compatible = "arm,pl180", "arm,primecell"; ++ reg = <0x05000 0x1000>; ++ interrupts = <9>, <10>; ++ cd-gpios = <&v2m_mmc_gpios 0 0>; ++ wp-gpios = <&v2m_mmc_gpios 1 0>; ++ max-frequency = <12000000>; ++ vmmc-supply = <&v2m_fixed_3v3>; ++ clocks = <&v2m_clk24mhz>, <&smbclk>; ++ clock-names = "mclk", "apb_pclk"; ++ }; ++ ++ v2m_serial0: uart@9000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x09000 0x1000>; ++ interrupts = <5>; ++ clocks = <&v2m_oscclk2>, <&smbclk>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ v2m_serial1: uart@a000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x0a000 0x1000>; ++ interrupts = <6>; ++ clocks = <&v2m_oscclk2>, <&smbclk>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ v2m_serial2: uart@b000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x0b000 0x1000>; ++ interrupts = <7>; ++ clocks = <&v2m_oscclk2>, <&smbclk>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ v2m_serial3: uart@c000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x0c000 0x1000>; ++ interrupts = <8>; ++ clocks = <&v2m_oscclk2>, <&smbclk>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ v2m_timer01: timer@11000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x11000 0x1000>; ++ interrupts = <2>; ++ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; ++ clock-names = "timclken1", "timclken2", "apb_pclk"; ++ }; ++ ++ v2m_timer23: timer@12000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x12000 0x1000>; ++ interrupts = <3>; ++ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; ++ clock-names = "timclken1", "timclken2", "apb_pclk"; ++ }; ++ ++ /* DVI I2C bus */ ++ v2m_i2c_dvi: i2c@16000 { ++ compatible = "arm,versatile-i2c"; ++ reg = <0x16000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dvi-transmitter@39 { ++ compatible = "sil,sii9022-tpi", "sil,sii9022"; ++ reg = <0x39>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* ++ * Both the core tile and the motherboard routes their output ++ * pads to this transmitter. The motherboard system controller ++ * can select one of them as input using a mux register in ++ * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is ++ * the only platform with this specific set-up. ++ */ ++ port@0 { ++ reg = <0>; ++ dvi_bridge_in_ct: endpoint { ++ remote-endpoint = <&clcd_pads_ct>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ dvi_bridge_in_mb: endpoint { ++ remote-endpoint = <&clcd_pads_mb>; ++ }; ++ }; ++ }; ++ }; ++ ++ dvi-transmitter@60 { ++ compatible = "sil,sii9022-cpi", "sil,sii9022"; ++ reg = <0x60>; ++ }; ++ }; ++ ++ rtc@17000 { ++ compatible = "arm,pl031", "arm,primecell"; ++ reg = <0x17000 0x1000>; ++ interrupts = <4>; ++ clocks = <&smbclk>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ compact-flash@1a000 { ++ compatible = "arm,vexpress-cf", "ata-generic"; ++ reg = <0x1a000 0x100 ++ 0x1a100 0xf00>; ++ reg-shift = <2>; ++ }; ++ ++ ++ clcd@1f000 { ++ compatible = "arm,pl111", "arm,primecell"; ++ reg = <0x1f000 0x1000>; ++ interrupt-names = "combined"; ++ interrupts = <14>; ++ clocks = <&v2m_oscclk1>, <&smbclk>; ++ clock-names = "clcdclk", "apb_pclk"; ++ /* 800x600 16bpp @36MHz works fine */ ++ max-memory-bandwidth = <54000000>; ++ memory-region = <&vram>; ++ ++ port { ++ clcd_pads_mb: endpoint { ++ remote-endpoint = <&dvi_bridge_in_mb>; ++ arm,pl11x,tft-r0g0b0-pads = <0 8 16>; ++ }; ++ }; ++ }; ++ }; ++ ++ v2m_fixed_3v3: fixed-regulator-0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ v2m_clk24mhz: clk24mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ clock-output-names = "v2m:clk24mhz"; ++ }; ++ ++ v2m_refclk1mhz: refclk1mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <1000000>; ++ clock-output-names = "v2m:refclk1mhz"; ++ }; ++ ++ v2m_refclk32khz: refclk32khz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "v2m:refclk32khz"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ user1 { ++ label = "v2m:green:user1"; ++ gpios = <&v2m_led_gpios 0 0>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ user2 { ++ label = "v2m:green:user2"; ++ gpios = <&v2m_led_gpios 1 0>; ++ linux,default-trigger = "mmc0"; ++ }; ++ ++ user3 { ++ label = "v2m:green:user3"; ++ gpios = <&v2m_led_gpios 2 0>; ++ linux,default-trigger = "cpu0"; ++ }; ++ ++ user4 { ++ label = "v2m:green:user4"; ++ gpios = <&v2m_led_gpios 3 0>; ++ linux,default-trigger = "cpu1"; ++ }; ++ ++ user5 { ++ label = "v2m:green:user5"; ++ gpios = <&v2m_led_gpios 4 0>; ++ linux,default-trigger = "cpu2"; ++ }; ++ ++ user6 { ++ label = "v2m:green:user6"; ++ gpios = <&v2m_led_gpios 5 0>; ++ linux,default-trigger = "cpu3"; ++ }; ++ ++ user7 { ++ label = "v2m:green:user7"; ++ gpios = <&v2m_led_gpios 6 0>; ++ linux,default-trigger = "cpu4"; ++ }; ++ ++ user8 { ++ label = "v2m:green:user8"; ++ gpios = <&v2m_led_gpios 7 0>; ++ linux,default-trigger = "cpu5"; ++ }; ++ }; ++ ++ mcc { ++ compatible = "arm,vexpress,config-bus"; ++ arm,vexpress,config-bridge = <&v2m_sysreg>; ++ ++ oscclk0 { ++ /* MCC static memory clock */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 0>; ++ freq-range = <25000000 60000000>; ++ #clock-cells = <0>; ++ clock-output-names = "v2m:oscclk0"; ++ }; ++ ++ v2m_oscclk1: oscclk1 { ++ /* CLCD clock */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 1>; ++ freq-range = <23750000 65000000>; ++ #clock-cells = <0>; ++ clock-output-names = "v2m:oscclk1"; ++ }; ++ ++ v2m_oscclk2: oscclk2 { ++ /* IO FPGA peripheral clock */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 2>; ++ freq-range = <24000000 24000000>; ++ #clock-cells = <0>; ++ clock-output-names = "v2m:oscclk2"; ++ }; ++ ++ volt-vio { ++ /* Logic level voltage */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 0>; ++ regulator-name = "VIO"; ++ regulator-always-on; ++ label = "VIO"; ++ }; ++ ++ temp-mcc { ++ /* MCC internal operating temperature */ ++ compatible = "arm,vexpress-temp"; ++ arm,vexpress-sysreg,func = <4 0>; ++ label = "MCC"; ++ }; ++ ++ reset { ++ compatible = "arm,vexpress-reset"; ++ arm,vexpress-sysreg,func = <5 0>; ++ }; ++ ++ muxfpga { ++ compatible = "arm,vexpress-muxfpga"; ++ arm,vexpress-sysreg,func = <7 0>; ++ }; ++ ++ shutdown { ++ compatible = "arm,vexpress-shutdown"; ++ arm,vexpress-sysreg,func = <8 0>; ++ }; ++ ++ reboot { ++ compatible = "arm,vexpress-reboot"; ++ arm,vexpress-sysreg,func = <9 0>; ++ }; ++ ++ dvimode { ++ compatible = "arm,vexpress-dvimode"; ++ arm,vexpress-sysreg,func = <11 0>; ++ }; ++ }; ++ }; ++ }; ++}; +\ No newline at end of file +diff -ruN u-boot-2021.10/arch/arm/dts/vexpress-v2p-ca9.dts u-boot/arch/arm/dts/vexpress-v2p-ca9.dts +--- u-boot-2021.10/arch/arm/dts/vexpress-v2p-ca9.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/dts/vexpress-v2p-ca9.dts 2021-11-01 17:10:13.689623842 +0100 +@@ -0,0 +1,369 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * ARM Ltd. Versatile Express ++ * ++ * CoreTile Express A9x4 ++ * Cortex-A9 MPCore (V2P-CA9) ++ * ++ * HBI-0191B ++ */ ++ ++/dts-v1/; ++#include "vexpress-v2m.dtsi" ++ ++/ { ++ model = "V2P-CA9"; ++ arm,hbi = <0x191>; ++ arm,vexpress,site = <0xf>; ++ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ chosen { }; ++ ++ aliases { ++ serial0 = &v2m_serial0; ++ serial1 = &v2m_serial1; ++ serial2 = &v2m_serial2; ++ serial3 = &v2m_serial3; ++ i2c0 = &v2m_i2c_dvi; ++ i2c1 = &v2m_i2c_pcie; ++ mmc0 = &mmc0; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ A9_0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <0>; ++ next-level-cache = <&L2>; ++ }; ++ ++ A9_1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <1>; ++ next-level-cache = <&L2>; ++ }; ++ ++ A9_2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <2>; ++ next-level-cache = <&L2>; ++ }; ++ ++ A9_3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <3>; ++ next-level-cache = <&L2>; ++ }; ++ }; ++ ++ memory@60000000 { ++ device_type = "memory"; ++ reg = <0x60000000 0x40000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /* Chipselect 3 is physically at 0x4c000000 */ ++ vram: vram@4c000000 { ++ /* 8 MB of designated video RAM */ ++ compatible = "shared-dma-pool"; ++ reg = <0x4c000000 0x00800000>; ++ no-map; ++ }; ++ }; ++ ++ clcd@10020000 { ++ compatible = "arm,pl111", "arm,primecell"; ++ reg = <0x10020000 0x1000>; ++ interrupt-names = "combined"; ++ interrupts = <0 44 4>; ++ clocks = <&oscclk1>, <&oscclk2>; ++ clock-names = "clcdclk", "apb_pclk"; ++ /* 1024x768 16bpp @65MHz */ ++ max-memory-bandwidth = <95000000>; ++ ++ port { ++ clcd_pads_ct: endpoint { ++ remote-endpoint = <&dvi_bridge_in_ct>; ++ arm,pl11x,tft-r0g0b0-pads = <0 8 16>; ++ }; ++ }; ++ }; ++ ++ memory-controller@100e0000 { ++ compatible = "arm,pl341", "arm,primecell"; ++ reg = <0x100e0000 0x1000>; ++ clocks = <&oscclk2>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ memory-controller@100e1000 { ++ compatible = "arm,pl354", "arm,primecell"; ++ reg = <0x100e1000 0x1000>; ++ interrupts = <0 45 4>, ++ <0 46 4>; ++ clocks = <&oscclk2>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ timer@100e4000 { ++ compatible = "arm,sp804", "arm,primecell"; ++ reg = <0x100e4000 0x1000>; ++ interrupts = <0 48 4>, ++ <0 49 4>; ++ clocks = <&oscclk2>, <&oscclk2>; ++ clock-names = "timclk", "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ watchdog@100e5000 { ++ compatible = "arm,sp805", "arm,primecell"; ++ reg = <0x100e5000 0x1000>; ++ interrupts = <0 51 4>; ++ clocks = <&oscclk2>, <&oscclk2>; ++ clock-names = "wdogclk", "apb_pclk"; ++ }; ++ ++ scu@1e000000 { ++ compatible = "arm,cortex-a9-scu"; ++ reg = <0x1e000000 0x58>; ++ }; ++ ++ timer@1e000600 { ++ compatible = "arm,cortex-a9-twd-timer"; ++ reg = <0x1e000600 0x20>; ++ interrupts = <1 13 0xf04>; ++ }; ++ ++ watchdog@1e000620 { ++ compatible = "arm,cortex-a9-twd-wdt"; ++ reg = <0x1e000620 0x20>; ++ interrupts = <1 14 0xf04>; ++ }; ++ ++ gic: interrupt-controller@1e001000 { ++ compatible = "arm,cortex-a9-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0x1e001000 0x1000>, ++ <0x1e000100 0x100>; ++ }; ++ ++ L2: cache-controller@1e00a000 { ++ compatible = "arm,pl310-cache"; ++ reg = <0x1e00a000 0x1000>; ++ interrupts = <0 43 4>; ++ cache-unified; ++ cache-level = <2>; ++ arm,data-latency = <1 1 1>; ++ arm,tag-latency = <1 1 1>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = <0 60 4>, ++ <0 61 4>, ++ <0 62 4>, ++ <0 63 4>; ++ interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; ++ ++ }; ++ ++ dcc { ++ compatible = "arm,vexpress,config-bus"; ++ arm,vexpress,config-bridge = <&v2m_sysreg>; ++ ++ oscclk0: extsaxiclk { ++ /* ACLK clock to the AXI master port on the test chip */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 0>; ++ freq-range = <30000000 50000000>; ++ #clock-cells = <0>; ++ clock-output-names = "extsaxiclk"; ++ }; ++ ++ oscclk1: clcdclk { ++ /* Reference clock for the CLCD */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 1>; ++ freq-range = <10000000 80000000>; ++ #clock-cells = <0>; ++ clock-output-names = "clcdclk"; ++ }; ++ ++ smbclk: oscclk2: tcrefclk { ++ /* Reference clock for the test chip internal PLLs */ ++ compatible = "arm,vexpress-osc"; ++ arm,vexpress-sysreg,func = <1 2>; ++ freq-range = <33000000 100000000>; ++ #clock-cells = <0>; ++ clock-output-names = "tcrefclk"; ++ }; ++ ++ volt-vd10 { ++ /* Test Chip internal logic voltage */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 0>; ++ regulator-name = "VD10"; ++ regulator-always-on; ++ label = "VD10"; ++ }; ++ ++ volt-vd10-s2 { ++ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 1>; ++ regulator-name = "VD10_S2"; ++ regulator-always-on; ++ label = "VD10_S2"; ++ }; ++ ++ volt-vd10-s3 { ++ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 2>; ++ regulator-name = "VD10_S3"; ++ regulator-always-on; ++ label = "VD10_S3"; ++ }; ++ ++ volt-vcc1v8 { ++ /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 3>; ++ regulator-name = "VCC1V8"; ++ regulator-always-on; ++ label = "VCC1V8"; ++ }; ++ ++ volt-ddr2vtt { ++ /* DDR2 SDRAM VTT termination voltage */ ++ compatible = "arm,vexpress-volt"; ++ arm,vexpress-sysreg,func = <2 4>; ++ regulator-name = "DDR2VTT"; ++ regulator-always-on; ++ label = "DDR2VTT"; ++ }; ++ ++ volt-vcc3v3 { ++ /* Local board supply for miscellaneous logic external to the Test Chip */ ++ arm,vexpress-sysreg,func = <2 5>; ++ compatible = "arm,vexpress-volt"; ++ regulator-name = "VCC3V3"; ++ regulator-always-on; ++ label = "VCC3V3"; ++ }; ++ ++ amp-vd10-s2 { ++ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ ++ compatible = "arm,vexpress-amp"; ++ arm,vexpress-sysreg,func = <3 0>; ++ label = "VD10_S2"; ++ }; ++ ++ amp-vd10-s3 { ++ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ ++ compatible = "arm,vexpress-amp"; ++ arm,vexpress-sysreg,func = <3 1>; ++ label = "VD10_S3"; ++ }; ++ ++ power-vd10-s2 { ++ /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ ++ compatible = "arm,vexpress-power"; ++ arm,vexpress-sysreg,func = <12 0>; ++ label = "PVD10_S2"; ++ }; ++ ++ power-vd10-s3 { ++ /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ ++ compatible = "arm,vexpress-power"; ++ arm,vexpress-sysreg,func = <12 1>; ++ label = "PVD10_S3"; ++ }; ++ }; ++ ++ smb: smb@4000000 { ++ compatible = "simple-bus"; ++ ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ranges = <0 0 0x40000000 0x04000000>, ++ <1 0 0x44000000 0x04000000>, ++ <2 0 0x48000000 0x04000000>, ++ <3 0 0x4c000000 0x04000000>, ++ <7 0 0x10000000 0x00020000>; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 63>; ++ interrupt-map = <0 0 0 &gic 0 0 4>, ++ <0 0 1 &gic 0 1 4>, ++ <0 0 2 &gic 0 2 4>, ++ <0 0 3 &gic 0 3 4>, ++ <0 0 4 &gic 0 4 4>, ++ <0 0 5 &gic 0 5 4>, ++ <0 0 6 &gic 0 6 4>, ++ <0 0 7 &gic 0 7 4>, ++ <0 0 8 &gic 0 8 4>, ++ <0 0 9 &gic 0 9 4>, ++ <0 0 10 &gic 0 10 4>, ++ <0 0 11 &gic 0 11 4>, ++ <0 0 12 &gic 0 12 4>, ++ <0 0 13 &gic 0 13 4>, ++ <0 0 14 &gic 0 14 4>, ++ <0 0 15 &gic 0 15 4>, ++ <0 0 16 &gic 0 16 4>, ++ <0 0 17 &gic 0 17 4>, ++ <0 0 18 &gic 0 18 4>, ++ <0 0 19 &gic 0 19 4>, ++ <0 0 20 &gic 0 20 4>, ++ <0 0 21 &gic 0 21 4>, ++ <0 0 22 &gic 0 22 4>, ++ <0 0 23 &gic 0 23 4>, ++ <0 0 24 &gic 0 24 4>, ++ <0 0 25 &gic 0 25 4>, ++ <0 0 26 &gic 0 26 4>, ++ <0 0 27 &gic 0 27 4>, ++ <0 0 28 &gic 0 28 4>, ++ <0 0 29 &gic 0 29 4>, ++ <0 0 30 &gic 0 30 4>, ++ <0 0 31 &gic 0 31 4>, ++ <0 0 32 &gic 0 32 4>, ++ <0 0 33 &gic 0 33 4>, ++ <0 0 34 &gic 0 34 4>, ++ <0 0 35 &gic 0 35 4>, ++ <0 0 36 &gic 0 36 4>, ++ <0 0 37 &gic 0 37 4>, ++ <0 0 38 &gic 0 38 4>, ++ <0 0 39 &gic 0 39 4>, ++ <0 0 40 &gic 0 40 4>, ++ <0 0 41 &gic 0 41 4>, ++ <0 0 42 &gic 0 42 4>; ++ }; ++ ++ site2: hsb@e0000000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0xe0000000 0x20000000>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 3>; ++ interrupt-map = <0 0 &gic 0 36 4>, ++ <0 1 &gic 0 37 4>, ++ <0 2 &gic 0 38 4>, ++ <0 3 &gic 0 39 4>; ++ }; ++}; +diff -ruN u-boot-2021.10/arch/arm/dts/vf610-pinfunc.h u-boot/arch/arm/dts/vf610-pinfunc.h +--- u-boot-2021.10/arch/arm/dts/vf610-pinfunc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/vf610-pinfunc.h 2021-11-01 17:10:13.689623842 +0100 +@@ -424,7 +424,7 @@ + #define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 + #define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 + #define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 ++#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 + #define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 + #define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 + #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +diff -ruN u-boot-2021.10/arch/arm/dts/zynqmp-e-a2197-00-revA.dts u-boot/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +--- u-boot-2021.10/arch/arm/dts/zynqmp-e-a2197-00-revA.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/zynqmp-e-a2197-00-revA.dts 2021-11-01 17:10:13.689623842 +0100 +@@ -24,6 +24,9 @@ + i2c1 = &i2c1; + mmc0 = &sdhci1; + nvmem0 = &eeprom; ++ nvmem1 = &eeprom_ebm; ++ nvmem2 = &eeprom_fmc1; ++ nvmem3 = &eeprom_fmc2; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; +@@ -477,6 +480,10 @@ + silabs,skip-recall; + }; + /* and connector J212D */ ++ eeprom_ebm: eeprom@52 { /* x-ebm module */ ++ compatible = "st,24c128", "atmel,24c128"; ++ reg = <0x52>; ++ }; + }; + fmc1: i2c@1 { /* FMCP1_IIC */ + #address-cells = <1>; +@@ -484,6 +491,10 @@ + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 FMC cards */ ++ eeprom_fmc1: eeprom@50 { ++ compatible = "st,24c128", "atmel,24c128"; ++ reg = <0x50>; ++ }; + }; + fmc2: i2c@2 { /* FMCP2_IIC */ + #address-cells = <1>; +@@ -491,6 +502,10 @@ + reg = <2>; + /* FIXME connection to Samtec J53C */ + /* expected eeprom 0x50 FMC cards */ ++ eeprom_fmc2: eeprom@50 { ++ compatible = "st,24c128", "atmel,24c128"; ++ reg = <0x50>; ++ }; + }; + i2c@3 { /* DDR4_DIMM1 */ + #address-cells = <1>; +diff -ruN u-boot-2021.10/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts u-boot/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +--- u-boot-2021.10/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts 2021-11-01 17:10:13.692956993 +0100 +@@ -140,6 +140,8 @@ + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-0"; ++ nand-ecc-step-size = <1024>; ++ nand-ecc-strength = <24>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; +@@ -174,6 +176,8 @@ + nand-ecc-algo = "bch"; + nand-rb = <0>; + label = "main-storage-1"; ++ nand-ecc-step-size = <1024>; ++ nand-ecc-strength = <24>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; +diff -ruN u-boot-2021.10/arch/arm/dts/zynq-zed.dts u-boot/arch/arm/dts/zynq-zed.dts +--- u-boot-2021.10/arch/arm/dts/zynq-zed.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/dts/zynq-zed.dts 2021-11-01 17:10:13.689623842 +0100 +@@ -53,7 +53,7 @@ + status = "okay"; + num-cs = <1>; + flash@0 { +- compatible = "spansion,s25fl256s", "jedec,spi-nor"; ++ compatible = "spansion,s25fl256s1", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + m25p,fast-read; +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-am33xx/chilisom.h u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h +--- u-boot-2021.10/arch/arm/include/asm/arch-am33xx/chilisom.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-am33xx/chilisom.h 2021-11-01 17:10:13.692956993 +0100 +@@ -6,7 +6,7 @@ + #ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ + #define __ARCH_ARM_MACH_CHILISOM_SOM_H__ + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + void chilisom_enable_pin_mux(void); + void chilisom_spl_board_init(void); + #endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-am33xx/cpu.h u-boot/arch/arm/include/asm/arch-am33xx/cpu.h +--- u-boot-2021.10/arch/arm/include/asm/arch-am33xx/cpu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-am33xx/cpu.h 2021-11-01 17:10:13.692956993 +0100 +@@ -408,7 +408,7 @@ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ + unsigned int resv2[11]; +- unsigned int clkselmacclk; /* offset 0x34 */ ++ unsigned int clkselmacclk; /* offset 0x34 */ + }; + #endif /* CONFIG_AM43XX */ + +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/armada100.h u-boot/arch/arm/include/asm/arch-armada100/armada100.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/armada100.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/armada100.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,59 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar +- * Contributor: Mahavir Jain +- */ +- +-#ifndef _ASM_ARCH_ARMADA100_H +-#define _ASM_ARCH_ARMADA100_H +- +-#if defined (CONFIG_ARMADA100) +- +-/* Common APB clock register bit definitions */ +-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ +-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ +-#define APBC_RST (1<<2) /* Reset Generation */ +-/* Functional Clock Selection Mask */ +-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +- +-/* Fast Ethernet Controller Clock register definition */ +-#define FE_CLK_RST 0x1 +-#define FE_CLK_ENA 0x8 +- +-/* SSP2 Clock Control */ +-#define SSP2_APBCLK 0x01 +-#define SSP2_FNCLK 0x02 +- +-/* USB Clock/reset control bits */ +-#define USB_SPH_AXICLK_EN 0x10 +-#define USB_SPH_AXI_RST 0x02 +- +-/* MPMU Clocks */ +-#define APB2_26M_EN (1 << 20) +-#define AP_26M (1 << 4) +- +-/* Register Base Addresses */ +-#define ARMD1_DRAM_BASE 0xB0000000 +-#define ARMD1_FEC_BASE 0xC0800000 +-#define ARMD1_TIMER_BASE 0xD4014000 +-#define ARMD1_APBC1_BASE 0xD4015000 +-#define ARMD1_APBC2_BASE 0xD4015800 +-#define ARMD1_UART1_BASE 0xD4017000 +-#define ARMD1_UART2_BASE 0xD4018000 +-#define ARMD1_GPIO_BASE 0xD4019000 +-#define ARMD1_SSP1_BASE 0xD401B000 +-#define ARMD1_SSP2_BASE 0xD401C000 +-#define ARMD1_MFPR_BASE 0xD401E000 +-#define ARMD1_SSP3_BASE 0xD401F000 +-#define ARMD1_SSP4_BASE 0xD4020000 +-#define ARMD1_SSP5_BASE 0xD4021000 +-#define ARMD1_UART3_BASE 0xD4026000 +-#define ARMD1_MPMU_BASE 0xD4050000 +-#define ARMD1_USB_HOST_BASE 0xD4209000 +-#define ARMD1_APMU_BASE 0xD4282800 +-#define ARMD1_CPU_BASE 0xD4282C00 +- +-#endif /* CONFIG_ARMADA100 */ +-#endif /* _ASM_ARCH_ARMADA100_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/config.h u-boot/arch/arm/include/asm/arch-armada100/config.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/config.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,27 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * Marvell Semiconductor +- * Written-by: Lei Wen +- */ +- +-/* +- * This file should be included in board config header file. +- * +- * It supports common definitions for Armada100 platform +- */ +- +-#ifndef _ARMD1_CONFIG_H +-#define _ARMD1_CONFIG_H +- +-#include +- +-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ +-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ +-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ +-#define MV_MFPR_BASE ARMD1_MFPR_BASE +-#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE +-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register +- represents UART Unit Enable */ +- +-#endif /* _ARMD1_CONFIG_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/cpu.h u-boot/arch/arm/include/asm/arch-armada100/cpu.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/cpu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/cpu.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,161 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar , Contributor: Mahavir Jain +- */ +- +-#ifndef _ARMADA100CPU_H +-#define _ARMADA100CPU_H +- +-#include +-#include +- +-/* +- * Main Power Management (MPMU) Registers +- * Refer Datasheet Appendix A.8 +- */ +-struct armd1mpmu_registers { +- u8 pad0[0x08 - 0x00]; +- u32 fccr; /*0x0008*/ +- u32 pocr; /*0x000c*/ +- u32 posr; /*0x0010*/ +- u32 succr; /*0x0014*/ +- u8 pad1[0x030 - 0x014 - 4]; +- u32 gpcr; /*0x0030*/ +- u8 pad2[0x200 - 0x030 - 4]; +- u32 wdtpcr; /*0x0200*/ +- u8 pad3[0x1000 - 0x200 - 4]; +- u32 apcr; /*0x1000*/ +- u32 apsr; /*0x1004*/ +- u8 pad4[0x1020 - 0x1004 - 4]; +- u32 aprr; /*0x1020*/ +- u32 acgr; /*0x1024*/ +- u32 arsr; /*0x1028*/ +-}; +- +-/* +- * Application Subsystem Power Management +- * Refer Datasheet Appendix A.9 +- */ +-struct armd1apmu_registers { +- u32 pcr; /* 0x000 */ +- u32 ccr; /* 0x004 */ +- u32 pad1; +- u32 ccsr; /* 0x00C */ +- u32 fc_timer; /* 0x010 */ +- u32 pad2; +- u32 ideal_cfg; /* 0x018 */ +- u8 pad3[0x04C - 0x018 - 4]; +- u32 lcdcrc; /* 0x04C */ +- u32 cciccrc; /* 0x050 */ +- u32 sd1crc; /* 0x054 */ +- u32 sd2crc; /* 0x058 */ +- u32 usbcrc; /* 0x05C */ +- u32 nfccrc; /* 0x060 */ +- u32 dmacrc; /* 0x064 */ +- u32 pad4; +- u32 buscrc; /* 0x06C */ +- u8 pad5[0x07C - 0x06C - 4]; +- u32 wake_clr; /* 0x07C */ +- u8 pad6[0x090 - 0x07C - 4]; +- u32 core_status; /* 0x090 */ +- u32 rfsc; /* 0x094 */ +- u32 imr; /* 0x098 */ +- u32 irwc; /* 0x09C */ +- u32 isr; /* 0x0A0 */ +- u8 pad7[0x0B0 - 0x0A0 - 4]; +- u32 mhst; /* 0x0B0 */ +- u32 msr; /* 0x0B4 */ +- u8 pad8[0x0C0 - 0x0B4 - 4]; +- u32 msst; /* 0x0C0 */ +- u32 pllss; /* 0x0C4 */ +- u32 smb; /* 0x0C8 */ +- u32 gccrc; /* 0x0CC */ +- u8 pad9[0x0D4 - 0x0CC - 4]; +- u32 smccrc; /* 0x0D4 */ +- u32 pad10; +- u32 xdcrc; /* 0x0DC */ +- u32 sd3crc; /* 0x0E0 */ +- u32 sd4crc; /* 0x0E4 */ +- u8 pad11[0x0F0 - 0x0E4 - 4]; +- u32 cfcrc; /* 0x0F0 */ +- u32 mspcrc; /* 0x0F4 */ +- u32 cmucrc; /* 0x0F8 */ +- u32 fecrc; /* 0x0FC */ +- u32 pciecrc; /* 0x100 */ +- u32 epdcrc; /* 0x104 */ +-}; +- +-/* +- * APB1 Clock Reset/Control Registers +- * Refer Datasheet Appendix A.10 +- */ +-struct armd1apb1_registers { +- u32 uart1; /*0x000*/ +- u32 uart2; /*0x004*/ +- u32 gpio; /*0x008*/ +- u32 pwm1; /*0x00c*/ +- u32 pwm2; /*0x010*/ +- u32 pwm3; /*0x014*/ +- u32 pwm4; /*0x018*/ +- u8 pad0[0x028 - 0x018 - 4]; +- u32 rtc; /*0x028*/ +- u32 twsi0; /*0x02c*/ +- u32 kpc; /*0x030*/ +- u32 timers; /*0x034*/ +- u8 pad1[0x03c - 0x034 - 4]; +- u32 aib; /*0x03c*/ +- u32 sw_jtag; /*0x040*/ +- u32 timer1; /*0x044*/ +- u32 onewire; /*0x048*/ +- u8 pad2[0x050 - 0x048 - 4]; +- u32 asfar; /*0x050 AIB Secure First Access Reg*/ +- u32 assar; /*0x054 AIB Secure Second Access Reg*/ +- u8 pad3[0x06c - 0x054 - 4]; +- u32 twsi1; /*0x06c*/ +- u32 uart3; /*0x070*/ +- u8 pad4[0x07c - 0x070 - 4]; +- u32 timer2; /*0x07C*/ +- u8 pad5[0x084 - 0x07c - 4]; +- u32 ac97; /*0x084*/ +-}; +- +-/* +-* APB2 Clock Reset/Control Registers +-* Refer Datasheet Appendix A.11 +-*/ +-struct armd1apb2_registers { +- u32 pad1[0x01C - 0x000]; +- u32 ssp1_clkrst; /* 0x01C */ +- u32 ssp2_clkrst; /* 0x020 */ +- u32 pad2[0x04C - 0x020 - 4]; +- u32 ssp3_clkrst; /* 0x04C */ +- u32 pad3[0x058 - 0x04C - 4]; +- u32 ssp4_clkrst; /* 0x058 */ +- u32 ssp5_clkrst; /* 0x05C */ +-}; +- +-/* +- * CPU Interface Registers +- * Refer Datasheet Appendix A.2 +- */ +-struct armd1cpu_registers { +- u32 chip_id; /* Chip Id Reg */ +- u32 pad; +- u32 cpu_conf; /* CPU Conf Reg */ +- u32 pad1; +- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ +- u32 pad2; +- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ +- u32 mcb_conf; /* MCB Conf Reg */ +- u32 sys_boot_ctl; /* Sytem Boot Control */ +-}; +- +-/* +- * Functions +- */ +-u32 armd1_sdram_base(int); +-u32 armd1_sdram_size(int); +- +-#endif /* _ARMADA100CPU_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/gpio.h u-boot/arch/arm/include/asm/arch-armada100/gpio.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/gpio.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,31 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * eInfochips Ltd. +- * Written-by: Ajay Bhargav +- * +- * (C) Copyright 2010 +- * Marvell Semiconductor +- */ +- +-#ifndef _ASM_ARCH_GPIO_H +-#define _ASM_ARCH_GPIO_H +- +-#include +-#include +- +-#define GPIO_HIGH 1 +-#define GPIO_LOW 0 +- +-#define GPIO_TO_REG(gp) (gp >> 5) +-#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) +-#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) +- +-static inline void *get_gpio_base(int bank) +-{ +- const unsigned int offset[4] = {0, 4, 8, 0x100}; +- /* gpio register bank offset - refer Appendix A.36 */ +- return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); +-} +- +-#endif /* _ASM_ARCH_GPIO_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/mfp.h u-boot/arch/arm/include/asm/arch-armada100/mfp.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/mfp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/mfp.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,79 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h +- * (C) Copyright 2007 +- * Marvell Semiconductor +- * 2007-08-21: eric miao +- * +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar +- * Contributor: Mahavir Jain +- */ +- +-#ifndef __ARMADA100_MFP_H +-#define __ARMADA100_MFP_H +- +-/* +- * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs +- * +- * offset, pull,pF, drv,dF, edge,eF ,afn,aF +- */ +-/* UART1 */ +-#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) +-#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) +-#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) +-#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) +-#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +-#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) +-#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +-#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) +-#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) +-#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) +-#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) +-#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) +- +-/* UART2 */ +-#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) +-#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) +-#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) +-#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) +- +-/* UART3 */ +-#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) +-#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) +- +-/* I2c */ +-#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +-#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +- +-/* Fast Ethernet */ +-#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +-#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +- +-/* SPI */ +-#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) +-#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) +-#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) +-#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) +- +-/* More macros can be defined here... */ +- +-#define MFP_PIN_MAX 117 +- +-#endif /* __ARMADA100_MFP_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/spi.h u-boot/arch/arm/include/asm/arch-armada100/spi.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/spi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/spi.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,78 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * eInfochips Ltd. +- * Written-by: Ajay Bhargav +- * +- * (C) Copyright 2010 +- * Marvell Semiconductor +- */ +- +-#ifndef __ARMADA100_SPI_H_ +-#define __ARMADA100_SPI_H_ +- +-#include +- +-#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE +-#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) +- +-/* +- * SSP Serial Port Registers +- * refer Appendix A.26 +- */ +-struct ssp_reg { +- u32 sscr0; /* SSP Control Register 0 - 0x000 */ +- u32 sscr1; /* SSP Control Register 1 - 0x004 */ +- u32 sssr; /* SSP Status Register - 0x008 */ +- u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ +- u32 ssdr; /* SSP Data Register - 0x010 */ +- u32 pad1[5]; +- u32 ssto; /* SSP Timeout Register - 0x028 */ +- u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ +- u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ +- u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ +- u32 sstss; /* SSP Timeslot Status Register - 0x038 */ +-}; +- +-#define DEFAULT_WORD_LEN 8 +-#define SSP_FLUSH_NUM 0x2000 +-#define RX_THRESH_DEF 8 +-#define TX_THRESH_DEF 8 +-#define TIMEOUT_DEF 1000 +- +-#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +-#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +-#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +-#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity +- setting */ +-#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +-#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +-#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ +-#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ +- +-#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ +-#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ +-#define SSCR1_TINTE (1 << 19) /* Receiver Time-out +- Interrupt enable */ +- +-#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ +-#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ +-#define SSCR0_FRF 0x30 /* FRame Format (mask) */ +-#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial +- Peripheral Interface */ +-#define SSCR0_TI (0x1 << 4) /* TI's Synchronous +- Serial Protocol (SSP) */ +-#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ +-#define SSCR0_ECS (1 << 6) /* External clock select */ +-#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port +- Enable */ +- +-#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ +-#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ +-#define SSSR_BSY (1 << 4) /* SSP Busy */ +-#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ +-#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ +-#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ +-#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ +- +-#endif /* __ARMADA100_SPI_H_ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-armada100/utmi-armada100.h u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h +--- u-boot-2021.10/arch/arm/include/asm/arch-armada100/utmi-armada100.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,62 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2012 +- * eInfochips Ltd. +- * Written-by: Ajay Bhargav +- * +- * (C) Copyright 2009 +- * Marvell Semiconductor +- */ +- +-#ifndef __UTMI_ARMADA100__ +-#define __UTMI_ARMADA100__ +- +-#define UTMI_PHY_BASE 0xD4206000 +- +-/* utmi_ctrl - bits */ +-#define INPKT_DELAY_SOF (1 << 28) +-#define PLL_PWR_UP 2 +-#define PHY_PWR_UP 1 +- +-/* utmi_pll - bits */ +-#define PLL_FBDIV_MASK 0x00000FF0 +-#define PLL_FBDIV 4 +-#define PLL_REFDIV_MASK 0x0000000F +-#define PLL_REFDIV 0 +-#define PLL_READY 0x800000 +-#define VCOCAL_START (1 << 21) +- +-#define N_DIVIDER 0xEE +-#define M_DIVIDER 0x0B +- +-/* utmi_tx - bits */ +-#define CK60_PHSEL 17 +-#define PHSEL_VAL 0x4 +-#define RCAL_START (1 << 12) +- +-/* +- * USB PHY registers +- * Refer Datasheet Appendix A.21 +- */ +-struct armd1usb_phy_reg { +- u32 utmi_rev; /* USB PHY Revision */ +- u32 utmi_ctrl; /* USB PHY Control register */ +- u32 utmi_pll; /* PLL register */ +- u32 utmi_tx; /* Tx register */ +- u32 utmi_rx; /* Rx register */ +- u32 utmi_ivref; /* IVREF register */ +- u32 utmi_tst_g0; /* Test group 0 register */ +- u32 utmi_tst_g1; /* Test group 1 register */ +- u32 utmi_tst_g2; /* Test group 2 register */ +- u32 utmi_tst_g3; /* Test group 3 register */ +- u32 utmi_tst_g4; /* Test group 4 register */ +- u32 utmi_tst_g5; /* Test group 5 register */ +- u32 utmi_reserve; /* Reserve Register */ +- u32 utmi_usb_int; /* USB interuppt register */ +- u32 utmi_dbg_ctl; /* Debug control register */ +- u32 utmi_otg_addon; /* OTG addon register */ +-}; +- +-int utmi_init(void); +- +-#endif /* __UTMI_ARMADA100__ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-fsl-layerscape/config.h u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h +--- u-boot-2021.10/arch/arm/include/asm/arch-fsl-layerscape/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-fsl-layerscape/config.h 2021-11-01 17:10:13.696290145 +0100 +@@ -123,7 +123,6 @@ + #elif defined(CONFIG_ARCH_LS1088A) + #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 + #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +-#define CONFIG_GICV3 + #define CONFIG_SYS_PAGE_SIZE 0x10000 + + #define SRDS_MAX_LANES 4 +@@ -183,10 +182,6 @@ + #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) + #define TZPC_BASE 0x02200000 + #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_EARLY_INIT +-#endif + #define SRDS_MAX_LANES 8 + #ifndef L1_CACHE_BYTES + #define L1_CACHE_SHIFT 6 +@@ -239,7 +234,6 @@ + #elif defined(CONFIG_ARCH_LS1028A) + #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 + #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +-#define CONFIG_GICV3 + #define CONFIG_FSL_TZPC_BP147 + #define CONFIG_FSL_TZASC_400 + +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-imxrt/imxrt.h u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h +--- u-boot-2021.10/arch/arm/include/asm/arch-imxrt/imxrt.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-imxrt/imxrt.h 2021-11-01 17:10:13.702956446 +0100 +@@ -8,4 +8,3 @@ + #define _ASM_ARCH_IMXRT_H + + #endif /* _ASM_ARCH_IMXRT_H */ +- +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-lpc32xx/config.h u-boot/arch/arm/include/asm/arch-lpc32xx/config.h +--- u-boot-2021.10/arch/arm/include/asm/arch-lpc32xx/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-lpc32xx/config.h 2021-11-01 17:10:13.702956446 +0100 +@@ -34,28 +34,18 @@ + #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 + #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 + +-#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE +-#endif +- + #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) +-#define CONFIG_SYS_NAND_OOBSIZE 16 + #define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #else + #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" + #endif + + #define CONFIG_SYS_NAND_ECCSIZE 0x100 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) + #endif /* CONFIG_NAND_LPC32XX_SLC */ + + /* NOR Flash */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx25/clock.h u-boot/arch/arm/include/asm/arch-mx25/clock.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx25/clock.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx25/clock.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,57 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * +- * (c) 2009 Ilya Yanok, Emcraft Systems +- * +- * Modified for mx25 by John Rigby +- */ +- +-#ifndef __ASM_ARCH_CLOCK_H +-#define __ASM_ARCH_CLOCK_H +- +-#ifdef CONFIG_MX25_HCLK_FREQ +-#define MXC_HCLK CONFIG_MX25_HCLK_FREQ +-#else +-#define MXC_HCLK 24000000 +-#endif +- +-#ifdef CONFIG_MX25_CLK32 +-#define MXC_CLK32 CONFIG_MX25_CLK32 +-#else +-#define MXC_CLK32 32768 +-#endif +- +-enum mxc_clock { +- /* PER clocks (do not change order) */ +- MXC_CSI_CLK, +- MXC_EPIT_CLK, +- MXC_ESAI_CLK, +- MXC_ESDHC1_CLK, +- MXC_ESDHC2_CLK, +- MXC_GPT_CLK, +- MXC_I2C_CLK, +- MXC_LCDC_CLK, +- MXC_NFC_CLK, +- MXC_OWIRE_CLK, +- MXC_PWM_CLK, +- MXC_SIM1_CLK, +- MXC_SIM2_CLK, +- MXC_SSI1_CLK, +- MXC_SSI2_CLK, +- MXC_UART_CLK, +- /* Other clocks */ +- MXC_ARM_CLK, +- MXC_AHB_CLK, +- MXC_IPG_CLK, +- MXC_CSPI_CLK, +- MXC_FEC_CLK, +- MXC_CLK_NUM +-}; +- +-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq); +-unsigned int mxc_get_clock(enum mxc_clock clk); +- +-#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) +-#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) +- +-#endif /* __ASM_ARCH_CLOCK_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx25/gpio.h u-boot/arch/arm/include/asm/arch-mx25/gpio.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx25/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx25/gpio.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2011 +- * Stefano Babic, DENX Software Engineering, +- */ +- +- +-#ifndef __ASM_ARCH_MX25_GPIO_H +-#define __ASM_ARCH_MX25_GPIO_H +- +-#include +- +-#endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx25/imx-regs.h u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx25/imx-regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,504 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2009, DENX Software Engineering +- * Author: John Rigby +- * and arch-mx27/imx-regs.h +- * Copyright (C) 2007 Pengutronix, +- * Sascha Hauer +- * Copyright (C) 2009 Ilya Yanok, +- * Emcraft Systems +- */ +- +-#ifndef _IMX_REGS_H +-#define _IMX_REGS_H +- +-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +-#include +- +-/* Clock Control Module (CCM) registers */ +-struct ccm_regs { +- u32 mpctl; /* Core PLL Control */ +- u32 upctl; /* USB PLL Control */ +- u32 cctl; /* Clock Control */ +- u32 cgr0; /* Clock Gating Control 0 */ +- u32 cgr1; /* Clock Gating Control 1 */ +- u32 cgr2; /* Clock Gating Control 2 */ +- u32 pcdr[4]; /* PER Clock Dividers */ +- u32 rcsr; /* CCM Status */ +- u32 crdr; /* CCM Reset and Debug */ +- u32 dcvr0; /* DPTC Comparator Value 0 */ +- u32 dcvr1; /* DPTC Comparator Value 1 */ +- u32 dcvr2; /* DPTC Comparator Value 2 */ +- u32 dcvr3; /* DPTC Comparator Value 3 */ +- u32 ltr0; /* Load Tracking 0 */ +- u32 ltr1; /* Load Tracking 1 */ +- u32 ltr2; /* Load Tracking 2 */ +- u32 ltr3; /* Load Tracking 3 */ +- u32 ltbr0; /* Load Tracking Buffer 0 */ +- u32 ltbr1; /* Load Tracking Buffer 1 */ +- u32 pcmr0; /* Power Management Control 0 */ +- u32 pcmr1; /* Power Management Control 1 */ +- u32 pcmr2; /* Power Management Control 2 */ +- u32 mcr; /* Miscellaneous Control */ +- u32 lpimr0; /* Low Power Interrupt Mask 0 */ +- u32 lpimr1; /* Low Power Interrupt Mask 1 */ +-}; +- +-/* Enhanced SDRAM Controller (ESDRAMC) registers */ +-struct esdramc_regs { +- u32 ctl0; /* control 0 */ +- u32 cfg0; /* configuration 0 */ +- u32 ctl1; /* control 1 */ +- u32 cfg1; /* configuration 1 */ +- u32 misc; /* miscellaneous */ +- u32 pad[3]; +- u32 cdly1; /* Delay Line 1 configuration debug */ +- u32 cdly2; /* delay line 2 configuration debug */ +- u32 cdly3; /* delay line 3 configuration debug */ +- u32 cdly4; /* delay line 4 configuration debug */ +- u32 cdly5; /* delay line 5 configuration debug */ +- u32 cdlyl; /* delay line cycle length debug */ +-}; +- +-/* General Purpose Timer (GPT) registers */ +-struct gpt_regs { +- u32 ctrl; /* control */ +- u32 pre; /* prescaler */ +- u32 stat; /* status */ +- u32 intr; /* interrupt */ +- u32 cmp[3]; /* output compare 1-3 */ +- u32 capt[2]; /* input capture 1-2 */ +- u32 counter; /* counter */ +-}; +- +-/* Watchdog Timer (WDOG) registers */ +-struct wdog_regs { +- u16 wcr; /* Control */ +- u16 wsr; /* Service */ +- u16 wrsr; /* Reset Status */ +- u16 wicr; /* Interrupt Control */ +- u16 wmcr; /* Misc Control */ +-}; +- +-/* IIM control registers */ +-struct iim_regs { +- u32 iim_stat; +- u32 iim_statm; +- u32 iim_err; +- u32 iim_emask; +- u32 iim_fctl; +- u32 iim_ua; +- u32 iim_la; +- u32 iim_sdat; +- u32 iim_prev; +- u32 iim_srev; +- u32 iim_prg_p; +- u32 iim_scs0; +- u32 iim_scs1; +- u32 iim_scs2; +- u32 iim_scs3; +- u32 res1[0x1f1]; +- struct fuse_bank { +- u32 fuse_regs[0x20]; +- u32 fuse_rsvd[0xe0]; +- } bank[3]; +-}; +- +-struct fuse_bank0_regs { +- u32 fuse0_7[8]; +- u32 uid[8]; +- u32 fuse16_25[0xa]; +- u32 mac_addr[6]; +-}; +- +-struct fuse_bank1_regs { +- u32 fuse0_21[0x16]; +- u32 usr5; +- u32 fuse23_29[7]; +- u32 usr6[2]; +-}; +- +-/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +-struct max_regs { +- u32 mpr0; +- u32 pad00[3]; +- u32 sgpcr0; +- u32 pad01[59]; +- u32 mpr1; +- u32 pad02[3]; +- u32 sgpcr1; +- u32 pad03[59]; +- u32 mpr2; +- u32 pad04[3]; +- u32 sgpcr2; +- u32 pad05[59]; +- u32 mpr3; +- u32 pad06[3]; +- u32 sgpcr3; +- u32 pad07[59]; +- u32 mpr4; +- u32 pad08[3]; +- u32 sgpcr4; +- u32 pad09[251]; +- u32 mgpcr0; +- u32 pad10[63]; +- u32 mgpcr1; +- u32 pad11[63]; +- u32 mgpcr2; +- u32 pad12[63]; +- u32 mgpcr3; +- u32 pad13[63]; +- u32 mgpcr4; +-}; +- +-/* AHB <-> IP-Bus Interface (AIPS) */ +-struct aips_regs { +- u32 mpr_0_7; +- u32 mpr_8_15; +-}; +-/* LCD controller registers */ +-struct lcdc_regs { +- u32 lssar; /* Screen Start Address */ +- u32 lsr; /* Size */ +- u32 lvpwr; /* Virtual Page Width */ +- u32 lcpr; /* Cursor Position */ +- u32 lcwhb; /* Cursor Width Height and Blink */ +- u32 lccmr; /* Color Cursor Mapping */ +- u32 lpcr; /* Panel Configuration */ +- u32 lhcr; /* Horizontal Configuration */ +- u32 lvcr; /* Vertical Configuration */ +- u32 lpor; /* Panning Offset */ +- u32 lscr; /* Sharp Configuration */ +- u32 lpccr; /* PWM Contrast Control */ +- u32 ldcr; /* DMA Control */ +- u32 lrmcr; /* Refresh Mode Control */ +- u32 licr; /* Interrupt Configuration */ +- u32 lier; /* Interrupt Enable */ +- u32 lisr; /* Interrupt Status */ +- u32 res0[3]; +- u32 lgwsar; /* Graphic Window Start Address */ +- u32 lgwsr; /* Graphic Window Size */ +- u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ +- u32 lgwpor; /* Graphic Window Panning Offset */ +- u32 lgwpr; /* Graphic Window Position */ +- u32 lgwcr; /* Graphic Window Control */ +- u32 lgwdcr; /* Graphic Window DMA Control */ +- u32 res1[5]; +- u32 lauscr; /* AUS Mode Control */ +- u32 lausccr; /* AUS mode Cursor Control */ +- u32 res2[31 + 64*7]; +- u32 bglut; /* Background Lookup Table */ +- u32 gwlut; /* Graphic Window Lookup Table */ +-}; +- +-/* Wireless External Interface Module Registers */ +-struct weim_regs { +- u32 cscr0u; /* Chip Select 0 Upper Register */ +- u32 cscr0l; /* Chip Select 0 Lower Register */ +- u32 cscr0a; /* Chip Select 0 Addition Register */ +- u32 pad0; +- u32 cscr1u; /* Chip Select 1 Upper Register */ +- u32 cscr1l; /* Chip Select 1 Lower Register */ +- u32 cscr1a; /* Chip Select 1 Addition Register */ +- u32 pad1; +- u32 cscr2u; /* Chip Select 2 Upper Register */ +- u32 cscr2l; /* Chip Select 2 Lower Register */ +- u32 cscr2a; /* Chip Select 2 Addition Register */ +- u32 pad2; +- u32 cscr3u; /* Chip Select 3 Upper Register */ +- u32 cscr3l; /* Chip Select 3 Lower Register */ +- u32 cscr3a; /* Chip Select 3 Addition Register */ +- u32 pad3; +- u32 cscr4u; /* Chip Select 4 Upper Register */ +- u32 cscr4l; /* Chip Select 4 Lower Register */ +- u32 cscr4a; /* Chip Select 4 Addition Register */ +- u32 pad4; +- u32 cscr5u; /* Chip Select 5 Upper Register */ +- u32 cscr5l; /* Chip Select 5 Lower Register */ +- u32 cscr5a; /* Chip Select 5 Addition Register */ +- u32 pad5; +- u32 wcr; /* WEIM Configuration Register */ +-}; +- +-/* Multi-Master Memory Interface */ +-struct m3if_regs { +- u32 ctl; /* Control Register */ +- u32 wcfg0; /* Watermark Configuration Register 0 */ +- u32 wcfg1; /* Watermark Configuration Register1 */ +- u32 wcfg2; /* Watermark Configuration Register2 */ +- u32 wcfg3; /* Watermark Configuration Register 3 */ +- u32 wcfg4; /* Watermark Configuration Register 4 */ +- u32 wcfg5; /* Watermark Configuration Register 5 */ +- u32 wcfg6; /* Watermark Configuration Register 6 */ +- u32 wcfg7; /* Watermark Configuration Register 7 */ +- u32 wcsr; /* Watermark Control and Status Register */ +- u32 scfg0; /* Snooping Configuration Register 0 */ +- u32 scfg1; /* Snooping Configuration Register 1 */ +- u32 scfg2; /* Snooping Configuration Register 2 */ +- u32 ssr0; /* Snooping Status Register 0 */ +- u32 ssr1; /* Snooping Status Register 1 */ +- u32 res0; +- u32 mlwe0; /* Master Lock WEIM CS0 Register */ +- u32 mlwe1; /* Master Lock WEIM CS1 Register */ +- u32 mlwe2; /* Master Lock WEIM CS2 Register */ +- u32 mlwe3; /* Master Lock WEIM CS3 Register */ +- u32 mlwe4; /* Master Lock WEIM CS4 Register */ +- u32 mlwe5; /* Master Lock WEIM CS5 Register */ +-}; +- +-/* Pulse width modulation */ +-struct pwm_regs { +- u32 cr; /* Control Register */ +- u32 sr; /* Status Register */ +- u32 ir; /* Interrupt Register */ +- u32 sar; /* Sample Register */ +- u32 pr; /* Period Register */ +- u32 cnr; /* Counter Register */ +-}; +- +-/* Enhanced Periodic Interrupt Timer */ +-struct epit_regs { +- u32 cr; /* Control register */ +- u32 sr; /* Status register */ +- u32 lr; /* Load register */ +- u32 cmpr; /* Compare register */ +- u32 cnr; /* Counter register */ +-}; +- +-#endif +- +-#define ARCH_MXC +- +-/* AIPS 1 */ +-#define IMX_AIPS1_BASE (0x43F00000) +-#define IMX_MAX_BASE (0x43F04000) +-#define IMX_CLKCTL_BASE (0x43F08000) +-#define IMX_ETB_SLOT4_BASE (0x43F0C000) +-#define IMX_ETB_SLOT5_BASE (0x43F10000) +-#define IMX_ECT_CTIO_BASE (0x43F18000) +-#define I2C1_BASE_ADDR (0x43F80000) +-#define I2C3_BASE_ADDR (0x43F84000) +-#define IMX_CAN1_BASE (0x43F88000) +-#define IMX_CAN2_BASE (0x43F8C000) +-#define UART1_BASE (0x43F90000) +-#define UART2_BASE (0x43F94000) +-#define I2C2_BASE_ADDR (0x43F98000) +-#define IMX_OWIRE_BASE (0x43F9C000) +-#define IMX_CSPI1_BASE (0x43FA4000) +-#define IMX_KPP_BASE (0x43FA8000) +-#define IMX_IOPADMUX_BASE (0x43FAC000) +-#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE +-#define IMX_IOPADCTL_BASE (0x43FAC22C) +-#define IMX_IOPADGRPCTL_BASE (0x43FAC418) +-#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) +-#define IMX_AUDMUX_BASE (0x43FB0000) +-#define IMX_ECT_IP1_BASE (0x43FB8000) +-#define IMX_ECT_IP2_BASE (0x43FBC000) +- +-/* SPBA */ +-#define IMX_SPBA_BASE (0x50000000) +-#define IMX_CSPI3_BASE (0x50004000) +-#define UART4_BASE (0x50008000) +-#define UART3_BASE (0x5000C000) +-#define IMX_CSPI2_BASE (0x50010000) +-#define IMX_SSI2_BASE (0x50014000) +-#define IMX_ESAI_BASE (0x50018000) +-#define IMX_ATA_DMA_BASE (0x50020000) +-#define IMX_SIM1_BASE (0x50024000) +-#define IMX_SIM2_BASE (0x50028000) +-#define UART5_BASE (0x5002C000) +-#define IMX_TSC_BASE (0x50030000) +-#define IMX_SSI1_BASE (0x50034000) +-#define IMX_FEC_BASE (0x50038000) +-#define IMX_SPBA_CTRL_BASE (0x5003C000) +- +-/* AIPS 2 */ +-#define IMX_AIPS2_BASE (0x53F00000) +-#define IMX_CCM_BASE (0x53F80000) +-#define IMX_GPT4_BASE (0x53F84000) +-#define IMX_GPT3_BASE (0x53F88000) +-#define IMX_GPT2_BASE (0x53F8C000) +-#define IMX_GPT1_BASE (0x53F90000) +-#define IMX_EPIT1_BASE (0x53F94000) +-#define IMX_EPIT2_BASE (0x53F98000) +-#define IMX_GPIO4_BASE (0x53F9C000) +-#define IMX_PWM2_BASE (0x53FA0000) +-#define IMX_GPIO3_BASE (0x53FA4000) +-#define IMX_PWM3_BASE (0x53FA8000) +-#define IMX_SCC_BASE (0x53FAC000) +-#define IMX_SCM_BASE (0x53FAE000) +-#define IMX_SMN_BASE (0x53FAF000) +-#define IMX_RNGD_BASE (0x53FB0000) +-#define IMX_MMC_SDHC1_BASE (0x53FB4000) +-#define IMX_MMC_SDHC2_BASE (0x53FB8000) +-#define IMX_LCDC_BASE (0x53FBC000) +-#define IMX_SLCDC_BASE (0x53FC0000) +-#define IMX_PWM4_BASE (0x53FC8000) +-#define IMX_GPIO1_BASE (0x53FCC000) +-#define IMX_GPIO2_BASE (0x53FD0000) +-#define IMX_SDMA_BASE (0x53FD4000) +-#define IMX_WDT_BASE (0x53FDC000) +-#define WDOG1_BASE_ADDR IMX_WDT_BASE +-#define IMX_PWM1_BASE (0x53FE0000) +-#define IMX_RTIC_BASE (0x53FEC000) +-#define IMX_IIM_BASE (0x53FF0000) +-#define IIM_BASE_ADDR IMX_IIM_BASE +-#define IMX_USB_BASE (0x53FF4000) +-/* +- * This is in contradiction to the imx25 reference manual, which says that +- * port 1's registers start at 0x53FF4200. The correct base address for +- * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. +- */ +-#define IMX_USB_PORT_OFFSET 0x400 +-#define IMX_CSI_BASE (0x53FF8000) +-#define IMX_DRYICE_BASE (0x53FFC000) +- +-#define IMX_ARM926_ROMPATCH (0x60000000) +-#define IMX_ARM926_ASIC (0x68000000) +- +-/* 128K Internal Static RAM */ +-#define IMX_RAM_BASE (0x78000000) +-#define IMX_RAM_SIZE (128 * 1024) +- +-/* SDRAM BANKS */ +-#define IMX_SDRAM_BANK0_BASE (0x80000000) +-#define IMX_SDRAM_BANK1_BASE (0x90000000) +- +-#define IMX_WEIM_CS0 (0xA0000000) +-#define IMX_WEIM_CS1 (0xA8000000) +-#define IMX_WEIM_CS2 (0xB0000000) +-#define IMX_WEIM_CS3 (0xB2000000) +-#define IMX_WEIM_CS4 (0xB4000000) +-#define IMX_ESDRAMC_BASE (0xB8001000) +-#define IMX_WEIM_CTRL_BASE (0xB8002000) +-#define IMX_M3IF_CTRL_BASE (0xB8003000) +-#define IMX_EMI_CTRL_BASE (0xB8004000) +- +-/* NAND Flash Controller */ +-#define IMX_NFC_BASE (0xBB000000) +-#define NFC_BASE_ADDR IMX_NFC_BASE +- +-/* CCM bitfields */ +-#define CCM_PLL_MFI_SHIFT 10 +-#define CCM_PLL_MFI_MASK 0xf +-#define CCM_PLL_MFN_SHIFT 0 +-#define CCM_PLL_MFN_MASK 0x3ff +-#define CCM_PLL_MFD_SHIFT 16 +-#define CCM_PLL_MFD_MASK 0x3ff +-#define CCM_PLL_PD_SHIFT 26 +-#define CCM_PLL_PD_MASK 0xf +-#define CCM_CCTL_ARM_DIV_SHIFT 30 +-#define CCM_CCTL_ARM_DIV_MASK 3 +-#define CCM_CCTL_AHB_DIV_SHIFT 28 +-#define CCM_CCTL_AHB_DIV_MASK 3 +-#define CCM_CCTL_ARM_SRC (1 << 14) +-#define CCM_CGR1_GPT1 (1 << 19) +-#define CCM_PERCLK_REG(clk) (clk / 4) +-#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) +-#define CCM_PERCLK_MASK 0x3f +-#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +-#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +-#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +-#define CCM_CRDR_BT_UART_SRC_MASK 7 +- +-/* ESDRAM Controller register bitfields */ +-#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +-#define ESDCTL_BL (1 << 7) +-#define ESDCTL_FP (1 << 8) +-#define ESDCTL_PWDT(x) (((x) & 3) << 10) +-#define ESDCTL_SREFR(x) (((x) & 7) << 13) +-#define ESDCTL_DSIZ_16_UPPER (0 << 16) +-#define ESDCTL_DSIZ_16_LOWER (1 << 16) +-#define ESDCTL_DSIZ_32 (2 << 16) +-#define ESDCTL_COL8 (0 << 20) +-#define ESDCTL_COL9 (1 << 20) +-#define ESDCTL_COL10 (2 << 20) +-#define ESDCTL_ROW11 (0 << 24) +-#define ESDCTL_ROW12 (1 << 24) +-#define ESDCTL_ROW13 (2 << 24) +-#define ESDCTL_ROW14 (3 << 24) +-#define ESDCTL_ROW15 (4 << 24) +-#define ESDCTL_SP (1 << 27) +-#define ESDCTL_SMODE_NORMAL (0 << 28) +-#define ESDCTL_SMODE_PRECHARGE (1 << 28) +-#define ESDCTL_SMODE_AUTO_REF (2 << 28) +-#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +-#define ESDCTL_SMODE_MAN_REF (4 << 28) +-#define ESDCTL_SDE (1 << 31) +- +-#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +-#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +-#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +-#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +-#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +-#define ESDCFG_TWR (1 << 15) +-#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +-#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +-#define ESDCFG_TWTR (1 << 20) +-#define ESDCFG_TXP(x) (((x) & 0x3) << 21) +- +-#define ESDMISC_RST (1 << 1) +-#define ESDMISC_MDDREN (1 << 2) +-#define ESDMISC_MDDR_DL_RST (1 << 3) +-#define ESDMISC_MDDR_MDIS (1 << 4) +-#define ESDMISC_LHD (1 << 5) +-#define ESDMISC_MA10_SHARE (1 << 6) +-#define ESDMISC_SDRAM_RDY (1 << 31) +- +-/* GPT bits */ +-#define GPT_CTRL_SWR (1 << 15) /* Software reset */ +-#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ +-#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ +-#define GPT_CTRL_TEN 1 /* Timer enable */ +- +-/* WDOG enable */ +-#define WCR_WDE 0x04 +-#define WSR_UNLOCK1 0x5555 +-#define WSR_UNLOCK2 0xAAAA +- +-/* MAX bits */ +-#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) +- +-/* M3IF bits */ +-#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) +- +-/* WEIM bits */ +-/* 13 fields of the upper CS control register */ +-#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ +- cnc, wsc, ew, wws, edc) \ +- ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ +- (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ +- (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) +-/* 12 fields of the lower CS control register */ +-#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ +- csa, ebc, dsz, csn, psr, cre, wrap, csen) \ +- ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ +- (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ +- (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +-/* 14 fields of the additional CS control register */ +-#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ +- wwu, age, cnc2, fce) \ +- ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ +- (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ +- (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ +- (age) << 2 | (cnc2) << 1 | (fce) << 0) +- +-/* Names used in GPIO driver */ +-#define GPIO1_BASE_ADDR IMX_GPIO1_BASE +-#define GPIO2_BASE_ADDR IMX_GPIO2_BASE +-#define GPIO3_BASE_ADDR IMX_GPIO3_BASE +-#define GPIO4_BASE_ADDR IMX_GPIO4_BASE +- +-/* +- * CSPI register definitions +- */ +-#define MXC_SPI_BASE_ADDRESSES \ +- IMX_CSPI1_BASE, \ +- IMX_CSPI2_BASE, \ +- IMX_CSPI3_BASE +- +-#endif /* _IMX_REGS_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx25/iomux-mx25.h u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx25/iomux-mx25.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,537 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2013 ADVANSEE +- * Benoît Thébaudeau +- * +- * Based on mainline Linux i.MX iomux-mx25.h file: +- * Copyright (C) 2009 by Lothar Wassmann +- * +- * Based on Linux arch/arm/mach-mx25/mx25_pins.h: +- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. +- * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: +- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH +- */ +- +-#ifndef __IOMUX_MX25_H__ +-#define __IOMUX_MX25_H__ +- +-#include +- +-/* Pad control groupings */ +-#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP +-#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) +- +-/* +- * The naming convention for the pad modes is MX25_PAD___ +- * If or refers to a GPIO, it is named GPIO__ +- * See also iomux-v3.h +- */ +- +-/* PAD MUX ALT INPSE PATH PADCTRL */ +-enum { +- MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), +- +- MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), +- MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), +- +- MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), +- +- MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), +- +- MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), +- +- MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), +- MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), +- MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), +- MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), +- MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), +- MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), +- MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), +- MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), +- MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), +- +- MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), +- +- MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), +- +- MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), +- MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), +- MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), +- +- MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), +- +- MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), +- +- MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), +- +- MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), +- +- MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), +- +- MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), +- +- MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), +- MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), +- MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), +- MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), +- MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), +- MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), +- MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), +- MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), +- MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), +- MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), +- +- /* +- * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD +- * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM +- * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon +- * bug that configuring the SD1_CMD function doesn't enable the input path for +- * this pin. +- * This might have side effects for other hardware units that are connected to +- * that pin and use the respective function as input. +- */ +- MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), +- MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), +- MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), +- MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), +- MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), +- MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), +- MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), +- MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), +- MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), +- MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), +- MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), +- MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), +- MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), +- MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), +- MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), +- MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), +- MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), +- MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), +- MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), +- MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), +- MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), +- MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), +- MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), +- MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), +- MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), +- MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), +- MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), +- MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), +- MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), +- MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), +- +- MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), +- MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), +- +- MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), +- +- MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), +- +- MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), +- MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), +- MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), +- MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), +- MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), +- MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), +- MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), +- +- MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), +- MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), +-}; +- +-#endif /* __IOMUX_MX25_H__ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx25/macro.h u-boot/arch/arm/include/asm/arch-mx25/macro.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx25/macro.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx25/macro.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,90 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * Matthias Weisser +- * +- * (C) Copyright 2009 DENX Software Engineering +- * Author: John Rigby +- * +- * Common asm macros for imx25 +- */ +- +-#ifndef __ASM_ARM_ARCH_MACRO_H__ +-#define __ASM_ARM_ARCH_MACRO_H__ +-#ifdef __ASSEMBLY__ +- +-#include +-#include +-#include +- +-/* +- * AIPS setup - Only setup MPROTx registers. +- * The PACR default values are good. +- * +- * Default argument values: +- * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to +- * user-mode. +- */ +-.macro init_aips mpr=0x77777777 +- ldr r0, =IMX_AIPS1_BASE +- ldr r1, =\mpr +- str r1, [r0, #AIPS_MPR_0_7] +- str r1, [r0, #AIPS_MPR_8_15] +- ldr r2, =IMX_AIPS2_BASE +- str r1, [r2, #AIPS_MPR_0_7] +- str r1, [r2, #AIPS_MPR_8_15] +-.endm +- +-/* +- * MAX (Multi-Layer AHB Crossbar Switch) setup +- * +- * Default argument values: +- * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA +- * - SGPCR: always park on last master +- * - MGPCR: restore default values +- */ +-.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 +- ldr r0, =IMX_MAX_BASE +- ldr r1, =\mpr +- str r1, [r0, #MAX_MPR0] /* for S0 */ +- str r1, [r0, #MAX_MPR1] /* for S1 */ +- str r1, [r0, #MAX_MPR2] /* for S2 */ +- str r1, [r0, #MAX_MPR3] /* for S3 */ +- str r1, [r0, #MAX_MPR4] /* for S4 */ +- ldr r1, =\sgpcr +- str r1, [r0, #MAX_SGPCR0] /* for S0 */ +- str r1, [r0, #MAX_SGPCR1] /* for S1 */ +- str r1, [r0, #MAX_SGPCR2] /* for S2 */ +- str r1, [r0, #MAX_SGPCR3] /* for S3 */ +- str r1, [r0, #MAX_SGPCR4] /* for S4 */ +- ldr r1, =\mgpcr +- str r1, [r0, #MAX_MGPCR0] /* for M0 */ +- str r1, [r0, #MAX_MGPCR1] /* for M1 */ +- str r1, [r0, #MAX_MGPCR2] /* for M2 */ +- str r1, [r0, #MAX_MGPCR3] /* for M3 */ +- str r1, [r0, #MAX_MGPCR4] /* for M4 */ +-.endm +- +-/* +- * M3IF setup +- * +- * Default argument values: +- * - CTL: +- * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 +- * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 +- * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 +- * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 +- * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 +- * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 +- * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 +- * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 +- * ------------ +- * 0x00000001 +- */ +-.macro init_m3if ctl=0x00000001 +- /* M3IF Control Register (M3IFCTL) */ +- write32 IMX_M3IF_CTRL_BASE, \ctl +-.endm +- +-#endif /* __ASSEMBLY__ */ +-#endif /* __ASM_ARM_ARCH_MACRO_H__ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/clock.h u-boot/arch/arm/include/asm/arch-mx35/clock.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/clock.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/clock.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,67 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * Stefano Babic, DENX Software Engineering, sbabic@denx.de. +- */ +- +-#ifndef __ASM_ARCH_CLOCK_H +-#define __ASM_ARCH_CLOCK_H +- +-#ifdef CONFIG_MX35_HCLK_FREQ +-#define MXC_HCLK CONFIG_MX35_HCLK_FREQ +-#else +-#define MXC_HCLK 24000000 +-#endif +- +-#ifdef CONFIG_MX35_CLK32 +-#define MXC_CLK32 CONFIG_MX35_CLK32 +-#else +-#define MXC_CLK32 32768 +-#endif +- +-enum mxc_clock { +- MXC_ARM_CLK, +- MXC_AHB_CLK, +- MXC_IPG_CLK, +- MXC_IPG_PERCLK, +- MXC_UART_CLK, +- MXC_ESDHC1_CLK, +- MXC_ESDHC2_CLK, +- MXC_ESDHC3_CLK, +- MXC_USB_CLK, +- MXC_CSPI_CLK, +- MXC_FEC_CLK, +- MXC_I2C_CLK, +-}; +- +-enum mxc_main_clock { +- CPU_CLK, +- AHB_CLK, +- IPG_CLK, +- IPG_PER_CLK, +- NFC_CLK, +- USB_CLK, +- HSP_CLK, +-}; +- +-enum mxc_peri_clock { +- UART1_BAUD, +- UART2_BAUD, +- UART3_BAUD, +- SSI1_BAUD, +- SSI2_BAUD, +- CSI_BAUD, +- MSHC_CLK, +- ESDHC1_CLK, +- ESDHC2_CLK, +- ESDHC3_CLK, +- SPDIF_CLK, +- SPI1_CLK, +- SPI2_CLK, +-}; +- +-u32 imx_get_uartclk(void); +-u32 imx_get_fecclk(void); +-unsigned int mxc_get_clock(enum mxc_clock clk); +- +-#endif /* __ASM_ARCH_CLOCK_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/crm_regs.h u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/crm_regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,243 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright 2004-2009 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +-#define __CPU_ARM1136_MX35_CRM_REGS_H__ +- +-/* Register bit definitions */ +-#define MXC_CCM_CCMR_WFI (1 << 30) +-#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +-#define MXC_CCM_CCMR_VSTBY (1 << 28) +-#define MXC_CCM_CCMR_WBEN (1 << 27) +-#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +-#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +-#define MXC_CCM_CCMR_ROMW_OFFSET 18 +-#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +-#define MXC_CCM_CCMR_RAMW_OFFSET 16 +-#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) +-#define MXC_CCM_CCMR_LPM_OFFSET 14 +-#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +-#define MXC_CCM_CCMR_UPE (1 << 9) +-#define MXC_CCM_CCMR_MPE (1 << 3) +- +-#define MXC_CCM_PDR0_PER_SEL (1 << 26) +-#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +-#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +-#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +-#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +-#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +-#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +-#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +-#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) +-#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +-#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +-#define MXC_CCM_PDR0_AUTO_CON 0x1 +- +-#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +-#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +-#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +-#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +-#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) +- +-#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +-#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +-#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +-#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +-#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +-#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) +-#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +-#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +-#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +-#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +-#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +-#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) +- +-#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +-#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +-#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +-#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +-#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +-#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +-#define MXC_CCM_PDR3_UART_M_U (1 << 14) +-#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) +-#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +-#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) +- +-#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +-#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +-#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +-#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) +-#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +-#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) +-#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +-#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) +-#define MXC_CCM_PDR4_USB_M_U (1 << 9) +- +-/* Bit definitions for RCSR */ +-#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +-#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +-#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +-#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +-#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +-#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +-#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +-#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +-#define MXC_CCM_RCSR_NF16B (1 << 14) +-#define MXC_CCM_RCSR_NFC_4K (1 << 9) +-#define MXC_CCM_RCSR_NFC_FMS (1 << 8) +- +-/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +-#define MXC_CCM_PCTL_BRM 0x80000000 +-#define MXC_CCM_PCTL_PD_OFFSET 26 +-#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +-#define MXC_CCM_PCTL_MFD_OFFSET 16 +-#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +-#define MXC_CCM_PCTL_MFI_OFFSET 10 +-#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +-#define MXC_CCM_PCTL_MFN_OFFSET 0 +-#define MXC_CCM_PCTL_MFN_MASK 0x3FF +- +-/* Bit definitions for Audio clock mux register*/ +-#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +-#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +-#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +-#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +-#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +-#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) +- +-/* Bit definitions for Clock gating Register*/ +-#define MXC_CCM_CGR_CG_MASK 0x3 +-#define MXC_CCM_CGR_CG_OFF 0x0 +-#define MXC_CCM_CGR_CG_RUN_ON 0x1 +-#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +-#define MXC_CCM_CGR_CG_ON 0x3 +- +-#define MXC_CCM_CGR0_ASRC_OFFSET 0 +-#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +-#define MXC_CCM_CGR0_ATA_OFFSET 2 +-#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +-#define MXC_CCM_CGR0_CAN1_OFFSET 6 +-#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +-#define MXC_CCM_CGR0_CAN2_OFFSET 8 +-#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +-#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +-#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +-#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +-#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +-#define MXC_CCM_CGR0_ECT_OFFSET 14 +-#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +-#define MXC_CCM_CGR0_EDIO_OFFSET 16 +-#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) +-#define MXC_CCM_CGR0_EMI_OFFSET 18 +-#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +-#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +-#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +-#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +-#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +-#define MXC_CCM_CGR0_ESAI_OFFSET 24 +-#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +-#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +-#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +-#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +-#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +-#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +-#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) +- +-#define MXC_CCM_CGR1_FEC_OFFSET 0 +-#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +-#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +-#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +-#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +-#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +-#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +-#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +-#define MXC_CCM_CGR1_GPT_OFFSET 8 +-#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +-#define MXC_CCM_CGR1_I2C1_OFFSET 10 +-#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +-#define MXC_CCM_CGR1_I2C2_OFFSET 12 +-#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +-#define MXC_CCM_CGR1_I2C3_OFFSET 14 +-#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +-#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +-#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +-#define MXC_CCM_CGR1_IPU_OFFSET 18 +-#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +-#define MXC_CCM_CGR1_KPP_OFFSET 20 +-#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +-#define MXC_CCM_CGR1_MLB_OFFSET 22 +-#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +-#define MXC_CCM_CGR1_MSHC_OFFSET 24 +-#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +-#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +-#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +-#define MXC_CCM_CGR1_PWM_OFFSET 28 +-#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +-#define MXC_CCM_CGR1_RNGC_OFFSET 30 +-#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) +- +-#define MXC_CCM_CGR2_RTC_OFFSET 0 +-#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +-#define MXC_CCM_CGR2_RTIC_OFFSET 2 +-#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +-#define MXC_CCM_CGR2_SCC_OFFSET 4 +-#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +-#define MXC_CCM_CGR2_SDMA_OFFSET 6 +-#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +-#define MXC_CCM_CGR2_SPBA_OFFSET 8 +-#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +-#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +-#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +-#define MXC_CCM_CGR2_SSI1_OFFSET 12 +-#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +-#define MXC_CCM_CGR2_SSI2_OFFSET 14 +-#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +-#define MXC_CCM_CGR2_UART1_OFFSET 16 +-#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +-#define MXC_CCM_CGR2_UART2_OFFSET 18 +-#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +-#define MXC_CCM_CGR2_UART3_OFFSET 20 +-#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +-#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +-#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +-#define MXC_CCM_CGR2_WDOG_OFFSET 24 +-#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +-#define MXC_CCM_CGR2_MAX_OFFSET 26 +-#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +-#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +-#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +-#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) +- +-#define MXC_CCM_CGR3_CSI_OFFSET 0 +-#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +-#define MXC_CCM_CGR3_IIM_OFFSET 2 +-#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +-#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +-#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) +- +-#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +-#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +-#define MXC_CCM_COSR_CLKOEN (1 << 5) +-#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +-#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +-#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 +-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +-#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 +- +-#endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/gpio.h u-boot/arch/arm/include/asm/arch-mx35/gpio.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/gpio.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2011 +- * Stefano Babic, DENX Software Engineering, +- */ +- +- +-#ifndef __ASM_ARCH_MX35_GPIO_H +-#define __ASM_ARCH_MX35_GPIO_H +- +-#include +- +-#endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/imx-regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,356 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (c) 2007 Pengutronix, Sascha Hauer +- * +- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +- */ +- +-#ifndef __ASM_ARCH_MX35_H +-#define __ASM_ARCH_MX35_H +- +-#define ARCH_MXC +- +-/* +- * IRAM +- */ +-#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ +-#define IRAM_SIZE 0x00020000 /* 128 KB */ +- +-#define LOW_LEVEL_SRAM_STACK 0x1001E000 +- +-/* +- * AIPS 1 +- */ +-#define AIPS1_BASE_ADDR 0x43F00000 +-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +-#define MAX_BASE_ADDR 0x43F04000 +-#define EVTMON_BASE_ADDR 0x43F08000 +-#define CLKCTL_BASE_ADDR 0x43F0C000 +-#define I2C1_BASE_ADDR 0x43F80000 +-#define I2C3_BASE_ADDR 0x43F84000 +-#define ATA_BASE_ADDR 0x43F8C000 +-#define UART1_BASE 0x43F90000 +-#define UART2_BASE 0x43F94000 +-#define I2C2_BASE_ADDR 0x43F98000 +-#define CSPI1_BASE_ADDR 0x43FA4000 +-#define IOMUXC_BASE_ADDR 0x43FAC000 +- +-/* +- * SPBA +- */ +-#define SPBA_BASE_ADDR 0x50000000 +-#define UART3_BASE 0x5000C000 +-#define CSPI2_BASE_ADDR 0x50010000 +-#define ATA_DMA_BASE_ADDR 0x50020000 +-#define FEC_BASE_ADDR 0x50038000 +-#define SPBA_CTRL_BASE_ADDR 0x5003C000 +- +-/* +- * AIPS 2 +- */ +-#define AIPS2_BASE_ADDR 0x53F00000 +-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +-#define CCM_BASE_ADDR 0x53F80000 +-#define GPT1_BASE_ADDR 0x53F90000 +-#define EPIT1_BASE_ADDR 0x53F94000 +-#define EPIT2_BASE_ADDR 0x53F98000 +-#define GPIO3_BASE_ADDR 0x53FA4000 +-#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +-#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +-#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +-#define IPU_CTRL_BASE_ADDR 0x53FC0000 +-#define GPIO1_BASE_ADDR 0x53FCC000 +-#define GPIO2_BASE_ADDR 0x53FD0000 +-#define SDMA_BASE_ADDR 0x53FD4000 +-#define RTC_BASE_ADDR 0x53FD8000 +-#define WDOG1_BASE_ADDR 0x53FDC000 +-#define PWM_BASE_ADDR 0x53FE0000 +-#define RTIC_BASE_ADDR 0x53FEC000 +-#define IIM_BASE_ADDR 0x53FF0000 +-#define IMX_USB_BASE 0x53FF4000 +-#define IMX_USB_PORT_OFFSET 0x400 +- +-#define IMX_CCM_BASE CCM_BASE_ADDR +- +-/* +- * ROMPATCH and AVIC +- */ +-#define ROMPATCH_BASE_ADDR 0x60000000 +-#define AVIC_BASE_ADDR 0x68000000 +- +-/* +- * NAND, SDRAM, WEIM, M3IF, EMI controllers +- */ +-#define EXT_MEM_CTRL_BASE 0xB8000000 +-#define ESDCTL_BASE_ADDR 0xB8001000 +-#define WEIM_BASE_ADDR 0xB8002000 +-#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +-#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +-#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +-#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +-#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +-#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +-#define M3IF_BASE_ADDR 0xB8003000 +-#define EMI_BASE_ADDR 0xB8004000 +- +-#define NFC_BASE_ADDR 0xBB000000 +- +-/* +- * Memory regions and CS +- */ +-#define IPU_MEM_BASE_ADDR 0x70000000 +-#define CSD0_BASE_ADDR 0x80000000 +-#define CSD1_BASE_ADDR 0x90000000 +-#define CS0_BASE_ADDR 0xA0000000 +-#define CS1_BASE_ADDR 0xA8000000 +-#define CS2_BASE_ADDR 0xB0000000 +-#define CS3_BASE_ADDR 0xB2000000 +-#define CS4_BASE_ADDR 0xB4000000 +-#define CS5_BASE_ADDR 0xB6000000 +- +-/* +- * IRQ Controller Register Definitions. +- */ +-#define AVIC_NIMASK 0x04 +-#define AVIC_INTTYPEH 0x18 +-#define AVIC_INTTYPEL 0x1C +- +-/* L210 */ +-#define L2CC_BASE_ADDR 0x30000000 +-#define L2_CACHE_LINE_SIZE 32 +-#define L2_CACHE_CTL_REG 0x100 +-#define L2_CACHE_AUX_CTL_REG 0x104 +-#define L2_CACHE_SYNC_REG 0x730 +-#define L2_CACHE_INV_LINE_REG 0x770 +-#define L2_CACHE_INV_WAY_REG 0x77C +-#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +-#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +-#define L2_CACHE_DBG_CTL_REG 0xF40 +- +-#define CLKMODE_AUTO 0 +-#define CLKMODE_CONSUMER 1 +- +-#define PLL_PD(x) (((x) & 0xf) << 26) +-#define PLL_MFD(x) (((x) & 0x3ff) << 16) +-#define PLL_MFI(x) (((x) & 0xf) << 10) +-#define PLL_MFN(x) (((x) & 0x3ff) << 0) +- +-#define _PLL_BRM(x) ((x) << 31) +-#define _PLL_PD(x) (((x) - 1) << 26) +-#define _PLL_MFD(x) (((x) - 1) << 16) +-#define _PLL_MFI(x) ((x) << 10) +-#define _PLL_MFN(x) (x) +-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ +- (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ +- _PLL_MFN(mfn)) +- +-#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) +- +-#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +-#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +-#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) +- +-#define IIM_SREV 0x24 +-#define ROMPATCH_REV 0x40 +- +-#define IPU_CONF IPU_CTRL_BASE_ADDR +- +-#define IPU_CONF_PXL_ENDIAN (1<<8) +-#define IPU_CONF_DU_EN (1<<7) +-#define IPU_CONF_DI_EN (1<<6) +-#define IPU_CONF_ADC_EN (1<<5) +-#define IPU_CONF_SDC_EN (1<<4) +-#define IPU_CONF_PF_EN (1<<3) +-#define IPU_CONF_ROT_EN (1<<2) +-#define IPU_CONF_IC_EN (1<<1) +-#define IPU_CONF_CSI_EN (1<<0) +- +-/* +- * CSPI register definitions +- */ +-#define MXC_SPI_BASE_ADDRESSES \ +- 0x43fa4000, \ +- 0x50010000, +- +-#define GPIO_PORT_NUM 3 +-#define GPIO_NUM_PIN 32 +- +-#define CHIP_REV_1_0 0x10 +-#define CHIP_REV_2_0 0x20 +- +-#define BOARD_REV_1_0 0x0 +-#define BOARD_REV_2_0 0x1 +- +-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +-#include +- +-/* Clock Control Module (CCM) registers */ +-struct ccm_regs { +- u32 ccmr; /* Control */ +- u32 pdr0; /* Post divider 0 */ +- u32 pdr1; /* Post divider 1 */ +- u32 pdr2; /* Post divider 2 */ +- u32 pdr3; /* Post divider 3 */ +- u32 pdr4; /* Post divider 4 */ +- u32 rcsr; /* CCM Status */ +- u32 mpctl; /* Core PLL Control */ +- u32 ppctl; /* Peripheral PLL Control */ +- u32 acmr; /* Audio clock mux */ +- u32 cosr; /* Clock out source */ +- u32 cgr0; /* Clock Gating Control 0 */ +- u32 cgr1; /* Clock Gating Control 1 */ +- u32 cgr2; /* Clock Gating Control 2 */ +- u32 cgr3; /* Clock Gating Control 3 */ +- u32 reserved; +- u32 dcvr0; /* DPTC Comparator 0 */ +- u32 dcvr1; /* DPTC Comparator 0 */ +- u32 dcvr2; /* DPTC Comparator 0 */ +- u32 dcvr3; /* DPTC Comparator 0 */ +- u32 ltr0; /* Load Tracking 0 */ +- u32 ltr1; /* Load Tracking 1 */ +- u32 ltr2; /* Load Tracking 2 */ +- u32 ltr3; /* Load Tracking 3 */ +- u32 ltbr0; /* Load Tracking Buffer 0 */ +-}; +- +-/* IIM control registers */ +-struct iim_regs { +- u32 iim_stat; +- u32 iim_statm; +- u32 iim_err; +- u32 iim_emask; +- u32 iim_fctl; +- u32 iim_ua; +- u32 iim_la; +- u32 iim_sdat; +- u32 iim_prev; +- u32 iim_srev; +- u32 iim_prg_p; +- u32 iim_scs0; +- u32 iim_scs1; +- u32 iim_scs2; +- u32 iim_scs3; +- u32 res1[0x1f1]; +- struct fuse_bank { +- u32 fuse_regs[0x20]; +- u32 fuse_rsvd[0xe0]; +- } bank[3]; +-}; +- +-struct fuse_bank0_regs { +- u32 fuse0_7[8]; +- u32 uid[8]; +- u32 fuse16_31[0x10]; +-}; +- +-struct fuse_bank1_regs { +- u32 fuse0_21[0x16]; +- u32 usr; +- u32 fuse23_31[9]; +-}; +- +-/* General Purpose Timer (GPT) registers */ +-struct gpt_regs { +- u32 ctrl; /* control */ +- u32 pre; /* prescaler */ +- u32 stat; /* status */ +- u32 intr; /* interrupt */ +- u32 cmp[3]; /* output compare 1-3 */ +- u32 capt[2]; /* input capture 1-2 */ +- u32 counter; /* counter */ +-}; +- +-struct esdc_regs { +- u32 esdctl0; +- u32 esdcfg0; +- u32 esdctl1; +- u32 esdcfg1; +- u32 esdmisc; +- u32 reserved[4]; +- u32 esdcdly[5]; +- u32 esdcdlyl; +-}; +- +-#define ESDC_MISC_RST (1 << 1) +-#define ESDC_MISC_MDDR_EN (1 << 2) +-#define ESDC_MISC_MDDR_DL_RST (1 << 3) +-#define ESDC_MISC_DDR_EN (1 << 8) +-#define ESDC_MISC_DDR2_EN (1 << 9) +- +-/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +-struct max_regs { +- u32 mpr0; +- u32 pad00[3]; +- u32 sgpcr0; +- u32 pad01[59]; +- u32 mpr1; +- u32 pad02[3]; +- u32 sgpcr1; +- u32 pad03[59]; +- u32 mpr2; +- u32 pad04[3]; +- u32 sgpcr2; +- u32 pad05[59]; +- u32 mpr3; +- u32 pad06[3]; +- u32 sgpcr3; +- u32 pad07[59]; +- u32 mpr4; +- u32 pad08[3]; +- u32 sgpcr4; +- u32 pad09[251]; +- u32 mgpcr0; +- u32 pad10[63]; +- u32 mgpcr1; +- u32 pad11[63]; +- u32 mgpcr2; +- u32 pad12[63]; +- u32 mgpcr3; +- u32 pad13[63]; +- u32 mgpcr4; +- u32 pad14[63]; +- u32 mgpcr5; +-}; +- +-/* AHB <-> IP-Bus Interface (AIPS) */ +-struct aips_regs { +- u32 mpr_0_7; +- u32 mpr_8_15; +- u32 pad0[6]; +- u32 pacr_0_7; +- u32 pacr_8_15; +- u32 pacr_16_23; +- u32 pacr_24_31; +- u32 pad1[4]; +- u32 opacr_0_7; +- u32 opacr_8_15; +- u32 opacr_16_23; +- u32 opacr_24_31; +- u32 opacr_32_39; +-}; +- +-/* +- * NFMS bit in RCSR register for pagesize of nandflash +- */ +-#define NFMS_BIT 8 +-#define NFMS_NF_DWIDTH 14 +-#define NFMS_NF_PG_SZ 8 +- +-#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +- +-#endif +- +-/* +- * Generic timer support +- */ +-#ifdef CONFIG_MX35_CLK32 +-#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 +-#else +-#define CONFIG_SYS_TIMER_RATE 32768 +-#endif +- +-#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) +- +-#endif /* __ASM_ARCH_MX35_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/iomux-mx35.h u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/iomux-mx35.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,1259 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2013 ADVANSEE +- * Benoît Thébaudeau +- * +- * Based on mainline Linux i.MX iomux-mx35.h file: +- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH +- */ +- +-#ifndef __IOMUX_MX35_H__ +-#define __IOMUX_MX35_H__ +- +-#include +- +-/* +- * The naming convention for the pad modes is MX35_PAD___ +- * If or refers to a GPIO, it is named GPIO_ +- * See also iomux-v3.h +- */ +- +-/* PAD MUX ALT INPSE PATH PADCTRL */ +-enum { +- MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL), +- MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL), +- MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL), +- +- MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL), +- MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL), +- +- MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL), +- MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL), +- +- MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL), +- +- MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL), +- MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL), +- +- MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL), +- MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL), +- MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL), +- +- MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL), +- +- MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL), +- MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL), +- MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL), +- MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL), +- MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL), +- MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL), +- MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL), +- MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL), +- MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL), +- MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL), +- MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL), +- MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL), +- MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL), +- MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL), +- MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL), +- MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL), +- +- MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL), +- MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL), +- MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL), +- MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL), +- MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL), +- MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL), +- MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL), +- MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL), +- MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL), +- MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL), +- MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL), +- MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL), +- MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL), +- MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL), +- MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL), +- MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL), +- MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL), +- MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL), +- MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL), +- MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL), +- MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL), +- MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL), +- +- MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL), +- MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL), +- MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL), +- +- MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL), +- MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL), +- MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL), +- MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL), +- +- MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL), +- MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL), +- MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL), +- +- MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL), +- MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL), +- MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL), +- +- MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL), +- MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL), +- MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL), +- +- MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL), +- MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL), +- MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL), +- MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL), +- +- MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL), +- MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL), +- MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL), +- MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL), +- MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL), +- MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL), +- MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL), +- MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL), +- MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL), +- MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL), +- MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL), +- MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL), +- MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL), +- MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL), +- MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL), +- MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL), +- MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL), +- MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL), +- MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL), +- MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL), +- MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL), +- MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL), +- +- MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL), +- MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL), +- MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL), +- MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL), +- MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL), +- MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL), +- MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL), +- MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL), +- MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL), +- +- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL), +- MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL), +- MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL), +- MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL), +- MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL), +- MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL), +- MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL), +- MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL), +- MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL), +- MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL), +- MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL), +- MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL), +- MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL), +- MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL), +- MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL), +- MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL), +- MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL), +- MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL), +- MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL), +- MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL), +- MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL), +- MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL), +- MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL), +- MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL), +- MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL), +- MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL), +- MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL), +- MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL), +- MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL), +- MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL), +- MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL), +- MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL), +- MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL), +- MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL), +- MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL), +- MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL), +- MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL), +- MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL), +- +- MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL), +- MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL), +- +- MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL), +- +- MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL), +- +- MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL), +- MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL), +- +- MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL), +- MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL), +- MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL), +- MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL), +- MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL), +- +- MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL), +- +- MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL), +- MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +- +- MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL), +-}; +- +-#endif /* __IOMUX_MX35_H__ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/lowlevel_macro.S u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/lowlevel_macro.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1,125 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2007, Guennadi Liakhovetski +- * +- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. +- */ +- +-#include +-#include +-#include +- +-/* +- * AIPS setup - Only setup MPROTx registers. +- * The PACR default values are good. +- * +- * Default argument values: +- * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to +- * user-mode. +- * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for +- * SDMA to access them. +- */ +-.macro init_aips mpr=0x77777777, opacr=0x00000000 +- ldr r0, =AIPS1_BASE_ADDR +- ldr r1, =\mpr +- str r1, [r0, #AIPS_MPR_0_7] +- str r1, [r0, #AIPS_MPR_8_15] +- ldr r2, =AIPS2_BASE_ADDR +- str r1, [r2, #AIPS_MPR_0_7] +- str r1, [r2, #AIPS_MPR_8_15] +- +- /* Did not change the AIPS control registers access type. */ +- ldr r1, =\opacr +- str r1, [r0, #AIPS_OPACR_0_7] +- str r1, [r0, #AIPS_OPACR_8_15] +- str r1, [r0, #AIPS_OPACR_16_23] +- str r1, [r0, #AIPS_OPACR_24_31] +- str r1, [r0, #AIPS_OPACR_32_39] +- str r1, [r2, #AIPS_OPACR_0_7] +- str r1, [r2, #AIPS_OPACR_8_15] +- str r1, [r2, #AIPS_OPACR_16_23] +- str r1, [r2, #AIPS_OPACR_24_31] +- str r1, [r2, #AIPS_OPACR_32_39] +-.endm +- +-/* +- * MAX (Multi-Layer AHB Crossbar Switch) setup +- * +- * Default argument values: +- * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 +- * - SGPCR: always park on last master +- * - MGPCR: restore default values +- */ +-.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 +- ldr r0, =MAX_BASE_ADDR +- ldr r1, =\mpr +- str r1, [r0, #MAX_MPR0] /* for S0 */ +- str r1, [r0, #MAX_MPR1] /* for S1 */ +- str r1, [r0, #MAX_MPR2] /* for S2 */ +- str r1, [r0, #MAX_MPR3] /* for S3 */ +- str r1, [r0, #MAX_MPR4] /* for S4 */ +- ldr r1, =\sgpcr +- str r1, [r0, #MAX_SGPCR0] /* for S0 */ +- str r1, [r0, #MAX_SGPCR1] /* for S1 */ +- str r1, [r0, #MAX_SGPCR2] /* for S2 */ +- str r1, [r0, #MAX_SGPCR3] /* for S3 */ +- str r1, [r0, #MAX_SGPCR4] /* for S4 */ +- ldr r1, =\mgpcr +- str r1, [r0, #MAX_MGPCR0] /* for M0 */ +- str r1, [r0, #MAX_MGPCR1] /* for M1 */ +- str r1, [r0, #MAX_MGPCR2] /* for M2 */ +- str r1, [r0, #MAX_MGPCR3] /* for M3 */ +- str r1, [r0, #MAX_MGPCR4] /* for M4 */ +- str r1, [r0, #MAX_MGPCR5] /* for M5 */ +-.endm +- +-/* +- * M3IF setup +- * +- * Default argument values: +- * - CTL: +- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 +- * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 +- * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 +- * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 +- * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 +- * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 +- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 +- * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 +- * ------------ +- * 0x00000040 +- */ +-.macro init_m3if ctl=0x00000040 +- /* M3IF Control Register (M3IFCTL) */ +- write32 M3IF_BASE_ADDR, \ctl +-.endm +- +-.macro core_init +- mrc p15, 0, r1, c1, c0, 0 +- +- /* Set branch prediction enable */ +- mrc p15, 0, r0, c1, c0, 1 +- orr r0, r0, #7 +- mcr p15, 0, r0, c1, c0, 1 +- orr r1, r1, #1 << 11 +- +- /* Set unaligned access enable */ +- orr r1, r1, #1 << 22 +- +- /* Set low int latency enable */ +- orr r1, r1, #1 << 21 +- +- mcr p15, 0, r1, c1, c0, 0 +- +- mov r0, #0 +- +- mcr p15, 0, r0, c15, c2, 4 +- +- mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ +- mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ +- mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ +- +- /* Setup the Peripheral Port Memory Remap Register */ +- ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ +- mcr p15, 0, r0, c15, c2, 4 +-.endm +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/mmc_host_def.h u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/mmc_host_def.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,14 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * (C) Copyright 2008 +- * Texas Instruments, +- * Syed Mohammed Khasim +- */ +- +-#ifndef MMC_HOST_DEF_H +-#define MMC_HOST_DEF_H +- +-/* Driver definitions */ +-#define MMCSD_SECTOR_SIZE 512 +- +-#endif /* MMC_HOST_DEF_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx35/sys_proto.h u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx35/sys_proto.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,15 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * Stefano Babic, DENX Software Engineering, sbabic@denx.de. +- */ +- +-#ifndef _MX35_SYS_PROTO_H_ +-#define _MX35_SYS_PROTO_H_ +- +-#include +- +-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row, +- u32 col, u32 dsize, u32 refresh); +- +-#endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx5/imx-regs.h u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h +--- u-boot-2021.10/arch/arm/include/asm/arch-mx5/imx-regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h 2021-11-01 17:10:13.706289597 +0100 +@@ -43,7 +43,7 @@ + #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) + #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) + #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) +-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) ++#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) + #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) + #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) + #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +@@ -97,7 +97,7 @@ + #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) + #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) + #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) ++#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) + #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) + #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) + #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx6/mx6_plugin.S u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S +--- u-boot-2021.10/arch/arm/include/asm/arch-mx6/mx6_plugin.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx6/mx6_plugin.S 2021-11-01 17:10:13.706289597 +0100 +@@ -7,10 +7,10 @@ + + #ifdef CONFIG_ROM_UNIFIED_SECTIONS + #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +-#define ROM_VERSION_OFFSET 0x80 ++#define ROM_VERSION_OFFSET 0x80 + #else + #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 +-#define ROM_VERSION_OFFSET 0x48 ++#define ROM_VERSION_OFFSET 0x48 + #endif + #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 + #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx7/mx7_plugin.S u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S +--- u-boot-2021.10/arch/arm/include/asm/arch-mx7/mx7_plugin.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx7/mx7_plugin.S 2021-11-01 17:10:13.712955899 +0100 +@@ -6,7 +6,7 @@ + #include + + #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +-#define ROM_VERSION_OFFSET 0x80 ++#define ROM_VERSION_OFFSET 0x80 + #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + + plugin_start: +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S +--- u-boot-2021.10/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S 2021-11-01 17:10:13.712955899 +0100 +@@ -6,7 +6,7 @@ + #include + + #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 +-#define ROM_VERSION_OFFSET 0x80 ++#define ROM_VERSION_OFFSET 0x80 + #define ROM_API_HWCNFG_SETUP_OFFSET 0x08 + + plugin_start: +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-rockchip/cru_rk3368.h u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +--- u-boot-2021.10/arch/arm/include/asm/arch-rockchip/cru_rk3368.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h 2021-11-01 17:10:13.729621654 +0100 +@@ -126,17 +126,17 @@ + /* GLB_RST_CON */ + PMU_GLB_SRST_CTRL_SHIFT = 2, + PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), +- PMU_RST_BY_FST_GLB_SRST = 0, +- PMU_RST_BY_SND_GLB_SRST = 1, ++ PMU_RST_BY_FST_GLB_SRST = 0, ++ PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_DISABLE = 2, + WDT_GLB_SRST_CTRL_SHIFT = 1, + WDT_GLB_SRST_CTRL_MASK = BIT(1), +- WDT_TRIGGER_SND_GLB_SRST = 0, +- WDT_TRIGGER_FST_GLB_SRST = 1, +- TSADC_GLB_SRST_CTRL_SHIFT = 0, +- TSADC_GLB_SRST_CTRL_MASK = BIT(0), +- TSADC_TRIGGER_SND_GLB_SRST = 0, +- TSADC_TRIGGER_FST_GLB_SRST = 1, ++ WDT_TRIGGER_SND_GLB_SRST = 0, ++ WDT_TRIGGER_FST_GLB_SRST = 1, ++ TSADC_GLB_SRST_CTRL_SHIFT = 0, ++ TSADC_GLB_SRST_CTRL_MASK = BIT(0), ++ TSADC_TRIGGER_SND_GLB_SRST = 0, ++ TSADC_TRIGGER_FST_GLB_SRST = 1, + + }; + #endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-rockchip/f_rockusb.h u-boot/arch/arm/include/asm/arch-rockchip/f_rockusb.h +--- u-boot-2021.10/arch/arm/include/asm/arch-rockchip/f_rockusb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-rockchip/f_rockusb.h 2021-11-01 17:10:13.729621654 +0100 +@@ -133,4 +133,3 @@ + /* init rockusb device, tell rockusb which device you want to read/write*/ + void rockusb_dev_init(char *dev_type, int dev_index); + #endif /* _F_ROCKUSB_H_ */ +- +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-stm32/stm32f.h u-boot/arch/arm/include/asm/arch-stm32/stm32f.h +--- u-boot-2021.10/arch/arm/include/asm/arch-stm32/stm32f.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-stm32/stm32f.h 2021-11-01 17:10:13.732954806 +0100 +@@ -18,4 +18,3 @@ + void stm32_flash_latency_cfg(int latency); + + #endif /* _ASM_ARCH_STM32F_H */ +- +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-stv0991/stv0991_defs.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h +--- u-boot-2021.10/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 2021-11-01 17:10:13.732954806 +0100 +@@ -12,4 +12,3 @@ + extern int clock_setup(enum periph_clock); + + #endif +- +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-sunxi/ccu.h u-boot/arch/arm/include/asm/arch-sunxi/ccu.h +--- u-boot-2021.10/arch/arm/include/asm/arch-sunxi/ccu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-sunxi/ccu.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2018 Amarula Solutions. +- * Author: Jagan Teki +- */ +- +-#ifndef _ASM_ARCH_CCU_H +-#define _ASM_ARCH_CCU_H +- +-#ifndef __ASSEMBLY__ +-#include +-#endif +- +-/** +- * enum ccu_flags - ccu clock/reset flags +- * +- * @CCU_CLK_F_IS_VALID: is given clock gate is valid? +- * @CCU_RST_F_IS_VALID: is given reset control is valid? +- */ +-enum ccu_flags { +- CCU_CLK_F_IS_VALID = BIT(0), +- CCU_RST_F_IS_VALID = BIT(1), +-}; +- +-/** +- * struct ccu_clk_gate - ccu clock gate +- * @off: gate offset +- * @bit: gate bit +- * @flags: ccu clock gate flags +- */ +-struct ccu_clk_gate { +- u16 off; +- u32 bit; +- enum ccu_flags flags; +-}; +- +-#define GATE(_off, _bit) { \ +- .off = _off, \ +- .bit = _bit, \ +- .flags = CCU_CLK_F_IS_VALID, \ +-} +- +-/** +- * struct ccu_reset - ccu reset +- * @off: reset offset +- * @bit: reset bit +- * @flags: ccu reset control flags +- */ +-struct ccu_reset { +- u16 off; +- u32 bit; +- enum ccu_flags flags; +-}; +- +-#define RESET(_off, _bit) { \ +- .off = _off, \ +- .bit = _bit, \ +- .flags = CCU_RST_F_IS_VALID, \ +-} +- +-/** +- * struct ccu_desc - clock control unit descriptor +- * +- * @gates: clock gates +- * @resets: reset unit +- */ +-struct ccu_desc { +- const struct ccu_clk_gate *gates; +- const struct ccu_reset *resets; +-}; +- +-/** +- * struct ccu_priv - sunxi clock control unit +- * +- * @base: base address +- * @desc: ccu descriptor +- */ +-struct ccu_priv { +- void *base; +- const struct ccu_desc *desc; +-}; +- +-/** +- * sunxi_clk_probe - common sunxi clock probe +- * @dev: clock device +- */ +-int sunxi_clk_probe(struct udevice *dev); +- +-extern struct clk_ops sunxi_clk_ops; +- +-/** +- * sunxi_reset_bind() - reset binding +- * +- * @dev: reset device +- * @count: reset count +- * @return 0 success, or error value +- */ +-int sunxi_reset_bind(struct udevice *dev, ulong count); +- +-#endif /* _ASM_ARCH_CCU_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-sunxi/gpio.h u-boot/arch/arm/include/asm/arch-sunxi/gpio.h +--- u-boot-2021.10/arch/arm/include/asm/arch-sunxi/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-sunxi/gpio.h 2021-11-01 17:10:13.732954806 +0100 +@@ -9,7 +9,9 @@ + #define _SUNXI_GPIO_H + + #include ++#if 0 + #include ++#endif + + /* + * sunxi has 9 banks of gpio, they are: +@@ -55,30 +57,36 @@ + struct sunxi_gpio { + u32 cfg[4]; + u32 dat; +- u32 drv[2]; ++ u32 drv[4]; + u32 pull[2]; ++ u32 reserved; + }; + + /* gpio interrupt control */ + struct sunxi_gpio_int { +- u32 cfg[3]; ++ u32 cfg[4]; + u32 ctl; + u32 sta; + u32 deb; /* interrupt debounce */ ++ u32 reserved; + }; + ++#if 0 + struct sunxi_gpio_reg { + struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; + u8 res[0xbc]; + struct sunxi_gpio_int gpio_int; + }; ++#endif + + #define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 + #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + ++#if 0 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) ++#endif + + #define GPIO_BANK(pin) ((pin) >> 5) + #define GPIO_NUM(pin) ((pin) & 0x1f) +@@ -93,20 +101,10 @@ + #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + + /* GPIO bank sizes */ +-#define SUNXI_GPIO_A_NR 32 +-#define SUNXI_GPIO_B_NR 32 +-#define SUNXI_GPIO_C_NR 32 +-#define SUNXI_GPIO_D_NR 32 +-#define SUNXI_GPIO_E_NR 32 +-#define SUNXI_GPIO_F_NR 32 +-#define SUNXI_GPIO_G_NR 32 +-#define SUNXI_GPIO_H_NR 32 +-#define SUNXI_GPIO_I_NR 32 +-#define SUNXI_GPIO_L_NR 32 +-#define SUNXI_GPIO_M_NR 32 ++#define SUNXI_GPIOS_PER_BANK 32 + + #define SUNXI_GPIO_NEXT(__gpio) \ +- ((__gpio##_START) + (__gpio##_NR) + 0) ++ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) + + enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, +@@ -121,7 +119,6 @@ + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), +- SUNXI_GPIO_AXP0_START = 1024, + }; + + /* SUNXI GPIO number definitions */ +@@ -138,18 +135,11 @@ + #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) + #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) + +-#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) +- + /* GPIO pin function config */ + #define SUNXI_GPIO_INPUT 0 + #define SUNXI_GPIO_OUTPUT 1 + #define SUNXI_GPIO_DISABLE 7 + +-#define SUNXI_GPA_EMAC 2 +-#define SUN6I_GPA_GMAC 2 +-#define SUN7I_GPA_GMAC 5 +-#define SUN6I_GPA_SDC2 5 +-#define SUN6I_GPA_SDC3 4 + #define SUN8I_H3_GPA_UART0 2 + + #define SUN4I_GPB_PWM 2 +@@ -173,12 +163,9 @@ + #define SUN6I_GPC_SDC3 4 + #define SUN50I_GPC_SPI0 4 + +-#define SUN8I_GPD_SDC1 3 + #define SUNXI_GPD_LCD0 2 + #define SUNXI_GPD_LVDS0 3 +-#define SUNXI_GPD_PWM 2 + +-#define SUN5I_GPE_SDC2 3 + #define SUN8I_GPE_TWI2 3 + #define SUN50I_GPE_TWI2 3 + +@@ -230,26 +217,19 @@ + #define SUNXI_GPIO_PULL_UP 1 + #define SUNXI_GPIO_PULL_DOWN 2 + +-/* Virtual AXP0 GPIOs */ +-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" +-#define SUNXI_GPIO_AXP0_VBUS_DETECT 4 +-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 +-#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 +- + void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); + void sunxi_gpio_set_cfgpin(u32 pin, u32 val); + int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); + int sunxi_gpio_get_cfgpin(u32 pin); +-int sunxi_gpio_set_drv(u32 pin, u32 val); +-int sunxi_gpio_set_pull(u32 pin, u32 val); +-int sunxi_name_to_gpio_bank(const char *name); ++void sunxi_gpio_set_drv(u32 pin, u32 val); ++void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); ++void sunxi_gpio_set_pull(u32 pin, u32 val); ++void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); + int sunxi_name_to_gpio(const char *name); +-#define name_to_gpio(name) sunxi_name_to_gpio(name) + +-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +-int axp_gpio_init(void); +-#else +-static inline int axp_gpio_init(void) { return 0; } +-#endif ++struct sunxi_gpio_plat { ++ struct sunxi_gpio *regs; ++ char bank_name[3]; ++}; + + #endif /* _SUNXI_GPIO_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-sunxi/mmc.h u-boot/arch/arm/include/asm/arch-sunxi/mmc.h +--- u-boot-2021.10/arch/arm/include/asm/arch-sunxi/mmc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-sunxi/mmc.h 2021-11-01 17:10:13.736287957 +0100 +@@ -1,139 +1,8 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2007-2011 +- * Allwinner Technology Co., Ltd. +- * Aaron +- * +- * MMC register definition for allwinner sunxi platform. +- */ + +-#ifndef _SUNXI_MMC_H +-#define _SUNXI_MMC_H +- +-#include +- +-struct sunxi_mmc { +- u32 gctrl; /* 0x00 global control */ +- u32 clkcr; /* 0x04 clock control */ +- u32 timeout; /* 0x08 time out */ +- u32 width; /* 0x0c bus width */ +- u32 blksz; /* 0x10 block size */ +- u32 bytecnt; /* 0x14 byte count */ +- u32 cmd; /* 0x18 command */ +- u32 arg; /* 0x1c argument */ +- u32 resp0; /* 0x20 response 0 */ +- u32 resp1; /* 0x24 response 1 */ +- u32 resp2; /* 0x28 response 2 */ +- u32 resp3; /* 0x2c response 3 */ +- u32 imask; /* 0x30 interrupt mask */ +- u32 mint; /* 0x34 masked interrupt status */ +- u32 rint; /* 0x38 raw interrupt status */ +- u32 status; /* 0x3c status */ +- u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ +- u32 funcsel; /* 0x44 function select */ +- u32 cbcr; /* 0x48 CIU byte count */ +- u32 bbcr; /* 0x4c BIU byte count */ +- u32 dbgc; /* 0x50 debug enable */ +- u32 res0; /* 0x54 reserved */ +- u32 a12a; /* 0x58 Auto command 12 argument */ +- u32 ntsr; /* 0x5c New timing set register */ +- u32 res1[8]; +- u32 dmac; /* 0x80 internal DMA control */ +- u32 dlba; /* 0x84 internal DMA descr list base address */ +- u32 idst; /* 0x88 internal DMA status */ +- u32 idie; /* 0x8c internal DMA interrupt enable */ +- u32 chda; /* 0x90 */ +- u32 cbda; /* 0x94 */ +- u32 res2[26]; +-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +- u32 res3[17]; +- u32 samp_dl; +- u32 res4[46]; +-#endif +- u32 fifo; /* 0x100 / 0x200 FIFO access address */ +-}; +- +-#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +-#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +-#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) +- +-#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +-#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +-#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +-#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ +- SUNXI_MMC_GCTRL_FIFO_RESET|\ +- SUNXI_MMC_GCTRL_DMA_RESET) +-#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) +- +-#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +-#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +-#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +-#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +-#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +-#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +-#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +-#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +-#define SUNXI_MMC_CMD_START (0x1 << 31) +- +-#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +-#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +-#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +-#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +-#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +-#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +-#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +-#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +-#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +-#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +-#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +-#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +-#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +-#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ +- (SUNXI_MMC_RINT_RESP_ERROR | \ +- SUNXI_MMC_RINT_RESP_CRC_ERROR | \ +- SUNXI_MMC_RINT_DATA_CRC_ERROR | \ +- SUNXI_MMC_RINT_RESP_TIMEOUT | \ +- SUNXI_MMC_RINT_DATA_TIMEOUT | \ +- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ +- SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ +- SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ +- SUNXI_MMC_RINT_START_BIT_ERROR | \ +- SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ +- (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ +- SUNXI_MMC_RINT_DATA_OVER | \ +- SUNXI_MMC_RINT_COMMAND_DONE | \ +- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) +- +-#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +-#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +-#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +-#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +-#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) +-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff) +- +-#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) +- +-#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +-#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +-#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) +- +-#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +-#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) +- +-#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) +-#define SUNXI_MMC_COMMON_RESET (1 << 18) +- +-#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) ++#ifndef _ARCH_SUNXI_MMC_H ++#define _ARCH_SUNXI_MMC_H + + struct mmc *sunxi_mmc_init(int sdc_no); +-#endif /* _SUNXI_MMC_H */ ++ ++#endif /* _ARCH_SUNXI_MMC_H */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-sunxi/spl.h u-boot/arch/arm/include/asm/arch-sunxi/spl.h +--- u-boot-2021.10/arch/arm/include/asm/arch-sunxi/spl.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-sunxi/spl.h 2021-11-01 17:10:13.736287957 +0100 +@@ -19,8 +19,6 @@ + #define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 + #define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 + +-#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0) +- + uint32_t sunxi_get_boot_device(void); + + #endif +diff -ruN u-boot-2021.10/arch/arm/include/asm/arch-vf610/iomux-vf610.h u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h +--- u-boot-2021.10/arch/arm/include/asm/arch-vf610/iomux-vf610.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h 2021-11-01 17:10:13.739621108 +0100 +@@ -163,13 +163,13 @@ + VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + +- VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), ++ VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + +- VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), ++ VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), + +- VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), ++ VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + +- VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), ++ VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + + VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), + VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), +diff -ruN u-boot-2021.10/arch/arm/include/asm/bootm.h u-boot/arch/arm/include/asm/bootm.h +--- u-boot-2021.10/arch/arm/include/asm/bootm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/bootm.h 2021-11-01 17:10:13.739621108 +0100 +@@ -10,11 +10,7 @@ + + extern void udc_disconnect(void); + +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + # define BOOTM_ENABLE_TAGS 1 + #else + # define BOOTM_ENABLE_TAGS 0 +@@ -41,9 +37,12 @@ + struct tag_serialnr; + #ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +-void get_board_serial(struct tag_serialnr *serialnr); + #else + #define BOOTM_ENABLE_SERIAL_TAG 0 ++#endif ++#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) ++void get_board_serial(struct tag_serialnr *serialnr); ++#else + static inline void get_board_serial(struct tag_serialnr *serialnr) + { + } +diff -ruN u-boot-2021.10/arch/arm/include/asm/mach-types.h u-boot/arch/arm/include/asm/mach-types.h +--- u-boot-2021.10/arch/arm/include/asm/mach-types.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/mach-types.h 2021-11-01 17:10:13.746287410 +0100 +@@ -267,7 +267,6 @@ + #define MACH_TYPE_BMS 259 + #define MACH_TYPE_IXCDP1100 260 + #define MACH_TYPE_PRPMC1100 261 +-#define MACH_TYPE_AT91RM9200DK 262 + #define MACH_TYPE_ARMSTICK 263 + #define MACH_TYPE_ARMONIE 264 + #define MACH_TYPE_MPORT1 265 +diff -ruN u-boot-2021.10/arch/arm/include/asm/macro.h u-boot/arch/arm/include/asm/macro.h +--- u-boot-2021.10/arch/arm/include/asm/macro.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/macro.h 2021-11-01 17:10:13.749620561 +0100 +@@ -154,7 +154,7 @@ + orr \xreg1, \xreg1, \xreg2 + cbz \xreg1, \master_label + #else +- b \master_label ++ b \master_label + #endif + .endm + +@@ -256,7 +256,7 @@ + * For loading 64-bit OS, x0 is physical address to the FDT blob. + * They will be passed to the guest. + */ +-.macro armv8_switch_to_el1_m, ep, flag, tmp ++.macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2 + /* Initialize Generic Timers */ + mrs \tmp, cnthctl_el2 + /* Enable EL1 access to timers */ +@@ -306,7 +306,14 @@ + b.eq 1f + + /* Initialize HCR_EL2 */ +- ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) ++ /* Only disable PAuth traps if PAuth is supported */ ++ mrs \tmp, id_aa64isar1_el1 ++ ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \ ++ ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA) ++ tst \tmp, \tmp2 ++ mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) ++ orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API) ++ csel \tmp, \tmp2, \tmp, eq + msr hcr_el2, \tmp + + /* Return to the EL1_SP1 mode from EL2 */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/string.h u-boot/arch/arm/include/asm/string.h +--- u-boot-2021.10/arch/arm/include/asm/string.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/string.h 2021-11-01 17:10:13.749620561 +0100 +@@ -19,7 +19,11 @@ + #endif + extern void * memcpy(void *, const void *, __kernel_size_t); + ++#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE) ++#define __HAVE_ARCH_MEMMOVE ++#else + #undef __HAVE_ARCH_MEMMOVE ++#endif + extern void * memmove(void *, const void *, __kernel_size_t); + + #undef __HAVE_ARCH_MEMCHR +diff -ruN u-boot-2021.10/arch/arm/include/asm/system.h u-boot/arch/arm/include/asm/system.h +--- u-boot-2021.10/arch/arm/include/asm/system.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/system.h 2021-11-01 17:10:13.749620561 +0100 +@@ -75,11 +75,26 @@ + /* + * HCR_EL2 bits definitions + */ ++#define HCR_EL2_API (1 << 41) /* Trap pointer authentication ++ instructions */ ++#define HCR_EL2_APK (1 << 40) /* Trap pointer authentication ++ key access */ + #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ + #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ + #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ + + /* ++ * ID_AA64ISAR1_EL1 bits definitions ++ */ ++#define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic ++ code auth algorithm */ ++#define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth ++ algorithm */ ++#define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address ++ auth algorithm */ ++#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */ ++ ++/* + * ID_AA64PFR0_EL1 bits definitions + */ + #define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */ +@@ -551,7 +566,6 @@ + u32 psci_migrate_info_type(void); + void psci_system_off(void); + void psci_system_reset(void); +-s32 psci_features(u32 function_id, u32 psci_fid); + #endif + + #endif /* __ASSEMBLY__ */ +diff -ruN u-boot-2021.10/arch/arm/include/asm/ti-common/davinci_nand.h u-boot/arch/arm/include/asm/ti-common/davinci_nand.h +--- u-boot-2021.10/arch/arm/include/asm/ti-common/davinci_nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/ti-common/davinci_nand.h 2021-11-01 17:10:13.749620561 +0100 +@@ -9,12 +9,11 @@ + #ifndef _DAVINCI_NAND_H_ + #define _DAVINCI_NAND_H_ + +-#include + #include + +-#define NAND_READ_START 0x00 +-#define NAND_READ_END 0x30 +-#define NAND_STATUS 0x70 ++#define NAND_READ_START 0x00 ++#define NAND_READ_END 0x30 ++#define NAND_STATUS 0x70 + + #define MASK_CLE 0x10 + #define MASK_ALE 0x08 +diff -ruN u-boot-2021.10/arch/arm/include/asm/xen.h u-boot/arch/arm/include/asm/xen.h +--- u-boot-2021.10/arch/arm/include/asm/xen.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/include/asm/xen.h 2021-11-01 17:10:13.749620561 +0100 +@@ -4,4 +4,3 @@ + */ + + extern unsigned long rom_pointer[]; +- +diff -ruN u-boot-2021.10/arch/arm/Kconfig u-boot/arch/arm/Kconfig +--- u-boot-2021.10/arch/arm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/Kconfig 2021-11-01 17:10:13.546298348 +0100 +@@ -9,9 +9,19 @@ + select PHYS_64BIT + select SYS_CACHE_SHIFT_6 + +-if ARM64 ++config ARM64_CRC32 ++ bool "Enable support for CRC32 instruction" ++ depends on ARM64 ++ default y ++ help ++ ARMv8 implements dedicated crc32 instruction for crc32 calculation. ++ This is faster than software crc32 calculation. This instruction may ++ not be present on all ARMv8.0, but is always present on ARMv8.1 and ++ newer. ++ + config POSITION_INDEPENDENT + bool "Generate position-independent pre-relocation code" ++ depends on ARM64 || CPU_V7A + help + U-Boot expects to be linked to a specific hard-coded address, and to + be loaded to and run from that address. This option lifts that +@@ -22,6 +32,7 @@ + + config INIT_SP_RELATIVE + bool "Specify the early stack pointer relative to the .bss section" ++ depends on ARM64 + default n if ARCH_QEMU + default y if POSITION_INDEPENDENT + help +@@ -37,6 +48,7 @@ + + config SYS_INIT_SP_BSS_OFFSET + int "Early stack offset from the .bss base address" ++ depends on ARM64 + depends on INIT_SP_RELATIVE + default 524288 + help +@@ -46,6 +58,7 @@ + do not overlap any appended DTB. + + config LINUX_KERNEL_IMAGE_HEADER ++ depends on ARM64 + bool + help + Place a Linux kernel image header at the start of the U-Boot binary. +@@ -54,14 +67,18 @@ + image header reports the amount of memory (BSS and similar) that + U-Boot needs to use, but which isn't part of the binary. + +-if LINUX_KERNEL_IMAGE_HEADER + config LNX_KRNL_IMG_TEXT_OFFSET_BASE ++ depends on LINUX_KERNEL_IMAGE_HEADER + hex + help + The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the + TEXT_OFFSET value written to the Linux kernel image header. +-endif +-endif ++ ++config GICV2 ++ bool ++ ++config GICV3 ++ bool + + config GIC_V3_ITS + bool "ARM GICV3 ITS" +@@ -104,7 +121,6 @@ + + config SYS_ICACHE_OFF + bool "Do not enable icache" +- default n + help + Do not enable instruction cache in U-Boot. + +@@ -117,7 +133,6 @@ + + config SYS_DCACHE_OFF + bool "Do not enable dcache" +- default n + help + Do not enable data cache in U-Boot. + +@@ -332,21 +347,6 @@ + default 4 if CPU_SA1100 + default 8 if ARM64 + +-config SYS_CACHE_SHIFT_5 +- bool +- +-config SYS_CACHE_SHIFT_6 +- bool +- +-config SYS_CACHE_SHIFT_7 +- bool +- +-config SYS_CACHELINE_SIZE +- int +- default 128 if SYS_CACHE_SHIFT_7 +- default 64 if SYS_CACHE_SHIFT_6 +- default 32 if SYS_CACHE_SHIFT_5 +- + choice + prompt "Select the ARM data write cache policy" + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ +@@ -452,12 +452,11 @@ + + config ARM_CORTEX_CPU_IS_UP + bool +- default n + + config USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy" +- default y +- depends on !ARM64 ++ default y if !ARM64 ++ depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400)) + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions +@@ -466,7 +465,7 @@ + config SPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for SPL" + default y if USE_ARCH_MEMCPY +- depends on !ARM64 && SPL ++ depends on SPL + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions +@@ -475,16 +474,43 @@ + config TPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for TPL" + default y if USE_ARCH_MEMCPY +- depends on !ARM64 && TPL ++ depends on TPL + help + Enable the generation of an optimized version of memcpy. + Such an implementation may be faster under some conditions + but may increase the binary size. + ++config USE_ARCH_MEMMOVE ++ bool "Use an assembly optimized implementation of memmove" if !ARM64 ++ default USE_ARCH_MEMCPY if ARM64 ++ depends on ARM64 ++ help ++ Enable the generation of an optimized version of memmove. ++ Such an implementation may be faster under some conditions ++ but may increase the binary size. ++ ++config SPL_USE_ARCH_MEMMOVE ++ bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64 ++ default SPL_USE_ARCH_MEMCPY if ARM64 ++ depends on SPL && ARM64 ++ help ++ Enable the generation of an optimized version of memmove. ++ Such an implementation may be faster under some conditions ++ but may increase the binary size. ++ ++config TPL_USE_ARCH_MEMMOVE ++ bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64 ++ default TPL_USE_ARCH_MEMCPY if ARM64 ++ depends on TPL && ARM64 ++ help ++ Enable the generation of an optimized version of memmove. ++ Such an implementation may be faster under some conditions ++ but may increase the binary size. ++ + config USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset" +- default y +- depends on !ARM64 ++ default y if !ARM64 ++ depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400)) + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions +@@ -493,7 +519,7 @@ + config SPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for SPL" + default y if USE_ARCH_MEMSET +- depends on !ARM64 && SPL ++ depends on SPL + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions +@@ -502,7 +528,7 @@ + config TPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for TPL" + default y if USE_ARCH_MEMSET +- depends on !ARM64 && TPL ++ depends on TPL + help + Enable the generation of an optimized version of memset. + Such an implementation may be faster under some conditions +@@ -525,11 +551,6 @@ + select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB + select SPL_SEPARATE_BSS if SPL + +-config TARGET_ASPENITE +- bool "Support aspenite" +- select CPU_ARM926EJS +- select GPIO_EXTRA_HEADER +- + config ARCH_DAVINCI + bool "TI DaVinci" + select CPU_ARM926EJS +@@ -579,11 +600,6 @@ + select SPI_FLASH + imply CMD_DM + +-config TARGET_FLEA3 +- bool "Support flea3" +- select CPU_ARM1136 +- select GPIO_EXTRA_HEADER +- + config ARCH_BCM283X + bool "Broadcom BCM283X family" + select DM +@@ -626,6 +642,11 @@ + This enables support for Broadcom ARM-based set-top box + chipsets, including the 7445 family of chips. + ++config TARGET_VEXPRESS_CA9X4 ++ bool "Support vexpress_ca9x4" ++ select CPU_V7A ++ select PL011_SERIAL ++ + config TARGET_BCMCYGNUS + bool "Support bcmcygnus" + select CPU_V7A +@@ -723,6 +744,7 @@ + bool "TI Keystone" + select CMD_POWEROFF + select CPU_V7A ++ select DDR_SPD + select GPIO_EXTRA_HEADER + select SUPPORT_SPL + select SYS_ARCH_TIMER +@@ -787,6 +809,7 @@ + select ARM64 + select DM + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select OF_CONTROL + select ENABLE_ARM_SOC_BOOT0_HOOK + +@@ -794,9 +817,11 @@ + bool "NXP i.MX8M platform" + select ARM64 + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE ++ select SYS_I2C_MXC + select DM + select SUPPORT_SPL + imply CMD_DM +@@ -805,6 +830,7 @@ + bool "NXP i.MX8ULP platform" + select ARM64 + select DM ++ select MACH_IMX + select OF_CONTROL + select SUPPORT_SPL + select GPIO_EXTRA_HEADER +@@ -816,6 +842,7 @@ + select DM + select DM_SERIAL + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SUPPORT_SPL + imply CMD_DM + +@@ -823,31 +850,29 @@ + bool "NXP i.MX23 family" + select CPU_ARM926EJS + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select PL011_SERIAL + select SUPPORT_SPL + +-config ARCH_MX25 +- bool "NXP MX25" +- select CPU_ARM926EJS +- select GPIO_EXTRA_HEADER +- imply MXC_GPIO +- + config ARCH_MX28 + bool "NXP i.MX28 family" + select CPU_ARM926EJS + select GPIO_EXTRA_HEADER + select PL011_SERIAL ++ select MACH_IMX + select SUPPORT_SPL + + config ARCH_MX31 + bool "NXP i.MX31 family" + select CPU_ARM1136 + select GPIO_EXTRA_HEADER ++ select MACH_IMX + + config ARCH_MX7ULP + bool "NXP MX7ULP" + select CPU_V7A + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE +@@ -860,6 +885,7 @@ + select ARCH_MISC_INIT + select CPU_V7A + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE +@@ -871,6 +897,7 @@ + bool "Freescale MX6" + select CPU_V7A + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE +@@ -887,6 +914,7 @@ + select BOARD_EARLY_INIT_F + select CPU_V7A + select GPIO_EXTRA_HEADER ++ select MACH_IMX + imply MXC_GPIO + + config ARCH_NEXELL +@@ -952,6 +980,7 @@ + select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select DM + select DM_SERIAL ++ select GICV2 + select GPIO_EXTRA_HEADER + select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select OF_CONTROL +@@ -962,7 +991,7 @@ + select SPL_NAND_SUPPORT if SPL_NAND_DENALI + select SPL_OF_CONTROL + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 +- select SPL_SERIAL_SUPPORT ++ select SPL_SERIAL + select SPL_SYSRESET + select SPL_WATCHDOG + select SUPPORT_SPL +@@ -982,11 +1011,11 @@ + imply SPL_DM_SPI + imply SPL_DM_SPI_FLASH + imply SPL_LIBDISK_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + imply SPL_SPI_FLASH_SUPPORT +- imply SPL_SPI_SUPPORT ++ imply SPL_SPI + imply L2X0_CACHE + + config ARCH_SUNXI +@@ -999,6 +1028,7 @@ + select DM + select DM_ETH + select DM_GPIO ++ select DM_I2C if I2C + select DM_KEYBOARD + select DM_MMC if MMC + select DM_SCSI if SCSI +@@ -1007,13 +1037,16 @@ + select OF_BOARD_SETUP + select OF_CONTROL + select OF_SEPARATE ++ select PINCTRL + select SPECIFY_CONSOLE_INDEX ++ select SPL_SEPARATE_BSS if SPL + select SPL_STACK_R if SPL + select SPL_SYS_MALLOC_SIMPLE if SPL + select SPL_SYS_THUMB_BUILD if !ARM64 + select SUNXI_GPIO + select SYS_NS16550 + select SYS_THUMB_BUILD if !ARM64 ++ select TOOLS_LIBCRYPTO + select USB if DISTRO_DEFAULTS + select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST + select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST +@@ -1032,10 +1065,17 @@ + imply SPL_GPIO + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT if MMC ++ imply SPL_MMC if MMC + imply SPL_POWER +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL ++ imply SYSRESET ++ imply SYSRESET_WATCHDOG ++ imply SYSRESET_WATCHDOG_AUTO ++ imply USB_EHCI_GENERIC ++ imply USB_ETHER if USB_MUSB_GADGET + imply USB_GADGET ++ imply USB_OHCI_GENERIC ++ imply WDT + + config ARCH_U8500 + bool "ST-Ericsson U8500 Series" +@@ -1044,14 +1084,22 @@ + select DM_GPIO + select DM_MMC if MMC + select DM_SERIAL ++ select DM_USB_GADGET if DM_USB + select OF_CONTROL + select SYSRESET + select TIMER ++ imply AB8500_USB_PHY + imply ARM_PL180_MMCI ++ imply CLK ++ imply DM_PMIC + imply DM_RTC ++ imply NOMADIK_GPIO + imply NOMADIK_MTU_TIMER ++ imply PHY + imply PL01X_SERIAL ++ imply PMIC_AB8500 + imply RTC_PL031 ++ imply SYS_THUMB_BUILD + imply SYSRESET_SYSCON + + config ARCH_VERSAL +@@ -1062,6 +1110,7 @@ + select DM_ETH if NET + select DM_MMC if MMC + select DM_SERIAL ++ select GICV3 + select GPIO_EXTRA_HEADER + select OF_CONTROL + select SOC_DEVICE +@@ -1072,6 +1121,7 @@ + bool "Freescale Vybrid" + select CPU_V7A + select GPIO_EXTRA_HEADER ++ select MACH_IMX + select SYS_FSL_ERRATUM_ESDHC111 + imply CMD_MTDPARTS + imply MTD_RAW_NAND +@@ -1131,6 +1181,7 @@ + select DM_SPI if SPI + select DM_SPI_FLASH if DM_SPI + select FIRMWARE ++ select GICV2 + select GPIO_EXTRA_HEADER + select OF_CONTROL + select SPL_BOARD_INIT if SPL +@@ -1880,6 +1931,7 @@ + config TARGET_PRESIDIO_ASIC + bool "Support Cortina Presidio ASIC Platform" + select ARM64 ++ select GICV2 + + config TARGET_XENGUEST_ARM64 + bool "Xen guest ARM64" +@@ -1891,13 +1943,56 @@ + select SSCANF + endchoice + ++config SUPPORT_PASSING_ATAGS ++ bool "Support pre-devicetree ATAG-based booting" ++ depends on !ARM64 ++ imply SETUP_MEMORY_TAGS ++ help ++ Support for booting older Linux kernels, using ATAGs rather than ++ passing a devicetree. This is option is rarely used, and the ++ semantics are defined at ++ https://www.kernel.org/doc/Documentation/arm/Booting at section 4a. ++ ++config SETUP_MEMORY_TAGS ++ bool "Pass memory size information via ATAG" ++ depends on SUPPORT_PASSING_ATAGS ++ ++config CMDLINE_TAG ++ bool "Pass Linux kernel cmdline via ATAG" ++ depends on SUPPORT_PASSING_ATAGS ++ ++config INITRD_TAG ++ bool "Pass initrd starting point and size via ATAG" ++ depends on SUPPORT_PASSING_ATAGS ++ ++config REVISION_TAG ++ bool "Pass system revision via ATAG" ++ depends on SUPPORT_PASSING_ATAGS ++ ++config SERIAL_TAG ++ bool "Pass system serial number via ATAG" ++ depends on SUPPORT_PASSING_ATAGS ++ ++config STATIC_MACH_TYPE ++ bool "Statically define the Machine ID number" ++ help ++ When booting via ATAGs, enable this option if we know the correct ++ machine ID number to use at compile time. Some systems will be ++ passed the number dynamically by whatever loads U-Boot. ++ ++config MACH_TYPE ++ int "Machine ID number" ++ depends on STATIC_MACH_TYPE ++ help ++ When booting via ATAGs, the machine type must be passed as a number. ++ For the full list see https://www.arm.linux.org.uk/developer/machines ++ + config ARCH_SUPPORT_TFABOOT + bool + + config TFABOOT + bool "Support for booting from TF-A" + depends on ARCH_SUPPORT_TFABOOT +- default n + help + Some platforms support the setup of secure registers (for instance + for CPU errata handling) or provide secure services like PSCI. +@@ -1966,8 +2061,6 @@ + + source "arch/arm/cpu/armv7/ls102xa/Kconfig" + +-source "arch/arm/mach-imx/mx2/Kconfig" +- + source "arch/arm/mach-imx/mx3/Kconfig" + + source "arch/arm/mach-imx/mx5/Kconfig" +@@ -2048,10 +2141,9 @@ + + source "board/bosch/shc/Kconfig" + source "board/bosch/guardian/Kconfig" +-source "board/CarMediaLab/flea3/Kconfig" +-source "board/Marvell/aspenite/Kconfig" + source "board/Marvell/octeontx/Kconfig" + source "board/Marvell/octeontx2/Kconfig" ++source "board/armltd/vexpress/Kconfig" + source "board/armltd/vexpress64/Kconfig" + source "board/cortina/presidio-asic/Kconfig" + source "board/broadcom/bcm963158/Kconfig" +diff -ruN u-boot-2021.10/arch/arm/lib/asmdefs.h u-boot/arch/arm/lib/asmdefs.h +--- u-boot-2021.10/arch/arm/lib/asmdefs.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/lib/asmdefs.h 2021-11-01 17:10:13.749620561 +0100 +@@ -0,0 +1,98 @@ ++/* SPDX-License-Identifier: MIT */ ++/* ++ * Macros for asm code. ++ * ++ * Copyright (c) 2019, Arm Limited. ++ */ ++ ++#ifndef _ASMDEFS_H ++#define _ASMDEFS_H ++ ++#if defined(__aarch64__) ++ ++/* Branch Target Identitication support. */ ++#define BTI_C hint 34 ++#define BTI_J hint 36 ++/* Return address signing support (pac-ret). */ ++#define PACIASP hint 25; .cfi_window_save ++#define AUTIASP hint 29; .cfi_window_save ++ ++/* GNU_PROPERTY_AARCH64_* macros from elf.h. */ ++#define FEATURE_1_AND 0xc0000000 ++#define FEATURE_1_BTI 1 ++#define FEATURE_1_PAC 2 ++ ++/* Add a NT_GNU_PROPERTY_TYPE_0 note. */ ++#define GNU_PROPERTY(type, value) \ ++ .section .note.gnu.property, "a"; \ ++ .p2align 3; \ ++ .word 4; \ ++ .word 16; \ ++ .word 5; \ ++ .asciz "GNU"; \ ++ .word type; \ ++ .word 4; \ ++ .word value; \ ++ .word 0; \ ++ .text ++ ++/* If set then the GNU Property Note section will be added to ++ mark objects to support BTI and PAC-RET. */ ++#ifndef WANT_GNU_PROPERTY ++#define WANT_GNU_PROPERTY 1 ++#endif ++ ++#if WANT_GNU_PROPERTY ++/* Add property note with supported features to all asm files. */ ++GNU_PROPERTY (FEATURE_1_AND, FEATURE_1_BTI|FEATURE_1_PAC) ++#endif ++ ++#define ENTRY_ALIGN(name, alignment) \ ++ .global name; \ ++ .type name,%function; \ ++ .align alignment; \ ++ name: \ ++ .cfi_startproc; \ ++ BTI_C; ++ ++#else ++ ++#define END_FILE ++ ++#define ENTRY_ALIGN(name, alignment) \ ++ .global name; \ ++ .type name,%function; \ ++ .align alignment; \ ++ name: \ ++ .cfi_startproc; ++ ++#endif ++ ++#define ENTRY(name) ENTRY_ALIGN(name, 6) ++ ++#define ENTRY_ALIAS(name) \ ++ .global name; \ ++ .type name,%function; \ ++ name: ++ ++#define END(name) \ ++ .cfi_endproc; \ ++ .size name, .-name; ++ ++#define L(l) .L ## l ++ ++#ifdef __ILP32__ ++ /* Sanitize padding bits of pointer arguments as per aapcs64 */ ++#define PTR_ARG(n) mov w##n, w##n ++#else ++#define PTR_ARG(n) ++#endif ++ ++#ifdef __ILP32__ ++ /* Sanitize padding bits of size arguments as per aapcs64 */ ++#define SIZE_ARG(n) mov w##n, w##n ++#else ++#define SIZE_ARG(n) ++#endif ++ ++#endif +diff -ruN u-boot-2021.10/arch/arm/lib/asm-offsets.c u-boot/arch/arm/lib/asm-offsets.c +--- u-boot-2021.10/arch/arm/lib/asm-offsets.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/asm-offsets.c 2021-11-01 17:10:13.749620561 +0100 +@@ -15,7 +15,7 @@ + #include + #include + +-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ ++#if defined(CONFIG_MX27) \ + || defined(CONFIG_MX51) || defined(CONFIG_MX53) + #include + #endif +@@ -35,42 +35,6 @@ + * code. Is it better to define the macros directly in headers? + */ + +-#if defined(CONFIG_MX25) +- /* Clock Control Module */ +- DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); +- DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); +- DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); +- DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); +- DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); +- DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); +- +- /* Enhanced SDRAM Controller */ +- DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); +- DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); +- DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); +- +- /* Multi-Layer AHB Crossbar Switch */ +- DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); +- DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); +- DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); +- DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); +- DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); +- DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); +- DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); +- DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); +- DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); +- DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); +- DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); +- DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); +- DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); +- DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); +- DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); +- +- /* AHB <-> IP-Bus Interface */ +- DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); +- DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); +-#endif +- + #if defined(CONFIG_MX27) + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); +@@ -97,56 +61,6 @@ + offsetof(struct system_control_regs, fmcr)); + #endif + +-#if defined(CONFIG_MX35) +- /* Round up to make sure size gives nice stack alignment */ +- DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); +- DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); +- DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); +- DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); +- DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); +- DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); +- DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); +- DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); +- DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); +- DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); +- DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); +- DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); +- DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); +- DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); +- DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); +- +- /* Multi-Layer AHB Crossbar Switch */ +- DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); +- DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); +- DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); +- DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); +- DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); +- DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); +- DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); +- DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); +- DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); +- DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); +- DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); +- DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); +- DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); +- DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); +- DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); +- DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); +- +- /* AHB <-> IP-Bus Interface */ +- DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); +- DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); +- DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); +- DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); +- DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); +- DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); +- DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); +- DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); +- DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); +- DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); +- DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); +-#endif +- + #if defined(CONFIG_MX51) || defined(CONFIG_MX53) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); +diff -ruN u-boot-2021.10/arch/arm/lib/bootm.c u-boot/arch/arm/lib/bootm.c +--- u-boot-2021.10/arch/arm/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/bootm.c 2021-11-01 17:10:13.749620561 +0100 +@@ -16,7 +16,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -43,50 +42,6 @@ + + static struct tag *params; + +-static ulong get_sp(void) +-{ +- ulong ret; +- +- asm("mov %0, sp" : "=r"(ret) : ); +- return ret; +-} +- +-void arch_lmb_reserve(struct lmb *lmb) +-{ +- ulong sp, bank_end; +- int bank; +- +- /* +- * Booting a (Linux) kernel image +- * +- * Allocate space for command line and board info - the +- * address should be as high as possible within the reach of +- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused +- * memory, which means far enough below the current stack +- * pointer. +- */ +- sp = get_sp(); +- debug("## Current stack ends at 0x%08lx ", sp); +- +- /* adjust sp by 4K to be safe */ +- sp -= 4096; +- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { +- if (!gd->bd->bi_dram[bank].size || +- sp < gd->bd->bi_dram[bank].start) +- continue; +- /* Watch out for RAM at end of address space! */ +- bank_end = gd->bd->bi_dram[bank].start + +- gd->bd->bi_dram[bank].size - 1; +- if (sp > bank_end) +- continue; +- if (bank_end > gd->ram_top) +- bank_end = gd->ram_top - 1; +- +- lmb_reserve(lmb, sp, bank_end - sp + 1); +- break; +- } +-} +- + __weak void board_quiesce_devices(void) + { + } +diff -ruN u-boot-2021.10/arch/arm/lib/ccn504.S u-boot/arch/arm/lib/ccn504.S +--- u-boot-2021.10/arch/arm/lib/ccn504.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/ccn504.S 2021-11-01 17:10:13.752953712 +0100 +@@ -12,7 +12,7 @@ + /************************************************************************* + * + * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, +- * CCI_MN_DVM_DOMAIN_CTL_SET); ++ * CCI_MN_DVM_DOMAIN_CTL_SET); + * + * Add fully-coherent masters to DVM domain + * +@@ -78,4 +78,3 @@ + + ret + ENDPROC(ccn504_set_aux) +- +diff -ruN u-boot-2021.10/arch/arm/lib/crt0.S u-boot/arch/arm/lib/crt0.S +--- u-boot-2021.10/arch/arm/lib/crt0.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/crt0.S 2021-11-01 17:10:13.752953712 +0100 +@@ -130,6 +130,14 @@ + ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ + + adr lr, here ++#if defined(CONFIG_POSITION_INDEPENDENT) ++ adr r0, _main ++ ldr r1, _start_ofs ++ add r0, r1 ++ ldr r1, =CONFIG_SYS_TEXT_BASE ++ sub r1, r0 ++ add lr, r1 ++#endif + ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ + add lr, lr, r0 + #if defined(CONFIG_CPU_V7M) +@@ -180,3 +188,6 @@ + #endif + + ENDPROC(_main) ++ ++_start_ofs: ++ .word _start - _main +diff -ruN u-boot-2021.10/arch/arm/lib/div64.S u-boot/arch/arm/lib/div64.S +--- u-boot-2021.10/arch/arm/lib/div64.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/div64.S 2021-11-01 17:10:13.752953712 +0100 +@@ -34,12 +34,12 @@ + * This is meant to be used by do_div() from include/asm/div64.h only. + * + * Input parameters: +- * xh-xl = dividend (clobbered) +- * r4 = divisor (preserved) ++ * xh-xl = dividend (clobbered) ++ * r4 = divisor (preserved) + * + * Output values: +- * yh-yl = result +- * xh = remainder ++ * yh-yl = result ++ * xh = remainder + * + * Clobbered regs: xl, ip + */ +@@ -85,7 +85,7 @@ + #endif + + @ The division loop for needed upper bit positions. +- @ Break out early if dividend reaches 0. ++ @ Break out early if dividend reaches 0. + 2: cmp xh, yl + orrcs yh, yh, ip + subscs xh, xh, yl +diff -ruN u-boot-2021.10/arch/arm/lib/lib1funcs.S u-boot/arch/arm/lib/lib1funcs.S +--- u-boot-2021.10/arch/arm/lib/lib1funcs.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/lib1funcs.S 2021-11-01 17:10:13.752953712 +0100 +@@ -34,7 +34,7 @@ + mov \divisor, \divisor, lsl \result + mov \curbit, \curbit, lsl \result + mov \result, #0 +- ++ + #else + + @ Initially shift the divisor left 3 bits if possible, +@@ -48,7 +48,7 @@ + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main +- @ division loop. Continue shifting until the divisor is ++ @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + 1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend +@@ -135,7 +135,7 @@ + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main +- @ division loop. Continue shifting until the divisor is ++ @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + 1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend +diff -ruN u-boot-2021.10/arch/arm/lib/Makefile u-boot/arch/arm/lib/Makefile +--- u-boot-2021.10/arch/arm/lib/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/Makefile 2021-11-01 17:10:13.749620561 +0100 +@@ -39,8 +39,13 @@ + obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o + obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o + endif ++ifdef CONFIG_ARM64 ++obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o ++obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o ++else + obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o + obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o ++endif + obj-$(CONFIG_SEMIHOSTING) += semihosting.o + + obj-y += bdinfo.o +diff -ruN u-boot-2021.10/arch/arm/lib/memcpy-arm64.S u-boot/arch/arm/lib/memcpy-arm64.S +--- u-boot-2021.10/arch/arm/lib/memcpy-arm64.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/lib/memcpy-arm64.S 2021-11-01 17:10:13.752953712 +0100 +@@ -0,0 +1,242 @@ ++/* SPDX-License-Identifier: MIT */ ++/* ++ * memcpy - copy memory area ++ * ++ * Copyright (c) 2012-2020, Arm Limited. ++ */ ++ ++/* Assumptions: ++ * ++ * ARMv8-a, AArch64, unaligned accesses. ++ * ++ */ ++ ++#include "asmdefs.h" ++ ++#define dstin x0 ++#define src x1 ++#define count x2 ++#define dst x3 ++#define srcend x4 ++#define dstend x5 ++#define A_l x6 ++#define A_lw w6 ++#define A_h x7 ++#define B_l x8 ++#define B_lw w8 ++#define B_h x9 ++#define C_l x10 ++#define C_lw w10 ++#define C_h x11 ++#define D_l x12 ++#define D_h x13 ++#define E_l x14 ++#define E_h x15 ++#define F_l x16 ++#define F_h x17 ++#define G_l count ++#define G_h dst ++#define H_l src ++#define H_h srcend ++#define tmp1 x14 ++ ++/* This implementation handles overlaps and supports both memcpy and memmove ++ from a single entry point. It uses unaligned accesses and branchless ++ sequences to keep the code small, simple and improve performance. ++ ++ Copies are split into 3 main cases: small copies of up to 32 bytes, medium ++ copies of up to 128 bytes, and large copies. The overhead of the overlap ++ check is negligible since it is only required for large copies. ++ ++ Large copies use a software pipelined loop processing 64 bytes per iteration. ++ The destination pointer is 16-byte aligned to minimize unaligned accesses. ++ The loop tail is handled by always copying 64 bytes from the end. ++*/ ++ ++ENTRY_ALIAS (memmove) ++ENTRY (memcpy) ++ PTR_ARG (0) ++ PTR_ARG (1) ++ SIZE_ARG (2) ++ add srcend, src, count ++ add dstend, dstin, count ++ cmp count, 128 ++ b.hi L(copy_long) ++ cmp count, 32 ++ b.hi L(copy32_128) ++ ++ /* Small copies: 0..32 bytes. */ ++ cmp count, 16 ++ b.lo L(copy16) ++ ldp A_l, A_h, [src] ++ ldp D_l, D_h, [srcend, -16] ++ stp A_l, A_h, [dstin] ++ stp D_l, D_h, [dstend, -16] ++ ret ++ ++ /* Copy 8-15 bytes. */ ++L(copy16): ++ tbz count, 3, L(copy8) ++ ldr A_l, [src] ++ ldr A_h, [srcend, -8] ++ str A_l, [dstin] ++ str A_h, [dstend, -8] ++ ret ++ ++ .p2align 3 ++ /* Copy 4-7 bytes. */ ++L(copy8): ++ tbz count, 2, L(copy4) ++ ldr A_lw, [src] ++ ldr B_lw, [srcend, -4] ++ str A_lw, [dstin] ++ str B_lw, [dstend, -4] ++ ret ++ ++ /* Copy 0..3 bytes using a branchless sequence. */ ++L(copy4): ++ cbz count, L(copy0) ++ lsr tmp1, count, 1 ++ ldrb A_lw, [src] ++ ldrb C_lw, [srcend, -1] ++ ldrb B_lw, [src, tmp1] ++ strb A_lw, [dstin] ++ strb B_lw, [dstin, tmp1] ++ strb C_lw, [dstend, -1] ++L(copy0): ++ ret ++ ++ .p2align 4 ++ /* Medium copies: 33..128 bytes. */ ++L(copy32_128): ++ ldp A_l, A_h, [src] ++ ldp B_l, B_h, [src, 16] ++ ldp C_l, C_h, [srcend, -32] ++ ldp D_l, D_h, [srcend, -16] ++ cmp count, 64 ++ b.hi L(copy128) ++ stp A_l, A_h, [dstin] ++ stp B_l, B_h, [dstin, 16] ++ stp C_l, C_h, [dstend, -32] ++ stp D_l, D_h, [dstend, -16] ++ ret ++ ++ .p2align 4 ++ /* Copy 65..128 bytes. */ ++L(copy128): ++ ldp E_l, E_h, [src, 32] ++ ldp F_l, F_h, [src, 48] ++ cmp count, 96 ++ b.ls L(copy96) ++ ldp G_l, G_h, [srcend, -64] ++ ldp H_l, H_h, [srcend, -48] ++ stp G_l, G_h, [dstend, -64] ++ stp H_l, H_h, [dstend, -48] ++L(copy96): ++ stp A_l, A_h, [dstin] ++ stp B_l, B_h, [dstin, 16] ++ stp E_l, E_h, [dstin, 32] ++ stp F_l, F_h, [dstin, 48] ++ stp C_l, C_h, [dstend, -32] ++ stp D_l, D_h, [dstend, -16] ++ ret ++ ++ .p2align 4 ++ /* Copy more than 128 bytes. */ ++L(copy_long): ++ /* Use backwards copy if there is an overlap. */ ++ sub tmp1, dstin, src ++ cbz tmp1, L(copy0) ++ cmp tmp1, count ++ b.lo L(copy_long_backwards) ++ ++ /* Copy 16 bytes and then align dst to 16-byte alignment. */ ++ ++ ldp D_l, D_h, [src] ++ and tmp1, dstin, 15 ++ bic dst, dstin, 15 ++ sub src, src, tmp1 ++ add count, count, tmp1 /* Count is now 16 too large. */ ++ ldp A_l, A_h, [src, 16] ++ stp D_l, D_h, [dstin] ++ ldp B_l, B_h, [src, 32] ++ ldp C_l, C_h, [src, 48] ++ ldp D_l, D_h, [src, 64]! ++ subs count, count, 128 + 16 /* Test and readjust count. */ ++ b.ls L(copy64_from_end) ++ ++L(loop64): ++ stp A_l, A_h, [dst, 16] ++ ldp A_l, A_h, [src, 16] ++ stp B_l, B_h, [dst, 32] ++ ldp B_l, B_h, [src, 32] ++ stp C_l, C_h, [dst, 48] ++ ldp C_l, C_h, [src, 48] ++ stp D_l, D_h, [dst, 64]! ++ ldp D_l, D_h, [src, 64]! ++ subs count, count, 64 ++ b.hi L(loop64) ++ ++ /* Write the last iteration and copy 64 bytes from the end. */ ++L(copy64_from_end): ++ ldp E_l, E_h, [srcend, -64] ++ stp A_l, A_h, [dst, 16] ++ ldp A_l, A_h, [srcend, -48] ++ stp B_l, B_h, [dst, 32] ++ ldp B_l, B_h, [srcend, -32] ++ stp C_l, C_h, [dst, 48] ++ ldp C_l, C_h, [srcend, -16] ++ stp D_l, D_h, [dst, 64] ++ stp E_l, E_h, [dstend, -64] ++ stp A_l, A_h, [dstend, -48] ++ stp B_l, B_h, [dstend, -32] ++ stp C_l, C_h, [dstend, -16] ++ ret ++ ++ .p2align 4 ++ ++ /* Large backwards copy for overlapping copies. ++ Copy 16 bytes and then align dst to 16-byte alignment. */ ++L(copy_long_backwards): ++ ldp D_l, D_h, [srcend, -16] ++ and tmp1, dstend, 15 ++ sub srcend, srcend, tmp1 ++ sub count, count, tmp1 ++ ldp A_l, A_h, [srcend, -16] ++ stp D_l, D_h, [dstend, -16] ++ ldp B_l, B_h, [srcend, -32] ++ ldp C_l, C_h, [srcend, -48] ++ ldp D_l, D_h, [srcend, -64]! ++ sub dstend, dstend, tmp1 ++ subs count, count, 128 ++ b.ls L(copy64_from_start) ++ ++L(loop64_backwards): ++ stp A_l, A_h, [dstend, -16] ++ ldp A_l, A_h, [srcend, -16] ++ stp B_l, B_h, [dstend, -32] ++ ldp B_l, B_h, [srcend, -32] ++ stp C_l, C_h, [dstend, -48] ++ ldp C_l, C_h, [srcend, -48] ++ stp D_l, D_h, [dstend, -64]! ++ ldp D_l, D_h, [srcend, -64]! ++ subs count, count, 64 ++ b.hi L(loop64_backwards) ++ ++ /* Write the last iteration and copy 64 bytes from the start. */ ++L(copy64_from_start): ++ ldp G_l, G_h, [src, 48] ++ stp A_l, A_h, [dstend, -16] ++ ldp A_l, A_h, [src, 32] ++ stp B_l, B_h, [dstend, -32] ++ ldp B_l, B_h, [src, 16] ++ stp C_l, C_h, [dstend, -48] ++ ldp C_l, C_h, [src] ++ stp D_l, D_h, [dstend, -64] ++ stp G_l, G_h, [dstin, 48] ++ stp A_l, A_h, [dstin, 32] ++ stp B_l, B_h, [dstin, 16] ++ stp C_l, C_h, [dstin] ++ ret ++ ++END (memcpy) +diff -ruN u-boot-2021.10/arch/arm/lib/memset-arm64.S u-boot/arch/arm/lib/memset-arm64.S +--- u-boot-2021.10/arch/arm/lib/memset-arm64.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/arm/lib/memset-arm64.S 2021-11-01 17:10:13.752953712 +0100 +@@ -0,0 +1,148 @@ ++/* SPDX-License-Identifier: MIT */ ++/* ++ * memset - fill memory with a constant byte ++ * ++ * Copyright (c) 2012-2021, Arm Limited. ++ */ ++ ++/* Assumptions: ++ * ++ * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses. ++ * ++ */ ++ ++#include ++#include "asmdefs.h" ++ ++#define dstin x0 ++#define val x1 ++#define valw w1 ++#define count x2 ++#define dst x3 ++#define dstend x4 ++#define zva_val x5 ++ ++ENTRY (memset) ++ PTR_ARG (0) ++ SIZE_ARG (2) ++ ++ /* ++ * The optimized memset uses the dc opcode, which causes problems ++ * when the cache is disabled. Let's check if the cache is disabled ++ * and use a very simple memset implementation in this case. Otherwise ++ * jump to the optimized version. ++ */ ++ switch_el x6, 3f, 2f, 1f ++3: mrs x6, sctlr_el3 ++ b 0f ++2: mrs x6, sctlr_el2 ++ b 0f ++1: mrs x6, sctlr_el1 ++0: ++ tst x6, #CR_C ++ bne 9f ++ ++ /* ++ * A very "simple" memset implementation without the use of the ++ * dc opcode. Can be run with caches disabled. ++ */ ++ mov x3, #0x0 ++ cmp count, x3 /* check for zero length */ ++ beq 8f ++4: strb valw, [dstin, x3] ++ add x3, x3, #0x1 ++ cmp count, x3 ++ bne 4b ++8: ret ++9: ++ ++ /* Here the optimized memset version starts */ ++ dup v0.16B, valw ++ add dstend, dstin, count ++ ++ cmp count, 96 ++ b.hi L(set_long) ++ cmp count, 16 ++ b.hs L(set_medium) ++ mov val, v0.D[0] ++ ++ /* Set 0..15 bytes. */ ++ tbz count, 3, 1f ++ str val, [dstin] ++ str val, [dstend, -8] ++ ret ++ .p2align 4 ++1: tbz count, 2, 2f ++ str valw, [dstin] ++ str valw, [dstend, -4] ++ ret ++2: cbz count, 3f ++ strb valw, [dstin] ++ tbz count, 1, 3f ++ strh valw, [dstend, -2] ++3: ret ++ ++ /* Set 17..96 bytes. */ ++L(set_medium): ++ str q0, [dstin] ++ tbnz count, 6, L(set96) ++ str q0, [dstend, -16] ++ tbz count, 5, 1f ++ str q0, [dstin, 16] ++ str q0, [dstend, -32] ++1: ret ++ ++ .p2align 4 ++ /* Set 64..96 bytes. Write 64 bytes from the start and ++ 32 bytes from the end. */ ++L(set96): ++ str q0, [dstin, 16] ++ stp q0, q0, [dstin, 32] ++ stp q0, q0, [dstend, -32] ++ ret ++ ++ .p2align 4 ++L(set_long): ++ and valw, valw, 255 ++ bic dst, dstin, 15 ++ str q0, [dstin] ++ cmp count, 160 ++ ccmp valw, 0, 0, hs ++ b.ne L(no_zva) ++ ++#ifndef SKIP_ZVA_CHECK ++ mrs zva_val, dczid_el0 ++ and zva_val, zva_val, 31 ++ cmp zva_val, 4 /* ZVA size is 64 bytes. */ ++ b.ne L(no_zva) ++#endif ++ str q0, [dst, 16] ++ stp q0, q0, [dst, 32] ++ bic dst, dst, 63 ++ sub count, dstend, dst /* Count is now 64 too large. */ ++ sub count, count, 128 /* Adjust count and bias for loop. */ ++ ++ .p2align 4 ++L(zva_loop): ++ add dst, dst, 64 ++ dc zva, dst ++ subs count, count, 64 ++ b.hi L(zva_loop) ++ stp q0, q0, [dstend, -64] ++ stp q0, q0, [dstend, -32] ++ ret ++ ++L(no_zva): ++ sub count, dstend, dst /* Count is 16 too large. */ ++ sub dst, dst, 16 /* Dst is biased by -32. */ ++ sub count, count, 64 + 16 /* Adjust count and bias for loop. */ ++L(no_zva_loop): ++ stp q0, q0, [dst, 32] ++ stp q0, q0, [dst, 64]! ++ subs count, count, 64 ++ b.hi L(no_zva_loop) ++ stp q0, q0, [dstend, -64] ++ stp q0, q0, [dstend, -32] ++ ret ++ ++END (memset) +diff -ruN u-boot-2021.10/arch/arm/lib/relocate.S u-boot/arch/arm/lib/relocate.S +--- u-boot-2021.10/arch/arm/lib/relocate.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/relocate.S 2021-11-01 17:10:13.752953712 +0100 +@@ -78,22 +78,28 @@ + */ + + ENTRY(relocate_code) +- ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ +- subs r4, r0, r1 /* r4 <- relocation offset */ +- beq relocate_done /* skip relocation */ +- ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ +- ++ adr r3, relocate_code ++ ldr r1, _image_copy_start_ofs ++ add r1, r3 /* r1 <- Run &__image_copy_start */ ++ subs r4, r0, r1 /* r4 <- Run to copy offset */ ++ beq relocate_done /* skip relocation */ ++ ldr r1, _image_copy_start_ofs ++ add r1, r3 /* r1 <- Run &__image_copy_start */ ++ ldr r2, _image_copy_end_ofs ++ add r2, r3 /* r2 <- Run &__image_copy_end */ + copy_loop: +- ldmia r1!, {r10-r11} /* copy from source address [r1] */ +- stmia r0!, {r10-r11} /* copy to target address [r0] */ +- cmp r1, r2 /* until source end address [r2] */ ++ ldmia r1!, {r10-r11} /* copy from source address [r1] */ ++ stmia r0!, {r10-r11} /* copy to target address [r0] */ ++ cmp r1, r2 /* until source end address [r2] */ + blo copy_loop + + /* + * fix .rel.dyn relocations + */ +- ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */ +- ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */ ++ ldr r1, _rel_dyn_start_ofs ++ add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */ ++ ldr r1, _rel_dyn_end_ofs ++ add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */ + fixloop: + ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ + and r1, r1, #0xff +@@ -129,3 +135,12 @@ + #endif + + ENDPROC(relocate_code) ++ ++_image_copy_start_ofs: ++ .word __image_copy_start - relocate_code ++_image_copy_end_ofs: ++ .word __image_copy_end - relocate_code ++_rel_dyn_start_ofs: ++ .word __rel_dyn_start - relocate_code ++_rel_dyn_end_ofs: ++ .word __rel_dyn_end - relocate_code +diff -ruN u-boot-2021.10/arch/arm/lib/stack.c u-boot/arch/arm/lib/stack.c +--- u-boot-2021.10/arch/arm/lib/stack.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/lib/stack.c 2021-11-01 17:10:13.752953712 +0100 +@@ -12,6 +12,7 @@ + */ + #include + #include ++#include + #include + + DECLARE_GLOBAL_DATA_PTR; +@@ -33,3 +34,16 @@ + + return 0; + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mov %0, sp" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384); ++} +diff -ruN u-boot-2021.10/arch/arm/mach-at91/arm920t/lowlevel_init.S u-boot/arch/arm/mach-at91/arm920t/lowlevel_init.S +--- u-boot-2021.10/arch/arm/mach-at91/arm920t/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/arm920t/lowlevel_init.S 2021-11-01 17:10:13.756286863 +0100 +@@ -10,7 +10,7 @@ + + #include + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + #include + #include +@@ -148,4 +148,4 @@ + .word CONFIG_SYS_SDRAM_VAL + SMRDATA1E: + /* SMRDATA1 is 176 bytes long */ +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/mach-at91/armv7/Makefile u-boot/arch/arm/mach-at91/armv7/Makefile +--- u-boot-2021.10/arch/arm/mach-at91/armv7/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/armv7/Makefile 2021-11-01 17:10:13.756286863 +0100 +@@ -11,7 +11,9 @@ + obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o + obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o + obj-y += cpu.o +-obj-y += reset.o ++ifndef CONFIG_$(SPL_TPL_)SYSRESET ++obj-y += reset.o ++endif + ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) + ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y) + # old non-DM timer driver +diff -ruN u-boot-2021.10/arch/arm/mach-at91/armv7/sama5d2_devices.c u-boot/arch/arm/mach-at91/armv7/sama5d2_devices.c +--- u-boot-2021.10/arch/arm/mach-at91/armv7/sama5d2_devices.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/armv7/sama5d2_devices.c 2021-11-01 17:10:13.756286863 +0100 +@@ -46,6 +46,8 @@ + return "SAMA5D28-CU"; + case ARCH_EXID_SAMA5D28CN: + return "SAMA5D28-CN"; ++ case ARCH_EXID_SAMA5D29CN: ++ return "SAMA5D29-CN"; + } + } + +diff -ruN u-boot-2021.10/arch/arm/mach-at91/armv7/sama7g5_devices.c u-boot/arch/arm/mach-at91/armv7/sama7g5_devices.c +--- u-boot-2021.10/arch/arm/mach-at91/armv7/sama7g5_devices.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/armv7/sama7g5_devices.c 2021-11-01 17:10:13.756286863 +0100 +@@ -8,4 +8,3 @@ + { + return "SAMA7G5"; + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-at91/atmel_sfr.c u-boot/arch/arm/mach-at91/atmel_sfr.c +--- u-boot-2021.10/arch/arm/mach-at91/atmel_sfr.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/atmel_sfr.c 2021-11-01 17:10:13.756286863 +0100 +@@ -39,4 +39,3 @@ + else + writel(0, &sfr->ddrcfg); + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-at91/include/mach/at91_mc.h u-boot/arch/arm/mach-at91/include/mach/at91_mc.h +--- u-boot-2021.10/arch/arm/mach-at91/include/mach/at91_mc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/include/mach/at91_mc.h 2021-11-01 17:10:13.756286863 +0100 +@@ -16,7 +16,7 @@ + #ifndef __ASSEMBLY__ + + typedef struct at91_ebi { +- u32 csa; /* 0x00 Chip Select Assignment Register */ ++ u32 csa; /* 0x00 Chip Select Assignment Register */ + u32 cfgr; /* 0x04 Configuration Register */ + u32 reserved[2]; + } at91_ebi_t; +@@ -28,20 +28,20 @@ + #define AT91_EBI_CSA_CS4A 0x0010 + + typedef struct at91_sdramc { +- u32 mr; /* 0x00 SDRAMC Mode Register */ +- u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ +- u32 cr; /* 0x08 SDRAMC Configuration Register */ +- u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ +- u32 lpr; /* 0x10 SDRAMC Low Power Register */ +- u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ +- u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ +- u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ +- u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ ++ u32 mr; /* 0x00 SDRAMC Mode Register */ ++ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ ++ u32 cr; /* 0x08 SDRAMC Configuration Register */ ++ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ ++ u32 lpr; /* 0x10 SDRAMC Low Power Register */ ++ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ ++ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ ++ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ ++ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ + u32 reserved[3]; + } at91_sdramc_t; + + typedef struct at91_smc { +- u32 csr[8]; /* 0x00 SDRAMC Mode Register */ ++ u32 csr[8]; /* 0x00 SDRAMC Mode Register */ + } at91_smc_t; + + #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) +@@ -60,7 +60,7 @@ + #define AT91_SMC_CSR_NWS(x) (x & 0x7F) + + typedef struct at91_bfc { +- u32 mr; /* 0x00 SDRAMC Mode Register */ ++ u32 mr; /* 0x00 SDRAMC Mode Register */ + } at91_bfc_t; + + typedef struct at91_mc { +diff -ruN u-boot-2021.10/arch/arm/mach-at91/include/mach/at91_st.h u-boot/arch/arm/mach-at91/include/mach/at91_st.h +--- u-boot-2021.10/arch/arm/mach-at91/include/mach/at91_st.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/include/mach/at91_st.h 2021-11-01 17:10:13.756286863 +0100 +@@ -24,6 +24,6 @@ + + #define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) + #define AT91_ST_WDMR_RSTEN 0x00010000 +-#define AT91_ST_WDMR_EXTEN 0x00020000 ++#define AT91_ST_WDMR_EXTEN 0x00020000 + + #endif +diff -ruN u-boot-2021.10/arch/arm/mach-at91/include/mach/sama5d2.h u-boot/arch/arm/mach-at91/include/mach/sama5d2.h +--- u-boot-2021.10/arch/arm/mach-at91/include/mach/sama5d2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/include/mach/sama5d2.h 2021-11-01 17:10:13.759620014 +0100 +@@ -215,6 +215,7 @@ + #define ARCH_EXID_SAMA5D27CN 0x00000021 + #define ARCH_EXID_SAMA5D28CU 0x00000010 + #define ARCH_EXID_SAMA5D28CN 0x00000020 ++#define ARCH_EXID_SAMA5D29CN 0x00000023 + + #define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2 + #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 +diff -ruN u-boot-2021.10/arch/arm/mach-at91/Kconfig u-boot/arch/arm/mach-at91/Kconfig +--- u-boot-2021.10/arch/arm/mach-at91/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/Kconfig 2021-11-01 17:10:13.752953712 +0100 +@@ -298,7 +298,6 @@ + + config ATMEL_SFR + bool +- default n + + config SYS_SOC + default "at91" +diff -ruN u-boot-2021.10/arch/arm/mach-at91/spl_at91.c u-boot/arch/arm/mach-at91/spl_at91.c +--- u-boot-2021.10/arch/arm/mach-at91/spl_at91.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-at91/spl_at91.c 2021-11-01 17:10:13.759620014 +0100 +@@ -136,7 +136,7 @@ + at91_periph_clk_enable(ATMEL_ID_PIOC); + #endif + +-#if defined(CONFIG_SPL_SERIAL_SUPPORT) ++#if defined(CONFIG_SPL_SERIAL) + /* init console */ + at91_seriald_hw_init(); + preloader_console_init(); +diff -ruN u-boot-2021.10/arch/arm/mach-bcm283x/msg.c u-boot/arch/arm/mach-bcm283x/msg.c +--- u-boot-2021.10/arch/arm/mach-bcm283x/msg.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-bcm283x/msg.c 2021-11-01 17:10:13.759620014 +0100 +@@ -202,4 +202,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-davinci/include/mach/da8xx-usb.h u-boot/arch/arm/mach-davinci/include/mach/da8xx-usb.h +--- u-boot-2021.10/arch/arm/mach-davinci/include/mach/da8xx-usb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-davinci/include/mach/da8xx-usb.h 2021-11-01 17:10:13.759620014 +0100 +@@ -29,22 +29,22 @@ + struct da8xx_usb_regs { + dv_reg revision; + dv_reg control; +- dv_reg status; +- dv_reg emulation; +- dv_reg mode; +- dv_reg autoreq; +- dv_reg srpfixtime; +- dv_reg teardown; +- dv_reg intsrc; +- dv_reg intsrc_set; +- dv_reg intsrc_clr; +- dv_reg intmsk; +- dv_reg intmsk_set; +- dv_reg intmsk_clr; +- dv_reg intsrcmsk; +- dv_reg eoi; +- dv_reg intvector; +- dv_reg grndis_size[4]; ++ dv_reg status; ++ dv_reg emulation; ++ dv_reg mode; ++ dv_reg autoreq; ++ dv_reg srpfixtime; ++ dv_reg teardown; ++ dv_reg intsrc; ++ dv_reg intsrc_set; ++ dv_reg intsrc_clr; ++ dv_reg intmsk; ++ dv_reg intmsk_set; ++ dv_reg intmsk_clr; ++ dv_reg intsrcmsk; ++ dv_reg eoi; ++ dv_reg intvector; ++ dv_reg grndis_size[4]; + }; + + #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) +@@ -68,13 +68,13 @@ + #define CFGCHIP2_OTGMODE (3 << 13) + #define CFGCHIP2_NO_OVERRIDE (0 << 13) + #define CFGCHIP2_FORCE_HOST (1 << 13) +-#define CFGCHIP2_FORCE_DEVICE (2 << 13) ++#define CFGCHIP2_FORCE_DEVICE (2 << 13) + #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) + #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) + #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) + #define CFGCHIP2_PHYPWRDN (1 << 10) + #define CFGCHIP2_OTGPWRDN (1 << 9) +-#define CFGCHIP2_DATPOL (1 << 8) ++#define CFGCHIP2_DATPOL (1 << 8) + #define CFGCHIP2_USB1SUSPENDM (1 << 7) + #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ + #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ +diff -ruN u-boot-2021.10/arch/arm/mach-davinci/include/mach/davinci_misc.h u-boot/arch/arm/mach-davinci/include/mach/davinci_misc.h +--- u-boot-2021.10/arch/arm/mach-davinci/include/mach/davinci_misc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-davinci/include/mach/davinci_misc.h 2021-11-01 17:10:13.759620014 +0100 +@@ -23,7 +23,7 @@ + /* pin table definition */ + struct pinmux_resource { + const struct pinmux_config *pins; +- const int n_pins; ++ const int n_pins; + }; + + #define PINMUX_ITEM(item) { \ +@@ -35,7 +35,6 @@ + const int lpsc_no; + }; + +-int dvevm_read_mac_address(uint8_t *buf); + void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); + int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); + int davinci_configure_pin_mux_items(const struct pinmux_resource *item, +diff -ruN u-boot-2021.10/arch/arm/mach-davinci/misc.c u-boot/arch/arm/mach-davinci/misc.c +--- u-boot-2021.10/arch/arm/mach-davinci/misc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-davinci/misc.c 2021-11-01 17:10:13.762953165 +0100 +@@ -42,33 +42,6 @@ + + #ifdef CONFIG_DRIVER_TI_EMAC + /* +- * Read ethernet MAC address from EEPROM for DVEVM compatible boards. +- * Returns 1 if found, 0 otherwise. +- */ +-int dvevm_read_mac_address(uint8_t *buf) +-{ +-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR +- /* Read MAC address. */ +- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, +- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) +- goto i2cerr; +- +- /* Check that MAC address is valid. */ +- if (!is_valid_ethaddr(buf)) +- goto err; +- +- return 1; /* Found */ +- +-i2cerr: +- printf("Read from EEPROM @ 0x%02x failed\n", +- CONFIG_SYS_I2C_EEPROM_ADDR); +-err: +-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ +- +- return 0; +-} +- +-/* + * Set the mii mode as MII or RMII + */ + void davinci_emac_mii_mode_sel(int mode_sel) +diff -ruN u-boot-2021.10/arch/arm/mach-davinci/spl.c u-boot/arch/arm/mach-davinci/spl.c +--- u-boot-2021.10/arch/arm/mach-davinci/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-davinci/spl.c 2021-11-01 17:10:13.762953165 +0100 +@@ -51,7 +51,7 @@ + return BOOT_DEVICE_NAND; + #endif + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + case DAVINCI_SD_OR_MMC_BOOT: + case DAVINCI_MMC_ONLY_BOOT: + return BOOT_DEVICE_MMC1; +diff -ruN u-boot-2021.10/arch/arm/mach-exynos/Kconfig u-boot/arch/arm/mach-exynos/Kconfig +--- u-boot-2021.10/arch/arm/mach-exynos/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-exynos/Kconfig 2021-11-01 17:10:13.762953165 +0100 +@@ -141,7 +141,7 @@ + choice + prompt "EXYNOS7 board select" + +-config TARGET_ESPRESSO7420 ++config TARGET_ESPRESSO7420 + bool "ESPRESSO7420 board" + select ARM64 + select ARMV8_MULTIENTRY +diff -ruN u-boot-2021.10/arch/arm/mach-exynos/lowlevel_init.c u-boot/arch/arm/mach-exynos/lowlevel_init.c +--- u-boot-2021.10/arch/arm/mach-exynos/lowlevel_init.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-exynos/lowlevel_init.c 2021-11-01 17:10:13.769619467 +0100 +@@ -218,7 +218,7 @@ + if (actions & DO_CLOCKS) { + system_clock_init(); + #ifdef CONFIG_DEBUG_UART +-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \ ++#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ + !defined(CONFIG_SPL_BUILD) + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + debug_uart_init(); +diff -ruN u-boot-2021.10/arch/arm/mach-imx/cmd_nandbcb.c u-boot/arch/arm/mach-imx/cmd_nandbcb.c +--- u-boot-2021.10/arch/arm/mach-imx/cmd_nandbcb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/cmd_nandbcb.c 2021-11-01 17:10:13.769619467 +0100 +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + + #include + #include +diff -ruN u-boot-2021.10/arch/arm/mach-imx/image-container.c u-boot/arch/arm/mach-imx/image-container.c +--- u-boot-2021.10/arch/arm/mach-imx/image-container.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/image-container.c 2021-11-01 17:10:13.769619467 +0100 +@@ -73,7 +73,7 @@ + return -ENOMEM; + } + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + if (dev_type == MMC_DEV) { + unsigned long count = 0; + struct mmc *mmc = (struct mmc *)dev; +@@ -213,7 +213,7 @@ + } + #endif + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) + { +diff -ruN u-boot-2021.10/arch/arm/mach-imx/imx8/cpu.c u-boot/arch/arm/mach-imx/imx8/cpu.c +--- u-boot-2021.10/arch/arm/mach-imx/imx8/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/imx8/cpu.c 2021-11-01 17:10:13.772952618 +0100 +@@ -172,7 +172,7 @@ + return boot_dev; + } + +-#ifdef CONFIG_SERIAL_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define FUSE_UNIQUE_ID_WORD0 16 + #define FUSE_UNIQUE_ID_WORD1 17 + void get_board_serial(struct tag_serialnr *serialnr) +@@ -201,7 +201,7 @@ + serialnr->low = val1; + serialnr->high = val2; + } +-#endif /*CONFIG_SERIAL_TAG*/ ++#endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/ + + #ifdef CONFIG_ENV_IS_IN_MMC + __weak int board_mmc_get_env_dev(int devno) +diff -ruN u-boot-2021.10/arch/arm/mach-imx/imx8ulp/soc.c u-boot/arch/arm/mach-imx/imx8ulp/soc.c +--- u-boot-2021.10/arch/arm/mach-imx/imx8ulp/soc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/imx8ulp/soc.c 2021-11-01 17:10:13.772952618 +0100 +@@ -405,7 +405,7 @@ + return 0; + } + +-#ifdef CONFIG_SERIAL_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + void get_board_serial(struct tag_serialnr *serialnr) + { + u32 uid[4]; +diff -ruN u-boot-2021.10/arch/arm/mach-imx/Kconfig u-boot/arch/arm/mach-imx/Kconfig +--- u-boot-2021.10/arch/arm/mach-imx/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/Kconfig 2021-11-01 17:10:13.769619467 +0100 +@@ -1,8 +1,13 @@ ++config MACH_IMX ++ bool ++ + config HAS_CAAM + bool + + config IMX_CONFIG +- string ++ string "DCD script to use" ++ depends on MACH_IMX ++ default "arch/arm/mach-imx/spl_sd.cfg" + + config ROM_UNIFIED_SECTIONS + bool +diff -ruN u-boot-2021.10/arch/arm/mach-imx/Makefile u-boot/arch/arm/mach-imx/Makefile +--- u-boot-2021.10/arch/arm/mach-imx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/Makefile 2021-11-01 17:10:13.769619467 +0100 +@@ -34,7 +34,7 @@ + obj-$(CONFIG_SPL_BUILD) += spl.o + endif + ifeq ($(SOC),$(filter $(SOC),mx7)) +-obj-y += cpu.o ++obj-y += cpu.o + obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o + obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o + obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o +@@ -43,7 +43,7 @@ + obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o + endif + ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) +-obj-y += cache.o init.o ++obj-y += cache.o init.o + obj-$(CONFIG_FEC_MXC) += mac.o + obj-$(CONFIG_IMX_RDC) += rdc-sema.o + ifneq ($(CONFIG_SPL_BUILD),y) +diff -ruN u-boot-2021.10/arch/arm/mach-imx/misc.c u-boot/arch/arm/mach-imx/misc.c +--- u-boot-2021.10/arch/arm/mach-imx/misc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/misc.c 2021-11-01 17:10:13.772952618 +0100 +@@ -77,33 +77,3 @@ + + return 0; + } +- +-static ulong get_sp(void) +-{ +- ulong ret; +- +- asm("mov %0, sp" : "=r"(ret) : ); +- return ret; +-} +- +-void board_lmb_reserve(struct lmb *lmb) +-{ +- ulong sp, bank_end; +- int bank; +- +- sp = get_sp(); +- debug("## Current stack ends at 0x%08lx ", sp); +- +- /* adjust sp by 16K to be safe */ +- sp -= 4096 << 2; +- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { +- if (sp < gd->bd->bi_dram[bank].start) +- continue; +- bank_end = gd->bd->bi_dram[bank].start + +- gd->bd->bi_dram[bank].size; +- if (sp >= bank_end) +- continue; +- lmb_reserve(lmb, sp, bank_end - sp); +- break; +- } +-} +diff -ruN u-boot-2021.10/arch/arm/mach-imx/mx2/Kconfig u-boot/arch/arm/mach-imx/mx2/Kconfig +--- u-boot-2021.10/arch/arm/mach-imx/mx2/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/mx2/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,23 +0,0 @@ +-if ARCH_MX25 +- +-config MX25 +- bool +- default y +- select SYS_FSL_ERRATUM_ESDHC_A001 +-choice +- prompt "MX25 board select" +- optional +- +-config TARGET_ZMX25 +- bool "Support zmx25" +- select BOARD_LATE_INIT +- select CPU_ARM926EJS +- +-endchoice +- +-config SYS_SOC +- default "mx25" +- +-source "board/syteco/zmx25/Kconfig" +- +-endif +diff -ruN u-boot-2021.10/arch/arm/mach-imx/mx6/Kconfig u-boot/arch/arm/mach-imx/mx6/Kconfig +--- u-boot-2021.10/arch/arm/mach-imx/mx6/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/mx6/Kconfig 2021-11-01 17:10:13.776285769 +0100 +@@ -102,7 +102,6 @@ + config MX6_DDRCAL + bool "Include dynamic DDR calibration routines" + depends on SPL +- default n + help + Say "Y" if your board uses dynamic (per-boot) DDR calibration. + If unsure, say N. +@@ -305,12 +304,12 @@ + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBDISK_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL +- select SPL_MMC_SUPPORT if SPL ++ select SPL_MMC if SPL + select SPL_OF_CONTROL if SPL + select SPL_OF_LIBFDT if SPL + select SPL_PINCTRL if SPL + select SPL_SEPARATE_BSS if SPL +- select SPL_SERIAL_SUPPORT if SPL ++ select SPL_SERIAL if SPL + select SPL_USB_GADGET if SPL + select SPL_USB_HOST if SPL + select SPL_USB_SDP_SUPPORT if SPL +diff -ruN u-boot-2021.10/arch/arm/mach-imx/mx7/Kconfig u-boot/arch/arm/mach-imx/mx7/Kconfig +--- u-boot-2021.10/arch/arm/mach-imx/mx7/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/mx7/Kconfig 2021-11-01 17:10:13.776285769 +0100 +@@ -23,6 +23,14 @@ + depends on SPL + default 0x00912000 + ++config OPTEE_TZDRAM_SIZE ++ hex "Amount of Trust-Zone RAM for the OPTEE image" ++ default 0x0000000 ++ depends on OPTEE_LIB ++ help ++ The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE ++ runtime. ++ + choice + prompt "MX7 board select" + optional +@@ -91,6 +99,7 @@ + select DM + select DM_SERIAL + select DM_THERMAL ++ select MX7D + imply CMD_DM + + endchoice +diff -ruN u-boot-2021.10/arch/arm/mach-imx/mx7/soc.c u-boot/arch/arm/mach-imx/mx7/soc.c +--- u-boot-2021.10/arch/arm/mach-imx/mx7/soc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/mx7/soc.c 2021-11-01 17:10:13.776285769 +0100 +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -224,7 +225,7 @@ + }; + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* enable all periherial can be accessed in nosec mode */ + static void init_csu(void) + { +@@ -337,10 +338,19 @@ + int arch_misc_init(void) + { + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG ++ struct tag_serialnr serialnr; ++ char serial_string[0x20]; ++ + if (is_mx7d()) + env_set("soc", "imx7d"); + else + env_set("soc", "imx7s"); ++ ++ /* Set serial# standard environment variable based on OTP settings */ ++ get_board_serial(&serialnr); ++ snprintf(serial_string, sizeof(serial_string), "0x%08x%08x", ++ serialnr.low, serialnr.high); ++ env_set("serial#", serial_string); + #endif + + #ifdef CONFIG_FSL_CAAM +@@ -351,7 +361,7 @@ + } + #endif + +-#ifdef CONFIG_SERIAL_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* + * OCOTP_TESTER + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 +@@ -435,4 +445,3 @@ + #endif + #endif + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-imx/mxs/Kconfig u-boot/arch/arm/mach-imx/mxs/Kconfig +--- u-boot-2021.10/arch/arm/mach-imx/mxs/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/mxs/Kconfig 2021-11-01 17:10:13.776285769 +0100 +@@ -3,6 +3,7 @@ + config MX23 + bool + default y ++ select TOOLS_LIBCRYPTO + + choice + prompt "MX23 board select" +@@ -34,14 +35,12 @@ + config MX28 + bool + default y ++ select TOOLS_LIBCRYPTO + + choice + prompt "MX28 board select" + optional + +-config TARGET_BG0900 +- bool "Support bg0900" +- + config TARGET_MX28EVK + bool "Support mx28evk" + select BOARD_EARLY_INIT_F +@@ -56,6 +55,5 @@ + + source "board/freescale/mx28evk/Kconfig" + source "board/liebherr/xea/Kconfig" +-source "board/ppcag/bg0900/Kconfig" + + endif +diff -ruN u-boot-2021.10/arch/arm/mach-imx/spl.c u-boot/arch/arm/mach-imx/spl.c +--- u-boot-2021.10/arch/arm/mach-imx/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/spl.c 2021-11-01 17:10:13.776285769 +0100 +@@ -199,7 +199,7 @@ + } + #endif + +-#if defined(CONFIG_SPL_MMC_SUPPORT) ++#if defined(CONFIG_SPL_MMC) + /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ + u32 spl_mmc_boot_mode(const u32 boot_device) + { +diff -ruN u-boot-2021.10/arch/arm/mach-imx/syscounter.c u-boot/arch/arm/mach-imx/syscounter.c +--- u-boot-2021.10/arch/arm/mach-imx/syscounter.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-imx/syscounter.c 2021-11-01 17:10:13.779618920 +0100 +@@ -59,7 +59,7 @@ + return usec; + } + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + int timer_init(void) + { + struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; +diff -ruN u-boot-2021.10/arch/arm/mach-k3/Kconfig u-boot/arch/arm/mach-k3/Kconfig +--- u-boot-2021.10/arch/arm/mach-k3/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-k3/Kconfig 2021-11-01 17:10:13.779618920 +0100 +@@ -168,4 +168,5 @@ + source "board/ti/am65x/Kconfig" + source "board/ti/am64x/Kconfig" + source "board/ti/j721e/Kconfig" ++source "board/siemens/iot2050/Kconfig" + endif +diff -ruN u-boot-2021.10/arch/arm/mach-k3/sysfw-loader.c u-boot/arch/arm/mach-k3/sysfw-loader.c +--- u-boot-2021.10/arch/arm/mach-k3/sysfw-loader.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-k3/sysfw-loader.c 2021-11-01 17:10:13.779618920 +0100 +@@ -370,7 +370,7 @@ + + /* Load combined System Controller firmware and config data image */ + switch (bootdev.boot_device) { +-#if CONFIG_IS_ENABLED(MMC_SUPPORT) ++#if CONFIG_IS_ENABLED(MMC) + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: +diff -ruN u-boot-2021.10/arch/arm/mach-keystone/include/mach/hardware.h u-boot/arch/arm/mach-keystone/include/mach/hardware.h +--- u-boot-2021.10/arch/arm/mach-keystone/include/mach/hardware.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-keystone/include/mach/hardware.h 2021-11-01 17:10:13.782952071 +0100 +@@ -148,8 +148,8 @@ + #define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 + #define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) + +-#define KS2_UART0_BASE 0x02530c00 +-#define KS2_UART1_BASE 0x02531000 ++#define KS2_UART0_BASE 0x02530c00 ++#define KS2_UART1_BASE 0x02531000 + + /* Boot Config */ + #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +@@ -210,7 +210,7 @@ + #endif + + /* AEMIF */ +-#define KS2_AEMIF_CNTRL_BASE 0x21000a00 ++#define KS2_AEMIF_CNTRL_BASE 0x21000a00 + #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + + /* Flag from ks2_debug options to check if DSPs need to stay ON */ +diff -ruN u-boot-2021.10/arch/arm/mach-keystone/Kconfig u-boot/arch/arm/mach-keystone/Kconfig +--- u-boot-2021.10/arch/arm/mach-keystone/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-keystone/Kconfig 2021-11-01 17:10:13.779618920 +0100 +@@ -6,6 +6,7 @@ + + config TARGET_K2HK_EVM + bool "TI Keystone 2 Kepler/Hawking EVM" ++ select SOC_K2HK + select SPL_BOARD_INIT if SPL + select CMD_DDR3 + imply DM_I2C +@@ -14,6 +15,7 @@ + + config TARGET_K2E_EVM + bool "TI Keystone 2 Edison EVM" ++ select SOC_K2E + select SPL_BOARD_INIT if SPL + select CMD_DDR3 + imply DM_I2C +@@ -22,6 +24,7 @@ + + config TARGET_K2L_EVM + bool "TI Keystone 2 Lamar EVM" ++ select SOC_K2L + select SPL_BOARD_INIT if SPL + select CMD_DDR3 + imply DM_I2C +@@ -31,6 +34,7 @@ + config TARGET_K2G_EVM + bool "TI Keystone 2 Galileo EVM" + select BOARD_LATE_INIT ++ select SOC_K2G + select SPL_BOARD_INIT if SPL + select TI_I2C_BOARD_DETECT + select CMD_DDR3 +@@ -40,6 +44,18 @@ + + endchoice + ++config SOC_K2E ++ bool ++ ++config SOC_K2G ++ bool ++ ++config SOC_K2HK ++ bool ++ ++config SOC_K2L ++ bool ++ + config SYS_SOC + default "keystone" + +diff -ruN u-boot-2021.10/arch/arm/mach-kirkwood/cpu.c u-boot/arch/arm/mach-kirkwood/cpu.c +--- u-boot-2021.10/arch/arm/mach-kirkwood/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-kirkwood/cpu.c 2021-11-01 17:10:13.782952071 +0100 +@@ -278,4 +278,3 @@ + return 0; + } + #endif +- +diff -ruN u-boot-2021.10/arch/arm/mach-kirkwood/include/mach/config.h u-boot/arch/arm/mach-kirkwood/include/mach/config.h +--- u-boot-2021.10/arch/arm/mach-kirkwood/include/mach/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-kirkwood/include/mach/config.h 2021-11-01 17:10:13.782952071 +0100 +@@ -91,18 +91,6 @@ + #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE + #endif /* CONFIG_IDE */ + +-/* +- * I2C related stuff +- */ +-#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) +-#ifndef CONFIG_SYS_I2C_SOFT +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI +-#endif +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif +- + /* Use common timer */ + #define CONFIG_SYS_TIMER_COUNTS_DOWN + #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +diff -ruN u-boot-2021.10/arch/arm/mach-mediatek/Kconfig u-boot/arch/arm/mach-mediatek/Kconfig +--- u-boot-2021.10/arch/arm/mach-mediatek/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mediatek/Kconfig 2021-11-01 17:10:13.782952071 +0100 +@@ -8,7 +8,6 @@ + + config MT8512 + bool "MediaTek MT8512 SoC" +- default n + + choice + prompt "MediaTek board select" +@@ -80,12 +79,40 @@ + + endchoice + +-source "board/mediatek/mt7622/Kconfig" +-source "board/mediatek/mt7623/Kconfig" +-source "board/mediatek/mt7629/Kconfig" +-source "board/mediatek/mt8183/Kconfig" +-source "board/mediatek/mt8512/Kconfig" +-source "board/mediatek/mt8516/Kconfig" +-source "board/mediatek/mt8518/Kconfig" ++config SYS_BOARD ++ string "Board name" ++ default "mt7622" if TARGET_MT7622 ++ default "mt7623" if TARGET_MT7623 ++ default "mt7629" if TARGET_MT7629 ++ default "mt8183" if TARGET_MT8183 ++ default "mt8512" if TARGET_MT8512 ++ default "mt8516" if TARGET_MT8516 ++ default "mt8518" if TARGET_MT8518 ++ default "" ++ help ++ This option contains information about board name. ++ Based on this option board// will ++ be used. ++ ++config SYS_CONFIG_NAME ++ string "Board configuration name" ++ default "mt7622" if TARGET_MT7622 ++ default "mt7623" if TARGET_MT7623 ++ default "mt7629" if TARGET_MT7629 ++ default "mt8183" if TARGET_MT8183 ++ default "mt8512" if TARGET_MT8512 ++ default "mt8516" if TARGET_MT8516 ++ default "mt8518" if TARGET_MT8518 ++ default "" ++ help ++ This option contains information about board configuration name. ++ Based on this option include/configs/.h header ++ will be used for board configuration. ++ ++config MTK_BROM_HEADER_INFO ++ string ++ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 ++ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 ++ default "lk=1" if TARGET_MT7623 + + endif +diff -ruN u-boot-2021.10/arch/arm/mach-mediatek/spl.c u-boot/arch/arm/mach-mediatek/spl.c +--- u-boot-2021.10/arch/arm/mach-mediatek/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mediatek/spl.c 2021-11-01 17:10:13.786285222 +0100 +@@ -31,9 +31,9 @@ + + u32 spl_boot_device(void) + { +-#if defined(CONFIG_SPL_SPI_SUPPORT) ++#if defined(CONFIG_SPL_SPI) + return BOOT_DEVICE_SPI; +-#elif defined(CONFIG_SPL_MMC_SUPPORT) ++#elif defined(CONFIG_SPL_MMC) + return BOOT_DEVICE_MMC1; + #elif defined(CONFIG_SPL_NAND_SUPPORT) + return BOOT_DEVICE_NAND; +diff -ruN u-boot-2021.10/arch/arm/mach-meson/board-info.c u-boot/arch/arm/mach-meson/board-info.c +--- u-boot-2021.10/arch/arm/mach-meson/board-info.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-meson/board-info.c 2021-11-01 17:10:13.786285222 +0100 +@@ -64,6 +64,7 @@ + { "A113X", 0x25, 0x37, 0xff }, + { "A113D", 0x25, 0x22, 0xff }, + { "S905D2", 0x28, 0x10, 0xf0 }, ++ { "S905Y2", 0x28, 0x30, 0xf0 }, + { "S905X2", 0x28, 0x40, 0xf0 }, + { "A311D", 0x29, 0x10, 0xf0 }, + { "S922X", 0x29, 0x40, 0xf0 }, +diff -ruN u-boot-2021.10/arch/arm/mach-mvebu/include/mach/config.h u-boot/arch/arm/mach-mvebu/include/mach/config.h +--- u-boot-2021.10/arch/arm/mach-mvebu/include/mach/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mvebu/include/mach/config.h 2021-11-01 17:10:13.786285222 +0100 +@@ -27,10 +27,6 @@ + + #define CONFIG_SYS_L2_PL310 + +-#ifdef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +-#endif +- + /* + * By default the generated mvebu kwbimage.cfg is used + * If for some board, different configuration file need to be used, +@@ -63,8 +59,6 @@ + #ifndef CONFIG_SYS_I2C_SOFT + #define CONFIG_I2C_MVTWSI + #endif +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + #endif + + /* Use common timer */ +diff -ruN u-boot-2021.10/arch/arm/mach-mvebu/Kconfig u-boot/arch/arm/mach-mvebu/Kconfig +--- u-boot-2021.10/arch/arm/mach-mvebu/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mvebu/Kconfig 2021-11-01 17:10:13.786285222 +0100 +@@ -2,7 +2,6 @@ + + config HAVE_MVEBU_EFUSE + bool +- default n + + config ARMADA_32BIT + bool +@@ -29,6 +28,7 @@ + bool + select ARMADA_32BIT + select HAVE_MVEBU_EFUSE ++ select TOOLS_LIBCRYPTO + + config ARMADA_38X_HS_IMPEDANCE_THRESH + hex "Armada 38x USB 2.0 High-Speed Impedance Threshold (0x0 - 0x7)" +@@ -184,6 +184,33 @@ + + endchoice + ++choice ++ prompt "DDR bus width" ++ default DDR_64BIT ++ depends on ARMADA_XP ++ ++config DDR_64BIT ++ bool "64bit bus width" ++ ++config DDR_32BIT ++ bool "32bit bus width" ++ ++endchoice ++ ++config DDR_LOG_LEVEL ++ int "DDR training code log level" ++ depends on ARMADA_XP ++ default 0 ++ range 0 3 ++ help ++ Amount of information provided on error while running the DDR ++ training code. At level 0, provides an error code in a case of ++ failure, RL, WL errors and other algorithm failure. At level 1, ++ provides the D-Unit setup (SPD/Static configuration). At level 2, ++ provides the windows margin as a results of DQS centeralization. ++ At level 3, rovides the windows margin of each DQ as a results of ++ DQS centeralization. ++ + config SYS_BOARD + default "clearfog" if TARGET_CLEARFOG + default "helios4" if TARGET_HELIOS4 +@@ -256,7 +283,7 @@ + imply SPL_DM_SPI + imply SPL_SPI_FLASH_SUPPORT + imply SPL_SPI_LOAD +- imply SPL_SPI_SUPPORT ++ imply SPL_SPI + select SPL_BOOTROM_SUPPORT + + config MVEBU_SPL_BOOT_DEVICE_MMC +@@ -267,12 +294,12 @@ + imply SPL_DM_MMC + imply SPL_GPIO + imply SPL_LIBDISK_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + select SPL_BOOTROM_SUPPORT + + config MVEBU_SPL_BOOT_DEVICE_SATA + bool "SATA" +- imply SPL_SATA_SUPPORT ++ imply SPL_SATA + imply SPL_LIBDISK_SUPPORT + select SPL_BOOTROM_SUPPORT + +@@ -284,14 +311,12 @@ + + config MVEBU_EFUSE + bool "Enable eFuse support" +- default n + depends on HAVE_MVEBU_EFUSE + help + Enable support for reading and writing eFuses on mvebu SoCs. + + config MVEBU_EFUSE_FAKE + bool "Fake eFuse access (dry run)" +- default n + depends on MVEBU_EFUSE + help + This enables a "dry run" mode where eFuses are not really programmed. +diff -ruN u-boot-2021.10/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c u-boot/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +--- u-boot-2021.10/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c 2021-11-01 17:10:13.786285222 +0100 +@@ -14,8 +14,6 @@ + #include "sys_env_lib.h" + #include "ctrl_pex.h" + +- +- + /* + * serdes_seq_db - holds all serdes sequences, their size and the + * relevant index in the data array initialized in serdes_seq_init +diff -ruN u-boot-2021.10/arch/arm/mach-mvebu/spl.c u-boot/arch/arm/mach-mvebu/spl.c +--- u-boot-2021.10/arch/arm/mach-mvebu/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-mvebu/spl.c 2021-11-01 17:10:13.789618373 +0100 +@@ -17,7 +17,8 @@ + #include + #include + +-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC_SUPPORT) || defined(CONFIG_SPL_SATA_SUPPORT) ++#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \ ++ defined(CONFIG_SPL_SATA) + + /* + * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must +@@ -39,7 +40,7 @@ + * and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the + * kwbimage main header. + */ +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported + #endif +@@ -56,7 +57,7 @@ + * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be + * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper. + */ +-#ifdef CONFIG_SPL_SATA_SUPPORT ++#ifdef CONFIG_SPL_SATA + #if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 + #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1 + #endif +@@ -92,7 +93,7 @@ + uint8_t checksum; /* 0x1F */ + } __packed; + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + u32 spl_mmc_boot_mode(const u32 boot_device) + { + return MMCSD_MODE_RAW; +@@ -121,10 +122,10 @@ + #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT + mhdr->blockid != IBR_HDR_SPI_ID && + #endif +-#ifdef CONFIG_SPL_SATA_SUPPORT ++#ifdef CONFIG_SPL_SATA + mhdr->blockid != IBR_HDR_SATA_ID && + #endif +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + mhdr->blockid != IBR_HDR_SDIO_ID && + #endif + 1 +@@ -135,7 +136,7 @@ + + spl_image->offset = mhdr->srcaddr; + +-#ifdef CONFIG_SPL_SATA_SUPPORT ++#ifdef CONFIG_SPL_SATA + /* + * For SATA srcaddr is specified in number of sectors. + * The main header is must be stored at sector number 1. +@@ -152,7 +153,7 @@ + } + #endif + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + /* + * For SDIO (eMMC) srcaddr is specified in number of sectors. + * This expects that sector size is 512 bytes and recalculates +@@ -193,11 +194,11 @@ + * If SPL is compiled with chosen boot_device support + * then use SPL driver for loading U-Boot proper. + */ +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + case BOOT_DEVICE_MMC1: + return BOOT_DEVICE_MMC1; + #endif +-#ifdef CONFIG_SPL_SATA_SUPPORT ++#ifdef CONFIG_SPL_SATA + case BOOT_FROM_SATA: + return BOOT_FROM_SATA; + #endif +diff -ruN u-boot-2021.10/arch/arm/mach-octeontx/Makefile u-boot/arch/arm/mach-octeontx/Makefile +--- u-boot-2021.10/arch/arm/mach-octeontx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-octeontx/Makefile 2021-11-01 17:10:13.789618373 +0100 +@@ -6,4 +6,3 @@ + # */ + + obj-y += lowlevel_init.o clock.o cpu.o +- +diff -ruN u-boot-2021.10/arch/arm/mach-octeontx2/Makefile u-boot/arch/arm/mach-octeontx2/Makefile +--- u-boot-2021.10/arch/arm/mach-octeontx2/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-octeontx2/Makefile 2021-11-01 17:10:13.789618373 +0100 +@@ -6,4 +6,3 @@ + # */ + + obj-y += lowlevel_init.o clock.o cpu.o +- +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/am33xx/board.c u-boot/arch/arm/mach-omap2/am33xx/board.c +--- u-boot-2021.10/arch/arm/mach-omap2/am33xx/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/am33xx/board.c 2021-11-01 17:10:13.789618373 +0100 +@@ -65,7 +65,7 @@ + + int dram_init(void) + { +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + sdram_init(); + #endif + +@@ -351,7 +351,7 @@ + + #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) +@@ -599,7 +599,7 @@ + int arch_cpu_init_dm(void) + { + hw_data_init(); +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + early_system_init(); + #endif + return 0; +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/am33xx/chilisom.c u-boot/arch/arm/mach-omap2/am33xx/chilisom.c +--- u-boot-2021.10/arch/arm/mach-omap2/am33xx/chilisom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/am33xx/chilisom.c 2021-11-01 17:10:13.789618373 +0100 +@@ -22,7 +22,7 @@ + #include + #include + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +@@ -182,4 +182,4 @@ + &ddr3_chilisom_emif_reg_data, 0); + } + +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/am33xx/Kconfig u-boot/arch/arm/mach-omap2/am33xx/Kconfig +--- u-boot-2021.10/arch/arm/mach-omap2/am33xx/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/am33xx/Kconfig 2021-11-01 17:10:13.789618373 +0100 +@@ -46,12 +46,12 @@ + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SPL_NAND_SUPPORT + imply SPL_OF_LIBFDT + imply SPL_POWER + imply SPL_SEPARATE_BSS +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_SYS_MALLOC_SIMPLE + imply SPL_WATCHDOG + imply SPL_YMODEM_SUPPORT +@@ -230,10 +230,10 @@ + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SPL_NAND_SUPPORT + imply SPL_POWER +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_WATCHDOG + imply SPL_YMODEM_SUPPORT + help +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/am33xx/Makefile u-boot/arch/arm/mach-omap2/am33xx/Makefile +--- u-boot-2021.10/arch/arm/mach-omap2/am33xx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/am33xx/Makefile 2021-11-01 17:10:13.789618373 +0100 +@@ -13,7 +13,7 @@ + obj-$(CONFIG_TI816X) += clock_ti816x.o + obj-y += sys_info.o + obj-y += ddr.o +-ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y += emif4.o + endif + obj-$(CONFIG_TI816X) += ti816x_emif4.o +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/boot-common.c u-boot/arch/arm/mach-omap2/boot-common.c +--- u-boot-2021.10/arch/arm/mach-omap2/boot-common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/boot-common.c 2021-11-01 17:10:13.792951524 +0100 +@@ -203,7 +203,7 @@ + gpmc_init(); + #endif + #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C) +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + #endif + #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW) + arch_misc_init(); +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/clocks-common.c u-boot/arch/arm/mach-omap2/clocks-common.c +--- u-boot-2021.10/arch/arm/mach-omap2/clocks-common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/clocks-common.c 2021-11-01 17:10:13.792951524 +0100 +@@ -552,7 +552,7 @@ + if (pv->value[opp]) { + /* Handle non-empty members only */ + pv->value[opp] = optimize_vcore_voltage(pv, opp); +- px = (struct volts *)vcores; ++ px = (struct volts *)vcores; + j = 0; + while (px < pv) { + /* +@@ -918,8 +918,8 @@ + static int gpi2c = 1; + + if (gpi2c) { +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, +- CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } + } +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/Kconfig u-boot/arch/arm/mach-omap2/Kconfig +--- u-boot-2021.10/arch/arm/mach-omap2/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/Kconfig 2021-11-01 17:10:13.789618373 +0100 +@@ -20,11 +20,11 @@ + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SPL_NAND_SUPPORT + imply SPL_OMAP3_ID_NAND + imply SPL_POWER +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SYS_I2C_OMAP24XX + imply SYS_THUMB_BUILD + imply TWL4030_POWER +@@ -42,11 +42,11 @@ + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SPL_NAND_SIMPLE + imply SPL_NAND_SUPPORT + imply SPL_POWER +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SYS_I2C_OMAP24XX + imply SYS_THUMB_BUILD + +@@ -66,12 +66,12 @@ + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_MMC_SUPPORT ++ imply SPL_MMC + imply SPL_NAND_AM33XX_BCH + imply SPL_NAND_AM33XX_BCH + imply SPL_NAND_SUPPORT + imply SPL_POWER +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SYS_I2C_OMAP24XX + + config TI814X +@@ -120,6 +120,7 @@ + select SPECIFY_CONSOLE_INDEX + imply NAND_OMAP_ELM + imply NAND_OMAP_GPMC ++ imply SKIP_LOWLEVEL_INIT + imply SPL_NAND_AM33XX_BCH + imply SPL_NAND_SUPPORT + imply SYS_I2C_OMAP24XX +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/omap3/board.c u-boot/arch/arm/mach-omap2/omap3/board.c +--- u-boot-2021.10/arch/arm/mach-omap2/omap3/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/omap3/board.c 2021-11-01 17:10:13.792951524 +0100 +@@ -76,8 +76,8 @@ + hw_data_init(); + } + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ +- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ ++ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + + /****************************************************************************** + * Routine: secure_unlock +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/omap3/lowlevel_init.S u-boot/arch/arm/mach-omap2/omap3/lowlevel_init.S +--- u-boot-2021.10/arch/arm/mach-omap2/omap3/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/omap3/lowlevel_init.S 2021-11-01 17:10:13.792951524 +0100 +@@ -170,8 +170,8 @@ + go_to_speed_end: + #endif + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ +- !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ ++ !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) + ENTRY(lowlevel_init) + ldr sp, SRAM_STACK + str ip, [sp] /* stash ip register */ +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/omap5/prcm-regs.c u-boot/arch/arm/mach-omap2/omap5/prcm-regs.c +--- u-boot-2021.10/arch/arm/mach-omap2/omap5/prcm-regs.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/omap5/prcm-regs.c 2021-11-01 17:10:13.796284675 +0100 +@@ -300,7 +300,7 @@ + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, +- .control_phy_power_usb = 0x4A002370, ++ .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, + .control_padconf_core_base = 0x4A002800, + .control_paconf_global = 0x4A002DA0, +diff -ruN u-boot-2021.10/arch/arm/mach-omap2/pipe3-phy.c u-boot/arch/arm/mach-omap2/pipe3-phy.c +--- u-boot-2021.10/arch/arm/mach-omap2/pipe3-phy.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-omap2/pipe3-phy.c 2021-11-01 17:10:13.796284675 +0100 +@@ -229,4 +229,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-orion5x/Makefile u-boot/arch/arm/mach-orion5x/Makefile +--- u-boot-2021.10/arch/arm/mach-orion5x/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-orion5x/Makefile 2021-11-01 17:10:13.796284675 +0100 +@@ -11,7 +11,7 @@ + obj-y += dram.o + obj-y += timer.o + +-ifndef CONFIG_SKIP_LOWLEVEL_INIT ++ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT + obj-y += lowlevel_init.o + endif + +diff -ruN u-boot-2021.10/arch/arm/mach-orion5x/timer.c u-boot/arch/arm/mach-orion5x/timer.c +--- u-boot-2021.10/arch/arm/mach-orion5x/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-orion5x/timer.c 2021-11-01 17:10:13.796284675 +0100 +@@ -69,7 +69,7 @@ + #define TVR_ARM_TIMER_OFFS 0 + #define TVR_ARM_TIMER_MASK 0xffffffff + #define TVR_ARM_TIMER_MAX 0xffffffff +-#define TIMER_LOAD_VAL 0xffffffff ++#define TIMER_LOAD_VAL 0xffffffff + + static inline ulong read_timer(void) + { +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7790.h u-boot/arch/arm/mach-rmobile/include/mach/r8a7790.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7790.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/r8a7790.h 2021-11-01 17:10:13.799617826 +0100 +@@ -10,10 +10,6 @@ + + #include "rcar-base.h" + +-/* SH-I2C */ +-#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +-#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 +- + /* Module stop control/status register bits */ + #define MSTP0_BITS 0x00640801 + #define MSTP1_BITS 0xDB6E9BDF +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7791.h u-boot/arch/arm/mach-rmobile/include/mach/r8a7791.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7791.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/r8a7791.h 2021-11-01 17:10:13.799617826 +0100 +@@ -13,9 +13,6 @@ + * R-Car (R8A7791) I/O Addresses + */ + +-/* SH-I2C */ +-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +- + /* SDHI */ + #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 + #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7792.h u-boot/arch/arm/mach-rmobile/include/mach/r8a7792.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7792.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/r8a7792.h 2021-11-01 17:10:13.799617826 +0100 +@@ -10,10 +10,6 @@ + + #include "rcar-base.h" + +-/* SH-I2C */ +-#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +-#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 +- + /* Module stop control/status register bits */ + #define MSTP0_BITS 0x00400801 + #define MSTP1_BITS 0x9B6F987F +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7793.h u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7793.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h 2021-11-01 17:10:13.799617826 +0100 +@@ -14,9 +14,6 @@ + * R8A7793 I/O Addresses + */ + +-/* SH-I2C */ +-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +- + /* SDHI */ + #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 + #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7794.h u-boot/arch/arm/mach-rmobile/include/mach/r8a7794.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/r8a7794.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/r8a7794.h 2021-11-01 17:10:13.799617826 +0100 +@@ -10,9 +10,6 @@ + + #include "rcar-base.h" + +-/* SH-I2C */ +-#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +- + /* Module stop control/status register bits */ + #define MSTP0_BITS 0x00440801 + #define MSTP1_BITS 0x936899DA +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/rcar-base.h u-boot/arch/arm/mach-rmobile/include/mach/rcar-base.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/rcar-base.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/rcar-base.h 2021-11-01 17:10:13.799617826 +0100 +@@ -70,14 +70,6 @@ + #define SMSTPCR10 0xE6150998 + #define SMSTPCR11 0xE615099C + +-/* +- * SH-I2C +- * Ch2 and ch3 are different address. These are defined +- * in the header of each SoCs. +- */ +-#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +-#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 +- + /* RCAR-I2C */ + #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 + #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h u-boot/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +--- u-boot-2021.10/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 2021-11-01 17:10:13.799617826 +0100 +@@ -74,9 +74,6 @@ + #define PUEN_USB1_OVC (1 << 2) + #define PUEN_USB1_PWEN (1 << 1) + +-/* IICDVFS (I2C) */ +-#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 +- + #ifndef __ASSEMBLY__ + #include + #include +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/Kconfig u-boot/arch/arm/mach-rmobile/Kconfig +--- u-boot-2021.10/arch/arm/mach-rmobile/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/Kconfig 2021-11-01 17:10:13.796284675 +0100 +@@ -29,7 +29,7 @@ + imply SPL_GZIP + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_SYS_MALLOC_SIMPLE + imply SPL_TINY_MEMSET + imply SPL_YMODEM_SUPPORT +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/Kconfig.32 u-boot/arch/arm/mach-rmobile/Kconfig.32 +--- u-boot-2021.10/arch/arm/mach-rmobile/Kconfig.32 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/Kconfig.32 2021-11-01 17:10:13.796284675 +0100 +@@ -133,7 +133,6 @@ + config RMOBILE_EXTRAM_BOOT + bool "Enable boot from RAM" + depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT +- default n + + choice + prompt "Qos setting primary" +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/Kconfig.64 u-boot/arch/arm/mach-rmobile/Kconfig.64 +--- u-boot-2021.10/arch/arm/mach-rmobile/Kconfig.64 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/Kconfig.64 2021-11-01 17:10:13.796284675 +0100 +@@ -4,61 +4,73 @@ + + config R8A774A1 + bool "Renesas SoC R8A774A1" ++ select GICV2 + imply CLK_R8A774A1 + imply PINCTRL_PFC_R8A774A1 + + config R8A774B1 + bool "Renesas SoC R8A774B1" ++ select GICV2 + imply CLK_R8A774B1 + imply PINCTRL_PFC_R8A774B1 + + config R8A774C0 + bool "Renesas SoC R8A774C0" ++ select GICV2 + imply CLK_R8A774C0 + imply PINCTRL_PFC_R8A774C0 + + config R8A774E1 + bool "Renesas SoC R8A774E1" ++ select GICV2 + imply CLK_R8A774E1 + imply PINCTRL_PFC_R8A774E1 + + config R8A7795 + bool "Renesas SoC R8A7795" ++ select GICV2 + imply CLK_R8A7795 + imply PINCTRL_PFC_R8A7795 + + config R8A7796 + bool "Renesas SoC R8A7796" ++ select GICV2 + imply CLK_R8A7796 + imply PINCTRL_PFC_R8A7796 + + config R8A77965 + bool "Renesas SoC R8A77965" ++ select GICV2 + imply CLK_R8A77965 + imply PINCTRL_PFC_R8A77965 + + config R8A77970 + bool "Renesas SoC R8A77970" ++ select GICV2 + imply CLK_R8A77970 + imply PINCTRL_PFC_R8A77970 + + config R8A77980 + bool "Renesas SoC R8A77980" ++ select GICV2 + imply CLK_R8A77980 + imply PINCTRL_PFC_R8A77980 + + config R8A77990 + bool "Renesas SoC R8A77990" ++ select GICV2 + imply CLK_R8A77990 + imply PINCTRL_PFC_R8A77990 + + config R8A77995 + bool "Renesas SoC R8A77995" ++ select GICV2 + imply CLK_R8A77995 + imply PINCTRL_PFC_R8A77995 + + config R8A779A0 + bool "Renesas SoC R8A779A0" ++ select GICV3 + imply CLK_R8A779A0 + imply PINCTRL_PFC_R8A779A0 + +diff -ruN u-boot-2021.10/arch/arm/mach-rmobile/pfc-r8a7790.h u-boot/arch/arm/mach-rmobile/pfc-r8a7790.h +--- u-boot-2021.10/arch/arm/mach-rmobile/pfc-r8a7790.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rmobile/pfc-r8a7790.h 2021-11-01 17:10:13.799617826 +0100 +@@ -82,7 +82,7 @@ + PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) + + #define CPU_32_PORT0_16(fn, pfx, sfx) \ +- PORT_10(fn, pfx, sfx), \ ++ PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \ +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/Kconfig u-boot/arch/arm/mach-rockchip/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/Kconfig 2021-11-01 17:10:13.799617826 +0100 +@@ -11,8 +11,8 @@ + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + imply SPL_SEPARATE_BSS +- select SPL_SERIAL_SUPPORT +- select TPL_SERIAL_SUPPORT ++ select SPL_SERIAL ++ select TPL_SERIAL + select DEBUG_UART_BOARD_INIT + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD +@@ -84,9 +84,9 @@ + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_DRIVERS_MISC + imply ROCKCHIP_COMMON_BOARD +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_ROCKCHIP_COMMON_BOARD +- imply TPL_SERIAL_SUPPORT ++ imply TPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT +@@ -100,6 +100,7 @@ + bool "Support Rockchip RK3288" + select CPU_V7A + select OF_BOARD_SETUP ++ select SKIP_LOWLEVEL_INIT_ONLY + select SUPPORT_SPL + select SPL + select SUPPORT_TPL +@@ -118,7 +119,7 @@ + imply TPL_RAM + imply TPL_REGMAP + imply TPL_ROCKCHIP_COMMON_BOARD +- imply TPL_SERIAL_SUPPORT ++ imply TPL_SERIAL + imply TPL_SYSCON + imply USB_FUNCTION_ROCKUSB + imply CMD_ROCKUSB +@@ -145,8 +146,8 @@ + imply SPL_REGMAP + imply SPL_SYSCON + imply SPL_RAM +- imply SPL_SERIAL_SUPPORT +- imply TPL_SERIAL_SUPPORT ++ imply SPL_SERIAL ++ imply TPL_SERIAL + imply SPL_SEPARATE_BSS + help + The Rockchip RK3308 is a ARM-based Soc which embedded with quad +@@ -164,8 +165,8 @@ + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_SDRAM_COMMON + imply SPL_ROCKCHIP_COMMON_BOARD +- imply SPL_SERIAL_SUPPORT +- imply TPL_SERIAL_SUPPORT ++ imply SPL_SERIAL ++ imply TPL_SERIAL + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT +@@ -187,8 +188,8 @@ + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SEPARATE_BSS +- imply SPL_SERIAL_SUPPORT +- imply TPL_SERIAL_SUPPORT ++ imply SPL_SERIAL ++ imply TPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + help + The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised +@@ -218,7 +219,7 @@ + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_SEPARATE_BSS +- select SPL_SERIAL_SUPPORT ++ select SPL_SERIAL + select SPL_DRIVERS_MISC + select CLK + select FIT +@@ -234,7 +235,7 @@ + imply ROCKCHIP_SDRAM_COMMON + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_ROCKCHIP_COMMON_BOARD +- imply TPL_SERIAL_SUPPORT ++ imply TPL_SERIAL + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SYS_MALLOC_SIMPLE +@@ -381,7 +382,7 @@ + This enables support code in the BOOT0 hook for the TPL stage + to allow multiple entries. + +-config SPL_MMC_SUPPORT ++config SPL_MMC + default y if !SPL_ROCKCHIP_BACK_TO_BROM + + config ROCKCHIP_SPI_IMAGE +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/px30/Kconfig u-boot/arch/arm/mach-rockchip/px30/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/px30/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/px30/Kconfig 2021-11-01 17:10:13.799617826 +0100 +@@ -36,7 +36,7 @@ + config SYS_MALLOC_F_LEN + default 0x400 + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config TPL_LDSCRIPT +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/px30-board-tpl.c u-boot/arch/arm/mach-rockchip/px30-board-tpl.c +--- u-boot-2021.10/arch/arm/mach-rockchip/px30-board-tpl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/px30-board-tpl.c 2021-11-01 17:10:13.799617826 +0100 +@@ -9,7 +9,6 @@ + #include + #include + #include +-#include + #include + #include + #include +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3036/Kconfig u-boot/arch/arm/mach-rockchip/rk3036/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3036/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3036/Kconfig 2021-11-01 17:10:13.802950977 +0100 +@@ -22,7 +22,7 @@ + config SYS_MALLOC_F_LEN + default 0x400 + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + source "board/rockchip/evb_rk3036/Kconfig" +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3188/Kconfig u-boot/arch/arm/mach-rockchip/rk3188/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3188/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3188/Kconfig 2021-11-01 17:10:13.802950977 +0100 +@@ -24,7 +24,7 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config TPL_LIBCOMMON_SUPPORT +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3188/rk3188.c u-boot/arch/arm/mach-rockchip/rk3188/rk3188.c +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3188/rk3188.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3188/rk3188.c 2021-11-01 17:10:13.802950977 +0100 +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + + #define GRF_BASE 0x20008000 +@@ -107,7 +108,6 @@ + } + + #ifdef CONFIG_SPL_BUILD +-DECLARE_GLOBAL_DATA_PTR; + static int setup_led(void) + { + #ifdef CONFIG_SPL_LED +@@ -115,7 +115,7 @@ + char *led_name; + int ret; + +- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); ++ led_name = ofnode_conf_read_str("u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk322x/Kconfig u-boot/arch/arm/mach-rockchip/rk322x/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/rk322x/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk322x/Kconfig 2021-11-01 17:10:13.802950977 +0100 +@@ -20,7 +20,7 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config TPL_MAX_SIZE +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3288/Kconfig u-boot/arch/arm/mach-rockchip/rk3288/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3288/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3288/Kconfig 2021-11-01 17:10:13.802950977 +0100 +@@ -163,7 +163,7 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config TPL_LDSCRIPT +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3308/Kconfig u-boot/arch/arm/mach-rockchip/rk3308/Kconfig +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3308/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3308/Kconfig 2021-11-01 17:10:13.802950977 +0100 +@@ -14,7 +14,7 @@ + config SYS_MALLOC_F_LEN + default 0x400 + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config ROCKCHIP_BOOT_MODE_REG +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3368/Makefile u-boot/arch/arm/mach-rockchip/rk3368/Makefile +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3368/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3368/Makefile 2021-11-01 17:10:13.802950977 +0100 +@@ -3,4 +3,4 @@ + # Copyright (c) 2016 Andreas Färber + obj-y += clk_rk3368.o + obj-y += rk3368.o +-obj-y += syscon_rk3368.o ++obj-y += syscon_rk3368.o +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c u-boot/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c 2021-11-01 17:10:13.802950977 +0100 +@@ -21,7 +21,7 @@ + U_BOOT_DRIVER(syscon_rk3399) = { + .name = "rk3399_syscon", + .id = UCLASS_SYSCON, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .of_match = rk3399_syscon_ids, +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c u-boot/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c +--- u-boot-2021.10/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c 2021-11-01 17:10:13.802950977 +0100 +@@ -18,7 +18,7 @@ + .name = "rk3568_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3568_syscon_ids, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/sdram.c u-boot/arch/arm/mach-rockchip/sdram.c +--- u-boot-2021.10/arch/arm/mach-rockchip/sdram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/sdram.c 2021-11-01 17:10:13.802950977 +0100 +@@ -45,7 +45,7 @@ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + #else +-#ifdef CONFIG_SPL_OPTEE ++#ifdef CONFIG_SPL_OPTEE_IMAGE + struct tos_parameter_t *tos_parameter; + + tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + +diff -ruN u-boot-2021.10/arch/arm/mach-rockchip/tpl.c u-boot/arch/arm/mach-rockchip/tpl.c +--- u-boot-2021.10/arch/arm/mach-rockchip/tpl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-rockchip/tpl.c 2021-11-01 17:10:13.802950977 +0100 +@@ -16,6 +16,10 @@ + #include + #include + ++#if CONFIG_IS_ENABLED(BANNER_PRINT) ++#include ++#endif ++ + #define TIMER_LOAD_COUNT_L 0x00 + #define TIMER_LOAD_COUNT_H 0x04 + #define TIMER_CONTROL_REG 0x10 +@@ -48,7 +52,7 @@ + struct udevice *dev; + int ret; + +-#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) ++#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL) + /* + * Debug UART can be used from here if required: + * +diff -ruN u-boot-2021.10/arch/arm/mach-s5pc1xx/include/mach/sromc.h u-boot/arch/arm/mach-s5pc1xx/include/mach/sromc.h +--- u-boot-2021.10/arch/arm/mach-s5pc1xx/include/mach/sromc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-s5pc1xx/include/mach/sromc.h 2021-11-01 17:10:13.802950977 +0100 +@@ -4,9 +4,9 @@ + * Naveen Krishna Ch + * + * Note: This file contains the register description for Memory subsystem +- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. ++ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * +- * Only SROMC is defined as of now ++ * Only SROMC is defined as of now + */ + + #ifndef __ASM_ARCH_SROMC_H_ +diff -ruN u-boot-2021.10/arch/arm/mach-snapdragon/dram.c u-boot/arch/arm/mach-snapdragon/dram.c +--- u-boot-2021.10/arch/arm/mach-snapdragon/dram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-snapdragon/dram.c 2021-11-01 17:10:13.806284128 +0100 +@@ -97,4 +97,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-snapdragon/misc.c u-boot/arch/arm/mach-snapdragon/misc.c +--- u-boot-2021.10/arch/arm/mach-snapdragon/misc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-snapdragon/misc.c 2021-11-01 17:10:13.806284128 +0100 +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + /* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ + #define UNSTUFF_BITS(resp, start, size) \ +@@ -33,21 +34,22 @@ + if (!mmc_dev) + return 0; + ++ if (mmc_init(mmc_dev)) ++ return 0; ++ + return UNSTUFF_BITS(mmc_dev->cid, 16, 32); + } + + void msm_generate_mac_addr(u8 *mac) + { +- int i; +- char sn[9]; +- +- snprintf(sn, 9, "%08x", msm_board_serial()); +- +- /* fill in the mac with serialno, use locally adminstrated pool */ ++ /* use locally adminstrated pool */ + mac[0] = 0x02; +- mac[1] = 00; +- for (i = 3; i >= 0; i--) { +- mac[i + 2] = hextoul(&sn[2 * i], NULL); +- sn[2 * i] = 0; +- } ++ mac[1] = 0x00; ++ ++ /* ++ * Put the 32-bit serial number in the last 32-bit of the MAC address. ++ * Use big endian order so it is consistent with the serial number ++ * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd ++ */ ++ put_unaligned_be32(msm_board_serial(), &mac[2]); + } +diff -ruN u-boot-2021.10/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +--- u-boot-2021.10/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 2021-11-01 17:10:13.806284128 +0100 +@@ -14,8 +14,8 @@ + + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) +-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) ++#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) ++#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) +@@ -26,9 +26,9 @@ + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) +-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) ++#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) ++#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) ++#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ +@@ -50,9 +50,9 @@ + #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) + #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) + +-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 ++#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) ++#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) ++#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 + #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) + #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 + +diff -ruN u-boot-2021.10/arch/arm/mach-socfpga/spl_a10.c u-boot/arch/arm/mach-socfpga/spl_a10.c +--- u-boot-2021.10/arch/arm/mach-socfpga/spl_a10.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-socfpga/spl_a10.c 2021-11-01 17:10:13.809617279 +0100 +@@ -93,7 +93,7 @@ + } + } + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + u32 spl_mmc_boot_mode(const u32 boot_device) + { + #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +diff -ruN u-boot-2021.10/arch/arm/mach-socfpga/spl_gen5.c u-boot/arch/arm/mach-socfpga/spl_gen5.c +--- u-boot-2021.10/arch/arm/mach-socfpga/spl_gen5.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-socfpga/spl_gen5.c 2021-11-01 17:10:13.809617279 +0100 +@@ -52,7 +52,7 @@ + } + } + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + u32 spl_mmc_boot_mode(const u32 boot_device) + { + #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +diff -ruN u-boot-2021.10/arch/arm/mach-socfpga/spl_soc64.c u-boot/arch/arm/mach-socfpga/spl_soc64.c +--- u-boot-2021.10/arch/arm/mach-socfpga/spl_soc64.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-socfpga/spl_soc64.c 2021-11-01 17:10:13.809617279 +0100 +@@ -14,7 +14,7 @@ + return BOOT_DEVICE_MMC1; + } + +-#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT) ++#if IS_ENABLED(CONFIG_SPL_MMC) + u32 spl_boot_mode(const u32 boot_device) + { + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) +diff -ruN u-boot-2021.10/arch/arm/mach-stm32/Kconfig u-boot/arch/arm/mach-stm32/Kconfig +--- u-boot-2021.10/arch/arm/mach-stm32/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-stm32/Kconfig 2021-11-01 17:10:13.809617279 +0100 +@@ -41,7 +41,7 @@ + select SPL_OF_TRANSLATE + select SPL_PINCTRL + select SPL_RAM +- select SPL_SERIAL_SUPPORT ++ select SPL_SERIAL + select SPL_SYS_MALLOC_SIMPLE + select SPL_TIMER + select SPL_XIP_SUPPORT +diff -ruN u-boot-2021.10/arch/arm/mach-stm32mp/fdt.c u-boot/arch/arm/mach-stm32mp/fdt.c +--- u-boot-2021.10/arch/arm/mach-stm32mp/fdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-stm32mp/fdt.c 2021-11-01 17:10:13.812950431 +0100 +@@ -341,7 +341,6 @@ + * when FIP is not used by TF-A + */ + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && +- CONFIG_IS_ENABLED(OPTEE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + +diff -ruN u-boot-2021.10/arch/arm/mach-stm32mp/Kconfig u-boot/arch/arm/mach-stm32mp/Kconfig +--- u-boot-2021.10/arch/arm/mach-stm32mp/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-stm32mp/Kconfig 2021-11-01 17:10:13.809617279 +0100 +@@ -15,14 +15,14 @@ + select SPL_PINCTRL + select SPL_REGMAP + select SPL_DM_RESET +- select SPL_SERIAL_SUPPORT ++ select SPL_SERIAL + select SPL_SYSCON + select SPL_WATCHDOG if WATCHDOG + imply BOOTSTAGE_STASH if SPL_BOOTSTAGE + imply SPL_BOOTSTAGE if BOOTSTAGE + imply SPL_DISPLAY_PRINT + imply SPL_LIBDISK_SUPPORT +- imply SPL_SPI_LOAD if SPL_SPI_SUPPORT ++ imply SPL_SPI_LOAD if SPL_SPI + + config SYS_SOC + default "stm32mp" +@@ -190,7 +190,6 @@ + + config CMD_STM32KEY + bool "command stm32key to fuse public key hash" +- default n + help + fuse public key hash in corresponding fuse used to authenticate + binary. +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/board.c u-boot/arch/arm/mach-sunxi/board.c +--- u-boot-2021.10/arch/arm/mach-sunxi/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/board.c 2021-11-01 17:10:13.812950431 +0100 +@@ -21,7 +21,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -79,6 +78,7 @@ + static int gpio_init(void) + { + __maybe_unused uint val; ++#if !CONFIG_IS_ENABLED(DM_SERIAL) + #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) + #if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ +@@ -161,6 +161,7 @@ + #else + #error Unsupported console port number. Please fix pin mux settings in board.c + #endif ++#endif + + #ifdef CONFIG_SUN50I_GEN_H6 + /* Update PIO power bias configuration by copy hardware detected value */ +@@ -244,12 +245,28 @@ + + #define SUNXI_INVALID_BOOT_SOURCE -1 + ++static int sunxi_egon_valid(struct boot_file_head *egon_head) ++{ ++ return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */ ++} ++ ++static int sunxi_toc0_valid(struct toc0_main_info *toc0_info) ++{ ++ return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */ ++} ++ + static int sunxi_get_boot_source(void) + { +- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ +- return SUNXI_INVALID_BOOT_SOURCE; ++ struct boot_file_head *egon_head = (void *)SPL_ADDR; ++ struct toc0_main_info *toc0_info = (void *)SPL_ADDR; ++ ++ if (sunxi_egon_valid(egon_head)) ++ return readb(&egon_head->boot_media); ++ if (sunxi_toc0_valid(toc0_info)) ++ return readb(&toc0_info->platform[0]); + +- return readb(SPL_ADDR + 0x28); ++ /* Not a valid image, so we must have been booted via FEL. */ ++ return SUNXI_INVALID_BOOT_SOURCE; + } + + /* The sunxi internal brom will try to loader external bootloader +@@ -297,10 +314,16 @@ + #ifdef CONFIG_SPL_BUILD + static u32 sunxi_get_spl_size(void) + { +- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ +- return 0; ++ struct boot_file_head *egon_head = (void *)SPL_ADDR; ++ struct toc0_main_info *toc0_info = (void *)SPL_ADDR; ++ ++ if (sunxi_egon_valid(egon_head)) ++ return readl(&egon_head->length); ++ if (sunxi_toc0_valid(toc0_info)) ++ return readl(&toc0_info->length); + +- return readl(SPL_ADDR + 0x10); ++ /* Not a valid image, so use the default U-Boot offset. */ ++ return 0; + } + + /* +@@ -347,6 +370,7 @@ + } + #endif + ++#if !CONFIG_IS_ENABLED(SYSRESET) + void reset_cpu(void) + { + #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) +@@ -377,6 +401,7 @@ + while (1) { } + #endif + } ++#endif + + #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) + void enable_caches(void) +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/clock.c u-boot/arch/arm/mach-sunxi/clock.c +--- u-boot-2021.10/arch/arm/mach-sunxi/clock.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/clock.c 2021-11-01 17:10:13.812950431 +0100 +@@ -10,7 +10,6 @@ + #include + #include + #include +-#include + #include + #include + #include +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/clock_sun4i.c u-boot/arch/arm/mach-sunxi/clock_sun4i.c +--- u-boot-2021.10/arch/arm/mach-sunxi/clock_sun4i.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/clock_sun4i.c 2021-11-01 17:10:13.812950431 +0100 +@@ -12,7 +12,6 @@ + #include + #include + #include +-#include + #include + + #ifdef CONFIG_SPL_BUILD +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/dram_sun4i.c u-boot/arch/arm/mach-sunxi/dram_sun4i.c +--- u-boot-2021.10/arch/arm/mach-sunxi/dram_sun4i.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/dram_sun4i.c 2021-11-01 17:10:13.812950431 +0100 +@@ -279,7 +279,7 @@ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); +- } else { ++ } else { + /* any other frequency that is a multiple of 24 */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/dram_sun8i_a33.c u-boot/arch/arm/mach-sunxi/dram_sun8i_a33.c +--- u-boot-2021.10/arch/arm/mach-sunxi/dram_sun8i_a33.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/dram_sun8i_a33.c 2021-11-01 17:10:13.816283581 +0100 +@@ -126,8 +126,8 @@ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ +- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ +- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ ++ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ ++ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* Set work mode register */ + mctl_set_cr(para); +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c u-boot/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +--- u-boot-2021.10/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c 2021-11-01 17:10:13.816283581 +0100 +@@ -30,7 +30,7 @@ + * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2, + * write levelling disabled, TDQS disabled, output buffer enabled + * MR2: manual full array self refresh, dynamic ODT off, +- * CAS write latency (CWL): 8 ++ * CAS write latency (CWL): 8 + */ + static u32 mr_ddr3[7] = { + 0x00001c70, 0x00000040, 0x00000018, 0x00000000, +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/Kconfig u-boot/arch/arm/mach-sunxi/Kconfig +--- u-boot-2021.10/arch/arm/mach-sunxi/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/Kconfig 2021-11-01 17:10:13.812950431 +0100 +@@ -88,17 +88,6 @@ + feature. + endif + +-config SUN6I_P2WI +- bool "Allwinner sun6i internal P2WI controller" +- help +- If you say yes to this option, support will be included for the +- P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi +- SOCs. +- The P2WI looks like an SMBus controller (which supports only byte +- accesses), except that it only supports one slave device. +- This interface is used to connect to specific PMIC devices (like the +- AXP221). +- + config SUN6I_PRCM + bool + help +@@ -106,19 +95,13 @@ + in A31 SoC. + + config AXP_PMIC_BUS +- bool "Sunxi AXP PMIC bus access helpers" ++ bool ++ select DM_PMIC if DM_I2C ++ select PMIC_AXP if DM_I2C + help + Select this PMIC bus access helpers for Sunxi platform PRCM or other + AXP family PMIC devices. + +-config SUN8I_RSB +- bool "Allwinner sunXi Reduced Serial Bus Driver" +- help +- Say y here to enable support for Allwinner's Reduced Serial Bus +- (RSB) support. This controller is responsible for communicating +- with various RSB based devices, such as AXP223, AXP8XX PMICs, +- and AC100/AC200 ICs. +- + config SUNXI_SRAM_ADDRESS + hex + default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 +@@ -182,7 +165,6 @@ + + config MACH_SUNXI_H3_H5 + bool +- select DM_I2C + select PHY_SUN4I_USB + select SUNXI_DE2 + select SUNXI_DRAM_DW +@@ -209,6 +191,8 @@ + select DRAM_SUN4I + select SUNXI_GEN_SUN4I + select SUPPORT_SPL ++ imply SPL_SYS_I2C_LEGACY ++ imply SYS_I2C_LEGACY + + config MACH_SUN5I + bool "sun5i (Allwinner A13)" +@@ -219,6 +203,8 @@ + select SUNXI_GEN_SUN4I + select SUPPORT_SPL + imply CONS_INDEX_2 if !DM_SERIAL ++ imply SPL_SYS_I2C_LEGACY ++ imply SYS_I2C_LEGACY + + config MACH_SUN6I + bool "sun6i (Allwinner A31)" +@@ -245,6 +231,8 @@ + select SUNXI_GEN_SUN4I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT ++ imply SPL_SYS_I2C_LEGACY ++ imply SYS_I2C_LEGACY + + config MACH_SUN8I_A23 + bool "sun8i (Allwinner A23)" +@@ -254,6 +242,7 @@ + select ARCH_SUPPORT_PSCI + select DRAM_SUN8I_A23 + select PHY_SUN4I_USB ++ select SUN8I_RSB + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +@@ -267,6 +256,7 @@ + select ARCH_SUPPORT_PSCI + select DRAM_SUN8I_A33 + select PHY_SUN4I_USB ++ select SUN8I_RSB + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +@@ -277,6 +267,7 @@ + select CPU_V7A + select DRAM_SUN8I_A83T + select PHY_SUN4I_USB ++ select SUN8I_RSB + select SUNXI_GEN_SUN6I + select MMC_SUNXI_HAS_NEW_MODE + select MMC_SUNXI_HAS_MODE_SWITCH +@@ -303,6 +294,7 @@ + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT + select PHY_SUN4I_USB ++ imply SPL_SYS_I2C_LEGACY + + config MACH_SUN8I_V3S + bool "sun8i (Allwinner V3/V3s/S3/S3L)" +@@ -329,7 +321,6 @@ + bool "sun50i (Allwinner A64)" + select ARM64 + select SPI +- select DM_I2C + select DM_SPI if SPI + select DM_SPI_FLASH + select PHY_SUN4I_USB +@@ -370,7 +361,6 @@ + # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" + config MACH_SUN8I + bool +- select SUN8I_RSB + select SUN6I_PRCM + default y if MACH_SUN8I_A23 + default y if MACH_SUN8I_A33 +@@ -622,7 +612,6 @@ + + config UART0_PORT_F + bool "UART0 on MicroSD breakout board" +- default n + ---help--- + Repurpose the SD card slot for getting access to the UART0 serial + console. Primarily useful only for low level u-boot debugging on +@@ -633,7 +622,6 @@ + + config OLD_SUNXI_KERNEL_COMPAT + bool "Enable workarounds for booting old kernels" +- default n + ---help--- + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. +@@ -672,24 +660,11 @@ + ---help--- + See MMC0_CD_PIN help text. + +-config MMC1_PINS +- string "Pins for mmc1" +- default "" +- ---help--- +- Set the pins used for mmc1, when applicable. This takes a string in the +- format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. +- +-config MMC2_PINS +- string "Pins for mmc2" +- default "" +- ---help--- +- See MMC1_PINS help text. +- +-config MMC3_PINS +- string "Pins for mmc3" +- default "" ++config MMC1_PINS_PH ++ bool "Pins for mmc1 are on Port H" ++ depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 + ---help--- +- See MMC1_PINS help text. ++ Select this option for boards where mmc1 uses the Port H pinmux. + + config MMC_SUNXI_SLOT_EXTRA + int "mmc extra slot number" +@@ -699,58 +674,6 @@ + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. + +-config INITIAL_USB_SCAN_DELAY +- int "delay initial usb scan by x ms to allow builtin devices to init" +- default 0 +- ---help--- +- Some boards have on board usb devices which need longer than the +- USB spec's 1 second to connect from board powerup. Set this config +- option to a non 0 value to add an extra delay before the first usb +- bus scan. +- +-config USB0_VBUS_PIN +- string "Vbus enable pin for usb0 (otg)" +- default "" +- ---help--- +- Set the Vbus enable pin for usb0 (otg). This takes a string in the +- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +- +-config USB0_VBUS_DET +- string "Vbus detect pin for usb0 (otg)" +- default "" +- ---help--- +- Set the Vbus detect pin for usb0 (otg). This takes a string in the +- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +- +-config USB0_ID_DET +- string "ID detect pin for usb0 (otg)" +- default "" +- ---help--- +- Set the ID detect pin for usb0 (otg). This takes a string in the +- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +- +-config USB1_VBUS_PIN +- string "Vbus enable pin for usb1 (ehci0)" +- default "PH6" if MACH_SUN4I || MACH_SUN7I +- default "PH27" if MACH_SUN6I +- ---help--- +- Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes +- a string in the format understood by sunxi_name_to_gpio, e.g. +- PH1 for pin 1 of port H. +- +-config USB2_VBUS_PIN +- string "Vbus enable pin for usb2 (ehci1)" +- default "PH3" if MACH_SUN4I || MACH_SUN7I +- default "PH24" if MACH_SUN6I +- ---help--- +- See USB1_VBUS_PIN help text. +- +-config USB3_VBUS_PIN +- string "Vbus enable pin for usb3 (ehci2)" +- default "" +- ---help--- +- See USB1_VBUS_PIN help text. +- + config I2C0_ENABLE + bool "Enable I2C/TWI controller 0" + default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 +@@ -764,14 +687,12 @@ + + config I2C1_ENABLE + bool "Enable I2C/TWI controller 1" +- default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. + + config I2C2_ENABLE + bool "Enable I2C/TWI controller 2" +- default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. +@@ -779,7 +700,6 @@ + if MACH_SUN6I || MACH_SUN7I + config I2C3_ENABLE + bool "Enable I2C/TWI controller 3" +- default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. +@@ -798,18 +718,11 @@ + if MACH_SUN7I + config I2C4_ENABLE + bool "Enable I2C/TWI controller 4" +- default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. + endif + +-config AXP_GPIO +- bool "Enable support for gpio-s on axp PMICs" +- default n +- ---help--- +- Say Y here to enable support for the gpio pins of the axp PMIC ICs. +- + config VIDEO_SUNXI + bool "Enable graphical uboot console on HDMI, LCD or VGA" + depends on !MACH_SUN8I_A83T +@@ -838,14 +751,12 @@ + config VIDEO_VGA + bool "VGA output support" + depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) +- default n + ---help--- + Say Y here to add support for outputting video over VGA. + + config VIDEO_VGA_VIA_LCD + bool "VGA via LCD controller support" + depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) +- default n + ---help--- + Say Y here to add support for external DACs connected to the parallel + LCD interface driving a VGA connector, such as found on the +@@ -854,7 +765,6 @@ + config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + bool "Force sync active high for VGA via LCD controller support" + depends on VIDEO_VGA_VIA_LCD +- default n + ---help--- + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough +@@ -872,7 +782,6 @@ + config VIDEO_COMPOSITE + bool "Composite video output support" + depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) +- default n + ---help--- + Say Y here to add support for outputting composite video. + +@@ -936,28 +845,17 @@ + config VIDEO_LCD_PANEL_I2C + bool "LCD panel needs to be configured via i2c" + depends on VIDEO_SUNXI +- default n +- select CMD_I2C ++ select DM_I2C_GPIO + ---help--- + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. + +-config VIDEO_LCD_PANEL_I2C_SDA +- string "LCD panel i2c interface SDA pin" ++config VIDEO_LCD_PANEL_I2C_NAME ++ string "LCD panel i2c interface node name" + depends on VIDEO_LCD_PANEL_I2C +- default "PG12" ++ default "i2c@0" + ---help--- +- Set the SDA pin for the LCD i2c interface. This takes a string in the +- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +- +-config VIDEO_LCD_PANEL_I2C_SCL +- string "LCD panel i2c interface SCL pin" +- depends on VIDEO_LCD_PANEL_I2C +- default "PG10" +- ---help--- +- Set the SCL pin for the LCD i2c interface. This takes a string in the +- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +- ++ Set the device tree node name for the LCD i2c interface. + + # Note only one of these may be selected at a time! But hidden choices are + # not supported by Kconfig +@@ -969,7 +867,6 @@ + + config SUNXI_DE2 + bool +- default n + + config VIDEO_DE2 + bool "Display Engine 2 video driver" +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/pinmux.c u-boot/arch/arm/mach-sunxi/pinmux.c +--- u-boot-2021.10/arch/arm/mach-sunxi/pinmux.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/pinmux.c 2021-11-01 17:10:13.816283581 +0100 +@@ -7,7 +7,7 @@ + + #include + #include +-#include ++//#include + + void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) + { +@@ -17,6 +17,7 @@ + clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); + } + ++#if !CONFIG_IS_ENABLED(DM_GPIO) + void sunxi_gpio_set_cfgpin(u32 pin, u32 val) + { + u32 bank = GPIO_BANK(pin); +@@ -24,6 +25,7 @@ + + sunxi_gpio_set_cfgbank(pio, pin, val); + } ++#endif + + int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) + { +@@ -37,6 +39,7 @@ + return cfg & 0xf; + } + ++#if !CONFIG_IS_ENABLED(DM_GPIO) + int sunxi_gpio_get_cfgpin(u32 pin) + { + u32 bank = GPIO_BANK(pin); +@@ -45,26 +48,37 @@ + return sunxi_gpio_get_cfgbank(pio, pin); + } + +-int sunxi_gpio_set_drv(u32 pin, u32 val) ++void sunxi_gpio_set_drv(u32 pin, u32 val) + { + u32 bank = GPIO_BANK(pin); +- u32 index = GPIO_DRV_INDEX(pin); +- u32 offset = GPIO_DRV_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + +- clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); ++ sunxi_gpio_set_drv_bank(pio, pin, val); ++} ++#endif + +- return 0; ++void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) ++{ ++ u32 index = GPIO_DRV_INDEX(bank_offset); ++ u32 offset = GPIO_DRV_OFFSET(bank_offset); ++ ++ clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); + } + +-int sunxi_gpio_set_pull(u32 pin, u32 val) ++#if !CONFIG_IS_ENABLED(DM_GPIO) ++void sunxi_gpio_set_pull(u32 pin, u32 val) + { + u32 bank = GPIO_BANK(pin); +- u32 index = GPIO_PULL_INDEX(pin); +- u32 offset = GPIO_PULL_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + +- clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); ++ sunxi_gpio_set_pull_bank(pio, pin, val); ++} ++#endif + +- return 0; ++void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) ++{ ++ u32 index = GPIO_PULL_INDEX(bank_offset); ++ u32 offset = GPIO_PULL_OFFSET(bank_offset); ++ ++ clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); + } +diff -ruN u-boot-2021.10/arch/arm/mach-sunxi/pmic_bus.c u-boot/arch/arm/mach-sunxi/pmic_bus.c +--- u-boot-2021.10/arch/arm/mach-sunxi/pmic_bus.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-sunxi/pmic_bus.c 2021-11-01 17:10:13.816283581 +0100 +@@ -8,10 +8,13 @@ + * axp223 uses the rsb bus, these functions abstract this. + */ + ++#include + #include ++#include + #include + #include + #include ++#include + #include + + #define AXP152_I2C_ADDR 0x30 +@@ -21,80 +24,80 @@ + #define AXP305_I2C_ADDR 0x36 + + #define AXP221_CHIP_ADDR 0x68 +-#define AXP221_CTRL_ADDR 0x3e +-#define AXP221_INIT_DATA 0x3e + +-/* AXP818 device and runtime addresses are same as AXP223 */ +-#define AXP223_DEVICE_ADDR 0x3a3 +-#define AXP223_RUNTIME_ADDR 0x2d ++#if CONFIG_IS_ENABLED(PMIC_AXP) ++static struct udevice *pmic; ++#else ++static int pmic_i2c_address(void) ++{ ++ if (IS_ENABLED(CONFIG_AXP152_POWER)) ++ return AXP152_I2C_ADDR; ++ if (IS_ENABLED(CONFIG_AXP305_POWER)) ++ return AXP305_I2C_ADDR; ++ ++ /* Other AXP2xx and AXP8xx variants */ ++ return AXP209_I2C_ADDR; ++} ++#endif + + int pmic_bus_init(void) + { + /* This cannot be 0 because it is used in SPL before BSS is ready */ + static int needs_init = 1; +- __maybe_unused int ret; ++ int ret = 0; + + if (!needs_init) + return 0; + +-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +-# ifdef CONFIG_MACH_SUN6I +- p2wi_init(); +- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, +- AXP221_INIT_DATA); +-# elif defined CONFIG_MACH_SUN8I_R40 +- /* Nothing. R40 uses the AXP221s in I2C mode */ +- ret = 0; +-# else +- ret = rsb_init(); +- if (ret) +- return ret; +- +- ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); +-# endif +- if (ret) +- return ret; ++#if CONFIG_IS_ENABLED(PMIC_AXP) ++ ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic), ++ &pmic); ++#else ++ if (IS_ENABLED(CONFIG_SUN6I_P2WI)) { ++ p2wi_init(); ++ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, ++ AXP_PMIC_MODE_REG, ++ AXP_PMIC_MODE_P2WI); ++ } else if (IS_ENABLED(CONFIG_SUN8I_RSB)) { ++ ret = rsb_init(); ++ if (ret) ++ return ret; ++ ++ ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, ++ AXP_PMIC_PRI_RUNTIME_ADDR); ++ } + #endif + +- needs_init = 0; +- return 0; ++ needs_init = ret; ++ ++ return ret; + } + + int pmic_bus_read(u8 reg, u8 *data) + { +-#ifdef CONFIG_AXP152_POWER +- return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); +-#elif defined CONFIG_AXP209_POWER +- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); +-#elif defined CONFIG_AXP305_POWER +- return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1); +-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +-# ifdef CONFIG_MACH_SUN6I +- return p2wi_read(reg, data); +-# elif defined CONFIG_MACH_SUN8I_R40 +- return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); +-# else +- return rsb_read(AXP223_RUNTIME_ADDR, reg, data); +-# endif ++#if CONFIG_IS_ENABLED(PMIC_AXP) ++ return pmic_read(pmic, reg, data, 1); ++#else ++ if (IS_ENABLED(CONFIG_SUN6I_P2WI)) ++ return p2wi_read(reg, data); ++ if (IS_ENABLED(CONFIG_SUN8I_RSB)) ++ return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); ++ ++ return i2c_read(pmic_i2c_address(), reg, 1, data, 1); + #endif + } + + int pmic_bus_write(u8 reg, u8 data) + { +-#ifdef CONFIG_AXP152_POWER +- return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); +-#elif defined CONFIG_AXP209_POWER +- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); +-#elif defined CONFIG_AXP305_POWER +- return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1); +-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER +-# ifdef CONFIG_MACH_SUN6I +- return p2wi_write(reg, data); +-# elif defined CONFIG_MACH_SUN8I_R40 +- return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); +-# else +- return rsb_write(AXP223_RUNTIME_ADDR, reg, data); +-# endif ++#if CONFIG_IS_ENABLED(PMIC_AXP) ++ return pmic_write(pmic, reg, &data, 1); ++#else ++ if (IS_ENABLED(CONFIG_SUN6I_P2WI)) ++ return p2wi_write(reg, data); ++ if (IS_ENABLED(CONFIG_SUN8I_RSB)) ++ return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); ++ ++ return i2c_write(pmic_i2c_address(), reg, 1, &data, 1); + #endif + } + +diff -ruN u-boot-2021.10/arch/arm/mach-tegra/Kconfig u-boot/arch/arm/mach-tegra/Kconfig +--- u-boot-2021.10/arch/arm/mach-tegra/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-tegra/Kconfig 2021-11-01 17:10:13.816283581 +0100 +@@ -9,7 +9,7 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config TEGRA_CLKRST +@@ -72,6 +72,7 @@ + select CPU_V7A + select SPL + select SPL_BOARD_INIT if SPL ++ select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL + select SUPPORT_SPL + select TEGRA_CLKRST + select TEGRA_COMMON +@@ -124,6 +125,7 @@ + + config TEGRA210 + bool "Tegra210 family" ++ select GICV2 + select TEGRA_ARMV8_COMMON + select TEGRA_CLKRST + select TEGRA_GPIO +@@ -137,6 +139,7 @@ + config TEGRA186 + bool "Tegra186 family" + select DM_MAILBOX ++ select GICV2 + select TEGRA186_BPMP + select TEGRA186_CLOCK + select TEGRA186_GPIO +diff -ruN u-boot-2021.10/arch/arm/mach-tegra/tegra20/display.c u-boot/arch/arm/mach-tegra/tegra20/display.c +--- u-boot-2021.10/arch/arm/mach-tegra/tegra20/display.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-tegra/tegra20/display.c 2021-11-01 17:10:13.819616732 +0100 +@@ -12,4 +12,3 @@ + #include + #include + #include +- +diff -ruN u-boot-2021.10/arch/arm/mach-u8500/Kconfig u-boot/arch/arm/mach-u8500/Kconfig +--- u-boot-2021.10/arch/arm/mach-u8500/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-u8500/Kconfig 2021-11-01 17:10:13.819616732 +0100 +@@ -13,14 +13,15 @@ + The Samsung "stemmy" board supports Samsung smartphones released with + the ST-Ericsson NovaThor U8500 SoC, e.g. + +- - Samsung Galaxy S III mini (GT-I8190) "golden" ++ - Samsung Galaxy Ace 2 (GT-I8160) "codina" ++ - Samsung Galaxy Amp (SGH-I407) "kyle" ++ - Samsung Galaxy Beam (GT-I8530) "gavini" ++ - Samsung Galaxy Exhibit (SGH-T599) "codina" (TMO) + - Samsung Galaxy S Advance (GT-I9070) "janice" ++ - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" +- - Samsung Galaxy Ace 2 (GT-I8160) "codina" +- +- and likely others as well (untested). + +- See board/ste/stemmy/README for details. ++ See doc/board/ste/stemmy.rst for details. + + endchoice + +diff -ruN u-boot-2021.10/arch/arm/mach-uniphier/Makefile u-boot/arch/arm/mach-uniphier/Makefile +--- u-boot-2021.10/arch/arm/mach-uniphier/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-uniphier/Makefile 2021-11-01 17:10:13.822949883 +0100 +@@ -6,7 +6,7 @@ + obj-y += spl_board_init.o + obj-y += memconf.o + obj-y += bcu/ +-obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o ++obj-$(CONFIG_SPL_MMC) += mmc-boot-mode.o + + else + +diff -ruN u-boot-2021.10/arch/arm/mach-versal/Kconfig u-boot/arch/arm/mach-versal/Kconfig +--- u-boot-2021.10/arch/arm/mach-versal/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-versal/Kconfig 2021-11-01 17:10:13.826283035 +0100 +@@ -21,9 +21,6 @@ + Based on this option include/configs/.h header + will be used for board configuration. + +-config GICV3 +- def_bool y +- + config SYS_MALLOC_LEN + default 0x2000000 + +diff -ruN u-boot-2021.10/arch/arm/mach-versatile/timer.c u-boot/arch/arm/mach-versatile/timer.c +--- u-boot-2021.10/arch/arm/mach-versatile/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-versatile/timer.c 2021-11-01 17:10:13.826283035 +0100 +@@ -60,4 +60,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/arch/arm/mach-zynq/Kconfig u-boot/arch/arm/mach-zynq/Kconfig +--- u-boot-2021.10/arch/arm/mach-zynq/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-zynq/Kconfig 2021-11-01 17:10:13.826283035 +0100 +@@ -15,16 +15,16 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_MMC_SUPPORT ++config SPL_MMC + default y if MMC_SDHCI_ZYNQ + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config SPL_SPI_FLASH_SUPPORT + default y if ZYNQ_QSPI + +-config SPL_SPI_SUPPORT ++config SPL_SPI + default y if ZYNQ_QSPI + + config ZYNQ_DDRC_INIT +diff -ruN u-boot-2021.10/arch/arm/mach-zynq/spl.c u-boot/arch/arm/mach-zynq/spl.c +--- u-boot-2021.10/arch/arm/mach-zynq/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-zynq/spl.c 2021-11-01 17:10:13.826283035 +0100 +@@ -45,7 +45,7 @@ + u32 mode; + + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { +-#ifdef CONFIG_SPL_SPI_SUPPORT ++#ifdef CONFIG_SPL_SPI + case ZYNQ_BM_QSPI: + mode = BOOT_DEVICE_SPI; + break; +@@ -56,7 +56,7 @@ + case ZYNQ_BM_NOR: + mode = BOOT_DEVICE_NOR; + break; +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + case ZYNQ_BM_SD: + mode = BOOT_DEVICE_MMC1; + break; +diff -ruN u-boot-2021.10/arch/arm/mach-zynqmp/Kconfig u-boot/arch/arm/mach-zynqmp/Kconfig +--- u-boot-2021.10/arch/arm/mach-zynqmp/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-zynqmp/Kconfig 2021-11-01 17:10:13.826283035 +0100 +@@ -12,16 +12,16 @@ + config SPL_LIBGENERIC_SUPPORT + default y + +-config SPL_MMC_SUPPORT ++config SPL_MMC + default y if MMC_SDHCI_ZYNQ + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + default y + + config SPL_SPI_FLASH_SUPPORT + default y if ZYNQ_QSPI + +-config SPL_SPI_SUPPORT ++config SPL_SPI + default y if ZYNQ_QSPI + + config SYS_BOARD +diff -ruN u-boot-2021.10/arch/arm/mach-zynqmp/spl.c u-boot/arch/arm/mach-zynqmp/spl.c +--- u-boot-2021.10/arch/arm/mach-zynqmp/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/mach-zynqmp/spl.c 2021-11-01 17:10:13.829616186 +0100 +@@ -88,7 +88,7 @@ + switch (bootmode) { + case JTAG_MODE: + return BOOT_DEVICE_RAM; +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + case SD_MODE1: + case SD1_LSHFT_MODE: /* not working on silicon v1 */ + return BOOT_DEVICE_MMC2; +@@ -100,11 +100,11 @@ + case USB_MODE: + return BOOT_DEVICE_DFU; + #endif +-#ifdef CONFIG_SPL_SATA_SUPPORT ++#ifdef CONFIG_SPL_SATA + case SW_SATA_MODE: + return BOOT_DEVICE_SATA; + #endif +-#ifdef CONFIG_SPL_SPI_SUPPORT ++#ifdef CONFIG_SPL_SPI + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + return BOOT_DEVICE_SPI; +diff -ruN u-boot-2021.10/arch/arm/Makefile u-boot/arch/arm/Makefile +--- u-boot-2021.10/arch/arm/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/arm/Makefile 2021-11-01 17:10:13.546298348 +0100 +@@ -18,7 +18,11 @@ + $(call cc-option, -march=armv7)) + arch-$(CONFIG_CPU_V7M) =-march=armv7-m + arch-$(CONFIG_CPU_V7R) =-march=armv7-r ++ifeq ($(CONFIG_ARM64_CRC32),y) ++arch-$(CONFIG_ARM64) =-march=armv8-a+crc ++else + arch-$(CONFIG_ARM64) =-march=armv8-a ++endif + + # On Tegra systems we must build SPL for the armv4 core on the device + # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH +@@ -107,7 +111,7 @@ + libs-y += arch/arm/lib/ + + ifeq ($(CONFIG_SPL_BUILD),y) +-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) ++ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) + libs-y += arch/arm/mach-imx/ + endif + else +diff -ruN u-boot-2021.10/arch/Kconfig u-boot/arch/Kconfig +--- u-boot-2021.10/arch/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/Kconfig 2021-11-01 17:10:13.542965197 +0100 +@@ -7,6 +7,27 @@ + config NEEDS_MANUAL_RELOC + bool + ++config SYS_CACHE_SHIFT_4 ++ bool ++ ++config SYS_CACHE_SHIFT_5 ++ bool ++ ++config SYS_CACHE_SHIFT_6 ++ bool ++ ++config SYS_CACHE_SHIFT_7 ++ bool ++ ++config SYS_CACHELINE_SIZE ++ int ++ default 128 if SYS_CACHE_SHIFT_7 ++ default 64 if SYS_CACHE_SHIFT_6 ++ default 32 if SYS_CACHE_SHIFT_5 ++ default 16 if SYS_CACHE_SHIFT_4 ++ # Fall-back for MIPS ++ default 32 if MIPS ++ + config LINKER_LIST_ALIGN + int + default 32 if SANDBOX +@@ -29,6 +50,7 @@ + select DM + select HAVE_PRIVATE_LIBGCC + select SUPPORT_OF_CONTROL ++ select SYS_CACHE_SHIFT_7 + select TIMER + + config ARM +@@ -44,6 +66,7 @@ + select NEEDS_MANUAL_RELOC + select SYS_BOOT_GET_CMDLINE + select SYS_BOOT_GET_KBD ++ select SYS_CACHE_SHIFT_4 + select SUPPORT_OF_CONTROL + + config MICROBLAZE +@@ -97,7 +120,7 @@ + imply SPL_OF_CONTROL + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_TIMER + + config SANDBOX +@@ -122,6 +145,7 @@ + select SPI + select SUPPORT_OF_CONTROL + select SYSRESET_CMD_POWEROFF ++ select SYS_CACHE_SHIFT_4 + select IRQ + select SUPPORT_EXTENSION_SCAN + imply BITREVERSE +@@ -187,6 +211,7 @@ + select OF_CONTROL + select PCI + select SUPPORT_OF_CONTROL ++ select SYS_CACHE_SHIFT_6 + select TIMER + select USE_PRIVATE_LIBGCC + select X86_TSC_TIMER +@@ -233,9 +258,9 @@ + imply SPL_PINCTRL + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT +- imply SPL_SERIAL_SUPPORT ++ imply SPL_SERIAL + imply SPL_SPI_FLASH_SUPPORT +- imply SPL_SPI_SUPPORT ++ imply SPL_SPI + imply SPL_OF_CONTROL + imply SPL_TIMER + imply SPL_REGMAP +@@ -247,7 +272,7 @@ + imply TPL_PINCTRL + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT +- imply TPL_SERIAL_SUPPORT ++ imply TPL_SERIAL + imply TPL_OF_CONTROL + imply TPL_TIMER + imply TPL_REGMAP +@@ -325,6 +350,63 @@ + Note that, its up to the individual architectures to implement + this functionality. + ++config SKIP_LOWLEVEL_INIT ++ bool "Skip the calls to certain low level initialization functions" ++ depends on ARM || NDS32 || MIPS || RISCV ++ help ++ If enabled, then certain low level initializations (like setting up ++ the memory controller) are omitted and/or U-Boot does not relocate ++ itself into RAM. ++ Normally this variable MUST NOT be defined. The only exception is ++ when U-Boot is loaded (to RAM) by some other boot loader or by a ++ debugger which performs these initializations itself. ++ ++config SPL_SKIP_LOWLEVEL_INIT ++ bool "Skip the calls to certain low level initialization functions" ++ depends on SPL && (ARM || NDS32 || MIPS || RISCV) ++ help ++ If enabled, then certain low level initializations (like setting up ++ the memory controller) are omitted and/or U-Boot does not relocate ++ itself into RAM. ++ Normally this variable MUST NOT be defined. The only exception is ++ when U-Boot is loaded (to RAM) by some other boot loader or by a ++ debugger which performs these initializations itself. ++ ++config TPL_SKIP_LOWLEVEL_INIT ++ bool "Skip the calls to certain low level initialization functions" ++ depends on SPL && ARM ++ help ++ If enabled, then certain low level initializations (like setting up ++ the memory controller) are omitted and/or U-Boot does not relocate ++ itself into RAM. ++ Normally this variable MUST NOT be defined. The only exception is ++ when U-Boot is loaded (to RAM) by some other boot loader or by a ++ debugger which performs these initializations itself. ++ ++config SKIP_LOWLEVEL_INIT_ONLY ++ bool "Skip the call to lowlevel_init during early boot ONLY" ++ depends on ARM ++ help ++ This allows just the call to lowlevel_init() to be skipped. The ++ normal CP15 init (such as enabling the instruction cache) is still ++ performed. ++ ++config SPL_SKIP_LOWLEVEL_INIT_ONLY ++ bool "Skip the call to lowlevel_init during early boot ONLY" ++ depends on SPL && ARM ++ help ++ This allows just the call to lowlevel_init() to be skipped. The ++ normal CP15 init (such as enabling the instruction cache) is still ++ performed. ++ ++config TPL_SKIP_LOWLEVEL_INIT_ONLY ++ bool "Skip the call to lowlevel_init during early boot ONLY" ++ depends on TPL && ARM ++ help ++ This allows just the call to lowlevel_init() to be skipped. The ++ normal CP15 init (such as enabling the instruction cache) is still ++ performed. ++ + source "arch/arc/Kconfig" + source "arch/arm/Kconfig" + source "arch/m68k/Kconfig" +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf5227x/start.S u-boot/arch/m68k/cpu/mcf5227x/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf5227x/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf5227x/start.S 2021-11-01 17:10:13.829616186 +0100 +@@ -6,7 +6,6 @@ + + #include + #include +-#include "version.h" + #include + + #define _START _start +@@ -38,10 +37,10 @@ + _vectors: + #if defined(CONFIG_CF_SBF) + INITSP: .long 0 /* Initial SP */ +-INITPC: .long ASM_DRAMINIT /* Initial PC */ ++INITPC: .long ASM_DRAMINIT /* Initial PC */ + #else + INITSP: .long 0 /* Initial SP */ +-INITPC: .long _START /* Initial PC */ ++INITPC: .long _START /* Initial PC */ + #endif + + vector02_0F: +@@ -489,7 +488,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf523x/cpu.c u-boot/arch/m68k/cpu/mcf523x/cpu.c +--- u-boot-2021.10/arch/m68k/cpu/mcf523x/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf523x/cpu.c 2021-11-01 17:10:13.829616186 +0100 +@@ -106,7 +106,7 @@ + #if defined(CONFIG_MCFFEC) + /* Default initializations for MCFFEC controllers. To override, + * create a board-specific function called: +- * int board_eth_init(struct bd_info *bis) ++ * int board_eth_init(struct bd_info *bis) + */ + + int cpu_eth_init(struct bd_info *bis) +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf523x/start.S u-boot/arch/m68k/cpu/mcf523x/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf523x/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf523x/start.S 2021-11-01 17:10:13.829616186 +0100 +@@ -6,7 +6,6 @@ + + #include + #include +-#include "version.h" + #include + + #define _START _start +@@ -253,7 +252,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf52x2/cpu.c u-boot/arch/m68k/cpu/mcf52x2/cpu.c +--- u-boot-2021.10/arch/m68k/cpu/mcf52x2/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf52x2/cpu.c 2021-11-01 17:10:13.829616186 +0100 +@@ -421,7 +421,7 @@ + #if defined(CONFIG_MCFFEC) + /* Default initializations for MCFFEC controllers. To override, + * create a board-specific function called: +- * int board_eth_init(struct bd_info *bis) ++ * int board_eth_init(struct bd_info *bis) + */ + + int cpu_eth_init(struct bd_info *bis) +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf52x2/start.S u-boot/arch/m68k/cpu/mcf52x2/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf52x2/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf52x2/start.S 2021-11-01 17:10:13.829616186 +0100 +@@ -6,7 +6,6 @@ + + #include + #include +-#include "version.h" + #include + + #define _START _start +@@ -335,7 +334,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf530x/Makefile u-boot/arch/m68k/cpu/mcf530x/Makefile +--- u-boot-2021.10/arch/m68k/cpu/mcf530x/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf530x/Makefile 2021-11-01 17:10:13.829616186 +0100 +@@ -4,4 +4,3 @@ + + extra-y = start.o + obj-y = interrupts.o cpu.o speed.o cpu_init.o +- +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf530x/start.S u-boot/arch/m68k/cpu/mcf530x/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf530x/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf530x/start.S 2021-11-01 17:10:13.829616186 +0100 +@@ -6,7 +6,6 @@ + + #include + #include +-#include "version.h" + #include + + #define _START _start +@@ -258,9 +257,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION +-.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" +-.ascii CONFIG_IDENT_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf532x/cpu.c u-boot/arch/m68k/cpu/mcf532x/cpu.c +--- u-boot-2021.10/arch/m68k/cpu/mcf532x/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf532x/cpu.c 2021-11-01 17:10:13.829616186 +0100 +@@ -148,7 +148,7 @@ + #if defined(CONFIG_MCFFEC) + /* Default initializations for MCFFEC controllers. To override, + * create a board-specific function called: +- * int board_eth_init(struct bd_info *bis) ++ * int board_eth_init(struct bd_info *bis) + */ + int cpu_eth_init(struct bd_info *bis) + { +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf532x/start.S u-boot/arch/m68k/cpu/mcf532x/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf532x/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf532x/start.S 2021-11-01 17:10:13.829616186 +0100 +@@ -9,7 +9,6 @@ + + #include + #include +-#include "version.h" + #include + + #define _START _start +@@ -268,7 +267,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf5445x/cpu.c u-boot/arch/m68k/cpu/mcf5445x/cpu.c +--- u-boot-2021.10/arch/m68k/cpu/mcf5445x/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf5445x/cpu.c 2021-11-01 17:10:13.829616186 +0100 +@@ -110,7 +110,7 @@ + #if defined(CONFIG_MCFFEC) + /* Default initializations for MCFFEC controllers. To override, + * create a board-specific function called: +- * int board_eth_init(struct bd_info *bis) ++ * int board_eth_init(struct bd_info *bis) + */ + + int cpu_eth_init(struct bd_info *bis) +diff -ruN u-boot-2021.10/arch/m68k/cpu/mcf5445x/start.S u-boot/arch/m68k/cpu/mcf5445x/start.S +--- u-boot-2021.10/arch/m68k/cpu/mcf5445x/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/mcf5445x/start.S 2021-11-01 17:10:13.832949336 +0100 +@@ -10,8 +10,6 @@ + #include + #include + #include +-#include +-#include "version.h" + #include + + #define _START _start +@@ -46,16 +44,16 @@ + + INITSP: .long 0 /* Initial SP */ + #ifdef CONFIG_CF_SBF +-INITPC: .long ASM_DRAMINIT /* Initial PC */ ++INITPC: .long ASM_DRAMINIT /* Initial PC */ + #endif + #ifdef CONFIG_SYS_NAND_BOOT +-INITPC: .long ASM_DRAMINIT_N /* Initial PC */ ++INITPC: .long ASM_DRAMINIT_N /* Initial PC */ + #endif + + #else + + INITSP: .long 0 /* Initial SP */ +-INITPC: .long _START /* Initial PC */ ++INITPC: .long _START /* Initial PC */ + + #endif + +@@ -610,7 +608,4 @@ + + /******************************************************************************/ + +-.globl version_string +-version_string: +-.ascii U_BOOT_VERSION_STRING, "\0" + .align 4 +diff -ruN u-boot-2021.10/arch/m68k/cpu/u-boot.lds u-boot/arch/m68k/cpu/u-boot.lds +--- u-boot-2021.10/arch/m68k/cpu/u-boot.lds 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/cpu/u-boot.lds 2021-11-01 17:10:13.832949336 +0100 +@@ -9,6 +9,7 @@ + #include + + OUTPUT_ARCH(m68k) ++ENTRY(_start) + + #ifndef LDS_BOARD_TEXT + #define LDS_BOARD_TEXT +diff -ruN u-boot-2021.10/arch/m68k/include/asm/immap_5307.h u-boot/arch/m68k/include/asm/immap_5307.h +--- u-boot-2021.10/arch/m68k/include/asm/immap_5307.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/include/asm/immap_5307.h 2021-11-01 17:10:13.832949336 +0100 +@@ -114,4 +114,3 @@ + } gpio_t; + + #endif /* __IMMAP_5307__ */ +- +diff -ruN u-boot-2021.10/arch/m68k/include/asm/m5271.h u-boot/arch/m68k/include/asm/m5271.h +--- u-boot-2021.10/arch/m68k/include/asm/m5271.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/include/asm/m5271.h 2021-11-01 17:10:13.836282487 +0100 +@@ -115,7 +115,7 @@ + #define MCF_GPIO_PAR_TIMER 0x10004C + + #define MCF_DSCR_EIM 0x100050 +-#define MCF_DCSR_FEC12C 0x100052 ++#define MCF_DCSR_FEC12C 0x100052 + #define MCF_DCSR_UART 0x100053 + #define MCF_DCSR_QSPI 0x100054 + #define MCF_DCSR_TIMER 0x100055 +diff -ruN u-boot-2021.10/arch/m68k/include/asm/m5307.h u-boot/arch/m68k/include/asm/m5307.h +--- u-boot-2021.10/arch/m68k/include/asm/m5307.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/include/asm/m5307.h 2021-11-01 17:10:13.836282487 +0100 +@@ -66,4 +66,3 @@ + #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + + #endif /* mcf5307_h */ +- +diff -ruN u-boot-2021.10/arch/m68k/lib/bootm.c u-boot/arch/m68k/lib/bootm.c +--- u-boot-2021.10/arch/m68k/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/lib/bootm.c 2021-11-01 17:10:13.836282487 +0100 +@@ -32,23 +32,7 @@ + + void arch_lmb_reserve(struct lmb *lmb) + { +- ulong sp; +- +- /* +- * Booting a (Linux) kernel image +- * +- * Allocate space for command line and board info - the +- * address should be as high as possible within the reach of +- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused +- * memory, which means far enough below the current stack +- * pointer. +- */ +- sp = get_sp(); +- debug ("## Current stack ends at 0x%08lx ", sp); +- +- /* adjust sp by 1K to be safe */ +- sp -= 1024; +- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp)); ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024); + } + + int do_bootm_linux(int flag, int argc, char *const argv[], +diff -ruN u-boot-2021.10/arch/m68k/lib/muldi3.c u-boot/arch/m68k/lib/muldi3.c +--- u-boot-2021.10/arch/m68k/lib/muldi3.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/m68k/lib/muldi3.c 2021-11-01 17:10:13.836282487 +0100 +@@ -41,7 +41,7 @@ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) + +-typedef int SItype __attribute__ ((mode (SI))); ++typedef int SItype __attribute__ ((mode (SI))); + typedef unsigned int USItype __attribute__ ((mode (SI))); + typedef int DItype __attribute__ ((mode (DI))); + typedef int word_type __attribute__ ((mode (__word__))); +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/microblaze/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/microblaze/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/leds/common.h u-boot/arch/microblaze/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/microblaze/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/microblaze/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/microblaze/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/microblaze/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/microblaze/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/microblaze/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/microblaze/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/microblaze/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/microblaze/lib/bootm.c u-boot/arch/microblaze/lib/bootm.c +--- u-boot-2021.10/arch/microblaze/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/microblaze/lib/bootm.c 2021-11-01 17:10:13.839615639 +0100 +@@ -34,33 +34,7 @@ + + void arch_lmb_reserve(struct lmb *lmb) + { +- ulong sp, bank_end; +- int bank; +- +- /* +- * Booting a (Linux) kernel image +- * +- * Allocate space for command line and board info - the +- * address should be as high as possible within the reach of +- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused +- * memory, which means far enough below the current stack +- * pointer. +- */ +- sp = get_sp(); +- debug("## Current stack ends at 0x%08lx ", sp); +- +- /* adjust sp by 4K to be safe */ +- sp -= 4096; +- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { +- if (sp < gd->bd->bi_dram[bank].start) +- continue; +- bank_end = gd->bd->bi_dram[bank].start + +- gd->bd->bi_dram[bank].size; +- if (sp >= bank_end) +- continue; +- lmb_reserve(lmb, sp, bank_end - sp); +- break; +- } ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); + } + + static void boot_jump_linux(bootm_headers_t *images, int flag) +diff -ruN u-boot-2021.10/arch/mips/cpu/start.S u-boot/arch/mips/cpu/start.S +--- u-boot-2021.10/arch/mips/cpu/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/cpu/start.S 2021-11-01 17:10:13.839615639 +0100 +@@ -233,7 +233,7 @@ + # endif + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init +@@ -254,7 +254,7 @@ + nop + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/mips/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/mips/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/mips/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/mips/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/mips/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/mips/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/mips/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/leds/common.h u-boot/arch/mips/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/mips/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/mips/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/mips/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/mips/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/mips/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/mips/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/mips/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/mips/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/mips/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/mips/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/mips/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/mips/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/mips/include/asm/cache.h u-boot/arch/mips/include/asm/cache.h +--- u-boot-2021.10/arch/mips/include/asm/cache.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/include/asm/cache.h 2021-11-01 17:10:13.842948790 +0100 +@@ -6,17 +6,7 @@ + #ifndef __MIPS_CACHE_H__ + #define __MIPS_CACHE_H__ + +-#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +- +-#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) +- +-/* +- * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for +- * DMA buffer alignment. Satisfy those drivers by providing it as a synonym +- * of ARCH_DMA_MINALIGN for now. +- */ +-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN ++#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE + + #ifndef __ASSEMBLY__ + /** +diff -ruN u-boot-2021.10/arch/mips/include/asm/mipsregs.h u-boot/arch/mips/include/asm/mipsregs.h +--- u-boot-2021.10/arch/mips/include/asm/mipsregs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/include/asm/mipsregs.h 2021-11-01 17:10:13.842948790 +0100 +@@ -2307,8 +2307,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mflo %0, $ac0 \n" \ +- " .set pop \n" \ +- : "=r" (mflo0)); \ ++ " .set pop \n" \ ++ : "=r" (mflo0)); \ + mflo0; \ + }) + +@@ -2320,8 +2320,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mflo %0, $ac1 \n" \ +- " .set pop \n" \ +- : "=r" (mflo1)); \ ++ " .set pop \n" \ ++ : "=r" (mflo1)); \ + mflo1; \ + }) + +@@ -2333,8 +2333,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mflo %0, $ac2 \n" \ +- " .set pop \n" \ +- : "=r" (mflo2)); \ ++ " .set pop \n" \ ++ : "=r" (mflo2)); \ + mflo2; \ + }) + +@@ -2346,8 +2346,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mflo %0, $ac3 \n" \ +- " .set pop \n" \ +- : "=r" (mflo3)); \ ++ " .set pop \n" \ ++ : "=r" (mflo3)); \ + mflo3; \ + }) + +@@ -2359,8 +2359,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mfhi %0, $ac0 \n" \ +- " .set pop \n" \ +- : "=r" (mfhi0)); \ ++ " .set pop \n" \ ++ : "=r" (mfhi0)); \ + mfhi0; \ + }) + +@@ -2372,8 +2372,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mfhi %0, $ac1 \n" \ +- " .set pop \n" \ +- : "=r" (mfhi1)); \ ++ " .set pop \n" \ ++ : "=r" (mfhi1)); \ + mfhi1; \ + }) + +@@ -2385,8 +2385,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mfhi %0, $ac2 \n" \ +- " .set pop \n" \ +- : "=r" (mfhi2)); \ ++ " .set pop \n" \ ++ : "=r" (mfhi2)); \ + mfhi2; \ + }) + +@@ -2398,8 +2398,8 @@ + " .set " MIPS_ISA_LEVEL " \n" \ + " .set dsp \n" \ + " mfhi %0, $ac3 \n" \ +- " .set pop \n" \ +- : "=r" (mfhi3)); \ ++ " .set pop \n" \ ++ : "=r" (mfhi3)); \ + mfhi3; \ + }) + +diff -ruN u-boot-2021.10/arch/mips/Kconfig u-boot/arch/mips/Kconfig +--- u-boot-2021.10/arch/mips/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/Kconfig 2021-11-01 17:10:13.839615639 +0100 +@@ -22,7 +22,7 @@ + select DYNAMIC_IO_PORT_BASE + select MIPS_CM + select MIPS_INSERT_BOOT_CONFIG +- select MIPS_L1_CACHE_SHIFT_6 ++ select SYS_CACHE_SHIFT_6 + select MIPS_L2_CACHE + select OF_CONTROL + select OF_ISA_BUS +@@ -132,7 +132,7 @@ + select DM + select DM_SERIAL + select MIPS_CM +- select MIPS_L1_CACHE_SHIFT_6 ++ select SYS_CACHE_SHIFT_6 + select MIPS_L2_CACHE + select OF_BOARD_SETUP + select OF_CONTROL +@@ -153,7 +153,7 @@ + select DM_ETH + select DM_GPIO + select DM_SERIAL +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 +@@ -346,7 +346,6 @@ + + config RESTORE_EXCEPTION_VECTOR_BASE + bool "Restore exception vector base before booting linux kernel" +- default n + help + In U-Boot the exception vector base will be moved to top of memory, + to be used to display register dump when exception occurs. +@@ -361,7 +360,6 @@ + config OVERRIDE_EXCEPTION_VECTOR_BASE + bool "Override the exception vector base to be restored" + depends on RESTORE_EXCEPTION_VECTOR_BASE +- default n + help + Enable this option if you want to use a different exception vector + base rather than the previously saved one. +@@ -376,7 +374,6 @@ + + config INIT_STACK_WITHOUT_MALLOC_F + bool "Do not reserve malloc space on initial stack" +- default n + help + Enable this option if you don't want to reserve malloc space on + initial stack. This is useful if the initial stack can't hold large +@@ -385,7 +382,6 @@ + + config SPL_INIT_STACK_WITHOUT_MALLOC_F + bool "Do not reserve malloc space on initial stack in SPL" +- default n + help + Enable this option if you don't want to reserve malloc space on + initial stack. This is useful if the initial stack can't hold large +@@ -394,7 +390,6 @@ + + config SPL_LOADER_SUPPORT + bool +- default n + help + Enable this option if you want to use SPL loaders without DM enabled. + +@@ -422,7 +417,6 @@ + + config MIPS_BOOT_FDT + bool "Hand over a flattened device tree to Linux kernel" +- default n + help + Enable this option if you want U-Boot to hand over a flattened + device tree to the kernel. According to UHI register $a0 will be set +@@ -501,7 +495,6 @@ + + config MIPS_INIT_STACK_IN_SRAM + bool +- default n + help + Select this if the initial stack frame could be setup in SRAM. + Normally the initial stack frame is set up in DRAM which is often +@@ -512,7 +505,6 @@ + + config MIPS_SRAM_INIT + bool +- default n + depends on MIPS_INIT_STACK_IN_SRAM + help + Select this if the SRAM for initial stack needs to be initialized +@@ -566,26 +558,6 @@ + so if you know the cache configuration for your system at compile + time it would be beneficial to configure it. + +-config MIPS_L1_CACHE_SHIFT_4 +- bool +- +-config MIPS_L1_CACHE_SHIFT_5 +- bool +- +-config MIPS_L1_CACHE_SHIFT_6 +- bool +- +-config MIPS_L1_CACHE_SHIFT_7 +- bool +- +-config MIPS_L1_CACHE_SHIFT +- int +- default "7" if MIPS_L1_CACHE_SHIFT_7 +- default "6" if MIPS_L1_CACHE_SHIFT_6 +- default "5" if MIPS_L1_CACHE_SHIFT_5 +- default "4" if MIPS_L1_CACHE_SHIFT_4 +- default "5" +- + config MIPS_L2_CACHE + bool + help +@@ -604,7 +576,6 @@ + + config MIPS_INSERT_BOOT_CONFIG + bool +- default n + help + Enable this to insert some board-specific boot configuration in + the U-Boot binary at offset 0x10. +diff -ruN u-boot-2021.10/arch/mips/lib/bootm.c u-boot/arch/mips/lib/bootm.c +--- u-boot-2021.10/arch/mips/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/lib/bootm.c 2021-11-01 17:10:13.846281940 +0100 +@@ -39,14 +39,7 @@ + + void arch_lmb_reserve(struct lmb *lmb) + { +- ulong sp; +- +- sp = arch_get_sp(); +- debug("## Current stack ends at 0x%08lx\n", sp); +- +- /* adjust sp by 4K to be safe */ +- sp -= 4096; +- lmb_reserve(lmb, sp, gd->ram_top - sp); ++ arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096); + } + + static void linux_cmdline_init(void) +diff -ruN u-boot-2021.10/arch/mips/mach-bmips/Kconfig u-boot/arch/mips/mach-bmips/Kconfig +--- u-boot-2021.10/arch/mips/mach-bmips/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-bmips/Kconfig 2021-11-01 17:10:13.849615092 +0100 +@@ -21,7 +21,7 @@ + + config SOC_BMIPS_BCM3380 + bool "BMIPS BCM3380 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -31,7 +31,7 @@ + + config SOC_BMIPS_BCM6318 + bool "BMIPS BCM6318 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -41,7 +41,7 @@ + + config SOC_BMIPS_BCM6328 + bool "BMIPS BCM6328 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -51,7 +51,7 @@ + + config SOC_BMIPS_BCM6338 + bool "BMIPS BCM6338 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -61,7 +61,7 @@ + + config SOC_BMIPS_BCM6348 + bool "BMIPS BCM6348 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -71,7 +71,7 @@ + + config SOC_BMIPS_BCM6358 + bool "BMIPS BCM6358 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -81,7 +81,7 @@ + + config SOC_BMIPS_BCM6368 + bool "BMIPS BCM6368 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -91,7 +91,7 @@ + + config SOC_BMIPS_BCM6362 + bool "BMIPS BCM6362 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -101,7 +101,7 @@ + + config SOC_BMIPS_BCM63268 + bool "BMIPS BCM63268 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +@@ -112,7 +112,7 @@ + + config SOC_BMIPS_BCM6838 + bool "BMIPS BCM6838 family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 +diff -ruN u-boot-2021.10/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h u-boot/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h +--- u-boot-2021.10/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h 2021-11-01 17:10:13.849615092 +0100 +@@ -454,4 +454,3 @@ + void sdram_init(void); + + #endif /* __JZ4780_DRAM_H__ */ +- +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/Kconfig u-boot/arch/mips/mach-mtmips/Kconfig +--- u-boot-2021.10/arch/mips/mach-mtmips/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/Kconfig 2021-11-01 17:10:13.849615092 +0100 +@@ -1,6 +1,9 @@ + menu "MediaTek MIPS platforms" + depends on ARCH_MTMIPS + ++config SYS_VENDOR ++ default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB ++ + config SYS_MALLOC_F_LEN + default 0x1000 + +@@ -39,7 +42,7 @@ + + config SOC_MT7620 + bool "MT7620" +- select MIPS_L1_CACHE_SHIFT_5 ++ select SYS_CACHE_SHIFT_5 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select PINCTRL_MT7620 + select MT7620_SERIAL +@@ -54,7 +57,7 @@ + + config SOC_MT7628 + bool "MT7628" +- select MIPS_L1_CACHE_SHIFT_5 ++ select SYS_CACHE_SHIFT_5 + select MIPS_INIT_STACK_IN_SRAM + select MIPS_SRAM_INIT + select SYS_MIPS_CACHE_INIT_RAM_LOAD +@@ -68,7 +71,7 @@ + select SPL_OF_CONTROL if SPL_DM + select SPL_SIMPLE_BUS if SPL_DM + select SPL_DM_SERIAL if SPL_DM +- select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT ++ select SPL_CLK if SPL_DM && SPL_SERIAL + select SPL_SYSRESET if SPL_DM + select SPL_OF_LIBFDT if SPL_OF_CONTROL + help +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/mt7620/Kconfig u-boot/arch/mips/mach-mtmips/mt7620/Kconfig +--- u-boot-2021.10/arch/mips/mach-mtmips/mt7620/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/mt7620/Kconfig 2021-11-01 17:10:13.852948243 +0100 +@@ -66,6 +66,12 @@ + default 6 if CPU_FREQ_600MHZ + default 7 if CPU_FREQ_620MHZ + +-source "board/mediatek/mt7620/Kconfig" ++config SYS_CONFIG_NAME ++ string "Board configuration name" ++ default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB ++ ++config SYS_BOARD ++ string "Board name" ++ default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + + endif +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/mt7620/serial.c u-boot/arch/mips/mach-mtmips/mt7620/serial.c +--- u-boot-2021.10/arch/mips/mach-mtmips/mt7620/serial.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/mt7620/serial.c 2021-11-01 17:10:13.852948243 +0100 +@@ -23,7 +23,7 @@ + + void mtmips_spl_serial_init(void) + { +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + #if CONFIG_CONS_INDEX == 1 +@@ -32,5 +32,5 @@ + clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, + UARTF_MODE_UARTF_GPIO << UARTF_SHARE_MODE_S); + #endif +-#endif /* CONFIG_SPL_SERIAL_SUPPORT */ ++#endif /* CONFIG_SPL_SERIAL */ + } +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/mt7628/Kconfig u-boot/arch/mips/mach-mtmips/mt7628/Kconfig +--- u-boot-2021.10/arch/mips/mach-mtmips/mt7628/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/mt7628/Kconfig 2021-11-01 17:10:13.852948243 +0100 +@@ -29,7 +29,7 @@ + + config BOARD_VOCORE2 + bool "VoCore2" +- select SPL_SERIAL_SUPPORT ++ select SPL_SERIAL + select SPL_UART2_SPIS_PINMUX + help + VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM +@@ -39,14 +39,20 @@ + + config SPL_UART2_SPIS_PINMUX + bool "Use alternative pinmux for UART2 in SPL stage" +- depends on SPL_SERIAL_SUPPORT +- default n ++ depends on SPL_SERIAL + help + Select this if the UART2 of your board is connected to GPIO 16/17 + (shared with SPIS) rather than the usual GPIO 20/21. + ++config SYS_BOARD ++ string "Board name" ++ default "mt7628" if BOARD_MT7628_RFB ++ ++config SYS_CONFIG_NAME ++ string "Board configuration name" ++ default "mt7628" if BOARD_MT7628_RFB ++ + source "board/gardena/smart-gateway-mt7688/Kconfig" +-source "board/mediatek/mt7628/Kconfig" + source "board/seeed/linkit-smart-7688/Kconfig" + source "board/vocore/vocore2/Kconfig" + +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/mt7628/lowlevel_init.S u-boot/arch/mips/mach-mtmips/mt7628/lowlevel_init.S +--- u-boot-2021.10/arch/mips/mach-mtmips/mt7628/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/mt7628/lowlevel_init.S 2021-11-01 17:10:13.852948243 +0100 +@@ -28,7 +28,7 @@ + .set noreorder + + LEAF(mips_sram_init) +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* Setup CPU PLL */ + li t0, DELAY_USEC(1000000) + li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG) +@@ -116,7 +116,7 @@ + sub a1, CONFIG_SYS_DCACHE_LINE_SIZE + bnez a1, 3b + nop +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + jr ra + nop +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/mt7628/serial.c u-boot/arch/mips/mach-mtmips/mt7628/serial.c +--- u-boot-2021.10/arch/mips/mach-mtmips/mt7628/serial.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/mt7628/serial.c 2021-11-01 17:10:13.852948243 +0100 +@@ -11,7 +11,7 @@ + + void mtmips_spl_serial_init(void) + { +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + #if CONFIG_CONS_INDEX == 1 +@@ -30,5 +30,5 @@ + 1 << SPIS_MODE_S); + #endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ + #endif /* CONFIG_CONS_INDEX */ +-#endif /* CONFIG_SPL_SERIAL_SUPPORT */ ++#endif /* CONFIG_SPL_SERIAL */ + } +diff -ruN u-boot-2021.10/arch/mips/mach-mtmips/spl.c u-boot/arch/mips/mach-mtmips/spl.c +--- u-boot-2021.10/arch/mips/mach-mtmips/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-mtmips/spl.c 2021-11-01 17:10:13.852948243 +0100 +@@ -17,7 +17,7 @@ + { + spl_init(); + +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + /* + * mtmips_spl_serial_init() is useful if debug uart is enabled, + * or DM based serial is not enabled. +diff -ruN u-boot-2021.10/arch/mips/mach-pic32/Kconfig u-boot/arch/mips/mach-pic32/Kconfig +--- u-boot-2021.10/arch/mips/mach-pic32/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/mips/mach-pic32/Kconfig 2021-11-01 17:10:13.872947149 +0100 +@@ -9,7 +9,7 @@ + + config SOC_PIC32MZDA + bool "Microchip PIC32MZ[DA] family" +- select MIPS_L1_CACHE_SHIFT_4 ++ select SYS_CACHE_SHIFT_4 + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 +diff -ruN u-boot-2021.10/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S u-boot/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S +--- u-boot-2021.10/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S 2021-11-01 17:10:13.872947149 +0100 +@@ -38,9 +38,9 @@ + * for Orca and Emerald + */ + #define BOARD_ID_REG 0x104 +-#define BOARD_ID_FAMILY_MASK 0xfff000 +-#define BOARD_ID_FAMILY_V5 0x556000 +-#define BOARD_ID_FAMILY_K7 0x74b000 ++#define BOARD_ID_FAMILY_MASK 0xfff000 ++#define BOARD_ID_FAMILY_V5 0x556000 ++#define BOARD_ID_FAMILY_K7 0x74b000 + + /* + * parameters for the static memory controller +@@ -94,7 +94,7 @@ + move $lp, $r11 + ret + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + .globl lowlevel_init + lowlevel_init: + move $r10, $lp +@@ -144,4 +144,4 @@ + ret + #endif + +-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/nds32/cpu/n1213/ag101/lowlevel_init.S u-boot/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +--- u-boot-2021.10/arch/nds32/cpu/n1213/ag101/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/cpu/n1213/ag101/lowlevel_init.S 2021-11-01 17:10:13.872947149 +0100 +@@ -38,9 +38,9 @@ + * for Orca and Emerald + */ + #define BOARD_ID_REG 0x104 +-#define BOARD_ID_FAMILY_MASK 0xfff000 +-#define BOARD_ID_FAMILY_V5 0x556000 +-#define BOARD_ID_FAMILY_K7 0x74b000 ++#define BOARD_ID_FAMILY_MASK 0xfff000 ++#define BOARD_ID_FAMILY_V5 0x556000 ++#define BOARD_ID_FAMILY_K7 0x74b000 + + /* + * parameters for the static memory controller +@@ -164,7 +164,7 @@ + ret + + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + .globl lowlevel_init + lowlevel_init: +@@ -314,4 +314,4 @@ + li $r8, (CONFIG_DEBUG_LED) + swi $r7, [$r8] + ret +-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ +diff -ruN u-boot-2021.10/arch/nds32/cpu/n1213/ag101/watchdog.S u-boot/arch/nds32/cpu/n1213/ag101/watchdog.S +--- u-boot-2021.10/arch/nds32/cpu/n1213/ag101/watchdog.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/cpu/n1213/ag101/watchdog.S 2021-11-01 17:10:13.872947149 +0100 +@@ -16,7 +16,7 @@ + #define WD_ENABLE 0x1 + + ! Turn off the watchdog, according to Faraday FTWDT010 spec +- li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR ++ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR + lwi $p1, [$p0] ! Get the config of WD + andi $p1, $p1, 0x1f ! Wipe out useless bits + li $r0, ~WD_ENABLE +diff -ruN u-boot-2021.10/arch/nds32/cpu/n1213/start.S u-boot/arch/nds32/cpu/n1213/start.S +--- u-boot-2021.10/arch/nds32/cpu/n1213/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/cpu/n1213/start.S 2021-11-01 17:10:13.872947149 +0100 +@@ -20,7 +20,7 @@ + */ + #define ENA_DCAC 2UL + #define DIS_DCAC ~ENA_DCAC +-#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way ++#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way + #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways + #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size + #define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way +@@ -174,7 +174,7 @@ + + jal mem_init + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + jal lowlevel_init + /* + * gp = ~VMA for burn mode +@@ -434,21 +434,21 @@ + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 1 ! Determine interruption type +- bal do_interruption ++ bal do_interruption + + .align 5 + tlb_not_present: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 2 ! Determine interruption type +- bal do_interruption ++ bal do_interruption + + .align 5 + tlb_misc: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 3 ! Determine interruption type +- bal do_interruption ++ bal do_interruption + + .align 5 + tlb_vlpt_miss: +diff -ruN u-boot-2021.10/arch/nds32/include/asm/bootm.h u-boot/arch/nds32/include/asm/bootm.h +--- u-boot-2021.10/arch/nds32/include/asm/bootm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/include/asm/bootm.h 2021-11-01 17:10:13.872947149 +0100 +@@ -12,11 +12,7 @@ + + extern void udc_disconnect(void); + +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + # define BOOTM_ENABLE_TAGS 1 + #else + # define BOOTM_ENABLE_TAGS 0 +diff -ruN u-boot-2021.10/arch/nds32/Kconfig u-boot/arch/nds32/Kconfig +--- u-boot-2021.10/arch/nds32/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/Kconfig 2021-11-01 17:10:13.872947149 +0100 +@@ -18,7 +18,6 @@ + + config SYS_ICACHE_OFF + bool "Do not enable icache" +- default n + help + Do not enable instruction cache in U-Boot. + +@@ -31,7 +30,6 @@ + + config SYS_DCACHE_OFF + bool "Do not enable dcache" +- default n + help + Do not enable data cache in U-Boot. + +diff -ruN u-boot-2021.10/arch/nds32/lib/bootm.c u-boot/arch/nds32/lib/bootm.c +--- u-boot-2021.10/arch/nds32/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nds32/lib/bootm.c 2021-11-01 17:10:13.872947149 +0100 +@@ -19,11 +19,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + static void setup_start_tag(struct bd_info *bd); + + # ifdef CONFIG_SETUP_MEMORY_TAGS +@@ -38,7 +34,7 @@ + static void setup_end_tag(struct bd_info *bd); + + static struct tag *params; +-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ ++#endif /* CONFIG_SUPPORT_PASSING_ATAGS */ + + int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) + { +@@ -82,11 +78,7 @@ + } + #endif + } else if (BOOTM_ENABLE_TAGS) { +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + setup_start_tag(bd); + #ifdef CONFIG_SERIAL_TAG + setup_serial_tag(¶ms); +@@ -127,11 +119,7 @@ + return 1; + } + +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + static void setup_start_tag(struct bd_info *bd) + { + params = (struct tag *)bd->bi_boot_params; +@@ -244,4 +232,17 @@ + params->hdr.size = 0; + } + +-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ ++#endif /* CONFIG_SUPPORT_PASSING_ATAGS */ ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("move %0, $sp" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/nios2/cpu/start.S u-boot/arch/nios2/cpu/start.S +--- u-boot-2021.10/arch/nios2/cpu/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nios2/cpu/start.S 2021-11-01 17:10:13.876280300 +0100 +@@ -6,7 +6,6 @@ + + #include + #include +-#include + + /* + * icache and dcache configuration used only for start.S. +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/nios2/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/nios2/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/nios2/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/nios2/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/nios2/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/nios2/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/nios2/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/leds/common.h u-boot/arch/nios2/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/nios2/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/nios2/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/nios2/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/nios2/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/nios2/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/nios2/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/nios2/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/nios2/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/nios2/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/nios2/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/nios2/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/nios2/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/nios2/lib/bootm.c u-boot/arch/nios2/lib/bootm.c +--- u-boot-2021.10/arch/nios2/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/nios2/lib/bootm.c 2021-11-01 17:10:13.876280300 +0100 +@@ -10,6 +10,9 @@ + #include + #include + #include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; + + #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ + +@@ -60,3 +63,16 @@ + + return 1; + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mov %0, sp" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/ecc.c u-boot/arch/powerpc/cpu/mpc83xx/ecc.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/ecc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/ecc.c 2021-11-01 17:10:13.879613451 +0100 +@@ -11,7 +11,6 @@ + #include + #include + +-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) + void ecc_print_status(void) + { + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +@@ -386,4 +385,3 @@ + " - writes pattern injecting errors with word access\n" + " - writes pattern with word access, generates error\n" + " - disables injects\n" " - re-inits memory"); +-#endif +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 2021-11-01 17:10:13.879613451 +0100 +@@ -22,7 +22,7 @@ + + config BR0_PORTSIZE_32BIT + depends on !BR0_MACHINE_FCM +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++ depends on ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + + endchoice +@@ -58,11 +58,11 @@ + bool "GPCM" + + config BR0_MACHINE_FCM +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "FCM" + + config BR0_MACHINE_SDRAM +- depends on ARCH_MPC8349 || ARCH_MPC8360 ++ depends on ARCH_MPC8360 + bool "SDRAM" + + config BR0_MACHINE_UPMA +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 2021-11-01 17:10:13.879613451 +0100 +@@ -22,7 +22,7 @@ + + config BR1_PORTSIZE_32BIT + depends on !BR1_MACHINE_FCM +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++ depends on ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + + endchoice +@@ -58,11 +58,11 @@ + bool "GPCM" + + config BR1_MACHINE_FCM +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "FCM" + + config BR1_MACHINE_SDRAM +- depends on ARCH_MPC8349 || ARCH_MPC8360 ++ depends on ARCH_MPC8360 + bool "SDRAM" + + config BR1_MACHINE_UPMA +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 2021-11-01 17:10:13.879613451 +0100 +@@ -22,7 +22,7 @@ + + config BR2_PORTSIZE_32BIT + depends on !BR2_MACHINE_FCM +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++ depends on ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + + endchoice +@@ -58,11 +58,11 @@ + bool "GPCM" + + config BR2_MACHINE_FCM +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "FCM" + + config BR2_MACHINE_SDRAM +- depends on ARCH_MPC8349 || ARCH_MPC8360 ++ depends on ARCH_MPC8360 + bool "SDRAM" + + config BR2_MACHINE_UPMA +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 2021-11-01 17:10:13.879613451 +0100 +@@ -22,7 +22,7 @@ + + config BR3_PORTSIZE_32BIT + depends on !BR3_MACHINE_FCM +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++ depends on ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + + endchoice +@@ -58,11 +58,11 @@ + bool "GPCM" + + config BR3_MACHINE_FCM +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "FCM" + + config BR3_MACHINE_SDRAM +- depends on ARCH_MPC8349 || ARCH_MPC8360 ++ depends on ARCH_MPC8360 + bool "SDRAM" + + config BR3_MACHINE_UPMA +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 2021-11-01 17:10:13.879613451 +0100 +@@ -22,7 +22,7 @@ + + config BR4_PORTSIZE_32BIT + depends on !BR4_MACHINE_FCM +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++ depends on ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + + endchoice +@@ -58,11 +58,11 @@ + bool "GPCM" + + config BR4_MACHINE_FCM +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "FCM" + + config BR4_MACHINE_SDRAM +- depends on ARCH_MPC8349 || ARCH_MPC8360 ++ depends on ARCH_MPC8360 + bool "SDRAM" + + config BR4_MACHINE_UPMA +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hid/Kconfig u-boot/arch/powerpc/cpu/mpc83xx/hid/Kconfig +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hid/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/hid/Kconfig 2021-11-01 17:10:13.879613451 +0100 +@@ -434,7 +434,7 @@ + config HID2_IWLCK_2 + bool "Way 0 through 2 locked" + +-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++if ARCH_MPC8360 || ARCH_MPC8379 + + config HID2_IWLCK_3 + bool "Way 0 through 3 locked" +@@ -470,7 +470,7 @@ + config HID2_DWLCK_2 + bool "Way 0 through 2 locked" + +-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 ++if ARCH_MPC8360 || ARCH_MPC8379 + + config HID2_DWLCK_3 + bool "Way 0 through 3 locked" +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h u-boot/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h 2021-11-01 17:10:13.879613451 +0100 +@@ -1,11 +1,3 @@ +-#ifdef CONFIG_ARCH_MPC8349 +-#define TSEC1_MODE_SHIFT 17 +-#define TSEC2_MODE_SHIFT 19 +-#else +-#define TSEC1_MODE_SHIFT 18 +-#define TSEC2_MODE_SHIFT 21 +-#endif +- + #define CONFIG_SYS_HRCW_LOW (\ + (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ + (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ +@@ -28,8 +20,8 @@ + (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ + (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ + (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ +- (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ +- (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ ++ (CONFIG_TSEC1_MODE << (31 - 18)) |\ ++ (CONFIG_TSEC2_MODE << (31 - 21)) |\ + (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ + (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ + (CONFIG_LALE_TIMING << (31 - 29)) |\ +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig u-boot/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig 2021-11-01 17:10:13.879613451 +0100 +@@ -7,7 +7,7 @@ + bool "1 : 1" + + config LBMC_CLOCK_MODE_1_2 +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X ++ depends on ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 2" + + endchoice +@@ -19,12 +19,12 @@ + bool "1 : 2" + + config DDR_MC_CLOCK_MODE_1_1 +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X ++ depends on ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 1" + + endchoice + +-if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 ++if !ARCH_MPC8313 && !ARCH_MPC832X + + choice + prompt "System PLL VCO division" +@@ -67,43 +67,43 @@ + bool "6 : 1" + + config SYSTEM_PLL_FACTOR_7_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "7 : 1" + + config SYSTEM_PLL_FACTOR_8_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "8 : 1" + + config SYSTEM_PLL_FACTOR_9_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "9 : 1" + + config SYSTEM_PLL_FACTOR_10_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "10 : 1" + + config SYSTEM_PLL_FACTOR_11_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "11 : 1" + + config SYSTEM_PLL_FACTOR_12_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "12 : 1" + + config SYSTEM_PLL_FACTOR_13_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "13 : 1" + + config SYSTEM_PLL_FACTOR_14_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "14 : 1" + + config SYSTEM_PLL_FACTOR_15_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X ++ depends on ARCH_MPV8360 || ARCH_MPC837X + bool "15 : 1" + + config SYSTEM_PLL_FACTOR_16_1 +- depends on ARCH_MPC8349 || ARCH_MPV8360 ++ depends on ARCH_MPV8360 + bool "16 : 1" + + endchoice +@@ -310,21 +310,6 @@ + + endchoice + +-if ARCH_MPC8349 +- +-choice +- prompt "PCI 64-bit mode" +- +-config PCI_64BIT_MODE_DISABLE +- bool "Disabled" +- +-config PCI_64BIT_MODE_ENABLE +- bool "Enabled" +- +-endchoice +- +-endif +- + choice + prompt "PCI internal arbiter 1 mode" + +@@ -336,21 +321,6 @@ + + endchoice + +-if ARCH_MPC8349 +- +-choice +- prompt "PCI internal arbiter 2 mode" +- +-config PCI_INT_ARBITER2_DISABLE +- bool "Disabled" +- +-config PCI_INT_ARBITER2_ENABLE +- bool "Enabled" +- +-endchoice +- +-endif +- + if ARCH_MPC8360 + + choice +@@ -425,10 +395,6 @@ + depends on MPC83XX_PCI_SUPPORT + bool "PCI1" + +-config BOOT_ROM_INTERFACE_PCI2 +- depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 +- bool "PCI2" +- + config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + depends on ARCH_MPC837X + bool "PCI2" +@@ -448,15 +414,15 @@ + bool "Local bus GPCM - 16-bit ROM" + + config BOOT_ROM_INTERFACE_GPCM_32BIT +- depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X ++ depends on ARCH_MPC8360 || ARCH_MPC837X + bool "Local bus GPCM - 32-bit ROM" + + config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit small page ROM" + + config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE +- depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 ++ depends on !ARCH_MPC832X && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit large page ROM" + + endchoice +@@ -467,11 +433,10 @@ + prompt "TSEC1 mode" + + config TSEC1_MODE_MII +- depends on !ARCH_MPC8349 + bool "MII" + + config TSEC1_MODE_RMII +- depends on ARCH_MPC831X && !ARCH_MPC8349 ++ depends on ARCH_MPC831X + bool "RMII" + + config TSEC1_MODE_RGMII +@@ -481,14 +446,6 @@ + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +-config TSEC1_MODE_GMII +- depends on ARCH_MPC8349 +- bool "GMII" +- +-config TSEC1_MODE_TBI +- depends on ARCH_MPC8349 +- bool "TBI" +- + config TSEC1_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" +@@ -503,11 +460,10 @@ + prompt "TSEC2 mode" + + config TSEC2_MODE_MII +- depends on !ARCH_MPC8349 + bool "MII" + + config TSEC2_MODE_RMII +- depends on ARCH_MPC831X && !ARCH_MPC8349 ++ depends on ARCH_MPC831X + bool "RMII" + + config TSEC2_MODE_RGMII +@@ -517,14 +473,6 @@ + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +-config TSEC2_MODE_GMII +- depends on ARCH_MPC8349 +- bool "GMII" +- +-config TSEC2_MODE_TBI +- depends on ARCH_MPC8349 +- bool "TBI" +- + config TSEC2_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" +@@ -559,7 +507,7 @@ + + endif + +-if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 ++if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360 + + choice + prompt "LALE timing" +@@ -603,7 +551,7 @@ + + config SYSTEM_PLL_VCO_DIV + int +- default 0 if ARCH_MPC8349 || ARCH_MPC832X ++ default 0 if ARCH_MPC832X + default 2 if ARCH_MPC8313 + default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X + default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X +@@ -675,7 +623,6 @@ + hex + default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM + default 0x4 if BOOT_ROM_INTERFACE_PCI1 +- default 0x8 if BOOT_ROM_INTERFACE_PCI2 + default 0x8 if BOOT_ROM_INTERFACE_ESDHC + default 0xc if BOOT_ROM_INTERFACE_SPI + default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM +@@ -690,26 +637,18 @@ + default 0x0 if !MPC83XX_TSEC1_SUPPORT + default 0x0 if TSEC1_MODE_MII + default 0x1 if TSEC1_MODE_RMII +- default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 +- default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 ++ default 0x3 if TSEC1_MODE_RGMII ++ default 0x5 if TSEC1_MODE_RTBI + default 0x6 if TSEC1_MODE_SGMII +- default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 +- default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 +- default 0x2 if TSEC1_MODE_GMII +- default 0x3 if TSEC1_MODE_TBI + + config TSEC2_MODE + hex + default 0x0 if !MPC83XX_TSEC2_SUPPORT + default 0x0 if TSEC2_MODE_MII + default 0x1 if TSEC2_MODE_RMII +- default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 +- default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 ++ default 0x3 if TSEC2_MODE_RGMII ++ default 0x5 if TSEC2_MODE_RTBI + default 0x6 if TSEC2_MODE_SGMII +- default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 +- default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 +- default 0x2 if TSEC2_MODE_GMII +- default 0x3 if TSEC2_MODE_TBI + + config SECONDARY_DDR_IO + int +@@ -792,9 +731,7 @@ + + config PCI_64BIT_MODE + int +- default 0 if !ARCH_MPC8349 +- default 0 if PCI_64BIT_MODE_DISABLE +- default 1 if PCI_64BIT_MODE_ENABLE ++ default 0 + + config PCI_INT_ARBITER1 + int +@@ -804,9 +741,7 @@ + + config PCI_INT_ARBITER2 + int +- default 0 if !ARCH_MPC8349 +- default 0 if PCI_INT_ARBITER2_DISABLE +- default 1 if PCI_INT_ARBITER2_ENABLE ++ default 0 + + config PCI_CLOCK_OUTPUT_DRIVE + int +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr 2021-11-01 17:10:13.879613451 +0100 +@@ -38,50 +38,6 @@ + + endif + +-if ARCH_MPC8349 +- +-choice +- prompt "TSEC1 emergency priority" +- +-config SPCR_TSEC1EP_UNSET +- bool "Don't set value" +- +-config SPCR_TSEC1EP_0 +- bool "Level 0 (lowest priority)" +- +-config SPCR_TSEC1EP_1 +- bool "Level 1" +- +-config SPCR_TSEC1EP_2 +- bool "Level 2" +- +-config SPCR_TSEC1EP_3 +- bool "Level 3 (highest priority)" +- +-endchoice +- +-choice +- prompt "TSEC2 emergency priority" +- +-config SPCR_TSEC2EP_UNSET +- bool "Don't set value" +- +-config SPCR_TSEC2EP_0 +- bool "Level 0 (lowest priority)" +- +-config SPCR_TSEC2EP_1 +- bool "Level 1" +- +-config SPCR_TSEC2EP_2 +- bool "Level 2" +- +-config SPCR_TSEC2EP_3 +- bool "Level 3 (highest priority)" +- +-endchoice +- +-endif +- + config SPCR_OPT + hex + default 0x0 if SPCR_OPT_UNSET +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/Kconfig u-boot/arch/powerpc/cpu/mpc83xx/Kconfig +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/Kconfig 2021-11-01 17:10:13.876280300 +0100 +@@ -8,22 +8,6 @@ + prompt "Target select" + optional + +-config TARGET_MPC8349EMDS +- bool "Support MPC8349EMDS" +- select ARCH_MPC8349 +- select BOARD_EARLY_INIT_F +- select SYS_FSL_DDR +- select SYS_FSL_DDR_BE +- select SYS_FSL_HAS_DDR2 +- +-config TARGET_MPC8349EMDS_SDRAM +- bool "Support MPC8349EMDS_SDRAM" +- select ARCH_MPC8349 +- select BOARD_EARLY_INIT_F +- select SYS_FSL_DDR +- select SYS_FSL_DDR_BE +- select SYS_FSL_HAS_DDR2 +- + config TARGET_MPC837XERDB + bool "Support MPC837XERDB" + select ARCH_MPC837X +@@ -119,7 +103,7 @@ + config MPC83XX_SDHC_SUPPORT + bool + +-config MPC83XX_SATA_SUPPORT ++config MPC83XX_SATA + bool + + config MPC83XX_SECOND_I2C +@@ -131,6 +115,7 @@ + config ARCH_MPC830X + bool + select MPC83XX_SDHC_SUPPORT ++ select SYS_CACHE_SHIFT_5 + + config ARCH_MPC8308 + bool +@@ -154,6 +139,7 @@ + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT ++ select SYS_CACHE_SHIFT_5 + + config ARCH_MPC8313 + bool +@@ -165,18 +151,11 @@ + bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT ++ select SYS_CACHE_SHIFT_5 + + config ARCH_MPC834X + bool +- +-config ARCH_MPC8349 +- bool +- select ARCH_MPC834X +- select MPC83XX_PCI_SUPPORT +- select MPC83XX_TSEC1_SUPPORT +- select MPC83XX_TSEC2_SUPPORT +- select MPC83XX_LDP_PIN +- select MPC83XX_SECOND_I2C ++ select SYS_CACHE_SHIFT_5 + + config ARCH_MPC8360 + bool +@@ -184,6 +163,7 @@ + select MPC83XX_PCI_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C ++ select SYS_CACHE_SHIFT_5 + + config ARCH_MPC837X + bool +@@ -193,9 +173,10 @@ + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SDHC_SUPPORT +- select MPC83XX_SATA_SUPPORT ++ select MPC83XX_SATA + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C ++ select SYS_CACHE_SHIFT_5 + select FSL_ELBC + + config SYS_IMMR +@@ -214,36 +195,9 @@ + source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" + source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig" + +-menu "Legacy options" +- +-if ARCH_MPC8349 +- +-#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT +-choice +- prompt "PMC slot configuration" +- +-config PCI_ALL_PCI1 +- bool "All PMC slots on PCI1" +- +-config PCI_ONE_PCI1 +- bool "First PMC1 on PCI1" +- +-config PCI_TWO_PCI1 +- bool "First two PMC1 on PCI1" +- +-endchoice +- +-config PCI_64BIT +- bool "PMC2 is 64bit" +- +-endif +- +-endmenu +- + config FSL_ELBC + bool + +-source "board/freescale/mpc8349emds/Kconfig" + source "board/freescale/mpc837xerdb/Kconfig" + source "board/ids/ids8313/Kconfig" + source "board/keymile/Kconfig" +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/Makefile u-boot/arch/powerpc/cpu/mpc83xx/Makefile +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/Makefile 2021-11-01 17:10:13.876280300 +0100 +@@ -26,7 +26,7 @@ + obj-y += cpu_init.o + obj-y += speed.o + obj-y += interrupts.o +-obj-y += ecc.o ++obj-$(CONFIG_DDR_ECC_CMD) += ecc.o + ifndef CONFIG_PINCTRL + obj-$(CONFIG_QE) += qe_io.o + endif +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/pcie.c u-boot/arch/powerpc/cpu/mpc83xx/pcie.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/pcie.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/pcie.c 2021-11-01 17:10:13.879613451 +0100 +@@ -34,148 +34,6 @@ + #endif + }; + +-#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES +- +-/* private structure for mpc83xx pcie hose */ +-static struct mpc83xx_pcie_priv { +- u8 index; +-} pcie_priv[PCIE_MAX_BUSES] = { +- { +- /* pcie controller 1 */ +- .index = 0, +- }, +- { +- /* pcie controller 2 */ +- .index = 1, +- }, +-}; +- +-static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) +-{ +- int bus = PCI_BUS(dev) - hose->first_busno; +- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; +- struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; +- pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; +- struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; +- u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); +- u32 dev_base = bus << 24 | devfn << 16; +- +- if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) +- return -1; +- /* +- * Workaround for the HW bug: for Type 0 configure transactions the +- * PCI-E controller does not check the device number bits and just +- * assumes that the device number bits are 0. +- */ +- if (devfn & 0xf8) +- return -1; +- +- out_le32(&out_win->tarl, dev_base); +- return 0; +-} +- +-#define cfg_read(val, addr, type, op) \ +- do { *val = op((type)(addr)); } while (0) +-#define cfg_write(val, addr, type, op) \ +- do { op((type *)(addr), (val)); } while (0) +- +-#define cfg_read_err(val) do { *val = -1; } while (0) +-#define cfg_write_err(val) do { } while (0) +- +-#define PCIE_OP(rw, size, type, op) \ +-static int pcie_##rw##_config_##size(struct pci_controller *hose, \ +- pci_dev_t dev, int offset, \ +- type val) \ +-{ \ +- int ret; \ +- \ +- ret = mpc83xx_pcie_remap_cfg(hose, dev); \ +- if (ret) { \ +- cfg_##rw##_err(val); \ +- return ret; \ +- } \ +- cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ +- return 0; \ +-} +- +-PCIE_OP(read, byte, u8 *, in_8) +-PCIE_OP(read, word, u16 *, in_le16) +-PCIE_OP(read, dword, u32 *, in_le32) +-PCIE_OP(write, byte, u8, out_8) +-PCIE_OP(write, word, u16, out_le16) +-PCIE_OP(write, dword, u32, out_le32) +- +-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, +- u8 link) +-{ +- extern void disable_addr_trans(void); /* start.S */ +- static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; +- struct pci_controller *hose = &pcie_hose[bus]; +- int i; +- +- /* +- * There are no spare BATs to remap all PCI-E windows for U-Boot, so +- * disable translations. In general, this is not great solution, and +- * that's why we don't register PCI-E hoses by default. +- */ +- disable_addr_trans(); +- +- for (i = 0; i < 2; i++, reg++) { +- if (reg->size == 0) +- break; +- +- hose->regions[i] = *reg; +- hose->region_count++; +- } +- +- i = hose->region_count++; +- hose->regions[i].bus_start = 0; +- hose->regions[i].phys_start = 0; +- hose->regions[i].size = gd->ram_size; +- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; +- +- i = hose->region_count++; +- hose->regions[i].bus_start = CONFIG_SYS_IMMR; +- hose->regions[i].phys_start = CONFIG_SYS_IMMR; +- hose->regions[i].size = 0x100000; +- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; +- +- hose->first_busno = pci_last_busno() + 1; +- hose->last_busno = 0xff; +- +- hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; +- +- hose->priv_data = &pcie_priv[bus]; +- +- pci_set_ops(hose, +- pcie_read_config_byte, +- pcie_read_config_word, +- pcie_read_config_dword, +- pcie_write_config_byte, +- pcie_write_config_word, +- pcie_write_config_dword); +- +- if (!link) +- hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; +- +- pci_register_hose(hose); +- +-#ifdef CONFIG_PCI_SCAN_SHOW +- printf("PCI: Bus Dev VenId DevId Class Int\n"); +-#endif +- /* +- * Hose scan. +- */ +- hose->last_busno = pci_hose_scan(hose); +-} +- +-#else +- +-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, +- u8 link) {} +- +-#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ +- + int get_pcie_clk(int index) + { + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; +@@ -340,8 +198,6 @@ + printf("link\n"); + else + printf("No link\n"); +- +- mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); + } + + /* +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/spd_sdram.c u-boot/arch/powerpc/cpu/mpc83xx/spd_sdram.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/spd_sdram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/spd_sdram.c 2021-11-01 17:10:13.879613451 +0100 +@@ -834,12 +834,6 @@ + #endif + debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); + +-#if defined(CONFIG_DDR_2T_TIMING) +- /* +- * Enable 2T timing by setting sdram_cfg[16]. +- */ +- sdram_cfg |= SDRAM_CFG_2T_EN; +-#endif + /* Enable controller, and GO! */ + ddr->sdram_cfg = sdram_cfg; + sync(); +@@ -914,16 +908,12 @@ + pattern[0] = 0xdeadbeef; + pattern[1] = 0xdeadbeef; + +-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) +- dma_meminit(pattern[0], dram_size); +-#else + debug("ddr init: CPU FP write method\n"); + size = dram_size; + for (p = 0; p < (u64*)(size); p++) { + ppcDWstore((u32*)p, pattern); + } + sync(); +-#endif + + t_end = get_tbms(); + icache_disable(); +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc83xx/start.S u-boot/arch/powerpc/cpu/mpc83xx/start.S +--- u-boot-2021.10/arch/powerpc/cpu/mpc83xx/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc83xx/start.S 2021-11-01 17:10:13.879613451 +0100 +@@ -13,7 +13,6 @@ + #include + #include + #include +-#include + + #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ + +@@ -92,12 +91,6 @@ + */ + .long 0x27051956 /* U-Boot Magic Number */ + +- .globl version_string +-version_string: +- .ascii U_BOOT_VERSION_STRING, "\0" +- +- .align 2 +- + .globl enable_addr_trans + enable_addr_trans: + /* enable address translation */ +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/cpu.c u-boot/arch/powerpc/cpu/mpc85xx/cpu.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/cpu.c 2021-11-01 17:10:13.882946602 +0100 +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -52,7 +53,8 @@ + uint major, minor; + struct cpu_type *cpu; + char buf1[32], buf2[32]; +-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ ++ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + #endif +@@ -70,12 +72,12 @@ + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; + #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + #else /* CONFIG_FSL_CORENET */ +-#ifdef CONFIG_DDR_CLK_FREQ ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + #else + u32 ddr_ratio = 0; +-#endif /* CONFIG_DDR_CLK_FREQ */ ++#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */ + #endif /* CONFIG_FSL_CORENET */ + + unsigned int i, core, nr_cores = cpu_numcores(); +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/ether_fcc.c u-boot/arch/powerpc/cpu/mpc85xx/ether_fcc.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/ether_fcc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/ether_fcc.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,460 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * MPC8560 FCC Fast Ethernet +- * Copyright (c) 2003 Motorola,Inc. +- * Xianghua Xiao, (X.Xiao@motorola.com) +- * +- * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) +- * +- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH +- * Marius Groeger +- */ +- +-/* +- * MPC8560 FCC Fast Ethernet +- * Basic ET HW initialization and packet RX/TX routines +- * +- * This code will not perform the IO port configuration. This should be +- * done in the iop_conf_t structure specific for the board. +- * +- * TODO: +- * add a PHY driver to do the negotiation +- * reflect negotiation results in FPSMR +- * look for ways to configure the board specific stuff elsewhere, eg. +- * config_xxx.h or the board directory +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +-#include +-#endif +- +-#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) +- +-static struct ether_fcc_info_s +-{ +- int ether_index; +- int proff_enet; +- ulong cpm_cr_enet_sblock; +- ulong cpm_cr_enet_page; +- ulong cmxfcr_mask; +- ulong cmxfcr_value; +-} +- ether_fcc_info[] = +-{ +-#ifdef CONFIG_ETHER_ON_FCC1 +-{ +- 0, +- PROFF_FCC1, +- CPM_CR_FCC1_SBLOCK, +- CPM_CR_FCC1_PAGE, +- CONFIG_SYS_CMXFCR_MASK1, +- CONFIG_SYS_CMXFCR_VALUE1 +-}, +-#endif +- +-#ifdef CONFIG_ETHER_ON_FCC2 +-{ +- 1, +- PROFF_FCC2, +- CPM_CR_FCC2_SBLOCK, +- CPM_CR_FCC2_PAGE, +- CONFIG_SYS_CMXFCR_MASK2, +- CONFIG_SYS_CMXFCR_VALUE2 +-}, +-#endif +- +-#ifdef CONFIG_ETHER_ON_FCC3 +-{ +- 2, +- PROFF_FCC3, +- CPM_CR_FCC3_SBLOCK, +- CPM_CR_FCC3_PAGE, +- CONFIG_SYS_CMXFCR_MASK3, +- CONFIG_SYS_CMXFCR_VALUE3 +-}, +-#endif +-}; +- +-/*---------------------------------------------------------------------*/ +- +-/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ +-#define PKT_MAXDMA_SIZE 1520 +- +-/* The FCC stores dest/src/type, data, and checksum for receive packets. */ +-#define PKT_MAXBUF_SIZE 1518 +-#define PKT_MINBUF_SIZE 64 +- +-/* Maximum input buffer size. Must be a multiple of 32. */ +-#define PKT_MAXBLR_SIZE 1536 +- +-#define TOUT_LOOP 1000000 +- +-#define TX_BUF_CNT 2 +- +-static uint rxIdx; /* index of the current RX buffer */ +-static uint txIdx; /* index of the current TX buffer */ +- +-/* +- * FCC Ethernet Tx and Rx buffer descriptors. +- * Provide for Double Buffering +- * Note: PKTBUFSRX is defined in net.h +- */ +- +-typedef volatile struct rtxbd { +- cbd_t rxbd[PKTBUFSRX]; +- cbd_t txbd[TX_BUF_CNT]; +-} RTXBD; +- +-/* Good news: the FCC supports external BDs! */ +-#ifdef __GNUC__ +-static RTXBD rtx __attribute__ ((aligned(8))); +-#else +-#error "rtx must be 64-bit aligned" +-#endif +- +-#undef ET_DEBUG +- +-static int fec_send(struct eth_device *dev, void *packet, int length) +-{ +- int i = 0; +- int result = 0; +- +- if (length <= 0) { +- printf("fec: bad packet size: %d\n", length); +- goto out; +- } +- +- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { +- if (i >= TOUT_LOOP) { +- printf("fec: tx buffer not ready\n"); +- goto out; +- } +- } +- +- rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; +- rtx.txbd[txIdx].cbd_datlen = length; +- rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ +- BD_ENET_TX_TC | BD_ENET_TX_PAD); +- +- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { +- if (i >= TOUT_LOOP) { +- printf("fec: tx error\n"); +- goto out; +- } +- } +- +-#ifdef ET_DEBUG +- printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); +- printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); +- for(i=0;i<(length/16 + 1);i++) { +- printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ +- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ +- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); +- } +-#endif +- +- /* return only status bits */ +- result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; +- txIdx = (txIdx + 1) % TX_BUF_CNT; +- +-out: +- return result; +-} +- +-static int fec_recv(struct eth_device* dev) +-{ +- int length; +- +- for (;;) +- { +- if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { +- length = -1; +- break; /* nothing received - leave for() loop */ +- } +- length = rtx.rxbd[rxIdx].cbd_datlen; +- +- if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { +- printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); +- } +- else { +- /* Pass the packet up to the protocol layers. */ +- net_process_received_packet(net_rx_packets[rxIdx], length - 4); +- } +- +- +- /* Give the buffer back to the FCC. */ +- rtx.rxbd[rxIdx].cbd_datlen = 0; +- +- /* wrap around buffer index when necessary */ +- if ((rxIdx + 1) >= PKTBUFSRX) { +- rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); +- rxIdx = 0; +- } +- else { +- rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; +- rxIdx++; +- } +- } +- return length; +-} +- +- +-static int fec_init(struct eth_device* dev, struct bd_info *bis) +-{ +- struct ether_fcc_info_s * info = dev->priv; +- int i; +- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; +- volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); +- fcc_enet_t *pram_ptr; +- unsigned long mem_addr; +- +-#if 0 +- mii_discover_phy(); +-#endif +- +- /* 28.9 - (1-2): ioports have been set up already */ +- +- /* 28.9 - (3): connect FCC's tx and rx clocks */ +- cpm->im_cpm_mux.cmxuar = 0; /* ATM */ +- cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | +- info->cmxfcr_value; +- +- /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; +- } else if (info->ether_index == 1) { +- cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; +- } else if (info->ether_index == 2) { +- cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; +- } +- +- /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; +- } else if (info->ether_index == 1){ +- cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; +- } else if (info->ether_index == 2){ +- cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; +- } +- +- /* 28.9 - (6): FDSR: Ethernet Syn */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.fdsr = 0xD555; +- } else if (info->ether_index == 1) { +- cpm->im_cpm_fcc2.fdsr = 0xD555; +- } else if (info->ether_index == 2) { +- cpm->im_cpm_fcc3.fdsr = 0xD555; +- } +- +- /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ +- rxIdx = 0; +- txIdx = 0; +- +- /* Setup Receiver Buffer Descriptors */ +- for (i = 0; i < PKTBUFSRX; i++) +- { +- rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; +- rtx.rxbd[i].cbd_datlen = 0; +- rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; +- } +- rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; +- +- /* Setup Ethernet Transmitter Buffer Descriptors */ +- for (i = 0; i < TX_BUF_CNT; i++) +- { +- rtx.txbd[i].cbd_sc = 0; +- rtx.txbd[i].cbd_datlen = 0; +- rtx.txbd[i].cbd_bufaddr = 0; +- } +- rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; +- +- /* 28.9 - (7): initialize parameter ram */ +- pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); +- +- /* clear whole structure to make sure all reserved fields are zero */ +- memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); +- +- /* +- * common Parameter RAM area +- * +- * Allocate space in the reserved FCC area of DPRAM for the +- * internal buffers. No one uses this space (yet), so we +- * can do this. Later, we will add resource management for +- * this area. +- * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 +- * 0x9000 for MPC8541, MPC8555 +- */ +- mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); +- pram_ptr->fen_genfcc.fcc_riptr = mem_addr; +- pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; +- /* +- * Set maximum bytes per receive buffer. +- * It must be a multiple of 32. +- */ +- pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ +- /* localbus SDRAM should be preferred */ +- pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | +- CONFIG_SYS_CPMFCR_RAMTYPE) << 24; +- pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); +- pram_ptr->fen_genfcc.fcc_rbdstat = 0; +- pram_ptr->fen_genfcc.fcc_rbdlen = 0; +- pram_ptr->fen_genfcc.fcc_rdptr = 0; +- /* localbus SDRAM should be preferred */ +- pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | +- CONFIG_SYS_CPMFCR_RAMTYPE) << 24; +- pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); +- pram_ptr->fen_genfcc.fcc_tbdstat = 0; +- pram_ptr->fen_genfcc.fcc_tbdlen = 0; +- pram_ptr->fen_genfcc.fcc_tdptr = 0; +- +- /* protocol-specific area */ +- pram_ptr->fen_statbuf = 0x0; +- pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ +- pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ +- pram_ptr->fen_crcec = 0; +- pram_ptr->fen_alec = 0; +- pram_ptr->fen_disfc = 0; +- pram_ptr->fen_retlim = 15; /* Retry limit threshold */ +- pram_ptr->fen_retcnt = 0; +- pram_ptr->fen_pper = 0; +- pram_ptr->fen_boffcnt = 0; +- pram_ptr->fen_gaddrh = 0; +- pram_ptr->fen_gaddrl = 0; +- pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ +- /* +- * Set Ethernet station address. +- * +- * This is supplied in the board information structure, so we +- * copy that into the controller. +- * So far we have only been given one Ethernet address. We make +- * it unique by setting a few bits in the upper byte of the +- * non-static part of the address. +- */ +-#define ea eth_get_ethaddr() +- pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; +- pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; +- pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; +-#undef ea +- pram_ptr->fen_ibdcount = 0; +- pram_ptr->fen_ibdstart = 0; +- pram_ptr->fen_ibdend = 0; +- pram_ptr->fen_txlen = 0; +- pram_ptr->fen_iaddrh = 0; /* disable hash */ +- pram_ptr->fen_iaddrl = 0; +- pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ +- /* pad pointer. use tiptr since we don't need a specific padding char */ +- pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; +- pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ +- pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ +- +-#if defined(ET_DEBUG) +- printf("parm_ptr(0xff788500) = %p\n",pram_ptr); +- printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", +- pram_ptr->fen_genfcc.fcc_rbase); +- printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", +- pram_ptr->fen_genfcc.fcc_tbase); +-#endif +- +- /* 28.9 - (8)(9): clear out events in FCCE */ +- /* 28.9 - (9): FCCM: mask all events */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.fcce = ~0x0; +- cpm->im_cpm_fcc1.fccm = 0; +- } else if (info->ether_index == 1) { +- cpm->im_cpm_fcc2.fcce = ~0x0; +- cpm->im_cpm_fcc2.fccm = 0; +- } else if (info->ether_index == 2) { +- cpm->im_cpm_fcc3.fcce = ~0x0; +- cpm->im_cpm_fcc3.fccm = 0; +- } +- +- /* 28.9 - (10-12): we don't use ethernet interrupts */ +- +- /* 28.9 - (13) +- * +- * Let's re-initialize the channel now. We have to do it later +- * than the manual describes because we have just now finished +- * the BD initialization. +- */ +- cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, +- info->cpm_cr_enet_sblock, +- 0x0c, +- CPM_CR_INIT_TRX) | CPM_CR_FLG; +- do { +- __asm__ __volatile__ ("eieio"); +- } while (cp->cpcr & CPM_CR_FLG); +- +- /* 28.9 - (14): enable tx/rx in gfmr */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; +- } else if (info->ether_index == 1) { +- cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; +- } else if (info->ether_index == 2) { +- cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; +- } +- +- return 1; +-} +- +-static void fec_halt(struct eth_device* dev) +-{ +- struct ether_fcc_info_s * info = dev->priv; +- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; +- +- /* write GFMR: disable tx/rx */ +- if(info->ether_index == 0) { +- cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); +- } else if(info->ether_index == 1) { +- cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); +- } else if(info->ether_index == 2) { +- cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); +- } +-} +- +-int fec_initialize(struct bd_info *bis) +-{ +- struct eth_device* dev; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) +- { +- dev = (struct eth_device*) malloc(sizeof *dev); +- memset(dev, 0, sizeof *dev); +- +- sprintf(dev->name, "FCC%d", +- ether_fcc_info[i].ether_index + 1); +- dev->priv = ðer_fcc_info[i]; +- dev->init = fec_init; +- dev->halt = fec_halt; +- dev->send = fec_send; +- dev->recv = fec_recv; +- +- eth_register(dev); +- +-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ +- && defined(CONFIG_BITBANGMII) +- int retval; +- struct mii_dev *mdiodev = mdio_alloc(); +- if (!mdiodev) +- return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); +- mdiodev->read = bb_miiphy_read; +- mdiodev->write = bb_miiphy_write; +- +- retval = mdio_register(mdiodev); +- if (retval < 0) +- return retval; +-#endif +- } +- +- return 1; +-} +- +-#endif +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c 2021-11-01 17:10:13.882946602 +0100 +@@ -399,4 +399,3 @@ + #endif + } + } +- +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c 2021-11-01 17:10:13.882946602 +0100 +@@ -885,4 +885,3 @@ + return "150"; + } + } +- +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/Kconfig u-boot/arch/powerpc/cpu/mpc85xx/Kconfig +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/Kconfig 2021-11-01 17:10:13.879613451 +0100 +@@ -48,6 +48,7 @@ + bool "Support MPC8548CDS" + select ARCH_MPC8548 + select FSL_VIA ++ select SYS_CACHE_SHIFT_5 + + config TARGET_P1010RDB_PA + bool "Support P1010RDB_PA" +@@ -316,6 +317,7 @@ + config ARCH_MPC8544 + bool + select FSL_LAW ++ select SYS_CACHE_SHIFT_5 + select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET + select SYS_FSL_HAS_DDR2 +@@ -350,6 +352,7 @@ + config ARCH_P1010 + bool + select FSL_LAW ++ select SYS_CACHE_SHIFT_5 + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 +@@ -395,6 +398,7 @@ + config ARCH_P1020 + bool + select FSL_LAW ++ select SYS_CACHE_SHIFT_5 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 +@@ -490,6 +494,7 @@ + config ARCH_P2020 + bool + select FSL_LAW ++ select SYS_CACHE_SHIFT_5 + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 +@@ -510,6 +515,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005275 +@@ -534,6 +540,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_44 + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 +@@ -563,6 +570,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_44 + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004580 +@@ -601,6 +609,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_44 + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004699 +@@ -624,11 +633,13 @@ + + config ARCH_QEMU_E500 + bool ++ select SYS_CACHE_SHIFT_5 + + config ARCH_T1024 + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008109 +@@ -651,6 +662,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 +@@ -673,6 +685,7 @@ + bool + select E500MC + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 +@@ -696,6 +709,7 @@ + select E500MC + select E6500 + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_47 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 +@@ -718,12 +732,14 @@ + imply CMD_NAND + imply CMD_REGINFO + imply FSL_SATA ++ imply ID_EEPROM + + config ARCH_T4240 + bool + select E500MC + select E6500 + select FSL_LAW ++ select SYS_CACHE_SHIFT_6 + select SYS_FSL_DDR_VER_47 + select SYS_FSL_ERRATUM_A004468 + select SYS_FSL_ERRATUM_A005871 +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/Makefile u-boot/arch/powerpc/cpu/mpc85xx/Makefile +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/Makefile 2021-11-01 17:10:13.879613451 +0100 +@@ -29,7 +29,6 @@ + endif + obj-$(CONFIG_CPM2) += commproc.o + +-obj-$(CONFIG_CPM2) += ether_fcc.o + obj-$(CONFIG_OF_LIBFDT) += fdt.o + obj-$(CONFIG_FSL_CORENET) += liodn.o + obj-$(CONFIG_MP) += mp.o +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/speed.c u-boot/arch/powerpc/cpu/mpc85xx/speed.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/speed.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/speed.c 2021-11-01 17:10:13.882946602 +0100 +@@ -11,6 +11,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -104,8 +105,8 @@ + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else + #endif +-#ifdef CONFIG_DDR_CLK_FREQ +- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) ++ sys_info->freq_ddrbus = get_board_ddr_clk(); + #else + sys_info->freq_ddrbus = sysclk; + #endif +@@ -538,12 +539,12 @@ + /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ + sys_info->freq_ddrbus = sys_info->freq_systembus; + +-#ifdef CONFIG_DDR_CLK_FREQ ++#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + { + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + if (ddr_ratio != 0x7) +- sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; ++ sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk(); + } + #endif + +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc85xx/start.S u-boot/arch/powerpc/cpu/mpc85xx/start.S +--- u-boot-2021.10/arch/powerpc/cpu/mpc85xx/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc85xx/start.S 2021-11-01 17:10:13.882946602 +0100 +@@ -14,7 +14,6 @@ + #include + #include + #include +-#include + + #include + #include +@@ -77,7 +76,7 @@ + _start_e500: + /* Enable debug exception */ + li r1,MSR_DE +- mtmsr r1 ++ mtmsr r1 + + /* + * If we got an ePAPR device tree pointer passed in as r3, we need that +@@ -1138,11 +1137,7 @@ + .globl _start + _start: + .long 0x27051956 /* U-BOOT Magic Number */ +- .globl version_string +-version_string: +- .ascii U_BOOT_VERSION_STRING, "\0" + +- .align 4 + .globl _start_cont + _start_cont: + /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ +@@ -1164,9 +1159,9 @@ + + li r0,0 + +-1: subi r4,r4,4 +- stw r0,0(r4) +- cmplw r4,r3 ++1: subi r4,r4,4 ++ stw r0,0(r4) ++ cmplw r4,r3 + bne 1b + + #if CONFIG_VAL(SYS_MALLOC_F_LEN) +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc8xx/Kconfig u-boot/arch/powerpc/cpu/mpc8xx/Kconfig +--- u-boot-2021.10/arch/powerpc/cpu/mpc8xx/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc8xx/Kconfig 2021-11-01 17:10:13.886279753 +0100 +@@ -19,9 +19,11 @@ + + config MPC866 + bool "MPC866" ++ select SYS_CACHE_SHIFT_4 + + config MPC885 + bool "MPC885" ++ select SYS_CACHE_SHIFT_4 + + endchoice + +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc8xx/start.S u-boot/arch/powerpc/cpu/mpc8xx/start.S +--- u-boot-2021.10/arch/powerpc/cpu/mpc8xx/start.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc8xx/start.S 2021-11-01 17:10:13.886279753 +0100 +@@ -23,7 +23,6 @@ + #include + #include + #include +-#include + + #include + #include +@@ -62,9 +61,6 @@ + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ +- .globl version_string +-version_string: +- .ascii U_BOOT_VERSION_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +diff -ruN u-boot-2021.10/arch/powerpc/cpu/mpc8xxx/cpu.c u-boot/arch/powerpc/cpu/mpc8xxx/cpu.c +--- u-boot-2021.10/arch/powerpc/cpu/mpc8xxx/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/cpu/mpc8xxx/cpu.c 2021-11-01 17:10:13.886279753 +0100 +@@ -351,10 +351,6 @@ + */ + int cpu_eth_init(struct bd_info *bis) + { +-#if defined(CONFIG_ETHER_ON_FCC) +- fec_initialize(bis); +-#endif +- + #if defined(CONFIG_UEC_ETH) + uec_standard_init(bis); + #endif +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/cache.h u-boot/arch/powerpc/include/asm/cache.h +--- u-boot-2021.10/arch/powerpc/include/asm/cache.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/cache.h 2021-11-01 17:10:13.892946055 +0100 +@@ -25,13 +25,6 @@ + */ + #define ARCH_DMA_MINALIGN L1_CACHE_BYTES + +-/* +- * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too +- */ +-#ifndef CONFIG_SYS_CACHELINE_SIZE +-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES +-#endif +- + #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) + #define L1_CACHE_PAGES 8 + +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/config.h u-boot/arch/powerpc/include/asm/config.h +--- u-boot-2021.10/arch/powerpc/include/asm/config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/config.h 2021-11-01 17:10:13.892946055 +0100 +@@ -26,15 +26,6 @@ + #endif + #endif + +-/* Check if boards need to enable FSL DMA engine for SDRAM init */ +-#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) +-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ +- ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ +- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) +-#define CONFIG_FSL_DMA +-#endif +-#endif +- + /* + * Provide a default boot page translation virtual address that lines up with + * Freescale's default e500 reset page. +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/config_mpc85xx.h u-boot/arch/powerpc/include/asm/config_mpc85xx.h +--- u-boot-2021.10/arch/powerpc/include/asm/config_mpc85xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/config_mpc85xx.h 2021-11-01 17:10:13.892946055 +0100 +@@ -167,7 +167,6 @@ + #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 + #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 + #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_ESDHC_HC_BLK_ADDR + + #elif defined(CONFIG_ARCH_BSC9132) +@@ -179,7 +178,6 @@ + #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 + #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 + #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK + #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" + #define CONFIG_ESDHC_HC_BLK_ADDR +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/fsl_lbc.h u-boot/arch/powerpc/include/asm/fsl_lbc.h +--- u-boot-2021.10/arch/powerpc/include/asm/fsl_lbc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/fsl_lbc.h 2021-11-01 17:10:13.892946055 +0100 +@@ -294,8 +294,8 @@ + #define LBCR_EPAR_SHIFT 16 + #define LBCR_BMT 0x0000FF00 + #define LBCR_BMT_SHIFT 8 +-#define LBCR_BMTPS 0x0000000F +-#define LBCR_BMTPS_SHIFT 0 ++#define LBCR_BMTPS 0x0000000F ++#define LBCR_BMTPS_SHIFT 0 + + /* LCRR - Clock Ratio Register + */ +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/immap_85xx.h u-boot/arch/powerpc/include/asm/immap_85xx.h +--- u-boot-2021.10/arch/powerpc/include/asm/immap_85xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/immap_85xx.h 2021-11-01 17:10:13.896279206 +0100 +@@ -1510,7 +1510,7 @@ + */ + + typedef struct cpc_corenet { +- u32 cpccsr0; /* Config/status reg */ ++ u32 cpccsr0; /* Config/status reg */ + u32 res1; + u32 cpccfg0; /* Configuration register */ + u32 res2; +@@ -1573,7 +1573,7 @@ + #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 + #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a + #define CPC_SRCR0_SRAMEN 0x00000001 +-#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ ++#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ + #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 + #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 + #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +diff -ruN u-boot-2021.10/arch/powerpc/include/asm/processor.h u-boot/arch/powerpc/include/asm/processor.h +--- u-boot-2021.10/arch/powerpc/include/asm/processor.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/include/asm/processor.h 2021-11-01 17:10:13.896279206 +0100 +@@ -46,11 +46,7 @@ + #define MSR_RI (1<<1) /* Recoverable Exception */ + #define MSR_LE (1<<0) /* Little Endian */ + +-#ifdef CONFIG_APUS_FAST_EXCEPT +-#define MSR_ MSR_ME|MSR_IP|MSR_RI +-#else + #define MSR_ MSR_ME|MSR_RI +-#endif + #ifndef CONFIG_E500 + #define MSR_KERNEL MSR_|MSR_IR|MSR_DR + #else +@@ -752,7 +748,7 @@ + #define MAS5 SPRN_MAS5 + #define MAS6 SPRN_MAS6 + #define MAS7 SPRN_MAS7 +-#define MAS8 SPRN_MAS8 ++#define MAS8 SPRN_MAS8 + + #if defined(CONFIG_MPC85xx) + #define DAR_DEAR DEAR +diff -ruN u-boot-2021.10/arch/powerpc/lib/bootm.c u-boot/arch/powerpc/lib/bootm.c +--- u-boot-2021.10/arch/powerpc/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/lib/bootm.c 2021-11-01 17:10:13.896279206 +0100 +@@ -119,7 +119,7 @@ + void arch_lmb_reserve(struct lmb *lmb) + { + phys_size_t bootm_size; +- ulong size, sp, bootmap_base; ++ ulong size, bootmap_base; + + bootmap_base = env_get_bootm_low(); + bootm_size = env_get_bootm_size(); +@@ -141,21 +141,7 @@ + lmb_reserve(lmb, base, bootm_size - size); + } + +- /* +- * Booting a (Linux) kernel image +- * +- * Allocate space for command line and board info - the +- * address should be as high as possible within the reach of +- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused +- * memory, which means far enough below the current stack +- * pointer. +- */ +- sp = get_sp(); +- debug("## Current stack ends at 0x%08lx\n", sp); +- +- /* adjust sp by 4K to be safe */ +- sp -= 4096; +- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); + + #ifdef CONFIG_MP + cpu_mp_lmb_reserve(lmb); +diff -ruN u-boot-2021.10/arch/powerpc/lib/ppccache.S u-boot/arch/powerpc/lib/ppccache.S +--- u-boot-2021.10/arch/powerpc/lib/ppccache.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/powerpc/lib/ppccache.S 2021-11-01 17:10:13.896279206 +0100 +@@ -104,4 +104,3 @@ + sync /* wait for dcbi's to get to ram */ + #endif + blr +- +diff -ruN u-boot-2021.10/arch/riscv/cpu/ax25/cpu.c u-boot/arch/riscv/cpu/ax25/cpu.c +--- u-boot-2021.10/arch/riscv/cpu/ax25/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/cpu/ax25/cpu.c 2021-11-01 17:10:13.899612357 +0100 +@@ -9,6 +9,22 @@ + #include + #include + #include ++#include ++ ++#define CSR_MCACHE_CTL 0x7ca ++#define CSR_MMISC_CTL 0x7d0 ++#define CSR_MARCHID 0xf12 ++ ++#define V5_MCACHE_CTL_IC_EN_OFFSET 0 ++#define V5_MCACHE_CTL_DC_EN_OFFSET 1 ++#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 ++#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 ++ ++#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) ++#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) ++#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) ++#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) ++ + + /* + * cleanup_before_linux() is called just before we call linux +@@ -27,3 +43,29 @@ + + return 0; + } ++ ++void harts_early_init(void) ++{ ++ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { ++ unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); ++ ++ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) ++ mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; ++ if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) ++ mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; ++ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) ++ mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; ++ csr_write(CSR_MCACHE_CTL, mcache_ctl_val); ++ ++ /* ++ * Check DC_COHEN_EN, if cannot write to mcache_ctl, ++ * we assume this bitmap not support L2 CM ++ */ ++ mcache_ctl_val = csr_read(CSR_MCACHE_CTL); ++ if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { ++ /* Wait for DC_COHSTA bit be set */ ++ while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) ++ mcache_ctl_val = csr_read(CSR_MCACHE_CTL); ++ } ++ } ++} +diff -ruN u-boot-2021.10/arch/riscv/cpu/cpu.c u-boot/arch/riscv/cpu/cpu.c +--- u-boot-2021.10/arch/riscv/cpu/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/cpu/cpu.c 2021-11-01 17:10:13.899612357 +0100 +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -138,7 +139,17 @@ + + int arch_early_init_r(void) + { +- return riscv_cpu_probe(); ++ int ret; ++ ++ ret = riscv_cpu_probe(); ++ if (ret) ++ return ret; ++ ++ if (IS_ENABLED(CONFIG_SYSRESET_SBI)) ++ device_bind_driver(gd->dm_root, "sbi-sysreset", ++ "sbi-sysreset", NULL); ++ ++ return 0; + } + + /** +diff -ruN u-boot-2021.10/arch/riscv/cpu/Makefile u-boot/arch/riscv/cpu/Makefile +--- u-boot-2021.10/arch/riscv/cpu/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/cpu/Makefile 2021-11-01 17:10:13.899612357 +0100 +@@ -5,3 +5,4 @@ + extra-y = start.o + + obj-y += cpu.o mtrap.o ++obj-y += thead/cache.o +diff -ruN u-boot-2021.10/arch/riscv/cpu/thead/cache.c u-boot/arch/riscv/cpu/thead/cache.c +--- u-boot-2021.10/arch/riscv/cpu/thead/cache.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/riscv/cpu/thead/cache.c 2021-11-01 17:10:13.899612357 +0100 +@@ -0,0 +1,119 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++ ++#define CSR_MHCR 0x7c1 ++#define CSR_MCOR 0x7c2 ++#define CSR_MHINT 0x7c5 ++ ++#define MHCR_IE BIT(0) /* icache enable */ ++#define MHCR_DE BIT(1) /* dcache enable */ ++#define MHCR_WA BIT(2) /* dcache write allocate */ ++#define MHCR_WB BIT(3) /* dcache write back */ ++#define MHCR_RS BIT(4) /* return stack enable */ ++#define MHCR_BPE BIT(5) /* branch prediction enable */ ++#define MHCR_BTB BIT(6) /* branch target prediction enable */ ++#define MHCR_WBR BIT(8) /* write burst enable */ ++#define MHCR_L0BTB BIT(12) ++ ++#define MCOR_CACHE_SEL_ICACHE (0x1 << 0) ++#define MCOR_CACHE_SEL_DCACHE (0x2 << 0) ++#define MCOR_CACHE_SEL_BOTH (0x3 << 0) ++#define MCOR_INV BIT(4) ++#define MCOR_CLR BIT(5) ++#define MCOR_BHT_INV BIT(16) ++#define MCOR_BTB_INV BIT(17) ++ ++#define MHINT_DPLD BIT(2) /* dcache prefetch enable */ ++#define MHINT_AMR_PAGE (0x0 << 3) ++#define MHINT_AMR_LIMIT_3 (0x1 << 3) ++#define MHINT_AMR_LIMIT_64 (0x2 << 3) ++#define MHINT_AMR_LIMIT_128 (0x3 << 3) ++#define MHINT_IPLD BIT(8) /* icache prefetch enable */ ++#define MHINT_IWPE BIT(9) /* icache prediction enable */ ++#define MHINT_DIS_PREFETCH_2 (0x0 << 13) ++#define MHINT_DIS_PREFETCH_4 (0x1 << 13) ++#define MHINT_DIS_PREFETCH_8 (0x2 << 13) ++#define MHINT_DIS_PREFETCH_16 (0x3 << 13) ++ ++#define sync_i() asm volatile (".long 0x01a0000b" ::: "memory") ++ ++void flush_dcache_all(void) ++{ ++ asm volatile (".long 0x0030000b" ::: "memory"); /* dcache.ciall */ ++ sync_i(); ++} ++ ++void flush_dcache_range(unsigned long start, unsigned long end) ++{ ++ register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE; ++ ++ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) ++ asm volatile (".long 0x02b5000b" ::: "memory"); /* dcache.cipa a0 */ ++ sync_i(); ++} ++ ++void invalidate_icache_range(unsigned long start, unsigned long end) ++{ ++ register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE; ++ ++ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) ++ asm volatile (".long 0x0385000b" ::: "memory"); /* icache.ipa a0 */ ++ sync_i(); ++} ++ ++void invalidate_dcache_range(unsigned long start, unsigned long end) ++{ ++ register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE; ++ ++ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) ++ asm volatile (".long 0x02a5000b" ::: "memory"); /* dcache.ipa a0 */ ++ sync_i(); ++} ++ ++#if 0 ++void icache_enable(void) ++{ ++ asm volatile (".long 0x0100000b" ::: "memory"); /* icache.iall */ ++ sync_i(); ++ csr_set(CSR_MHCR, MHCR_IE | MHCR_RS | MHCR_BPE | MHCR_BTB | MHCR_L0BTB); ++ csr_set(CSR_MHINT, MHINT_IPLD | MHINT_IWPE); ++} ++ ++void icache_disable(void) ++{ ++ csr_clear(CSR_MHCR, MHCR_IE); ++} ++ ++int icache_status(void) ++{ ++ return csr_read(CSR_MHCR) & MHCR_IE; ++} ++ ++void dcache_enable(void) ++{ ++ asm volatile (".long 0x0020000b" ::: "memory"); /* dcache.iall */ ++ sync_i(); ++ csr_set(CSR_MHCR, MHCR_DE | MHCR_WA | MHCR_WB | MHCR_WBR); ++ csr_set(CSR_MHINT, MHINT_DPLD | MHINT_AMR_LIMIT_3); ++} ++ ++void dcache_disable(void) ++{ ++ asm volatile (".long 0x0010000b" ::: "memory"); /* dcache.call */ ++ sync_i(); ++ csr_clear(CSR_MHCR, MHCR_DE); ++} ++ ++int dcache_status(void) ++{ ++ return csr_read(CSR_MHCR) & MHCR_DE; ++} ++ ++void enable_caches(void) ++{ ++ icache_enable(); ++ dcache_enable(); ++} ++#endif +diff -ruN u-boot-2021.10/arch/riscv/dts/Makefile u-boot/arch/riscv/dts/Makefile +--- u-boot-2021.10/arch/riscv/dts/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/dts/Makefile 2021-11-01 17:10:13.899612357 +0100 +@@ -7,6 +7,7 @@ + dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb + dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb + dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb ++dtb-$(CONFIG_TARGET_SUNXI) += sun20i-d1-nezha.dtb + + targets += $(dtb-y) + +diff -ruN u-boot-2021.10/arch/riscv/dts/sun20i-d1.dtsi u-boot/arch/riscv/dts/sun20i-d1.dtsi +--- u-boot-2021.10/arch/riscv/dts/sun20i-d1.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/riscv/dts/sun20i-d1.dtsi 2021-11-01 17:10:13.899612357 +0100 +@@ -0,0 +1,1158 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2021 Samuel Holland ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ // FIXME: no riscv architecture support for cpufreq ++ cpu_opp_table: cpu-opp-table { ++ compatible = "allwinner,sun20i-d1-operating-points", ++ "allwinner,sun50i-h6-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ ++ opp-1080000000 { ++ // FIXME: this is probably wrong now. ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1008000000>; ++ ++ // FIXME: derive a real voltage range. ++ opp-microvolt-speed0 = <1100000>; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <24000000>; ++ ++ cpu0: cpu@0 { ++ // FIXME: is this the right compatible? ++ compatible = "thead,c906", "riscv"; ++ device_type = "cpu"; ++ reg = <0>; ++ clocks = <&ccu CLK_RISCV>; ++ clock-frequency = <24000000>; ++ #cooling-cells = <2>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <32768>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp_table>; ++ riscv,isa = "rv64imafdc"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #address-cells = <0>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ }; ++ ++ osc24M: osc24M_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "osc24M"; ++ }; ++ ++ // FIXME: depends on what T-HEAD tries to upstream. ++ pmu { ++ compatible = "thead,c900-pmu"; ++ }; ++ ++ thermal-zones { ++ cpu-thermal { ++ polling-delay = <0>; ++ polling-delay-passive = <0>; ++ thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_target: cpu-target { ++ hysteresis = <3000>; ++ temperature = <85000>; ++ type = "passive"; ++ }; ++ ++ cpu-crit { ++ hysteresis = <0>; ++ temperature = <110000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_target>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ interrupt-parent = <&intc>; ++ ++ // TODO: write a binding and driver. ++ dsp: dsp@1700000 { ++ compatible = "allwinner,sun20i-d1-dsp"; ++ reg = <0x1700000 0x400>; ++ reg-names = "cfg"; ++ clocks = <&ccu CLK_BUS_DSP_CFG>, ++ <&ccu CLK_DSP>; ++ clock-names = "cfg", "dsp"; ++ resets = <&ccu RST_BUS_DSP_CFG>, ++ <&ccu RST_BUS_DSP_DBG>, ++ <&ccu RST_DSP>; ++ allwinner,sram = <&dsp_sram 1>; ++ interrupts = <136 IRQ_TYPE_LEVEL_HIGH>, ++ <137 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "dee", "pfe"; ++ // FIXME: this will be different for R528 (CPUX). ++ mboxes = <&riscv_msgbox MBOX_USER_DSP MBOX_RX>, ++ <&dsp_msgbox MBOX_USER_RISCV MBOX_TX>; ++ mbox-names = "rx", "tx"; ++ }; ++ ++ dsp_wdt: watchdog@1700400 { ++ compatible = "allwinner,sun20i-d1-wdt"; ++ reg = <0x1700400 0x20>; ++ clocks = <&osc24M>; ++ interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; ++ status = "reserved"; ++ }; ++ ++ // TODO: write a binding and driver. ++ dsp_msgbox: mailbox@1701000 { ++ compatible = "allwinner,sun20i-d1-msgbox"; ++ reg = <0x1701000 0x1000>; ++ clocks = <&ccu CLK_BUS_MSGBOX1>; ++ resets = <&ccu RST_BUS_MSGBOX1>; ++ interrupts = <139 IRQ_TYPE_LEVEL_HIGH>, ++ <140 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; ++ #mbox-cells = <2>; ++ }; ++ ++ ve: video-codec@1c0e000 { ++ compatible = "allwinner,sun20i-d1-video-engine"; ++ reg = <0x1c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, ++ <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ allwinner,sram = <&ve_sram 1>; ++ interconnects = <&mbus 4>; ++ interconnect-names = "dma-mem"; ++ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>; ++ iommus = <&iommu 0>; ++ }; ++ ++ gpio: pinctrl@2000000 { ++ compatible = "allwinner,sun20i-d1-pinctrl"; ++ #address-cells = <0>; ++ reg = <0x2000000 0x800>; ++ clocks = <&ccu CLK_APB0>, ++ <&osc24M>, ++ <&rtc CLK_OSC32K>; ++ clock-names = "apb", "hosc", "losc"; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, ++ <87 IRQ_TYPE_LEVEL_HIGH>, ++ <89 IRQ_TYPE_LEVEL_HIGH>, ++ <91 IRQ_TYPE_LEVEL_HIGH>, ++ <93 IRQ_TYPE_LEVEL_HIGH>, ++ <95 IRQ_TYPE_LEVEL_HIGH>; ++ // FIXME: not in binding, should we add these? ++ interrupt-names = "pb", "pc", "pd", "pe", "pf", "pg"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ ++ /omit-if-no-ref/ ++ i2c0_pb10_pins: i2c0-pb10-pins { ++ pins = "PB10", "PB11"; ++ function = "i2c0"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2_pb0_pins: i2c2-pb0-pins { ++ pins = "PB0", "PB1"; ++ function = "i2c2"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3_pb6_pins: i2c3-pb6-pins { ++ pins = "PB6", "PB7"; ++ function = "i2c3"; ++ }; ++ ++ /omit-if-no-ref/ ++ mmc0_pins: mmc0-pins { ++ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; ++ function = "mmc0"; ++ }; ++ ++ /omit-if-no-ref/ ++ mmc1_pins: mmc1-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; ++ function = "mmc1"; ++ }; ++ ++ /omit-if-no-ref/ ++ mmc2_pins: mmc2-pins { ++ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; ++ function = "mmc2"; ++ }; ++ ++ /omit-if-no-ref/ ++ rgmii_pe_pins: rgmii-pe-pins { ++ pins = "PE0", "PE1", "PE2", "PE3", "PE4", ++ "PE5", "PE6", "PE7", "PE8", "PE9", ++ "PE11", "PE12", "PE13", "PE14", "PE15"; ++ function = "emac"; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0_pins: spi0-pins { ++ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; ++ function = "spi0"; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1_pb_pins: spi1-pb-pins { ++ pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12"; ++ function = "spi1"; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1_pd_pins: spi1-pd-pins { ++ pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15"; ++ function = "spi1"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_pb8_pins: uart0-pb8-pins { ++ pins = "PB8", "PB9"; ++ function = "uart0"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1_pg6_pins: uart1-pg6-pins { ++ pins = "PG6", "PG7"; ++ function = "uart1"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { ++ pins = "PG8", "PG9"; ++ function = "uart1"; ++ }; ++ }; ++ ++ pwm: pwm@2000c00 { ++ compatible = "allwinner,sun20i-d1-pwm"; ++ reg = <0x2000c00 0x400>; ++ clocks = <&ccu CLK_BUS_PWM>, <&osc24M>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_PWM>; ++ interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ ccu: clock-controller@2001000 { ++ compatible = "allwinner,sun20i-d1-ccu"; ++ reg = <0x2001000 0x1000>; ++ clocks = <&osc24M>, ++ <&rtc CLK_OSC32K>, ++ <&rtc CLK_IOSC>; ++ clock-names = "hosc", "losc", "iosc"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ // TODO: write a binding and driver. ++ ir_tx: irled@2003000 { ++ compatible = "allwinner,sun20i-d1-ir-tx"; ++ reg = <0x2003000 0x400>; ++ clocks = <&ccu CLK_BUS_IR_TX>, ++ <&osc24M>, ++ <&ccu CLK_IR_TX>; ++ clock-names = "bus", "pclk", "mclk"; ++ resets = <&ccu RST_BUS_IR_TX>; ++ dmas = <&dma 13>; ++ dma-names = "tx"; ++ interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ ledc: led-controller@2008000 { ++ compatible = "allwinner,sun20i-d1-ledc", ++ "allwinner,sun50i-r329-ledc"; ++ reg = <0x2008000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_LEDC>; ++ dmas = <&dma 42>; ++ dma-names = "tx"; ++ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a binding and driver. ++ gpadc: adc@2009000 { ++ compatible = "allwinner,sun20i-d1-gpadc"; ++ reg = <0x2009000 0x400>; ++ clocks = <&ccu CLK_BUS_GPADC>; ++ resets = <&ccu RST_BUS_GPADC>; ++ dmas = <&dma 12>; ++ dma-names = "rx"; ++ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ ths: temperature-sensor@2009400 { ++ compatible = "allwinner,sun20i-d1-ths"; ++ reg = <0x2009400 0x400>; ++ clocks = <&ccu CLK_BUS_THS>, <&osc24M>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_THS>; ++ interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; ++ nvmem-cells = <&ths_calib>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <0>; ++ }; ++ ++ lradc: keys@2009800 { ++ compatible = "allwinner,sun20i-d1-lradc"; ++ reg = <0x2009800 0x400>; ++ clocks = <&ccu CLK_BUS_LRADC>; ++ resets = <&ccu RST_BUS_LRADC>; ++ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a binding and driver. ++ tpadc: touchscreen@2009c00 { ++ compatible = "allwinner,sun20i-d1-ts"; ++ reg = <0x2009c00 0x400>; ++ clocks = <&ccu CLK_BUS_TPADC>, <&ccu CLK_TPADC>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_TPADC>; ++ dmas = <&dma 13>; ++ dma-names = "rx"; ++ interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // FIXME: this driver probably needs updates. ++ iommu: iommu@2010000 { ++ compatible = "allwinner,sun20i-d1-iommu"; ++ reg = <0x2010000 0x10000>; ++ clocks = <&ccu CLK_BUS_IOMMU>; ++ interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; ++ #iommu-cells = <1>; ++ }; ++ ++ codec: audio-codec@2030000 { ++ compatible = "allwinner,sun20i-d1-audio-codec"; ++ reg = <0x2030000 0x1000>; ++ clocks = <&ccu CLK_BUS_AUDIO>, ++ <&ccu CLK_AUDIO_ADC>, ++ <&ccu CLK_AUDIO_DAC>, ++ <&osc24M>, ++ <&rtc CLK_OSC32K>; ++ clock-names = "bus", "adc", "dac", "hosc", "losc"; ++ resets = <&ccu RST_BUS_AUDIO>; ++ dmas = <&dma 7>, <&dma 7>; ++ dma-names = "rx", "tx"; ++ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ ++ regulators { ++ reg_aldo: aldo { ++ regulator-name = "aldo"; ++ }; ++ ++ reg_hpldo: hpldo { ++ regulator-name = "hpldo"; ++ }; ++ }; ++ ++ }; ++ ++ // TODO: try the posted driver. ++ dmic: dmic@2031000 { ++ compatible = "allwinner,sun20i-d1-dmic"; ++ reg = <0x2031000 0x400>; ++ clocks = <&ccu CLK_BUS_DMIC>, ++ <&ccu CLK_DMIC>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_DMIC>; ++ dmas = <&dma 8>; ++ dma-names = "rx"; ++ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s0: i2s@2032000 { ++ compatible = "allwinner,sun20i-d1-i2s"; ++ reg = <0x2032000 0x1000>; ++ clocks = <&ccu CLK_BUS_I2S0>, ++ <&ccu CLK_I2S0>; ++ clock-names = "apb", "mod"; ++ resets = <&ccu RST_BUS_I2S0>; ++ dmas = <&dma 3>, <&dma 3>; ++ dma-names = "rx", "tx"; ++ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s1: i2s@2033000 { ++ compatible = "allwinner,sun20i-d1-i2s"; ++ reg = <0x2033000 0x1000>; ++ clocks = <&ccu CLK_BUS_I2S1>, ++ <&ccu CLK_I2S1>; ++ clock-names = "apb", "mod"; ++ resets = <&ccu RST_BUS_I2S1>; ++ dmas = <&dma 4>, <&dma 4>; ++ dma-names = "rx", "tx"; ++ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ // TODO: how to integrate ASRC? same or separate node? ++ i2s2: i2s@2034000 { ++ compatible = "allwinner,sun20i-d1-i2s"; ++ reg = <0x2034000 0x1000>; ++ clocks = <&ccu CLK_BUS_I2S2>, ++ <&ccu CLK_I2S2>; ++ clock-names = "apb", "mod"; ++ resets = <&ccu RST_BUS_I2S2>; ++ dmas = <&dma 5>, <&dma 5>; ++ dma-names = "rx", "tx"; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ // TODO: add receive functionality ++ spdif: spdif@2036000 { ++ compatible = "allwinner,sun20i-d1-spdif"; ++ reg = <0x2036000 0x400>; ++ clocks = <&ccu CLK_BUS_SPDIF>, ++ <&ccu CLK_SPDIF_RX>, ++ <&ccu CLK_SPDIF_TX>; ++ clock-names = "apb", "rx", "tx"; ++ resets = <&ccu RST_BUS_SPDIF>; ++ dmas = <&dma 2>, <&dma 2>; ++ dma-names = "rx", "tx"; ++ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ timer: timer@2050000 { ++ compatible = "allwinner,sun20i-d1-timer", ++ "allwinner,sun8i-a23-timer"; ++ reg = <0x2050000 0xa0>; ++ clocks = <&osc24M>; ++ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, ++ <76 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ wdt: watchdog@20500a0 { ++ compatible = "allwinner,sun20i-d1-wdt-reset", ++ "allwinner,sun20i-d1-wdt"; ++ reg = <0x20500a0 0x20>; ++ clocks = <&osc24M>; ++ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; ++ status = "reserved"; ++ }; ++ ++ // TODO: write a driver. ++ uart0: serial@2500000 { ++ compatible = "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2500000 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART0>; ++ resets = <&ccu RST_BUS_UART0>; ++ dmas = <&dma 14>, <&dma 14>; ++ dma-names = "rx", "tx"; ++ fifo-size = <64>; ++ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a driver, add IDMA? ++ uart1: serial@2500400 { ++ compatible = "allwinner,sun20i-d1-uart1", ++ "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2500400 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART1>; ++ resets = <&ccu RST_BUS_UART1>; ++ dmas = <&dma 15>, <&dma 15>; ++ dma-names = "rx", "tx"; ++ fifo-size = <256>; ++ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a driver. ++ uart2: serial@2500800 { ++ compatible = "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2500800 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART2>; ++ resets = <&ccu RST_BUS_UART2>; ++ dmas = <&dma 16>, <&dma 16>; ++ dma-names = "rx", "tx"; ++ fifo-size = <256>; ++ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a driver. ++ uart3: serial@2500c00 { ++ compatible = "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2500c00 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART3>; ++ resets = <&ccu RST_BUS_UART3>; ++ dmas = <&dma 17>, <&dma 17>; ++ dma-names = "rx", "tx"; ++ fifo-size = <256>; ++ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a driver. ++ uart4: serial@2501000 { ++ compatible = "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2501000 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART4>; ++ resets = <&ccu RST_BUS_UART4>; ++ dmas = <&dma 18>, <&dma 18>; ++ dma-names = "rx", "tx"; ++ fifo-size = <256>; ++ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ // TODO: write a driver. ++ uart5: serial@2501400 { ++ compatible = "allwinner,sun20i-d1-uart", ++ "snps,dw-apb-uart"; ++ reg = <0x2501400 0x400>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ clocks = <&ccu CLK_BUS_UART5>; ++ resets = <&ccu RST_BUS_UART5>; ++ dmas = <&dma 19>, <&dma 19>; ++ dma-names = "rx", "tx"; ++ fifo-size = <256>; ++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@2502000 { ++ compatible = "allwinner,sun20i-d1-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x2502000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_I2C0>; ++ resets = <&ccu RST_BUS_I2C0>; ++ dmas = <&dma 43>, <&dma 43>; ++ dma-names = "rx", "tx"; ++ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@2502400 { ++ compatible = "allwinner,sun20i-d1-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x2502400 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_I2C1>; ++ resets = <&ccu RST_BUS_I2C1>; ++ dmas = <&dma 44>, <&dma 44>; ++ dma-names = "rx", "tx"; ++ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@2502800 { ++ compatible = "allwinner,sun20i-d1-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x2502800 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_I2C2>; ++ resets = <&ccu RST_BUS_I2C2>; ++ dmas = <&dma 45>, <&dma 45>; ++ dma-names = "rx", "tx"; ++ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@2502c00 { ++ compatible = "allwinner,sun20i-d1-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x2502c00 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_I2C3>; ++ resets = <&ccu RST_BUS_I2C3>; ++ dmas = <&dma 46>, <&dma 46>; ++ dma-names = "rx", "tx"; ++ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ syscon: syscon@3000000 { ++ compatible = "allwinner,sun20i-d1-system-control"; ++ reg = <0x3000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ regulators { ++ reg_ldoa: ldoa { ++ regulator-name = "ldoa"; ++ }; ++ ++ reg_ldob: ldob { ++ regulator-name = "ldob"; ++ }; ++ }; ++ ++ sram@400000 { ++ compatible = "mmio-sram"; ++ reg = <0x400000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x400000 0x20000>; ++ ++ /* ++ * This can be further divided into DSP IRAM, ++ * DSP DRAM0, and DSP DRAM1, but the mapping ++ * of all three is controlled by a single bit. ++ */ ++ dsp_sram: sram-section@0 { ++ compatible = "allwinner,sun20i-d1-dsp-sram"; ++ reg = <0 0x20000>; ++ }; ++ }; ++ ++ // FIXME: Address is not verified. It is copied from A64/H6. ++ sram@1d00000 { ++ compatible = "mmio-sram"; ++ reg = <0x1d00000 0x40000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x1d00000 0x40000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun20i-d1-sram-c1", ++ "allwinner,sun4i-a10-sram-c1"; ++ reg = <0 0x40000>; ++ }; ++ }; ++ }; ++ ++ dma: dma-controller@3002000 { ++ compatible = "allwinner,sun20i-d1-dma"; ++ reg = <0x3002000 0x1000>; ++ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; ++ clock-names = "bus", "mbus"; ++ resets = <&ccu RST_BUS_DMA>; ++ #dma-cells = <1>; ++ dma-channels = <16>; ++ dma-requests = <48>; ++ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>, ++ <142 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ msgbox: mailbox@3003000 { ++ compatible = "allwinner,sun20i-d1-msgbox"; ++ reg = <0x3003000 0x1000>; ++ clocks = <&ccu CLK_BUS_MSGBOX0>; ++ resets = <&ccu RST_BUS_MSGBOX0>; ++ interrupts = <101 IRQ_TYPE_LEVEL_HIGH>, ++ <102 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; ++ #mbox-cells = <2>; ++ }; ++ ++ hwspinlock: hwlock@3005000 { ++ compatible = "allwinner,sun20i-d1-hwspinlock", ++ "allwinner,sun6i-a31-hwspinlock"; ++ reg = <0x3005000 0x1000>; ++ clocks = <&ccu CLK_BUS_SPINLOCK>; ++ resets = <&ccu RST_BUS_SPINLOCK>; ++ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ sid: efuse@3006000 { ++ compatible = "allwinner,sun20i-d1-sid", ++ "allwinner,sun50i-a64-sid"; ++ reg = <0x3006000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu_speed_grade: cpu-speed-grade@0 { ++ reg = <0x0 0x2>; ++ }; ++ ++ ths_calib: ths-calib@14 { ++ reg = <0x14 0x4>; ++ }; ++ }; ++ ++ // TODO: write a binding and driver. ++ hstimer: timer@3008000 { ++ compatible = "allwinner,sun20i-d1-hstimer", ++ "allwinner,sun50i-h6-hstimer"; ++ reg = <0x3008000 0x1000>; ++ clocks = <&ccu CLK_BUS_HSTIMER>; ++ resets = <&ccu RST_BUS_HSTIMER>; ++ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>, ++ <72 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ crypto: crypto@3040000 { ++ compatible = "allwinner,sun20i-d1-crypto"; ++ reg = <0x3040000 0x800>; ++ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; ++ clock-names = "bus", "mod", "ram"; ++ resets = <&ccu RST_BUS_CE>; ++ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ // TODO: write a binding and driver. ++ mbus: dram-controller@3102000 { ++ compatible = "allwinner,sun20i-d1-mbus"; ++ reg = <0x3102000 0x200000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&ccu CLK_BUS_DRAM>, ++ <&ccu CLK_DRAM>, ++ <&ccu CLK_MBUS>; ++ clock-names = "bus", "dram", "mbus"; ++ dma-ranges = <0 0x40000000 0x80000000>; ++ #interconnect-cells = <1>; ++ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ mmc0: mmc@4020000 { ++ compatible = "allwinner,sun20i-d1-mmc"; ++ reg = <0x4020000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC0>; ++ reset-names = "ahb"; ++ cap-sd-highspeed; ++ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; ++ max-frequency = <150000000>; ++ no-mmc; ++ status = "disabled"; ++ }; ++ ++ mmc1: mmc@4021000 { ++ compatible = "allwinner,sun20i-d1-mmc"; ++ reg = <0x4021000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC1>; ++ reset-names = "ahb"; ++ cap-sd-highspeed; ++ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; ++ max-frequency = <150000000>; ++ no-mmc; ++ status = "disabled"; ++ }; ++ ++ mmc2: mmc@4022000 { ++ compatible = "allwinner,sun20i-d1-emmc"; ++ reg = <0x4022000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC2>; ++ reset-names = "ahb"; ++ cap-mmc-highspeed; ++ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; ++ max-frequency = <150000000>; ++ mmc-ddr-1_8v; ++ mmc-ddr-3_3v; ++ no-sd; ++ no-sdio; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@4025000 { ++ compatible = "allwinner,sun20i-d1-spi", ++ "allwinner,sun50i-r329-spi"; ++ reg = <0x4025000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; ++ clock-names = "ahb", "mod"; ++ resets = <&ccu RST_BUS_SPI0>; ++ dmas = <&dma 22>, <&dma 22>; ++ dma-names = "rx", "tx"; ++ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; ++ num-cs = <1>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@4026000 { ++ compatible = "allwinner,sun20i-d1-spi-dbi", ++ "allwinner,sun50i-r329-spi-dbi", ++ "allwinner,sun50i-r329-spi"; ++ reg = <0x4026000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; ++ clock-names = "ahb", "mod"; ++ resets = <&ccu RST_BUS_SPI1>; ++ dmas = <&dma 23>, <&dma 23>; ++ dma-names = "rx", "tx"; ++ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; ++ num-cs = <1>; ++ status = "disabled"; ++ }; ++ ++ usb_otg: usb@4100000 { ++ compatible = "allwinner,sun20i-d1-musb", ++ "allwinner,sun8i-a33-musb"; ++ reg = <0x4100000 0x400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ dmas = <&dma 30>, <&dma 30>, ++ <&dma 31>, <&dma 31>, ++ <&dma 32>, <&dma 32>, ++ <&dma 33>, <&dma 33>, ++ <&dma 34>, <&dma 34>; ++ dma-names = "ep1_rx", "ep1_tx", ++ "ep2_rx", "ep2_tx", ++ "ep3_rx", "ep3_tx", ++ "ep4_rx", "ep4_tx", ++ "ep5_rx", "ep5_tx"; ++ extcon = <&usbphy 0>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usbphy: phy@4100400 { ++ compatible = "allwinner,sun20i-d1-usb-phy"; ++ reg = <0x4100400 0x100>, ++ <0x4101800 0x100>, ++ <0x4200800 0x100>; ++ reg-names = "phy_ctrl", ++ "pmu0", ++ "pmu1"; ++ clocks = <&osc24M>, ++ <&osc24M>; ++ clock-names = "usb0_phy", ++ "usb1_phy"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY1>; ++ reset-names = "usb0_reset", ++ "usb1_reset"; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ ehci0: usb@4101000 { ++ compatible = "allwinner,sun20i-d1-ehci", ++ "generic-ehci"; ++ reg = <0x4101000 0x100>; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_BUS_EHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>, ++ <&ccu RST_BUS_EHCI0>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@4101400 { ++ compatible = "allwinner,sun20i-d1-ohci", ++ "generic-ohci"; ++ reg = <0x4101400 0x100>; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci1: usb@4200000 { ++ compatible = "allwinner,sun20i-d1-ehci", ++ "generic-ehci"; ++ reg = <0x4200000 0x100>; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_BUS_EHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>, ++ <&ccu RST_BUS_EHCI1>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci1: usb@4200400 { ++ compatible = "allwinner,sun20i-d1-ohci", ++ "generic-ohci"; ++ reg = <0x4200400 0x100>; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>; ++ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ emac: ethernet@4500000 { ++ compatible = "allwinner,sun20i-d1-emac", ++ "allwinner,sun50i-a64-emac"; ++ reg = <0x4500000 0x10000>; ++ clocks = <&ccu CLK_BUS_EMAC>; ++ clock-names = "stmmaceth"; ++ resets = <&ccu RST_BUS_EMAC>; ++ reset-names = "stmmaceth"; ++ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq"; ++ syscon = <&syscon>; ++ status = "disabled"; ++ ++ mdio: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ ++ de: display-engine@5000000 { ++ reg = <0x5000000 0x400000>; ++ interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; ++ interconnects = <&mbus 11>; ++ interconnect-names = "dma-mem"; ++ iommus = <&iommu 2>; ++ }; ++ ++ deinterlace: deinterlace@5400000 { ++ reg = <0x5400000 0x10000>; ++ interconnects = <&mbus 10>; ++ interconnect-names = "dma-mem"; ++ interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; ++ iommus = <&iommu 4>; ++ }; ++ ++ g2d: g2d@5410000 { ++ reg = <0x5410000 0x40000>; ++ interconnects = <&mbus 9>; ++ interconnect-names = "dma-mem"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ iommus = <&iommu 3>; ++ }; ++ ++ dsi: dsi@5450000 { ++ reg = <0x5450000 0x2000>; ++ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ tcon_top: tcon-top@5460000 { ++ reg = <0x5460000 0x1000>; ++ }; ++ ++ tcon_lcd: lcd-controller@5461000 { ++ reg = <0x5461000 0x1000>; ++ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ tcon_tv: lcd-controller@5470000 { ++ reg = <0x5470000 0x1000>; ++ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ hdmi: hdmi@5500000 { ++ reg = <0x5500000 0x100000>; ++ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ tve_top: video-codec@5600000 { ++ reg = <0x5600000 0x4000>; ++ }; ++ ++ tve0: video-codec@5604000 { ++ reg = <0x5604000 0x4000>; ++ interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ csi: csi@5800000 { ++ reg = <0x5800000 0x400000>; ++ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>, ++ <112 IRQ_TYPE_LEVEL_HIGH>, ++ <116 IRQ_TYPE_LEVEL_HIGH>, ++ <122 IRQ_TYPE_LEVEL_HIGH>; ++ interconnects = <&mbus 7>; ++ interconnect-names = "dma-mem"; ++ iommus = <&iommu 1>; ++ }; ++ ++ tvd_top: video-codec@5c00000 { ++ reg = <0x5c00000 0x1000>; ++ interconnects = <&mbus 6>; ++ interconnect-names = "dma-mem"; ++ }; ++ ++ tvd0: video-codec@5c01000 { ++ reg = <0x5c01000 0x1000>; ++ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ intc: interrupt-controller@6010000 { ++ compatible = "allwinner,sun20i-d1-intc"; ++ reg = <0x6010000 0x100>; ++ #address-cells = <0>; ++ clocks = <&ccu CLK_BUS_RISCV_CFG>; ++ resets = <&ccu RST_BUS_RISCV_CFG>; ++ interrupt-parent = <&plic>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ riscv_wdt: watchdog@6011000 { ++ compatible = "allwinner,sun20i-d1-wdt"; ++ reg = <0x6011000 0x20>; ++ clocks = <&osc24M>; ++ interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ riscv_msgbox: mailbox@601f000 { ++ compatible = "allwinner,sun20i-d1-msgbox"; ++ reg = <0x601f000 0x1000>; ++ clocks = <&ccu CLK_BUS_MSGBOX2>; ++ resets = <&ccu RST_BUS_MSGBOX2>; ++ interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, ++ <145 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; ++ #mbox-cells = <2>; ++ }; ++ ++ r_ccu: clock-controller@7010000 { ++ compatible = "allwinner,sun20i-d1-r-ccu"; ++ reg = <0x7010000 0x400>; ++ clocks = <&osc24M>, ++ <&rtc CLK_OSC32K>, ++ <&rtc CLK_IOSC>, ++ <&ccu CLK_PLL_PERIPH0_DIV3>; ++ clock-names = "hosc", "losc", "iosc", "pll-periph"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ r_ir_rx: ir@7040000 { ++ compatible = "allwinner,sun20i-d1-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x7040000 0x400>; ++ clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_BUS_R_IR_RX>; ++ interrupts = <167 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ // TODO: audit all blocks for hidden use of CLK_DCXO24M ++ rtc: rtc@7090000 { ++ compatible = "allwinner,sun20i-d1-rtc", ++ "allwinner,sun50i-r329-rtc"; ++ reg = <0x7090000 0x400>; ++ clocks = <&r_ccu CLK_R_AHB>, ++ <&r_ccu CLK_BUS_R_RTC>, ++ <&osc24M>; ++ clock-names = "ahb", "bus", "hosc"; ++ #clock-cells = <1>; ++ interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ plic: interrupt-controller@10000000 { ++ compatible = "allwinner,sun20i-d1-plic", ++ "sifive,plic-1.0.0"; ++ reg = <0x10000000 0x4000000>; ++ #address-cells = <0>; ++ interrupts-extended = <&cpu0_intc 11>, ++ <&cpu0_intc 9>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ riscv,ndev = <176>; ++ }; ++ ++ clint: clint@14000000 { ++ compatible = "allwinner,sun20i-d1-clint", ++ "sifive,clint0"; ++ reg = <0x14000000 0xc000>; ++ reg-io-width = <4>; ++ interrupts-extended = <&cpu0_intc 3>, ++ <&cpu0_intc 7>; ++ }; ++ }; ++}; +diff -ruN u-boot-2021.10/arch/riscv/dts/sun20i-d1-nezha.dts u-boot/arch/riscv/dts/sun20i-d1-nezha.dts +--- u-boot-2021.10/arch/riscv/dts/sun20i-d1-nezha.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/riscv/dts/sun20i-d1-nezha.dts 2021-11-01 17:10:13.899612357 +0100 +@@ -0,0 +1,373 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++// Copyright (C) 2021 Samuel Holland ++ ++/dts-v1/; ++ ++#include "sun20i-d1.dtsi" ++ ++#include ++#include ++#include ++#include ++ ++/ { ++ model = "Allwinner D1 NeZha"; ++ compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; ++ ++ aliases { ++ ethernet0 = &emac; ++ mmc0 = &mmc0; ++ mmc1 = &mmc1; ++ mmc2 = &mmc2; ++ serial0 = &uart0; ++ spi0 = &spi0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ hdmi_connector: connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ // FIXME: remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ reg_usbvbus: usbvbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usbvbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ ++ enable-active-high; ++ vin-supply = <®_vcc>; ++ }; ++ ++ reg_vcc: vcc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_vcc_3v3: vcc-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc>; ++ }; ++ ++ reg_vdd_cpu: vdd-cpu { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm 0 50000 0>; ++ pwm-supply = <®_vcc>; ++ regulator-name = "vdd-cpu"; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <1160000>; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ ++ }; ++}; ++ ++&codec { ++ allwinner,routing = "Headphone Jack", "HPOUTL", ++ "Headphone Jack", "HPOUTR", ++ "LINEINL", "HPOUTL", ++ "LINEINR", "HPOUTR", ++ "MICIN3", "Headset Microphone", ++ "Headset Microphone", "HBIAS"; ++ allwinner,widgets = "Microphone", "Headset Microphone", ++ "Headphone", "Headphone Jack"; ++ avcc-supply = <®_aldo>; ++ hpvcc-supply = <®_hpldo>; ++ vdd33-supply = <®_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpu>; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-0 = <&rgmii_pe_pins>; ++ pinctrl-names = "default"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <®_vcc_3v3>; ++ snps,reset-gpio = <&gpio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ ++ status = "okay"; ++}; ++ ++&gpio { ++ vcc-pa-supply = <®_vcc_3v3>; ++ vcc-pb-supply = <®_vcc_3v3>; ++ vcc-pc-supply = <®_vcc_3v3>; ++ vcc-pd-supply = <®_vcc_3v3>; ++ vcc-pe-supply = <®_vcc_3v3>; ++ vcc-pf-supply = <®_vcc_3v3>; ++ vcc-pg-supply = <®_vcc_3v3>; ++ ++ i2s2_pb_pins: i2s2-pb-pins { ++ pins = "PB5", "PB6", "PB7"; ++ function = "i2s2"; ++ }; ++ ++ i2s2_pb3_din_pin: i2s2-pb3-din-pin { ++ pins = "PB3"; ++ function = "i2s2_din"; ++ }; ++ ++ i2s2_pb4_dout_pin: i2s2-pb4-dout-pin { ++ pins = "PB4"; ++ function = "i2s2_dout"; ++ }; ++ ++ ledc_pc0_pin: ledc-pc0-pin { ++ pins = "PC0"; ++ function = "ledc"; ++ }; ++ ++ pwm0_pd16_pin: pwm0-pd16-pin { ++ pins = "PD16"; ++ function = "pwm"; ++ }; ++ ++ pwm2_pd18_pin: pwm2-pd18-pin { ++ pins = "PD18"; ++ function = "pwm"; ++ }; ++ ++ pwm7_pd22_pin: pwm7-pd22-pin { ++ pins = "PD22"; ++ function = "pwm"; ++ }; ++ ++ spdif_pd22_pin: spdif-pd22-pin { ++ pins = "PD22"; ++ function = "spdif"; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-0 = <&i2c0_pb10_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-0 = <&i2c2_pb0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ pcf8574a: gpio@38 { ++ compatible = "nxp,pcf8574a"; ++ #address-cells = <0>; ++ reg = <0x38>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupts-extended = <&gpio 1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++}; ++ ++&i2s2 { ++ pinctrl-0 = <&i2s2_pb_pins>, <&i2s2_pb3_din_pin>, <&i2s2_pb4_dout_pin>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&ledc { ++ pinctrl-0 = <&ledc_pc0_pin>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ led@0 { ++ reg = <0x0>; ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ }; ++}; ++ ++&lradc { ++ vref-supply = <®_aldo>; ++ wakeup-source; ++ status = "okay"; ++ ++ button-160 { ++ label = "OK"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <160000>; ++ }; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ bus-width = <4>; ++ cd-gpios = <&gpio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ disable-wp; ++ vmmc-supply = <®_vcc_3v3>; ++ vqmmc-supply = <®_vcc_3v3>; ++ pinctrl-0 = <&mmc0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ bus-width = <4>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ non-removable; ++ vmmc-supply = <®_vcc_3v3>; ++ vqmmc-supply = <®_vcc_3v3>; ++ pinctrl-0 = <&mmc1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ xr829: wifi@1 { ++ reg = <1>; ++ host-wake-gpios = <&gpio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ ++ }; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pwm { ++ pinctrl-0 = <&pwm0_pd16_pin>, <&pwm2_pd18_pin>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++®_aldo { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vdd33-supply = <®_vcc_3v3>; ++}; ++ ++®_hpldo { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ hpldoin-supply = <®_vcc_3v3>; ++}; ++ ++®_ldoa { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ldo-in-supply = <®_vcc_3v3>; ++}; ++ ++&spdif { ++ pinctrl-0 = <&spdif_pd22_pin>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-0 = <&spi0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "boot0"; ++ reg = <0x00000000 0x00100000>; ++ }; ++ ++ partition@100000 { ++ label = "uboot"; ++ reg = <0x00100000 0x00300000>; ++ }; ++ ++ partition@400000 { ++ label = "secure_storage"; ++ reg = <0x00400000 0x00100000>; ++ }; ++ ++ partition@500000 { ++ label = "sys"; ++ reg = <0x00500000 0x0fb00000>; ++ }; ++ }; ++ }; ++}; ++ ++&spi1 { ++ pinctrl-0 = <&spi1_pd_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&ths { ++ vref-supply = <®_aldo>; ++}; ++ ++&uart0 { ++ pinctrl-0 = <&uart0_pb8_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "xradio,xr829-bt"; ++ device-wakeup-gpios = <&gpio 6 16 GPIO_ACTIVE_LOW>; /* PG16 */ ++ interrupts-extended = <&gpio 6 17 IRQ_TYPE_LEVEL_LOW>; /* PG17 */ ++ interrupt-names = "wakeup"; ++ reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ ++ }; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&gpio 3 21 GPIO_ACTIVE_LOW>; /* PD21 */ ++ usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ ++ usb0_vbus-supply = <®_usbvbus>; ++ usb1_vbus-supply = <®_vcc>; ++ status = "okay"; ++}; +diff -ruN u-boot-2021.10/arch/riscv/dts/sun20i-d1-nezha-u-boot.dtsi u-boot/arch/riscv/dts/sun20i-d1-nezha-u-boot.dtsi +--- u-boot-2021.10/arch/riscv/dts/sun20i-d1-nezha-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/riscv/dts/sun20i-d1-nezha-u-boot.dtsi 2021-11-01 17:10:13.899612357 +0100 +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ ++#include "binman.dtsi" ++ ++/ { ++ // FIXME: this is temporary. ++ memory { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; /* 512 MB */ ++ }; ++}; +diff -ruN u-boot-2021.10/arch/riscv/include/asm/bitops.h u-boot/arch/riscv/include/asm/bitops.h +--- u-boot-2021.10/arch/riscv/include/asm/bitops.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/include/asm/bitops.h 2021-11-01 17:10:13.902945508 +0100 +@@ -78,6 +78,7 @@ + return retval; + } + ++#define test_and_clear_bit __test_and_clear_bit + static inline int __test_and_clear_bit(int nr, void *addr) + { + int mask, retval; +diff -ruN u-boot-2021.10/arch/riscv/include/asm/io.h u-boot/arch/riscv/include/asm/io.h +--- u-boot-2021.10/arch/riscv/include/asm/io.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/include/asm/io.h 2021-11-01 17:10:13.902945508 +0100 +@@ -110,6 +110,7 @@ + return val; + } + ++#define readl_relaxed readl + static inline u32 readl(const volatile void __iomem *addr) + { + u32 val; +@@ -242,6 +243,7 @@ + #define insb(p, d, l) readsb(__io(p), d, l) + #define insw(p, d, l) readsw(__io(p), d, l) + #define insl(p, d, l) readsl(__io(p), d, l) ++#endif + + static inline void readsb(unsigned int *addr, void *data, int bytelen) + { +@@ -332,7 +334,6 @@ + longlen--; + } + } +-#endif + + #define outb_p(val, port) outb((val), (port)) + #define outw_p(val, port) outw((val), (port)) +diff -ruN u-boot-2021.10/arch/riscv/include/asm/processor.h u-boot/arch/riscv/include/asm/processor.h +--- u-boot-2021.10/arch/riscv/include/asm/processor.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/include/asm/processor.h 2021-11-01 17:10:13.902945508 +0100 +@@ -23,4 +23,6 @@ + * no one uses the macros defined in this head file. + **************************************************************/ + ++#define cpu_relax() barrier() ++ + #endif /* __ASM_RISCV_PROCESSOR_H */ +diff -ruN u-boot-2021.10/arch/riscv/include/asm/sbi.h u-boot/arch/riscv/include/asm/sbi.h +--- u-boot-2021.10/arch/riscv/include/asm/sbi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/include/asm/sbi.h 2021-11-01 17:10:13.902945508 +0100 +@@ -12,7 +12,6 @@ + #include + + enum sbi_ext_id { +-#ifdef CONFIG_SBI_V01 + SBI_EXT_0_1_SET_TIMER = 0x0, + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, +@@ -22,11 +21,12 @@ + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, + SBI_EXT_0_1_SHUTDOWN = 0x8, +-#endif + SBI_EXT_BASE = 0x10, + SBI_EXT_TIME = 0x54494D45, + SBI_EXT_IPI = 0x735049, + SBI_EXT_RFENCE = 0x52464E43, ++ SBI_EXT_HSM = 0x48534D, ++ SBI_EXT_SRST = 0x53525354, + }; + + enum sbi_ext_base_fid { +@@ -51,6 +51,41 @@ + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, ++ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, ++ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, ++ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, ++ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, ++}; ++ ++enum sbi_ext_hsm_fid { ++ SBI_EXT_HSM_HART_START = 0, ++ SBI_EXT_HSM_HART_STOP, ++ SBI_EXT_HSM_HART_STATUS, ++ SBI_EXT_HSM_HART_SUSPEND, ++}; ++ ++enum sbi_hsm_hart_status { ++ SBI_HSM_HART_STATUS_STARTED = 0, ++ SBI_HSM_HART_STATUS_STOPPED, ++ SBI_HSM_HART_STATUS_START_PENDING, ++ SBI_HSM_HART_STATUS_STOP_PENDING, ++ SBI_HSM_HART_STATUS_SUSPEND_PENDING, ++ SBI_HSM_HART_STATUS_RESUME_PENDING, ++}; ++ ++enum sbi_ext_srst_fid { ++ SBI_EXT_SRST_RESET = 0, ++}; ++ ++enum sbi_srst_reset_type { ++ SBI_SRST_RESET_TYPE_SHUTDOWN = 0, ++ SBI_SRST_RESET_TYPE_COLD_REBOOT, ++ SBI_SRST_RESET_TYPE_WARM_REBOOT, ++}; ++ ++enum sbi_srst_reset_reason { ++ SBI_SRST_RESET_REASON_NONE = 0, ++ SBI_SRST_RESET_REASON_SYS_FAILURE, + }; + + #ifdef CONFIG_SBI_V01 +@@ -118,5 +153,6 @@ + long sbi_get_spec_version(void); + int sbi_get_impl_id(void); + int sbi_probe_extension(int ext); ++void sbi_srst_reset(unsigned long type, unsigned long reason); + + #endif +diff -ruN u-boot-2021.10/arch/riscv/Kconfig u-boot/arch/riscv/Kconfig +--- u-boot-2021.10/arch/riscv/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/Kconfig 2021-11-01 17:10:13.896279206 +0100 +@@ -14,6 +14,9 @@ + config TARGET_MICROCHIP_ICICLE + bool "Support Microchip PolarFire-SoC Icicle Board" + ++config TARGET_OPENPITON_RISCV64 ++ bool "Support RISC-V cores on OpenPiton SoC" ++ + config TARGET_QEMU_VIRT + bool "Support QEMU Virt Board" + +@@ -22,18 +25,20 @@ + + config TARGET_SIFIVE_UNMATCHED + bool "Support SiFive Unmatched Board" ++ select SYS_CACHE_SHIFT_6 + + config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" ++ select SYS_CACHE_SHIFT_6 + +-config TARGET_OPENPITON_RISCV64 +- bool "Support RISC-V cores on OpenPiton SoC" ++config TARGET_SUNXI ++ bool "Support Allwinner sunxi SoCs with RISC-V cores" ++ select SYS_CACHE_SHIFT_6 + + endchoice + + config SYS_ICACHE_OFF + bool "Do not enable icache" +- default n + help + Do not enable instruction cache in U-Boot. + +@@ -46,7 +51,6 @@ + + config SYS_DCACHE_OFF + bool "Do not enable dcache" +- default n + help + Do not enable data cache in U-Boot. + +@@ -61,9 +65,9 @@ + source "board/AndesTech/ax25-ae350/Kconfig" + source "board/emulation/qemu-riscv/Kconfig" + source "board/microchip/mpfs_icicle/Kconfig" ++source "board/openpiton/riscv64/Kconfig" + source "board/sifive/unleashed/Kconfig" + source "board/sifive/unmatched/Kconfig" +-source "board/openpiton/riscv64/Kconfig" + source "board/sipeed/maix/Kconfig" + + # platform-specific options below +diff -ruN u-boot-2021.10/arch/riscv/lib/bootm.c u-boot/arch/riscv/lib/bootm.c +--- u-boot-2021.10/arch/riscv/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/lib/bootm.c 2021-11-01 17:10:13.902945508 +0100 +@@ -135,3 +135,16 @@ + { + return do_bootm_linux(flag, argc, argv, images); + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mv %0, sp" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/riscv/lib/cache.c u-boot/arch/riscv/lib/cache.c +--- u-boot-2021.10/arch/riscv/lib/cache.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/lib/cache.c 2021-11-01 17:10:13.902945508 +0100 +@@ -20,7 +20,7 @@ + { + } + +-void invalidate_icache_range(unsigned long start, unsigned long end) ++__weak void invalidate_icache_range(unsigned long start, unsigned long end) + { + /* + * RISC-V does not have an instruction for invalidating parts of the +diff -ruN u-boot-2021.10/arch/riscv/lib/fdt_fixup.c u-boot/arch/riscv/lib/fdt_fixup.c +--- u-boot-2021.10/arch/riscv/lib/fdt_fixup.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/lib/fdt_fixup.c 2021-11-01 17:10:13.902945508 +0100 +@@ -31,7 +31,6 @@ + fdt_addr_t addr; + fdt_size_t size; + int offset, node, err, rmem_offset; +- bool nomap = true; + char basename[32] = {0}; + int bname_len; + int max_len = sizeof(basename); +@@ -81,9 +80,7 @@ + log_err("failed to add reserved memory: %d\n", err); + return err; + } +- if (!fdt_getprop(src, node, "no-map", NULL)) +- nomap = false; +- if (nomap) { ++ if (fdt_getprop(src, node, "no-map", NULL)) { + rmem_offset = fdt_node_offset_by_phandle(dst, phandle); + fdt_setprop_empty(dst, rmem_offset, "no-map"); + } +diff -ruN u-boot-2021.10/arch/riscv/lib/sbi.c u-boot/arch/riscv/lib/sbi.c +--- u-boot-2021.10/arch/riscv/lib/sbi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/riscv/lib/sbi.c 2021-11-01 17:10:13.902945508 +0100 +@@ -108,6 +108,18 @@ + return -ENOTSUPP; + } + ++/** ++ * sbi_srst_reset() - invoke system reset extension ++ * ++ * @type: type of reset ++ * @reason: reason for reset ++ */ ++void sbi_srst_reset(unsigned long type, unsigned long reason) ++{ ++ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, ++ 0, 0, 0, 0); ++} ++ + #ifdef CONFIG_SBI_V01 + + /** +diff -ruN u-boot-2021.10/arch/sandbox/cpu/os.c u-boot/arch/sandbox/cpu/os.c +--- u-boot-2021.10/arch/sandbox/cpu/os.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/cpu/os.c 2021-11-01 17:10:13.902945508 +0100 +@@ -133,6 +133,19 @@ + return 0; + } + ++int os_filesize(int fd) ++{ ++ off_t size; ++ ++ size = os_lseek(fd, 0, OS_SEEK_END); ++ if (size < 0) ++ return -errno; ++ if (os_lseek(fd, 0, OS_SEEK_SET) < 0) ++ return -errno; ++ ++ return size; ++} ++ + int os_read_file(const char *fname, void **bufp, int *sizep) + { + off_t size; +@@ -144,15 +157,12 @@ + printf("Cannot open file '%s'\n", fname); + goto err; + } +- size = os_lseek(fd, 0, OS_SEEK_END); ++ size = os_filesize(fd); + if (size < 0) { +- printf("Cannot seek to end of file '%s'\n", fname); +- goto err; +- } +- if (os_lseek(fd, 0, OS_SEEK_SET) < 0) { +- printf("Cannot seek to start of file '%s'\n", fname); ++ printf("Cannot get file size of '%s'\n", fname); + goto err; + } ++ + *bufp = os_malloc(size); + if (!*bufp) { + printf("Not enough memory to read file '%s'\n", fname); +@@ -172,6 +182,35 @@ + return ret; + } + ++int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep) ++{ ++ void *ptr; ++ int size; ++ int ifd; ++ ++ ifd = os_open(pathname, os_flags); ++ if (ifd < 0) { ++ printf("Cannot open file '%s'\n", pathname); ++ return -EIO; ++ } ++ size = os_filesize(ifd); ++ if (size < 0) { ++ printf("Cannot get file size of '%s'\n", pathname); ++ return -EIO; ++ } ++ ++ ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0); ++ if (ptr == MAP_FAILED) { ++ printf("Can't map file '%s': %s\n", pathname, strerror(errno)); ++ return -EPERM; ++ } ++ ++ *bufp = ptr; ++ *sizep = size; ++ ++ return 0; ++} ++ + /* Restore tty state when we exit */ + static struct termios orig_term; + static bool term_setup; +@@ -690,7 +729,6 @@ + continue; + } + } else if (!strcmp(arg, "--rm_memory")) { +- ap++; + continue; + } + argv[argc++] = arg; +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/sandbox/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/sandbox/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/leds/common.h u-boot/arch/sandbox/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/sandbox/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/sandbox/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/sandbox/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/sandbox/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/sandbox/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/sandbox/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/sandbox/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/sandbox/dts/overlay0.dts u-boot/arch/sandbox/dts/overlay0.dts +--- u-boot-2021.10/arch/sandbox/dts/overlay0.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/overlay0.dts 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Overlay test file ++ */ ++ + /dts-v1/; + /plugin/; + +diff -ruN u-boot-2021.10/arch/sandbox/dts/overlay1.dts u-boot/arch/sandbox/dts/overlay1.dts +--- u-boot-2021.10/arch/sandbox/dts/overlay1.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/overlay1.dts 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Overlay test file ++ */ ++ + /dts-v1/; + /plugin/; + +diff -ruN u-boot-2021.10/arch/sandbox/dts/sandbox64.dts u-boot/arch/sandbox/dts/sandbox64.dts +--- u-boot-2021.10/arch/sandbox/dts/sandbox64.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/sandbox64.dts 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Main sandbox64 devicetree ++ */ + /dts-v1/; + + #include +diff -ruN u-boot-2021.10/arch/sandbox/dts/sandbox.dts u-boot/arch/sandbox/dts/sandbox.dts +--- u-boot-2021.10/arch/sandbox/dts/sandbox.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/sandbox.dts 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Main sandbox devicetree ++ */ ++ + /dts-v1/; + + #include +diff -ruN u-boot-2021.10/arch/sandbox/dts/sandbox.dtsi u-boot/arch/sandbox/dts/sandbox.dtsi +--- u-boot-2021.10/arch/sandbox/dts/sandbox.dtsi 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/sandbox.dtsi 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,4 @@ ++// SPDX-License-Identifier: GPL-2.0+ + /* + * This is the common sandbox device-tree nodes. This is shared between sandbox + * and sandbox64 builds. +@@ -65,7 +66,7 @@ + }; + + gpio_b: gpios@1 { +- u-boot,dm-pre-proper; ++ u-boot,dm-spl; + gpio-controller; + compatible = "sandbox,gpio"; + #gpio-cells = <2>; +@@ -73,6 +74,12 @@ + sandbox,gpio-count = <10>; + }; + ++ gpio-test { ++ u-boot,dm-spl; ++ compatible = "sandbox,gpio-test"; ++ test-gpios = <&gpio_b 3 0>; ++ }; ++ + hexagon { + compatible = "demo-simple"; + colour = "white"; +@@ -123,6 +130,19 @@ + #sound-dai-cells = <1>; + }; + ++ irq_sandbox: irq-sbox { ++ u-boot,dm-spl; ++ compatible = "sandbox,irq"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ irq-test { ++ u-boot,dm-spl; ++ compatible = "sandbox,irq-test"; ++ interrupts-extended = <&irq_sandbox 3 0>; ++ }; ++ + lcd { + u-boot,dm-pre-proper; + compatible = "sandbox,lcd-sdl"; +diff -ruN u-boot-2021.10/arch/sandbox/dts/test.dts u-boot/arch/sandbox/dts/test.dts +--- u-boot-2021.10/arch/sandbox/dts/test.dts 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/dts/test.dts 2021-11-01 17:10:13.906278659 +0100 +@@ -1,3 +1,12 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Devicetree file for running sandbox tests ++ * ++ * This includes lots of extra devices used by various tests. ++ * ++ * Note that SPL use the main sandbox.dts file ++ */ ++ + /dts-v1/; + + #include +@@ -53,6 +62,9 @@ + }; + + config { ++ testing-bool; ++ testing-int = <123>; ++ testing-str = "testing"; + environment { + from_fdt = "yes"; + fdt_env_path = ""; +@@ -793,6 +805,13 @@ + }; + }; + ++ gpio-wdt { ++ gpios = <&gpio_a 7 0>; ++ compatible = "linux,wdt-gpio"; ++ hw_margin_ms = <100>; ++ always-running; ++ }; ++ + mbox: mbox { + compatible = "sandbox,mbox"; + #mbox-cells = <1>; +@@ -805,19 +824,27 @@ + }; + + cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; + timebase-frequency = <2000000>; +- cpu-test1 { ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ reg = <0x1>; + timebase-frequency = <3000000>; + compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; + }; + +- cpu-test2 { ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ reg = <0x2>; + compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; + }; + +- cpu-test3 { ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ reg = <0x3>; + compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; + }; +@@ -1272,6 +1299,7 @@ + + wdt0: wdt@0 { + compatible = "sandbox,wdt"; ++ hw_margin_ms = <200>; + }; + + axi: axi@0 { +diff -ruN u-boot-2021.10/arch/sandbox/include/asm/cache.h u-boot/arch/sandbox/include/asm/cache.h +--- u-boot-2021.10/arch/sandbox/include/asm/cache.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/include/asm/cache.h 2021-11-01 17:10:13.906278659 +0100 +@@ -19,6 +19,5 @@ + #else + #define ARCH_DMA_MINALIGN 16 + #endif +-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN + + #endif /* __SANDBOX_CACHE_H__ */ +diff -ruN u-boot-2021.10/arch/sandbox/include/asm/gpio.h u-boot/arch/sandbox/include/asm/gpio.h +--- u-boot-2021.10/arch/sandbox/include/asm/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sandbox/include/asm/gpio.h 2021-11-01 17:10:13.906278659 +0100 +@@ -65,7 +65,7 @@ + * + * @param dev device to use + * @param offset GPIO offset within bank +- * @param output 0 to set as input, 1 to set as output ++ * @param output 0 to set as input, 1 to set as output + * @return -1 on error, 0 if ok + */ + int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, +diff -ruN u-boot-2021.10/arch/sandbox/include/asm/irq.h u-boot/arch/sandbox/include/asm/irq.h +--- u-boot-2021.10/arch/sandbox/include/asm/irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/arch/sandbox/include/asm/irq.h 2021-11-01 17:10:13.906278659 +0100 +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright 2021 Google LLC ++ */ ++ ++#ifndef __SANDBOX_IRQ_H ++#define __SANDBOX_IRQ_H ++ ++/** ++ * struct sandbox_irq_priv - private data for this driver ++ * ++ * @count: Counts the number calls to the read_and_clear() method ++ * @pending: true if an interrupt is pending, else false ++ */ ++struct sandbox_irq_priv { ++ int count; ++ bool pending; ++}; ++ ++#endif /* __SANDBOX_IRQ_H */ +diff -ruN u-boot-2021.10/arch/sh/lib/bootm.c u-boot/arch/sh/lib/bootm.c +--- u-boot-2021.10/arch/sh/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sh/lib/bootm.c 2021-11-01 17:10:13.909611810 +0100 +@@ -12,8 +12,11 @@ + #include + #include + #include ++#include + #include + ++DECLARE_GLOBAL_DATA_PTR; ++ + #ifdef CONFIG_SYS_DEBUG + static void hexdump(unsigned char *buf, int len) + { +@@ -111,3 +114,16 @@ + /* does not return */ + return 1; + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mov r15, %0" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/sh/lib/time.c u-boot/arch/sh/lib/time.c +--- u-boot-2021.10/arch/sh/lib/time.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/sh/lib/time.c 2021-11-01 17:10:13.909611810 +0100 +@@ -32,4 +32,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/hostbridge.c u-boot/arch/x86/cpu/apollolake/hostbridge.c +--- u-boot-2021.10/arch/x86/cpu/apollolake/hostbridge.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/hostbridge.c 2021-11-01 17:10:13.912944961 +0100 +@@ -220,7 +220,7 @@ + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge PINCTRL", ret); +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int root; + + /* Get length of PCI Express Region */ +@@ -375,7 +375,7 @@ + #endif + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_hostbridge_ids[] = { + { .compatible = "intel,apl-hostbridge" }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/Kconfig u-boot/arch/x86/cpu/apollolake/Kconfig +--- u-boot-2021.10/arch/x86/cpu/apollolake/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/Kconfig 2021-11-01 17:10:13.909611810 +0100 +@@ -12,10 +12,10 @@ + select INTEL_SOC + select INTEL_PMC + select TPL_X86_TSC_TIMER_NATIVE +- select SPL_PCH_SUPPORT +- select TPL_PCH_SUPPORT ++ select SPL_PCH ++ select TPL_PCH + select PCIEX_LENGTH_256MB +- select PCH_SUPPORT ++ select PCH + select P2SB + select SMP_AP_WORK + select INTEL_GMA_SWSMISCI +@@ -88,7 +88,7 @@ + config APL_SPI_FLASH_BOOT + bool "Support booting with SPI-flash driver instead memory-mapped SPI" + select TPL_SPI_FLASH_SUPPORT +- select TPL_SPI_SUPPORT ++ select TPL_SPI + select TPL_DM_SPI + select TPL_DM_SPI_FLASH + help +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/lpc.c u-boot/arch/x86/cpu/apollolake/lpc.c +--- u-boot-2021.10/arch/x86/cpu/apollolake/lpc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/lpc.c 2021-11-01 17:10:13.912944961 +0100 +@@ -128,7 +128,7 @@ + .inject_dsdt = southbridge_inject_dsdt, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_lpc_ids[] = { + { .compatible = "intel,apl-lpc" }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/pch.c u-boot/arch/x86/cpu/apollolake/pch.c +--- u-boot-2021.10/arch/x86/cpu/apollolake/pch.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/pch.c 2021-11-01 17:10:13.912944961 +0100 +@@ -23,7 +23,7 @@ + .set_spi_protect = apl_set_spi_protect, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_pch_ids[] = { + { .compatible = "intel,apl-pch" }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/pmc.c u-boot/arch/x86/cpu/apollolake/pmc.c +--- u-boot-2021.10/arch/x86/cpu/apollolake/pmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/pmc.c 2021-11-01 17:10:13.912944961 +0100 +@@ -107,7 +107,7 @@ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct apl_pmc_plat *plat = dev_get_plat(dev); + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + u32 base[6]; + int size; + int ret; +@@ -206,7 +206,7 @@ + .global_reset_set_enable = apl_global_reset_set_enable, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_pmc_ids[] = { + { .compatible = "intel,apl-pmc" }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/apollolake/uart.c u-boot/arch/x86/cpu/apollolake/uart.c +--- u-boot-2021.10/arch/x86/cpu/apollolake/uart.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/apollolake/uart.c 2021-11-01 17:10:13.912944961 +0100 +@@ -123,7 +123,7 @@ + return 0; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_ns16550_serial_ids[] = { + { .compatible = "intel,apl-ns16550" }, + { }, +diff -ruN u-boot-2021.10/arch/x86/cpu/coreboot/coreboot.c u-boot/arch/x86/cpu/coreboot/coreboot.c +--- u-boot-2021.10/arch/x86/cpu/coreboot/coreboot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/coreboot/coreboot.c 2021-11-01 17:10:13.912944961 +0100 +@@ -16,8 +16,7 @@ + #include + #include + #include +- +-DECLARE_GLOBAL_DATA_PTR; ++#include + + int arch_cpu_init(void) + { +@@ -65,7 +64,7 @@ + mtrr_close(&state, true); + } + +- if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { ++ if (!ofnode_conf_read_bool("u-boot,no-apm-finalize")) { + /* + * Issue SMI to coreboot to lock down ME and registers + * when allowed via device tree +diff -ruN u-boot-2021.10/arch/x86/cpu/intel_common/car2.S u-boot/arch/x86/cpu/intel_common/car2.S +--- u-boot-2021.10/arch/x86/cpu/intel_common/car2.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/intel_common/car2.S 2021-11-01 17:10:13.916278112 +0100 +@@ -88,7 +88,7 @@ + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + +- movl $0x80000008, %eax /* Address sizes leaf */ ++ movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax +diff -ruN u-boot-2021.10/arch/x86/cpu/intel_common/itss.c u-boot/arch/x86/cpu/intel_common/itss.c +--- u-boot-2021.10/arch/x86/cpu/intel_common/itss.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/intel_common/itss.c 2021-11-01 17:10:13.916278112 +0100 +@@ -213,7 +213,7 @@ + #endif + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id itss_ids[] = { + { .compatible = "intel,itss", .data = X86_IRQT_ITSS }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/intel_common/p2sb.c u-boot/arch/x86/cpu/intel_common/p2sb.c +--- u-boot-2021.10/arch/x86/cpu/intel_common/p2sb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/intel_common/p2sb.c 2021-11-01 17:10:13.916278112 +0100 +@@ -88,7 +88,7 @@ + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); + struct p2sb_plat *plat = dev_get_plat(dev); + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int ret; + u32 base[2]; + +@@ -159,16 +159,16 @@ + + static int p2sb_child_post_bind(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); +- int ret; +- u32 pid; +- +- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); +- if (ret) +- return ret; +- pplat->pid = pid; +-#endif ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); ++ int ret; ++ u32 pid; ++ ++ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); ++ if (ret) ++ return ret; ++ pplat->pid = pid; ++ } + + return 0; + } +@@ -177,7 +177,7 @@ + .set_hide = intel_p2sb_set_hide, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id p2sb_ids[] = { + { .compatible = "intel,p2sb" }, + { } +diff -ruN u-boot-2021.10/arch/x86/cpu/ivybridge/Kconfig u-boot/arch/x86/cpu/ivybridge/Kconfig +--- u-boot-2021.10/arch/x86/cpu/ivybridge/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/ivybridge/Kconfig 2021-11-01 17:10:13.916278112 +0100 +@@ -45,7 +45,6 @@ + + config ENABLE_VMX + bool "Enable VMX for virtualization" +- default n + help + Virtual Machine Extensions are provided in many x86 CPUs. These + provide various facilities for allowing a host OS to provide an +@@ -64,10 +63,6 @@ + hex + default 0xfff80000 + +-config FSP_USE_UPD +- bool +- default n +- + config FSP_BROKEN_HOB + bool + default y +diff -ruN u-boot-2021.10/arch/x86/cpu/quark/mrc.c u-boot/arch/x86/cpu/quark/mrc.c +--- u-boot-2021.10/arch/x86/cpu/quark/mrc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/cpu/quark/mrc.c 2021-11-01 17:10:13.919611263 +0100 +@@ -33,7 +33,6 @@ + */ + + #include +-#include + #include + #include + #include "mrc_util.h" +@@ -191,8 +190,7 @@ + { + ENTERFN(); + +- DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION, +- U_BOOT_DATE, U_BOOT_TIME); ++ DPF(D_INFO, "MRC Version %04x\n", MRC_VERSION); + + /* Set up the data structures used by mrc_mem_init() */ + mrc_adjust_params(mrc_params); +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/x86/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/x86/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/x86/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/x86/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/x86/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/x86/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/x86/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/leds/common.h u-boot/arch/x86/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/x86/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/x86/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/x86/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/x86/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/x86/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/x86/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/x86/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/x86/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/x86/include/asm/cache.h u-boot/arch/x86/include/asm/cache.h +--- u-boot-2021.10/arch/x86/include/asm/cache.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/include/asm/cache.h 2021-11-01 17:10:13.942943321 +0100 +@@ -7,13 +7,8 @@ + #define __X86_CACHE_H__ + + /* +- * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise +- * use 64-bytes, a safe default for x86. ++ * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment. + */ +-#ifndef CONFIG_SYS_CACHELINE_SIZE +-#define CONFIG_SYS_CACHELINE_SIZE 64 +-#endif +- + #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE + + static inline void wbinvd(void) +diff -ruN u-boot-2021.10/arch/x86/Kconfig u-boot/arch/x86/Kconfig +--- u-boot-2021.10/arch/x86/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/Kconfig 2021-11-01 17:10:13.909611810 +0100 +@@ -146,14 +146,12 @@ + + config SMM_TSEG + bool +- default n + + config SMM_TSEG_SIZE + hex + + config X86_RESET_VECTOR + bool +- default n + select BINMAN + + # The following options control where the 16-bit and 32-bit init lies +@@ -490,7 +488,7 @@ + config FSP_USE_UPD + bool + depends on FSP_VERSION1 +- default y ++ default y if !NORTHBRIDGE_INTEL_IVYBRIDGE + help + Most FSPs use UPD data region for some FSP customization. But there + are still some FSPs that might not even have UPD. For such FSPs, +@@ -536,7 +534,6 @@ + config CACHE_MRC_BIN + bool + depends on HAVE_MRC +- default n + help + Enable caching for the memory reference code binary. This uses an + MTRR (memory type range register) to turn on caching for the section +@@ -605,7 +602,6 @@ + + config SMP + bool "Enable Symmetric Multiprocessing" +- default n + help + Enable use of more than one CPU in U-Boot and the Operating System + when loaded. Each CPU will be started up and information can be +@@ -745,7 +741,6 @@ + + config GENERATE_PIRQ_TABLE + bool "Generate a PIRQ table" +- default n + help + Generate a PIRQ routing table for this board. The PIRQ routing table + is generated by U-Boot in the system memory from 0xf0000 to 0xfffff +@@ -769,7 +764,6 @@ + + config GENERATE_MP_TABLE + bool "Generate an MP (Multi-Processor) table" +- default n + help + Generate an MP (Multi-Processor) table for this board. The MP table + provides a way for the operating system to support for symmetric +@@ -778,7 +772,6 @@ + + config GENERATE_ACPI_TABLE + bool "Generate an ACPI (Advanced Configuration and Power Interface) table" +- default n + select QFW if QEMU + help + The Advanced Configuration and Power Interface (ACPI) specification +diff -ruN u-boot-2021.10/arch/x86/lib/acpi_table.c u-boot/arch/x86/lib/acpi_table.c +--- u-boot-2021.10/arch/x86/lib/acpi_table.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/lib/acpi_table.c 2021-11-01 17:10:13.949609622 +0100 +@@ -16,7 +16,6 @@ + #include + #include + #include +-#include + #include + #include + #include +diff -ruN u-boot-2021.10/arch/x86/lib/bios_asm.S u-boot/arch/x86/lib/bios_asm.S +--- u-boot-2021.10/arch/x86/lib/bios_asm.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/lib/bios_asm.S 2021-11-01 17:10:13.949609622 +0100 +@@ -22,8 +22,8 @@ + .globl __idt_handler + __idt_handler: + pushal +- movb $0, %al /* This instruction gets modified */ +- ljmp $0, $__interrupt_handler_16bit ++ movb $0, %al /* This instruction gets modified */ ++ ljmp $0, $__interrupt_handler_16bit + .globl __idt_handler_size + __idt_handler_size: + .long . - __idt_handler +diff -ruN u-boot-2021.10/arch/x86/lib/bootm.c u-boot/arch/x86/lib/bootm.c +--- u-boot-2021.10/arch/x86/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/lib/bootm.c 2021-11-01 17:10:13.949609622 +0100 +@@ -223,3 +223,21 @@ + + return boot_jump_linux(images); + } ++ ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++#if CONFIG_IS_ENABLED(X86_64) ++ ret = gd->start_addr_sp; ++#else ++ asm("mov %%esp, %0" : "=r"(ret) : ); ++#endif ++ ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/x86/lib/lpc-uclass.c u-boot/arch/x86/lib/lpc-uclass.c +--- u-boot-2021.10/arch/x86/lib/lpc-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/lib/lpc-uclass.c 2021-11-01 17:10:13.949609622 +0100 +@@ -10,7 +10,7 @@ + UCLASS_DRIVER(lpc) = { + .id = UCLASS_LPC, + .name = "lpc", +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/arch/x86/lib/tpl.c u-boot/arch/x86/lib/tpl.c +--- u-boot-2021.10/arch/x86/lib/tpl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/x86/lib/tpl.c 2021-11-01 17:10:13.952942773 +0100 +@@ -139,7 +139,7 @@ + * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does + * the auto allocation (after relocation). + */ +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id tpl_fake_pci_ids[] = { + { .compatible = "pci-x86" }, + { } +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/axg-clkc.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/axg-clkc.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/g12a-clkc.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/g12a-clkc.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/mt7622-clk.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/mt7622-clk.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/clock/sun50i-rtc.h u-boot/arch/xtensa/dts/include/dt-bindings/clock/sun50i-rtc.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/comphy/comphy_data.h u-boot/arch/xtensa/dts/include/dt-bindings/comphy/comphy_data.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/leds/common.h u-boot/arch/xtensa/dts/include/dt-bindings/leds/common.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/arch/xtensa/dts/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/mfd/atmel-flexcom.h u-boot/arch/xtensa/dts/include/dt-bindings/mfd/atmel-flexcom.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/arch/xtensa/dts/include/dt-bindings/mfd/dbx500-prcmu.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/net/ti-dp83867.h u-boot/arch/xtensa/dts/include/dt-bindings/net/ti-dp83867.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/pinctrl/dra.h u-boot/arch/xtensa/dts/include/dt-bindings/pinctrl/dra.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/pinctrl/k3.h u-boot/arch/xtensa/dts/include/dt-bindings/pinctrl/k3.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/pinctrl/omap.h u-boot/arch/xtensa/dts/include/dt-bindings/pinctrl/omap.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/arch/xtensa/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/arch/xtensa/dts/include/dt-bindings/reset/sun20i-d1-ccu.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/arch/xtensa/dts/include/dt-bindings/reset/sun20i-d1-r-ccu.h +diff -ruN u-boot-2021.10/arch/xtensa/dts/include/dt-bindings/thermal/thermal.h u-boot/arch/xtensa/dts/include/dt-bindings/thermal/thermal.h +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/core.h u-boot/arch/xtensa/include/asm/arch-dc232b/core.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc232b/core.h 2021-11-01 17:10:13.952942773 +0100 +@@ -127,8 +127,6 @@ + #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ + + +- +- + /**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ +@@ -419,4 +417,3 @@ + + + #endif /* _XTENSA_CORE_CONFIGURATION_H */ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/tie-asm.h u-boot/arch/xtensa/include/asm/arch-dc232b/tie-asm.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/tie-asm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc232b/tie-asm.h 2021-11-01 17:10:13.952942773 +0100 +@@ -26,7 +26,6 @@ + #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ + + +- + /* Macro to save all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Save area ptr (clobbered): ptr (1 byte aligned) +@@ -109,12 +108,8 @@ + .endif + .endm // xchal_ncp_load + +- +- + #define XCHAL_NCP_NUM_ATMPS 2 + +- + #define XCHAL_SA_NUM_ATMPS 2 + + #endif /*_XTENSA_CORE_TIE_ASM_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/tie.h u-boot/arch/xtensa/include/asm/arch-dc232b/tie.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc232b/tie.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc232b/tie.h 2021-11-01 17:10:13.952942773 +0100 +@@ -126,4 +126,3 @@ + #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + + #endif /*_XTENSA_CORE_TIE_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/core.h u-boot/arch/xtensa/include/asm/arch-dc233c/core.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc233c/core.h 2021-11-01 17:10:13.952942773 +0100 +@@ -149,13 +149,10 @@ + #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ + + +- +- + /**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + +- + #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + + /*---------------------------------------------------------------------- +@@ -266,28 +263,28 @@ + EXCSAVE/EPS/EPC_n, RFI n) */ + + /* Type of each interrupt: */ +-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI ++#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + + /* Masks of interrupts for each type of interrupt: */ + #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +@@ -450,4 +447,3 @@ + + + #endif /* _XTENSA_CORE_CONFIGURATION_H */ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/tie-asm.h u-boot/arch/xtensa/include/asm/arch-dc233c/tie-asm.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/tie-asm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc233c/tie-asm.h 2021-11-01 17:10:13.952942773 +0100 +@@ -31,8 +31,6 @@ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + +- +- + /* + * Macro to save all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). +@@ -164,9 +162,6 @@ + + #define XCHAL_NCP_NUM_ATMPS 1 + +- +- + #define XCHAL_SA_NUM_ATMPS 1 + + #endif /*_XTENSA_CORE_TIE_ASM_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/tie.h u-boot/arch/xtensa/include/asm/arch-dc233c/tie.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-dc233c/tie.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-dc233c/tie.h 2021-11-01 17:10:13.952942773 +0100 +@@ -126,4 +126,3 @@ + #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + + #endif /*_XTENSA_CORE_TIE_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-de212/core.h u-boot/arch/xtensa/include/asm/arch-de212/core.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-de212/core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-de212/core.h 2021-11-01 17:10:13.952942773 +0100 +@@ -89,7 +89,7 @@ + #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ + #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +-#define XCHAL_HAVE_HIFI_MINI 0 ++#define XCHAL_HAVE_HIFI_MINI 0 + + + #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +@@ -108,8 +108,8 @@ + #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ + #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ ++#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ ++#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ + #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ + #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + #define XCHAL_HAVE_PDX4 0 /* PDX4 */ +@@ -127,8 +127,8 @@ + #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ + #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ + #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ ++#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ ++#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + + /*---------------------------------------------------------------------- +@@ -206,13 +206,10 @@ + #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + +- +- + /**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + +- + #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + + /*---------------------------------------------------------------------- +@@ -351,28 +348,28 @@ + EXCSAVE/EPS/EPC_n, RFI n) */ + + /* Type of each interrupt: */ +-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI ++#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + + /* Masks of interrupts for each type of interrupt: */ + #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +@@ -569,4 +566,3 @@ + + + #endif /* _XTENSA_CORE_CONFIGURATION_H */ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-de212/tie-asm.h u-boot/arch/xtensa/include/asm/arch-de212/tie-asm.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-de212/tie-asm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-de212/tie-asm.h 2021-11-01 17:10:13.952942773 +0100 +@@ -146,4 +146,3 @@ + #define XCHAL_SA_NUM_ATMPS 1 + + #endif /*_XTENSA_CORE_TIE_ASM_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/arch-de212/tie.h u-boot/arch/xtensa/include/asm/arch-de212/tie.h +--- u-boot-2021.10/arch/xtensa/include/asm/arch-de212/tie.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/arch-de212/tie.h 2021-11-01 17:10:13.952942773 +0100 +@@ -112,4 +112,3 @@ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + + #endif /*_XTENSA_CORE_TIE_H*/ +- +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/cacheasm.h u-boot/arch/xtensa/include/asm/cacheasm.h +--- u-boot-2021.10/arch/xtensa/include/asm/cacheasm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/cacheasm.h 2021-11-01 17:10:13.952942773 +0100 +@@ -134,7 +134,6 @@ + .endm + + +- + .macro ___flush_invalidate_dcache_range ar as at + + #if XCHAL_DCACHE_SIZE +@@ -171,7 +170,6 @@ + .endm + + +- + .macro ___flush_invalidate_dcache_page ar as + + #if XCHAL_DCACHE_SIZE +diff -ruN u-boot-2021.10/arch/xtensa/include/asm/regs.h u-boot/arch/xtensa/include/asm/regs.h +--- u-boot-2021.10/arch/xtensa/include/asm/regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/include/asm/regs.h 2021-11-01 17:10:13.956275925 +0100 +@@ -91,4 +91,3 @@ + #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ + + #endif /* _XTENSA_SPECREG_H */ +- +diff -ruN u-boot-2021.10/arch/xtensa/Kconfig u-boot/arch/xtensa/Kconfig +--- u-boot-2021.10/arch/xtensa/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/Kconfig 2021-11-01 17:10:13.952942773 +0100 +@@ -18,7 +18,6 @@ + + config SYS_ICACHE_OFF + bool "Do not enable icache" +- default n + help + Do not enable instruction cache in U-Boot. + +@@ -31,7 +30,6 @@ + + config SYS_DCACHE_OFF + bool "Do not enable dcache" +- default n + help + Do not enable data cache in U-Boot. + +diff -ruN u-boot-2021.10/arch/xtensa/lib/bootm.c u-boot/arch/xtensa/lib/bootm.c +--- u-boot-2021.10/arch/xtensa/lib/bootm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/lib/bootm.c 2021-11-01 17:10:13.956275925 +0100 +@@ -197,3 +197,15 @@ + return 1; + } + ++static ulong get_sp(void) ++{ ++ ulong ret; ++ ++ asm("mov %0, a1" : "=r"(ret) : ); ++ return ret; ++} ++ ++void arch_lmb_reserve(struct lmb *lmb) ++{ ++ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); ++} +diff -ruN u-boot-2021.10/arch/xtensa/lib/Makefile u-boot/arch/xtensa/lib/Makefile +--- u-boot-2021.10/arch/xtensa/lib/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/lib/Makefile 2021-11-01 17:10:13.956275925 +0100 +@@ -5,4 +5,4 @@ + + obj-$(CONFIG_CMD_BOOTM) += bootm.o + +-obj-y += cache.o misc.o relocate.o time.o ++obj-y += cache.o misc.o relocate.o time.o +diff -ruN u-boot-2021.10/arch/xtensa/lib/relocate.c u-boot/arch/xtensa/lib/relocate.c +--- u-boot-2021.10/arch/xtensa/lib/relocate.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/arch/xtensa/lib/relocate.c 2021-11-01 17:10:13.956275925 +0100 +@@ -14,4 +14,3 @@ + memset((void *)&__bss_start, 0x00, len); + return 0; + } +- +diff -ruN u-boot-2021.10/.azure-pipelines.yml u-boot/.azure-pipelines.yml +--- u-boot-2021.10/.azure-pipelines.yml 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/.azure-pipelines.yml 2021-11-01 17:10:13.536298895 +0100 +@@ -2,7 +2,7 @@ + windows_vm: vs2017-win2016 + ubuntu_vm: ubuntu-18.04 + macos_vm: macOS-10.15 +- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021 ++ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 + # Add '-u 0' options for Azure pipelines, otherwise we get "permission + # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", + # since our $(ci_runner_image) user is not root. +@@ -195,6 +195,9 @@ + evb_ast2500: + TEST_PY_BD: "evb-ast2500" + TEST_PY_ID: "--id qemu" ++ vexpress_ca9x4: ++ TEST_PY_BD: "vexpress_ca9x4" ++ TEST_PY_ID: "--id qemu" + integratorcp_cm926ejs: + TEST_PY_BD: "integratorcp_cm926ejs" + TEST_PY_ID: "--id qemu" +@@ -254,6 +257,12 @@ + r2dplus_tulip: + TEST_PY_BD: "r2dplus" + TEST_PY_ID: "--id tulip_qemu" ++ sifive_unleashed_sdcard: ++ TEST_PY_BD: "sifive_unleashed" ++ TEST_PY_ID: "--id sdcard_qemu" ++ sifive_unleashed_spi-nor: ++ TEST_PY_BD: "sifive_unleashed" ++ TEST_PY_ID: "--id spi-nor_qemu" + xilinx_zynq_virt: + TEST_PY_BD: "xilinx_zynq_virt" + TEST_PY_ID: "--id qemu" +@@ -289,7 +298,7 @@ + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + fi +- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then ++ if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + fi +@@ -302,6 +311,18 @@ + cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi + cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi + cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi ++ # create sdcard / spi-nor images for sifive unleashed using genimage ++ if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then ++ mkdir -p root; ++ cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .; ++ cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .; ++ rm -rf tmp; ++ genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg; ++ cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/; ++ rm -rf tmp; ++ genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg; ++ cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/; ++ fi + virtualenv -p /usr/bin/python3 /tmp/venv + . /tmp/venv/bin/activate + pip install -r test/py/requirements.txt +diff -ruN u-boot-2021.10/board/advantech/imx8qm_rom7720_a1/Kconfig u-boot/board/advantech/imx8qm_rom7720_a1/Kconfig +--- u-boot-2021.10/board/advantech/imx8qm_rom7720_a1/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/advantech/imx8qm_rom7720_a1/Kconfig 2021-11-01 17:10:13.962942226 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8qm_rom7720" + ++config IMX_CONFIG ++ default "board/advantech/imx8qm_rom7720_a1/imximage.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/advantech/imx8qm_rom7720_a1/spl.c u-boot/board/advantech/imx8qm_rom7720_a1/spl.c +--- u-boot-2021.10/board/advantech/imx8qm_rom7720_a1/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/advantech/imx8qm_rom7720_a1/spl.c 2021-11-01 17:10:13.966275377 +0100 +@@ -172,7 +172,7 @@ + + void spl_board_init(void) + { +-#if defined(CONFIG_SPL_SPI_SUPPORT) ++#if defined(CONFIG_SPL_SPI) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) { + puts("Warning: failed to initialize FSPI0\n"); +@@ -185,7 +185,7 @@ + + void spl_board_prepare_for_boot(void) + { +-#if defined(CONFIG_SPL_SPI_SUPPORT) ++#if defined(CONFIG_SPL_SPI) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) { + puts("Warning: failed to turn off FSPI0\n"); +diff -ruN u-boot-2021.10/board/alliedtelesis/x530/x530.c u-boot/board/alliedtelesis/x530/x530.c +--- u-boot-2021.10/board/alliedtelesis/x530/x530.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/alliedtelesis/x530/x530.c 2021-11-01 17:10:13.966275377 +0100 +@@ -121,9 +121,8 @@ + + void arch_preboot_os(void) + { +-#ifdef CONFIG_WATCHDOG +- wdt_stop(gd->watchdog_dev); +-#endif ++ if (CONFIG_IS_ENABLED(WDT)) ++ wdt_stop_all(); + } + + static int led_7seg_init(unsigned int segments) +diff -ruN u-boot-2021.10/board/amlogic/beelink-s922x/MAINTAINERS u-boot/board/amlogic/beelink-s922x/MAINTAINERS +--- u-boot-2021.10/board/amlogic/beelink-s922x/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/amlogic/beelink-s922x/MAINTAINERS 2021-11-01 17:10:13.966275377 +0100 +@@ -5,5 +5,6 @@ + F: board/amlogic/beelink-s922x/ + F: configs/beelink-gtking_defconfig + F: configs/beelink-gtkingpro_defconfig ++F: configs/beelink-gsking-x_defconfig + F: doc/board/amlogic/beelink-gtking.rst + F: doc/board/amlogic/beelink-gtkingpro.rst +diff -ruN u-boot-2021.10/board/amlogic/jethub-j80/jethub-j80.c u-boot/board/amlogic/jethub-j80/jethub-j80.c +--- u-boot-2021.10/board/amlogic/jethub-j80/jethub-j80.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/amlogic/jethub-j80/jethub-j80.c 2021-11-01 17:10:13.966275377 +0100 +@@ -0,0 +1,67 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Vyacheslav Bocharov ++ * Author: Vyacheslav Bocharov ++ * Author: Neil Armstrong ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define EFUSE_SN_OFFSET 50 ++#define EFUSE_SN_SIZE 32 ++#define EFUSE_MAC_OFFSET 0 ++#define EFUSE_MAC_SIZE 6 ++#define EFUSE_USID_OFFSET 18 ++#define EFUSE_USID_SIZE 32 ++ ++int misc_init_r(void) ++{ ++ u8 mac_addr[EFUSE_MAC_SIZE]; ++ char serial[EFUSE_SN_SIZE]; ++ char usid[EFUSE_USID_SIZE]; ++ ssize_t len; ++ unsigned int adcval; ++ int ret; ++ ++ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { ++ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, ++ mac_addr, EFUSE_MAC_SIZE); ++ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ else ++ meson_generate_serial_ethaddr(); ++ } ++ ++ if (!env_get("serial")) { ++ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, ++ EFUSE_SN_SIZE); ++ if (len == EFUSE_SN_SIZE) ++ env_set("serial", serial); ++ } ++ ++ if (!env_get("usid")) { ++ len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid, ++ EFUSE_USID_SIZE); ++ if (len == EFUSE_USID_SIZE) ++ env_set("usid", usid); ++ } ++ ++ ret = adc_channel_single_shot("adc@8680", 0, &adcval); ++ if (adcval < 3000) ++ env_set("userbutton", "true"); ++ else ++ env_set("userbutton", "false"); ++ ++ return 0; ++} +diff -ruN u-boot-2021.10/board/amlogic/jethub-j80/MAINTAINERS u-boot/board/amlogic/jethub-j80/MAINTAINERS +--- u-boot-2021.10/board/amlogic/jethub-j80/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/amlogic/jethub-j80/MAINTAINERS 2021-11-01 17:10:13.966275377 +0100 +@@ -0,0 +1,9 @@ ++JetHome JetHub ++M: Vyacheslav Bocharov ++S: Maintained ++L: u-boot-amlogic@groups.io ++F: board/amlogic/jethub-j80/ ++F: configs/jethub_j80_defconfig ++F: configs/jethub_j100_defconfig ++F: doc/board/amlogic/jethub-j80.rst ++F: doc/board/amlogic/jethub-j100.rst +diff -ruN u-boot-2021.10/board/amlogic/jethub-j80/Makefile u-boot/board/amlogic/jethub-j80/Makefile +--- u-boot-2021.10/board/amlogic/jethub-j80/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/amlogic/jethub-j80/Makefile 2021-11-01 17:10:13.966275377 +0100 +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2021 Vyacheslav Bocharov ++# Author: Vyacheslav Bocharov ++ ++obj-y := jethub-j80.o +diff -ruN u-boot-2021.10/board/amlogic/odroid-n2/MAINTAINERS u-boot/board/amlogic/odroid-n2/MAINTAINERS +--- u-boot-2021.10/board/amlogic/odroid-n2/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/amlogic/odroid-n2/MAINTAINERS 2021-11-01 17:10:13.966275377 +0100 +@@ -5,5 +5,6 @@ + F: board/amlogic/odroid-n2/ + F: configs/odroid-n2_defconfig + F: configs/odroid-c4_defconfig ++F: configs/odroid-hc4_defconfig + F: doc/board/amlogic/odroid-n2.rst + F: doc/board/amlogic/odroid-c4.rst +diff -ruN u-boot-2021.10/board/amlogic/u200/MAINTAINERS u-boot/board/amlogic/u200/MAINTAINERS +--- u-boot-2021.10/board/amlogic/u200/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/amlogic/u200/MAINTAINERS 2021-11-01 17:10:13.969608529 +0100 +@@ -4,4 +4,7 @@ + L: u-boot-amlogic@groups.io + F: board/amlogic/u200/ + F: configs/u200_defconfig ++F: configs/bananapi-m5_defconfig ++F: configs/radxa-zero_defconfig + F: doc/board/amlogic/u200.rst ++F: doc/board/amlogic/radxa-zero.rst +diff -ruN u-boot-2021.10/board/AndesTech/ax25-ae350/ax25-ae350.c u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c +--- u-boot-2021.10/board/AndesTech/ax25-ae350/ax25-ae350.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/AndesTech/ax25-ae350/ax25-ae350.c 2021-11-01 17:10:13.956275925 +0100 +@@ -109,7 +109,7 @@ + #ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, + #endif +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, + #endif + }; +diff -ruN u-boot-2021.10/board/aristainetos/Kconfig u-boot/board/aristainetos/Kconfig +--- u-boot-2021.10/board/aristainetos/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/aristainetos/Kconfig 2021-11-01 17:10:13.969608529 +0100 +@@ -8,6 +8,9 @@ + config SYS_BOARD_VERSION + default 5 + ++config IMX_CONFIG ++ default "board/aristainetos/aristainetos2.cfg" ++ + endif + + if TARGET_ARISTAINETOS2CCSLB +@@ -20,4 +23,7 @@ + config SYS_BOARD_VERSION + default 6 + ++config IMX_CONFIG ++ default "board/aristainetos/aristainetos2.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/armadeus/opos6uldev/Kconfig u-boot/board/armadeus/opos6uldev/Kconfig +--- u-boot-2021.10/board/armadeus/opos6uldev/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/armadeus/opos6uldev/Kconfig 2021-11-01 17:10:13.969608529 +0100 +@@ -9,7 +9,4 @@ + config SYS_CONFIG_NAME + default "opos6uldev" + +-config IMX_CONFIG +- default "arch/arm/mach-imx/spl_sd.cfg" +- + endif +diff -ruN u-boot-2021.10/board/armltd/vexpress/Kconfig u-boot/board/armltd/vexpress/Kconfig +--- u-boot-2021.10/board/armltd/vexpress/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/armltd/vexpress/Kconfig 2021-11-01 17:10:13.969608529 +0100 +@@ -0,0 +1,12 @@ ++if TARGET_VEXPRESS_CA9X4 ++ ++config SYS_BOARD ++ default "vexpress" ++ ++config SYS_VENDOR ++ default "armltd" ++ ++config SYS_CONFIG_NAME ++ default "vexpress_ca9x4" ++ ++endif +diff -ruN u-boot-2021.10/board/armltd/vexpress/MAINTAINERS u-boot/board/armltd/vexpress/MAINTAINERS +--- u-boot-2021.10/board/armltd/vexpress/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/armltd/vexpress/MAINTAINERS 2021-11-01 17:10:13.969608529 +0100 +@@ -0,0 +1,6 @@ ++VERSATILE EXPRESS BOARDS ++M: Kristian Amlie ++S: Maintained ++F: board/armltd/vexpress/ ++F: include/configs/vexpress_ca9x4.h ++F: configs/vexpress_ca9x4_defconfig +diff -ruN u-boot-2021.10/board/armltd/vexpress/Makefile u-boot/board/armltd/vexpress/Makefile +--- u-boot-2021.10/board/armltd/vexpress/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/armltd/vexpress/Makefile 2021-11-01 17:10:13.969608529 +0100 +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2000-2004 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ ++obj-y := vexpress_common.o +diff -ruN u-boot-2021.10/board/armltd/vexpress/vexpress_common.c u-boot/board/armltd/vexpress/vexpress_common.c +--- u-boot-2021.10/board/armltd/vexpress/vexpress_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/armltd/vexpress/vexpress_common.c 2021-11-01 17:10:13.969608529 +0100 +@@ -0,0 +1,167 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * (C) Copyright 2003 ++ * Texas Instruments, ++ * Kshitij Gupta ++ * ++ * (C) Copyright 2004 ++ * ARM Ltd. ++ * Philippe Robin, ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; ++static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; ++ ++static void flash__init(void); ++static void vexpress_timer_init(void); ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_SHOW_BOOT_PROGRESS) ++void show_boot_progress(int progress) ++{ ++ printf("Boot reached stage %d\n", progress); ++} ++#endif ++ ++static inline void delay(ulong loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b" : "=r" (loops) : "0" (loops)); ++} ++ ++int board_init(void) ++{ ++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; ++ gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; ++ ++ icache_enable(); ++ flash__init(); ++ vexpress_timer_init(); ++ ++ return 0; ++} ++ ++static void flash__init(void) ++{ ++ /* Setup the sytem control register to allow writing to flash */ ++ writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, ++ &sysctrl_base->scflashctrl); ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = ++ get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = ++ get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = ++ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); ++ ++ return 0; ++} ++ ++/* ++ * Start timer: ++ * Setup a 32 bit timer, running at 1KHz ++ * Versatile Express Motherboard provides 1 MHz timer ++ */ ++static void vexpress_timer_init(void) ++{ ++ /* ++ * Set clock frequency in system controller: ++ * VEXPRESS_REFCLK is 32KHz ++ * VEXPRESS_TIMCLK is 1MHz ++ */ ++ writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | ++ SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | ++ readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); ++ ++ /* ++ * Set Timer0 to be: ++ * Enabled, free running, no interrupt, 32-bit, wrapping ++ */ ++ writel(SYSTIMER_RELOAD, &systimer_base->timer0load); ++ writel(SYSTIMER_RELOAD, &systimer_base->timer0value); ++ writel(SYSTIMER_EN | SYSTIMER_32BIT | ++ readl(&systimer_base->timer0control), ++ &systimer_base->timer0control); ++} ++ ++int v2m_cfg_write(u32 devfn, u32 data) ++{ ++ /* Configuration interface broken? */ ++ u32 val; ++ ++ devfn |= SYS_CFG_START | SYS_CFG_WRITE; ++ ++ val = readl(V2M_SYS_CFGSTAT); ++ writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); ++ ++ writel(data, V2M_SYS_CFGDATA); ++ writel(devfn, V2M_SYS_CFGCTRL); ++ ++ do { ++ val = readl(V2M_SYS_CFGSTAT); ++ } while (val == 0); ++ ++ return !!(val & SYS_CFG_ERR); ++} ++ ++/* Use the ARM Watchdog System to cause reset */ ++void reset_cpu(void) ++{ ++ if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) ++ printf("Unable to reboot\n"); ++} ++ ++void lowlevel_init(void) ++{ ++} ++ ++ulong get_board_rev(void){ ++ return readl((u32 *)SYS_ID); ++} ++ ++#ifdef CONFIG_ARMV7_NONSEC ++/* Setting the address at which secondary cores start from. ++ * Versatile Express uses one address for all cores, so ignore corenr ++ */ ++void smp_set_core_boot_addr(unsigned long addr, int corenr) ++{ ++ /* The SYSFLAGS register on VExpress needs to be cleared first ++ * by writing to the next address, since any writes to the address ++ * at offset 0 will only be ORed in ++ */ ++ writel(~0, CONFIG_SYSFLAGS_ADDR + 4); ++ writel(addr, CONFIG_SYSFLAGS_ADDR); ++} ++#endif +diff -ruN u-boot-2021.10/board/atmark-techno/armadillo-800eva/Makefile u-boot/board/atmark-techno/armadillo-800eva/Makefile +--- u-boot-2021.10/board/atmark-techno/armadillo-800eva/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmark-techno/armadillo-800eva/Makefile 2021-11-01 17:10:13.972941680 +0100 +@@ -3,4 +3,3 @@ + # Copyright (C) 2012 Nobuhiro Iwamatsu + + obj-y += armadillo-800eva.o +- +diff -ruN u-boot-2021.10/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +--- u-boot-2021.10/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c 2021-11-01 17:10:13.972941680 +0100 +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -68,7 +69,7 @@ + int board_init(void) + { + /* address of boot parameters */ +- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; ++ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + #ifdef CONFIG_CMD_USB + board_usb_hw_init(); +@@ -77,11 +78,14 @@ + return 0; + } + ++int dram_init_banksize(void) ++{ ++ return fdtdec_setup_memory_banksize(); ++} ++ + int dram_init(void) + { +- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, +- CONFIG_SYS_SDRAM_SIZE); +- return 0; ++ return fdtdec_setup_mem_size_base(); + } + + #define MAC24AA_MAC_OFFSET 0xfa +diff -ruN u-boot-2021.10/board/atmel/sama5d2_icp/MAINTAINERS u-boot/board/atmel/sama5d2_icp/MAINTAINERS +--- u-boot-2021.10/board/atmel/sama5d2_icp/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmel/sama5d2_icp/MAINTAINERS 2021-11-01 17:10:13.972941680 +0100 +@@ -4,4 +4,5 @@ + F: board/atmel/sama5d2_icp/ + F: include/configs/sama5d2_icp.h + F: configs/sama5d2_icp_mmc_defconfig ++F: configs/sama5d2_icp_qspiflash_defconfig + +diff -ruN u-boot-2021.10/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +--- u-boot-2021.10/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c 2021-11-01 17:10:13.972941680 +0100 +@@ -10,7 +10,6 @@ + #include + #include + #include +-#include + #include + #include + #include +diff -ruN u-boot-2021.10/board/atmel/sama5d2_xplained/sama5d2_xplained.c u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c +--- u-boot-2021.10/board/atmel/sama5d2_xplained/sama5d2_xplained.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmel/sama5d2_xplained/sama5d2_xplained.c 2021-11-01 17:10:13.972941680 +0100 +@@ -68,7 +68,7 @@ + int board_init(void) + { + /* address of boot parameters */ +- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; ++ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + #ifdef CONFIG_CMD_USB + board_usb_hw_init(); +@@ -77,11 +77,14 @@ + return 0; + } + ++int dram_init_banksize(void) ++{ ++ return fdtdec_setup_memory_banksize(); ++} ++ + int dram_init(void) + { +- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, +- CONFIG_SYS_SDRAM_SIZE); +- return 0; ++ return fdtdec_setup_mem_size_base(); + } + + #define AT24MAC_MAC_OFFSET 0x9a +diff -ruN u-boot-2021.10/board/atmel/sama7g5ek/sama7g5ek.c u-boot/board/atmel/sama7g5ek/sama7g5ek.c +--- u-boot-2021.10/board/atmel/sama7g5ek/sama7g5ek.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/atmel/sama7g5ek/sama7g5ek.c 2021-11-01 17:10:13.976274831 +0100 +@@ -74,4 +74,3 @@ + CONFIG_SYS_SDRAM_SIZE); + return 0; + } +- +diff -ruN u-boot-2021.10/board/beacon/imx8mm/Kconfig u-boot/board/beacon/imx8mm/Kconfig +--- u-boot-2021.10/board/beacon/imx8mm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beacon/imx8mm/Kconfig 2021-11-01 17:10:13.976274831 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8mm_beacon" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/beacon/imx8mn/Kconfig u-boot/board/beacon/imx8mn/Kconfig +--- u-boot-2021.10/board/beacon/imx8mn/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beacon/imx8mn/Kconfig 2021-11-01 17:10:13.976274831 +0100 +@@ -11,11 +11,12 @@ + + config IMX8MN_FORCE_NOM_SOC + bool "Force to use nominal mode for SOC and ARM" +- default n + + config IMX8MN_BEACON_2GB_LPDDR + bool "Enable 2GB LPDDR" +- default n ++ ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" + + source "board/freescale/common/Kconfig" + +diff -ruN u-boot-2021.10/board/beacon/imx8mn/lpddr4_timing.c u-boot/board/beacon/imx8mn/lpddr4_timing.c +--- u-boot-2021.10/board/beacon/imx8mn/lpddr4_timing.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beacon/imx8mn/lpddr4_timing.c 2021-11-01 17:10:13.976274831 +0100 +@@ -1431,4 +1431,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, + }; +- +diff -ruN u-boot-2021.10/board/beacon/imx8mn/README u-boot/board/beacon/imx8mn/README +--- u-boot-2021.10/board/beacon/imx8mn/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beacon/imx8mn/README 2021-11-01 17:10:13.976274831 +0100 +@@ -36,4 +36,3 @@ + ==== + Set baseboard DIP switch: + S17: 1100XXXX +- +diff -ruN u-boot-2021.10/board/beckhoff/mx53cx9020/Kconfig u-boot/board/beckhoff/mx53cx9020/Kconfig +--- u-boot-2021.10/board/beckhoff/mx53cx9020/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beckhoff/mx53cx9020/Kconfig 2021-11-01 17:10:13.976274831 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx53cx9020" + ++config IMX_CONFIG ++ default "board/beckhoff/mx53cx9020/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/beckhoff/mx53cx9020/mx53cx9020.c u-boot/board/beckhoff/mx53cx9020/mx53cx9020.c +--- u-boot-2021.10/board/beckhoff/mx53cx9020/mx53cx9020.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/beckhoff/mx53cx9020/mx53cx9020.c 2021-11-01 17:10:13.976274831 +0100 +@@ -48,6 +48,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; +@@ -59,6 +60,7 @@ + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; + } ++#endif + + /* + * Set CCAT mode +diff -ruN u-boot-2021.10/board/bosch/guardian/board.c u-boot/board/bosch/guardian/board.c +--- u-boot-2021.10/board/bosch/guardian/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/bosch/guardian/board.c 2021-11-01 17:10:13.979607982 +0100 +@@ -40,7 +40,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + static const struct ddr_data ddr3_data = { +@@ -142,7 +142,7 @@ + const struct dpll_params *get_dpll_ddr_params(void) + { + enable_i2c0_pin_mux(); +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return &dpll_ddr; + } +diff -ruN u-boot-2021.10/board/bosch/guardian/Makefile u-boot/board/bosch/guardian/Makefile +--- u-boot-2021.10/board/bosch/guardian/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/bosch/guardian/Makefile 2021-11-01 17:10:13.979607982 +0100 +@@ -5,7 +5,7 @@ + # Copyright (C) 2018 Robert Bosch Power Tools GmbH + # + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/bosch/shc/board.c u-boot/board/bosch/shc/board.c +--- u-boot-2021.10/board/bosch/shc/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/bosch/shc/board.c 2021-11-01 17:10:13.979607982 +0100 +@@ -51,16 +51,17 @@ + /* + * Read header information from EEPROM into global structure. + */ ++#define EEPROM_ADDR 0x50 + static int read_eeprom(void) + { + /* Check if baseboard eeprom is available */ +- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { ++ if (i2c_probe(EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ +- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, ++ if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -EIO; +diff -ruN u-boot-2021.10/board/boundary/nitrogen6x/Kconfig u-boot/board/boundary/nitrogen6x/Kconfig +--- u-boot-2021.10/board/boundary/nitrogen6x/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/boundary/nitrogen6x/Kconfig 2021-11-01 17:10:13.979607982 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "nitrogen6x" + ++config DDR_MB ++ int "Memory size in MB" ++ + endif +diff -ruN u-boot-2021.10/board/boundary/nitrogen6x/README u-boot/board/boundary/nitrogen6x/README +--- u-boot-2021.10/board/boundary/nitrogen6x/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/boundary/nitrogen6x/README 2021-11-01 17:10:13.979607982 +0100 +@@ -74,7 +74,7 @@ + nitrogen6q i.MX6Q/6D 1GB + nitrogen6dl i.MX6DL 1GB + nitrogen6s i.MX6S 512MB +- nitrogen6q2g i.MX6Q/6D 2GB ++ nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6s1g i.MX6S 1GB + +diff -ruN u-boot-2021.10/board/boundary/nitrogen6x/README.mx6qsabrelite u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite +--- u-boot-2021.10/board/boundary/nitrogen6x/README.mx6qsabrelite 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/boundary/nitrogen6x/README.mx6qsabrelite 2021-11-01 17:10:13.979607982 +0100 +@@ -116,4 +116,3 @@ + 5. Use one of previous descriptions to re-flash the SPI-NOR as required. + + 6. Ensure SW1 is returned to "00" to boot from the fuses once done. +- +diff -ruN u-boot-2021.10/board/broadcom/bcmstb/bcmstb.c u-boot/board/broadcom/bcmstb/bcmstb.c +--- u-boot-2021.10/board/broadcom/bcmstb/bcmstb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/broadcom/bcmstb/bcmstb.c 2021-11-01 17:10:13.982941133 +0100 +@@ -38,11 +38,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + void reset_cpu(void) + { + } +diff -ruN u-boot-2021.10/board/cadence/xtfpga/README u-boot/board/cadence/xtfpga/README +--- u-boot-2021.10/board/cadence/xtfpga/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/cadence/xtfpga/README 2021-11-01 17:10:13.982941133 +0100 +@@ -122,4 +122,3 @@ + Because this problem is easy to fall into and difficult to debug + if one doesn't expect it, the linker script provides a link-time + check and fatal error message if the image size exceeds 128 KB. +- +diff -ruN u-boot-2021.10/board/CarMediaLab/flea3/flea3.c u-boot/board/CarMediaLab/flea3/flea3.c +--- u-boot-2021.10/board/CarMediaLab/flea3/flea3.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/CarMediaLab/flea3/flea3.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,225 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2007, Guennadi Liakhovetski +- * +- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. +- * +- * Copyright (C) 2011, Stefano Babic +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#ifndef CONFIG_BOARD_EARLY_INIT_F +-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +-#endif +- +-#define CCM_CCMR_CONFIG 0x003F4208 +- +-#define ESDCTL_DDR2_CONFIG 0x007FFC3F +- +-static inline void dram_wait(unsigned int count) +-{ +- volatile unsigned int wait = count; +- +- while (wait--) +- ; +-} +- +-DECLARE_GLOBAL_DATA_PTR; +- +-int dram_init(void) +-{ +- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, +- PHYS_SDRAM_1_SIZE); +- +- return 0; +-} +- +-static void board_setup_sdram(void) +-{ +- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; +- +- /* Initialize with default values both CSD0/1 */ +- writel(0x2000, &esdc->esdctl0); +- writel(0x2000, &esdc->esdctl1); +- +- +- mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, +- 13, 10, 2, 0x8080); +-} +- +-static void setup_iomux_uart3(void) +-{ +- static const iomux_v3_cfg_t uart3_pads[] = { +- MX35_PAD_RTS2__UART3_RXD_MUX, +- MX35_PAD_CTS2__UART3_TXD_MUX, +- }; +- +- imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +-} +- +-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) +- +-static void setup_iomux_i2c(void) +-{ +- static const iomux_v3_cfg_t i2c_pads[] = { +- NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), +- NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), +- +- NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), +- NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), +- }; +- +- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); +-} +- +- +-static void setup_iomux_spi(void) +-{ +- static const iomux_v3_cfg_t spi_pads[] = { +- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, +- MX35_PAD_CSPI1_MISO__CSPI1_MISO, +- MX35_PAD_CSPI1_SS0__CSPI1_SS0, +- MX35_PAD_CSPI1_SS1__CSPI1_SS1, +- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, +- }; +- +- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); +-} +- +-static void setup_iomux_fec(void) +-{ +- static const iomux_v3_cfg_t fec_pads[] = { +- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, +- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, +- MX35_PAD_FEC_RX_DV__FEC_RX_DV, +- MX35_PAD_FEC_COL__FEC_COL, +- MX35_PAD_FEC_RDATA0__FEC_RDATA_0, +- MX35_PAD_FEC_TDATA0__FEC_TDATA_0, +- MX35_PAD_FEC_TX_EN__FEC_TX_EN, +- MX35_PAD_FEC_MDC__FEC_MDC, +- MX35_PAD_FEC_MDIO__FEC_MDIO, +- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, +- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, +- MX35_PAD_FEC_CRS__FEC_CRS, +- MX35_PAD_FEC_RDATA1__FEC_RDATA_1, +- MX35_PAD_FEC_TDATA1__FEC_TDATA_1, +- MX35_PAD_FEC_RDATA2__FEC_RDATA_2, +- MX35_PAD_FEC_TDATA2__FEC_TDATA_2, +- MX35_PAD_FEC_RDATA3__FEC_RDATA_3, +- MX35_PAD_FEC_TDATA3__FEC_TDATA_3, +- /* GPIO used to power off ethernet */ +- MX35_PAD_STXFS4__GPIO2_31, +- }; +- +- /* setup pins for FEC */ +- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +-} +- +-int board_early_init_f(void) +-{ +- struct ccm_regs *ccm = +- (struct ccm_regs *)IMX_CCM_BASE; +- +- /* setup GPIO3_1 to set HighVCore signal */ +- imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); +- gpio_direction_output(65, 1); +- +- /* initialize PLL and clock configuration */ +- writel(CCM_CCMR_CONFIG, &ccm->ccmr); +- +- writel(CCM_MPLL_532_HZ, &ccm->mpctl); +- writel(CCM_PPLL_300_HZ, &ccm->ppctl); +- +- /* Set the core to run at 532 Mhz */ +- writel(0x00001000, &ccm->pdr0); +- +- /* Set-up RAM */ +- board_setup_sdram(); +- +- /* enable clocks */ +- writel(readl(&ccm->cgr0) | +- MXC_CCM_CGR0_EMI_MASK | +- MXC_CCM_CGR0_EDIO_MASK | +- MXC_CCM_CGR0_EPIT1_MASK, +- &ccm->cgr0); +- +- writel(readl(&ccm->cgr1) | +- MXC_CCM_CGR1_FEC_MASK | +- MXC_CCM_CGR1_GPIO1_MASK | +- MXC_CCM_CGR1_GPIO2_MASK | +- MXC_CCM_CGR1_GPIO3_MASK | +- MXC_CCM_CGR1_I2C1_MASK | +- MXC_CCM_CGR1_I2C2_MASK | +- MXC_CCM_CGR1_I2C3_MASK, +- &ccm->cgr1); +- +- /* Set-up NAND */ +- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); +- +- /* Set pinmux for the required peripherals */ +- setup_iomux_uart3(); +- setup_iomux_i2c(); +- setup_iomux_fec(); +- setup_iomux_spi(); +- +- return 0; +-} +- +-int board_init(void) +-{ +- /* address of boot parameters */ +- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +- +- /* Enable power for ethernet */ +- gpio_direction_output(63, 0); +- +- udelay(2000); +- +- return 0; +-} +- +-u32 get_board_rev(void) +-{ +- int rev = 0; +- +- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +-} +- +-/* +- * called prior to booting kernel or by 'fdt boardsetup' command +- * +- */ +-int ft_board_setup(void *blob, struct bd_info *bd) +-{ +- static const struct node_info nodes[] = { +- { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ +- { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ +- }; +- +- if (env_get("fdt_noauto")) { +- puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); +- return 0; +- } +- +- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +- +- return 0; +-} +diff -ruN u-boot-2021.10/board/CarMediaLab/flea3/Kconfig u-boot/board/CarMediaLab/flea3/Kconfig +--- u-boot-2021.10/board/CarMediaLab/flea3/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/CarMediaLab/flea3/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,15 +0,0 @@ +-if TARGET_FLEA3 +- +-config SYS_BOARD +- default "flea3" +- +-config SYS_VENDOR +- default "CarMediaLab" +- +-config SYS_SOC +- default "mx35" +- +-config SYS_CONFIG_NAME +- default "flea3" +- +-endif +diff -ruN u-boot-2021.10/board/CarMediaLab/flea3/lowlevel_init.S u-boot/board/CarMediaLab/flea3/lowlevel_init.S +--- u-boot-2021.10/board/CarMediaLab/flea3/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/CarMediaLab/flea3/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1,24 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2007, Guennadi Liakhovetski +- * +- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. +- * +- * Copyright (C) 2011, Stefano Babic +- */ +- +-#include +-#include +- +-.globl lowlevel_init +-lowlevel_init: +- +- core_init +- +- init_aips +- +- init_max +- +- init_m3if +- +- mov pc, lr +diff -ruN u-boot-2021.10/board/CarMediaLab/flea3/MAINTAINERS u-boot/board/CarMediaLab/flea3/MAINTAINERS +--- u-boot-2021.10/board/CarMediaLab/flea3/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/CarMediaLab/flea3/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 +@@ -1,6 +0,0 @@ +-FLEA3 BOARD +-M: Stefano Babic +-S: Maintained +-F: board/CarMediaLab/flea3/ +-F: include/configs/flea3.h +-F: configs/flea3_defconfig +diff -ruN u-boot-2021.10/board/CarMediaLab/flea3/Makefile u-boot/board/CarMediaLab/flea3/Makefile +--- u-boot-2021.10/board/CarMediaLab/flea3/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/CarMediaLab/flea3/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# Copyright (C) 2007, Guennadi Liakhovetski +-# +-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +- +-obj-y := flea3.o +-obj-y += lowlevel_init.o +diff -ruN u-boot-2021.10/board/compulab/cl-som-imx7/cl-som-imx7.c u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c +--- u-boot-2021.10/board/compulab/cl-som-imx7/cl-som-imx7.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c 2021-11-01 17:10:13.982941133 +0100 +@@ -267,7 +267,7 @@ + return 0; + } + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + #define I2C_PMIC 0 + int power_init_board(void) + { +@@ -293,7 +293,7 @@ + + return 0; + } +-#endif /* CONFIG_POWER */ ++#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ + + /* + * cl_som_imx7_setup_wdog() - watchdog configuration. +diff -ruN u-boot-2021.10/board/compulab/cl-som-imx7/spl.c u-boot/board/compulab/cl-som-imx7/spl.c +--- u-boot-2021.10/board/compulab/cl-som-imx7/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cl-som-imx7/spl.c 2021-11-01 17:10:13.986274284 +0100 +@@ -157,15 +157,15 @@ + } + } + +-#ifdef CONFIG_SPL_SPI_SUPPORT ++#ifdef CONFIG_SPL_SPI + + static void cl_som_imx7_spl_spi_init(void) + { + cl_som_imx7_espi1_pads_set(); + } +-#else /* !CONFIG_SPL_SPI_SUPPORT */ ++#else /* !CONFIG_SPL_SPI */ + static void cl_som_imx7_spl_spi_init(void) {} +-#endif /* CONFIG_SPL_SPI_SUPPORT */ ++#endif /* CONFIG_SPL_SPI */ + + void board_init_f(ulong dummy) + { +diff -ruN u-boot-2021.10/board/compulab/cm_fx6/cm_fx6.c u-boot/board/compulab/cm_fx6/cm_fx6.c +--- u-boot-2021.10/board/compulab/cm_fx6/cm_fx6.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cm_fx6/cm_fx6.c 2021-11-01 17:10:13.986274284 +0100 +@@ -720,10 +720,12 @@ + return 0; + } + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); + } ++#endif + + static struct mxc_serial_plat cm_fx6_mxc_serial_plat = { + .reg = (struct mxc_uart *)UART4_BASE, +diff -ruN u-boot-2021.10/board/compulab/cm_fx6/spl.c u-boot/board/compulab/cm_fx6/spl.c +--- u-boot-2021.10/board/compulab/cm_fx6/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cm_fx6/spl.c 2021-11-01 17:10:13.986274284 +0100 +@@ -302,7 +302,7 @@ + enable_uart_clk(1); + } + +-#ifdef CONFIG_SPL_SPI_SUPPORT ++#ifdef CONFIG_SPL_SPI + static void cm_fx6_setup_ecspi(void) + { + cm_fx6_set_ecspi_iomux(); +@@ -350,7 +350,7 @@ + } + } + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 4, +diff -ruN u-boot-2021.10/board/compulab/cm_t43/cm_t43.c u-boot/board/compulab/cm_t43/cm_t43.c +--- u-boot-2021.10/board/compulab/cm_t43/cm_t43.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cm_t43/cm_t43.c 2021-11-01 17:10:13.986274284 +0100 +@@ -48,7 +48,7 @@ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +diff -ruN u-boot-2021.10/board/compulab/cm_t43/spl.c u-boot/board/compulab/cm_t43/spl.c +--- u-boot-2021.10/board/compulab/cm_t43/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/cm_t43/spl.c 2021-11-01 17:10:13.986274284 +0100 +@@ -106,7 +106,7 @@ + void scale_vcores(void) + { + set_i2c_pin_mux(); +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (i2c_probe(TPS65218_CHIP_PM)) + return; + +@@ -133,4 +133,3 @@ + + hang(); + } +- +diff -ruN u-boot-2021.10/board/compulab/common/eeprom.c u-boot/board/compulab/common/eeprom.c +--- u-boot-2021.10/board/compulab/common/eeprom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/common/eeprom.c 2021-11-01 17:10:13.986274284 +0100 +@@ -15,15 +15,6 @@ + #include + #include "eeprom.h" + +-#ifndef CONFIG_SYS_I2C_EEPROM_ADDR +-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#endif +- +-#ifndef CONFIG_SYS_I2C_EEPROM_BUS +-#define CONFIG_SYS_I2C_EEPROM_BUS 0 +-#endif +- + #define EEPROM_LAYOUT_VER_OFFSET 44 + #define BOARD_SERIAL_OFFSET 20 + #define BOARD_SERIAL_OFFSET_LEGACY 8 +@@ -394,43 +385,8 @@ + #define LAYOUT_VERSION_VER2 3 + #define LAYOUT_VERSION_VER3 4 + +-extern struct eeprom_field layout_unknown[1]; +- + #define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x + +-#ifdef CONFIG_CM_T3X +-struct eeprom_field layout_legacy[5] = { +- { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, +- { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) }, +- { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) }, +- { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) }, +- { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved, +- eeprom_field_update_ascii }, +-}; +-#else +-#define layout_legacy layout_unknown +-#endif +- +-#if defined(CONFIG_CM_T3X) +-struct eeprom_field layout_v1[12] = { +- { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, +- { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, +- { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, +- { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, +- { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, +- { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, +- { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) }, +- { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, +- { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, +- { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, +- { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, +- { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, +- eeprom_field_update_ascii }, +-}; +-#else +-#define layout_v1 layout_unknown +-#endif +- + struct eeprom_field layout_v2[15] = { + { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, +@@ -473,14 +429,6 @@ + void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) + { + switch (layout->layout_version) { +- case LAYOUT_VERSION_LEGACY: +- layout->fields = layout_legacy; +- layout->num_of_fields = ARRAY_SIZE(layout_legacy); +- break; +- case LAYOUT_VERSION_VER1: +- layout->fields = layout_v1; +- layout->num_of_fields = ARRAY_SIZE(layout_v1); +- break; + case LAYOUT_VERSION_VER2: + layout->fields = layout_v2; + layout->num_of_fields = ARRAY_SIZE(layout_v2); +diff -ruN u-boot-2021.10/board/compulab/common/eeprom.h u-boot/board/compulab/common/eeprom.h +--- u-boot-2021.10/board/compulab/common/eeprom.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/common/eeprom.h 2021-11-01 17:10:13.986274284 +0100 +@@ -10,7 +10,7 @@ + #define _EEPROM_ + #include + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); + u32 cl_eeprom_get_board_rev(uint eeprom_bus); + int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus); +diff -ruN u-boot-2021.10/board/compulab/common/Makefile u-boot/board/compulab/common/Makefile +--- u-boot-2021.10/board/compulab/common/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/common/Makefile 2021-11-01 17:10:13.986274284 +0100 +@@ -5,6 +5,6 @@ + # Author: Igor Grinberg + + obj-y += common.o +-obj-$(CONFIG_SYS_I2C_LEGACY) += eeprom.o ++obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o + obj-$(CONFIG_LCD) += omap3_display.o + obj-$(CONFIG_SMC911X) += omap3_smc911x.o +diff -ruN u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c +--- u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c 2021-11-01 17:10:13.986274284 +0100 +@@ -1845,4 +1845,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 400, 100, }, + }; +- +diff -ruN u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/Kconfig u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig +--- u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig 2021-11-01 17:10:13.986274284 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mm-cl-iot-gate" + ++config IMX_CONFIG ++ default "board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/spl.c u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c +--- u-boot-2021.10/board/compulab/imx8mm-cl-iot-gate/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c 2021-11-01 17:10:13.986274284 +0100 +@@ -176,7 +176,7 @@ + + enable_tzc380(); + +- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); ++ setup_i2c(1, 100000, 0x7f, &i2c_pad_info1); + + power_init_board(); + +diff -ruN u-boot-2021.10/board/congatec/cgtqmx8/Kconfig u-boot/board/congatec/cgtqmx8/Kconfig +--- u-boot-2021.10/board/congatec/cgtqmx8/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/congatec/cgtqmx8/Kconfig 2021-11-01 17:10:13.989607435 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "cgtqmx8" + ++config IMX_CONFIG ++ default "board/congatec/cgtqmx8/imximage.cfg" ++ + source "board/congatec/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/congatec/common/Kconfig u-boot/board/congatec/common/Kconfig +--- u-boot-2021.10/board/congatec/common/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/congatec/common/Kconfig 2021-11-01 17:10:13.989607435 +0100 +@@ -28,7 +28,6 @@ + config VOL_MONITOR_LTC3882_READ + depends on VID + bool "Enable the LTC3882 voltage monitor read" +- default n + help + This option enables LTC3882 voltage monitor read + functionality. It is used by common VID driver. +@@ -36,13 +35,11 @@ + config VOL_MONITOR_LTC3882_SET + depends on VID + bool "Enable the LTC3882 voltage monitor set" +- default n + help + This option enables LTC3882 voltage monitor set + functionality. It is used by common VID driver. + + config USB_TCPC + bool "USB Typec port controller simple driver" +- default n + help + Enable USB type-c port controller (TCPC) driver +diff -ruN u-boot-2021.10/board/cssi/MCR3000/nand.c u-boot/board/cssi/MCR3000/nand.c +--- u-boot-2021.10/board/cssi/MCR3000/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/cssi/MCR3000/nand.c 2021-11-01 17:10:13.989607435 +0100 +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + + #define BIT_CLE ((unsigned short)0x0800) +diff -ruN u-boot-2021.10/board/davinci/da8xxevm/da850evm.c u-boot/board/davinci/da8xxevm/da850evm.c +--- u-boot-2021.10/board/davinci/da8xxevm/da850evm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/davinci/da8xxevm/da850evm.c 2021-11-01 17:10:13.989607435 +0100 +@@ -129,19 +129,12 @@ + { + dspwake(); + +-#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) +- +- uchar env_enetaddr[6]; +- int enetaddr_found; ++#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) ++ uchar env_enetaddr[6], buff[6]; ++ int enetaddr_found, spi_mac_read; + + enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr); + +-#endif +- +-#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH +- int spi_mac_read; +- uchar buff[6]; +- + spi_mac_read = get_mac_addr(buff); + buff[0] = 0; + +@@ -173,34 +166,6 @@ + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } +- +-#elif defined(CONFIG_MAC_ADDR_IN_EEPROM) +- uint8_t enetaddr[8]; +- int eeprom_mac_read; +- +- /* Read Ethernet MAC address from EEPROM */ +- eeprom_mac_read = dvevm_read_mac_address(enetaddr); +- +- /* +- * MAC address not present in the environment +- * try and read the MAC address from EEPROM flash +- * and set it. +- */ +- if (!enetaddr_found) { +- if (eeprom_mac_read) +- /* Set Ethernet MAC address from EEPROM */ +- davinci_sync_env_enetaddr(enetaddr); +- } else { +- /* +- * MAC address present in environment compare it with +- * the MAC address in EEPROM and warn on mismatch +- */ +- if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) +- printf("Warning: MAC address in EEPROM don't match " +- "with the MAC address in the environment\n"); +- printf("Default using MAC address from environment\n"); +- } +- + #endif + return 0; + } +@@ -267,6 +232,7 @@ + + #define REV_AM18X_EVM 0x100 + ++#ifdef CONFIG_REVISION_TAG + /* + * get_board_rev() - setup to pass kernel board revision information + * Returns: +@@ -294,6 +260,7 @@ + rev = 1; + return rev; + } ++#endif + + int board_early_init_f(void) + { +diff -ruN u-boot-2021.10/board/davinci/da8xxevm/Kconfig u-boot/board/davinci/da8xxevm/Kconfig +--- u-boot-2021.10/board/davinci/da8xxevm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/davinci/da8xxevm/Kconfig 2021-11-01 17:10:13.989607435 +0100 +@@ -22,15 +22,6 @@ + their MAC address in SPI Flash from the factory + Enable this option to read the MAC from SPI Flash + +-config MAC_ADDR_IN_EEPROM +- bool "MAC address in EEPROM" +- help +- The DA850 EVM comes with SoM are programmed with +- their MAC address in SPI Flash from the factory, +- but the kit has an optional expansion board with +- EEPROM available. Enable this option to read the +- MAC from the EEPROM +- + endif + + endif +diff -ruN u-boot-2021.10/board/davinci/da8xxevm/Makefile u-boot/board/davinci/da8xxevm/Makefile +--- u-boot-2021.10/board/davinci/da8xxevm/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/davinci/da8xxevm/Makefile 2021-11-01 17:10:13.989607435 +0100 +@@ -7,4 +7,4 @@ + + obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o + obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o +-obj-$(CONFIG_MACH_OMAPL138_LCDK) += omapl138_lcdk.o ++obj-$(CONFIG_TARGET_OMAPL138_LCDK) += omapl138_lcdk.o +diff -ruN u-boot-2021.10/board/davinci/da8xxevm/omapl138_lcdk.c u-boot/board/davinci/da8xxevm/omapl138_lcdk.c +--- u-boot-2021.10/board/davinci/da8xxevm/omapl138_lcdk.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/davinci/da8xxevm/omapl138_lcdk.c 2021-11-01 17:10:13.989607435 +0100 +@@ -143,20 +143,6 @@ + #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000 + #endif + +-/* +- * get_board_rev() - setup to pass kernel board revision information +- * Returns: +- * bit[0-3] Maximum cpu clock rate supported by onboard SoC +- * 0000b - 300 MHz +- * 0001b - 372 MHz +- * 0010b - 408 MHz +- * 0011b - 456 MHz +- */ +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_early_init_f(void) + { + /* +@@ -236,12 +222,6 @@ + + #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) + +-static int get_mac_addr(u8 *addr) +-{ +- /* Need to find a way to get MAC ADDRESS */ +- return 0; +-} +- + void dsp_lpsc_on(unsigned domain, unsigned int id) + { + dv_reg_p mdstat, mdctl, ptstat, ptcmd; +@@ -304,29 +284,6 @@ + + int misc_init_r(void) + { +- uint8_t tmp[20], addr[10]; +- +- +- if (env_get("ethaddr") == NULL) { +- /* Read Ethernet MAC address from EEPROM */ +- if (dvevm_read_mac_address(addr)) { +- /* Set Ethernet MAC address from EEPROM */ +- davinci_sync_env_enetaddr(addr); +- } else { +- get_mac_addr(addr); +- } +- +- if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) { +- sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", +- addr[0], addr[1], addr[2], addr[3], addr[4], +- addr[5]); +- +- env_set("ethaddr", (char *)tmp); +- } else { +- printf("Invalid MAC address read.\n"); +- } +- } +- + #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + /* Select RMII fucntion through the expander */ + if (rmii_hw_init()) +diff -ruN u-boot-2021.10/board/dhelectronics/dh_stm32mp1/board.c u-boot/board/dhelectronics/dh_stm32mp1/board.c +--- u-boot-2021.10/board/dhelectronics/dh_stm32mp1/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/dhelectronics/dh_stm32mp1/board.c 2021-11-01 17:10:13.992940586 +0100 +@@ -42,6 +42,7 @@ + #include + #include + #include ++#include + #include "../../st/common/stpmic1.h" + + /* SYSCFG registers */ +@@ -382,10 +383,10 @@ + #ifdef CONFIG_LED + static int get_led(struct udevice **dev, char *led_string) + { +- char *led_name; ++ const char *led_name; + int ret; + +- led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); ++ led_name = ofnode_conf_read_str(led_string); + if (!led_name) { + pr_debug("%s: could not find %s config string\n", + __func__, led_string); +diff -ruN u-boot-2021.10/board/ea/mx7ulp_com/Kconfig u-boot/board/ea/mx7ulp_com/Kconfig +--- u-boot-2021.10/board/ea/mx7ulp_com/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ea/mx7ulp_com/Kconfig 2021-11-01 17:10:13.992940586 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx7ulp_com" + ++config IMX_CONFIG ++ default "board/ea/mx7ulp_com/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/eets/pdu001/board.c u-boot/board/eets/pdu001/board.c +--- u-boot-2021.10/board/eets/pdu001/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/eets/pdu001/board.c 2021-11-01 17:10:13.992940586 +0100 +@@ -162,7 +162,7 @@ + } + } + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + static const struct ddr_data ddr2_data = { + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, +@@ -235,7 +235,7 @@ + config_ddr(266, &ioregs, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); + } +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + #ifdef CONFIG_DEBUG_UART + void board_debug_uart_init(void) +diff -ruN u-boot-2021.10/board/eets/pdu001/Makefile u-boot/board/eets/pdu001/Makefile +--- u-boot-2021.10/board/eets/pdu001/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/eets/pdu001/Makefile 2021-11-01 17:10:13.992940586 +0100 +@@ -6,7 +6,7 @@ + # SPDX-License-Identifier: GPL-2.0+ + # + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/embest/mx6boards/mx6boards.c u-boot/board/embest/mx6boards/mx6boards.c +--- u-boot-2021.10/board/embest/mx6boards/mx6boards.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/embest/mx6boards/mx6boards.c 2021-11-01 17:10:13.992940586 +0100 +@@ -473,7 +473,7 @@ + /* setup GP timer */ + timer_init(); + +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + setup_iomux_uart(); + preloader_console_init(); + #endif +diff -ruN u-boot-2021.10/board/engicam/imx8mm/Kconfig u-boot/board/engicam/imx8mm/Kconfig +--- u-boot-2021.10/board/engicam/imx8mm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/engicam/imx8mm/Kconfig 2021-11-01 17:10:13.996273737 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8mm_icore_mx8mm" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/firefly/firefly-rk3288/firefly-rk3288.c u-boot/board/firefly/firefly-rk3288/firefly-rk3288.c +--- u-boot-2021.10/board/firefly/firefly-rk3288/firefly-rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/firefly/firefly-rk3288/firefly-rk3288.c 2021-11-01 17:10:13.996273737 +0100 +@@ -8,9 +8,9 @@ + #include + #include + #include ++#include + + #ifdef CONFIG_SPL_BUILD +-DECLARE_GLOBAL_DATA_PTR; + static int setup_led(void) + { + #ifdef CONFIG_SPL_LED +@@ -18,7 +18,7 @@ + char *led_name; + int ret; + +- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); ++ led_name = ofnode_conf_read_str("u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); +diff -ruN u-boot-2021.10/board/freescale/common/ics307_clk.h u-boot/board/freescale/common/ics307_clk.h +--- u-boot-2021.10/board/freescale/common/ics307_clk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/common/ics307_clk.h 2021-11-01 17:10:13.999606888 +0100 +@@ -8,7 +8,6 @@ + #ifndef __ASSEMBLY__ + + extern unsigned long get_board_sys_clk(void); +-extern unsigned long get_board_ddr_clk(void); + extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); + #endif + +diff -ruN u-boot-2021.10/board/freescale/common/Kconfig u-boot/board/freescale/common/Kconfig +--- u-boot-2021.10/board/freescale/common/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/common/Kconfig 2021-11-01 17:10:13.996273737 +0100 +@@ -24,7 +24,6 @@ + + config FSL_USE_PCA9547_MUX + bool "Enable PCA9547 I2C Mux on Freescale boards" +- default n + help + This option enables the PCA9547 I2C mux on Freescale boards. + +diff -ruN u-boot-2021.10/board/freescale/common/sys_eeprom.c u-boot/board/freescale/common/sys_eeprom.c +--- u-boot-2021.10/board/freescale/common/sys_eeprom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/common/sys_eeprom.c 2021-11-01 17:10:13.999606888 +0100 +@@ -62,7 +62,7 @@ + u8 mac_count; /* 0x40 Number of MAC addresses */ + u8 mac_flag; /* 0x41 MAC table flags */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ +- u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ ++ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ + u32 crc; /* 0xfc - 0xff CRC32 checksum */ + #endif + } e; +diff -ruN u-boot-2021.10/board/freescale/common/zm7300.c u-boot/board/freescale/common/zm7300.c +--- u-boot-2021.10/board/freescale/common/zm7300.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/common/zm7300.c 2021-11-01 17:10:13.999606888 +0100 +@@ -230,4 +230,3 @@ + } + return 0; + } +- +diff -ruN u-boot-2021.10/board/freescale/imx8mm_evk/Kconfig u-boot/board/freescale/imx8mm_evk/Kconfig +--- u-boot-2021.10/board/freescale/imx8mm_evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mm_evk/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mm_evk" + ++config IMX_CONFIG ++ default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/imx8mn_evk/ddr4_timing.c u-boot/board/freescale/imx8mn_evk/ddr4_timing.c +--- u-boot-2021.10/board/freescale/imx8mn_evk/ddr4_timing.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mn_evk/ddr4_timing.c 2021-11-01 17:10:14.002940039 +0100 +@@ -1052,4 +1052,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, + }; +- +diff -ruN u-boot-2021.10/board/freescale/imx8mn_evk/ddr4_timing_ld.c u-boot/board/freescale/imx8mn_evk/ddr4_timing_ld.c +--- u-boot-2021.10/board/freescale/imx8mn_evk/ddr4_timing_ld.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mn_evk/ddr4_timing_ld.c 2021-11-01 17:10:14.002940039 +0100 +@@ -1054,4 +1054,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 1066, }, + }; +- +diff -ruN u-boot-2021.10/board/freescale/imx8mn_evk/Kconfig u-boot/board/freescale/imx8mn_evk/Kconfig +--- u-boot-2021.10/board/freescale/imx8mn_evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mn_evk/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -11,7 +11,9 @@ + + config IMX8MN_LOW_DRIVE_MODE + bool "Enable the low drive mode of iMX8MN on EVK board" +- default n ++ ++config IMX_CONFIG ++ default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" + + source "board/freescale/common/Kconfig" + +diff -ruN u-boot-2021.10/board/freescale/imx8mp_evk/Kconfig u-boot/board/freescale/imx8mp_evk/Kconfig +--- u-boot-2021.10/board/freescale/imx8mp_evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mp_evk/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8mp_evk" + ++config IMX_CONFIG ++ default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/freescale/imx8mp_evk/spl.c u-boot/board/freescale/imx8mp_evk/spl.c +--- u-boot-2021.10/board/freescale/imx8mp_evk/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mp_evk/spl.c 2021-11-01 17:10:14.002940039 +0100 +@@ -63,7 +63,7 @@ + }, + }; + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + #define I2C_PMIC 0 + int power_init_board(void) + { +diff -ruN u-boot-2021.10/board/freescale/imx8mq_evk/Kconfig u-boot/board/freescale/imx8mq_evk/Kconfig +--- u-boot-2021.10/board/freescale/imx8mq_evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mq_evk/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mq_evk" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/imx8mq_evk/spl.c u-boot/board/freescale/imx8mq_evk/spl.c +--- u-boot-2021.10/board/freescale/imx8mq_evk/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8mq_evk/spl.c 2021-11-01 17:10:14.002940039 +0100 +@@ -156,7 +156,7 @@ + return 0; + } + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + #define I2C_PMIC 0 + int power_init_board(void) + { +diff -ruN u-boot-2021.10/board/freescale/imx8qm_mek/Kconfig u-boot/board/freescale/imx8qm_mek/Kconfig +--- u-boot-2021.10/board/freescale/imx8qm_mek/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8qm_mek/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8qm_mek" + ++config IMX_CONFIG ++ default "board/freescale/imx8qm_mek/imximage.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/freescale/imx8qxp_mek/Kconfig u-boot/board/freescale/imx8qxp_mek/Kconfig +--- u-boot-2021.10/board/freescale/imx8qxp_mek/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imx8qxp_mek/Kconfig 2021-11-01 17:10:14.002940039 +0100 +@@ -9,6 +9,9 @@ + config SYS_CONFIG_NAME + default "imx8qxp_mek" + ++config IMX_CONFIG ++ default "board/freescale/imx8qxp_mek/imximage.cfg" ++ + source "board/freescale/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/freescale/imxrt1020-evk/imxrt1020-evk.c u-boot/board/freescale/imxrt1020-evk/imxrt1020-evk.c +--- u-boot-2021.10/board/freescale/imxrt1020-evk/imxrt1020-evk.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imxrt1020-evk/imxrt1020-evk.c 2021-11-01 17:10:14.006273190 +0100 +@@ -71,11 +71,6 @@ + } + #endif + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/freescale/imxrt1050-evk/imxrt1050-evk.c u-boot/board/freescale/imxrt1050-evk/imxrt1050-evk.c +--- u-boot-2021.10/board/freescale/imxrt1050-evk/imxrt1050-evk.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/imxrt1050-evk/imxrt1050-evk.c 2021-11-01 17:10:14.006273190 +0100 +@@ -71,11 +71,6 @@ + } + #endif + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/freescale/ls1012afrdm/README u-boot/board/freescale/ls1012afrdm/README +--- u-boot-2021.10/board/freescale/ls1012afrdm/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012afrdm/README 2021-11-01 17:10:14.006273190 +0100 +@@ -52,7 +52,7 @@ + Images | Size |QSPI Flash Address + ------------------------------------------ + RCW + PBI | 1MB | 0x4000_0000 +-U-boot | 1MB | 0x4010_0000 +-U-boot Env | 1MB | 0x4020_0000 ++U-boot | 1MB | 0x4010_0000 ++U-boot Env | 1MB | 0x4020_0000 + PPA FIT image | 2MB | 0x4050_0000 + Linux ITB | ~53MB | 0x40A0_0000 +diff -ruN u-boot-2021.10/board/freescale/ls1012aqds/eth.c u-boot/board/freescale/ls1012aqds/eth.c +--- u-boot-2021.10/board/freescale/ls1012aqds/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012aqds/eth.c 2021-11-01 17:10:14.006273190 +0100 +@@ -244,7 +244,7 @@ + bus = miiphy_get_dev_by_name(mdio_name); + pfe_set_mdio(1, bus); + pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, +- PHY_INTERFACE_MODE_SGMII_2500); ++ PHY_INTERFACE_MODE_2500BASEX); + + data8 = QIXIS_READ(brdcfg[12]); + data8 |= 0x20; +@@ -263,7 +263,7 @@ + pfe_set_mdio(0, bus); + pfe_set_phy_address_mode(0, + CONFIG_PFE_SGMII_2500_PHY1_ADDR, +- PHY_INTERFACE_MODE_SGMII_2500); ++ PHY_INTERFACE_MODE_2500BASEX); + } + break; + +diff -ruN u-boot-2021.10/board/freescale/ls1012aqds/ls1012aqds.c u-boot/board/freescale/ls1012aqds/ls1012aqds.c +--- u-boot-2021.10/board/freescale/ls1012aqds/ls1012aqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012aqds/ls1012aqds.c 2021-11-01 17:10:14.006273190 +0100 +@@ -265,7 +265,7 @@ + ETH_1_2_5G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_2_5G_MDIO_PHY_MASK); +- prop_val.phy_mode = "sgmii-2500"; ++ prop_val.phy_mode = "2500base-x"; + pfe_set_properties(l_blob, prop_val, ETH_1_PATH, + ETH_1_MDIO); + } else { +@@ -277,7 +277,7 @@ + ETH_2_2_5G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_2_5G_MDIO_PHY_MASK); +- prop_val.phy_mode = "sgmii-2500"; ++ prop_val.phy_mode = "2500base-x"; + pfe_set_properties(l_blob, prop_val, ETH_2_PATH, + ETH_2_MDIO); + } +diff -ruN u-boot-2021.10/board/freescale/ls1012aqds/ls1012aqds_pfe.h u-boot/board/freescale/ls1012aqds/ls1012aqds_pfe.h +--- u-boot-2021.10/board/freescale/ls1012aqds/ls1012aqds_pfe.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012aqds/ls1012aqds_pfe.h 2021-11-01 17:10:14.006273190 +0100 +@@ -17,7 +17,7 @@ + #define ETH_1_2_5G_PHY_ID 0x1 + #define ETH_1_2_5G_MDIO_MUX 0x2 + #define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 +-#define ETH_2_5G_PHY_MODE "sgmii-2500" ++#define ETH_2_5G_PHY_MODE "2500base-x" + #define ETH_2_2_5G_BUS_ID 0x1 + #define ETH_2_2_5G_PHY_ID 0x2 + #define ETH_2_2_5G_MDIO_MUX 0x3 +diff -ruN u-boot-2021.10/board/freescale/ls1012aqds/README u-boot/board/freescale/ls1012aqds/README +--- u-boot-2021.10/board/freescale/ls1012aqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012aqds/README 2021-11-01 17:10:14.006273190 +0100 +@@ -53,7 +53,7 @@ + Images | Size |QSPI Flash Address + ------------------------------------------ + RCW + PBI | 1MB | 0x4000_0000 +-U-boot | 1MB | 0x4010_0000 +-U-boot Env | 1MB | 0x4020_0000 ++U-boot | 1MB | 0x4010_0000 ++U-boot Env | 1MB | 0x4020_0000 + PPA FIT image | 2MB | 0x4050_0000 + Linux ITB | ~53MB | 0x40A0_0000 +diff -ruN u-boot-2021.10/board/freescale/ls1012ardb/eth.c u-boot/board/freescale/ls1012ardb/eth.c +--- u-boot-2021.10/board/freescale/ls1012ardb/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012ardb/eth.c 2021-11-01 17:10:14.006273190 +0100 +@@ -121,12 +121,12 @@ + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, +- PHY_INTERFACE_MODE_SGMII_2500); ++ PHY_INTERFACE_MODE_2500BASEX); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, +- PHY_INTERFACE_MODE_SGMII_2500); ++ PHY_INTERFACE_MODE_2500BASEX); + } + break; + default: +diff -ruN u-boot-2021.10/board/freescale/ls1012ardb/README u-boot/board/freescale/ls1012ardb/README +--- u-boot-2021.10/board/freescale/ls1012ardb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1012ardb/README 2021-11-01 17:10:14.006273190 +0100 +@@ -48,8 +48,8 @@ + Images | Size |QSPI Flash Address + ------------------------------------------ + RCW + PBI | 1MB | 0x4000_0000 +-U-boot | 1MB | 0x4010_0000 +-U-boot Env | 1MB | 0x4020_0000 ++U-boot | 1MB | 0x4010_0000 ++U-boot Env | 1MB | 0x4020_0000 + PPA FIT image | 2MB | 0x4050_0000 + Linux ITB | ~53MB | 0x40A0_0000 + +@@ -90,8 +90,8 @@ + Images | Size |QSPI Flash Address + ------------------------------------------ + RCW + PBI | 1MB | 0x4000_0000 +-U-boot | 1MB | 0x4010_0000 +-U-boot Env | 1MB | 0x4030_0000 ++U-boot | 1MB | 0x4010_0000 ++U-boot Env | 1MB | 0x4030_0000 + PPA FIT image | 2MB | 0x4040_0000 + PFE firmware | 20K | 0x00a0_0000 + Linux ITB | ~53MB | 0x4100_0000 +diff -ruN u-boot-2021.10/board/freescale/ls1021aqds/ls1021aqds.c u-boot/board/freescale/ls1021aqds/ls1021aqds.c +--- u-boot-2021.10/board/freescale/ls1021aqds/ls1021aqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1021aqds/ls1021aqds.c 2021-11-01 17:10:14.006273190 +0100 +@@ -127,6 +127,7 @@ + return 66666666; + } + ++#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ + unsigned long get_board_ddr_clk(void) + { + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +@@ -141,6 +142,7 @@ + } + return 66666666; + } ++#endif + + int dram_init(void) + { +diff -ruN u-boot-2021.10/board/freescale/ls1021aqds/README u-boot/board/freescale/ls1021aqds/README +--- u-boot-2021.10/board/freescale/ls1021aqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1021aqds/README 2021-11-01 17:10:14.006273190 +0100 +@@ -113,6 +113,5 @@ + + LS1021a rev1.0 Soc specific Options/Settings + -------------------------------------------- +-If the LS1021a Soc is rev1.0, you need modify the configure file. +-Add the following define in include/configs/ls1021aqds.h: +-#define CONFIG_SKIP_LOWLEVEL_INIT ++If the LS1021a Soc is rev1.0, you need modify the configuration and enable ++CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. +diff -ruN u-boot-2021.10/board/freescale/ls1021atsn/ls1021atsn.c u-boot/board/freescale/ls1021atsn/ls1021atsn.c +--- u-boot-2021.10/board/freescale/ls1021atsn/ls1021atsn.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1021atsn/ls1021atsn.c 2021-11-01 17:10:14.006273190 +0100 +@@ -1,5 +1,5 @@ + // SPDX-License-Identifier: GPL-2.0 +-/* Copyright 2016-2019 NXP Semiconductors ++/* Copyright 2016-2019 NXP + */ + #include + #include +diff -ruN u-boot-2021.10/board/freescale/ls1021atwr/README u-boot/board/freescale/ls1021atwr/README +--- u-boot-2021.10/board/freescale/ls1021atwr/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1021atwr/README 2021-11-01 17:10:14.006273190 +0100 +@@ -110,6 +110,5 @@ + + LS1021a rev1.0 Soc specific Options/Settings + -------------------------------------------- +-If the LS1021a Soc is rev1.0, you need modify the configure file. +-Add the following define in include/configs/ls1021atwr.h: +-#define CONFIG_SKIP_LOWLEVEL_INIT ++If the LS1021a Soc is rev1.0, you need modify the configuration and enable ++CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. +diff -ruN u-boot-2021.10/board/freescale/ls1028a/Kconfig u-boot/board/freescale/ls1028a/Kconfig +--- u-boot-2021.10/board/freescale/ls1028a/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1028a/Kconfig 2021-11-01 17:10:14.006273190 +0100 +@@ -14,7 +14,6 @@ + + config EMMC_BOOT + bool "Support for booting from EMMC" +- default n + + config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT +@@ -53,7 +52,6 @@ + + config EMMC_BOOT + bool "Support for booting from EMMC" +- default n + + config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT +diff -ruN u-boot-2021.10/board/freescale/ls1028a/ls1028a.c u-boot/board/freescale/ls1028a/ls1028a.c +--- u-boot-2021.10/board/freescale/ls1028a/ls1028a.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1028a/ls1028a.c 2021-11-01 17:10:14.006273190 +0100 +@@ -137,7 +137,7 @@ + u8 uart; + #endif + +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) + i2c_early_init_f(); + #endif + +diff -ruN u-boot-2021.10/board/freescale/ls1043aqds/eth.c u-boot/board/freescale/ls1043aqds/eth.c +--- u-boot-2021.10/board/freescale/ls1043aqds/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043aqds/eth.c 2021-11-01 17:10:14.009606341 +0100 +@@ -176,7 +176,7 @@ + "sgmii-riser-s4-p1"); + } + } else if (fm_info_get_enet_if(port) == +- PHY_INTERFACE_MODE_SGMII_2500) { ++ PHY_INTERFACE_MODE_2500BASEX) { + /* 2.5G SGMII interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); +@@ -187,7 +187,7 @@ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", +- "sgmii-2500"); ++ "2500base-x"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (mdio_mux[port]) { + case EMI1_SLOT1: +@@ -242,13 +242,13 @@ + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + port == FM1_10GEC1) { +- /* XFI interface */ ++ /* 10GBase-R interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; +- /* no PHY for XFI */ ++ /* no PHY for 10GBase-R */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); +@@ -430,12 +430,12 @@ + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); +- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { ++ } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { +diff -ruN u-boot-2021.10/board/freescale/ls1043aqds/ls1043aqds.c u-boot/board/freescale/ls1043aqds/ls1043aqds.c +--- u-boot-2021.10/board/freescale/ls1043aqds/ls1043aqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043aqds/ls1043aqds.c 2021-11-01 17:10:14.009606341 +0100 +@@ -52,10 +52,6 @@ + #define CFG_UART_MUX_SHIFT 1 + #define CFG_LPUART_EN 0x1 + +-#ifdef CONFIG_SYS_I2C_EARLY_INIT +-void i2c_early_init_f(void); +-#endif +- + #ifdef CONFIG_TFABOOT + struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { +@@ -447,7 +443,7 @@ + */ + out_le32(cntcr, 0x1); + +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); + #endif + fsl_lsch2_early_init_f(); +diff -ruN u-boot-2021.10/board/freescale/ls1043aqds/README u-boot/board/freescale/ls1043aqds/README +--- u-boot-2021.10/board/freescale/ls1043aqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043aqds/README 2021-11-01 17:10:14.006273190 +0100 +@@ -18,7 +18,7 @@ + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 +- - XFI ++ - 10GBase-R + - DDR Controller + - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus +diff -ruN u-boot-2021.10/board/freescale/ls1043ardb/eth.c u-boot/board/freescale/ls1043ardb/eth.c +--- u-boot-2021.10/board/freescale/ls1043ardb/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043ardb/eth.c 2021-11-01 17:10:14.009606341 +0100 +@@ -65,7 +65,7 @@ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + +- /* XFI on lane A, MAC 9 */ ++ /* 10GBase-R on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); +diff -ruN u-boot-2021.10/board/freescale/ls1043ardb/Kconfig u-boot/board/freescale/ls1043ardb/Kconfig +--- u-boot-2021.10/board/freescale/ls1043ardb/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043ardb/Kconfig 2021-11-01 17:10:14.009606341 +0100 +@@ -16,7 +16,6 @@ + config SYS_HAS_ARMV8_SECURE_BASE + bool "Enable secure address for PSCI image" + depends on ARMV8_PSCI +- default n + help + PSCI image can be re-located to secure RAM. + If enabled, please also define the value for ARMV8_SECURE_BASE, +diff -ruN u-boot-2021.10/board/freescale/ls1043ardb/README u-boot/board/freescale/ls1043ardb/README +--- u-boot-2021.10/board/freescale/ls1043ardb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1043ardb/README 2021-11-01 17:10:14.009606341 +0100 +@@ -17,7 +17,7 @@ + - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and + standard PCIe card + - QSGMII with x4 RJ45 connector +- - XFI with x1 RJ45 connector ++ - 10GBase-R with x1 RJ45 connector + - DDR Controller + - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus +diff -ruN u-boot-2021.10/board/freescale/ls1046afrwy/README u-boot/board/freescale/ls1046afrwy/README +--- u-boot-2021.10/board/freescale/ls1046afrwy/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046afrwy/README 2021-11-01 17:10:14.009606341 +0100 +@@ -42,8 +42,8 @@ + Start Address End Address Description Size + 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB + 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB ++0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB ++0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB + 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB + 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB + 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +diff -ruN u-boot-2021.10/board/freescale/ls1046aqds/eth.c u-boot/board/freescale/ls1046aqds/eth.c +--- u-boot-2021.10/board/freescale/ls1046aqds/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046aqds/eth.c 2021-11-01 17:10:14.009606341 +0100 +@@ -178,7 +178,7 @@ + default: + break; + } +- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { ++ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { + /* 2.5G SGMII interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); +@@ -189,7 +189,7 @@ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", +- "sgmii-2500"); ++ "2500base-x"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (port) { + case FM1_DTSEC1: +@@ -217,13 +217,13 @@ + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", port); + } else { +- /* XFI interface */ ++ /* 10GBase-R interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; +- /* no PHY for XFI */ ++ /* no PHY for 10GBase-R */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); +diff -ruN u-boot-2021.10/board/freescale/ls1046aqds/ls1046aqds.c u-boot/board/freescale/ls1046aqds/ls1046aqds.c +--- u-boot-2021.10/board/freescale/ls1046aqds/ls1046aqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046aqds/ls1046aqds.c 2021-11-01 17:10:14.009606341 +0100 +@@ -37,10 +37,6 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-#ifdef CONFIG_SYS_I2C_EARLY_INIT +-void i2c_early_init_f(void); +-#endif +- + #ifdef CONFIG_TFABOOT + struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { +@@ -318,7 +314,7 @@ + */ + out_le32(cntcr, 0x1); + +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); + #endif + fsl_lsch2_early_init_f(); +diff -ruN u-boot-2021.10/board/freescale/ls1046aqds/README u-boot/board/freescale/ls1046aqds/README +--- u-boot-2021.10/board/freescale/ls1046aqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046aqds/README 2021-11-01 17:10:14.009606341 +0100 +@@ -18,7 +18,7 @@ + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 +- - XFI ++ - 10GBase-R + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus +@@ -47,8 +47,8 @@ + Start Address End Address Description Size + 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB + 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB ++0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB ++0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB + 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB + 0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB + 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +diff -ruN u-boot-2021.10/board/freescale/ls1046ardb/eth.c u-boot/board/freescale/ls1046ardb/eth.c +--- u-boot-2021.10/board/freescale/ls1046ardb/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046ardb/eth.c 2021-11-01 17:10:14.009606341 +0100 +@@ -67,7 +67,7 @@ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + +- /* XFI on lane A, MAC 9 */ ++ /* 10GBase-R on lane A, MAC 9 */ + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); + +diff -ruN u-boot-2021.10/board/freescale/ls1046ardb/README u-boot/board/freescale/ls1046ardb/README +--- u-boot-2021.10/board/freescale/ls1046ardb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1046ardb/README 2021-11-01 17:10:14.009606341 +0100 +@@ -14,8 +14,8 @@ + LS1046ARDB board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: +- - Lane0: XFI with x1 RJ45 connector +- - Lane1: XFI Cage ++ - Lane0: 10GBase-R with x1 RJ45 connector ++ - Lane1: 10GBase-R Cage + - Lane2: SGMII.5 + - Lane3: SGMII.6 + - SERDES2 Connections, 4 lanes supporting: +@@ -43,8 +43,8 @@ + Start Address End Address Description Size + 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB + 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB ++0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB ++0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB + 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB + 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB + 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +@@ -59,7 +59,7 @@ + QSPI flash map: + Start Address End Address Description Size + 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB +-0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB ++0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB + 0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB + 0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB + 0x00_4060_0000 - 0x00_408F_FFFF Secure boot header +diff -ruN u-boot-2021.10/board/freescale/ls1088a/ddr.c u-boot/board/freescale/ls1088a/ddr.c +--- u-boot-2021.10/board/freescale/ls1088a/ddr.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1088a/ddr.c 2021-11-01 17:10:14.009606341 +0100 +@@ -88,8 +88,6 @@ + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + +- +- + popts->half_strength_driver_enable = 0; + /* + * Write leveling override +diff -ruN u-boot-2021.10/board/freescale/ls1088a/eth_ls1088ardb.c u-boot/board/freescale/ls1088a/eth_ls1088ardb.c +--- u-boot-2021.10/board/freescale/ls1088a/eth_ls1088ardb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1088a/eth_ls1088ardb.c 2021-11-01 17:10:14.009606341 +0100 +@@ -52,9 +52,9 @@ + switch (srds_s1) { + case 0x1D: + /* +- * XFI does not need a PHY to work, but to avoid U-boot use +- * default PHY address which is zero to a MAC when it found +- * a MAC has no PHY address, we give a PHY address to XFI ++ * 10GBase-R does not need a PHY to work, but to avoid U-boot ++ * use default PHY address which is zero to a MAC when it found ++ * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC error. + */ + wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); +diff -ruN u-boot-2021.10/board/freescale/ls1088a/README u-boot/board/freescale/ls1088a/README +--- u-boot-2021.10/board/freescale/ls1088a/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls1088a/README 2021-11-01 17:10:14.009606341 +0100 +@@ -42,7 +42,7 @@ + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 +- - XFI ++ - 10GBase-R + - QSGMII + - DDR Controller + - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four +@@ -106,7 +106,7 @@ + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 +- - 2 XFI ++ - 2 10GBase-R + - QSGMII, SGMII with help for Riser card + - 2 RGMII + - 5 slot for Riser card or PCIe NIC +diff -ruN u-boot-2021.10/board/freescale/ls2080aqds/eth.c u-boot/board/freescale/ls2080aqds/eth.c +--- u-boot-2021.10/board/freescale/ls2080aqds/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls2080aqds/eth.c 2021-11-01 17:10:14.012939492 +0100 +@@ -874,13 +874,12 @@ + case 0x4B: + case 0x4C: + /* +- * XFI does not need a PHY to work, but to avoid U-Boot use +- * default PHY address which is zero to a MAC when it found +- * a MAC has no PHY address, we give a PHY address to XFI +- * MAC, and should not use a real XAUI PHY address, since +- * MDIO can access it successfully, and then MDIO thinks +- * the XAUI card is used for the XFI MAC, which will cause +- * error. ++ * 10GBase-R does not need a PHY to work, but to avoid U-Boot ++ * use default PHY address which is zero to a MAC when it found ++ * a MAC has no PHY address, we give a PHY address to 10GBase-R ++ * MAC, and should not use a real XAUI PHY address, since MDIO ++ * can access it successfully, and then MDIO thinks the XAUI ++ * card is used for the 10GBase-R MAC, which will cause error. + */ + wriop_set_phy_address(i, 0, i + 4); + ls2080a_qds_enable_SFP_TX(SFP_TX); +diff -ruN u-boot-2021.10/board/freescale/ls2080aqds/ls2080aqds.c u-boot/board/freescale/ls2080aqds/ls2080aqds.c +--- u-boot-2021.10/board/freescale/ls2080aqds/ls2080aqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls2080aqds/ls2080aqds.c 2021-11-01 17:10:14.012939492 +0100 +@@ -241,7 +241,7 @@ + + int board_early_init_f(void) + { +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); + #endif + fsl_lsch3_early_init_f(); +diff -ruN u-boot-2021.10/board/freescale/ls2080aqds/README u-boot/board/freescale/ls2080aqds/README +--- u-boot-2021.10/board/freescale/ls2080aqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls2080aqds/README 2021-11-01 17:10:14.009606341 +0100 +@@ -19,7 +19,7 @@ + - QSGMII + - SATA 3.0 + - XAUI +- - XFI ++ - 10GBase-R + - DDR Controller + - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four + chip-selects and two DIMM connectors. Support is up to 2133MT/s. +@@ -213,4 +213,3 @@ + DPMAC14 -> PHY4-P1 + DPMAC15 -> PHY4-P2 + DPMAC16 -> PHY4-P3 +- +diff -ruN u-boot-2021.10/board/freescale/ls2080ardb/ls2080ardb.c u-boot/board/freescale/ls2080ardb/ls2080ardb.c +--- u-boot-2021.10/board/freescale/ls2080ardb/ls2080ardb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls2080ardb/ls2080ardb.c 2021-11-01 17:10:14.012939492 +0100 +@@ -314,7 +314,7 @@ + + int board_early_init_f(void) + { +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); + #endif + fsl_lsch3_early_init_f(); +diff -ruN u-boot-2021.10/board/freescale/ls2080ardb/README u-boot/board/freescale/ls2080ardb/README +--- u-boot-2021.10/board/freescale/ls2080ardb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/ls2080ardb/README 2021-11-01 17:10:14.012939492 +0100 +@@ -18,7 +18,7 @@ + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 +- - XFI ++ - 10GBase-R + - DDR Controller + - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four + chip-selects and two DIMM connectors. Support is up to 2133MT/s. +@@ -132,4 +132,3 @@ + => setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' +- +diff -ruN u-boot-2021.10/board/freescale/lx2160a/lx2160a.c u-boot/board/freescale/lx2160a/lx2160a.c +--- u-boot-2021.10/board/freescale/lx2160a/lx2160a.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/lx2160a/lx2160a.c 2021-11-01 17:10:14.012939492 +0100 +@@ -89,7 +89,7 @@ + + int board_early_init_f(void) + { +-#ifdef CONFIG_SYS_I2C_EARLY_INIT ++#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) + i2c_early_init_f(); + #endif + /* get required clock for UART IP */ +diff -ruN u-boot-2021.10/board/freescale/m53017evb/README u-boot/board/freescale/m53017evb/README +--- u-boot-2021.10/board/freescale/m53017evb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/m53017evb/README 2021-11-01 17:10:14.016272643 +0100 +@@ -98,7 +98,7 @@ + + CONFIG_SYS_MBAR -- define MBAR offset + +-CONFIG_MONITOR_IS_IN_RAM -- Not support ++CONFIG_MONITOR_IS_IN_RAM -- Not support + + CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM + +diff -ruN u-boot-2021.10/board/freescale/m5329evb/nand.c u-boot/board/freescale/m5329evb/nand.c +--- u-boot-2021.10/board/freescale/m5329evb/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/m5329evb/nand.c 2021-11-01 17:10:14.016272643 +0100 +@@ -15,6 +15,7 @@ + #if defined(CONFIG_CMD_NAND) + #include + #include ++#include + + #define SET_CLE 0x10 + #define SET_ALE 0x08 +diff -ruN u-boot-2021.10/board/freescale/m5373evb/nand.c u-boot/board/freescale/m5373evb/nand.c +--- u-boot-2021.10/board/freescale/m5373evb/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/m5373evb/nand.c 2021-11-01 17:10:14.016272643 +0100 +@@ -15,6 +15,7 @@ + #if defined(CONFIG_CMD_NAND) + #include + #include ++#include + + #define SET_CLE 0x10 + #define SET_ALE 0x08 +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/ddr.c u-boot/board/freescale/mpc8349emds/ddr.c +--- u-boot-2021.10/board/freescale/mpc8349emds/ddr.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/ddr.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,100 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- */ +- +-#include +- +-#include +-#include +- +-struct board_specific_parameters { +- u32 n_ranks; +- u32 datarate_mhz_high; +- u32 clk_adjust; +- u32 cpo; +- u32 write_data_delay; +- u32 force_2t; +-}; +- +-/* +- * This table contains all valid speeds we want to override with board +- * specific parameters. datarate_mhz_high values need to be in ascending order +- * for each n_ranks group. +- */ +-static const struct board_specific_parameters udimm0[] = { +- /* +- * memory controller 0 +- * num| hi| clk| cpo|wrdata|2T +- * ranks| mhz|adjst| | delay| +- */ +- {2, 300, 4, 4, 2, 0}, +- {2, 365, 4, 6, 2, 0}, +- {2, 450, 4, 7, 2, 0}, +- {2, 850, 4, 31, 2, 0}, +- {1, 300, 4, 4, 2, 0}, +- {1, 365, 4, 6, 2, 0}, +- {1, 450, 4, 7, 2, 0}, +- {1, 850, 4, 31, 2, 0}, +- {} +-}; +- +-void fsl_ddr_board_options(memctl_options_t *popts, +- dimm_params_t *pdimm, +- unsigned int ctrl_num) +-{ +- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; +- unsigned int i; +- ulong ddr_freq; +- +- if (ctrl_num != 0) /* we have only one controller */ +- return; +- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { +- if (pdimm[i].n_ranks) +- break; +- } +- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ +- return; +- +- pbsp = udimm0; +- +- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr +- * freqency and n_banks specified in board_specific_parameters table. +- */ +- ddr_freq = get_ddr_freq(0) / 1000000; +- while (pbsp->datarate_mhz_high) { +- if (pbsp->n_ranks == pdimm[i].n_ranks) { +- if (ddr_freq <= pbsp->datarate_mhz_high) { +- popts->clk_adjust = pbsp->clk_adjust; +- popts->cpo_override = pbsp->cpo; +- popts->write_data_delay = +- pbsp->write_data_delay; +- popts->twot_en = pbsp->force_2t; +- goto found; +- } +- pbsp_highest = pbsp; +- } +- pbsp++; +- } +- +- if (pbsp_highest) { +- printf("Error: board specific timing not found " +- "for data rate %lu MT/s!\n" +- "Trying to use the highest speed (%u) parameters\n", +- ddr_freq, pbsp_highest->datarate_mhz_high); +- popts->clk_adjust = pbsp_highest->clk_adjust; +- popts->cpo_override = pbsp_highest->cpo; +- popts->write_data_delay = pbsp_highest->write_data_delay; +- popts->twot_en = pbsp_highest->force_2t; +- } else { +- panic("DIMM is not supported by this board"); +- } +- +-found: +- /* +- * Factors to consider for half-strength driver enable: +- * - number of DIMMs installed +- */ +- popts->half_strength_driver_enable = 0; +- popts->dqs_config = 0; /* only true DQS signal is used on board */ +-} +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/Kconfig u-boot/board/freescale/mpc8349emds/Kconfig +--- u-boot-2021.10/board/freescale/mpc8349emds/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,25 +0,0 @@ +-if TARGET_MPC8349EMDS +- +-config SYS_BOARD +- default "mpc8349emds" +- +-config SYS_VENDOR +- default "freescale" +- +-config SYS_CONFIG_NAME +- default "MPC8349EMDS" +- +-endif +- +-if TARGET_MPC8349EMDS_SDRAM +- +-config SYS_BOARD +- default "mpc8349emds" +- +-config SYS_VENDOR +- default "freescale" +- +-config SYS_CONFIG_NAME +- default "MPC8349EMDS_SDRAM" +- +-endif +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/MAINTAINERS u-boot/board/freescale/mpc8349emds/MAINTAINERS +--- u-boot-2021.10/board/freescale/mpc8349emds/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 +@@ -1,9 +0,0 @@ +-MPC8349EMDS BOARD +-#M: Kim Phillips +-S: Orphan (since 2018-05) +-F: board/freescale/mpc8349emds/ +-F: include/configs/MPC8349EMDS.h +-F: configs/MPC8349EMDS_defconfig +-F: configs/MPC8349EMDS_SDRAM_defconfig +-F: configs/MPC8349EMDS_PCI64_defconfig +-F: configs/MPC8349EMDS_SLAVE_defconfig +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/Makefile u-boot/board/freescale/mpc8349emds/Makefile +--- u-boot-2021.10/board/freescale/mpc8349emds/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2006 +-# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- +-obj-y += mpc8349emds.o +-obj-$(CONFIG_PCI) += pci.o +-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/mpc8349emds.c u-boot/board/freescale/mpc8349emds/mpc8349emds.c +--- u-boot-2021.10/board/freescale/mpc8349emds/mpc8349emds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/mpc8349emds.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,302 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2006 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#ifdef CONFIG_SYS_FSL_DDR2 +-#include +-#else +-#include +-#endif +-#include +- +-#if defined(CONFIG_OF_LIBFDT) +-#include +-#endif +- +-DECLARE_GLOBAL_DATA_PTR; +- +-int fixed_sdram(void); +-void sdram_init(void); +- +-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) +-void ddr_enable_ecc(unsigned int dram_size); +-#endif +- +-int board_early_init_f (void) +-{ +- volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; +- +- /* Enable flash write */ +- bcsr[1] &= ~0x01; +- +-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY +- /* Use USB PHY on SYS board */ +- bcsr[5] |= 0x02; +-#endif +- +- return 0; +-} +- +-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) +- +-int dram_init(void) +-{ +- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; +- phys_size_t msize = 0; +- +- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) +- return -ENXIO; +- +- /* DDR SDRAM - Main SODIMM */ +- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; +-#if defined(CONFIG_SPD_EEPROM) +-#ifndef CONFIG_SYS_FSL_DDR2 +- msize = spd_sdram() * 1024 * 1024; +-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +- ddr_enable_ecc(msize); +-#endif +-#else +- msize = fsl_ddr_sdram(); +-#endif +-#else +- msize = fixed_sdram() * 1024 * 1024; +-#endif +- /* +- * Initialize SDRAM if it is on local bus. +- */ +- sdram_init(); +- +- /* set total bus SDRAM size(bytes) -- DDR */ +- gd->ram_size = msize; +- +- return 0; +-} +- +-#if !defined(CONFIG_SPD_EEPROM) +-/************************************************************************* +- * fixed sdram init -- doesn't use serial presence detect. +- ************************************************************************/ +-int fixed_sdram(void) +-{ +- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; +- u32 msize = CONFIG_SYS_DDR_SIZE; +- u32 ddr_size = msize << 20; /* DDR size in bytes */ +- u32 ddr_size_log2 = __ilog2(ddr_size); +- +- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; +- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +- +-#if (CONFIG_SYS_DDR_SIZE != 256) +-#warning Currenly any ddr size other than 256 is not supported +-#endif +-#ifdef CONFIG_DDR_II +- im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; +- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; +- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; +- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; +- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; +- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; +- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; +- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; +- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; +- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; +- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; +- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; +-#else +- +-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) +-#warning Chip select bounds is only configurable in 16MB increments +-#endif +- im->ddr.csbnds[2].csbnds = +- ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | +- (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> +- CSBNDS_EA_SHIFT) & CSBNDS_EA); +- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; +- +- /* currently we use only one CS, so disable the other banks */ +- im->ddr.cs_config[0] = 0; +- im->ddr.cs_config[1] = 0; +- im->ddr.cs_config[3] = 0; +- +- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; +- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; +- +- im->ddr.sdram_cfg = +- SDRAM_CFG_SREN +-#if defined(CONFIG_DDR_2T_TIMING) +- | SDRAM_CFG_2T_EN +-#endif +- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; +-#if defined (CONFIG_DDR_32BIT) +- /* for 32-bit mode burst length is 8 */ +- im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +-#endif +- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; +- +- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; +-#endif +- udelay(200); +- +- /* enable DDR controller */ +- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; +- return msize; +-} +-#endif/*!CONFIG_SYS_SPD_EEPROM*/ +- +- +-int checkboard (void) +-{ +- /* +- * Warning: do not read the BCSR registers here +- * +- * There is a timing bug in the 8349E and 8349EA BCSR code +- * version 1.2 (read from BCSR 11) that will cause the CFI +- * flash initialization code to overwrite BCSR 0, disabling +- * the serial ports and gigabit ethernet +- */ +- +- puts("Board: Freescale MPC8349EMDS\n"); +- return 0; +-} +- +-/* +- * if MPC8349EMDS is soldered with SDRAM +- */ +-#if defined(CONFIG_SYS_BR2_PRELIM) \ +- && defined(CONFIG_SYS_OR2_PRELIM) \ +- && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ +- && defined(CONFIG_SYS_LBLAWAR2_PRELIM) +-/* +- * Initialize SDRAM memory on the Local Bus. +- */ +- +-void sdram_init(void) +-{ +- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; +- volatile fsl_lbc_t *lbc = &immap->im_lbc; +- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; +- const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | +- LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | +- LSDMR_WRC3 | LSDMR_CL3; +- /* +- * Setup SDRAM Base and Option Registers, already done in cpu_init.c +- */ +- +- /* setup mtrpt, lsrt and lbcr for LB bus */ +- lbc->lbcr = 0x00000000; +- /* LB refresh timer prescal, 266MHz/32 */ +- lbc->mrtpr = 0x20000000; +- /* LB sdram refresh timer, about 6us */ +- lbc->lsrt = 0x32000000; +- asm("sync"); +- +- /* +- * Configure the SDRAM controller Machine Mode Register. +- */ +- +- /* 0x40636733; normal operation */ +- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; +- +- /* 0x68636733; precharge all the banks */ +- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; +- asm("sync"); +- *sdram_addr = 0xff; +- udelay(100); +- +- /* 0x48636733; auto refresh */ +- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; +- asm("sync"); +- /*1 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*2 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*3 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*4 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*5 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*6 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*7 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- /*8 times*/ +- *sdram_addr = 0xff; +- udelay(100); +- +- /* 0x58636733; mode register write operation */ +- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; +- asm("sync"); +- *sdram_addr = 0xff; +- udelay(100); +- +- /* 0x40636733; normal operation */ +- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; +- asm("sync"); +- *sdram_addr = 0xff; +- udelay(100); +-} +-#else +-void sdram_init(void) +-{ +-} +-#endif +- +-/* +- * The following are used to control the SPI chip selects for the SPI command. +- */ +-#ifdef CONFIG_MPC8XXX_SPI +- +-#define SPI_CS_MASK 0x80000000 +- +-int spi_cs_is_valid(unsigned int bus, unsigned int cs) +-{ +- return bus == 0 && cs == 0; +-} +- +-void spi_cs_activate(struct spi_slave *slave) +-{ +- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; +- +- iopd->dat &= ~SPI_CS_MASK; +-} +- +-void spi_cs_deactivate(struct spi_slave *slave) +-{ +- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; +- +- iopd->dat |= SPI_CS_MASK; +-} +-#endif +- +-#if defined(CONFIG_OF_BOARD_SETUP) +-int ft_board_setup(void *blob, struct bd_info *bd) +-{ +- ft_cpu_setup(blob, bd); +-#ifdef CONFIG_PCI +- ft_pci_setup(blob, bd); +-#endif +- +- return 0; +-} +-#endif +diff -ruN u-boot-2021.10/board/freescale/mpc8349emds/pci.c u-boot/board/freescale/mpc8349emds/pci.c +--- u-boot-2021.10/board/freescale/mpc8349emds/pci.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mpc8349emds/pci.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,118 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-static struct pci_region pci1_regions[] = { +- { +- bus_start: CONFIG_SYS_PCI1_MEM_BASE, +- phys_start: CONFIG_SYS_PCI1_MEM_PHYS, +- size: CONFIG_SYS_PCI1_MEM_SIZE, +- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH +- }, +- { +- bus_start: CONFIG_SYS_PCI1_IO_BASE, +- phys_start: CONFIG_SYS_PCI1_IO_PHYS, +- size: CONFIG_SYS_PCI1_IO_SIZE, +- flags: PCI_REGION_IO +- }, +- { +- bus_start: CONFIG_SYS_PCI1_MMIO_BASE, +- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, +- size: CONFIG_SYS_PCI1_MMIO_SIZE, +- flags: PCI_REGION_MEM +- }, +-}; +- +-#ifdef CONFIG_MPC83XX_PCI2 +-static struct pci_region pci2_regions[] = { +- { +- bus_start: CONFIG_SYS_PCI2_MEM_BASE, +- phys_start: CONFIG_SYS_PCI2_MEM_PHYS, +- size: CONFIG_SYS_PCI2_MEM_SIZE, +- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH +- }, +- { +- bus_start: CONFIG_SYS_PCI2_IO_BASE, +- phys_start: CONFIG_SYS_PCI2_IO_PHYS, +- size: CONFIG_SYS_PCI2_IO_SIZE, +- flags: PCI_REGION_IO +- }, +- { +- bus_start: CONFIG_SYS_PCI2_MMIO_BASE, +- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, +- size: CONFIG_SYS_PCI2_MMIO_SIZE, +- flags: PCI_REGION_MEM +- }, +-}; +-#endif +- +-#ifndef CONFIG_PCISLAVE +-void pib_init(void) +-{ +- u8 val8, orig_i2c_bus; +- /* +- * Assign PIB PMC slot to desired PCI bus +- */ +- /* Switch temporarily to I2C bus #2 */ +- orig_i2c_bus = i2c_get_bus_num(); +- i2c_set_bus_num(1); +- +- val8 = 0; +- i2c_write(0x23, 0x6, 1, &val8, 1); +- i2c_write(0x23, 0x7, 1, &val8, 1); +- val8 = 0xff; +- i2c_write(0x23, 0x2, 1, &val8, 1); +- i2c_write(0x23, 0x3, 1, &val8, 1); +- +- val8 = 0; +- i2c_write(0x26, 0x6, 1, &val8, 1); +- val8 = 0x34; +- i2c_write(0x26, 0x7, 1, &val8, 1); +-#if defined(CONFIG_PCI_64BIT) +- val8 = 0xf4; /* PMC2:PCI1/64-bit */ +-#elif defined(CONFIG_PCI_ALL_PCI1) +- val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ +-#elif defined(CONFIG_PCI_ONE_PCI1) +- val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ +-#else +- val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ +-#endif +- i2c_write(0x26, 0x2, 1, &val8, 1); +- val8 = 0xff; +- i2c_write(0x26, 0x3, 1, &val8, 1); +- val8 = 0; +- i2c_write(0x27, 0x6, 1, &val8, 1); +- i2c_write(0x27, 0x7, 1, &val8, 1); +- val8 = 0xff; +- i2c_write(0x27, 0x2, 1, &val8, 1); +- val8 = 0xef; +- i2c_write(0x27, 0x3, 1, &val8, 1); +- asm("eieio"); +- +-#if defined(CONFIG_PCI_64BIT) +- printf("PCI1: 64-bit on PMC2\n"); +-#elif defined(CONFIG_PCI_ALL_PCI1) +- printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); +-#elif defined(CONFIG_PCI_ONE_PCI1) +- printf("PCI1: 32-bit on PMC1\n"); +- printf("PCI2: 32-bit on PMC2, PMC3\n"); +-#else +- printf("PCI1: 32-bit on PMC1, PMC2\n"); +- printf("PCI2: 32-bit on PMC3\n"); +-#endif +- /* Reset to original I2C bus */ +- i2c_set_bus_num(orig_i2c_bus); +-} +- +-#endif /* CONFIG_PCISLAVE */ +diff -ruN u-boot-2021.10/board/freescale/mx51evk/Kconfig u-boot/board/freescale/mx51evk/Kconfig +--- u-boot-2021.10/board/freescale/mx51evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx51evk/Kconfig 2021-11-01 17:10:14.019605794 +0100 +@@ -12,4 +12,7 @@ + config SYS_CONFIG_NAME + default "mx51evk" + ++config IMX_CONFIG ++ default "board/freescale/mx51evk/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx51evk/mx51evk.c u-boot/board/freescale/mx51evk/mx51evk.c +--- u-boot-2021.10/board/freescale/mx51evk/mx51evk.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx51evk/mx51evk.c 2021-11-01 17:10:14.019605794 +0100 +@@ -35,6 +35,7 @@ + return 0; + } + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + u32 rev = get_cpu_rev(); +@@ -42,6 +43,7 @@ + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; + } ++#endif + + #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) + +diff -ruN u-boot-2021.10/board/freescale/mx53loco/Kconfig u-boot/board/freescale/mx53loco/Kconfig +--- u-boot-2021.10/board/freescale/mx53loco/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx53loco/Kconfig 2021-11-01 17:10:14.019605794 +0100 +@@ -12,4 +12,7 @@ + config SYS_CONFIG_NAME + default "mx53loco" + ++config IMX_CONFIG ++ default "board/freescale/mx53loco/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx53loco/mx53loco.c u-boot/board/freescale/mx53loco/mx53loco.c +--- u-boot-2021.10/board/freescale/mx53loco/mx53loco.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx53loco/mx53loco.c 2021-11-01 17:10:14.019605794 +0100 +@@ -32,6 +32,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; +@@ -46,6 +47,7 @@ + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; + } ++#endif + + #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) +diff -ruN u-boot-2021.10/board/freescale/mx6memcal/Kconfig u-boot/board/freescale/mx6memcal/Kconfig +--- u-boot-2021.10/board/freescale/mx6memcal/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6memcal/Kconfig 2021-11-01 17:10:14.019605794 +0100 +@@ -87,12 +87,12 @@ + help + Select the type of DDR (DDR3 or LPDDR2) used on your design + +-config DDR3 ++config DDR3 + bool "DDR3" + help + Select this if your board design uses DDR3. + +-config LPDDR2 ++config LPDDR2 + bool "LPDDR2" + help + Select this if your board design uses LPDDR2. +@@ -223,5 +223,8 @@ + details. + + endmenu +-endif + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/spl_sd.cfg" ++ ++endif +diff -ruN u-boot-2021.10/board/freescale/mx6memcal/mx6memcal.c u-boot/board/freescale/mx6memcal/mx6memcal.c +--- u-boot-2021.10/board/freescale/mx6memcal/mx6memcal.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6memcal/mx6memcal.c 2021-11-01 17:10:14.019605794 +0100 +@@ -30,4 +30,3 @@ + gd->ram_size = imx_ddr_size(); + return 0; + } +- +diff -ruN u-boot-2021.10/board/freescale/mx6sabreauto/mx6sabreauto.c u-boot/board/freescale/mx6sabreauto/mx6sabreauto.c +--- u-boot-2021.10/board/freescale/mx6sabreauto/mx6sabreauto.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6sabreauto/mx6sabreauto.c 2021-11-01 17:10:14.019605794 +0100 +@@ -321,12 +321,14 @@ + } + #endif + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + int rev = nxp_board_rev(); + + return (get_cpu_rev() & ~(0xF << 8)) | rev; + } ++#endif + + static int ar8031_phy_fixup(struct phy_device *phydev) + { +diff -ruN u-boot-2021.10/board/freescale/mx6slevk/Kconfig u-boot/board/freescale/mx6slevk/Kconfig +--- u-boot-2021.10/board/freescale/mx6slevk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6slevk/Kconfig 2021-11-01 17:10:14.019605794 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx6slevk" + ++config IMX_CONFIG ++ default "board/freescale/mx6slevk/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx6sllevk/Kconfig u-boot/board/freescale/mx6sllevk/Kconfig +--- u-boot-2021.10/board/freescale/mx6sllevk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6sllevk/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx6sllevk" + ++config IMX_CONFIG ++ default "board/freescale/mx6sllevk/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx6sxsabreauto/Kconfig u-boot/board/freescale/mx6sxsabreauto/Kconfig +--- u-boot-2021.10/board/freescale/mx6sxsabreauto/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6sxsabreauto/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx6sxsabreauto" + ++config IMX_CONFIG ++ default "board/freescale/mx6sxsabreauto/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx6sxsabresd/Kconfig u-boot/board/freescale/mx6sxsabresd/Kconfig +--- u-boot-2021.10/board/freescale/mx6sxsabresd/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6sxsabresd/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx6sxsabresd" + ++config IMX_CONFIG ++ default "board/freescale/mx6sxsabresd/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx6ullevk/Kconfig u-boot/board/freescale/mx6ullevk/Kconfig +--- u-boot-2021.10/board/freescale/mx6ullevk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx6ullevk/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx6ullevk" + ++config IMX_CONFIG ++ default "board/freescale/mx6ullevk/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx7dsabresd/Kconfig u-boot/board/freescale/mx7dsabresd/Kconfig +--- u-boot-2021.10/board/freescale/mx7dsabresd/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx7dsabresd/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx7dsabresd" + ++config IMX_CONFIG ++ default "board/freescale/mx7dsabresd/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/mx7ulp_evk/Kconfig u-boot/board/freescale/mx7ulp_evk/Kconfig +--- u-boot-2021.10/board/freescale/mx7ulp_evk/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/mx7ulp_evk/Kconfig 2021-11-01 17:10:14.022938945 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "mx7ulp_evk" + ++config IMX_CONFIG ++ default "board/freescale/mx7ulp_evk/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/freescale/p1010rdb/p1010rdb.c u-boot/board/freescale/p1010rdb/p1010rdb.c +--- u-boot-2021.10/board/freescale/p1010rdb/p1010rdb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/p1010rdb/p1010rdb.c 2021-11-01 17:10:14.022938945 +0100 +@@ -427,7 +427,7 @@ + dm_i2c_write(dev, 2, &val, 1); + #else + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); +- i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + val = 0x0; /* no polarity inversion */ + i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); + #endif +diff -ruN u-boot-2021.10/board/freescale/p1_p2_rdb_pc/spl.c u-boot/board/freescale/p1_p2_rdb_pc/spl.c +--- u-boot-2021.10/board/freescale/p1_p2_rdb_pc/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/p1_p2_rdb_pc/spl.c 2021-11-01 17:10:14.022938945 +0100 +@@ -99,7 +99,7 @@ + env_relocate(); + #endif + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + i2c_init_all(); + #else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +diff -ruN u-boot-2021.10/board/freescale/t102xrdb/eth_t102xrdb.c u-boot/board/freescale/t102xrdb/eth_t102xrdb.c +--- u-boot-2021.10/board/freescale/t102xrdb/eth_t102xrdb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t102xrdb/eth_t102xrdb.c 2021-11-01 17:10:14.026272096 +0100 +@@ -64,7 +64,7 @@ + /* set the on-board RGMII2 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + +- /* set 10G XFI with Aquantia AQR105 PHY */ ++ /* set 10GBase-R with Aquantia AQR105 PHY */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + break; + #endif +@@ -103,7 +103,7 @@ + #endif + fm_info_set_mdio(i, dev); + break; +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; +@@ -133,12 +133,12 @@ + enum fm_port port, int offset) + { + #if defined(CONFIG_TARGET_T1024RDB) +- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || ++ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || + (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && + (port == FM1_DTSEC3)) { + fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); + fdt_setprop_string(fdt, offset, "phy-connection-type", +- "sgmii-2500"); ++ "2500base-x"); + fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); + } + #endif +diff -ruN u-boot-2021.10/board/freescale/t102xrdb/README u-boot/board/freescale/t102xrdb/README +--- u-boot-2021.10/board/freescale/t102xrdb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t102xrdb/README 2021-11-01 17:10:14.026272096 +0100 +@@ -39,7 +39,7 @@ + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps +- - 10GbE XFI or 10Base-KR interface ++ - 10GBase-R or 10Base-KR interface + - Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC +diff -ruN u-boot-2021.10/board/freescale/t102xrdb/spl.c u-boot/board/freescale/t102xrdb/spl.c +--- u-boot-2021.10/board/freescale/t102xrdb/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t102xrdb/spl.c 2021-11-01 17:10:14.026272096 +0100 +@@ -30,11 +30,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + #if defined(CONFIG_SPL_MMC_BOOT) + #define GPIO1_SD_SEL 0x00020000 + int board_mmc_getcd(struct mmc *mmc) +diff -ruN u-boot-2021.10/board/freescale/t102xrdb/t102xrdb.c u-boot/board/freescale/t102xrdb/t102xrdb.c +--- u-boot-2021.10/board/freescale/t102xrdb/t102xrdb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t102xrdb/t102xrdb.c 2021-11-01 17:10:14.026272096 +0100 +@@ -167,11 +167,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + #ifdef CONFIG_TARGET_T1024RDB + void board_reset(void) + { +diff -ruN u-boot-2021.10/board/freescale/t104xrdb/spl.c u-boot/board/freescale/t104xrdb/spl.c +--- u-boot-2021.10/board/freescale/t104xrdb/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t104xrdb/spl.c 2021-11-01 17:10:14.026272096 +0100 +@@ -30,11 +30,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + void board_init_f(ulong bootflag) + { +diff -ruN u-boot-2021.10/board/freescale/t208xqds/eth_t208xqds.c u-boot/board/freescale/t208xqds/eth_t208xqds.c +--- u-boot-2021.10/board/freescale/t208xqds/eth_t208xqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xqds/eth_t208xqds.c 2021-11-01 17:10:14.026272096 +0100 +@@ -310,16 +310,16 @@ + + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + switch (srds_s1) { +- case 0x66: /* XFI interface */ ++ case 0x66: /* 10GBase-R interface */ + case 0x6b: + case 0x6c: + case 0x6d: + case 0x71: + /* +- * if the 10G is XFI, check hwconfig to see what is the +- * media type, there are two types, fiber or copper, +- * fix the dtb accordingly. +- */ ++ * Check hwconfig to see what is the media type, there ++ * are two types, fiber or copper, fix the dtb ++ * accordingly. ++ */ + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { +@@ -378,7 +378,7 @@ + printf("Interface %d in backplane KR mode\n", + port); + } else { +- /* fixed-link for XFI fiber cable */ ++ /* fixed-link for 10GBase-R fiber cable */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; +@@ -538,12 +538,12 @@ + case 0x66: + case 0x67: + /* +- * XFI does not need a PHY to work, but to avoid U-Boot use +- * default PHY address which is zero to a MAC when it found +- * a MAC has no PHY address, we give a PHY address to XFI ++ * 10GBase-R does not need a PHY to work, but to avoid U-Boot ++ * use default PHY address which is zero to a MAC when it found ++ * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks +- * the XAUI card is used for the XFI MAC, which will cause ++ * the XAUI card is used for the 10GBase-R MAC, which will cause + * error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); +@@ -701,7 +701,7 @@ + (srds_s1 == 0x6a) || (srds_s1 == 0x70) || + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || + (srds_s1 == 0x71)) { +- /* As XFI is in cage intead of a slot, so ++ /* As 10GBase-R is in cage intead of a slot, so + * ensure doesn't disable the corresponding port + */ + break; +diff -ruN u-boot-2021.10/board/freescale/t208xqds/README u-boot/board/freescale/t208xqds/README +--- u-boot-2021.10/board/freescale/t208xqds/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xqds/README 2021-11-01 17:10:14.026272096 +0100 +@@ -55,14 +55,14 @@ + - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support + Ethernet interfaces: + - Two 1Gbps RGMII on-board ports +- - Four 10Gbps XFI on-board cages ++ - Four 10GBase-R on-board cages + - 1Gbps/2.5Gbps SGMII Riser card + - 10Gbps XAUI Riser card + Accelerator: + - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC + SerDes: + - 16 lanes up to 10.3125GHz +- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI ++ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI + IFC: + - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA + eSPI: +@@ -85,14 +85,14 @@ + - QIXIS-II FPGA system controll + Debug Features: + - Support Legacy, COP/JTAG, Aurora, Event and EVT +-XFI: +- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to ++10GBase-R: ++ - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to + a on-board SFP+ cages, which to house optical module (fiber cable) or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. +- So, for XFI usage, there are two scenarios, one will use fiber cable, ++ So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is +- introduced to indicate a XFI port will use copper cable, and U-Boot ++ introduced to indicate a 10GBase-R port will use copper cable, and U-Boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they +@@ -100,10 +100,10 @@ + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in +- hwconfig, then both four XFI ports will use copper cable. ++ hwconfig, then both four 10GBase-R ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two +- XFI ports will use copper cable, the other two XFI ports will use fiber +- cable. ++ 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use ++ fiber cable. + 1000BASE-KX(1G-KX): + - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane + runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane +@@ -158,7 +158,6 @@ + 0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +- + Software configurations and board settings + ------------------------------------------ + 1. NOR boot: +diff -ruN u-boot-2021.10/board/freescale/t208xqds/t208xqds.c u-boot/board/freescale/t208xqds/t208xqds.c +--- u-boot-2021.10/board/freescale/t208xqds/t208xqds.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xqds/t208xqds.c 2021-11-01 17:10:14.026272096 +0100 +@@ -136,14 +136,14 @@ + break; + case 0x66: + case 0x67: +- /* SD1(A:D) => XFI cage ++ /* SD1(A:D) => 10GBase-R cage + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xfe); + break; + case 0x6a: + case 0x6b: +- /* SD1(A:D) => XFI cage ++ /* SD1(A:D) => 10GBase-R cage + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ +@@ -151,14 +151,14 @@ + break; + case 0x6c: + case 0x6d: +- /* SD1(A:B) => XFI cage ++ /* SD1(A:B) => 10GBase-R cage + * SD1(C:D) => SLOT3 SGMII + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xda); + break; + case 0x6e: +- /* SD1(A:B) => SFP Module, XFI ++ /* SD1(A:B) => SFP Module, 10GBase-R + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII +diff -ruN u-boot-2021.10/board/freescale/t208xrdb/Kconfig u-boot/board/freescale/t208xrdb/Kconfig +--- u-boot-2021.10/board/freescale/t208xrdb/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xrdb/Kconfig 2021-11-01 17:10:14.026272096 +0100 +@@ -11,7 +11,6 @@ + + config T2080RDB_REV_D + bool "Support for T2080RDB revisions D and up" +- default n + + source "board/freescale/common/Kconfig" + +diff -ruN u-boot-2021.10/board/freescale/t208xrdb/README u-boot/board/freescale/t208xrdb/README +--- u-boot-2021.10/board/freescale/t208xrdb/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xrdb/README 2021-11-01 17:10:14.029605247 +0100 +@@ -54,7 +54,7 @@ + T2080PCIe-RDB board Overview + ---------------------------- + - SERDES Configuration +- - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) ++ - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) +@@ -62,7 +62,7 @@ + - SerDes-2 Lane G-H: to SATA1 & SATA2 + - Ethernet + - Two on-board 10M/100M/1G RGMII ethernet ports +- - Two on-board 10Gbps XFI fiber ports ++ - Two on-board 10GBase-R fiber ports + - Two on-board 10Gbps Base-T copper ports + - DDR Memory + - Supports 72bit 4GB DDR3-LP SODIMM +diff -ruN u-boot-2021.10/board/freescale/t208xrdb/spl.c u-boot/board/freescale/t208xrdb/spl.c +--- u-boot-2021.10/board/freescale/t208xrdb/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xrdb/spl.c 2021-11-01 17:10:14.029605247 +0100 +@@ -29,11 +29,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + void board_init_f(ulong bootflag) + { + u32 plat_ratio, sys_clk, ccb_clk; +diff -ruN u-boot-2021.10/board/freescale/t208xrdb/t208xrdb.c u-boot/board/freescale/t208xrdb/t208xrdb.c +--- u-boot-2021.10/board/freescale/t208xrdb/t208xrdb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t208xrdb/t208xrdb.c 2021-11-01 17:10:14.029605247 +0100 +@@ -114,11 +114,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + int misc_init_r(void) + { + u8 reg; +diff -ruN u-boot-2021.10/board/freescale/t4rdb/cpld.h u-boot/board/freescale/t4rdb/cpld.h +--- u-boot-2021.10/board/freescale/t4rdb/cpld.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t4rdb/cpld.h 2021-11-01 17:10:14.029605247 +0100 +@@ -45,4 +45,3 @@ + #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) + #define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) +- +diff -ruN u-boot-2021.10/board/freescale/t4rdb/eth.c u-boot/board/freescale/t4rdb/eth.c +--- u-boot-2021.10/board/freescale/t4rdb/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t4rdb/eth.c 2021-11-01 17:10:14.029605247 +0100 +@@ -106,7 +106,7 @@ + + #if (CONFIG_SYS_NUM_FMAN == 2) + if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { +- /* SGMII && XFI */ ++ /* SGMII && 10GBase-R */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); +diff -ruN u-boot-2021.10/board/freescale/t4rdb/spl.c u-boot/board/freescale/t4rdb/spl.c +--- u-boot-2021.10/board/freescale/t4rdb/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/t4rdb/spl.c 2021-11-01 17:10:14.029605247 +0100 +@@ -35,11 +35,6 @@ + return CONFIG_SYS_CLK_FREQ; + } + +-unsigned long get_board_ddr_clk(void) +-{ +- return CONFIG_DDR_CLK_FREQ; +-} +- + void board_init_f(ulong bootflag) + { + u32 plat_ratio, sys_clk, ccb_clk; +diff -ruN u-boot-2021.10/board/freescale/vf610twr/Kconfig u-boot/board/freescale/vf610twr/Kconfig +--- u-boot-2021.10/board/freescale/vf610twr/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/freescale/vf610twr/Kconfig 2021-11-01 17:10:14.029605247 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "vf610twr" + ++config IMX_CONFIG ++ default "board/freescale/vf610twr/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/friendlyarm/nanopi2/board.c u-boot/board/friendlyarm/nanopi2/board.c +--- u-boot-2021.10/board/friendlyarm/nanopi2/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/friendlyarm/nanopi2/board.c 2021-11-01 17:10:14.029605247 +0100 +@@ -295,12 +295,12 @@ + env_set("ethaddr", ethaddr); + } + +-#ifdef CONFIG_REVISION_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + static void set_board_rev(void) + { + char info[64] = {0, }; + +- snprintf(info, ARRAY_SIZE(info), "%02x", get_board_rev()); ++ snprintf(info, ARRAY_SIZE(info), "%02x", get_board_revision()); + env_set("board_rev", info); + } + #endif +@@ -310,7 +310,7 @@ + char info[64] = {0, }; + + snprintf(info, ARRAY_SIZE(info), +- "s5p4418-nanopi2-rev%02x.dtb", get_board_rev()); ++ "s5p4418-nanopi2-rev%02x.dtb", get_board_revision()); + env_set("dtb_name", info); + } + +@@ -436,7 +436,7 @@ + { + bd_update_env(); + +-#ifdef CONFIG_REVISION_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_rev(); + #endif + set_dtb_name(); +diff -ruN u-boot-2021.10/board/friendlyarm/nanopi2/hwrev.c u-boot/board/friendlyarm/nanopi2/hwrev.c +--- u-boot-2021.10/board/friendlyarm/nanopi2/hwrev.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/friendlyarm/nanopi2/hwrev.c 2021-11-01 17:10:14.029605247 +0100 +@@ -80,11 +80,18 @@ + } + + /* To override __weak symbols */ +-u32 get_board_rev(void) ++u32 get_board_revision(void) + { + return (base_rev << 8) | pcb_rev; + } + ++#ifdef CONFIG_REVISION_TAG ++u32 get_board_rev(void) ++{ ++ return get_board_revision(); ++} ++#endif ++ + const char *get_board_name(void) + { + bd_hwrev_init(); +diff -ruN u-boot-2021.10/board/friendlyarm/nanopi2/hwrev.h u-boot/board/friendlyarm/nanopi2/hwrev.h +--- u-boot-2021.10/board/friendlyarm/nanopi2/hwrev.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/friendlyarm/nanopi2/hwrev.h 2021-11-01 17:10:14.029605247 +0100 +@@ -9,7 +9,7 @@ + + extern void bd_hwrev_init(void); + extern void bd_base_rev_init(void); +-extern u32 get_board_rev(void); ++extern u32 get_board_revision(void); + extern const char *get_board_name(void); + + #endif /* __BD_HW_REV_H__ */ +diff -ruN u-boot-2021.10/board/gateworks/gw_ventana/gsc.h u-boot/board/gateworks/gw_ventana/gsc.h +--- u-boot-2021.10/board/gateworks/gw_ventana/gsc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/gateworks/gw_ventana/gsc.h 2021-11-01 17:10:14.032938398 +0100 +@@ -69,4 +69,3 @@ + int gsc_boot_wd_disable(void); + const char *gsc_get_dtb_name(int level, char *buf, int sz); + #endif +- +diff -ruN u-boot-2021.10/board/gateworks/gw_ventana/Makefile u-boot/board/gateworks/gw_ventana/Makefile +--- u-boot-2021.10/board/gateworks/gw_ventana/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/gateworks/gw_ventana/Makefile 2021-11-01 17:10:14.029605247 +0100 +@@ -8,4 +8,3 @@ + + obj-y := gw_ventana.o gsc.o eeprom.o common.o + obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o +- +diff -ruN u-boot-2021.10/board/gateworks/venice/Kconfig u-boot/board/gateworks/venice/Kconfig +--- u-boot-2021.10/board/gateworks/venice/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/gateworks/venice/Kconfig 2021-11-01 17:10:14.032938398 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mm_venice" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/gdsys/a38x/dt_helpers.c u-boot/board/gdsys/a38x/dt_helpers.c +--- u-boot-2021.10/board/gdsys/a38x/dt_helpers.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/gdsys/a38x/dt_helpers.c 2021-11-01 17:10:14.032938398 +0100 +@@ -39,4 +39,3 @@ + + return dm_gpio_request(gpio, gpio_name); + } +- +diff -ruN u-boot-2021.10/board/gdsys/a38x/ihs_phys.c u-boot/board/gdsys/a38x/ihs_phys.c +--- u-boot-2021.10/board/gdsys/a38x/ihs_phys.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/gdsys/a38x/ihs_phys.c 2021-11-01 17:10:14.032938398 +0100 +@@ -110,9 +110,7 @@ + + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, +- name, +- MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + +diff -ruN u-boot-2021.10/board/ge/b1x5v2/b1x5v2.c u-boot/board/ge/b1x5v2/b1x5v2.c +--- u-boot-2021.10/board/ge/b1x5v2/b1x5v2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/b1x5v2/b1x5v2.c 2021-11-01 17:10:14.036271549 +0100 +@@ -30,7 +30,7 @@ + #include + #include + #include +-#include ++#include + + #include "../common/vpd_reader.h" + +diff -ruN u-boot-2021.10/board/ge/bx50v3/bx50v3.c u-boot/board/ge/bx50v3/bx50v3.c +--- u-boot-2021.10/board/ge/bx50v3/bx50v3.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/bx50v3/bx50v3.c 2021-11-01 17:10:14.036271549 +0100 +@@ -34,7 +34,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include "../common/ge_rtc.h" +diff -ruN u-boot-2021.10/board/ge/common/ge_rtc.c u-boot/board/ge/common/ge_rtc.c +--- u-boot-2021.10/board/ge/common/ge_rtc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/common/ge_rtc.c 2021-11-01 17:10:14.036271549 +0100 +@@ -53,4 +53,3 @@ + else + env_set("rtc_status", "OK"); + } +- +diff -ruN u-boot-2021.10/board/ge/mx53ppd/Kconfig u-boot/board/ge/mx53ppd/Kconfig +--- u-boot-2021.10/board/ge/mx53ppd/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/mx53ppd/Kconfig 2021-11-01 17:10:14.036271549 +0100 +@@ -1,4 +1,3 @@ +- + if TARGET_MX53PPD + + config SYS_BOARD +@@ -13,6 +12,9 @@ + config SYS_CONFIG_NAME + default "mx53ppd" + ++config IMX_CONFIG ++ default "board/ge/mx53ppd/imximage.cfg" ++ + source "board/ge/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/ge/mx53ppd/mx53ppd.c u-boot/board/ge/mx53ppd/mx53ppd.c +--- u-boot-2021.10/board/ge/mx53ppd/mx53ppd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/mx53ppd/mx53ppd.c 2021-11-01 17:10:14.036271549 +0100 +@@ -33,7 +33,7 @@ + #include + #include + #include +-#include ++#include + #include + #include "ppd_gpio.h" + #include +@@ -81,10 +81,12 @@ + return 0; + } + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + return get_cpu_rev() & ~(0xF << 8); + } ++#endif + + #ifdef CONFIG_USB_EHCI_MX5 + int board_ehci_hcd_init(int port) +diff -ruN u-boot-2021.10/board/ge/mx53ppd/mx53ppd_video.c u-boot/board/ge/mx53ppd/mx53ppd_video.c +--- u-boot-2021.10/board/ge/mx53ppd/mx53ppd_video.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ge/mx53ppd/mx53ppd_video.c 2021-11-01 17:10:14.036271549 +0100 +@@ -92,4 +92,3 @@ + }; + + size_t display_count = ARRAY_SIZE(displays); +- +diff -ruN u-boot-2021.10/board/google/chromebook_coral/coral.c u-boot/board/google/chromebook_coral/coral.c +--- u-boot-2021.10/board/google/chromebook_coral/coral.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/google/chromebook_coral/coral.c 2021-11-01 17:10:14.036271549 +0100 +@@ -300,7 +300,7 @@ + .get_str = coral_get_str, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id coral_ids[] = { + { .compatible = "google,coral" }, + { } +diff -ruN u-boot-2021.10/board/google/imx8mq_phanbell/Kconfig u-boot/board/google/imx8mq_phanbell/Kconfig +--- u-boot-2021.10/board/google/imx8mq_phanbell/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/google/imx8mq_phanbell/Kconfig 2021-11-01 17:10:14.036271549 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mq_phanbell" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/grinn/chiliboard/board.c u-boot/board/grinn/chiliboard/board.c +--- u-boot-2021.10/board/grinn/chiliboard/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/grinn/chiliboard/board.c 2021-11-01 17:10:14.039604700 +0100 +@@ -30,7 +30,7 @@ + static __maybe_unused struct ctrl_dev *cdev = + (struct ctrl_dev *)CTRL_DEVICE_BASE; + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ +@@ -69,9 +69,7 @@ + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + } +-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT + void set_uart_mux_conf(void) + { + configure_module_pin_mux(uart0_pin_mux); +@@ -86,7 +84,7 @@ + { + chilisom_spl_board_init(); + } +-#endif ++#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + /* + * Basic board specific setup. Pinmux has been handled already. +diff -ruN u-boot-2021.10/board/hisilicon/poplar/poplar.c u-boot/board/hisilicon/poplar/poplar.c +--- u-boot-2021.10/board/hisilicon/poplar/poplar.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/hisilicon/poplar/poplar.c 2021-11-01 17:10:14.039604700 +0100 +@@ -195,4 +195,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/board/imgtec/ci20/ci20.c u-boot/board/imgtec/ci20/ci20.c +--- u-boot-2021.10/board/imgtec/ci20/ci20.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/imgtec/ci20/ci20.c 2021-11-01 17:10:14.039604700 +0100 +@@ -254,7 +254,7 @@ + + #ifdef CONFIG_SPL_BUILD + +-#if defined(CONFIG_SPL_MMC_SUPPORT) ++#if defined(CONFIG_SPL_MMC) + int board_mmc_init(struct bd_info *bd) + { + ci20_mux_mmc(); +diff -ruN u-boot-2021.10/board/inversepath/usbarmory/usbarmory.c u-boot/board/inversepath/usbarmory/usbarmory.c +--- u-boot-2021.10/board/inversepath/usbarmory/usbarmory.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/inversepath/usbarmory/usbarmory.c 2021-11-01 17:10:14.042937851 +0100 +@@ -27,6 +27,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; +@@ -38,6 +39,7 @@ + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; + } ++#endif + + struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR} +diff -ruN u-boot-2021.10/board/keymile/common/ivm.c u-boot/board/keymile/common/ivm.c +--- u-boot-2021.10/board/keymile/common/ivm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/keymile/common/ivm.c 2021-11-01 17:10:14.046271002 +0100 +@@ -346,17 +346,17 @@ + struct udevice *eedev = NULL; + + ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS, +- CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev); ++ CONFIG_SYS_IVM_EEPROM_ADR, 1, &eedev); + if (ret) { + printf("failed to get device for EEPROM at address 0x%02x\n", +- CONFIG_SYS_I2C_EEPROM_ADDR); ++ CONFIG_SYS_IVM_EEPROM_ADR); + return 1; + } + + ret = dm_i2c_read(eedev, 0, buf, len); + if (ret != 0) { + printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n", +- CONFIG_SYS_I2C_EEPROM_ADDR, 0); ++ CONFIG_SYS_IVM_EEPROM_ADR, 0); + return 1; + } + #else +diff -ruN u-boot-2021.10/board/keymile/common/qrio.c u-boot/board/keymile/common/qrio.c +--- u-boot-2021.10/board/keymile/common/qrio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/keymile/common/qrio.c 2021-11-01 17:10:14.046271002 +0100 +@@ -290,4 +290,3 @@ + return qrio_get_gpio(KM_I2C_DEBLOCK_PORT, + KM_I2C_DEBLOCK_SCL); + } +- +diff -ruN u-boot-2021.10/board/keymile/km83xx/km83xx_i2c.c u-boot/board/keymile/km83xx/km83xx_i2c.c +--- u-boot-2021.10/board/keymile/km83xx/km83xx_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/keymile/km83xx/km83xx_i2c.c 2021-11-01 17:10:14.046271002 +0100 +@@ -15,7 +15,7 @@ + { + struct fsl_i2c_base *base; + base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + +- CONFIG_SYS_I2C_OFFSET); ++ CONFIG_SYS_FSL_I2C_OFFSET); + udelay(DELAY_ABORT_SEQ); + out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); +@@ -26,7 +26,7 @@ + { + struct fsl_i2c_base *base; + base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + +- CONFIG_SYS_I2C_OFFSET); ++ CONFIG_SYS_FSL_I2C_OFFSET); + uchar last; + int nbr_read = 0; + int i = 0; +diff -ruN u-boot-2021.10/board/keymile/km_arm/Kconfig u-boot/board/keymile/km_arm/Kconfig +--- u-boot-2021.10/board/keymile/km_arm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/keymile/km_arm/Kconfig 2021-11-01 17:10:14.046271002 +0100 +@@ -3,37 +3,31 @@ + + config KM_FPGA_CONFIG + bool "FPGA Configuration" +- default n + help + Include capability to change FPGA configuration. + + config KM_FPGA_FORCE_CONFIG + bool "FPGA reconfiguration" +- default n + help + If yes we force to reconfigure the FPGA always + + config KM_FPGA_NO_RESET + bool "FPGA skip reset" +- default n + help + If yes we skip triggering a reset of the FPGA + + config KM_ENV_IS_IN_SPI_NOR + bool "Environment in SPI NOR" +- default n + help + Put the U-Boot environment in the SPI NOR flash. + + config KM_PIGGY4_88E6061 + bool "Piggy via Switch 88E6061" +- default n + help + The Piggy4 board is connected via a Marvell 88E6061 switch. + + config KM_PIGGY4_88E6352 + bool "Piggy via Switch 88E6352" +- default n + help + The Piggy4 board is connected via a Marvell 88E6352 switch. + +diff -ruN u-boot-2021.10/board/k+p/kp_imx53/Kconfig u-boot/board/k+p/kp_imx53/Kconfig +--- u-boot-2021.10/board/k+p/kp_imx53/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/k+p/kp_imx53/Kconfig 2021-11-01 17:10:14.046271002 +0100 +@@ -12,4 +12,7 @@ + config SYS_CONFIG_NAME + default "kp_imx53" + ++config IMX_CONFIG ++ default "board/freescale/mx53loco/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/k+p/kp_imx53/kp_id_rev.c u-boot/board/k+p/kp_imx53/kp_id_rev.c +--- u-boot-2021.10/board/k+p/kp_imx53/kp_id_rev.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/k+p/kp_imx53/kp_id_rev.c 2021-11-01 17:10:14.046271002 +0100 +@@ -64,6 +64,10 @@ + eth_env_set_enetaddr("ethaddr", p); + } + ++#define I2C_EEPROM_BUS_NUM 1 ++#define I2C_EEPROM_ADDR 0x50 ++#define I2C_EEPROM_ADDR_LEN 2 ++ + int read_eeprom(void) + { + struct udevice *dev; +@@ -72,9 +76,8 @@ + if (eeprom_has_been_read) + return 0; + +- ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, +- CONFIG_SYS_I2C_EEPROM_ADDR, +- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); ++ ret = i2c_get_chip_for_busnum(I2C_EEPROM_BUS_NUM, I2C_EEPROM_ADDR, ++ I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("Cannot find EEPROM !\n"); + return ret; +diff -ruN u-boot-2021.10/board/LaCie/netspace_v2/netspace_v2.c u-boot/board/LaCie/netspace_v2/netspace_v2.c +--- u-boot-2021.10/board/LaCie/netspace_v2/netspace_v2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/LaCie/netspace_v2/netspace_v2.c 2021-11-01 17:10:13.959609076 +0100 +@@ -73,8 +73,10 @@ + + int board_init(void) + { ++#ifdef CONFIG_MACH_TYPE + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; ++#endif + + /* Boot parameters address */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; +diff -ruN u-boot-2021.10/board/l+g/vinco/vinco.c u-boot/board/l+g/vinco/vinco.c +--- u-boot-2021.10/board/l+g/vinco/vinco.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/l+g/vinco/vinco.c 2021-11-01 17:10:14.049604154 +0100 +@@ -30,7 +30,6 @@ + #include + #include + #include +-#include + + DECLARE_GLOBAL_DATA_PTR; + +diff -ruN u-boot-2021.10/board/lg/sniper/sniper.c u-boot/board/lg/sniper/sniper.c +--- u-boot-2021.10/board/lg/sniper/sniper.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/lg/sniper/sniper.c 2021-11-01 17:10:14.049604154 +0100 +@@ -156,11 +156,13 @@ + return 0; + } + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + /* Sold devices are expected to be at least revision F. */ + return 6; + } ++#endif + + void get_board_serial(struct tag_serialnr *serialnr) + { +diff -ruN u-boot-2021.10/board/liebherr/display5/spl.c u-boot/board/liebherr/display5/spl.c +--- u-boot-2021.10/board/liebherr/display5/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/liebherr/display5/spl.c 2021-11-01 17:10:14.049604154 +0100 +@@ -273,7 +273,7 @@ + #endif + } + +-#ifdef CONFIG_SPL_SPI_SUPPORT ++#ifdef CONFIG_SPL_SPI + static void displ5_init_ecspi(void) + { + displ5_set_iomux_ecspi_spl(); +@@ -283,7 +283,7 @@ + static inline void displ5_init_ecspi(void) { } + #endif + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC4_BASE_ADDR, + .max_bus_width = 8, +diff -ruN u-boot-2021.10/board/logicpd/am3517evm/am3517evm.h u-boot/board/logicpd/am3517evm/am3517evm.h +--- u-boot-2021.10/board/logicpd/am3517evm/am3517evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/logicpd/am3517evm/am3517evm.h 2021-11-01 17:10:14.052937304 +0100 +@@ -314,7 +314,7 @@ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + /*SYS_nRESWARM */\ +- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ ++ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + /* - PEN_IRQ */\ +diff -ruN u-boot-2021.10/board/logicpd/imx6/Makefile u-boot/board/logicpd/imx6/Makefile +--- u-boot-2021.10/board/logicpd/imx6/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/logicpd/imx6/Makefile 2021-11-01 17:10:14.052937304 +0100 +@@ -7,4 +7,3 @@ + # + + obj-y := imx6logic.o +- +diff -ruN u-boot-2021.10/board/logicpd/imx6/README u-boot/board/logicpd/imx6/README +--- u-boot-2021.10/board/logicpd/imx6/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/logicpd/imx6/README 2021-11-01 17:10:14.052937304 +0100 +@@ -80,4 +80,3 @@ + + Additional Support Documentation can be found at: + https://support.logicpd.com/ +- +diff -ruN u-boot-2021.10/board/logicpd/omap3som/omap3logic.h u-boot/board/logicpd/omap3som/omap3logic.h +--- u-boot-2021.10/board/logicpd/omap3som/omap3logic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/logicpd/omap3som/omap3logic.h 2021-11-01 17:10:14.052937304 +0100 +@@ -243,7 +243,7 @@ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/ +- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ ++ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/ +diff -ruN u-boot-2021.10/board/Marvell/aspenite/aspenite.c u-boot/board/Marvell/aspenite/aspenite.c +--- u-boot-2021.10/board/Marvell/aspenite/aspenite.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/aspenite/aspenite.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,45 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor +- * Written-by: Prafulla Wadaskar +- * Contributor: Mahavir Jain +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-DECLARE_GLOBAL_DATA_PTR; +- +-int board_early_init_f(void) +-{ +- u32 mfp_cfg[] = { +- /* I2C */ +- MFP105_CI2C_SDA, +- MFP106_CI2C_SCL, +- +- /* Enable Console on UART1 */ +- MFP107_UART1_RXD, +- MFP108_UART1_TXD, +- +- MFP_EOC /*End of configureation*/ +- }; +- /* configure MFP's */ +- mfp_config(mfp_cfg); +- return 0; +-} +- +-int board_init(void) +-{ +- /* arch number of Board */ +- gd->bd->bi_arch_number = MACH_TYPE_ASPENITE; +- /* adress of boot parameters */ +- gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; +- return 0; +-} +diff -ruN u-boot-2021.10/board/Marvell/aspenite/Kconfig u-boot/board/Marvell/aspenite/Kconfig +--- u-boot-2021.10/board/Marvell/aspenite/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/aspenite/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,15 +0,0 @@ +-if TARGET_ASPENITE +- +-config SYS_BOARD +- default "aspenite" +- +-config SYS_VENDOR +- default "Marvell" +- +-config SYS_SOC +- default "armada100" +- +-config SYS_CONFIG_NAME +- default "aspenite" +- +-endif +diff -ruN u-boot-2021.10/board/Marvell/aspenite/MAINTAINERS u-boot/board/Marvell/aspenite/MAINTAINERS +--- u-boot-2021.10/board/Marvell/aspenite/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/aspenite/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 +@@ -1,6 +0,0 @@ +-ASPENITE BOARD +-M: Prafulla Wadaskar +-S: Maintained +-F: board/Marvell/aspenite/ +-F: include/configs/aspenite.h +-F: configs/aspenite_defconfig +diff -ruN u-boot-2021.10/board/Marvell/aspenite/Makefile u-boot/board/Marvell/aspenite/Makefile +--- u-boot-2021.10/board/Marvell/aspenite/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/aspenite/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,8 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2010 +-# Marvell Semiconductor +-# Written-by: Prafulla Wadaskar +-# Contributor: Mahavir Jain +- +-obj-y := aspenite.o +diff -ruN u-boot-2021.10/board/Marvell/guruplug/guruplug.c u-boot/board/Marvell/guruplug/guruplug.c +--- u-boot-2021.10/board/Marvell/guruplug/guruplug.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/guruplug/guruplug.c 2021-11-01 17:10:13.959609076 +0100 +@@ -77,7 +77,7 @@ + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, +- MPP46_GPIO, /* M_RLED */ ++ MPP46_GPIO, /* M_RLED */ + MPP47_GPIO, /* M_GLED */ + MPP48_GPIO, /* B_RLED */ + MPP49_GPIO, /* B_GLED */ +diff -ruN u-boot-2021.10/board/Marvell/octeon_ebb7304/board.c u-boot/board/Marvell/octeon_ebb7304/board.c +--- u-boot-2021.10/board/Marvell/octeon_ebb7304/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/octeon_ebb7304/board.c 2021-11-01 17:10:13.962942226 +0100 +@@ -339,7 +339,7 @@ + case CVMX_QLM_MODE_XFI: + case CVMX_QLM_MODE_RGMII_XFI: + case CVMX_QLM_MODE_RGMII_XFI_1X1: +- type_str = "xfi"; ++ type_str = "10gbase-r"; + break; + case CVMX_QLM_MODE_10G_KR: + case CVMX_QLM_MODE_RGMII_10G_KR: +@@ -393,7 +393,7 @@ + if (pmd_control.s.train_en) + type_str = "10G_KR"; + else +- type_str = "xfi"; ++ type_str = "10gbase-r"; + break; + case 4: + if (pmd_control.s.train_en) +@@ -618,7 +618,7 @@ + speed[qlm] = 103125; + } + printf("QLM %d: XLAUI\n", qlm); +- } else if (!strncmp(mode_str, "xfi", 3)) { ++ } else if (!strncmp(mode_str, "10gbase-r", 3)) { + bool rgmii = false; + + speed[qlm] = 103125; +diff -ruN u-boot-2021.10/board/Marvell/octeontx/smc.c u-boot/board/Marvell/octeontx/smc.c +--- u-boot-2021.10/board/Marvell/octeontx/smc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/octeontx/smc.c 2021-11-01 17:10:13.962942226 +0100 +@@ -22,4 +22,3 @@ + + return regs.regs[0]; + } +- +diff -ruN u-boot-2021.10/board/Marvell/octeontx2/soc-utils.c u-boot/board/Marvell/octeontx2/soc-utils.c +--- u-boot-2021.10/board/Marvell/octeontx2/soc-utils.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Marvell/octeontx2/soc-utils.c 2021-11-01 17:10:13.962942226 +0100 +@@ -46,4 +46,3 @@ + { + return fdt_get_board_model(); + } +- +diff -ruN u-boot-2021.10/board/mediatek/mt7620/Kconfig u-boot/board/mediatek/mt7620/Kconfig +--- u-boot-2021.10/board/mediatek/mt7620/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7620/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,12 +0,0 @@ +-if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB +- +-config SYS_BOARD +- default "mt7620" +- +-config SYS_VENDOR +- default "mediatek" +- +-config SYS_CONFIG_NAME +- default "mt7620" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt7622/Kconfig u-boot/board/mediatek/mt7622/Kconfig +--- u-boot-2021.10/board/mediatek/mt7622/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7622/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,17 +0,0 @@ +-if TARGET_MT7622 +- +-config SYS_BOARD +- default "mt7622" +- +-config SYS_CONFIG_NAME +- default "mt7622" +- +-config MTK_BROM_HEADER_INFO +- string +- default "lk=1" +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=nor" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt7622/Makefile u-boot/board/mediatek/mt7622/Makefile +--- u-boot-2021.10/board/mediatek/mt7622/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7622/Makefile 2021-11-01 17:10:14.052937304 +0100 +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + + obj-y += mt7622_rfb.o +- +diff -ruN u-boot-2021.10/board/mediatek/mt7623/Kconfig u-boot/board/mediatek/mt7623/Kconfig +--- u-boot-2021.10/board/mediatek/mt7623/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7623/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,13 +0,0 @@ +-if TARGET_MT7623 +- +-config SYS_BOARD +- default "mt7623" +- +-config SYS_CONFIG_NAME +- default "mt7623" +- +-config MTK_BROM_HEADER_INFO +- string +- default "lk=1" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt7628/Kconfig u-boot/board/mediatek/mt7628/Kconfig +--- u-boot-2021.10/board/mediatek/mt7628/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7628/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,12 +0,0 @@ +-if BOARD_MT7628_RFB +- +-config SYS_BOARD +- default "mt7628" +- +-config SYS_VENDOR +- default "mediatek" +- +-config SYS_CONFIG_NAME +- default "mt7628" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt7629/Kconfig u-boot/board/mediatek/mt7629/Kconfig +--- u-boot-2021.10/board/mediatek/mt7629/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt7629/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,17 +0,0 @@ +-if TARGET_MT7629 +- +-config SYS_BOARD +- default "mt7629" +- +-config SYS_CONFIG_NAME +- default "mt7629" +- +-config MTK_SPL_PAD_SIZE +- hex +- default 0x10000 +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=nor" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt8183/Kconfig u-boot/board/mediatek/mt8183/Kconfig +--- u-boot-2021.10/board/mediatek/mt8183/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt8183/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,13 +0,0 @@ +-if TARGET_MT8183 +- +-config SYS_BOARD +- default "mt8183" +- +-config SYS_CONFIG_NAME +- default "mt8183" +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=emmc" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt8512/Kconfig u-boot/board/mediatek/mt8512/Kconfig +--- u-boot-2021.10/board/mediatek/mt8512/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt8512/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,14 +0,0 @@ +-if TARGET_MT8512 +- +-config SYS_BOARD +- default "mt8512" +- +-config SYS_CONFIG_NAME +- default "mt8512" +- +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=nor" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt8516/Kconfig u-boot/board/mediatek/mt8516/Kconfig +--- u-boot-2021.10/board/mediatek/mt8516/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt8516/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,13 +0,0 @@ +-if TARGET_MT8516 +- +-config SYS_BOARD +- default "mt8516" +- +-config SYS_CONFIG_NAME +- default "mt8516" +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=emmc" +- +-endif +diff -ruN u-boot-2021.10/board/mediatek/mt8518/Kconfig u-boot/board/mediatek/mt8518/Kconfig +--- u-boot-2021.10/board/mediatek/mt8518/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mediatek/mt8518/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,14 +0,0 @@ +-if TARGET_MT8518 +- +-config SYS_BOARD +- default "mt8518" +- +-config SYS_CONFIG_NAME +- default "mt8518" +- +- +-config MTK_BROM_HEADER_INFO +- string +- default "media=nor" +- +-endif +diff -ruN u-boot-2021.10/board/menlo/m53menlo/Kconfig u-boot/board/menlo/m53menlo/Kconfig +--- u-boot-2021.10/board/menlo/m53menlo/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/menlo/m53menlo/Kconfig 2021-11-01 17:10:14.052937304 +0100 +@@ -12,4 +12,7 @@ + config SYS_CONFIG_NAME + default "m53menlo" + ++config IMX_CONFIG ++ default "board/menlo/m53menlo/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/mqmaker/miqi_rk3288/miqi-rk3288.c u-boot/board/mqmaker/miqi_rk3288/miqi-rk3288.c +--- u-boot-2021.10/board/mqmaker/miqi_rk3288/miqi-rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mqmaker/miqi_rk3288/miqi-rk3288.c 2021-11-01 17:10:14.056270455 +0100 +@@ -2,4 +2,3 @@ + /* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ +- +diff -ruN u-boot-2021.10/board/mscc/jr2/Makefile u-boot/board/mscc/jr2/Makefile +--- u-boot-2021.10/board/mscc/jr2/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mscc/jr2/Makefile 2021-11-01 17:10:14.056270455 +0100 +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: (GPL-2.0+ OR MIT) + + obj-$(CONFIG_SOC_JR2) := jr2.o +- +diff -ruN u-boot-2021.10/board/mscc/ocelot/Makefile u-boot/board/mscc/ocelot/Makefile +--- u-boot-2021.10/board/mscc/ocelot/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/mscc/ocelot/Makefile 2021-11-01 17:10:14.056270455 +0100 +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: (GPL-2.0+ OR MIT) + + obj-$(CONFIG_SOC_OCELOT) := ocelot.o +- +diff -ruN u-boot-2021.10/board/nokia/rx51/rx51.c u-boot/board/nokia/rx51/rx51.c +--- u-boot-2021.10/board/nokia/rx51/rx51.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/nokia/rx51/rx51.c 2021-11-01 17:10:14.056270455 +0100 +@@ -241,6 +241,7 @@ + return 0; + } + ++#ifdef CONFIG_REVISION_TAG + /* + * Routine: get_board_revision + * Description: Return board revision. +@@ -249,6 +250,7 @@ + { + return simple_strtol(hw_build_ptr, NULL, 16); + } ++#endif + + /* + * Routine: setup_board_tags +diff -ruN u-boot-2021.10/board/novtech/meerkat96/Kconfig u-boot/board/novtech/meerkat96/Kconfig +--- u-boot-2021.10/board/novtech/meerkat96/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/novtech/meerkat96/Kconfig 2021-11-01 17:10:14.056270455 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "meerkat96" + ++config IMX_CONFIG ++ default "board/novtech/meerkat96/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/nvidia/seaboard/seaboard.c u-boot/board/nvidia/seaboard/seaboard.c +--- u-boot-2021.10/board/nvidia/seaboard/seaboard.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/nvidia/seaboard/seaboard.c 2021-11-01 17:10:14.059603607 +0100 +@@ -16,7 +16,7 @@ + #include + + /* TODO: Remove this code when the SPI switch is working */ +-#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) ++#ifndef CONFIG_TARGET_VENTANA + void gpio_early_init_uart(void) + { + /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ +diff -ruN u-boot-2021.10/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c u-boot/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +--- u-boot-2021.10/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 2021-11-01 17:10:14.059603607 +0100 +@@ -289,4 +289,3 @@ + return ret; + return PS7_INIT_SUCCESS; + } +- +diff -ruN u-boot-2021.10/board/phytec/pcm052/Kconfig u-boot/board/phytec/pcm052/Kconfig +--- u-boot-2021.10/board/phytec/pcm052/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytec/pcm052/Kconfig 2021-11-01 17:10:14.062936758 +0100 +@@ -13,6 +13,9 @@ + int + default 256 + ++config IMX_CONFIG ++ default "board/phytec/pcm052/imximage.cfg" ++ + endif + + if TARGET_BK4R1 +@@ -30,4 +33,7 @@ + int + default 512 + ++config IMX_CONFIG ++ default "board/phytec/pcm052/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/phytec/phycore_imx8mm/Kconfig u-boot/board/phytec/phycore_imx8mm/Kconfig +--- u-boot-2021.10/board/phytec/phycore_imx8mm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytec/phycore_imx8mm/Kconfig 2021-11-01 17:10:14.062936758 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "phycore_imx8mm" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/phytec/phycore_imx8mp/Kconfig u-boot/board/phytec/phycore_imx8mp/Kconfig +--- u-boot-2021.10/board/phytec/phycore_imx8mp/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytec/phycore_imx8mp/Kconfig 2021-11-01 17:10:14.062936758 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "phycore_imx8mp" + ++config IMX_CONFIG ++ default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/phytium/durian/cpu.h u-boot/board/phytium/durian/cpu.h +--- u-boot-2021.10/board/phytium/durian/cpu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytium/durian/cpu.h 2021-11-01 17:10:14.062936758 +0100 +@@ -20,4 +20,3 @@ + #define HNF_BASE (unsigned long)(0x3A200000) + + #endif /* _FT_DURIAN_H */ +- +diff -ruN u-boot-2021.10/board/phytium/durian/durian.c u-boot/board/phytium/durian/durian.c +--- u-boot-2021.10/board/phytium/durian/durian.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytium/durian/durian.c 2021-11-01 17:10:14.062936758 +0100 +@@ -113,4 +113,3 @@ + } + return ret; + } +- +diff -ruN u-boot-2021.10/board/phytium/durian/Makefile u-boot/board/phytium/durian/Makefile +--- u-boot-2021.10/board/phytium/durian/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/phytium/durian/Makefile 2021-11-01 17:10:14.062936758 +0100 +@@ -6,4 +6,3 @@ + # + + obj-y += durian.o +- +diff -ruN u-boot-2021.10/board/ppcag/bg0900/bg0900.c u-boot/board/ppcag/bg0900/bg0900.c +--- u-boot-2021.10/board/ppcag/bg0900/bg0900.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ppcag/bg0900/bg0900.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,89 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * PPC-AG BG0900 board +- * +- * Copyright (C) 2013 Marek Vasut +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-DECLARE_GLOBAL_DATA_PTR; +- +-/* +- * Functions +- */ +-int board_early_init_f(void) +-{ +- /* IO0 clock at 480MHz */ +- mxs_set_ioclk(MXC_IOCLK0, 480000); +- /* IO1 clock at 480MHz */ +- mxs_set_ioclk(MXC_IOCLK1, 480000); +- +- /* SSP2 clock at 160MHz */ +- mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); +- +- return 0; +-} +- +-int dram_init(void) +-{ +- return mxs_dram_init(); +-} +- +-int board_init(void) +-{ +- /* Adress of boot parameters */ +- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +- +- return 0; +-} +- +-#ifdef CONFIG_CMD_NET +-int board_eth_init(struct bd_info *bis) +-{ +- struct mxs_clkctrl_regs *clkctrl_regs = +- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; +- struct eth_device *dev; +- int ret; +- +- ret = cpu_eth_init(bis); +- +- /* BG0900 uses ENET_CLK PAD to drive FEC clock */ +- writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, +- &clkctrl_regs->hw_clkctrl_enet); +- +- /* Reset FEC PHYs */ +- gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); +- udelay(200); +- gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); +- +- ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); +- if (ret) { +- puts("FEC MXS: Unable to init FEC0\n"); +- return ret; +- } +- +- dev = eth_get_dev_by_name("FEC0"); +- if (!dev) { +- puts("FEC MXS: Unable to get FEC0 device entry\n"); +- return -EINVAL; +- } +- +- return ret; +-} +- +-#endif +diff -ruN u-boot-2021.10/board/ppcag/bg0900/Kconfig u-boot/board/ppcag/bg0900/Kconfig +--- u-boot-2021.10/board/ppcag/bg0900/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ppcag/bg0900/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,15 +0,0 @@ +-if TARGET_BG0900 +- +-config SYS_BOARD +- default "bg0900" +- +-config SYS_VENDOR +- default "ppcag" +- +-config SYS_SOC +- default "mxs" +- +-config SYS_CONFIG_NAME +- default "bg0900" +- +-endif +diff -ruN u-boot-2021.10/board/ppcag/bg0900/MAINTAINERS u-boot/board/ppcag/bg0900/MAINTAINERS +--- u-boot-2021.10/board/ppcag/bg0900/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ppcag/bg0900/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 +@@ -1,6 +0,0 @@ +-BG0900 BOARD +-M: Marek Vasut +-S: Maintained +-F: board/ppcag/bg0900/ +-F: include/configs/bg0900.h +-F: configs/bg0900_defconfig +diff -ruN u-boot-2021.10/board/ppcag/bg0900/Makefile u-boot/board/ppcag/bg0900/Makefile +--- u-boot-2021.10/board/ppcag/bg0900/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ppcag/bg0900/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,10 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2000-2006 +-# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- +-ifndef CONFIG_SPL_BUILD +-obj-y := bg0900.o +-else +-obj-y := spl_boot.o +-endif +diff -ruN u-boot-2021.10/board/ppcag/bg0900/spl_boot.c u-boot/board/ppcag/bg0900/spl_boot.c +--- u-boot-2021.10/board/ppcag/bg0900/spl_boot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ppcag/bg0900/spl_boot.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,152 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * PPC-AG BG0900 Boot setup +- * +- * Copyright (C) 2013 Marek Vasut +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +-#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +- +-const iomux_cfg_t iomux_setup[] = { +- /* DUART */ +- MX28_PAD_PWM0__DUART_RX, +- MX28_PAD_PWM1__DUART_TX, +- +- /* GPMI NAND */ +- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_RDN__GPMI_RDN | +- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, +- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, +- +- /* FEC0 */ +- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, +- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, +- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, +- +- /* FEC0 Reset */ +- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | +- (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), +- +- /* EMI */ +- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, +- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, +- +- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, +- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, +- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, +- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, +- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, +- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, +- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, +- +- /* SPI2 (for SPI flash) */ +- MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, +- MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, +- MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, +- MX28_PAD_SSP2_SS0__SSP2_D3 | +- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +-}; +- +-void mxs_adjust_memory_params(uint32_t *dram_vals) +-{ +- /* +- * DDR Controller Registers +- * Manufacturer: Winbond +- * Device Part Number: W972GG6JB-25I +- * Clock Freq.: 200MHz +- * Density: 2Gb +- * Chip Selects: 1 +- * Number of Banks: 8 +- * Row address: 14 +- * Column address: 10 +- */ +- +- dram_vals[0x74 / 4] = 0x0102010A; +- dram_vals[0x98 / 4] = 0x04005003; +- dram_vals[0x9c / 4] = 0x090000c8; +- +- dram_vals[0xa8 / 4] = 0x0036b009; +- dram_vals[0xac / 4] = 0x03270612; +- +- dram_vals[0xb0 / 4] = 0x02020202; +- dram_vals[0xb4 / 4] = 0x00c80029; +- +- dram_vals[0xc0 / 4] = 0x00011900; +- +- dram_vals[0x12c / 4] = 0x07400300; +- dram_vals[0x130 / 4] = 0x07400300; +- dram_vals[0x2c4 / 4] = 0x02030303; +-} +- +-void board_init_ll(const uint32_t arg, const uint32_t *resptr) +-{ +- mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +-} +diff -ruN u-boot-2021.10/board/qca/ap152/ap152.c u-boot/board/qca/ap152/ap152.c +--- u-boot-2021.10/board/qca/ap152/ap152.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/qca/ap152/ap152.c 2021-11-01 17:10:14.062936758 +0100 +@@ -66,7 +66,7 @@ + void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* CPU:775, DDR:650, AHB:258 */ + qca956x_pll_init(); + qca956x_ddr_init(); +diff -ruN u-boot-2021.10/board/qualcomm/dragonboard820c/dragonboard820c.c u-boot/board/qualcomm/dragonboard820c/dragonboard820c.c +--- u-boot-2021.10/board/qualcomm/dragonboard820c/dragonboard820c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/qualcomm/dragonboard820c/dragonboard820c.c 2021-11-01 17:10:14.062936758 +0100 +@@ -73,7 +73,7 @@ + + /* drive strength configs for sdhc pins */ + const struct tlmm_cfg hdrv[] = { +- ++ + { SDC1_CLK_HDRV, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, }, + { SDC1_CMD_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, + { SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, +@@ -81,14 +81,14 @@ + + /* pull configs for sdhc pins */ + const struct tlmm_cfg pull[] = { +- ++ + { SDC1_CLK_PULL, TLMM_NO_PULL, TLMM_PULL_MASK, }, + { SDC1_CMD_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, + { SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, + }; + + const struct tlmm_cfg rclk[] = { +- ++ + { SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,}, + }; + +diff -ruN u-boot-2021.10/board/raspberrypi/rpi/rpi.c u-boot/board/raspberrypi/rpi/rpi.c +--- u-boot-2021.10/board/raspberrypi/rpi/rpi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/raspberrypi/rpi/rpi.c 2021-11-01 17:10:14.066269908 +0100 +@@ -419,7 +419,7 @@ + return 0; + } + +-static void get_board_rev(void) ++static void get_board_revision(void) + { + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); + int ret; +@@ -478,7 +478,7 @@ + hw_watchdog_init(); + #endif + +- get_board_rev(); ++ get_board_revision(); + + gd->bd->bi_boot_params = 0x100; + +diff -ruN u-boot-2021.10/board/renesas/draak/draak.c u-boot/board/renesas/draak/draak.c +--- u-boot-2021.10/board/renesas/draak/draak.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/renesas/draak/draak.c 2021-11-01 17:10:14.066269908 +0100 +@@ -38,7 +38,7 @@ + + int board_early_init_f(void) + { +-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); + #endif +diff -ruN u-boot-2021.10/board/renesas/grpeach/lowlevel_init.S u-boot/board/renesas/grpeach/lowlevel_init.S +--- u-boot-2021.10/board/renesas/grpeach/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/renesas/grpeach/lowlevel_init.S 2021-11-01 17:10:14.066269908 +0100 +@@ -4,7 +4,6 @@ + * Copyright (C) 2017 Chris Brandt + */ + #include +-#include + #include + + /* Watchdog Registers */ +diff -ruN u-boot-2021.10/board/renesas/salvator-x/salvator-x.c u-boot/board/renesas/salvator-x/salvator-x.c +--- u-boot-2021.10/board/renesas/salvator-x/salvator-x.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/renesas/salvator-x/salvator-x.c 2021-11-01 17:10:14.069603059 +0100 +@@ -37,7 +37,7 @@ + + int board_early_init_f(void) + { +-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); + #endif +@@ -75,7 +75,7 @@ + + void reset_cpu(void) + { +-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) + i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); + #else + /* only CA57 ? */ +diff -ruN u-boot-2021.10/board/renesas/ulcb/ulcb.c u-boot/board/renesas/ulcb/ulcb.c +--- u-boot-2021.10/board/renesas/ulcb/ulcb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/renesas/ulcb/ulcb.c 2021-11-01 17:10:14.069603059 +0100 +@@ -35,7 +35,7 @@ + + int board_early_init_f(void) + { +-#if defined(CONFIG_SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); + #endif +diff -ruN u-boot-2021.10/board/rockchip/evb_rk3229/evb_rk3229.c u-boot/board/rockchip/evb_rk3229/evb_rk3229.c +--- u-boot-2021.10/board/rockchip/evb_rk3229/evb_rk3229.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/rockchip/evb_rk3229/evb_rk3229.c 2021-11-01 17:10:14.069603059 +0100 +@@ -7,4 +7,3 @@ + #include + #include + #include +- +diff -ruN u-boot-2021.10/board/rockchip/evb_rk3288/evb-rk3288.c u-boot/board/rockchip/evb_rk3288/evb-rk3288.c +--- u-boot-2021.10/board/rockchip/evb_rk3288/evb-rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/rockchip/evb_rk3288/evb-rk3288.c 2021-11-01 17:10:14.069603059 +0100 +@@ -2,4 +2,3 @@ + /* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ +- +diff -ruN u-boot-2021.10/board/rockchip/evb_rk3328/evb-rk3328.c u-boot/board/rockchip/evb_rk3328/evb-rk3328.c +--- u-boot-2021.10/board/rockchip/evb_rk3328/evb-rk3328.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/rockchip/evb_rk3328/evb-rk3328.c 2021-11-01 17:10:14.069603059 +0100 +@@ -2,4 +2,3 @@ + /* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ +- +diff -ruN u-boot-2021.10/board/ronetix/imx8mq-cm/Kconfig u-boot/board/ronetix/imx8mq-cm/Kconfig +--- u-boot-2021.10/board/ronetix/imx8mq-cm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ronetix/imx8mq-cm/Kconfig 2021-11-01 17:10:14.072936211 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "imx8mq_cm" + ++config IMX_CONFIG ++ default "board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/samsung/common/board.c u-boot/board/samsung/common/board.c +--- u-boot-2021.10/board/samsung/common/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/common/board.c 2021-11-01 17:10:14.072936211 +0100 +@@ -185,7 +185,7 @@ + } + #endif + +-#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC) ++#if CONFIG_IS_ENABLED(POWER_LEGACY) || CONFIG_IS_ENABLED(DM_PMIC) + int power_init_board(void) + { + set_ps_hold_ctrl(); +diff -ruN u-boot-2021.10/board/samsung/common/exynos5-dt-types.c u-boot/board/samsung/common/exynos5-dt-types.c +--- u-boot-2021.10/board/samsung/common/exynos5-dt-types.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/common/exynos5-dt-types.c 2021-11-01 17:10:14.072936211 +0100 +@@ -47,18 +47,6 @@ + { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, + }; + +-static unsigned int odroid_get_rev(void) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { +- if (odroid_info[i].board_type == gd->board_type) +- return odroid_info[i].board_rev; +- } +- +- return 0; +-} +- + /* + * Read ADC at least twice and check the resuls. If regulator providing voltage + * on to measured point was just turned on, first reads might require time +@@ -200,6 +188,19 @@ + return false; + } + ++#ifdef CONFIG_REVISION_TAG ++static unsigned int odroid_get_rev(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { ++ if (odroid_info[i].board_type == gd->board_type) ++ return odroid_info[i].board_rev; ++ } ++ ++ return 0; ++} ++ + /** + * get_board_rev() - return detected board revision. + * +@@ -212,6 +213,7 @@ + + return odroid_get_rev(); + } ++#endif + + /** + * get_board_type() - returns board type string. +diff -ruN u-boot-2021.10/board/samsung/goni/goni.c u-boot/board/samsung/goni/goni.c +--- u-boot-2021.10/board/samsung/goni/goni.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/goni/goni.c 2021-11-01 17:10:14.072936211 +0100 +@@ -24,11 +24,6 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + /* Set Initial global variables */ +diff -ruN u-boot-2021.10/board/samsung/origen/origen.c u-boot/board/samsung/origen/origen.c +--- u-boot-2021.10/board/samsung/origen/origen.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/origen/origen.c 2021-11-01 17:10:14.076269362 +0100 +@@ -12,11 +12,6 @@ + #include + #include + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int exynos_init(void) + { + return 0; +diff -ruN u-boot-2021.10/board/samsung/trats2/trats2.c u-boot/board/samsung/trats2/trats2.c +--- u-boot-2021.10/board/samsung/trats2/trats2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/trats2/trats2.c 2021-11-01 17:10:14.076269362 +0100 +@@ -67,10 +67,12 @@ + board_rev = modelrev << 8; + } + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + return board_rev; + } ++#endif + + static inline u32 get_model_rev(void) + { +diff -ruN u-boot-2021.10/board/samsung/universal_c210/universal.c u-boot/board/samsung/universal_c210/universal.c +--- u-boot-2021.10/board/samsung/universal_c210/universal.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/samsung/universal_c210/universal.c 2021-11-01 17:10:14.076269362 +0100 +@@ -33,10 +33,12 @@ + unsigned int board_rev; + static int init_pmic_lcd(void); + ++#ifdef CONFIG_REVISION_TAG + u32 get_board_rev(void) + { + return board_rev; + } ++#endif + + int exynos_power_init(void) + { +diff -ruN u-boot-2021.10/board/sandbox/sandbox.c u-boot/board/sandbox/sandbox.c +--- u-boot-2021.10/board/sandbox/sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/sandbox/sandbox.c 2021-11-01 17:10:14.076269362 +0100 +@@ -26,7 +26,10 @@ + gd_t *gd; + + #if !CONFIG_IS_ENABLED(OF_PLATDATA) +-/* Add a simple GPIO device */ ++/* ++ * Add a simple GPIO device (don't use with of-platdata as it interferes with ++ * the auto-generated devices) ++ */ + U_BOOT_DRVINFO(gpio_sandbox) = { + .name = "sandbox_gpio", + }; +diff -ruN u-boot-2021.10/board/siemens/capricorn/Kconfig u-boot/board/siemens/capricorn/Kconfig +--- u-boot-2021.10/board/siemens/capricorn/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/siemens/capricorn/Kconfig 2021-11-01 17:10:14.079602512 +0100 +@@ -9,6 +9,8 @@ + config SYS_CONFIG_NAME + default "giedi" + ++config IMX_CONFIG ++ default "board/siemens/capricorn/imximage.cfg" + endif + + if TARGET_DENEB +@@ -22,4 +24,7 @@ + config SYS_CONFIG_NAME + default "deneb" + ++config IMX_CONFIG ++ default "board/siemens/capricorn/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/siemens/common/board.c u-boot/board/siemens/common/board.c +--- u-boot-2021.10/board/siemens/common/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/siemens/common/board.c 2021-11-01 17:10:14.079602512 +0100 +@@ -70,6 +70,7 @@ + #endif /* #ifdef CONFIG_SPL_BUILD */ + + #ifndef CONFIG_SPL_BUILD ++#define FACTORYSET_EEPROM_ADDR 0x50 + /* + * Basic board specific setup. Pinmux has been handled already. + */ +@@ -87,7 +88,7 @@ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + #ifdef CONFIG_FACTORYSET +- factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); ++ factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); + #endif + + gpmc_init(); +diff -ruN u-boot-2021.10/board/siemens/draco/board.c u-boot/board/siemens/draco/board.c +--- u-boot-2021.10/board/siemens/draco/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/siemens/draco/board.c 2021-11-01 17:10:14.079602512 +0100 +@@ -132,12 +132,16 @@ + u8 nand_bus; + }; + ++#define EEPROM_ADDR 0x50 ++#define EEPROM_ADDR_DDR3 0x90 ++#define EEPROM_ADDR_CHIP 0x120 ++ + static int draco_read_nand_geometry(void) + { + struct am335x_nand_geometry geo; + + /* Read NAND geometry */ +- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2, ++ if (i2c_read(EEPROM_ADDR, 0x80, 2, + (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { + printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); + return -EIO; +@@ -160,20 +164,20 @@ + static int read_eeprom(void) + { + /* Check if baseboard eeprom is available */ +- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { ++ if (i2c_probe(EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + + #ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ +- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, ++ if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ +- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, ++ if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + +diff -ruN u-boot-2021.10/board/siemens/iot2050/board.c u-boot/board/siemens/iot2050/board.c +--- u-boot-2021.10/board/siemens/iot2050/board.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/siemens/iot2050/board.c 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,272 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Board specific initialization for IOT2050 ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin ++ * Jan Kiszka ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define IOT2050_INFO_MAGIC 0x20502050 ++ ++struct iot2050_info { ++ u32 magic; ++ u16 size; ++ char name[20 + 1]; ++ char serial[16 + 1]; ++ char mlfb[18 + 1]; ++ char uuid[32 + 1]; ++ char a5e[18 + 1]; ++ u8 mac_addr_cnt; ++ u8 mac_addr[8][ARP_HLEN]; ++ char seboot_version[40 + 1]; ++} __packed; ++ ++/* ++ * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data. ++ */ ++#define IOT2050_INFO_DATA ((struct iot2050_info *) \ ++ TI_SRAM_SCRATCH_BOARD_EEPROM_START) ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static bool board_is_advanced(void) ++{ ++ struct iot2050_info *info = IOT2050_INFO_DATA; ++ ++ return info->magic == IOT2050_INFO_MAGIC && ++ strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; ++} ++ ++static bool board_is_sr1(void) ++{ ++ struct iot2050_info *info = IOT2050_INFO_DATA; ++ ++ return info->magic == IOT2050_INFO_MAGIC && ++ !strstr((char *)info->name, "-PG2"); ++} ++ ++static void remove_mmc1_target(void) ++{ ++ char *boot_targets = strdup(env_get("boot_targets")); ++ char *mmc1 = strstr(boot_targets, "mmc1"); ++ ++ if (mmc1) { ++ memmove(mmc1, mmc1 + 4, strlen(mmc1 + 4) + 1); ++ env_set("boot_targets", boot_targets); ++ } ++ ++ free(boot_targets); ++} ++ ++void set_board_info_env(void) ++{ ++ struct iot2050_info *info = IOT2050_INFO_DATA; ++ u8 __maybe_unused mac_cnt; ++ const char *fdtfile; ++ ++ if (info->magic != IOT2050_INFO_MAGIC) { ++ pr_err("IOT2050: Board info parsing error!\n"); ++ return; ++ } ++ ++ if (env_get("board_uuid")) ++ return; ++ ++ env_set("board_name", info->name); ++ env_set("board_serial", info->serial); ++ env_set("mlfb", info->mlfb); ++ env_set("board_uuid", info->uuid); ++ env_set("board_a5e", info->a5e); ++ env_set("fw_version", PLAIN_VERSION); ++ env_set("seboot_version", info->seboot_version); ++ ++ if (IS_ENABLED(CONFIG_NET)) { ++ /* set MAC addresses to ensure forwarding to the OS */ ++ for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) { ++ if (is_valid_ethaddr(info->mac_addr[mac_cnt])) ++ eth_env_set_enetaddr_by_index("eth", ++ mac_cnt + 1, ++ info->mac_addr[mac_cnt]); ++ } ++ } ++ ++ if (board_is_advanced()) { ++ if (board_is_sr1()) ++ fdtfile = "ti/k3-am6548-iot2050-advanced.dtb"; ++ else ++ fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb"; ++ } else { ++ if (board_is_sr1()) ++ fdtfile = "ti/k3-am6528-iot2050-basic.dtb"; ++ else ++ fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb"; ++ /* remove the unavailable eMMC (mmc1) from the list */ ++ remove_mmc1_target(); ++ } ++ env_set("fdtfile", fdtfile); ++ ++ env_save(); ++} ++ ++int board_init(void) ++{ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ if (board_is_advanced()) ++ gd->ram_size = SZ_2G; ++ else ++ gd->ram_size = SZ_1G; ++ ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ dram_init(); ++ ++ /* Bank 0 declares the memory available in the DDR low region */ ++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; ++ gd->bd->bi_dram[0].size = gd->ram_size; ++ ++ /* Bank 1 declares the memory available in the DDR high region */ ++ gd->bd->bi_dram[1].start = 0; ++ gd->bd->bi_dram[1].size = 0; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_SPL_LOAD_FIT ++int board_fit_config_name_match(const char *name) ++{ ++ struct iot2050_info *info = IOT2050_INFO_DATA; ++ char upper_name[32]; ++ ++ if (info->magic != IOT2050_INFO_MAGIC || ++ strlen(name) >= sizeof(upper_name)) ++ return -1; ++ ++ str_to_upper(name, upper_name, sizeof(upper_name)); ++ if (!strcmp(upper_name, (char *)info->name)) ++ return 0; ++ ++ return -1; ++} ++#endif ++ ++int do_board_detect(void) ++{ ++ return 0; ++} ++ ++#ifdef CONFIG_IOT2050_BOOT_SWITCH ++static bool user_button_pressed(void) ++{ ++ struct udevice *red_led = NULL; ++ unsigned long count = 0; ++ struct gpio_desc gpio; ++ ++ memset(&gpio, 0, sizeof(gpio)); ++ ++ if (dm_gpio_lookup_name("25", &gpio) < 0 || ++ dm_gpio_request(&gpio, "USER button") < 0 || ++ dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN) < 0) ++ return false; ++ ++ if (dm_gpio_get_value(&gpio) == 1) ++ return false; ++ ++ printf("USER button pressed - booting from external media only\n"); ++ ++ led_get_by_label("status-led-red", &red_led); ++ ++ if (red_led) ++ led_set_state(red_led, LEDST_ON); ++ ++ while (dm_gpio_get_value(&gpio) == 0 && count++ < 10000) ++ mdelay(1); ++ ++ if (red_led) ++ led_set_state(red_led, LEDST_OFF); ++ ++ return true; ++} ++#endif ++ ++#define SERDES0_LANE_SELECT 0x00104080 ++ ++int board_late_init(void) ++{ ++ /* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */ ++ writel(0x3, SERDES0_LANE_SELECT); ++ ++ set_board_info_env(); ++ ++ /* remove the eMMC if requested via button */ ++ if (IS_ENABLED(CONFIG_IOT2050_BOOT_SWITCH) && board_is_advanced() && ++ user_button_pressed()) ++ remove_mmc1_target(); ++ ++ return 0; ++} ++ ++#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) ++int ft_board_setup(void *blob, struct bd_info *bd) ++{ ++ int ret; ++ ++ ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000"); ++ if (ret < 0) ++ ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", ++ "sram@70000000"); ++ if (ret) ++ pr_err("%s: fixing up msmc ram failed %d\n", __func__, ret); ++ ++ return ret; ++} ++#endif ++ ++void spl_board_init(void) ++{ ++} ++ ++#if CONFIG_IS_ENABLED(LED) && CONFIG_IS_ENABLED(BOOTSTAGE) ++/* ++ * Indicate any error or (accidental?) entering of CLI via the red status LED. ++ */ ++void show_boot_progress(int progress) ++{ ++ struct udevice *dev; ++ int ret; ++ ++ if (progress < 0 || progress == BOOTSTAGE_ID_ENTER_CLI_LOOP) { ++ ret = led_get_by_label("status-led-green", &dev); ++ if (ret == 0) ++ led_set_state(dev, LEDST_OFF); ++ ++ ret = led_get_by_label("status-led-red", &dev); ++ if (ret == 0) ++ led_set_state(dev, LEDST_ON); ++ } ++} ++#endif +diff -ruN u-boot-2021.10/board/siemens/iot2050/config.mk u-boot/board/siemens/iot2050/config.mk +--- u-boot-2021.10/board/siemens/iot2050/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/siemens/iot2050/config.mk 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (c) Siemens AG, 2020-2021 ++# ++# Authors: ++# Jan Kiszka ++ ++flash.bin: all +diff -ruN u-boot-2021.10/board/siemens/iot2050/Kconfig u-boot/board/siemens/iot2050/Kconfig +--- u-boot-2021.10/board/siemens/iot2050/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/siemens/iot2050/Kconfig 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,32 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (c) Siemens AG, 2018-2021 ++# ++# Authors: ++# Le Jin ++# Jan Kiszka ++ ++config TARGET_IOT2050_A53 ++ bool "IOT2050 running on A53" ++ select ARM64 ++ select SOC_K3_AM6 ++ select BOARD_LATE_INIT ++ select SYS_DISABLE_DCACHE_OPS ++ select BINMAN ++ ++if TARGET_IOT2050_A53 ++ ++config SYS_BOARD ++ default "iot2050" ++ ++config SYS_VENDOR ++ default "siemens" ++ ++config SYS_CONFIG_NAME ++ default "iot2050" ++ ++config IOT2050_BOOT_SWITCH ++ bool "Disable eMMC boot via USER button (Advanced version only)" ++ default y ++ ++endif +diff -ruN u-boot-2021.10/board/siemens/iot2050/MAINTAINERS u-boot/board/siemens/iot2050/MAINTAINERS +--- u-boot-2021.10/board/siemens/iot2050/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/siemens/iot2050/MAINTAINERS 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,9 @@ ++IOT2050 BOARD ++M: Le Jin ++M: Jan Kiszka ++S: Maintained ++F: board/siemens/iot2050/ ++F: include/configs/iot2050.h ++F: configs/iot2050_defconfig ++F: arch/arm/dts/iot2050-* ++F: doc/board/siemens/iot2050.rst +diff -ruN u-boot-2021.10/board/siemens/iot2050/Makefile u-boot/board/siemens/iot2050/Makefile +--- u-boot-2021.10/board/siemens/iot2050/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/siemens/iot2050/Makefile 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,10 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Makefile for Siemens IOT2050 board ++# Copyright (c) Siemens AG, 2018-2021 ++# ++# Authors: ++# Le Jin ++# ++ ++obj-y += board.o +diff -ruN u-boot-2021.10/board/sifive/unleashed/genimage_sdcard.cfg u-boot/board/sifive/unleashed/genimage_sdcard.cfg +--- u-boot-2021.10/board/sifive/unleashed/genimage_sdcard.cfg 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/sifive/unleashed/genimage_sdcard.cfg 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,19 @@ ++image sdcard.img { ++ size = 128M ++ ++ hdimage { ++ gpt = true ++ } ++ ++ partition u-boot-spl { ++ image = "u-boot-spl.bin" ++ offset = 17K ++ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 ++ } ++ ++ partition u-boot { ++ image = "u-boot.itb" ++ offset = 1041K ++ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 ++ } ++} +diff -ruN u-boot-2021.10/board/sifive/unleashed/genimage_spi-nor.cfg u-boot/board/sifive/unleashed/genimage_spi-nor.cfg +--- u-boot-2021.10/board/sifive/unleashed/genimage_spi-nor.cfg 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/sifive/unleashed/genimage_spi-nor.cfg 2021-11-01 17:10:14.079602512 +0100 +@@ -0,0 +1,19 @@ ++image spi-nor.img { ++ size = 32M ++ ++ hdimage { ++ gpt = true ++ } ++ ++ partition u-boot-spl { ++ image = "u-boot-spl.bin" ++ offset = 20K ++ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47 ++ } ++ ++ partition u-boot { ++ image = "u-boot.itb" ++ offset = 1044K ++ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985 ++ } ++} +diff -ruN u-boot-2021.10/board/socrates/nand.c u-boot/board/socrates/nand.c +--- u-boot-2021.10/board/socrates/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/socrates/nand.c 2021-11-01 17:10:14.082935663 +0100 +@@ -9,6 +9,7 @@ + #if defined(CONFIG_SYS_NAND_BASE) + #include + #include ++#include + #include + + static int state; +diff -ruN u-boot-2021.10/board/softing/vining_2000/Kconfig u-boot/board/softing/vining_2000/Kconfig +--- u-boot-2021.10/board/softing/vining_2000/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/softing/vining_2000/Kconfig 2021-11-01 17:10:14.082935663 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "vining_2000" + ++config IMX_CONFIG ++ default "board/softing/vining_2000/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/somlabs/visionsom-6ull/Kconfig u-boot/board/somlabs/visionsom-6ull/Kconfig +--- u-boot-2021.10/board/somlabs/visionsom-6ull/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/somlabs/visionsom-6ull/Kconfig 2021-11-01 17:10:14.082935663 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "somlabs_visionsom_6ull" + ++config IMX_CONFIG ++ default "board/somlabs/visionsom-6ull/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/somlabs/visionsom-6ull/visionsom-6ull.c u-boot/board/somlabs/visionsom-6ull/visionsom-6ull.c +--- u-boot-2021.10/board/somlabs/visionsom-6ull/visionsom-6ull.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/somlabs/visionsom-6ull/visionsom-6ull.c 2021-11-01 17:10:14.082935663 +0100 +@@ -104,7 +104,7 @@ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + #endif + +diff -ruN u-boot-2021.10/board/st/common/stm32mp_mtdparts.c u-boot/board/st/common/stm32mp_mtdparts.c +--- u-boot-2021.10/board/st/common/stm32mp_mtdparts.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/common/stm32mp_mtdparts.c 2021-11-01 17:10:14.082935663 +0100 +@@ -119,8 +119,7 @@ + } + + #ifdef CONFIG_STM32MP15x_STM32IMAGE +- if (!serial && CONFIG_IS_ENABLED(OPTEE) && +- tee_find_device(NULL, NULL, NULL, NULL)) ++ if (!serial && tee_find_device(NULL, NULL, NULL, NULL)) + tee = true; + #endif + +diff -ruN u-boot-2021.10/board/st/stm32f429-discovery/stm32f429-discovery.c u-boot/board/st/stm32f429-discovery/stm32f429-discovery.c +--- u-boot-2021.10/board/st/stm32f429-discovery/stm32f429-discovery.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32f429-discovery/stm32f429-discovery.c 2021-11-01 17:10:14.086268815 +0100 +@@ -46,11 +46,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/st/stm32f429-evaluation/stm32f429-evaluation.c u-boot/board/st/stm32f429-evaluation/stm32f429-evaluation.c +--- u-boot-2021.10/board/st/stm32f429-evaluation/stm32f429-evaluation.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32f429-evaluation/stm32f429-evaluation.c 2021-11-01 17:10:14.086268815 +0100 +@@ -40,11 +40,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/st/stm32f469-discovery/stm32f469-discovery.c u-boot/board/st/stm32f469-discovery/stm32f469-discovery.c +--- u-boot-2021.10/board/st/stm32f469-discovery/stm32f469-discovery.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32f469-discovery/stm32f469-discovery.c 2021-11-01 17:10:14.086268815 +0100 +@@ -40,11 +40,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/st/stm32f746-disco/stm32f746-disco.c u-boot/board/st/stm32f746-disco/stm32f746-disco.c +--- u-boot-2021.10/board/st/stm32f746-disco/stm32f746-disco.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32f746-disco/stm32f746-disco.c 2021-11-01 17:10:14.086268815 +0100 +@@ -77,12 +77,7 @@ + { + return BOOT_DEVICE_XIP; + } +- + #endif +-u32 get_board_rev(void) +-{ +- return 0; +-} + + int board_late_init(void) + { +diff -ruN u-boot-2021.10/board/st/stm32h743-disco/stm32h743-disco.c u-boot/board/st/stm32h743-disco/stm32h743-disco.c +--- u-boot-2021.10/board/st/stm32h743-disco/stm32h743-disco.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32h743-disco/stm32h743-disco.c 2021-11-01 17:10:14.086268815 +0100 +@@ -36,11 +36,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/st/stm32h743-eval/stm32h743-eval.c u-boot/board/st/stm32h743-eval/stm32h743-eval.c +--- u-boot-2021.10/board/st/stm32h743-eval/stm32h743-eval.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32h743-eval/stm32h743-eval.c 2021-11-01 17:10:14.086268815 +0100 +@@ -36,11 +36,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_init(void) + { + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; +diff -ruN u-boot-2021.10/board/st/stm32h750-art-pi/stm32h750-art-pi.c u-boot/board/st/stm32h750-art-pi/stm32h750-art-pi.c +--- u-boot-2021.10/board/st/stm32h750-art-pi/stm32h750-art-pi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32h750-art-pi/stm32h750-art-pi.c 2021-11-01 17:10:14.086268815 +0100 +@@ -41,11 +41,6 @@ + return 0; + } + +-u32 get_board_rev(void) +-{ +- return 0; +-} +- + int board_late_init(void) + { + return 0; +diff -ruN u-boot-2021.10/board/st/stm32mp1/stm32mp1.c u-boot/board/st/stm32mp1/stm32mp1.c +--- u-boot-2021.10/board/st/stm32mp1/stm32mp1.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/st/stm32mp1/stm32mp1.c 2021-11-01 17:10:14.086268815 +0100 +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -235,10 +236,10 @@ + + static int get_led(struct udevice **dev, char *led_string) + { +- char *led_name; ++ const char *led_name; + int ret; + +- led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); ++ led_name = ofnode_conf_read_str(led_string); + if (!led_name) { + log_debug("could not find %s config string\n", led_string); + return -ENOENT; +diff -ruN u-boot-2021.10/board/ste/stemmy/MAINTAINERS u-boot/board/ste/stemmy/MAINTAINERS +--- u-boot-2021.10/board/ste/stemmy/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ste/stemmy/MAINTAINERS 2021-11-01 17:10:14.086268815 +0100 +@@ -2,5 +2,6 @@ + M: Stephan Gerhold + S: Maintained + F: board/ste/stemmy/ +-F: include/configs/stemmy.h + F: configs/stemmy_defconfig ++F: doc/board/ste/stemmy.rst ++F: include/configs/stemmy.h +diff -ruN u-boot-2021.10/board/ste/stemmy/README u-boot/board/ste/stemmy/README +--- u-boot-2021.10/board/ste/stemmy/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ste/stemmy/README 1970-01-01 01:00:00.000000000 +0100 +@@ -1,50 +0,0 @@ +-ST-Ericsson U8500 Samsung "stemmy" board +-======================================== +- +-The "stemmy" board supports Samsung smartphones released with +-the ST-Ericsson NovaThor U8500 SoC, e.g. +- +- - Samsung Galaxy S III mini (GT-I8190) "golden" +- - Samsung Galaxy S Advance (GT-I9070) "janice" +- - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" +- - Samsung Galaxy Ace 2 (GT-I8160) "codina" +- +-and likely others as well (untested). +- +-At the moment, U-Boot is intended to be chain-loaded from +-the original Samsung bootloader, not replacing it entirely. +- +-Installation +------------- +- +-1. Setup cross compiler, e.g. export CROSS_COMPILE=arm-none-eabi- +-2. make stemmy_defconfig +-3. make +- +-For newer devices (golden and skomer), the U-Boot binary has to be packed into +-an Android boot image. janice boots the raw U-Boot binary from the boot partition. +- +-4. Obtain mkbootimg, e.g. https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg +-5. mkbootimg \ +- --kernel=u-boot.bin \ +- --base=0x00000000 \ +- --kernel_offset=0x00100000 \ +- --ramdisk_offset=0x02000000 \ +- --tags_offset=0x00000100 \ +- --output=u-boot.img +- +-6. Enter Samsung download mode (press Power + Home + Volume Down) +-7. Flash U-Boot image to Android boot partition using Heimdall: +- https://gitlab.com/BenjaminDobell/Heimdall +- +- heimdall flash --Kernel u-boot.(bin|img) +- +-8. After reboot U-Boot prompt should appear via UART. +- +-UART +----- +- +-UART is available through the micro USB port, similar to the Carkit standard. +-With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-. +- +-Make sure to connect the UART cable *before* turning on the phone. +diff -ruN u-boot-2021.10/board/storopack/smegw01/Kconfig u-boot/board/storopack/smegw01/Kconfig +--- u-boot-2021.10/board/storopack/smegw01/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/storopack/smegw01/Kconfig 2021-11-01 17:10:14.086268815 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "smegw01" + ++config IMX_CONFIG ++ default "board/storopack/smegw01/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/sunxi/board.c u-boot/board/sunxi/board.c +--- u-boot-2021.10/board/sunxi/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/sunxi/board.c 2021-11-01 17:10:14.086268815 +0100 +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -47,47 +46,6 @@ + #include + #include + +-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +-/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ +-int soft_i2c_gpio_sda; +-int soft_i2c_gpio_scl; +- +-static int soft_i2c_board_init(void) +-{ +- int ret; +- +- soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); +- if (soft_i2c_gpio_sda < 0) { +- printf("Error invalid soft i2c sda pin: '%s', err %d\n", +- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); +- return soft_i2c_gpio_sda; +- } +- ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); +- if (ret) { +- printf("Error requesting soft i2c sda pin: '%s', err %d\n", +- CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); +- return ret; +- } +- +- soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); +- if (soft_i2c_gpio_scl < 0) { +- printf("Error invalid soft i2c scl pin: '%s', err %d\n", +- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); +- return soft_i2c_gpio_scl; +- } +- ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); +- if (ret) { +- printf("Error requesting soft i2c scl pin: '%s', err %d\n", +- CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); +- return ret; +- } +- +- return 0; +-} +-#else +-static int soft_i2c_board_init(void) { return 0; } +-#endif +- + DECLARE_GLOBAL_DATA_PTR; + + void i2c_init_board(void) +@@ -266,10 +224,6 @@ + } + #endif /* !CONFIG_ARM64 */ + +- ret = axp_gpio_init(); +- if (ret) +- return ret; +- + /* strcmp() would look better, but doesn't get optimised away. */ + if (CONFIG_SATAPWR[0]) { + satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); +@@ -293,27 +247,7 @@ + } + } + +-#if CONFIG_IS_ENABLED(DM_I2C) +- /* +- * Temporary workaround for enabling I2C clocks until proper sunxi DM +- * clk, reset and pinctrl drivers land. +- */ +- i2c_init_board(); +-#endif +- +-#ifdef CONFIG_DM_MMC +- /* +- * Temporary workaround for enabling MMC clocks until a sunxi DM +- * pinctrl driver lands. +- */ +- mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); +-#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 +- mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); +-#endif +-#endif /* CONFIG_DM_MMC */ +- +- /* Uses dm gpio code so do this here and not in i2c_init_board() */ +- return soft_i2c_board_init(); ++ return 0; + } + + /* +@@ -413,7 +347,6 @@ + static void mmc_pinmux_setup(int sdc) + { + unsigned int pin; +- __maybe_unused int pins; + + switch (sdc) { + case 0: +@@ -426,11 +359,9 @@ + break; + + case 1: +- pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); +- + #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) +- if (pins == SUNXI_GPIO_H) { ++ if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { + /* SDC1: PH22-PH-27 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); +@@ -460,27 +391,16 @@ + sunxi_gpio_set_drv(pin, 2); + } + #elif defined(CONFIG_MACH_SUN8I) +- if (pins == SUNXI_GPIO_D) { +- /* SDC1: PD2-PD7 */ +- for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- } else { +- /* SDC1: PG0-PG5 */ +- for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } ++ /* SDC1: PG0-PG5 */ ++ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); + } + #endif + break; + + case 2: +- pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); +- + #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* SDC2: PC6-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { +@@ -489,41 +409,23 @@ + sunxi_gpio_set_drv(pin, 2); + } + #elif defined(CONFIG_MACH_SUN5I) +- if (pins == SUNXI_GPIO_E) { +- /* SDC2: PE4-PE9 */ +- for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- } else { +- /* SDC2: PC6-PC15 */ +- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } ++ /* SDC2: PC6-PC15 */ ++ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); + } + #elif defined(CONFIG_MACH_SUN6I) +- if (pins == SUNXI_GPIO_A) { +- /* SDC2: PA9-PA14 */ +- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- } else { +- /* SDC2: PC6-PC15, PC24 */ +- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- +- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); +- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(SUNXI_GPC(24), 2); ++ /* SDC2: PC6-PC15, PC24 */ ++ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); + } ++ ++ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); ++ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + #elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { +@@ -579,8 +481,6 @@ + break; + + case 3: +- pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); +- + #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + /* SDC3: PI4-PI9 */ +@@ -590,25 +490,16 @@ + sunxi_gpio_set_drv(pin, 2); + } + #elif defined(CONFIG_MACH_SUN6I) +- if (pins == SUNXI_GPIO_A) { +- /* SDC3: PA9-PA14 */ +- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- } else { +- /* SDC3: PC6-PC15, PC24 */ +- for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); +- sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(pin, 2); +- } +- +- sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); +- sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); +- sunxi_gpio_set_drv(SUNXI_GPC(24), 2); ++ /* SDC3: PC6-PC15, PC24 */ ++ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { ++ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); ++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(pin, 2); + } ++ ++ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); ++ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); ++ sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + #endif + break; + +diff -ruN u-boot-2021.10/board/sunxi/board-riscv.c u-boot/board/sunxi/board-riscv.c +--- u-boot-2021.10/board/sunxi/board-riscv.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/sunxi/board-riscv.c 2021-11-01 17:10:14.086268815 +0100 +@@ -0,0 +1,14 @@ ++#include ++#include ++#include ++ ++int board_init(void) ++{ ++ /* https://lore.kernel.org/u-boot/31587574-4cd1-02da-9761-0134ac82b94b@sholland.org/ */ ++ return cpu_probe_all(); ++} ++ ++uint32_t spl_boot_device(void) ++{ ++ return BOOT_DEVICE_MMC1; ++} +diff -ruN u-boot-2021.10/board/sunxi/gmac.c u-boot/board/sunxi/gmac.c +--- u-boot-2021.10/board/sunxi/gmac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/sunxi/gmac.c 2021-11-01 17:10:14.086268815 +0100 +@@ -1,10 +1,8 @@ + #include + #include + #include +-#include + #include + #include +-#include + + void eth_init_board(void) + { +@@ -22,57 +20,4 @@ + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | + CCM_GMAC_CTRL_GPIT_MII); + #endif +- +-#ifndef CONFIG_MACH_SUN6I +- /* Configure pin mux settings for GMAC */ +-#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) { +-#else +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { +-#endif +-#ifdef CONFIG_RGMII +- /* skip unused pins in RGMII mode */ +- if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) +- continue; +-#endif +- sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 3); +- } +-#elif defined CONFIG_RGMII +- /* Configure sun6i RGMII mode pin mux settings */ +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 3); +- } +- for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 3); +- } +- for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 3); +- } +- for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 3); +- } +-#elif defined CONFIG_GMII +- /* Configure sun6i GMII mode pin mux settings */ +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- sunxi_gpio_set_drv(pin, 2); +- } +-#else +- /* Configure sun6i MII mode pin mux settings */ +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +- for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) +- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +-#endif + } +diff -ruN u-boot-2021.10/board/sunxi/Kconfig u-boot/board/sunxi/Kconfig +--- u-boot-2021.10/board/sunxi/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/sunxi/Kconfig 2021-11-01 17:10:14.086268815 +0100 +@@ -0,0 +1,112 @@ ++menu "Board-specific options" ++ depends on ARCH_SUNXI || TARGET_SUNXI ++ ++choice ++ prompt "sunxi SoC Variant" ++ ++config MACH_SUN20I ++ bool "sun20i (Allwinner D1)" ++ depends on RISCV ++ select GENERIC_RISCV ++ select SPL_DM if SPL ++ imply SYSRESET_SBI ++ ++endchoice ++ ++config NR_DRAM_BANKS ++ default 1 ++ ++choice ++ prompt "SPL Image Type" ++ depends on SPL ++ default SPL_IMAGE_TYPE_SUNXI_EGON ++ ++config SPL_IMAGE_TYPE_SUNXI_EGON ++ bool "eGON (normal)" ++ help ++ Select this option to embed the SPL binary in an eGON.BT0 image, ++ which is compatible with the normal boot ROM (NBROM). ++ ++ This is usually the correct option to choose. ++ ++config SPL_IMAGE_TYPE_SUNXI_TOC0 ++ bool "TOC0 (secure)" ++ help ++ Select this option to embed the SPL binary in a TOC0 image, ++ which is compatible with the secure boot ROM (SBROM). ++ ++endchoice ++ ++config SPL_IMAGE_TYPE ++ string ++ default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON ++ default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0 ++ ++config SPL_MAX_SIZE ++ hex ++ default SUNXI_SRAM_SIZE ++ ++config SPL_OPENSBI_LOAD_ADDR ++ default 0x40000000 ++ ++config SUNXI_SRAM_ADDRESS ++ hex ++ default 0x20000 if MACH_SUN20I ++ ++config SUNXI_SRAM_SIZE ++ hex ++ default 0x28000 if MACH_SUN20I ++ ++config SYS_BOARD ++ default "sunxi" ++ ++config SYS_CONFIG_NAME ++ default "sun20i" if MACH_SUN20I ++ ++config SYS_CPU ++ default "generic" if MACH_SUN20I ++ ++config SYS_SOC ++ default "sunxi" ++ ++config SYS_TEXT_BASE ++ default 0x4a000000 if MACH_SUN20I ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select CLK ++ select DM_ETH if NET ++ select DM_GPIO ++ select DM_I2C if I2C ++ select DM_SERIAL ++ select DM_SPI if SPI ++ select GPIO ++ select MMC_SUNXI_HAS_NEW_MODE if MMC_SUNXI ++ select PHY_SUN4I_USB if USB ++ select PINCTRL ++ select SPL_CLK if SPL_DM ++ select SPL_GPIO if SPL_DM ++ select SPL_OF_CONTROL if SPL_DM ++ select SPL_PINCTRL if SPL_DM ++ select SPL_SEPARATE_BSS if SPL ++ select SUPPORT_SPL ++ select TOOLS_LIBCRYPTO ++ imply CMD_MMC ++ imply CMD_USB ++ imply DISTRO_DEFAULTS ++ imply FIT ++ imply MMC ++ imply SPL ++ imply SPL_SPI if SPI ++ imply SPL_MMC if MMC ++ imply SUNXI_GPIO ++ imply SYS_I2C_MVTWSI ++ imply SYS_NS16550 ++ imply SYSRESET ++ imply USB_EHCI_GENERIC ++ imply USB_EHCI_HCD ++ imply USB_OHCI_GENERIC ++ imply USB_OHCI_HCD ++ imply WDT ++ ++endmenu +diff -ruN u-boot-2021.10/board/sunxi/Makefile u-boot/board/sunxi/Makefile +--- u-boot-2021.10/board/sunxi/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/sunxi/Makefile 2021-11-01 17:10:14.086268815 +0100 +@@ -6,7 +6,8 @@ + # + # (C) Copyright 2000-2003 + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +-obj-y += board.o ++obj-$(CONFIG_ARCH_SUNXI) += board.o ++obj-$(CONFIG_TARGET_SUNXI) += board-riscv.o + obj-$(CONFIG_SUN7I_GMAC) += gmac.o + obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o + obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o +diff -ruN u-boot-2021.10/board/Synology/common/legacy.c u-boot/board/Synology/common/legacy.c +--- u-boot-2021.10/board/Synology/common/legacy.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Synology/common/legacy.c 2021-11-01 17:10:13.962942226 +0100 +@@ -15,14 +15,15 @@ + + static unsigned int syno_board_id(void) + { ++#ifdef CONFIG_MACH_TYPE + switch (CONFIG_MACH_TYPE) { + case 527: + return SYNO_DS109_ID; + case 3036: + return SYNO_AXP_4BAY_2BAY; +- default: +- return 0; + } ++#endif ++ return 0; + } + + static unsigned int usb_port_modes(void) +diff -ruN u-boot-2021.10/board/Synology/common/Makefile u-boot/board/Synology/common/Makefile +--- u-boot-2021.10/board/Synology/common/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/Synology/common/Makefile 2021-11-01 17:10:13.962942226 +0100 +@@ -2,4 +2,4 @@ + # + # Copyright (C) 2021 Phil Sutter + +-obj-y += legacy.o ++obj-$(SUPPORT_PASSING_ATAGS) += legacy.o +diff -ruN u-boot-2021.10/board/synopsys/axs10x/axs10x.h u-boot/board/synopsys/axs10x/axs10x.h +--- u-boot-2021.10/board/synopsys/axs10x/axs10x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/synopsys/axs10x/axs10x.h 2021-11-01 17:10:14.086268815 +0100 +@@ -12,4 +12,3 @@ + }; + + #endif /* _BOARD_SYNOPSYS_AXS10X_H */ +- +diff -ruN u-boot-2021.10/board/sysam/stmark2/sbf_dram_init.S u-boot/board/sysam/stmark2/sbf_dram_init.S +--- u-boot-2021.10/board/sysam/stmark2/sbf_dram_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/sysam/stmark2/sbf_dram_init.S 2021-11-01 17:10:14.089601966 +0100 +@@ -5,7 +5,7 @@ + * (C) Copyright 2017 Angelo Dureghello + */ + +-.equ PPMCR0, 0xfc04002d ++.equ PPMCR0, 0xfc04002d + .equ MSCR_SDRAMC, 0xec094060 + .equ MISCCR2, 0xec09001a + .equ DDR_RCR, 0xfc0b8180 +diff -ruN u-boot-2021.10/board/syteco/zmx25/Kconfig u-boot/board/syteco/zmx25/Kconfig +--- u-boot-2021.10/board/syteco/zmx25/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/syteco/zmx25/Kconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,15 +0,0 @@ +-if TARGET_ZMX25 +- +-config SYS_BOARD +- default "zmx25" +- +-config SYS_VENDOR +- default "syteco" +- +-config SYS_SOC +- default "mx25" +- +-config SYS_CONFIG_NAME +- default "zmx25" +- +-endif +diff -ruN u-boot-2021.10/board/syteco/zmx25/lowlevel_init.S u-boot/board/syteco/zmx25/lowlevel_init.S +--- u-boot-2021.10/board/syteco/zmx25/lowlevel_init.S 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/syteco/zmx25/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1,96 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011 +- * Matthias Weisser +- * +- * (C) Copyright 2009 DENX Software Engineering +- * Author: John Rigby +- * +- * Based on U-Boot and RedBoot sources for several different i.mx +- * platforms. +- */ +- +-#include +-#include +-#include +-#include +- +-/* +- * clocks +- */ +-.macro init_clocks +- +- /* disable clock output */ +- write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 +- write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 +- +- /* +- * enable all implemented clocks in all three +- * clock control registers +- */ +- write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff +- write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff +- write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff +- +- /* Devide NAND clock by 32 */ +- write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F +-.endm +- +-/* +- * sdram controller init +- */ +-.macro init_lpddr +- ldr r0, =IMX_ESDRAMC_BASE +- ldr r2, =IMX_SDRAM_BANK0_BASE +- +- /* +- * reset SDRAM controller +- * then wait for initialization to complete +- */ +- ldr r1, =(1 << 1) | (1 << 2) +- str r1, [r0, #ESDRAMC_ESDMISC] +-1: ldr r3, [r0, #ESDRAMC_ESDMISC] +- tst r3, #(1 << 31) +- beq 1b +- ldr r1, =(1 << 2) +- str r1, [r0, #ESDRAMC_ESDMISC] +- +- ldr r1, =0x002a7420 +- str r1, [r0, #ESDRAMC_ESDCFG0] +- +- /* control | precharge */ +- ldr r1, =0x92216008 +- str r1, [r0, #ESDRAMC_ESDCTL0] +- /* dram command encoded in address */ +- str r1, [r2, #0x400] +- +- /* auto refresh */ +- ldr r1, =0xa2216008 +- str r1, [r0, #ESDRAMC_ESDCTL0] +- /* read dram twice to auto refresh */ +- ldr r3, [r2] +- ldr r3, [r2] +- +- /* control | load mode */ +- ldr r1, =0xb2216008 +- str r1, [r0, #ESDRAMC_ESDCTL0] +- +- /* mode register of lpddram */ +- strb r1, [r2, #0x33] +- +- /* extended mode register of lpddrram */ +- ldr r2, =0x81000000 +- strb r1, [r2] +- +- /* control | normal */ +- ldr r1, =0x82216008 +- str r1, [r0, #ESDRAMC_ESDCTL0] +-.endm +- +-.globl lowlevel_init +-lowlevel_init: +- init_aips +- init_max +- init_clocks +- init_lpddr +- mov pc, lr +diff -ruN u-boot-2021.10/board/syteco/zmx25/MAINTAINERS u-boot/board/syteco/zmx25/MAINTAINERS +--- u-boot-2021.10/board/syteco/zmx25/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/syteco/zmx25/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100 +@@ -1,6 +0,0 @@ +-ZMX25 BOARD +-M: Matthias Weisser +-S: Maintained +-F: board/syteco/zmx25/ +-F: include/configs/zmx25.h +-F: configs/zmx25_defconfig +diff -ruN u-boot-2021.10/board/syteco/zmx25/Makefile u-boot/board/syteco/zmx25/Makefile +--- u-boot-2021.10/board/syteco/zmx25/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/syteco/zmx25/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,7 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (c) 2010 Graf-Syteco, Matthias Weisser +-# +- +-obj-y += zmx25.o +-obj-y += lowlevel_init.o +diff -ruN u-boot-2021.10/board/syteco/zmx25/zmx25.c u-boot/board/syteco/zmx25/zmx25.c +--- u-boot-2021.10/board/syteco/zmx25/zmx25.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/syteco/zmx25/zmx25.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,178 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (c) 2011 Graf-Syteco, Matthias Weisser +- * +- * +- * Based on tx25.c: +- * (C) Copyright 2009 DENX Software Engineering +- * Author: John Rigby +- * +- * Based on imx27lite.c: +- * Copyright (C) 2008,2009 Eric Jarrige +- * Copyright (C) 2009 Ilya Yanok +- * And: +- * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat +- */ +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-DECLARE_GLOBAL_DATA_PTR; +- +-int board_init() +-{ +- static const iomux_v3_cfg_t sdhc1_pads[] = { +- NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), +- }; +- +- static const iomux_v3_cfg_t dig_out_pads[] = { +- MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */ +- MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */ +- NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */ +- NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */ +- }; +- +- static const iomux_v3_cfg_t led_pads[] = { +- MX25_PAD_CSI_D9__GPIO_4_21, +- MX25_PAD_CSI_D4__GPIO_1_29, +- }; +- +- static const iomux_v3_cfg_t can_pads[] = { +- NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL), +- }; +- +- static const iomux_v3_cfg_t i2c3_pads[] = { +- MX25_PAD_CSPI1_SS1__I2C3_DAT, +- MX25_PAD_GPIO_E__I2C3_CLK, +- }; +- +- icache_enable(); +- +- /* Setup of core voltage selection pin to run at 1.4V */ +- imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */ +- gpio_direction_output(IMX_GPIO_NR(3, 15), 1); +- +- /* Setup of SD card pins*/ +- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); +- +- /* Setup of digital output for USB power and OC */ +- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */ +- gpio_direction_output(IMX_GPIO_NR(1, 28), 1); +- +- imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */ +- gpio_direction_input(IMX_GPIO_NR(1, 18)); +- +- /* Setup of digital output control pins */ +- imx_iomux_v3_setup_multiple_pads(dig_out_pads, +- ARRAY_SIZE(dig_out_pads)); +- +- /* Switch both output drivers off */ +- gpio_direction_output(IMX_GPIO_NR(1, 7), 0); +- gpio_direction_output(IMX_GPIO_NR(1, 6), 0); +- +- /* Setup of key input pin */ +- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0)); +- gpio_direction_input(IMX_GPIO_NR(2, 29)); +- +- /* Setup of status LED outputs */ +- imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads)); +- +- /* Switch both LEDs off */ +- gpio_direction_output(IMX_GPIO_NR(4, 21), 0); +- gpio_direction_output(IMX_GPIO_NR(1, 29), 0); +- +- /* Setup of CAN1 and CAN2 signals */ +- imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads)); +- +- /* Setup of I2C3 signals */ +- imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); +- +- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +- +- return 0; +-} +- +-int board_late_init(void) +-{ +- const char *e; +- +-#ifdef CONFIG_FEC_MXC +-/* +- * FIXME: need to revisit this +- * The original code enabled PUE and 100-k pull-down without PKE, so the right +- * value here is likely: +- * 0 for no pull +- * or: +- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down +- */ +-#define FEC_OUT_PAD_CTRL 0 +- +- static const iomux_v3_cfg_t fec_pads[] = { +- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, +- MX25_PAD_FEC_RX_DV__FEC_RX_DV, +- MX25_PAD_FEC_RDATA0__FEC_RDATA0, +- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), +- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), +- MX25_PAD_FEC_MDIO__FEC_MDIO, +- MX25_PAD_FEC_RDATA1__FEC_RDATA1, +- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), +- +- MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */ +- MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */ +- }; +- +- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +- +- /* assert PHY reset (low) */ +- gpio_direction_output(IMX_GPIO_NR(3, 16), 0); +- +- udelay(5000); +- +- /* deassert PHY reset */ +- gpio_set_value(IMX_GPIO_NR(3, 16), 1); +- +- udelay(5000); +-#endif +- +- e = env_get("gs_base_board"); +- if (e != NULL) { +- if (strcmp(e, "G283") == 0) { +- int key = gpio_get_value(IMX_GPIO_NR(2, 29)); +- +- if (key) { +- /* Switch on both LEDs to inidcate boot mode */ +- gpio_set_value(IMX_GPIO_NR(1, 29), 0); +- gpio_set_value(IMX_GPIO_NR(4, 21), 0); +- +- env_set("preboot", "run gs_slow_boot"); +- } else +- env_set("preboot", "run gs_fast_boot"); +- } +- } +- +- return 0; +-} +- +-int dram_init(void) +-{ +- /* dram_init must store complete ramsize in gd->ram_size */ +- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, +- PHYS_SDRAM_SIZE); +- return 0; +-} +diff -ruN u-boot-2021.10/board/tcl/sl50/board.c u-boot/board/tcl/sl50/board.c +--- u-boot-2021.10/board/tcl/sl50/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/tcl/sl50/board.c 2021-11-01 17:10:14.089601966 +0100 +@@ -40,7 +40,7 @@ + + static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + static const struct ddr_data ddr3_sl50_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, +@@ -161,7 +161,7 @@ + const struct dpll_params *get_dpll_ddr_params(void) + { + enable_i2c0_pin_mux(); +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return &dpll_ddr_sl50; + } +diff -ruN u-boot-2021.10/board/tcl/sl50/Makefile u-boot/board/tcl/sl50/Makefile +--- u-boot-2021.10/board/tcl/sl50/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/tcl/sl50/Makefile 2021-11-01 17:10:14.089601966 +0100 +@@ -4,7 +4,7 @@ + # + # Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/technexion/pico-imx7d/pico-imx7d.c u-boot/board/technexion/pico-imx7d/pico-imx7d.c +--- u-boot-2021.10/board/technexion/pico-imx7d/pico-imx7d.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx7d/pico-imx7d.c 2021-11-01 17:10:14.092935117 +0100 +@@ -60,7 +60,7 @@ + return 0; + } + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + #define I2C_PMIC 3 + int power_init_board(void) + { +@@ -244,4 +244,3 @@ + } + return 0; + } +- +diff -ruN u-boot-2021.10/board/technexion/pico-imx8mq/Kconfig u-boot/board/technexion/pico-imx8mq/Kconfig +--- u-boot-2021.10/board/technexion/pico-imx8mq/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx8mq/Kconfig 2021-11-01 17:10:14.092935117 +0100 +@@ -9,4 +9,7 @@ + config SYS_CONFIG_NAME + default "pico-imx8mq" + ++config IMX_CONFIG ++ default "arch/arm/mach-imx/imx8m/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c u-boot/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c +--- u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c 2021-11-01 17:10:14.092935117 +0100 +@@ -1731,4 +1731,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, + }; +- +diff -ruN u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c u-boot/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c +--- u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c 2021-11-01 17:10:14.092935117 +0100 +@@ -1731,4 +1731,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, + }; +- +diff -ruN u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c u-boot/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c +--- u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c 2021-11-01 17:10:14.092935117 +0100 +@@ -1731,4 +1731,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, + }; +- +diff -ruN u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c u-boot/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c +--- u-boot-2021.10/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c 2021-11-01 17:10:14.092935117 +0100 +@@ -1731,4 +1731,3 @@ + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, + }; +- +diff -ruN u-boot-2021.10/board/terasic/de0-nano-soc/qts/pll_config.h u-boot/board/terasic/de0-nano-soc/qts/pll_config.h +--- u-boot-2021.10/board/terasic/de0-nano-soc/qts/pll_config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/terasic/de0-nano-soc/qts/pll_config.h 2021-11-01 17:10:14.092935117 +0100 +@@ -81,4 +81,3 @@ + #define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 + + #endif /* _PRELOADER_PLL_CONFIG_H_ */ +- +diff -ruN u-boot-2021.10/board/ti/am335x/board.c u-boot/board/ti/am335x/board.c +--- u-boot-2021.10/board/ti/am335x/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am335x/board.c 2021-11-01 17:10:14.092935117 +0100 +@@ -79,10 +79,6 @@ + { + enable_i2c0_pin_mux(); + enable_i2c2_pin_mux(); +-#if !CONFIG_IS_ENABLED(DM_I2C) +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2); +-#endif + if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS)) + printf("ti_i2c_eeprom_init failed\n"); +@@ -99,7 +95,7 @@ + } + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + static const struct ddr_data ddr2_data = { + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, +@@ -253,7 +249,7 @@ + #ifdef CONFIG_SPL_OS_BOOT + int spl_start_uboot(void) + { +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; +@@ -339,13 +335,8 @@ + if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) + return; + +-#if !CONFIG_IS_ENABLED(DM_I2C) +- if (i2c_probe(TPS65217_CHIP_PM)) +- return; +-#else + if (power_tps65217_init(0)) + return; +-#endif + + + /* +@@ -438,13 +429,8 @@ + * 1.10V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +- if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) +- return; +-#else + if (power_tps65910_init(0)) + return; +-#endif + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. +@@ -472,10 +458,6 @@ + + if (first_time) { + enable_i2c0_pin_mux(); +-#if !CONFIG_IS_ENABLED(DM_I2C) +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, +- CONFIG_SYS_OMAP24_I2C_SLAVE); +-#endif + first_time = false; + } + } +diff -ruN u-boot-2021.10/board/ti/am335x/Makefile u-boot/board/ti/am335x/Makefile +--- u-boot-2021.10/board/ti/am335x/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am335x/Makefile 2021-11-01 17:10:14.092935117 +0100 +@@ -4,7 +4,7 @@ + # + # Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/ti/am335x/mux.c u-boot/board/ti/am335x/mux.c +--- u-boot-2021.10/board/ti/am335x/mux.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am335x/mux.c 2021-11-01 17:10:14.092935117 +0100 +@@ -345,14 +345,6 @@ + static unsigned short detect_daughter_board_profile(void) + { + unsigned short val; +- +-#if !CONFIG_IS_ENABLED(DM_I2C) +- if (i2c_probe(I2C_CPLD_ADDR)) +- return PROFILE_NONE; +- +- if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) +- return PROFILE_NONE; +-#else + struct udevice *dev = NULL; + int rc; + +@@ -362,7 +354,6 @@ + rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2); + if (rc) + return PROFILE_NONE; +-#endif + return (1 << (val & PROFILE_MASK)); + } + +diff -ruN u-boot-2021.10/board/ti/am335x/README u-boot/board/ti/am335x/README +--- u-boot-2021.10/board/ti/am335x/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am335x/README 1970-01-01 01:00:00.000000000 +0100 +@@ -1,205 +0,0 @@ +-Summary +-======= +- +-This document covers various features of the 'am335x_evm' build, and some of +-the related build targets (am335x_evm_uartN, etc). +- +-Hardware +-======== +- +-The binary produced by this board supports, based on parsing of the EEPROM +-documented in TI's reference designs: +-- AM335x GP EVM +-- AM335x EVM SK +-- Beaglebone White +-- Beaglebone Black +- +-Customization +-============= +- +-Given that all of the above boards are reference platforms (and the +-Beaglebone platforms are OSHA), it is likely that this platform code and +-configuration will be used as the basis of a custom platform. It is +-worth noting that aside from things such as NAND or MMC only being +-required if a custom platform makes use of these blocks, the following +-are required, depending on design: +- +-- GPIO is only required if DDR3 power is controlled in a way similar to +- EVM SK +-- SPI is only required for SPI flash, or exposing the SPI bus. +- +-The following blocks are required: +-- I2C, to talk with the PMIC and ensure that we do not run afoul of +- errata 1.0.24. +- +-When removing options as part of customization, +-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +-needs and to remove no longer relevant options as in some cases we +-define additional text blocks (such as for NAND or DFU strings). Also +-note that all of the SPL options are grouped together, rather than with +-the IP blocks, so both areas will need their choices updated to reflect +-the custom design. +- +-NAND +-==== +- +-The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In +-this example to program the NAND we assume that an SD card has been +-inserted with the files to write in the first SD slot and that mtdparts +-have been configured correctly for the board. All images are first loaded +-into memory, then written to NAND. +- +-Step-1: Building u-boot for NAND boot +- Set following CONFIGxx options for NAND device. +- CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page +- CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page +- CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block +- CONFIG_SYS_NAND_ECCPOS ECC map for NAND page +- CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) +- +-Step-2: Flashing NAND via MMC/SD +- # select BOOTSEL to MMC/SD boot and boot from MMC/SD card +- U-Boot # mmc rescan +- # erase flash +- U-Boot # nand erase.chip +- U-Boot # env default -f -a +- U-Boot # saveenv +- # flash MLO. Redundant copies of MLO are kept for failsafe +- U-Boot # load mmc 0 0x82000000 MLO +- U-Boot # nand write 0x82000000 0x00000 0x20000 +- U-Boot # nand write 0x82000000 0x20000 0x20000 +- U-Boot # nand write 0x82000000 0x40000 0x20000 +- U-Boot # nand write 0x82000000 0x60000 0x20000 +- # flash u-boot.img +- U-Boot # load mmc 0 0x82000000 u-boot.img +- U-Boot # nand write 0x82000000 0x80000 0x60000 +- # flash kernel image +- U-Boot # load mmc 0 0x82000000 uImage +- U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} +- # flash filesystem image +- U-Boot # load mmc 0 0x82000000 filesystem.img +- U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 +- +-Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. +- The device should boot from images flashed on NAND device. +- +-NOR +-=== +- +-The Beaglebone White can be equipped with a "memory cape" that in turn can +-have a NOR module plugged into it. In this case it is then possible to +-program and boot from NOR. Note that due to how U-Boot is designed we +-must build a specific version of U-Boot that knows we have NOR flash. This +-build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' +-build that will assume that the environment is on NOR rather than NAND. In +-the following example we assume that and SD card has been populated with +-MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the +-'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a +-binary must be written to the start of NOR, with no header or similar +-prepended. In the following example we use a size of 512KiB (0x80000) +-as that is how much space we set aside before the environment, as per +-the config file. +- +-U-Boot # mmc rescan +-U-Boot # load mmc 0 ${loadaddr} u-boot.bin +-U-Boot # protect off 08000000 +80000 +-U-Boot # erase 08000000 +80000 +-U-Boot # cp.b ${loadaddr} 08000000 ${filesize} +- +-Falcon Mode +-=========== +- +-The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, +-eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is +-to read a 'c' on the console while in SPL at any point prior to loading the +-OS payload (so as soon as possible) to opt to booting full U-Boot. Also +-note that while one can program Falcon Mode "in place" great care needs to +-be taken by the user to not 'brick' their setup. As these are all eval +-boards with multiple boot methods, recovery should not be an issue in this +-worst-case however. +- +-Falcon Mode: eMMC +-================= +- +-The recommended layout in this case is: +- +-MMC BLOCKS |--------------------------------| LOCATION IN BYTES +-0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 +-0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 +-0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 +-0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 +-0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 +-0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 +-0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 +- +-Note that when we run 'spl export' it will prepare to boot the kernel. +-This includes relocation of the uImage from where we loaded it to the entry +-point defined in the header. As these locations overlap by default, it +-would leave us with an image that if written to MMC will not boot, so +-instead of using the loadaddr variable we use 0x81000000 in the following +-example. In this example we are loading from the network, for simplicity, +-and assume a valid partition table already exists and 'mmc dev' has already +-been run to select the correct device. Also note that if you previously +-had a FAT partition (such as on a Beaglebone Black) it is not enough to +-write garbage into the area, you must delete it from the partition table +-first. +- +-# Ensure we are able to talk with this mmc device +-U-Boot # mmc rescan +-U-Boot # tftp 81000000 am335x/MLO +-# Write to two of the backup locations ROM uses +-U-Boot # mmc write 81000000 100 100 +-U-Boot # mmc write 81000000 200 100 +-# Write U-Boot to the location set in the config +-U-Boot # tftp 81000000 am335x/u-boot.img +-U-Boot # mmc write 81000000 300 400 +-# Load kernel and device tree into memory, perform export +-U-Boot # tftp 81000000 am335x/uImage +-U-Boot # run findfdt +-U-Boot # tftp ${fdtaddr} am335x/${fdtfile} +-U-Boot # run mmcargs +-U-Boot # spl export fdt 81000000 - ${fdtaddr} +-# Write the updated device tree to MMC +-U-Boot # mmc write ${fdtaddr} 80 80 +-# Write the uImage to MMC +-U-Boot # mmc write 81000000 900 2000 +- +-Falcon Mode: FAT SD cards +-========================= +- +-In this case the additional file is written to the filesystem. In this +-example we assume that the uImage and device tree to be used are already on +-the FAT filesystem (only the uImage MUST be for this to function +-afterwards) along with a Falcon Mode aware MLO and the FAT partition has +-already been created and marked bootable: +- +-U-Boot # mmc rescan +-# Load kernel and device tree into memory, perform export +-U-Boot # load mmc 0:1 ${loadaddr} uImage +-U-Boot # run findfdt +-U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} +-U-Boot # run mmcargs +-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +- +-This will print a number of lines and then end with something like: +- Using Device Tree in place at 80f80000, end 80f85928 +- Using Device Tree in place at 80f80000, end 80f88928 +-So then you: +- +-U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 +- +-Falcon Mode: NAND +-================= +- +-In this case the additional data is written to another partition of the +-NAND. In this example we assume that the uImage and device tree to be are +-already located on the NAND somewhere (such as filesystem or mtd partition) +-along with a Falcon Mode aware MLO written to the correct locations for +-booting and mtdparts have been configured correctly for the board: +- +-U-Boot # nand read ${loadaddr} kernel +-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb +-U-Boot # run nandargs +-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +-U-Boot # nand erase.part u-boot-spl-os +-U-Boot # nand write ${fdtaddr} u-boot-spl-os +diff -ruN u-boot-2021.10/board/ti/am43xx/board.c u-boot/board/ti/am43xx/board.c +--- u-boot-2021.10/board/ti/am43xx/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am43xx/board.c 2021-11-01 17:10:14.092935117 +0100 +@@ -56,7 +56,7 @@ + } + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + + const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ +@@ -393,13 +393,8 @@ + { + int mpu_vdd, ddr_volt; + +-#if !CONFIG_IS_ENABLED(DM_I2C) +- if (i2c_probe(TPS65218_CHIP_PM)) +- return; +-#else + if (power_tps65218_init(0)) + return; +-#endif + + switch (m) { + case 1000: +@@ -451,13 +446,8 @@ + { + int mpu_vdd; + +-#if !CONFIG_IS_ENABLED(DM_I2C) +- if (i2c_probe(TPS62362_I2C_ADDR)) +- return; +-#else + if (power_tps62362_init(0)) + return; +-#endif + + switch (m) { + case 1000: +@@ -492,10 +482,6 @@ + + if (first_time) { + enable_i2c0_pin_mux(); +-#if !CONFIG_IS_ENABLED(DM_I2C) +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, +- CONFIG_SYS_OMAP24_I2C_SLAVE); +-#endif + first_time = false; + } + } +@@ -632,28 +618,15 @@ + int power_init_board(void) + { + int rc; +-#if !CONFIG_IS_ENABLED(DM_I2C) +- struct pmic *p = NULL; +-#endif + if (board_is_idk()) { + rc = power_tps62362_init(0); + if (rc) + goto done; +-#if !CONFIG_IS_ENABLED(DM_I2C) +- p = pmic_get("TPS62362"); +- if (!p || pmic_probe(p)) +- goto done; +-#endif + puts("PMIC: TPS62362\n"); + } else { + rc = power_tps65218_init(0); + if (rc) + goto done; +-#if !CONFIG_IS_ENABLED(DM_I2C) +- p = pmic_get("TPS65218_PMIC"); +- if (!p || pmic_probe(p)) +- goto done; +-#endif + puts("PMIC: TPS65218\n"); + } + done: +diff -ruN u-boot-2021.10/board/ti/am43xx/Makefile u-boot/board/ti/am43xx/Makefile +--- u-boot-2021.10/board/ti/am43xx/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am43xx/Makefile 2021-11-01 17:10:14.092935117 +0100 +@@ -4,7 +4,7 @@ + # + # Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/ti/am57xx/board.c u-boot/board/ti/am57xx/board.c +--- u-boot-2021.10/board/ti/am57xx/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am57xx/board.c 2021-11-01 17:10:14.096268268 +0100 +@@ -144,13 +144,13 @@ + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, +- .emif_ddr_phy_ctlr_1_init = 0x0024400b, ++ .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, +- .emif_ddr_ext_phy_ctrl_1 = 0x10040100, +- .emif_ddr_ext_phy_ctrl_2 = 0x00910091, +- .emif_ddr_ext_phy_ctrl_3 = 0x00950095, +- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, +- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, ++ .emif_ddr_ext_phy_ctrl_1 = 0x10040100, ++ .emif_ddr_ext_phy_ctrl_2 = 0x00910091, ++ .emif_ddr_ext_phy_ctrl_3 = 0x00950095, ++ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, ++ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, +@@ -208,13 +208,13 @@ + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, +- .emif_ddr_phy_ctlr_1_init = 0x0024400b, ++ .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, +- .emif_ddr_ext_phy_ctrl_1 = 0x10040100, +- .emif_ddr_ext_phy_ctrl_2 = 0x00910091, +- .emif_ddr_ext_phy_ctrl_3 = 0x00950095, +- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, +- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, ++ .emif_ddr_ext_phy_ctrl_1 = 0x10040100, ++ .emif_ddr_ext_phy_ctrl_2 = 0x00910091, ++ .emif_ddr_ext_phy_ctrl_3 = 0x00950095, ++ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, ++ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, +diff -ruN u-boot-2021.10/board/ti/am57xx/mux_data.h u-boot/board/ti/am57xx/mux_data.h +--- u-boot-2021.10/board/ti/am57xx/mux_data.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/am57xx/mux_data.h 2021-11-01 17:10:14.096268268 +0100 +@@ -539,7 +539,7 @@ + {0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */ + {0x0888, 683, 0}, /* CFG_UART2_RXD_IN */ + {0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */ +- {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */ ++ {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */ + {0x0894, 835, 0}, /* CFG_UART2_TXD_IN */ + {0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */ + {0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */ +@@ -553,7 +553,7 @@ + {0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */ + {0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */ + {0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */ +- {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */ ++ {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */ + {0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */ + }; + +diff -ruN u-boot-2021.10/board/ti/panda/panda.c u-boot/board/ti/panda/panda.c +--- u-boot-2021.10/board/ti/panda/panda.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/panda/panda.c 2021-11-01 17:10:14.099601419 +0100 +@@ -312,6 +312,7 @@ + #endif + #endif + ++#ifdef CONFIG_REVISION_TAG + /* + * get_board_rev() - get board revision + */ +@@ -319,3 +320,4 @@ + { + return 0x20; + } ++#endif +diff -ruN u-boot-2021.10/board/ti/sdp4430/sdp.c u-boot/board/ti/sdp4430/sdp.c +--- u-boot-2021.10/board/ti/sdp4430/sdp.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/ti/sdp4430/sdp.c 2021-11-01 17:10:14.099601419 +0100 +@@ -104,6 +104,7 @@ + } + #endif /* CONFIG_SPL_OS_BOOT */ + ++#ifdef CONFIG_REVISION_TAG + /* + * get_board_rev() - get board revision + */ +@@ -111,3 +112,4 @@ + { + return 0x20; + } ++#endif +diff -ruN u-boot-2021.10/board/toradex/apalis_imx6/apalis_imx6.c u-boot/board/toradex/apalis_imx6/apalis_imx6.c +--- u-boot-2021.10/board/toradex/apalis_imx6/apalis_imx6.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/apalis_imx6/apalis_imx6.c 2021-11-01 17:10:14.102934570 +0100 +@@ -707,12 +707,11 @@ + #ifdef CONFIG_BOARD_LATE_INIT + int board_late_init(void) + { +-#if defined(CONFIG_REVISION_TAG) && \ +- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) ++#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) + char env_str[256]; + u32 rev; + +- rev = get_board_rev(); ++ rev = get_board_revision(); + snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); + env_set("board_rev", env_str); + +diff -ruN u-boot-2021.10/board/toradex/apalis_imx6/Kconfig u-boot/board/toradex/apalis_imx6/Kconfig +--- u-boot-2021.10/board/toradex/apalis_imx6/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/apalis_imx6/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -48,7 +48,6 @@ + This option configures DCE mode unconditionally. Whithout this + option the config block stating V1.0 HW selects DCE mode, + otherwise the UARTs are configuered in DTE mode. +- default n + + source "board/toradex/common/Kconfig" + +diff -ruN u-boot-2021.10/board/toradex/apalis-imx8/Kconfig u-boot/board/toradex/apalis-imx8/Kconfig +--- u-boot-2021.10/board/toradex/apalis-imx8/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/apalis-imx8/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -25,6 +25,9 @@ + config TDX_CFG_BLOCK_OFFSET + default "-512" + ++config IMX_CONFIG ++ default "board/toradex/apalis-imx8/apalis-imx8-imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/apalis-imx8x/Kconfig u-boot/board/toradex/apalis-imx8x/Kconfig +--- u-boot-2021.10/board/toradex/apalis-imx8x/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/apalis-imx8x/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -25,6 +25,9 @@ + config TDX_CFG_BLOCK_OFFSET + default "-512" + ++config IMX_CONFIG ++ default "board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/colibri_imx6/colibri_imx6.c u-boot/board/toradex/colibri_imx6/colibri_imx6.c +--- u-boot-2021.10/board/toradex/colibri_imx6/colibri_imx6.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/colibri_imx6/colibri_imx6.c 2021-11-01 17:10:14.102934570 +0100 +@@ -611,12 +611,11 @@ + #ifdef CONFIG_BOARD_LATE_INIT + int board_late_init(void) + { +-#if defined(CONFIG_REVISION_TAG) && \ +- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) ++#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) + char env_str[256]; + u32 rev; + +- rev = get_board_rev(); ++ rev = get_board_revision(); + snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); + env_set("board_rev", env_str); + #endif +diff -ruN u-boot-2021.10/board/toradex/colibri-imx6ull/Kconfig u-boot/board/toradex/colibri-imx6ull/Kconfig +--- u-boot-2021.10/board/toradex/colibri-imx6ull/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/colibri-imx6ull/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -24,6 +24,9 @@ + config TDX_CFG_BLOCK_2ND_ETHADDR + default y + ++config IMX_CONFIG ++ default "board/toradex/colibri-imx6ull/imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/colibri_imx7/Kconfig u-boot/board/toradex/colibri_imx7/Kconfig +--- u-boot-2021.10/board/toradex/colibri_imx7/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/colibri_imx7/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -71,6 +71,9 @@ + + endif + ++config IMX_CONFIG ++ default "board/toradex/colibri_imx7/imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/colibri-imx8x/Kconfig u-boot/board/toradex/colibri-imx8x/Kconfig +--- u-boot-2021.10/board/toradex/colibri-imx8x/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/colibri-imx8x/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -25,6 +25,9 @@ + config TDX_CFG_BLOCK_OFFSET + default "-512" + ++config IMX_CONFIG ++ default "board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/colibri_vf/Kconfig u-boot/board/toradex/colibri_vf/Kconfig +--- u-boot-2021.10/board/toradex/colibri_vf/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/colibri_vf/Kconfig 2021-11-01 17:10:14.102934570 +0100 +@@ -21,6 +21,9 @@ + config TDX_CFG_BLOCK_2ND_ETHADDR + default y + ++config IMX_CONFIG ++ default "board/toradex/colibri_vf/imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/toradex/common/tdx-cfg-block.c u-boot/board/toradex/common/tdx-cfg-block.c +--- u-boot-2021.10/board/toradex/common/tdx-cfg-block.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/common/tdx-cfg-block.c 2021-11-01 17:10:14.106267721 +0100 +@@ -493,24 +493,24 @@ + else + tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; + } +-#ifdef CONFIG_MACH_TYPE ++#if defined(CONFIG_TARGET_APALIS_T30) || defined(CONFIG_TARGET_COLIBRI_T30) + else if (!strcmp("tegra30", soc)) { +- if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) { +- if (it == 'y' || it == 'Y') +- tdx_hw_tag.prodid = APALIS_T30_IT; +- else +- if (gd->ram_size == 0x40000000) +- tdx_hw_tag.prodid = APALIS_T30_1GB; +- else +- tdx_hw_tag.prodid = APALIS_T30_2GB; +- } else { +- if (it == 'y' || it == 'Y') +- tdx_hw_tag.prodid = COLIBRI_T30_IT; ++#ifdef CONFIG_TARGET_APALIS_T30 ++ if (it == 'y' || it == 'Y') ++ tdx_hw_tag.prodid = APALIS_T30_IT; ++ else ++ if (gd->ram_size == 0x40000000) ++ tdx_hw_tag.prodid = APALIS_T30_1GB; + else +- tdx_hw_tag.prodid = COLIBRI_T30; +- } ++ tdx_hw_tag.prodid = APALIS_T30_2GB; ++#else ++ if (it == 'y' || it == 'Y') ++ tdx_hw_tag.prodid = COLIBRI_T30_IT; ++ else ++ tdx_hw_tag.prodid = COLIBRI_T30; ++#endif + } +-#endif /* CONFIG_MACH_TYPE */ ++#endif /* CONFIG_TARGET_APALIS_T30 || CONFIG_TARGET_COLIBRI_T30 */ + else if (!strcmp("tegra124", soc)) { + tdx_hw_tag.prodid = APALIS_TK1_2GB; + } else if (!strcmp("vf500", soc)) { +diff -ruN u-boot-2021.10/board/toradex/common/tdx-common.c u-boot/board/toradex/common/tdx-common.c +--- u-boot-2021.10/board/toradex/common/tdx-common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/common/tdx-common.c 2021-11-01 17:10:14.106267721 +0100 +@@ -32,8 +32,8 @@ + static char *tdx_carrier_board_name; + #endif + +-#ifdef CONFIG_REVISION_TAG +-u32 get_board_rev(void) ++#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) ++u32 get_board_revision(void) + { + /* Check validity */ + if (!tdx_hw_tag.ver_major) +@@ -183,8 +183,8 @@ + + #else /* CONFIG_TDX_CFG_BLOCK */ + +-#ifdef CONFIG_REVISION_TAG +-u32 get_board_rev(void) ++#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) ++u32 get_board_revision(void) + { + return 0; + } +diff -ruN u-boot-2021.10/board/toradex/common/tdx-common.h u-boot/board/toradex/common/tdx-common.h +--- u-boot-2021.10/board/toradex/common/tdx-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/common/tdx-common.h 2021-11-01 17:10:14.106267721 +0100 +@@ -10,6 +10,7 @@ + #define TDX_USB_VID 0x1B67 + + int ft_common_board_setup(void *blob, struct bd_info *bd); ++u32 get_board_revision(void); + + #if defined(CONFIG_DM_VIDEO) + int show_boot_logo(void); +diff -ruN u-boot-2021.10/board/toradex/verdin-imx8mm/Kconfig u-boot/board/toradex/verdin-imx8mm/Kconfig +--- u-boot-2021.10/board/toradex/verdin-imx8mm/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/toradex/verdin-imx8mm/Kconfig 2021-11-01 17:10:14.106267721 +0100 +@@ -31,6 +31,9 @@ + config TDX_CFG_BLOCK_OFFSET + default "-512" + ++config IMX_CONFIG ++ default "board/toradex/verdin-imx8mm/imximage.cfg" ++ + source "board/toradex/common/Kconfig" + + endif +diff -ruN u-boot-2021.10/board/tplink/wdr4300/wdr4300.c u-boot/board/tplink/wdr4300/wdr4300.c +--- u-boot-2021.10/board/tplink/wdr4300/wdr4300.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/tplink/wdr4300/wdr4300.c 2021-11-01 17:10:14.106267721 +0100 +@@ -71,7 +71,7 @@ + wdr4300_pinmux_config(); + #endif + +-#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + ar934x_pll_init(560, 480, 240); + ar934x_ddr_init(560, 480, 240); + #endif +diff -ruN u-boot-2021.10/board/tqc/tqma6/tqma6.c u-boot/board/tqc/tqma6/tqma6.c +--- u-boot-2021.10/board/tqc/tqma6/tqma6.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/tqc/tqma6/tqma6.c 2021-11-01 17:10:14.106267721 +0100 +@@ -171,7 +171,7 @@ + #endif + #endif + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + static struct i2c_pads_info tqma6_i2c3_pads = { + /* I2C3: on board LM75, M24C64, */ + .scl = { +@@ -216,7 +216,7 @@ + #ifndef CONFIG_DM_SPI + tqma6_iomuxc_spi(); + #endif +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + tqma6_setup_i2c(); + #endif + +@@ -247,7 +247,7 @@ + }; + } + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + /* setup board specific PMIC */ + int power_init_board(void) + { +diff -ruN u-boot-2021.10/board/udoo/neo/neo.c u-boot/board/udoo/neo/neo.c +--- u-boot-2021.10/board/udoo/neo/neo.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/udoo/neo/neo.c 2021-11-01 17:10:14.106267721 +0100 +@@ -96,7 +96,7 @@ + }; + #endif + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + int power_init_board(void) + { + struct pmic *p; +diff -ruN u-boot-2021.10/board/varisys/common/eeprom.h u-boot/board/varisys/common/eeprom.h +--- u-boot-2021.10/board/varisys/common/eeprom.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/varisys/common/eeprom.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,6 +0,0 @@ +-/* EEPROM init functions for Cyrus */ +- +- +-void init_eeprom(int bus_num, int addr, int addr_len); +-void mac_read_from_fixed_id(void); +-int mac_read_from_eeprom_common(void); +diff -ruN u-boot-2021.10/board/varisys/common/Makefile u-boot/board/varisys/common/Makefile +--- u-boot-2021.10/board/varisys/common/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/varisys/common/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,21 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0+ +-# +-# (C) Copyright 2006 +-# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- +-MINIMAL= +- +-ifdef CONFIG_SPL_BUILD +-ifdef CONFIG_SPL_INIT_MINIMAL +-MINIMAL=y +-endif +-endif +- +-ifdef MINIMAL +-# necessary to create built-in.o +-obj- := __dummy__.o +-else +-ifndef CONFIG_SPL_BUILD +-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o +-endif +-endif +diff -ruN u-boot-2021.10/board/varisys/common/sys_eeprom.c u-boot/board/varisys/common/sys_eeprom.c +--- u-boot-2021.10/board/varisys/common/sys_eeprom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/varisys/common/sys_eeprom.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,500 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Based on board/freescale/common/sys_eeprom.c +- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor +- * +- * This defines the API for storing board information in the +- * eeprom. It has been adapted from an earlier version of the +- * Freescale API, but has a number of key differences. Because +- * the two APIs are independent and may diverge further, the +- * Varisys version of the API is implemented separately here. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "eeprom.h" +- +-#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC +-#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC +-#else +-#define MAX_NUM_PORTS 8 +-#endif +-#define NXID_VERSION 0 +- +-/** +- * static eeprom: EEPROM layout for NXID formats +- * +- * See Freescale application note AN3638 for details. +- */ +-static struct __attribute__ ((__packed__)) eeprom { +- u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ +- u8 sn[12]; /* 0x04 - 0x0F Serial Number */ +- u8 errata[5]; /* 0x10 - 0x14 Errata Level */ +- u8 date[6]; /* 0x15 - 0x1a Build Date */ +- u8 res_0; /* 0x1b Reserved */ +- u32 version; /* 0x1c - 0x1f NXID Version */ +- u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ +- u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ +- u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ +- u8 res_1[21]; /* 0x2b - 0x3f Reserved */ +- u8 mac_count; /* 0x40 Number of MAC addresses */ +- u8 mac_flag; /* 0x41 MAC table flags */ +- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ +- u32 crc; /* x+1 CRC32 checksum */ +-} e; +- +-/* Set to 1 if we've read EEPROM into memory */ +-static int has_been_read; +- +-/* Is this a valid NXID EEPROM? */ +-#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ +- (e.id[2] == 'I') || (e.id[3] == 'D')) +- +-/** Fixed ID field in EEPROM */ +-static unsigned char uid[16]; +- +-static int eeprom_bus_num = -1; +-static int eeprom_addr; +-static int eeprom_addr_len; +- +-/** +- * This must be called before any eeprom access. +- */ +-void init_eeprom(int bus_num, int addr, int addr_len) +-{ +- eeprom_bus_num = bus_num; +- eeprom_addr = addr; +- eeprom_addr_len = addr_len; +-} +- +-/** +- * show_eeprom - display the contents of the EEPROM +- */ +-void show_eeprom(void) +-{ +- int i; +- unsigned int crc; +- +- /* EEPROM tag ID, either CCID or NXID */ +- printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], +- be32_to_cpu(e.version)); +- +- /* Serial number */ +- printf("SN: %s\n", e.sn); +- +- printf("UID: "); +- for (i = 0; i < 16; i++) +- printf("%02x", uid[i]); +- printf("\n"); +- +- /* Errata level. */ +- printf("Errata: %s\n", e.errata); +- +- /* Build date, BCD date values, as YYMMDDhhmmss */ +- printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", +- e.date[0], e.date[1], e.date[2], +- e.date[3] & 0x7F, e.date[4], e.date[5], +- e.date[3] & 0x80 ? "PM" : ""); +- +- /* Show MAC addresses */ +- for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { +- u8 *p = e.mac[i]; +- +- printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i, +- p[0], p[1], p[2], p[3], p[4], p[5]); +- } +- +- crc = crc32(0, (void *)&e, sizeof(e) - 4); +- +- if (crc == be32_to_cpu(e.crc)) +- printf("CRC: %08x\n", be32_to_cpu(e.crc)); +- else +- printf("CRC: %08x (should be %08x)\n", +- be32_to_cpu(e.crc), crc); +- +-#ifdef DEBUG +- printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); +- for (i = 0; i < sizeof(e); i++) { +- if ((i % 16) == 0) +- printf("%02X: ", i); +- printf("%02X ", ((u8 *)&e)[i]); +- if (((i % 16) == 15) || (i == sizeof(e) - 1)) +- printf("\n"); +- } +-#endif +-} +- +-/** +- * read_eeprom - read the EEPROM into memory +- */ +-int read_eeprom(void) +-{ +- int ret; +- unsigned int bus; +- +- if (eeprom_bus_num < 0) { +- printf("EEPROM not configured\n"); +- return -1; +- } +- +- if (has_been_read) +- return 0; +- +- bus = i2c_get_bus_num(); +- i2c_set_bus_num(eeprom_bus_num); +- +- ret = i2c_read(eeprom_addr, 0, eeprom_addr_len, +- (void *)&e, sizeof(e)); +- +- +- /* Fixed address of ID field */ +- i2c_read(0x5f, 0x80, 1, uid, 16); +- +- i2c_set_bus_num(bus); +- +-#ifdef DEBUG +- show_eeprom(); +-#endif +- +- has_been_read = (ret == 0) ? 1 : 0; +- +- return ret; +-} +- +-/** +- * update_crc - update the CRC +- * +- * This function should be called after each update to the EEPROM structure, +- * to make sure the CRC is always correct. +- */ +-static void update_crc(void) +-{ +- u32 crc, crc_offset = offsetof(struct eeprom, crc); +- +- crc = crc32(0, (void *)&e, crc_offset); +- e.crc = cpu_to_be32(crc); +-} +- +-/** +- * prog_eeprom - write the EEPROM from memory +- */ +-static int prog_eeprom(void) +-{ +- int ret = 0; +- int i; +- void *p; +- unsigned int bus; +- +- if (eeprom_bus_num < 0) { +- printf("EEPROM not configured\n"); +- return -1; +- } +- +- /* Set the reserved values to 0xFF */ +- e.res_0 = 0xFF; +- memset(e.res_1, 0xFF, sizeof(e.res_1)); +- update_crc(); +- +- bus = i2c_get_bus_num(); +- i2c_set_bus_num(eeprom_bus_num); +- +- /* +- * The AT24C02 datasheet says that data can only be written in page +- * mode, which means 8 bytes at a time, and it takes up to 5ms to +- * complete a given write. +- */ +- for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { +- ret = i2c_write(eeprom_addr, i, eeprom_addr_len, +- p, min((int)(sizeof(e) - i), 8)); +- if (ret) +- break; +- udelay(5000); /* 5ms write cycle timing */ +- } +- +- if (!ret) { +- /* Verify the write by reading back the EEPROM and comparing */ +- struct eeprom e2; +- +- ret = i2c_read(eeprom_addr, 0, +- eeprom_addr_len, (void *)&e2, sizeof(e2)); +- if (!ret && memcmp(&e, &e2, sizeof(e))) +- ret = -1; +- } +- +- i2c_set_bus_num(bus); +- +- if (ret) { +- printf("Programming failed.\n"); +- has_been_read = 0; +- return -1; +- } +- +- printf("Programming passed.\n"); +- return 0; +-} +- +-/** +- * h2i - converts hex character into a number +- * +- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns +- * the integer equivalent. +- */ +-static inline u8 h2i(char p) +-{ +- if ((p >= '0') && (p <= '9')) +- return p - '0'; +- +- if ((p >= 'A') && (p <= 'F')) +- return (p - 'A') + 10; +- +- if ((p >= 'a') && (p <= 'f')) +- return (p - 'a') + 10; +- +- return 0; +-} +- +-/** +- * set_date - stores the build date into the EEPROM +- * +- * This function takes a pointer to a string in the format "YYMMDDhhmmss" +- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, +- * and stores it in the build date field of the EEPROM local copy. +- */ +-static void set_date(const char *string) +-{ +- unsigned int i; +- +- if (strlen(string) != 12) { +- printf("Usage: mac date YYMMDDhhmmss\n"); +- return; +- } +- +- for (i = 0; i < 6; i++) +- e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); +- +- update_crc(); +-} +- +-/** +- * set_mac_address - stores a MAC address into the EEPROM +- * +- * This function takes a pointer to MAC address string +- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and +- * stores it in one of the MAC address fields of the EEPROM local copy. +- */ +-static void set_mac_address(unsigned int index, const char *string) +-{ +- char *p = (char *)string; +- unsigned int i; +- +- if ((index >= MAX_NUM_PORTS) || !string) { +- printf("Usage: mac XX:XX:XX:XX:XX:XX\n"); +- return; +- } +- +- for (i = 0; *p && (i < 6); i++) { +- e.mac[index][i] = hextoul(p, &p); +- if (*p == ':') +- p++; +- } +- +- update_crc(); +-} +- +-int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +-{ +- char cmd; +- +- if (argc == 1) { +- show_eeprom(); +- return 0; +- } +- +- cmd = argv[1][0]; +- +- if (cmd == 'r') { +- read_eeprom(); +- return 0; +- } +- +- if (cmd == 'i') { +- memcpy(e.id, "NXID", sizeof(e.id)); +- e.version = NXID_VERSION; +- update_crc(); +- return 0; +- } +- +- if (!is_valid) { +- printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n"); +- return 0; +- } +- +- if (argc == 2) { +- switch (cmd) { +- case 's': /* save */ +- prog_eeprom(); +- break; +- default: +- return cmd_usage(cmdtp); +- } +- +- return 0; +- } +- +- /* We know we have at least one parameter */ +- +- switch (cmd) { +- case 'n': /* serial number */ +- memset(e.sn, 0, sizeof(e.sn)); +- strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); +- update_crc(); +- break; +- case 'e': /* errata */ +- memset(e.errata, 0, 5); +- strncpy((char *)e.errata, argv[2], 4); +- update_crc(); +- break; +- case 'd': /* date BCD format YYMMDDhhmmss */ +- set_date(argv[2]); +- break; +- case 'p': /* MAC table size */ +- e.mac_count = hextoul(argv[2], NULL); +- update_crc(); +- break; +- case '0' ... '9': /* "mac 0" through "mac 22" */ +- set_mac_address(dectoul(argv[1], NULL), argv[2]); +- break; +- case 'h': /* help */ +- default: +- return cmd_usage(cmdtp); +- } +- +- return 0; +-} +- +-int mac_read_from_generic_eeprom(const char *envvar, int chip, +- int address, int mac_bus) +-{ +- int ret; +- unsigned int bus; +- unsigned char mac[6]; +- char ethaddr[18]; +- +- bus = i2c_get_bus_num(); +- i2c_set_bus_num(mac_bus); +- +- ret = i2c_read(chip, address, 1, mac, 6); +- +- i2c_set_bus_num(bus); +- +- if (!ret) { +- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", +- mac[0], +- mac[1], +- mac[2], +- mac[3], +- mac[4], +- mac[5]); +- +- printf("MAC: %s\n", ethaddr); +- env_set(envvar, ethaddr); +- } +- +- return ret; +-} +- +-void mac_read_from_fixed_id(void) +-{ +-#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR +- mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR, +- CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS); +-#endif +-#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR +- mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR, +- CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS); +-#endif +-} +- +-/** +- * mac_read_from_eeprom - read the MAC addresses from EEPROM +- * +- * This function reads the MAC addresses from EEPROM and sets the +- * appropriate environment variables for each one read. +- * +- * The environment variables are only set if they haven't been set already. +- * This ensures that any user-saved variables are never overwritten. +- * +- * This function must be called after relocation. +- * +- * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 +- * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is +- * located at a different offset. +- */ +-int mac_read_from_eeprom_common(void) +-{ +- unsigned int i; +- u32 crc, crc_offset = offsetof(struct eeprom, crc); +- u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ +- +- puts("EEPROM: "); +- +- if (read_eeprom()) { +- printf("Read failed.\n"); +- return 0; +- } +- +- if (!is_valid) { +- printf("Invalid ID (%02x %02x %02x %02x)\n", +- e.id[0], e.id[1], e.id[2], e.id[3]); +- return 0; +- } +- +- crc = crc32(0, (void *)&e, crc_offset); +- crcp = (void *)&e + crc_offset; +- if (crc != be32_to_cpu(*crcp)) { +- printf("CRC mismatch (%08x != %08x)\n", crc, +- be32_to_cpu(e.crc)); +- return 0; +- } +- +- /* +- * MAC address #9 in v1 occupies the same position as the CRC in v0. +- * Erase it so that it's not mistaken for a MAC address. We'll +- * update the CRC later. +- */ +- if (e.version == 0) +- memset(e.mac[8], 0xff, 6); +- +- for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { +- if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && +- memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { +- char ethaddr[18]; +- char enetvar[9]; +- +- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", +- e.mac[i][0], +- e.mac[i][1], +- e.mac[i][2], +- e.mac[i][3], +- e.mac[i][4], +- e.mac[i][5]); +- sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); +- /* Only initialize environment variables that are blank +- * (i.e. have not yet been set) +- */ +- if (!env_get(enetvar)) +- env_set(enetvar, ethaddr); +- } +- } +- +- printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], +- be32_to_cpu(e.version)); +- +- return 0; +-} +diff -ruN u-boot-2021.10/board/vscom/baltos/board.c u-boot/board/vscom/baltos/board.c +--- u-boot-2021.10/board/vscom/baltos/board.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/vscom/baltos/board.c 2021-11-01 17:10:14.106267721 +0100 +@@ -187,7 +187,7 @@ + */ + i2c_set_bus_num(1); + +- printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED); ++ printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED); + + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { + puts("i2c: cannot access TPS65910\n"); +diff -ruN u-boot-2021.10/board/vscom/baltos/Makefile u-boot/board/vscom/baltos/Makefile +--- u-boot-2021.10/board/vscom/baltos/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/vscom/baltos/Makefile 2021-11-01 17:10:14.106267721 +0100 +@@ -4,7 +4,7 @@ + # + # Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) ++ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) + obj-y := mux.o + endif + +diff -ruN u-boot-2021.10/board/warp/Kconfig u-boot/board/warp/Kconfig +--- u-boot-2021.10/board/warp/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/warp/Kconfig 2021-11-01 17:10:14.109600872 +0100 +@@ -6,4 +6,7 @@ + config SYS_CONFIG_NAME + default "warp" + ++config IMX_CONFIG ++ default "board/warp/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/warp7/Kconfig u-boot/board/warp7/Kconfig +--- u-boot-2021.10/board/warp7/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/warp7/Kconfig 2021-11-01 17:10:14.109600872 +0100 +@@ -20,4 +20,7 @@ + help + The address the FDT file should be loaded to. + ++config IMX_CONFIG ++ default "board/warp7/imximage.cfg" ++ + endif +diff -ruN u-boot-2021.10/board/warp7/README u-boot/board/warp7/README +--- u-boot-2021.10/board/warp7/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/warp7/README 2021-11-01 17:10:14.109600872 +0100 +@@ -19,7 +19,7 @@ + + This will generate the U-Boot binary called u-boot-dtb.imx. + +-Put warp7 board in USB download mode: ++Put warp7 board in USB download mode: + + Remove the CPU board from the base board then put switch 2 in the upper + position +diff -ruN u-boot-2021.10/board/warp7/warp7.c u-boot/board/warp7/warp7.c +--- u-boot-2021.10/board/warp7/warp7.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/warp7/warp7.c 2021-11-01 17:10:14.109600872 +0100 +@@ -134,7 +134,7 @@ + int board_late_init(void) + { + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +-#ifdef CONFIG_SERIAL_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + struct tag_serialnr serialnr; + char serial_string[0x20]; + #endif +@@ -156,7 +156,7 @@ + env_set_ulong(HAB_ENABLED_ENVNAME, 0); + #endif + +-#ifdef CONFIG_SERIAL_TAG ++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", +diff -ruN u-boot-2021.10/board/work-microwave/work_92105/work_92105_display.c u-boot/board/work-microwave/work_92105/work_92105_display.c +--- u-boot-2021.10/board/work-microwave/work_92105/work_92105_display.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/board/work-microwave/work_92105/work_92105_display.c 2021-11-01 17:10:14.109600872 +0100 +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +diff -ruN u-boot-2021.10/board/xen/xenguest_arm64/xenguest_arm64.c u-boot/board/xen/xenguest_arm64/xenguest_arm64.c +diff -ruN u-boot-2021.10/board/xes/common/actl_nand.c u-boot/board/xes/common/actl_nand.c +diff -ruN u-boot-2021.10/board/xilinx/versal/cmds.c u-boot/board/xilinx/versal/cmds.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/board.c u-boot/board/xilinx/zynq/board.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-cse-qspi-single/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-cse-qspi-single/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +diff -ruN u-boot-2021.10/board/xilinx/zynqmp/zynqmp.c u-boot/board/xilinx/zynqmp/zynqmp.c +diff -ruN u-boot-2021.10/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c u-boot/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c +diff -ruN u-boot-2021.10/cmd/bedbug.c u-boot/cmd/bedbug.c +--- u-boot-2021.10/cmd/bedbug.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/bedbug.c 2021-11-01 17:10:14.129599778 +0100 +@@ -39,7 +39,6 @@ + } /* bedbug_puts */ + + +- + /* ====================================================================== + * Initialize the bug_ctx structure used by the bedbug debugger. This is + * specific to the CPU since each has different debug registers and +@@ -53,7 +52,6 @@ + } /* bedbug_init */ + + +- + /* ====================================================================== + * Entry point from the interpreter to the disassembler. Repeated calls + * will resume from the last disassembled address. +@@ -183,7 +181,6 @@ + } /* do_bedbug_breakpoint */ + + +- + /* ====================================================================== + * Called from the CPU-specific breakpoint handling routine. Enter a + * mini main loop until the stopped flag is cleared from the breakpoint +@@ -241,7 +238,6 @@ + } /* bedbug_main_loop */ + + +- + /* ====================================================================== + * Interpreter command to continue from a breakpoint. Just clears the + * stopped flag in the context so that the breakpoint routine will +diff -ruN u-boot-2021.10/cmd/cramfs.c u-boot/cmd/cramfs.c +--- u-boot-2021.10/cmd/cramfs.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/cramfs.c 2021-11-01 17:10:14.132932929 +0100 +@@ -3,7 +3,7 @@ + * + * based on: cmd_jffs2.c + * +- * Add support for a CRAMFS located in RAM ++ * Add support for a CRAMFS located in RAM + */ + + +diff -ruN u-boot-2021.10/cmd/date.c u-boot/cmd/date.c +--- u-boot-2021.10/cmd/date.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/date.c 2021-11-01 17:10:14.132932929 +0100 +@@ -49,7 +49,7 @@ + return CMD_RET_FAILURE; + } + } +-#elif defined(CONFIG_SYS_I2C_LEGACY) ++#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); + #else +@@ -122,7 +122,7 @@ + } + + /* switch back to original I2C bus */ +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + i2c_set_bus_num(old_bus); + #elif !defined(CONFIG_DM_RTC) + I2C_SET_BUS(old_bus); +diff -ruN u-boot-2021.10/cmd/eeprom.c u-boot/cmd/eeprom.c +--- u-boot-2021.10/cmd/eeprom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/eeprom.c 2021-11-01 17:10:14.132932929 +0100 +@@ -15,7 +15,7 @@ + * degradation (typical for EEPROM) is incured for FRAM memory: + * + * #define CONFIG_SYS_I2C_FRAM +- * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS ++ * Set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to 0 + * + */ + +@@ -27,18 +27,6 @@ + #include + #include + +-#ifndef CONFIG_SYS_I2C_SPEED +-#define CONFIG_SYS_I2C_SPEED 50000 +-#endif +- +-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0 +-#endif +- +-#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8 +-#endif +- + #ifndef I2C_RXTX_LEN + #define I2C_RXTX_LEN 128 + #endif +@@ -46,21 +34,6 @@ + #define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) + #define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) + +-/* +- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is +- * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. +- * +- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is +- * 0x00000nxx for EEPROM address selectors and page number at n. +- */ +-#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C) +-#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \ +- (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \ +- (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2) +-#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2 +-#endif +-#endif +- + #if CONFIG_IS_ENABLED(DM_I2C) + static int eeprom_i2c_bus; + #endif +@@ -75,13 +48,20 @@ + /* I2C EEPROM */ + #if CONFIG_IS_ENABLED(DM_I2C) + eeprom_i2c_bus = bus; +-#elif defined(CONFIG_SYS_I2C_LEGACY) ++#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + if (bus >= 0) + i2c_set_bus_num(bus); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + #endif + } + ++/* ++ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is ++ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. ++ * ++ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is ++ * 0x00000nxx for EEPROM address selectors and page number at n. ++ */ + static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr) + { + unsigned blk_off; +@@ -183,8 +163,10 @@ + buffer += len; + offset += len; + ++#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0 + if (!read) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); ++#endif + } + + return rcode; +@@ -243,10 +225,10 @@ + int argc_no_bus = argc_no_bus_addr + 1; + int argc_bus_addr = argc_no_bus_addr + 2; + +-#ifdef CONFIG_SYS_DEF_EEPROM_ADDR ++#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + if (argc == argc_no_bus_addr) { + *i2c_bus = -1; +- *i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR; ++ *i2c_addr = CONFIG_SYS_I2C_EEPROM_ADDR; + + return 0; + } +diff -ruN u-boot-2021.10/cmd/fdt.c u-boot/cmd/fdt.c +--- u-boot-2021.10/cmd/fdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/fdt.c 2021-11-01 17:10:14.132932929 +0100 +@@ -624,7 +624,7 @@ + fdt_strerror(err)); + return CMD_RET_FAILURE; + } +-#ifdef CONFIG_SOC_KEYSTONE ++#ifdef CONFIG_ARCH_KEYSTONE + ft_board_setup_ex(working_fdt, gd->bd); + #endif + } +diff -ruN u-boot-2021.10/cmd/i2c.c u-boot/cmd/i2c.c +--- u-boot-2021.10/cmd/i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/i2c.c 2021-11-01 17:10:14.136266080 +0100 +@@ -98,7 +98,7 @@ + * pairs. The following macros take care of this */ + + #if defined(CONFIG_SYS_I2C_NOPROBES) +-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) + static struct + { + uchar bus; +@@ -114,7 +114,7 @@ + #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ + #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) + #define NO_PROBE_ADDR(i) i2c_no_probes[(i)] +-#endif /* defined(CONFIG_SYS_I2C_LEGACY) */ ++#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */ + #endif + + #define DISP_LINE_LEN 16 +@@ -195,54 +195,6 @@ + { + } + +-/* TODO: Implement architecture-specific get/set functions */ +- +-/** +- * i2c_get_bus_speed() - Return I2C bus speed +- * +- * This function is the default implementation of function for retrieveing +- * the current I2C bus speed in Hz. +- * +- * A driver implementing runtime switching of I2C bus speed must override +- * this function to report the speed correctly. Simple or legacy drivers +- * can use this fallback. +- * +- * Returns I2C bus speed in Hz. +- */ +-#if !defined(CONFIG_SYS_I2C_LEGACY) && !CONFIG_IS_ENABLED(DM_I2C) +-/* +- * TODO: Implement architecture-specific get/set functions +- * Should go away, if we switched completely to new multibus support +- */ +-__weak +-unsigned int i2c_get_bus_speed(void) +-{ +- return CONFIG_SYS_I2C_SPEED; +-} +- +-/** +- * i2c_set_bus_speed() - Configure I2C bus speed +- * @speed: Newly set speed of the I2C bus in Hz +- * +- * This function is the default implementation of function for setting +- * the I2C bus speed in Hz. +- * +- * A driver implementing runtime switching of I2C bus speed must override +- * this function to report the speed correctly. Simple or legacy drivers +- * can use this fallback. +- * +- * Returns zero on success, negative value on error. +- */ +-__weak +-int i2c_set_bus_speed(unsigned int speed) +-{ +- if (speed != CONFIG_SYS_I2C_SPEED) +- return -1; +- +- return 0; +-} +-#endif +- + /** + * get_alen() - Small parser helper function to get address length + * +@@ -922,7 +874,7 @@ + if (ret) + return i2c_report_err(ret, + I2C_ERR_WRITE); +-#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS ++#if CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS > 0 + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + #endif + if (incrflag) +@@ -1725,7 +1677,7 @@ + * + * Returns zero always. + */ +-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) + static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) + { +@@ -1811,7 +1763,7 @@ + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ + CONFIG_IS_ENABLED(DM_I2C) + static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +@@ -1834,7 +1786,7 @@ + printf("Current bus is %d\n", bus_no); + } else { + bus_no = dectoul(argv[1], NULL); +-#if defined(CONFIG_SYS_I2C_LEGACY) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { + printf("Invalid bus %d\n", bus_no); + return -1; +@@ -1852,7 +1804,7 @@ + + return ret ? CMD_RET_FAILURE : 0; + } +-#endif /* defined(CONFIG_SYS_I2C_LEGACY) */ ++#endif /* CONFIG_IS_ENABLED(SYS_I2C_LEGACY) */ + + /** + * do_i2c_bus_speed() - Handle the "i2c speed" command-line command +@@ -1951,20 +1903,18 @@ + printf("Error: Not supported by the driver\n"); + return CMD_RET_FAILURE; + } +-#elif defined(CONFIG_SYS_I2C_LEGACY) ++#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); +-#else +- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + #endif + return 0; + } + + static struct cmd_tbl cmd_i2c_sub[] = { +-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) + U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""), + #endif + U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), +-#if defined(CONFIG_SYS_I2C_LEGACY) || \ ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ + defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) + U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), + #endif /* CONFIG_I2C_MULTI_BUS */ +@@ -2036,12 +1986,12 @@ + /***************************************************/ + #ifdef CONFIG_SYS_LONGHELP + static char i2c_help_text[] = +-#if defined(CONFIG_SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) + "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n" + "i2c " /* That's the prefix for the crc32 command below. */ + #endif + "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" +-#if defined(CONFIG_SYS_I2C_LEGACY) || \ ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ + defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) + "i2c dev [dev] - show or set current I2C bus\n" + #endif /* CONFIG_I2C_MULTI_BUS */ +diff -ruN u-boot-2021.10/cmd/Kconfig u-boot/cmd/Kconfig +--- u-boot-2021.10/cmd/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/Kconfig 2021-11-01 17:10:14.129599778 +0100 +@@ -471,7 +471,6 @@ + + config CMD_ERASEENV + bool "eraseenv" +- default n + depends on CMD_SAVEENV + help + Erase environment variables from the compiled-in persistent +@@ -614,6 +613,37 @@ + Help printed with the LAYOUT VERSIONS part of the 'eeprom' + command's help. + ++config SYS_I2C_EEPROM_BUS ++ int "I2C bus of the EEPROM device." ++ depends on CMD_EEPROM ++ default 0 ++ ++config SYS_I2C_EEPROM_ADDR_LEN ++ int "Length in bytes of the EEPROM memory array address" ++ depends on CMD_EEPROM || ID_EEPROM ++ default 1 ++ range 1 2 ++ help ++ Note: This is NOT the chip address length! ++ ++config SYS_EEPROM_SIZE ++ depends on CMD_EEPROM ++ int "Size in bytes of the EEPROM device" ++ default 256 ++ ++config SYS_EEPROM_PAGE_WRITE_BITS ++ int "Number of bits used to address bytes in a single page" ++ depends on CMD_EEPROM ++ default 8 ++ help ++ The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. ++ A 64 byte page, for example would require six bits. ++ ++config SYS_EEPROM_PAGE_WRITE_DELAY_MS ++ int "Number of milliseconds to delay between page writes" ++ depends on CMD_EEPROM || CMD_I2C ++ default 0 ++ + config LOOPW + bool "loopw" + help +@@ -621,14 +651,12 @@ + + config CMD_MD5SUM + bool "md5sum" +- default n + select MD5 + help + Compute MD5 checksum. + + config MD5SUM_VERIFY + bool "md5sum -v" +- default n + depends on CMD_MD5SUM + help + Add -v option to verify data against an MD5 checksum. +@@ -1088,7 +1116,6 @@ + config CMD_BKOPS_ENABLE + bool "mmc bkops enable" + depends on CMD_MMC +- default n + help + Enable command for setting manual background operations handshake + on a eMMC device. The feature is optionally available on eMMC devices +@@ -1416,7 +1443,6 @@ + + config CMD_SETEXPR_FMT + bool "setexpr_fmt" +- default n + depends on CMD_SETEXPR + help + Evaluate format string expression and store result in an environment +@@ -1428,7 +1454,6 @@ + + config CMD_AB_SELECT + bool "ab_select" +- default n + depends on ANDROID_AB + help + On Android devices with more than one boot slot (multiple copies of +@@ -1733,7 +1758,6 @@ + bool "efidebug - display/configure UEFI environment" + depends on EFI_LOADER + select EFI_DEVICE_PATH_TO_TEXT +- default n + help + Enable the 'efidebug' command which provides a subset of UEFI + shell utility with simplified functionality. It will be useful +@@ -2336,7 +2360,6 @@ + config CMD_AVB + bool "avb - Android Verified Boot 2.0 operations" + depends on AVB_VERIFY +- default n + help + Enables a "avb" command to perform verification of partitions using + Android Verified Boot 2.0 functionality. It includes such subcommands: +@@ -2376,7 +2399,6 @@ + config CMD_UBI_RENAME + bool "Enable rename" + depends on CMD_UBI +- default n + help + Enable a "ubi" command to rename ubi volume: + ubi rename +diff -ruN u-boot-2021.10/cmd/load.c u-boot/cmd/load.c +--- u-boot-2021.10/cmd/load.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/load.c 2021-11-01 17:10:14.136266080 +0100 +@@ -474,6 +474,14 @@ + + addr = load_serial_ymodem(offset, xyzModem_ymodem); + ++ if (addr == ~0) { ++ image_load_addr = 0; ++ printf("## Binary (ymodem) download aborted\n"); ++ rcode = 1; ++ } else { ++ printf("## Start Addr = 0x%08lX\n", addr); ++ image_load_addr = addr; ++ } + } else if (strcmp(argv[0],"loadx")==0) { + printf("## Ready for binary (xmodem) download " + "to 0x%08lX at %d bps...\n", +@@ -482,6 +490,14 @@ + + addr = load_serial_ymodem(offset, xyzModem_xmodem); + ++ if (addr == ~0) { ++ image_load_addr = 0; ++ printf("## Binary (xmodem) download aborted\n"); ++ rcode = 1; ++ } else { ++ printf("## Start Addr = 0x%08lX\n", addr); ++ image_load_addr = addr; ++ } + } else { + + printf("## Ready for binary (kermit) download " +@@ -535,6 +551,9 @@ + udelay(1000); + } + ++ if (size == 0) ++ return ~0; /* Download aborted */ ++ + flush_cache(offset, size); + + printf("## Total Size = 0x%08x = %d Bytes\n", size, size); +@@ -975,6 +994,7 @@ + res = xyzModem_stream_open(&info, &err); + if (!res) { + ++ err = 0; + while ((res = + xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0) { + store_addr = addr + offset; +@@ -987,6 +1007,9 @@ + rc = flash_write((char *) ymodemBuf, + store_addr, res); + if (rc != 0) { ++ xyzModem_stream_terminate(true, &getcxmodem); ++ xyzModem_stream_close(&err); ++ printf("\n"); + flash_perror(rc); + return (~0); + } +@@ -998,16 +1021,24 @@ + } + + } ++ if (err) { ++ xyzModem_stream_terminate((err == xyzModem_cancel) ? false : true, &getcxmodem); ++ xyzModem_stream_close(&err); ++ printf("\n%s\n", xyzModem_error(err)); ++ return (~0); /* Download aborted */ ++ } ++ + if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) + efi_set_bootdev("Uart", "", "", + map_sysmem(offset, 0), size); + + } else { +- printf("%s\n", xyzModem_error(err)); ++ printf("\n%s\n", xyzModem_error(err)); ++ return (~0); /* Download aborted */ + } + +- xyzModem_stream_close(&err); + xyzModem_stream_terminate(false, &getcxmodem); ++ xyzModem_stream_close(&err); + + + flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN)); +diff -ruN u-boot-2021.10/cmd/mvebu/Kconfig u-boot/cmd/mvebu/Kconfig +--- u-boot-2021.10/cmd/mvebu/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/mvebu/Kconfig 2021-11-01 17:10:14.139599231 +0100 +@@ -3,7 +3,6 @@ + + config CMD_MVEBU_BUBT + bool "bubt" +- default n + select SHA256 if ARMADA_3700 + help + bubt - Burn a u-boot image to flash +diff -ruN u-boot-2021.10/cmd/nand.c u-boot/cmd/nand.c +--- u-boot-2021.10/cmd/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/nand.c 2021-11-01 17:10:14.139599231 +0100 +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + #include + #include + #include +diff -ruN u-boot-2021.10/cmd/pci.c u-boot/cmd/pci.c +--- u-boot-2021.10/cmd/pci.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/pci.c 2021-11-01 17:10:14.139599231 +0100 +@@ -59,7 +59,7 @@ + } + } + +-int pci_bar_show(struct udevice *dev) ++static int pci_bar_show(struct udevice *dev) + { + u8 header_type; + int bar_cnt, bar_id, mem_type; +@@ -223,7 +223,7 @@ + * + * @dev: Bus+Device+Function number + */ +-void pci_header_show(struct udevice *dev) ++static void pci_header_show(struct udevice *dev) + { + unsigned long class, header_type; + +@@ -251,7 +251,7 @@ + } + } + +-void pciinfo_header(int busnum, bool short_listing) ++static void pciinfo_header(int busnum, bool short_listing) + { + printf("Scanning PCI devices on bus %d\n", busnum); + +diff -ruN u-boot-2021.10/cmd/pvblock.c u-boot/cmd/pvblock.c +--- u-boot-2021.10/cmd/pvblock.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/pvblock.c 2021-11-01 17:10:14.139599231 +0100 +@@ -27,4 +27,3 @@ + "pvblock write addr blk# cnt - read/write `cnt'" + " blocks starting at block `blk#'\n" + " to/from memory address `addr'"); +- +diff -ruN u-boot-2021.10/cmd/qfw.c u-boot/cmd/qfw.c +--- u-boot-2021.10/cmd/qfw.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/qfw.c 2021-11-01 17:10:14.142932382 +0100 +@@ -121,11 +121,7 @@ + env = env_get("loadaddr"); + load_addr = env ? + (void *)hextoul(env, NULL) : +-#ifdef CONFIG_LOADADDR +- (void *)CONFIG_LOADADDR; +-#else +- NULL; +-#endif ++ (void *)CONFIG_SYS_LOAD_ADDR; + + env = env_get("ramdiskaddr"); + initrd_addr = env ? +diff -ruN u-boot-2021.10/cmd/riscv/sbi.c u-boot/cmd/riscv/sbi.c +--- u-boot-2021.10/cmd/riscv/sbi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/riscv/sbi.c 2021-11-01 17:10:14.142932382 +0100 +@@ -29,21 +29,21 @@ + }; + + static struct sbi_ext extensions[] = { +- { 0x00000000, "sbi_set_timer" }, +- { 0x00000001, "sbi_console_putchar" }, +- { 0x00000002, "sbi_console_getchar" }, +- { 0x00000003, "sbi_clear_ipi" }, +- { 0x00000004, "sbi_send_ipi" }, +- { 0x00000005, "sbi_remote_fence_i" }, +- { 0x00000006, "sbi_remote_sfence_vma" }, +- { 0x00000007, "sbi_remote_sfence_vma_asid" }, +- { 0x00000008, "sbi_shutdown" }, +- { 0x00000010, "SBI Base Functionality" }, +- { 0x54494D45, "Timer Extension" }, +- { 0x00735049, "IPI Extension" }, +- { 0x52464E43, "RFENCE Extension" }, +- { 0x0048534D, "Hart State Management Extension" }, +- { 0x53525354, "System Reset Extension" }, ++ { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" }, ++ { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" }, ++ { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" }, ++ { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" }, ++ { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" }, ++ { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" }, ++ { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" }, ++ { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" }, ++ { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" }, ++ { SBI_EXT_BASE, "SBI Base Functionality" }, ++ { SBI_EXT_TIME, "Timer Extension" }, ++ { SBI_EXT_IPI, "IPI Extension" }, ++ { SBI_EXT_RFENCE, "RFENCE Extension" }, ++ { SBI_EXT_HSM, "Hart State Management Extension" }, ++ { SBI_EXT_SRST, "System Reset Extension" }, + }; + + static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, +diff -ruN u-boot-2021.10/cmd/scp03.c u-boot/cmd/scp03.c +--- u-boot-2021.10/cmd/scp03.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/scp03.c 2021-11-01 17:10:14.142932382 +0100 +@@ -49,4 +49,3 @@ + U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text, + U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable), + U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision)); +- +diff -ruN u-boot-2021.10/cmd/smccc.c u-boot/cmd/smccc.c +--- u-boot-2021.10/cmd/smccc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/smccc.c 2021-11-01 17:10:14.142932382 +0100 +@@ -69,4 +69,3 @@ + " - id Session ID, passed to W7 (defaults to zero)\n" + ); + #endif +- +diff -ruN u-boot-2021.10/cmd/spi.c u-boot/cmd/spi.c +--- u-boot-2021.10/cmd/spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/spi.c 2021-11-01 17:10:14.142932382 +0100 +@@ -29,9 +29,9 @@ + static unsigned int cs; + static unsigned int mode; + static unsigned int freq; +-static int bitlen; +-static uchar dout[MAX_SPI_BYTES]; +-static uchar din[MAX_SPI_BYTES]; ++static int bitlen; ++static uchar dout[MAX_SPI_BYTES]; ++static uchar din[MAX_SPI_BYTES]; + + static int do_spi_xfer(int bus, int cs) + { +diff -ruN u-boot-2021.10/cmd/spl.c u-boot/cmd/spl.c +--- u-boot-2021.10/cmd/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/spl.c 2021-11-01 17:10:14.142932382 +0100 +@@ -32,11 +32,7 @@ + NULL, + }, + [SPL_EXPORT_ATAGS] = (const char * []) { +-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ +- defined(CONFIG_CMDLINE_TAG) || \ +- defined(CONFIG_INITRD_TAG) || \ +- defined(CONFIG_SERIAL_TAG) || \ +- defined(CONFIG_REVISION_TAG) ++#ifdef CONFIG_SUPPORT_PASSING_ATAGS + "start", + "loados", + #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH +diff -ruN u-boot-2021.10/cmd/version.c u-boot/cmd/version.c +--- u-boot-2021.10/cmd/version.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/cmd/version.c 2021-11-01 17:10:14.146265533 +0100 +@@ -6,13 +6,18 @@ + + #include + #include ++#include + #include ++#include + #include + #ifdef CONFIG_SYS_COREBOOT + #include + #endif + +-const char __weak version_string[] = U_BOOT_VERSION_STRING; ++#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ ++ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING ++ ++const char version_string[] = U_BOOT_VERSION_STRING; + + static int do_version(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +diff -ruN u-boot-2021.10/common/autoboot.c u-boot/common/autoboot.c +--- u-boot-2021.10/common/autoboot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/autoboot.c 2021-11-01 17:10:14.146265533 +0100 +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + DECLARE_GLOBAL_DATA_PTR; + +@@ -424,12 +425,12 @@ + ulong addr; + + /* Add an env variable to point to a kernel payload, if available */ +- addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); ++ addr = ofnode_conf_read_int("kernel-offset", 0); + if (addr) + env_set_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); + + /* Add an env variable to point to a root disk, if available */ +- addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); ++ addr = ofnode_conf_read_int("rootdisk-offset", 0); + if (addr) + env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); + #endif /* CONFIG_SYS_TEXT_BASE */ +@@ -446,8 +447,7 @@ + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; + + if (IS_ENABLED(CONFIG_OF_CONTROL)) +- bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", +- bootdelay); ++ bootdelay = ofnode_conf_read_int("bootdelay", bootdelay); + + debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); + +diff -ruN u-boot-2021.10/common/board_f.c u-boot/common/board_f.c +--- u-boot-2021.10/common/board_f.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/board_f.c 2021-11-01 17:10:14.149598684 +0100 +@@ -244,7 +244,7 @@ + return 0; + } + +-#if defined(CONFIG_SYS_I2C_LEGACY) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + static int init_func_i2c(void) + { + puts("I2C: "); +@@ -871,7 +871,7 @@ + misc_init_f, + #endif + INIT_FUNC_WATCHDOG_RESET +-#if defined(CONFIG_SYS_I2C_LEGACY) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + init_func_i2c, + #endif + #if defined(CONFIG_VID) && !defined(CONFIG_SPL) +diff -ruN u-boot-2021.10/common/board_r.c u-boot/common/board_r.c +--- u-boot-2021.10/common/board_r.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/board_r.c 2021-11-01 17:10:14.149598684 +0100 +@@ -67,6 +67,7 @@ + #endif + #include + #include ++#include + #include + #include + #include +@@ -448,8 +449,7 @@ + static int should_load_env(void) + { + if (IS_ENABLED(CONFIG_OF_CONTROL)) +- return fdtdec_get_config_int(gd->fdt_blob, +- "load-environment", 1); ++ return ofnode_conf_read_int("load-environment", 1); + + if (IS_ENABLED(CONFIG_DELAY_ENVIRONMENT)) + return 0; +@@ -720,7 +720,7 @@ + #endif + INIT_FUNC_WATCHDOG_RESET + cpu_secondary_init_r, +-#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) ++#if defined(CONFIG_ID_EEPROM) + mac_read_from_eeprom, + #endif + INIT_FUNC_WATCHDOG_RESET +diff -ruN u-boot-2021.10/common/cli.c u-boot/common/cli.c +--- u-boot-2021.10/common/cli.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/cli.c 2021-11-01 17:10:14.149598684 +0100 +@@ -19,8 +19,7 @@ + #include + #include + #include +- +-DECLARE_GLOBAL_DATA_PTR; ++#include + + #ifdef CONFIG_CMDLINE + /* +@@ -157,7 +156,7 @@ + bool cli_process_fdt(const char **cmdp) + { + /* Allow the fdt to override the boot command */ +- char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); ++ const char *env = ofnode_conf_read_str("bootcmd"); + if (env) + *cmdp = env; + /* +@@ -165,7 +164,7 @@ + * Always use 'env' in this case, since bootsecure requres that the + * bootcmd was specified in the FDT too. + */ +- return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0; ++ return ofnode_conf_read_int("bootsecure", 0); + } + + /* +diff -ruN u-boot-2021.10/common/hash.c u-boot/common/hash.c +--- u-boot-2021.10/common/hash.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/hash.c 2021-11-01 17:10:14.152931835 +0100 +@@ -228,7 +228,7 @@ + #endif + #ifdef CONFIG_SHA1 + { +- .name = "sha1", ++ .name = "sha1", + .digest_size = SHA1_SUM_LEN, + .chunk_size = CHUNKSZ_SHA1, + #ifdef CONFIG_SHA_HW_ACCEL +diff -ruN u-boot-2021.10/common/hwconfig.c u-boot/common/hwconfig.c +--- u-boot-2021.10/common/hwconfig.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/hwconfig.c 2021-11-01 17:10:14.152931835 +0100 +@@ -179,7 +179,7 @@ + * + * This call is similar to hwconfig_f(), except that it takes additional + * argument @subopt. In this example: +- * "dr_usb:mode=peripheral" ++ * "dr_usb:mode=peripheral" + * "dr_usb" is an option, "mode" is a sub-option, and "peripheral" is its + * argument. + */ +diff -ruN u-boot-2021.10/common/image.c u-boot/common/image.c +--- u-boot-2021.10/common/image.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/image.c 2021-11-01 17:10:14.156264986 +0100 +@@ -191,6 +191,8 @@ + { IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" }, + { IH_TYPE_COPRO, "copro", "Coprocessor Image"}, + { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" }, ++ { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" }, ++ { IH_TYPE_SUNXI_TOC1, "sunxi_toc1", "Allwinner TOC1 Boot Image" }, + { -1, "", "", }, + }; + +@@ -216,6 +218,8 @@ + { IH_COMP_GZIP, "gzip", {0x1f, 0x8b},}, + { IH_COMP_LZMA, "lzma", {0x5d, 0x00},}, + { IH_COMP_LZO, "lzo", {0x89, 0x4c},}, ++ { IH_COMP_LZ4, "lz4", {0x04, 0x22},}, ++ { IH_COMP_ZSTD, "zstd", {0x28, 0xb5},}, + { IH_COMP_NONE, "none", {}, }, + }; + +@@ -682,7 +686,7 @@ + + #if defined(CONFIG_SYS_SDRAM_BASE) + return CONFIG_SYS_SDRAM_BASE; +-#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) ++#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) + return gd->bd->bi_dram[0].start; + #else + return 0; +diff -ruN u-boot-2021.10/common/image-fdt.c u-boot/common/image-fdt.c +--- u-boot-2021.10/common/image-fdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/image-fdt.c 2021-11-01 17:10:14.152931835 +0100 +@@ -628,7 +628,7 @@ + if (!ft_verify_fdt(blob)) + goto err; + +-#if defined(CONFIG_SOC_KEYSTONE) ++#if defined(CONFIG_ARCH_KEYSTONE) + if (IMAGE_OF_BOARD_SETUP) + ft_board_setup_ex(blob, gd->bd); + #endif +diff -ruN u-boot-2021.10/common/image-fit.c u-boot/common/image-fit.c +--- u-boot-2021.10/common/image-fit.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/image-fit.c 2021-11-01 17:10:14.156264986 +0100 +@@ -25,6 +25,10 @@ + #include + #include + #include ++#ifdef CONFIG_DM_HASH ++#include ++#include ++#endif + DECLARE_GLOBAL_DATA_PTR; + #endif /* !USE_HOSTCC*/ + +@@ -1214,6 +1218,31 @@ + int calculate_hash(const void *data, int data_len, const char *name, + uint8_t *value, int *value_len) + { ++#if !defined(USE_HOSTCC) && defined(CONFIG_DM_HASH) ++ int rc; ++ enum HASH_ALGO hash_algo; ++ struct udevice *dev; ++ ++ rc = uclass_get_device(UCLASS_HASH, 0, &dev); ++ if (rc) { ++ debug("failed to get hash device, rc=%d\n", rc); ++ return -1; ++ } ++ ++ hash_algo = hash_algo_lookup_by_name(algo); ++ if (hash_algo == HASH_ALGO_INVALID) { ++ debug("Unsupported hash algorithm\n"); ++ return -1; ++ }; ++ ++ rc = hash_digest_wd(dev, hash_algo, data, data_len, value, CHUNKSZ); ++ if (rc) { ++ debug("failed to get hash value, rc=%d\n", rc); ++ return -1; ++ } ++ ++ *value_len = hash_algo_digest_size(hash_algo); ++#else + struct hash_algo *algo; + int ret; + +@@ -1225,6 +1254,7 @@ + + algo->hash_func_ws(data, data_len, value, algo->chunk_size); + *value_len = algo->digest_size; ++#endif + + return 0; + } +diff -ruN u-boot-2021.10/common/Kconfig u-boot/common/Kconfig +--- u-boot-2021.10/common/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/Kconfig 2021-11-01 17:10:14.146265533 +0100 +@@ -548,6 +548,12 @@ + help + Enabling this option calls 'misc_init_r' function + ++config ID_EEPROM ++ bool "Enable I2C connected system identifier EEPROM" ++ help ++ A number of different systems and vendors enable a vendor-specified ++ EEPROM that contains various identifying features. ++ + config PCI_INIT_R + bool "Enumerate PCI buses during init" + depends on PCI +@@ -627,7 +633,6 @@ + + config STACKPROTECTOR + bool "Stack Protector buffer overflow detection" +- default n + help + Enable stack smash detection through compiler's stack-protector + canary logic +@@ -635,12 +640,10 @@ + config SPL_STACKPROTECTOR + bool "Stack Protector buffer overflow detection for SPL" + depends on STACKPROTECTOR && SPL +- default n + + config TPL_STACKPROTECTOR + bool "Stack Protector buffer overflow detection for TPL" + depends on STACKPROTECTOR && TPL +- default n + + endmenu + +@@ -648,7 +651,6 @@ + + config UPDATE_COMMON + bool +- default n + select DFU_WRITE_ALT + + config UPDATE_TFTP +@@ -680,7 +682,6 @@ + + config ANDROID_AB + bool "Android A/B updates" +- default n + help + If enabled, adds support for the new Android A/B update model. This + allows the bootloader to select which slot to boot from based on the +diff -ruN u-boot-2021.10/common/Kconfig.boot u-boot/common/Kconfig.boot +--- u-boot-2021.10/common/Kconfig.boot 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/Kconfig.boot 2021-11-01 17:10:14.146265533 +0100 +@@ -80,7 +80,6 @@ + config FIT_RSASSA_PSS + bool "Support rsassa-pss signature scheme of FIT image contents" + depends on FIT_SIGNATURE +- default n + help + Enable this to support the pss padding algorithm as described + in the rfc8017 (https://tools.ietf.org/html/rfc8017). +@@ -373,6 +372,26 @@ + distinguishing between booting Chrome OS in a basic way (developer + mode) and a full boot. + ++config RAMBOOT_PBL ++ bool "Freescale PBL(pre-boot loader) image format support" ++ help ++ Some SoCs use PBL to load RCW and/or pre-initialization instructions. ++ For more details refer to doc/README.pblimage ++ ++config SYS_FSL_PBL_PBI ++ string "PBI(pre-boot instructions) commands for the PBL image" ++ depends on RAMBOOT_PBL ++ help ++ PBI commands can be used to configure SoC before it starts the execution. ++ Please refer doc/README.pblimage for more details. ++ ++config SYS_FSL_PBL_RCW ++ string "Aadditional RCW (Power on reset configuration) for the PBL image" ++ depends on RAMBOOT_PBL ++ help ++ Enables addition of RCW (Power on reset configuration) in built image. ++ Please refer doc/README.pblimage for more details. ++ + endmenu # Boot images + + menu "Boot timing" +@@ -682,7 +701,6 @@ + + config NAND_BOOT + bool "Support for booting from NAND flash" +- default n + imply MTD_RAW_NAND + help + Enabling this will make a U-Boot binary that is capable of being +@@ -691,7 +709,6 @@ + + config ONENAND_BOOT + bool "Support for booting from ONENAND" +- default n + imply MTD_RAW_NAND + help + Enabling this will make a U-Boot binary that is capable of being +@@ -700,7 +717,6 @@ + + config QSPI_BOOT + bool "Support for booting from QSPI flash" +- default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via QSPI flash. This is not a must, some SoCs need this, +@@ -708,7 +724,6 @@ + + config SATA_BOOT + bool "Support for booting from SATA" +- default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via SATA. This is not a must, some SoCs need this, +@@ -716,7 +731,6 @@ + + config SD_BOOT + bool "Support for booting from SD/EMMC" +- default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via SD/EMMC. This is not a must, some SoCs need this, +@@ -724,7 +738,6 @@ + + config SPI_BOOT + bool "Support for booting from SPI flash" +- default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via SPI flash. This is not a must, some SoCs need this, +@@ -758,7 +771,6 @@ + + config AUTOBOOT_KEYED + bool "Stop autobooting via specific input key / string" +- default n + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or +@@ -845,7 +857,6 @@ + config AUTOBOOT_KEYED_CTRLC + bool "Enable Ctrl-C autoboot interruption" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION +- default n + help + This option allows for the boot sequence to be interrupted + by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey". +diff -ruN u-boot-2021.10/common/lcd_console.c u-boot/common/lcd_console.c +--- u-boot-2021.10/common/lcd_console.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/lcd_console.c 2021-11-01 17:10:14.156264986 +0100 +@@ -258,4 +258,3 @@ + "print string on lcd-framebuffer", + " " + ); +- +diff -ruN u-boot-2021.10/common/main.c u-boot/common/main.c +--- u-boot-2021.10/common/main.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/main.c 2021-11-01 17:10:14.156264986 +0100 +@@ -15,7 +15,7 @@ + #include + #include + #include +-#include ++#include + #include + + static void run_preboot_environment_command(void) +diff -ruN u-boot-2021.10/common/Makefile u-boot/common/Makefile +--- u-boot-2021.10/common/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/Makefile 2021-11-01 17:10:14.146265533 +0100 +@@ -66,7 +66,7 @@ + obj-$(CONFIG_DFU_OVER_USB) += dfu.o + endif + obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o +-obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o ++obj-$(CONFIG_SPL_NET) += miiphyutil.o + obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o + + ifdef CONFIG_SPL_USB_HOST +@@ -85,9 +85,9 @@ + obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o + ifdef CONFIG_SPL_BUILD + ifdef CONFIG_TPL_BUILD +-obj-$(CONFIG_TPL_SERIAL_SUPPORT) += console.o ++obj-$(CONFIG_TPL_SERIAL) += console.o + else +-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o ++obj-$(CONFIG_SPL_SERIAL) += console.o + endif + else + obj-y += console.o +diff -ruN u-boot-2021.10/common/spl/Kconfig u-boot/common/spl/Kconfig +--- u-boot-2021.10/common/spl/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/Kconfig 2021-11-01 17:10:14.159598137 +0100 +@@ -160,7 +160,7 @@ + hex "SPL Text Base" + default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE + default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I +- default 0x20060 if SUN50I_GEN_H6 ++ default 0x20060 if SUN50I_GEN_H6 || MACH_SUN20I + default 0x00060 if ARCH_SUNXI + default 0xfffc0000 if ARCH_ZYNQMP + default 0x0 +@@ -196,7 +196,7 @@ + + config SPL_RAW_IMAGE_SUPPORT + bool "Support SPL loading and booting of RAW images" +- default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) ++ default n if (ARCH_MX6 && (SPL_MMC || SPL_SATA)) + default y if !TI_SECURE_DEVICE + help + SPL will support loading and booting a RAW image when this option +@@ -453,7 +453,7 @@ + ensure this information is available to the next image + invoked). + +-config SPL_CACHE_SUPPORT ++config SPL_CACHE + bool "Support CACHE drivers" + help + Enable CACHE drivers in SPL. These drivers can keep data so that +@@ -522,12 +522,13 @@ + config SPL_ETH + bool "Support Ethernet" + depends on SPL_ENV_SUPPORT ++ depends on SPL_NET + help + Enable access to the network subsystem and associated Ethernet + drivers in SPL. This permits SPL to load U-Boot over an Ethernet + link rather than from an on-board peripheral. Environment support + is required since the network stack uses a number of environment +- variables. See also SPL_NET_SUPPORT. ++ variables. See also SPL_NET. + + config SPL_FS_EXT4 + bool "Support EXT filesystems" +@@ -637,7 +638,7 @@ + this option to build the drivers in drivers/mailbox as part of + SPL build. + +-config SPL_MMC_SUPPORT ++config SPL_MMC + bool "Support MMC" + depends on MMC + select HAVE_BLOCK_DEVICE +@@ -658,8 +659,7 @@ + + config SPL_MMC_TINY + bool "Tiny MMC framework in SPL" +- depends on SPL_MMC_SUPPORT +- default n ++ depends on SPL_MMC + help + Enable MMC framework tinification support. This option is useful if + if your SPL is extremely size constrained. Heed the warning, enable +@@ -675,13 +675,12 @@ + + config SPL_MMC_WRITE + bool "MMC/SD/SDIO card support for write operations in SPL" +- depends on SPL_MMC_SUPPORT +- default n ++ depends on SPL_MMC + help + Enable write access to MMC and SD Cards in SPL + + +-config SPL_MPC8XXX_INIT_DDR_SUPPORT ++config SPL_MPC8XXX_INIT_DDR + bool "Support MPC8XXX DDR init" + help + Enable support for DDR-SDRAM (double-data-rate synchronous dynamic +@@ -747,12 +746,6 @@ + README.ubispl for more info. + + if SPL_DM +-config SPL_CACHE +- depends on CACHE +- bool "Support cache drivers in SPL" +- help +- Enable support for cache drivers in SPL. +- + config SPL_DM_SPI + bool "Support SPI DM drivers in SPL" + help +@@ -849,14 +842,13 @@ + + config UBI_SPL_SILENCE_MSG + bool "silence UBI SPL messages" +- default n + help + Disable messages from UBI SPL. This leaves warnings + and errors enabled. + + endif # if SPL_UBI + +-config SPL_NET_SUPPORT ++config SPL_NET + bool "Support networking" + help + Enable support for network devices (such as Ethernet) in SPL. +@@ -865,7 +857,7 @@ + the network stack uses a number of environment variables. See also + SPL_ETH. + +-if SPL_NET_SUPPORT ++if SPL_NET + config SPL_NET_VCI_STRING + string "BOOTP Vendor Class Identifier string sent by SPL" + help +@@ -874,7 +866,7 @@ + of a client. This is often used in practice to allow for the DHCP + server to specify different files to load depending on if the ROM, + SPL or U-Boot itself makes the request +-endif # if SPL_NET_SUPPORT ++endif # if SPL_NET + + config SPL_NO_CPU_SUPPORT + bool "Drop CPU code in SPL" +@@ -912,7 +904,6 @@ + config SPL_OS_BOOT + bool "Activate Falcon Mode" + depends on !TI_SECURE_DEVICE +- default n + help + Enable booting directly to an OS from SPL. + for more info read doc/README.falcon +@@ -945,7 +936,7 @@ + necessary driver support. This enables the drivers in drivers/pci + as part of an SPL build. + +-config SPL_PCH_SUPPORT ++config SPL_PCH + bool "Support PCH drivers" + help + Enable support for PCH (Platform Controller Hub) devices in SPL. +@@ -985,6 +976,7 @@ + + config SPL_POWER_DOMAIN + bool "Support power domain drivers" ++ select SPL_POWER + help + Enable support for power domain control in SPL. Many SoCs allow + power to be applied to or removed from portions of the SoC (power +@@ -1014,7 +1006,7 @@ + Enable support for REMOTEPROCs in SPL. This permits to load + a remote processor firmware in SPL. + +-config SPL_RTC_SUPPORT ++config SPL_RTC + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in SPL. This includes support +@@ -1023,7 +1015,7 @@ + needed. This enables the drivers in drivers/rtc as part of an SPL + build. + +-config SPL_SATA_SUPPORT ++config SPL_SATA + bool "Support loading from SATA" + help + Enable support for SATA (Serial AT attachment) in SPL. This allows +@@ -1035,7 +1027,7 @@ + + config SPL_SATA_RAW_U_BOOT_USE_SECTOR + bool "SATA raw mode: by sector" +- depends on SPL_SATA_SUPPORT ++ depends on SPL_SATA + default y if ARCH_MVEBU + help + Use sector number for specifying U-Boot location on SATA disk in +@@ -1049,7 +1041,7 @@ + Sector on the SATA disk to load U-Boot from, when the SATA disk is being + used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes). + +-config SPL_SERIAL_SUPPORT ++config SPL_SERIAL + bool "Support serial" + select SPL_PRINTF + select SPL_STRTO +@@ -1060,7 +1052,7 @@ + unless there are space reasons not to. Even then, consider + enabling SPL_USE_TINY_PRINTF which is a small printf() version. + +-config SPL_SPI_SUPPORT ++config SPL_SPI + bool "Support SPI drivers" + help + Enable support for using SPI in SPL. This is used for connecting +@@ -1072,14 +1064,14 @@ + + config SPL_SPI_FLASH_SUPPORT + bool "Support SPI flash drivers" +- depends on SPL_SPI_SUPPORT ++ depends on SPL_SPI + help + Enable support for using SPI flash in SPL, and loading U-Boot from + SPI flash. SPI flash (Serial Peripheral Bus flash) is named after + the SPI bus that is used to connect it to a system. It is a simple + but fast bidirectional 4-wire bus (clock, chip select and two data + lines). This enables the drivers in drivers/mtd/spi as part of an +- SPL build. This normally requires SPL_SPI_SUPPORT. ++ SPL build. This normally requires SPL_SPI. + + if SPL_SPI_FLASH_SUPPORT + +@@ -1162,13 +1154,14 @@ + + config SPL_USB_ETHER + bool "Support USB Ethernet drivers" ++ depends on SPL_NET + help + Enable access to the USB network subsystem and associated + drivers in SPL. This permits SPL to load U-Boot over a + USB-connected Ethernet link (such as a USB Ethernet dongle) rather + than from an onboard peripheral. Environment support is required + since the network stack uses a number of environment variables. +- See also SPL_NET_SUPPORT and SPL_ETH. ++ See also SPL_NET and SPL_ETH. + + config SPL_DFU + bool "Support DFU (Device Firmware Upgrade)" +@@ -1199,7 +1192,7 @@ + + config SPL_USB_SDP_SUPPORT + bool "Support SDP (Serial Download Protocol)" +- depends on SPL_SERIAL_SUPPORT ++ depends on SPL_SERIAL + help + Enable Serial Download Protocol (SDP) device support in SPL. This + allows to download images into memory and execute (jump to) them +@@ -1225,7 +1218,7 @@ + + config SPL_YMODEM_SUPPORT + bool "Support loading using Ymodem" +- depends on SPL_SERIAL_SUPPORT ++ depends on SPL_SERIAL + help + While loading from serial is slow it can be a useful backup when + there is no other option. The Ymodem protocol provides a reliable +@@ -1270,16 +1263,16 @@ + Enable access to the AM33xx RTC and select the external 32kHz clock + source. + +-config SPL_OPTEE +- bool "Support OP-TEE Trusted OS" ++config SPL_OPTEE_IMAGE ++ bool "Support OP-TEE Trusted OS image in SPL" + depends on ARM + help +- OP-TEE is an open source Trusted OS which is loaded by SPL. ++ OP-TEE is an open source Trusted OS which is loaded by SPL. + More detail at: https://github.com/OP-TEE/optee_os + + config SPL_OPENSBI + bool "Support RISC-V OpenSBI" +- depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE ++ depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE && SPL_LOAD_FIT + help + OpenSBI is an open-source implementation of the RISC-V Supervisor Binary + Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC +@@ -1359,7 +1352,6 @@ + + config TPL_NEEDS_SEPARATE_TEXT_BASE + bool "TPL needs a separate text-base" +- default n + depends on TPL + help + Enable, if the TPL stage should not inherit its text-base +@@ -1368,12 +1360,23 @@ + + config TPL_NEEDS_SEPARATE_STACK + bool "TPL needs a separate initial stack-pointer" +- default n + depends on TPL + help + Enable, if the TPL stage should not inherit its initial + stack-pointer from the settings for the SPL stage. + ++config TPL_POWER ++ bool "Support power drivers" ++ help ++ Enable support for power control in TPL. This includes support ++ for PMICs (Power-management Integrated Circuits) and some of the ++ features provided by PMICs. In particular, voltage regulators can ++ be used to enable/disable power and vary its voltage. That can be ++ useful in TPL to turn on boot peripherals and adjust CPU voltage ++ so that the clock speed can be increased. This enables the drivers ++ in drivers/power, drivers/power/pmic and drivers/power/regulator ++ as part of an TPL build. ++ + config TPL_TEXT_BASE + hex "Base address for the .text section of the TPL stage" + depends on TPL_NEEDS_SEPARATE_TEXT_BASE +@@ -1458,17 +1461,17 @@ + Enable support for generic U-Boot libraries within TPL. See + SPL_LIBGENERIC_SUPPORT for details. + +-config TPL_MPC8XXX_INIT_DDR_SUPPORT ++config TPL_MPC8XXX_INIT_DDR + bool "Support MPC8XXX DDR init" + help + Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See +- SPL_MPC8XXX_INIT_DDR_SUPPORT for details. ++ SPL_MPC8XXX_INIT_DDR for details. + +-config TPL_MMC_SUPPORT ++config TPL_MMC + bool "Support MMC" + depends on MMC + help +- Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details. ++ Enable support for MMC within TPL. See SPL_MMC for details. + + config TPL_NAND_SUPPORT + bool "Support NAND flash" +@@ -1483,7 +1486,7 @@ + necessary driver support. This enables the drivers in drivers/pci + as part of a TPL build. + +-config TPL_PCH_SUPPORT ++config TPL_PCH + bool "Support PCH drivers" + help + Enable support for PCH (Platform Controller Hub) devices in TPL. +@@ -1505,7 +1508,7 @@ + be already in memory when TPL takes over, e.g. loaded by the boot + ROM. + +-config TPL_RTC_SUPPORT ++config TPL_RTC + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in TPL. This includes support +@@ -1514,12 +1517,12 @@ + needed. This enables the drivers in drivers/rtc as part of an TPL + build. + +-config TPL_SERIAL_SUPPORT ++config TPL_SERIAL + bool "Support serial" + select TPL_PRINTF + select TPL_STRTO + help +- Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for ++ Enable support for serial in TPL. See SPL_SERIAL for + details. + + config TPL_SPI_FLASH_SUPPORT +@@ -1545,10 +1548,10 @@ + Enable support for loading next stage, U-Boot or otherwise, from + SPI NOR in U-Boot TPL. + +-config TPL_SPI_SUPPORT ++config TPL_SPI + bool "Support SPI drivers" + help +- Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for ++ Enable support for using SPI in TPL. See SPL_SPI for + details. + + config TPL_DM_SPI +@@ -1563,7 +1566,7 @@ + + config TPL_YMODEM_SUPPORT + bool "Support loading using Ymodem" +- depends on TPL_SERIAL_SUPPORT ++ depends on TPL_SERIAL + help + While loading from serial is slow it can be a useful backup when + there is no other option. The Ymodem protocol provides a reliable +@@ -1575,7 +1578,6 @@ + config SPL_AT91_MCK_BYPASS + bool "Use external clock signal as a source of main clock for AT91 platforms" + depends on ARCH_AT91 +- default n + help + Use external 8 to 24 Mhz clock signal as source of main clock instead + of an external crystal oscillator. +diff -ruN u-boot-2021.10/common/spl/Makefile u-boot/common/spl/Makefile +--- u-boot-2021.10/common/spl/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/Makefile 2021-11-01 17:10:14.159598137 +0100 +@@ -19,15 +19,15 @@ + obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o + endif + obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o +-obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o +-obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o ++obj-$(CONFIG_$(SPL_TPL_)NET) += spl_net.o ++obj-$(CONFIG_$(SPL_TPL_)MMC) += spl_mmc.o + obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o +-obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o ++obj-$(CONFIG_$(SPL_TPL_)OPTEE_IMAGE) += spl_optee.o + obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o + obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o + obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o + obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o +-obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o ++obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o + obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o + obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o + obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o +diff -ruN u-boot-2021.10/common/spl/spl.c u-boot/common/spl/spl.c +--- u-boot-2021.10/common/spl/spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/spl.c 2021-11-01 17:10:14.159598137 +0100 +@@ -24,6 +24,9 @@ + #include + #include + #include ++#if CONFIG_IS_ENABLED(BANNER_PRINT) ++#include ++#endif + #include + #include + #include +@@ -486,7 +489,7 @@ + return ret; + } + #endif +- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ++ if (CONFIG_IS_ENABLED(OF_REAL)) { + ret = fdtdec_setup(); + if (ret) { + debug("fdtdec_setup() returned error %d\n", ret); +@@ -623,7 +626,7 @@ + if (CONFIG_IS_ENABLED(SHOW_ERRORS)) + ret = -ENXIO; + loader = spl_ll_find_loader(bootdev); +- if (CONFIG_IS_ENABLED(SERIAL_SUPPORT) && ++ if (CONFIG_IS_ENABLED(SERIAL) && + CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && + !IS_ENABLED(CONFIG_SILENT_CONSOLE)) { + if (loader) +@@ -773,7 +776,7 @@ + spl_invoke_atf(&spl_image); + break; + #endif +-#if CONFIG_IS_ENABLED(OPTEE) ++#if CONFIG_IS_ENABLED(OPTEE_IMAGE) + case IH_OS_TEE: + debug("Jumping to U-Boot via OP-TEE\n"); + spl_board_prepare_for_optee(spl_image.fdt_addr); +@@ -821,7 +824,7 @@ + */ + void preloader_console_init(void) + { +-#ifdef CONFIG_SPL_SERIAL_SUPPORT ++#ifdef CONFIG_SPL_SERIAL + gd->baudrate = CONFIG_BAUDRATE; + + serial_init(); /* serial communications setup */ +diff -ruN u-boot-2021.10/common/spl/spl_mmc.c u-boot/common/spl/spl_mmc.c +--- u-boot-2021.10/common/spl/spl_mmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/spl_mmc.c 2021-11-01 17:10:14.159598137 +0100 +@@ -194,7 +194,7 @@ + err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); + if (err) + continue; +- if (info.sys_ind == ++ if (info.sys_ind == + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { + partition = type_part; + break; +diff -ruN u-boot-2021.10/common/spl/spl_ram.c u-boot/common/spl/spl_ram.c +--- u-boot-2021.10/common/spl/spl_ram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/spl_ram.c 2021-11-01 17:10:14.159598137 +0100 +@@ -81,5 +81,3 @@ + #if CONFIG_IS_ENABLED(DFU) + SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image); + #endif +- +- +diff -ruN u-boot-2021.10/common/spl/spl_spi.c u-boot/common/spl/spl_spi.c +--- u-boot-2021.10/common/spl/spl_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/spl/spl_spi.c 2021-11-01 17:10:14.159598137 +0100 +@@ -16,8 +16,7 @@ + #include + #include + #include +- +-DECLARE_GLOBAL_DATA_PTR; ++#include + + #ifdef CONFIG_SPL_OS_BOOT + /* +@@ -103,11 +102,10 @@ + + header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +- payload_offs = fdtdec_get_config_int(gd->fdt_blob, +- "u-boot,spl-payload-offset", +- payload_offs); +-#endif ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset", ++ payload_offs); ++ } + + #ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header)) +diff -ruN u-boot-2021.10/common/stdio.c u-boot/common/stdio.c +--- u-boot-2021.10/common/stdio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/stdio.c 2021-11-01 17:10:14.159598137 +0100 +@@ -336,7 +336,7 @@ + dev->name); + } + } +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + i2c_init_all(); + #endif + if (IS_ENABLED(CONFIG_DM_VIDEO)) { +diff -ruN u-boot-2021.10/common/usb_storage.c u-boot/common/usb_storage.c +--- u-boot-2021.10/common/usb_storage.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/usb_storage.c 2021-11-01 17:10:14.159598137 +0100 +@@ -94,7 +94,7 @@ + int action; /* what to do */ + int ip_wanted; /* needed */ + int *irq_handle; /* for USB int requests */ +- unsigned int irqpipe; /* pipe for release_irq */ ++ unsigned int irqpipe; /* pipe for release_irq */ + unsigned char irqmaxp; /* max packed for irq Pipe */ + unsigned char irqinterval; /* Intervall for IRQ Pipe */ + struct scsi_cmd *srb; /* current srb */ +diff -ruN u-boot-2021.10/common/xyzModem.c u-boot/common/xyzModem.c +--- u-boot-2021.10/common/xyzModem.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/common/xyzModem.c 2021-11-01 17:10:14.159598137 +0100 +@@ -32,6 +32,7 @@ + /* Values magic to the protocol */ + #define SOH 0x01 + #define STX 0x02 ++#define ETX 0x03 /* ^C for interrupt */ + #define EOT 0x04 + #define ACK 0x06 + #define BSP 0x08 +@@ -283,6 +284,7 @@ + hdr_found = true; + break; + case CAN: ++ case ETX: + xyz.total_CAN++; + ZM_DEBUG (zm_dump (__LINE__)); + if (++can_total == xyzModem_CAN_COUNT) +@@ -494,7 +496,7 @@ + total = 0; + stat = xyzModem_cancel; + /* Try and get 'size' bytes into the buffer */ +- while (!xyz.at_eof && (size > 0)) ++ while (!xyz.at_eof && xyz.len >= 0 && (size > 0)) + { + if (xyz.len == 0) + { +@@ -572,6 +574,8 @@ + CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); + ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__)); + } ++ else ++ stat = 0; + xyz.at_eof = true; + break; + } +@@ -587,7 +591,7 @@ + } + } + /* Don't "read" data from the EOF protocol package */ +- if (!xyz.at_eof) ++ if (!xyz.at_eof && xyz.len > 0) + { + len = xyz.len; + if (size < len) +@@ -606,10 +610,10 @@ + void + xyzModem_stream_close (int *err) + { +- diag_printf ++ ZM_DEBUG (zm_dprintf + ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", + xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX, +- xyz.total_CAN, xyz.total_retries); ++ xyz.total_CAN, xyz.total_retries)); + ZM_DEBUG (zm_flush ()); + } + +diff -ruN u-boot-2021.10/configs/10m50_defconfig u-boot/configs/10m50_defconfig +--- u-boot-2021.10/configs/10m50_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/10m50_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -3,8 +3,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" ++CONFIG_SYS_LOAD_ADDR=0xcc000000 + CONFIG_FIT=y + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/3c120_defconfig u-boot/configs/3c120_defconfig +--- u-boot-2021.10/configs/3c120_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/3c120_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -3,8 +3,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" ++CONFIG_SYS_LOAD_ADDR=0xd4000000 + CONFIG_FIT=y + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/A10-OLinuXino-Lime_defconfig u-boot/configs/A10-OLinuXino-Lime_defconfig +--- u-boot-2021.10/configs/A10-OLinuXino-Lime_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A10-OLinuXino-Lime_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -13,6 +13,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_AXP_ALDO3_VOLT=2800 +@@ -20,3 +23,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/A10s-OLinuXino-M_defconfig u-boot/configs/A10s-OLinuXino-M_defconfig +--- u-boot-2021.10/configs/A10s-OLinuXino-M_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A10s-OLinuXino-M_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -7,9 +7,12 @@ + CONFIG_MMC0_CD_PIN="PG1" + CONFIG_MMC1_CD_PIN="PG13" + CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +-CONFIG_USB1_VBUS_PIN="PB10" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_AXP152_POWER=y +diff -ruN u-boot-2021.10/configs/A13-OLinuXino_defconfig u-boot/configs/A13-OLinuXino_defconfig +--- u-boot-2021.10/configs/A13-OLinuXino_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A13-OLinuXino_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=0 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB1_VBUS_PIN="PG11" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_VGA_VIA_LCD=y +@@ -20,6 +19,9 @@ + CONFIG_CMD_USB_MASS_STORAGE=y + CONFIG_DFU_RAM=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP_ALDO3_VOLT=3300 + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/A13-OLinuXinoM_defconfig u-boot/configs/A13-OLinuXinoM_defconfig +--- u-boot-2021.10/configs/A13-OLinuXinoM_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A13-OLinuXinoM_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,13 +6,16 @@ + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=0 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB1_VBUS_PIN="PG11" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_VGA_VIA_LCD=y + CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y + CONFIG_VIDEO_LCD_POWER="PB10" + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_SUNXI_NO_PMIC=y + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/A20-Olimex-SOM204-EVB_defconfig u-boot/configs/A20-Olimex-SOM204-EVB_defconfig +--- u-boot-2021.10/configs/A20-Olimex-SOM204-EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-Olimex-SOM204-EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,7 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PC17" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_I2C1_ENABLE=y + CONFIG_SATAPWR="PC3" + CONFIG_GMAC_TX_DELAY=4 +@@ -15,6 +14,9 @@ + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_ADDR=3 + CONFIG_PHY_MICREL=y + CONFIG_PHY_MICREL_KSZ90X1=y +diff -ruN u-boot-2021.10/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig u-boot/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +--- u-boot-2021.10/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="PC17" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_I2C1_ENABLE=y + CONFIG_SATAPWR="PC3" + CONFIG_GMAC_TX_DELAY=4 +@@ -16,6 +15,9 @@ + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_ADDR=3 + CONFIG_PHY_MICREL=y + CONFIG_PHY_MICREL_KSZ90X1=y +diff -ruN u-boot-2021.10/configs/A20-Olimex-SOM-EVB_defconfig u-boot/configs/A20-Olimex-SOM-EVB_defconfig +--- u-boot-2021.10/configs/A20-Olimex-SOM-EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-Olimex-SOM-EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,15 +6,16 @@ + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_MMC3_CD_PIN="PH0" +-CONFIG_MMC3_PINS="PH" + CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SATAPWR="PC3" + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_RTL8211X_PHY_FORCE_MASTER=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/A20-OLinuXino-Lime2_defconfig u-boot/configs/A20-OLinuXino-Lime2_defconfig +--- u-boot-2021.10/configs/A20-OLinuXino-Lime2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-OLinuXino-Lime2_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,7 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PC17" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_I2C1_ENABLE=y + CONFIG_SATAPWR="PC3" + CONFIG_AHCI=y +@@ -17,6 +16,9 @@ + CONFIG_SCSI_AHCI=y + CONFIG_DFU_RAM=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_RTL8211X_PHY_FORCE_MASTER=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/A20-OLinuXino-Lime2-eMMC_defconfig u-boot/configs/A20-OLinuXino-Lime2-eMMC_defconfig +--- u-boot-2021.10/configs/A20-OLinuXino-Lime2-eMMC_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-OLinuXino-Lime2-eMMC_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="PC17" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_I2C1_ENABLE=y + CONFIG_SATAPWR="PC3" + CONFIG_SPL_SPI_SUNXI=y +@@ -19,6 +18,9 @@ + CONFIG_SCSI_AHCI=y + CONFIG_DFU_RAM=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_MICREL=y + CONFIG_PHY_MICREL_KSZ90X1=y + CONFIG_PHY_REALTEK=y +diff -ruN u-boot-2021.10/configs/A20-OLinuXino-Lime_defconfig u-boot/configs/A20-OLinuXino-Lime_defconfig +--- u-boot-2021.10/configs/A20-OLinuXino-Lime_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-OLinuXino-Lime_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -11,6 +11,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -20,3 +23,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/A20-OLinuXino_MICRO_defconfig u-boot/configs/A20-OLinuXino_MICRO_defconfig +--- u-boot-2021.10/configs/A20-OLinuXino_MICRO_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-OLinuXino_MICRO_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -14,6 +14,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -24,3 +27,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/A20-OLinuXino_MICRO-eMMC_defconfig u-boot/configs/A20-OLinuXino_MICRO-eMMC_defconfig +--- u-boot-2021.10/configs/A20-OLinuXino_MICRO-eMMC_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A20-OLinuXino_MICRO-eMMC_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -13,6 +13,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -23,3 +26,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/A33-OLinuXino_defconfig u-boot/configs/A33-OLinuXino_defconfig +--- u-boot-2021.10/configs/A33-OLinuXino_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/A33-OLinuXino_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -7,9 +7,8 @@ + CONFIG_DRAM_ZQ=15291 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PB3" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/adp-ae3xx_defconfig u-boot/configs/adp-ae3xx_defconfig +--- u-boot-2021.10/configs/adp-ae3xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/adp-ae3xx_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,11 +1,14 @@ + CONFIG_NDS32=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x4A000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x140000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae3xx" + CONFIG_TARGET_ADP_AE3XX=y ++CONFIG_SYS_LOAD_ADDR=0x300000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + # CONFIG_AUTO_COMPLETE is not set +diff -ruN u-boot-2021.10/configs/adp-ag101p_defconfig u-boot/configs/adp-ag101p_defconfig +--- u-boot-2021.10/configs/adp-ag101p_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/adp-ag101p_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,10 +1,13 @@ + CONFIG_NDS32=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x11000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ag101p" + CONFIG_TARGET_ADP_AG101P=y ++CONFIG_SYS_LOAD_ADDR=0x300000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + # CONFIG_AUTO_COMPLETE is not set +diff -ruN u-boot-2021.10/configs/ae350_rv32_defconfig u-boot/configs/ae350_rv32_defconfig +--- u-boot-2021.10/configs/ae350_rv32_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv32_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,9 +2,11 @@ + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_32" + CONFIG_TARGET_AX25_AE350=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/ae350_rv32_spl_defconfig u-boot/configs/ae350_rv32_spl_defconfig +--- u-boot-2021.10/configs/ae350_rv32_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv32_spl_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,12 +2,14 @@ + CONFIG_SYS_TEXT_BASE=0x01200000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_32" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 + CONFIG_SPL=y + CONFIG_TARGET_AX25_AE350=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/ae350_rv32_spl_xip_defconfig u-boot/configs/ae350_rv32_spl_xip_defconfig +--- u-boot-2021.10/configs/ae350_rv32_spl_xip_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv32_spl_xip_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0x01200000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_32" + CONFIG_SPL_TEXT_BASE=0x80000000 + CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +@@ -10,6 +11,7 @@ + CONFIG_RISCV_SMODE=y + CONFIG_XIP=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/ae350_rv32_xip_defconfig u-boot/configs/ae350_rv32_xip_defconfig +--- u-boot-2021.10/configs/ae350_rv32_xip_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv32_xip_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,10 +2,12 @@ + CONFIG_SYS_TEXT_BASE=0x80000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_32" + CONFIG_TARGET_AX25_AE350=y + CONFIG_XIP=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/ae350_rv64_defconfig u-boot/configs/ae350_rv64_defconfig +--- u-boot-2021.10/configs/ae350_rv64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv64_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,10 +2,12 @@ + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_64" + CONFIG_TARGET_AX25_AE350=y + CONFIG_ARCH_RV64I=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/ae350_rv64_spl_defconfig u-boot/configs/ae350_rv64_spl_defconfig +--- u-boot-2021.10/configs/ae350_rv64_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv64_spl_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0x01200000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_64" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 + CONFIG_SPL=y +@@ -9,6 +10,7 @@ + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/ae350_rv64_spl_xip_defconfig u-boot/configs/ae350_rv64_spl_xip_defconfig +--- u-boot-2021.10/configs/ae350_rv64_spl_xip_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv64_spl_xip_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0x01200000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_64" + CONFIG_SPL_TEXT_BASE=0x80000000 + CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +@@ -11,6 +12,7 @@ + CONFIG_RISCV_SMODE=y + CONFIG_XIP=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/ae350_rv64_xip_defconfig u-boot/configs/ae350_rv64_xip_defconfig +--- u-boot-2021.10/configs/ae350_rv64_xip_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ae350_rv64_xip_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,11 +2,13 @@ + CONFIG_SYS_TEXT_BASE=0x80000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="ae350_64" + CONFIG_TARGET_AX25_AE350=y + CONFIG_ARCH_RV64I=y + CONFIG_XIP=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/Ainol_AW1_defconfig u-boot/configs/Ainol_AW1_defconfig +--- u-boot-2021.10/configs/Ainol_AW1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Ainol_AW1_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,8 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=123 + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" +@@ -15,4 +15,7 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/alt_defconfig u-boot/configs/alt_defconfig +--- u-boot-2021.10/configs/alt_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/alt_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt" + CONFIG_R8A7794=y + CONFIG_TARGET_ALT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/am335x_baltos_defconfig u-boot/configs/am335x_baltos_defconfig +--- u-boot-2021.10/configs/am335x_baltos_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_baltos_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,8 +6,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_BALTOS=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -28,6 +28,7 @@ + CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_CMD_ASKENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -50,13 +51,21 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_BOOTCOUNT_LIMIT=y +-CONFIG_SYS_OMAP24_I2C_SPEED=1000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SPEED=1000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MMC_OMAP_HS_ADMA=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +-CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000 ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_ATHEROS=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/am335x_boneblack_vboot_defconfig u-boot/configs/am335x_boneblack_vboot_defconfig +--- u-boot-2021.10/configs/am335x_boneblack_vboot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_boneblack_vboot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -21,12 +21,13 @@ + CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_MUSB_NEW=y + # CONFIG_SPL_NAND_SUPPORT is not set +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_USB_ETHER=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set + CONFIG_BOOTP_DNS2=y +@@ -47,6 +48,7 @@ + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/am335x_evm_defconfig u-boot/configs/am335x_evm_defconfig +--- u-boot-2021.10/configs/am335x_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -21,13 +21,14 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_USB_ETHER=y + CONFIG_CMD_SPL=y + CONFIG_CMD_SPL_NAND_OFS=0x00080000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -57,10 +58,18 @@ + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC_HW_PARTITIONING is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=24000000 + CONFIG_SPI_FLASH_WINBOND=y +diff -ruN u-boot-2021.10/configs/am335x_evm_spiboot_defconfig u-boot/configs/am335x_evm_spiboot_defconfig +--- u-boot-2021.10/configs/am335x_evm_spiboot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_evm_spiboot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,10 +6,10 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" + CONFIG_AM33XX=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_OF_BOARD_SETUP=y +@@ -25,6 +25,7 @@ + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 + CONFIG_CMD_SPL=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -55,11 +56,17 @@ + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_SPL_DM_MMC is not set + # CONFIG_MMC_HW_PARTITIONING is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + # CONFIG_SPL_NAND_AM33XX_BCH is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=24000000 +diff -ruN u-boot-2021.10/configs/am335x_guardian_defconfig u-boot/configs/am335x_guardian_defconfig +--- u-boot-2021.10/configs/am335x_guardian_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_guardian_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -10,7 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_GUARDIAN=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y +@@ -35,7 +35,7 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL" + CONFIG_SPL_POWER=y + CONFIG_SPL_USB_GADGET=y +@@ -64,6 +64,7 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_SPL_ENV_IS_NOWHERE=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y +@@ -78,6 +79,8 @@ + CONFIG_CLK_TI_DIVIDER=y + CONFIG_CLK_TI_GATE=y + CONFIG_CLK_TI_MUX=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_LED=y + CONFIG_LED_GPIO=y + CONFIG_MISC=y +@@ -85,6 +88,12 @@ + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0x100 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000 + CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x200000 +diff -ruN u-boot-2021.10/configs/am335x_hs_evm_defconfig u-boot/configs/am335x_hs_evm_defconfig +--- u-boot-2021.10/configs/am335x_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_hs_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -26,6 +26,7 @@ + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y + # CONFIG_SPL_YMODEM_SUPPORT is not set ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -50,10 +51,16 @@ + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC_HW_PARTITIONING is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=24000000 + CONFIG_SPI_FLASH_WINBOND=y +diff -ruN u-boot-2021.10/configs/am335x_hs_evm_uart_defconfig u-boot/configs/am335x_hs_evm_uart_defconfig +--- u-boot-2021.10/configs/am335x_hs_evm_uart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_hs_evm_uart_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,7 +6,7 @@ + CONFIG_TI_COMMON_CMD_OPTIONS=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" + CONFIG_AM33XX=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_SPL=y + # CONFIG_SPL_FS_FAT is not set + # CONFIG_SPL_LIBDISK_SUPPORT is not set +@@ -28,6 +28,7 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -52,10 +53,16 @@ + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC_HW_PARTITIONING is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=24000000 + CONFIG_SPI_FLASH_WINBOND=y +diff -ruN u-boot-2021.10/configs/am335x_igep003x_defconfig u-boot/configs/am335x_igep003x_defconfig +--- u-boot-2021.10/configs/am335x_igep003x_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_igep003x_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,14 +9,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_IGEP003X=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033" + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_SPL_FS_EXT4=y +@@ -68,9 +67,16 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PHY_SMSC=y + CONFIG_MII=y +diff -ruN u-boot-2021.10/configs/am335x_pdu001_defconfig u-boot/configs/am335x_pdu001_defconfig +--- u-boot-2021.10/configs/am335x_pdu001_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_pdu001_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,8 +8,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" + CONFIG_AM33XX=y + CONFIG_TARGET_PDU001=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y +diff -ruN u-boot-2021.10/configs/am335x_shc_defconfig u-boot/configs/am335x_shc_defconfig +--- u-boot-2021.10/configs/am335x_shc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_shc_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,8 +9,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_SHC=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x9000 + CONFIG_SPL_FS_FAT=y +@@ -51,6 +51,10 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SLAVE=0x1 ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MMC_OMAP_HS=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/am335x_shc_ict_defconfig u-boot/configs/am335x_shc_ict_defconfig +--- u-boot-2021.10/configs/am335x_shc_ict_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_shc_ict_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,8 +9,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_SHC=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x9000 + CONFIG_SPL_FS_FAT=y +@@ -52,6 +52,10 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SLAVE=0x1 ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MMC_OMAP_HS=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/am335x_shc_netboot_defconfig u-boot/configs/am335x_shc_netboot_defconfig +--- u-boot-2021.10/configs/am335x_shc_netboot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_shc_netboot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,8 +9,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_SHC=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x9000 + CONFIG_SPL_FS_FAT=y +@@ -52,6 +52,10 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SLAVE=0x1 ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MMC_OMAP_HS=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/am335x_shc_sdboot_defconfig u-boot/configs/am335x_shc_sdboot_defconfig +--- u-boot-2021.10/configs/am335x_shc_sdboot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_shc_sdboot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,8 +9,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_SHC=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x9000 + CONFIG_SPL_FS_FAT=y +@@ -51,6 +51,10 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SLAVE=0x1 ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MMC_OMAP_HS=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/am335x_sl50_defconfig u-boot/configs/am335x_sl50_defconfig +--- u-boot-2021.10/configs/am335x_sl50_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am335x_sl50_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,8 +8,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50" + CONFIG_AM33XX=y + CONFIG_TARGET_AM335X_SL50=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x20000 + CONFIG_SPL_FS_FAT=y +@@ -29,7 +29,7 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_POWER=y +@@ -38,6 +38,7 @@ + CONFIG_CMD_SPL=y + CONFIG_CMD_ASKENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -57,6 +58,9 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_BOOTCOUNT_LIMIT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_PHY_SMSC=y + CONFIG_MII=y +diff -ruN u-boot-2021.10/configs/am3517_evm_defconfig u-boot/configs/am3517_evm_defconfig +--- u-boot-2021.10/configs/am3517_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am3517_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -57,6 +57,11 @@ + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +@@ -77,6 +82,8 @@ + CONFIG_OMAP3_SPI=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=57 + CONFIG_USB_MUSB_HOST=y + CONFIG_USB_MUSB_AM35X=y + CONFIG_BCH=y +diff -ruN u-boot-2021.10/configs/am43xx_evm_defconfig u-boot/configs/am43xx_evm_defconfig +--- u-boot-2021.10/configs/am43xx_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am43xx_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_TI_COMMON_CMD_OPTIONS=y +@@ -20,7 +21,7 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_USB_HOST=y +@@ -29,6 +30,7 @@ + CONFIG_CMD_SPL=y + CONFIG_CMD_SPL_NAND_OFS=0x00100000 + CONFIG_CMD_SPL_WRITE_SIZE=0x40000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -54,9 +56,18 @@ + CONFIG_DFU_RAM=y + CONFIG_DFU_SF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_PHY_GIGE=y +@@ -75,11 +86,11 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_DWC3_PHY_OMAP=y +-CONFIG_OMAP_USB_PHY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" + CONFIG_USB_GADGET_VENDOR_NUM=0x0403 +diff -ruN u-boot-2021.10/configs/am43xx_evm_qspiboot_defconfig u-boot/configs/am43xx_evm_qspiboot_defconfig +--- u-boot-2021.10/configs/am43xx_evm_qspiboot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am43xx_evm_qspiboot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -11,7 +11,7 @@ + CONFIG_AM43XX=y + CONFIG_ENV_OFFSET_REDUND=0x120000 + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI,QSPI_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="QSPI" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -43,21 +43,24 @@ + CONFIG_DFU_MMC=y + CONFIG_DFU_RAM=y + CONFIG_DFU_SF=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_MII=y + CONFIG_DRIVER_TI_CPSW=y ++CONFIG_SPL_POWER_LEGACY=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_SYS_NS16550=y + CONFIG_SPI=y + CONFIG_TI_QSPI=y + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_PHY_OMAP=y +-CONFIG_OMAP_USB_PHY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" + CONFIG_USB_GADGET_VENDOR_NUM=0x0403 +diff -ruN u-boot-2021.10/configs/am43xx_evm_rtconly_defconfig u-boot/configs/am43xx_evm_rtconly_defconfig +--- u-boot-2021.10/configs/am43xx_evm_rtconly_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am43xx_evm_rtconly_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_TI_COMMON_CMD_OPTIONS=y +@@ -23,6 +24,7 @@ + CONFIG_CMD_SPL=y + CONFIG_CMD_SPL_NAND_OFS=0x00100000 + CONFIG_CMD_SPL_WRITE_SIZE=0x40000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -41,9 +43,18 @@ + CONFIG_DFU_MMC=y + CONFIG_DFU_RAM=y + CONFIG_DFU_SF=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_PHY_GIGE=y +@@ -57,10 +68,10 @@ + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_PHY_OMAP=y +-CONFIG_OMAP_USB_PHY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" + CONFIG_USB_GADGET_VENDOR_NUM=0x0403 +diff -ruN u-boot-2021.10/configs/am43xx_evm_usbhost_boot_defconfig u-boot/configs/am43xx_evm_usbhost_boot_defconfig +--- u-boot-2021.10/configs/am43xx_evm_usbhost_boot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am43xx_evm_usbhost_boot_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_ISW_ENTRY_ADDR=0x40300350 +@@ -22,7 +23,6 @@ + CONFIG_SPL_USB_HOST=y + CONFIG_SPL_USB_STORAGE=y + CONFIG_SPL_USB_GADGET=y +-CONFIG_SPL_USB_ETHER=y + CONFIG_CMD_SPL=y + CONFIG_CMD_SPL_NAND_OFS=0x00100000 + CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +@@ -63,6 +63,14 @@ + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_PHY_GIGE=y +@@ -79,11 +87,11 @@ + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_DWC3_PHY_OMAP=y +-CONFIG_OMAP_USB_PHY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" + CONFIG_USB_GADGET_VENDOR_NUM=0x0403 +diff -ruN u-boot-2021.10/configs/am43xx_hs_evm_defconfig u-boot/configs/am43xx_hs_evm_defconfig +--- u-boot-2021.10/configs/am43xx_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am43xx_hs_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_TI_SECURE_DEVICE=y +@@ -29,11 +30,12 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_ECC=y + CONFIG_SPL_NAND_BASE=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" + CONFIG_SPL_USB_HOST=y + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_USB_ETHER=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -59,9 +61,18 @@ + CONFIG_DFU_RAM=y + CONFIG_DFU_SF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000 + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_PHY_GIGE=y +@@ -80,11 +91,11 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_DWC3_PHY_OMAP=y +-CONFIG_OMAP_USB_PHY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" + CONFIG_USB_GADGET_VENDOR_NUM=0x0403 +diff -ruN u-boot-2021.10/configs/am57xx_evm_defconfig u-boot/configs/am57xx_evm_defconfig +--- u-boot-2021.10/configs/am57xx_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am57xx_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -12,7 +12,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -39,6 +39,7 @@ + CONFIG_CMD_ADTIMG=y + CONFIG_CMD_ABOOTIMG=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_BCB=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set +@@ -78,6 +79,7 @@ + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y +@@ -106,6 +108,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_GADGET=y +diff -ruN u-boot-2021.10/configs/am57xx_hs_evm_defconfig u-boot/configs/am57xx_hs_evm_defconfig +--- u-boot-2021.10/configs/am57xx_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am57xx_hs_evm_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -15,7 +15,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -41,6 +41,7 @@ + CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 + CONFIG_CMD_ADTIMG=y + CONFIG_CMD_ABOOTIMG=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_BCB=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set +@@ -74,6 +75,7 @@ + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y +@@ -102,6 +104,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_GADGET=y +diff -ruN u-boot-2021.10/configs/am57xx_hs_evm_usb_defconfig u-boot/configs/am57xx_hs_evm_usb_defconfig +--- u-boot-2021.10/configs/am57xx_hs_evm_usb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am57xx_hs_evm_usb_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -17,7 +17,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -48,6 +48,7 @@ + CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_CMD_ADTIMG=y + CONFIG_CMD_ABOOTIMG=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_BCB=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set +@@ -81,6 +82,7 @@ + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y +@@ -110,6 +112,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_GADGET=y +diff -ruN u-boot-2021.10/configs/am64x_evm_a53_defconfig u-boot/configs/am64x_evm_a53_defconfig +--- u-boot-2021.10/configs/am64x_evm_a53_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am64x_evm_a53_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_K3=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y +@@ -9,17 +10,18 @@ + CONFIG_TARGET_AM642_A53_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/am64x_evm_r5_defconfig u-boot/configs/am64x_evm_r5_defconfig +--- u-boot-2021.10/configs/am64x_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am64x_evm_r5_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,12 +8,13 @@ + CONFIG_TARGET_AM642_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm" + CONFIG_SPL_TEXT_BASE=0x70000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_SIZE_LIMIT=0x190000 +@@ -21,7 +22,7 @@ + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 + # CONFIG_DISPLAY_CPUINFO is not set +@@ -40,7 +41,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/am65x_evm_a53_defconfig u-boot/configs/am65x_evm_a53_defconfig +--- u-boot-2021.10/configs/am65x_evm_a53_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_evm_a53_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_K3=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y +@@ -8,19 +9,20 @@ + CONFIG_TARGET_AM654_A53_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x6A0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/am65x_evm_r5_defconfig u-boot/configs/am65x_evm_r5_defconfig +--- u-boot-2021.10/configs/am65x_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_evm_r5_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,12 +9,13 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_AM654_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_SIZE_LIMIT=0x7ec00 +@@ -22,7 +23,7 @@ + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +@@ -41,7 +42,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/am65x_evm_r5_usbdfu_defconfig u-boot/configs/am65x_evm_r5_usbdfu_defconfig +--- u-boot-2021.10/configs/am65x_evm_r5_usbdfu_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_evm_r5_usbdfu_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -9,10 +9,11 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_AM654_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y +@@ -30,7 +31,6 @@ + CONFIG_SPL_I2C=y + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/am65x_evm_r5_usbmsc_defconfig u-boot/configs/am65x_evm_r5_usbmsc_defconfig +--- u-boot-2021.10/configs/am65x_evm_r5_usbmsc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_evm_r5_usbmsc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -9,10 +9,11 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_AM654_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y +@@ -29,7 +30,6 @@ + CONFIG_SPL_I2C=y + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/am65x_hs_evm_a53_defconfig u-boot/configs/am65x_hs_evm_a53_defconfig +--- u-boot-2021.10/configs/am65x_hs_evm_a53_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_hs_evm_a53_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_K3=y + CONFIG_TI_SECURE_DEVICE=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -9,19 +10,20 @@ + CONFIG_TARGET_AM654_A53_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x6A0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/am65x_hs_evm_r5_defconfig u-boot/configs/am65x_hs_evm_r5_defconfig +--- u-boot-2021.10/configs/am65x_hs_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/am65x_hs_evm_r5_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -10,18 +10,19 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_AM654_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +@@ -38,7 +39,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/amcore_defconfig u-boot/configs/amcore_defconfig +--- u-boot-2021.10/configs/amcore_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/amcore_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -3,8 +3,10 @@ + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="amcore" + CONFIG_TARGET_AMCORE=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=1 + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/Ampe_A76_defconfig u-boot/configs/Ampe_A76_defconfig +--- u-boot-2021.10/configs/Ampe_A76_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Ampe_A76_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +@@ -16,5 +14,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/ap121_defconfig u-boot/configs/ap121_defconfig +--- u-boot-2021.10/configs/ap121_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ap121_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -6,12 +6,14 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x40000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="ap121" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xb8020000 + CONFIG_DEBUG_UART_CLOCK=25000000 + CONFIG_ARCH_ATH79=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +diff -ruN u-boot-2021.10/configs/ap143_defconfig u-boot/configs/ap143_defconfig +--- u-boot-2021.10/configs/ap143_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ap143_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x40000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="ap143" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xb8020000 +@@ -13,6 +14,7 @@ + CONFIG_ARCH_ATH79=y + CONFIG_TARGET_AP143=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +diff -ruN u-boot-2021.10/configs/ap152_defconfig u-boot/configs/ap152_defconfig +--- u-boot-2021.10/configs/ap152_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ap152_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x40000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="ap152" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xb8020000 +@@ -13,6 +14,7 @@ + CONFIG_ARCH_ATH79=y + CONFIG_TARGET_AP152=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +diff -ruN u-boot-2021.10/configs/apalis_imx6_defconfig u-boot/configs/apalis_imx6_defconfig +--- u-boot-2021.10/configs/apalis_imx6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/apalis_imx6_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -11,17 +11,20 @@ + CONFIG_ENV_OFFSET=0xFFFFDE00 + CONFIG_MX6Q=y + CONFIG_TARGET_APALIS_IMX6=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +@@ -70,6 +73,9 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_MXC_I2C3_SPEED=400000 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/apalis-imx8_defconfig u-boot/configs/apalis-imx8_defconfig +--- u-boot-2021.10/configs/apalis-imx8_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/apalis-imx8_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,13 +7,14 @@ + CONFIG_SYS_MEMTEST_END=0x89000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" + CONFIG_TARGET_APALIS_IMX8=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8-imximage.cfg" + CONFIG_LOG=y + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_BOARD_EARLY_INIT_F=y +@@ -34,6 +35,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=4096 +diff -ruN u-boot-2021.10/configs/apalis-imx8x_defconfig u-boot/configs/apalis-imx8x_defconfig +--- u-boot-2021.10/configs/apalis-imx8x_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/apalis-imx8x_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,13 +7,14 @@ + CONFIG_SYS_MEMTEST_END=0x89000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" + CONFIG_TARGET_APALIS_IMX8X=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x89000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" + CONFIG_BOOTDELAY=1 + CONFIG_LOG=y + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -36,6 +37,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_IP_DEFRAG=y +diff -ruN u-boot-2021.10/configs/apalis_t30_defconfig u-boot/configs/apalis_t30_defconfig +--- u-boot-2021.10/configs/apalis_t30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/apalis_t30_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA30=y + CONFIG_TARGET_APALIS_T30=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/apalis-tk1_defconfig u-boot/configs/apalis-tk1_defconfig +--- u-boot-2021.10/configs/apalis-tk1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/apalis-tk1_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA124=y + CONFIG_TARGET_APALIS_TK1=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_BOOTDELAY=1 +diff -ruN u-boot-2021.10/configs/aristainetos2ccslb_defconfig u-boot/configs/aristainetos2ccslb_defconfig +--- u-boot-2021.10/configs/aristainetos2ccslb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/aristainetos2ccslb_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -13,7 +13,6 @@ + # CONFIG_CMD_DEKBLOB is not set + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" + CONFIG_BOOTDELAY=-2 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_ENCRYPTION=y +diff -ruN u-boot-2021.10/configs/aristainetos2c_defconfig u-boot/configs/aristainetos2c_defconfig +--- u-boot-2021.10/configs/aristainetos2c_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/aristainetos2c_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -13,7 +13,6 @@ + # CONFIG_CMD_DEKBLOB is not set + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" + CONFIG_BOOTDELAY=-2 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_ENCRYPTION=y +diff -ruN u-boot-2021.10/configs/armadillo-800eva_defconfig u-boot/configs/armadillo-800eva_defconfig +--- u-boot-2021.10/configs/armadillo-800eva_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/armadillo-800eva_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,9 +7,11 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board" + CONFIG_R8A7740=y + CONFIG_TARGET_ARMADILLO_800EVA=y ++CONFIG_SYS_LOAD_ADDR=0x44000000 + CONFIG_BOOTDELAY=3 + # CONFIG_CMDLINE_EDITING is not set + # CONFIG_AUTO_COMPLETE is not set +diff -ruN u-boot-2021.10/configs/arndale_defconfig u-boot/configs/arndale_defconfig +--- u-boot-2021.10/configs/arndale_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/arndale_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x43E00000 +@@ -7,11 +9,13 @@ + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x86200 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" + CONFIG_SPL_TEXT_BASE=0x02023400 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for ARNDALE" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_USE_PREBOOT=y +@@ -31,6 +35,7 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_DW=y + CONFIG_MMC_SDHCI=y +diff -ruN u-boot-2021.10/configs/aspenite_defconfig u-boot/configs/aspenite_defconfig +--- u-boot-2021.10/configs/aspenite_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/aspenite_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,17 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_ARCH_CPU_INIT=y +-CONFIG_TARGET_ASPENITE=y +-CONFIG_SYS_TEXT_BASE=0x600000 +-CONFIG_NR_DRAM_BANKS=2 +-CONFIG_ENV_SIZE=0x20000 +-CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" +-CONFIG_BOOTDELAY=3 +-CONFIG_USE_PREBOOT=y +-# CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_BOARD_EARLY_INIT_F=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_SYS_RELOC_GD_ENV_ADDR=y +-# CONFIG_NET is not set +-# CONFIG_MMC is not set +-CONFIG_SYS_NS16550=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/astro_mcf5373l_defconfig u-boot/configs/astro_mcf5373l_defconfig +--- u-boot-2021.10/configs/astro_mcf5373l_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/astro_mcf5373l_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_ENV_SIZE=0x8000 + CONFIG_ENV_SECT_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l" + CONFIG_TARGET_ASTRO_MCF5373L=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" +@@ -25,6 +27,11 @@ + CONFIG_FPGA_CYCLON2=y + CONFIG_FPGA_XILINX=y + CONFIG_FPGA_SPARTAN3=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +diff -ruN u-boot-2021.10/configs/at91sam9260ek_dataflash_cs0_defconfig u-boot/configs/at91sam9260ek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9260ek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9260ek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9260ek_dataflash_cs1_defconfig u-boot/configs/at91sam9260ek_dataflash_cs1_defconfig +--- u-boot-2021.10/configs/at91sam9260ek_dataflash_cs1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9260ek_dataflash_cs1_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9260ek_nandflash_defconfig u-boot/configs/at91sam9260ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9260ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9260ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9260EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9261ek_dataflash_cs0_defconfig u-boot/configs/at91sam9261ek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9261ek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9261ek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9261ek_dataflash_cs3_defconfig u-boot/configs/at91sam9261ek_dataflash_cs3_defconfig +--- u-boot-2021.10/configs/at91sam9261ek_dataflash_cs3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9261ek_dataflash_cs3_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9261ek_nandflash_defconfig u-boot/configs/at91sam9261ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9261ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9261ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9263ek_dataflash_cs0_defconfig u-boot/configs/at91sam9263ek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9263ek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9263ek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9263ek_dataflash_defconfig u-boot/configs/at91sam9263ek_dataflash_defconfig +--- u-boot-2021.10/configs/at91sam9263ek_dataflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9263ek_dataflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9263ek_nandflash_defconfig u-boot/configs/at91sam9263ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9263ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9263ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 + CONFIG_TARGET_AT91SAM9263EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9263ek_norflash_boot_defconfig u-boot/configs/at91sam9263ek_norflash_boot_defconfig +--- u-boot-2021.10/configs/at91sam9263ek_norflash_boot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9263ek_norflash_boot_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,12 +7,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x50000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +diff -ruN u-boot-2021.10/configs/at91sam9263ek_norflash_defconfig u-boot/configs/at91sam9263ek_norflash_defconfig +--- u-boot-2021.10/configs/at91sam9263ek_norflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9263ek_norflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -7,12 +8,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x50000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +diff -ruN u-boot-2021.10/configs/at91sam9g10ek_dataflash_cs0_defconfig u-boot/configs/at91sam9g10ek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9g10ek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g10ek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g10ek_dataflash_cs3_defconfig u-boot/configs/at91sam9g10ek_dataflash_cs3_defconfig +--- u-boot-2021.10/configs/at91sam9g10ek_dataflash_cs3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g10ek_dataflash_cs3_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g10ek_nandflash_defconfig u-boot/configs/at91sam9g10ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9g10ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g10ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9261EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g20ek_2mmc_defconfig u-boot/configs/at91sam9g20ek_2mmc_defconfig +--- u-boot-2021.10/configs/at91sam9g20ek_2mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g20ek_2mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -7,12 +8,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x23000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g20ek_2mmc_nandflash_defconfig u-boot/configs/at91sam9g20ek_2mmc_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9g20ek_2mmc_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g20ek_2mmc_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9260EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g20ek_dataflash_cs0_defconfig u-boot/configs/at91sam9g20ek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9g20ek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g20ek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g20ek_dataflash_cs1_defconfig u-boot/configs/at91sam9g20ek_dataflash_cs1_defconfig +--- u-boot-2021.10/configs/at91sam9g20ek_dataflash_cs1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g20ek_dataflash_cs1_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9g20ek_nandflash_defconfig u-boot/configs/at91sam9g20ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9g20ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9g20ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9260EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9m10g45ek_mmc_defconfig u-boot/configs/at91sam9m10g45ek_mmc_defconfig +--- u-boot-2021.10/configs/at91sam9m10g45ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9m10g45ek_mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,16 +1,19 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x73f00000 + CONFIG_TARGET_AT91SAM9M10G45EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x2c000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9m10g45ek_nandflash_defconfig u-boot/configs/at91sam9m10g45ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9m10g45ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9m10g45ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x73f00000 + CONFIG_TARGET_AT91SAM9M10G45EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9n12ek_mmc_defconfig u-boot/configs/at91sam9n12ek_mmc_defconfig +--- u-boot-2021.10/configs/at91sam9n12ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9n12ek_mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9N12EK=y +@@ -11,6 +12,7 @@ + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +diff -ruN u-boot-2021.10/configs/at91sam9n12ek_nandflash_defconfig u-boot/configs/at91sam9n12ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9n12ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9n12ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9N12EK=y +@@ -11,6 +12,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -41,6 +43,8 @@ + CONFIG_MTD=y + CONFIG_NAND_ATMEL=y + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/at91sam9n12ek_spiflash_defconfig u-boot/configs/at91sam9n12ek_spiflash_defconfig +--- u-boot-2021.10/configs/at91sam9n12ek_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9n12ek_spiflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9N12EK=y +@@ -13,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +diff -ruN u-boot-2021.10/configs/at91sam9rlek_dataflash_defconfig u-boot/configs/at91sam9rlek_dataflash_defconfig +--- u-boot-2021.10/configs/at91sam9rlek_dataflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9rlek_dataflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9rlek_mmc_defconfig u-boot/configs/at91sam9rlek_mmc_defconfig +--- u-boot-2021.10/configs/at91sam9rlek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9rlek_mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -6,12 +7,14 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x2c000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9rlek_nandflash_defconfig u-boot/configs/at91sam9rlek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9rlek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9rlek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 + CONFIG_TARGET_AT91SAM9RLEK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9x5ek_dataflash_defconfig u-boot/configs/at91sam9x5ek_dataflash_defconfig +--- u-boot-2021.10/configs/at91sam9x5ek_dataflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9x5ek_dataflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9X5EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 +@@ -47,6 +50,8 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ATMEL=y + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/at91sam9x5ek_mmc_defconfig u-boot/configs/at91sam9x5ek_mmc_defconfig +--- u-boot-2021.10/configs/at91sam9x5ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9x5ek_mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,16 +1,19 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9X5EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/at91sam9x5ek_nandflash_defconfig u-boot/configs/at91sam9x5ek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9x5ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9x5ek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9X5EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -45,6 +48,8 @@ + CONFIG_MTD=y + CONFIG_NAND_ATMEL=y + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/at91sam9x5ek_spiflash_defconfig u-boot/configs/at91sam9x5ek_spiflash_defconfig +--- u-boot-2021.10/configs/at91sam9x5ek_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9x5ek_spiflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_AT91SAM9X5EK=y +@@ -7,12 +8,14 @@ + CONFIG_ENV_SIZE=0x3000 + CONFIG_ENV_OFFSET=0x5000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/at91sam9xeek_dataflash_cs0_defconfig u-boot/configs/at91sam9xeek_dataflash_cs0_defconfig +--- u-boot-2021.10/configs/at91sam9xeek_dataflash_cs0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9xeek_dataflash_cs0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9xeek_dataflash_cs1_defconfig u-boot/configs/at91sam9xeek_dataflash_cs1_defconfig +--- u-boot-2021.10/configs/at91sam9xeek_dataflash_cs1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9xeek_dataflash_cs1_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -8,12 +9,14 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/at91sam9xeek_nandflash_defconfig u-boot/configs/at91sam9xeek_nandflash_defconfig +--- u-boot-2021.10/configs/at91sam9xeek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/at91sam9xeek_nandflash_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 + CONFIG_TARGET_AT91SAM9260EK=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/Auxtek-T003_defconfig u-boot/configs/Auxtek-T003_defconfig +--- u-boot-2021.10/configs/Auxtek-T003_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Auxtek-T003_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,10 +5,13 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=0 +-CONFIG_USB1_VBUS_PIN="PB10" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP152_POWER=y + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/Auxtek-T004_defconfig u-boot/configs/Auxtek-T004_defconfig +--- u-boot-2021.10/configs/Auxtek-T004_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Auxtek-T004_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,9 +4,12 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=432 +-CONFIG_USB1_VBUS_PIN="PG13" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP152_POWER=y + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig u-boot/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +--- u-boot-2021.10/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,17 +4,19 @@ + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SYS_MEMTEST_START=0x00000000 + CONFIG_SYS_MEMTEST_END=0x00001000 ++CONFIG_SYS_MALLOC_LEN=0x4008000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ZYNQ_MAC_IN_EEPROM=y + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/axm_defconfig u-boot/configs/axm_defconfig +--- u-boot-2021.10/configs/axm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/axm_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SPL_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y +@@ -14,6 +16,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x460000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +@@ -22,9 +25,10 @@ + CONFIG_DEBUG_UART_CLOCK=18432000 + CONFIG_ENV_OFFSET_REDUND=0x180000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y +-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068" ++CONFIG_SYS_LOAD_ADDR=0x22000000 ++CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTCOMMAND=y + CONFIG_BOOTCOMMAND="run flash_self" +@@ -69,6 +73,12 @@ + CONFIG_MTD_RAW_NAND=y + # CONFIG_SYS_NAND_USE_FLASH_BBT is not set + CONFIG_NAND_ATMEL=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/axs101_defconfig u-boot/configs/axs101_defconfig +--- u-boot-2021.10/configs/axs101_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/axs101_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,12 +1,14 @@ + CONFIG_ARC=y + CONFIG_TARGET_AXS101=y + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="axs101" + CONFIG_DEBUG_UART_BASE=0xe0022000 + CONFIG_DEBUG_UART_CLOCK=33333333 + CONFIG_SYS_CLK_FREQ=750000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS3,115200n8" +diff -ruN u-boot-2021.10/configs/axs103_defconfig u-boot/configs/axs103_defconfig +--- u-boot-2021.10/configs/axs103_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/axs103_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,12 +1,14 @@ + CONFIG_ARC=y + CONFIG_ISA_ARCV2=y + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="axs103" + CONFIG_DEBUG_UART_BASE=0xe0022000 + CONFIG_DEBUG_UART_CLOCK=33333333 + CONFIG_SYS_CLK_FREQ=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS3,115200n8" +diff -ruN u-boot-2021.10/configs/ba10_tv_box_defconfig u-boot/configs/ba10_tv_box_defconfig +--- u-boot-2021.10/configs/ba10_tv_box_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ba10_tv_box_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -5,11 +5,13 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=384 + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB2_VBUS_PIN="PH12" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/Bananapi_defconfig u-boot/configs/Bananapi_defconfig +--- u-boot-2021.10/configs/Bananapi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Bananapi_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -12,6 +12,9 @@ + CONFIG_SPL_I2C=y + CONFIG_NETCONSOLE=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +@@ -20,3 +23,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/bananapi_m1_plus_defconfig u-boot/configs/bananapi_m1_plus_defconfig +--- u-boot-2021.10/configs/bananapi_m1_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bananapi_m1_plus_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -12,6 +12,9 @@ + CONFIG_SPL_I2C=y + CONFIG_NETCONSOLE=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +@@ -20,3 +23,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/bananapi_m2_berry_defconfig u-boot/configs/bananapi_m2_berry_defconfig +--- u-boot-2021.10/configs/bananapi_m2_berry_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bananapi_m2_berry_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -5,11 +5,15 @@ + CONFIG_MACH_SUN8I_R40=y + CONFIG_DRAM_CLK=576 + CONFIG_MMC0_CD_PIN="PH13" +-CONFIG_USB1_VBUS_PIN="PH23" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_RGMII=y + CONFIG_SUN8I_EMAC=y + CONFIG_AXP_DLDO4_VOLT=2500 +diff -ruN u-boot-2021.10/configs/Bananapi_m2m_defconfig u-boot/configs/Bananapi_m2m_defconfig +--- u-boot-2021.10/configs/Bananapi_m2m_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Bananapi_m2m_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -8,7 +8,6 @@ + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="PB4" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_ID_DET="PH8" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/Bananapi_M2_Ultra_defconfig u-boot/configs/Bananapi_M2_Ultra_defconfig +--- u-boot-2021.10/configs/Bananapi_M2_Ultra_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Bananapi_M2_Ultra_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -7,12 +7,15 @@ + CONFIG_MACPWR="PA17" + CONFIG_MMC0_CD_PIN="PH13" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB1_VBUS_PIN="PH23" +-CONFIG_USB2_VBUS_PIN="PH23" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_RGMII=y + CONFIG_SUN8I_EMAC=y + CONFIG_AXP_DLDO4_VOLT=2500 +diff -ruN u-boot-2021.10/configs/bananapi-m5_defconfig u-boot/configs/bananapi-m5_defconfig +--- u-boot-2021.10/configs/bananapi-m5_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/bananapi-m5_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -0,0 +1,74 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING="bpi-m5" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_ADC=y ++CONFIG_SARADC_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_BMP_RLE8=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/Bananapro_defconfig u-boot/configs/Bananapro_defconfig +--- u-boot-2021.10/configs/Bananapro_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Bananapro_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,7 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=432 + CONFIG_MACPWR="PH23" +-CONFIG_USB1_VBUS_PIN="PH0" +-CONFIG_USB2_VBUS_PIN="PH1" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + CONFIG_GMAC_TX_DELAY=3 + CONFIG_AHCI=y +@@ -14,6 +13,9 @@ + CONFIG_SPL_I2C=y + CONFIG_NETCONSOLE=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +diff -ruN u-boot-2021.10/configs/bcm7260_defconfig u-boot/configs/bcm7260_defconfig +--- u-boot-2021.10/configs/bcm7260_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm7260_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,11 +1,14 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_BCMSTB=y + CONFIG_SYS_TEXT_BASE=0x10100000 + CONFIG_TARGET_BCM7260=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x814800 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_ENV_OFFSET_REDUND=0x824800 ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_BOOTDELAY=1 +diff -ruN u-boot-2021.10/configs/bcm7445_defconfig u-boot/configs/bcm7445_defconfig +--- u-boot-2021.10/configs/bcm7445_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm7445_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_BCMSTB=y + CONFIG_SYS_TEXT_BASE=0x80100000 + CONFIG_TARGET_BCM7445=y +@@ -6,7 +7,9 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x1E0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_ENV_OFFSET_REDUND=0x1F0000 ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_BOOTDELAY=1 +diff -ruN u-boot-2021.10/configs/bcm963158_ram_defconfig u-boot/configs/bcm963158_ram_defconfig +--- u-boot-2021.10/configs/bcm963158_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm963158_ram_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,14 +1,17 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_ARM64_SUPPORT_AARCH32 is not set + CONFIG_ARCH_BCM63158=y + CONFIG_SYS_TEXT_BASE=0x10000000 + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="bcm963158" + CONFIG_TARGET_BCM963158=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_RSASSA_PSS=y +@@ -41,6 +44,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_BRCMNAND=y + CONFIG_NAND_BRCMNAND_63158=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPECIFY_CONSOLE_INDEX=y +diff -ruN u-boot-2021.10/configs/bcm968360bg_ram_defconfig u-boot/configs/bcm968360bg_ram_defconfig +--- u-boot-2021.10/configs/bcm968360bg_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm968360bg_ram_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,13 +1,16 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_BCM68360=y + CONFIG_SYS_TEXT_BASE=0x10000000 + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg" + CONFIG_TARGET_BCM968360BG=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -37,6 +40,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_BRCMNAND=y + CONFIG_NAND_BRCMNAND_68360=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_SFDP_SUPPORT=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/bcm968380gerg_ram_defconfig u-boot/configs/bcm968380gerg_ram_defconfig +--- u-boot-2021.10/configs/bcm968380gerg_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm968380gerg_ram_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6838=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +@@ -44,6 +48,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_BRCMNAND=y + CONFIG_NAND_BRCMNAND_6838=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY=y + CONFIG_BCM6368_USBH_PHY=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/bcm968580xref_ram_defconfig u-boot/configs/bcm968580xref_ram_defconfig +--- u-boot-2021.10/configs/bcm968580xref_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm968580xref_ram_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,13 +1,16 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_BCM6858=y + CONFIG_SYS_TEXT_BASE=0x10000000 + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" + CONFIG_TARGET_BCM968580XREF=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -37,6 +40,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_BRCMNAND=y + CONFIG_NAND_BRCMNAND_6858=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_SFDP_SUPPORT=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/bcm_ns3_defconfig u-boot/configs/bcm_ns3_defconfig +--- u-boot-2021.10/configs/bcm_ns3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bcm_ns3_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,7 +4,9 @@ + CONFIG_SYS_TEXT_BASE=0xFF000000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x80000 ++CONFIG_SYS_MALLOC_LEN=0xc00000 + CONFIG_DEFAULT_DEVICE_TREE="ns3-board" ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_SIGNATURE_MAX_SIZE=0x20000000 +diff -ruN u-boot-2021.10/configs/beaver_defconfig u-boot/configs/beaver_defconfig +--- u-boot-2021.10/configs/beaver_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/beaver_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,10 +4,12 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA30=y + CONFIG_TARGET_BEAVER=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/beelink-gsking-x_defconfig u-boot/configs/beelink-gsking-x_defconfig +--- u-boot-2021.10/configs/beelink-gsking-x_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/beelink-gsking-x_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -0,0 +1,71 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="beelink-s922x" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" beelink" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/beelink-gtking_defconfig u-boot/configs/beelink-gtking_defconfig +--- u-boot-2021.10/configs/beelink-gtking_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/beelink-gtking_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" beelink" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/beelink-gtkingpro_defconfig u-boot/configs/beelink-gtkingpro_defconfig +--- u-boot-2021.10/configs/beelink-gtkingpro_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/beelink-gtkingpro_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" beelink" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/bg0900_defconfig u-boot/configs/bg0900_defconfig +--- u-boot-2021.10/configs/bg0900_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bg0900_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,41 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_ARCH_MX28=y +-CONFIG_SYS_TEXT_BASE=0x40002000 +-CONFIG_SPL_GPIO=y +-CONFIG_SPL_LIBCOMMON_SUPPORT=y +-CONFIG_SPL_LIBGENERIC_SUPPORT=y +-CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x4000 +-CONFIG_SPL_TEXT_BASE=0x00001000 +-CONFIG_TARGET_BG0900=y +-CONFIG_SPL_SERIAL_SUPPORT=y +-CONFIG_SPL=y +-CONFIG_BOOTDELAY=3 +-CONFIG_USE_BOOTARGS=y +-CONFIG_BOOTARGS="console=ttyAMA0,115200" +-# CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_ARCH_MISC_INIT=y +-CONFIG_BOARD_EARLY_INIT_F=y +-# CONFIG_SPL_FRAMEWORK is not set +-CONFIG_HUSH_PARSER=y +-CONFIG_CMD_BOOTZ=y +-# CONFIG_CMD_FLASH is not set +-CONFIG_CMD_GPIO=y +-CONFIG_CMD_NAND_TRIMFFS=y +-CONFIG_CMD_DHCP=y +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_CACHE=y +-CONFIG_DOS_PARTITION=y +-CONFIG_ENV_OVERWRITE=y +-CONFIG_SYS_RELOC_GD_ENV_ADDR=y +-CONFIG_VERSION_VARIABLE=y +-CONFIG_MXS_GPIO=y +-# CONFIG_MMC is not set +-CONFIG_MTD=y +-CONFIG_MTD_RAW_NAND=y +-CONFIG_NAND_MXS=y +-CONFIG_MII=y +-CONFIG_CONS_INDEX=0 +-CONFIG_SPI=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/bitmain_antminer_s9_defconfig u-boot/configs/bitmain_antminer_s9_defconfig +--- u-boot-2021.10/configs/bitmain_antminer_s9_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bitmain_antminer_s9_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -16,6 +16,7 @@ + CONFIG_DEBUG_UART=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -65,6 +66,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ZYNQ=y + CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MII=y + CONFIG_ZYNQ_GEM=y + CONFIG_DEBUG_UART_ZYNQ=y +diff -ruN u-boot-2021.10/configs/bk4r1_defconfig u-boot/configs/bk4r1_defconfig +--- u-boot-2021.10/configs/bk4r1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bk4r1_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_VF610=y + CONFIG_SYS_TEXT_BASE=0x3f401000 +@@ -8,6 +9,7 @@ + CONFIG_SYS_MEMTEST_END=0x87c00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x200000 ++CONFIG_SYS_MALLOC_LEN=0x402000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 +@@ -15,8 +17,8 @@ + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_ENV_OFFSET_REDUND=0x220000 + CONFIG_TARGET_BK4R1=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Enter passphrase to stop autoboot, booting in %d seconds\n" +@@ -58,15 +60,12 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_I2C_EEPROM_BUS=2 +-CONFIG_SYS_EEPROM_SIZE=32768 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_NAND_VF610_NFC=y + CONFIG_NAND_VF610_NFC_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y +diff -ruN u-boot-2021.10/configs/blanche_defconfig u-boot/configs/blanche_defconfig +--- u-boot-2021.10/configs/blanche_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/blanche_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -8,11 +8,13 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot" + CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche" + CONFIG_R8A7792=y + CONFIG_TARGET_BLANCHE=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/boston32r2_defconfig u-boot/configs/boston32r2_defconfig +--- u-boot-2021.10/configs/boston32r2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston32r2_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,12 +4,14 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston32r2el_defconfig u-boot/configs/boston32r2el_defconfig +--- u-boot-2021.10/configs/boston32r2el_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston32r2el_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_SYS_LITTLE_ENDIAN=y +@@ -11,6 +12,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston32r6_defconfig u-boot/configs/boston32r6_defconfig +--- u-boot-2021.10/configs/boston32r6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston32r6_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_CPU_MIPS32_R6=y +@@ -11,6 +12,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston32r6el_defconfig u-boot/configs/boston32r6el_defconfig +--- u-boot-2021.10/configs/boston32r6el_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston32r6el_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_SYS_LITTLE_ENDIAN=y +@@ -12,6 +13,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston64r2_defconfig u-boot/configs/boston64r2_defconfig +--- u-boot-2021.10/configs/boston64r2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston64r2_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_CPU_MIPS64_R2=y +@@ -11,6 +12,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston64r2el_defconfig u-boot/configs/boston64r2el_defconfig +--- u-boot-2021.10/configs/boston64r2el_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston64r2el_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_SYS_LITTLE_ENDIAN=y +@@ -12,6 +13,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston64r6_defconfig u-boot/configs/boston64r6_defconfig +--- u-boot-2021.10/configs/boston64r6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston64r6_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_CPU_MIPS64_R6=y +@@ -11,6 +12,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/boston64r6el_defconfig u-boot/configs/boston64r6el_defconfig +--- u-boot-2021.10/configs/boston64r6el_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/boston64r6el_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x90000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="img,boston" + CONFIG_TARGET_BOSTON=y + CONFIG_SYS_LITTLE_ENDIAN=y +@@ -12,6 +13,7 @@ + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/brppt1_mmc_defconfig u-boot/configs/brppt1_mmc_defconfig +--- u-boot-2021.10/configs/brppt1_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brppt1_mmc_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,15 +7,17 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc" + CONFIG_AM33XX=y + CONFIG_TARGET_BRPPT1=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x50000 + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTDELAY=0 +diff -ruN u-boot-2021.10/configs/brppt1_nand_defconfig u-boot/configs/brppt1_nand_defconfig +--- u-boot-2021.10/configs/brppt1_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brppt1_nand_defconfig 2021-11-01 17:10:14.169597590 +0100 +@@ -7,13 +7,15 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x60000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand" + CONFIG_AM33XX=y + CONFIG_TARGET_BRPPT1=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTDELAY=0 +@@ -87,6 +89,10 @@ + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_PHY_NATSEMI=y +diff -ruN u-boot-2021.10/configs/brppt1_spi_defconfig u-boot/configs/brppt1_spi_defconfig +--- u-boot-2021.10/configs/brppt1_spi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brppt1_spi_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -8,17 +8,19 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x20000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi" + CONFIG_AM33XX=y + CONFIG_TARGET_BRPPT1=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x30000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_OF_BOARD_SETUP=y + CONFIG_SPI_BOOT=y +diff -ruN u-boot-2021.10/configs/brppt2_defconfig u-boot/configs/brppt2_defconfig +--- u-boot-2021.10/configs/brppt2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brppt2_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -14,17 +14,18 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6QDL=y + CONFIG_TARGET_BRPPT2=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-brppt2" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 + CONFIG_SPL=y + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_CMD_BMODE is not set + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x10700000 + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=0 + CONFIG_USE_BOOTCOMMAND=y +diff -ruN u-boot-2021.10/configs/brsmarc1_defconfig u-boot/configs/brsmarc1_defconfig +--- u-boot-2021.10/configs/brsmarc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brsmarc1_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -7,19 +7,21 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x20000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=600 + CONFIG_TARGET_BRSMARC1=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x30000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTDELAY=0 +diff -ruN u-boot-2021.10/configs/brxre1_defconfig u-boot/configs/brxre1_defconfig +--- u-boot-2021.10/configs/brxre1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/brxre1_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -6,17 +6,19 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-brxre1" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=1000 + CONFIG_TARGET_BRXRE1=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x50000 + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTDELAY=0 +diff -ruN u-boot-2021.10/configs/bubblegum_96_defconfig u-boot/configs/bubblegum_96_defconfig +--- u-boot-2021.10/configs/bubblegum_96_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/bubblegum_96_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y + CONFIG_ARCH_OWL=y + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" + CONFIG_MACH_S900=y + CONFIG_IDENT_STRING="\nBubblegum-96" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x7ffc0 + CONFIG_BOOTDELAY=5 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyOWL5,115200n8" +diff -ruN u-boot-2021.10/configs/cardhu_defconfig u-boot/configs/cardhu_defconfig +--- u-boot-2021.10/configs/cardhu_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cardhu_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA30=y + CONFIG_TARGET_CARDHU=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/cei-tk1-som_defconfig u-boot/configs/cei-tk1-som_defconfig +--- u-boot-2021.10/configs/cei-tk1-som_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cei-tk1-som_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,11 +4,13 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA124=y + CONFIG_TARGET_CEI_TK1_SOM=y + CONFIG_ARMV7_PSCI_0_1=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/cgtqmx8_defconfig u-boot/configs/cgtqmx8_defconfig +--- u-boot-2021.10/configs/cgtqmx8_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cgtqmx8_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -9,23 +9,23 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2400000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8" + CONFIG_TARGET_CONGA_QMX8=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_LOG=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +@@ -46,6 +46,7 @@ + CONFIG_SPL_OF_CONTROL=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_SPL_DM=y + CONFIG_SPL_CLK=y + CONFIG_CLK_IMX8=y +diff -ruN u-boot-2021.10/configs/chiliboard_defconfig u-boot/configs/chiliboard_defconfig +--- u-boot-2021.10/configs/chiliboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chiliboard_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -9,8 +9,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard" + CONFIG_AM33XX=y + CONFIG_TARGET_CHILIBOARD=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x22000 + CONFIG_SPL_FS_FAT=y +@@ -47,10 +47,19 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_BOOTCOUNT_LIMIT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MISC=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + CONFIG_PHY_SMSC=y + CONFIG_DM_ETH=y + CONFIG_MII=y +diff -ruN u-boot-2021.10/configs/CHIP_defconfig u-boot/configs/CHIP_defconfig +--- u-boot-2021.10/configs/CHIP_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/CHIP_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,12 +4,15 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +-CONFIG_USB0_VBUS_PIN="PB10" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + CONFIG_CHIP_DIP_SCAN=y + CONFIG_SPL_I2C=y + CONFIG_CMD_DFU=y + CONFIG_DFU_RAM=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_MMC is not set + CONFIG_AXP_ALDO3_VOLT=3300 + CONFIG_AXP_ALDO4_VOLT=3300 +diff -ruN u-boot-2021.10/configs/CHIP_pro_defconfig u-boot/configs/CHIP_pro_defconfig +--- u-boot-2021.10/configs/CHIP_pro_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/CHIP_pro_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,7 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +-CONFIG_USB0_VBUS_PIN="PB10" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SPL_I2C=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_MTDPARTS=y +@@ -13,10 +13,14 @@ + CONFIG_ENV_IS_IN_UBI=y + CONFIG_ENV_UBI_PART="UBI" + CONFIG_ENV_UBI_VOLUME="uboot-env" ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_PAGE_SIZE=0x1000 + CONFIG_SYS_NAND_OOBSIZE=0x100 + CONFIG_AXP_ALDO3_VOLT=3300 +diff -ruN u-boot-2021.10/configs/chromebit_mickey_defconfig u-boot/configs/chromebit_mickey_defconfig +--- u-boot-2021.10/configs/chromebit_mickey_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebit_mickey_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00100000 +@@ -6,15 +7,16 @@ + CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" + CONFIG_SPL_TEXT_BASE=0xff704000 + CONFIG_ROCKCHIP_RK3288=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_TARGET_CHROMEBIT_MICKEY=y + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/chromebook_bob_defconfig u-boot/configs/chromebook_bob_defconfig +--- u-boot-2021.10/configs/chromebook_bob_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_bob_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -9,12 +10,13 @@ + CONFIG_ROCKCHIP_RK3399=y + CONFIG_ROCKCHIP_BOOT_MODE_REG=0 + CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_DEBUG_UART_BASE=0xff1a0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/chromebook_coral_defconfig u-boot/configs/chromebook_coral_defconfig +--- u-boot-2021.10/configs/chromebook_coral_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_coral_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -44,7 +44,9 @@ + CONFIG_SPL_CPU=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_PCI=y ++CONFIG_SPL_POWER=y + # CONFIG_SPL_SPI_FLASH_TINY is not set ++CONFIG_TPL_POWER=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_CPU=y + CONFIG_CMD_PMC=y +diff -ruN u-boot-2021.10/configs/chromebook_jerry_defconfig u-boot/configs/chromebook_jerry_defconfig +--- u-boot-2021.10/configs/chromebook_jerry_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_jerry_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00100000 +@@ -6,14 +7,15 @@ + CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" + CONFIG_SPL_TEXT_BASE=0xff704000 + CONFIG_ROCKCHIP_RK3288=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" + CONFIG_SILENT_CONSOLE=y +diff -ruN u-boot-2021.10/configs/chromebook_link64_defconfig u-boot/configs/chromebook_link64_defconfig +--- u-boot-2021.10/configs/chromebook_link64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_link64_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -35,10 +35,10 @@ + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y + CONFIG_SPL_DM_SPI_FLASH=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_PCI=y +-CONFIG_SPL_PCH_SUPPORT=y +-CONFIG_SPL_RTC_SUPPORT=y ++CONFIG_SPL_PCH=y ++CONFIG_SPL_RTC=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_CPU=y + CONFIG_CMD_GPIO=y +diff -ruN u-boot-2021.10/configs/chromebook_minnie_defconfig u-boot/configs/chromebook_minnie_defconfig +--- u-boot-2021.10/configs/chromebook_minnie_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_minnie_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00100000 +@@ -6,15 +7,16 @@ + CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" + CONFIG_SPL_TEXT_BASE=0xff704000 + CONFIG_ROCKCHIP_RK3288=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_TARGET_CHROMEBOOK_MINNIE=y + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" + CONFIG_SILENT_CONSOLE=y +diff -ruN u-boot-2021.10/configs/chromebook_samus_tpl_defconfig u-boot/configs/chromebook_samus_tpl_defconfig +--- u-boot-2021.10/configs/chromebook_samus_tpl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_samus_tpl_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -34,11 +34,11 @@ + CONFIG_HANDOFF=y + CONFIG_SPL_SEPARATE_BSS=y + CONFIG_SPL_DM_SPI_FLASH=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_PCI=y +-CONFIG_SPL_PCH_SUPPORT=y ++CONFIG_SPL_PCH=y + CONFIG_TPL_PCI=y +-CONFIG_TPL_PCH_SUPPORT=y ++CONFIG_TPL_PCH=y + CONFIG_TPL_DM_SPI=y + CONFIG_TPL_DM_SPI_FLASH=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/chromebook_speedy_defconfig u-boot/configs/chromebook_speedy_defconfig +--- u-boot-2021.10/configs/chromebook_speedy_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/chromebook_speedy_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00100000 +@@ -6,15 +7,16 @@ + CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" + CONFIG_SPL_TEXT_BASE=0xff704000 + CONFIG_ROCKCHIP_RK3288=y +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_TARGET_CHROMEBOOK_SPEEDY=y + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" + CONFIG_SILENT_CONSOLE=y +diff -ruN u-boot-2021.10/configs/Chuwi_V7_CW0825_defconfig u-boot/configs/Chuwi_V7_CW0825_defconfig +--- u-boot-2021.10/configs/Chuwi_V7_CW0825_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Chuwi_V7_CW0825_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" +@@ -15,6 +13,9 @@ + CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y + CONFIG_VIDEO_LCD_SPI_CS="PA0" + CONFIG_VIDEO_LCD_SPI_SCLK="PA1" +diff -ruN u-boot-2021.10/configs/ci20_mmc_defconfig u-boot/configs/ci20_mmc_defconfig +--- u-boot-2021.10/configs/ci20_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ci20_mmc_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_SPL_GPIO=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y +@@ -6,11 +7,13 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x8000 + CONFIG_ENV_OFFSET=0x83800 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DEFAULT_DEVICE_TREE="ci20" + CONFIG_SPL_TEXT_BASE=0xf4000a00 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_ARCH_JZ47XX=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_FIT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1" +diff -ruN u-boot-2021.10/configs/clearfog_defconfig u-boot/configs/clearfog_defconfig +--- u-boot-2021.10/configs/clearfog_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/clearfog_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_MVEBU=y +@@ -12,13 +13,14 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/clearfog_gt_8k_defconfig u-boot/configs/clearfog_gt_8k_defconfig +--- u-boot-2021.10/configs/clearfog_gt_8k_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/clearfog_gt_8k_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -16,6 +16,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/cl-som-imx7_defconfig u-boot/configs/cl-som-imx7_defconfig +--- u-boot-2021.10/configs/cl-som-imx7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cl-som-imx7_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -7,18 +7,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" + CONFIG_TARGET_CL_SOM_IMX7=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_LATE_INIT=y +@@ -37,6 +38,7 @@ + # CONFIG_CMD_EXPORTENV is not set + # CONFIG_CMD_IMPORTENV is not set + CONFIG_CMD_GREPENV=y ++CONFIG_CMD_EEPROM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -60,6 +62,9 @@ + CONFIG_SPL_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_CMD_PCA953X=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -77,7 +82,9 @@ + CONFIG_PHYLIB=y + CONFIG_PHY_ATHEROS=y + CONFIG_MII=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_SPI=y + CONFIG_DM_SPI=y +diff -ruN u-boot-2021.10/configs/cm_fx6_defconfig u-boot/configs/cm_fx6_defconfig +--- u-boot-2021.10/configs/cm_fx6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cm_fx6_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,18 +10,21 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6QDL=y + CONFIG_TARGET_CM_FX6=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_CMD_BMODE is not set + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" + CONFIG_USE_PREBOOT=y +@@ -38,6 +41,9 @@ + CONFIG_CMD_EEPROM=y + CONFIG_CMD_EEPROM_LAYOUT=y + CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" ++CONFIG_SYS_I2C_EEPROM_BUS=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -63,10 +69,16 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y + # CONFIG_DWC_AHSATA_AHCI is not set ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_MXC_I2C3_SPEED=400000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=25000000 +diff -ruN u-boot-2021.10/configs/cm_t335_defconfig u-boot/configs/cm_t335_defconfig +--- u-boot-2021.10/configs/cm_t335_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cm_t335_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -8,8 +8,8 @@ + CONFIG_ENV_OFFSET=0x300000 + CONFIG_AM33XX=y + CONFIG_TARGET_CM_T335=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -30,6 +30,8 @@ + CONFIG_CMD_EEPROM=y + CONFIG_CMD_EEPROM_LAYOUT=y + CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -47,15 +49,25 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_CMD_PCA953X=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_LED_STATUS=y + CONFIG_LED_STATUS_GPIO=y + CONFIG_LED_STATUS0=y + CONFIG_LED_STATUS_BIT=64 + CONFIG_LED_STATUS_BOOT_ENABLE=y + CONFIG_LED_STATUS_BOOT=0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHY_ATHEROS=y + CONFIG_MII=y + CONFIG_DRIVER_TI_CPSW=y +diff -ruN u-boot-2021.10/configs/cm_t43_defconfig u-boot/configs/cm_t43_defconfig +--- u-boot-2021.10/configs/cm_t43_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cm_t43_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -12,13 +13,13 @@ + CONFIG_SPL_TEXT_BASE=0x40300350 + CONFIG_AM43XX=y + CONFIG_TARGET_CM_T43=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -42,6 +43,8 @@ + CONFIG_CMD_EEPROM=y + CONFIG_CMD_EEPROM_LAYOUT=y + CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -61,9 +64,14 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_DM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=48000000 + CONFIG_SPI_FLASH_ATMEL=y +@@ -77,6 +85,8 @@ + CONFIG_PHY_ATHEROS=y + CONFIG_MII=y + CONFIG_DRIVER_TI_CPSW=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_DM_SERIAL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y +@@ -84,4 +94,4 @@ + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y +-CONFIG_OMAP_USB_PHY=y ++CONFIG_USB_XHCI_OMAP=y +diff -ruN u-boot-2021.10/configs/cobra5272_defconfig u-boot/configs/cobra5272_defconfig +--- u-boot-2021.10/configs/cobra5272_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cobra5272_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="cobra5272" + CONFIG_TARGET_COBRA5272=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +diff -ruN u-boot-2021.10/configs/colibri_imx6_defconfig u-boot/configs/colibri_imx6_defconfig +--- u-boot-2021.10/configs/colibri_imx6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_imx6_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -11,16 +11,19 @@ + CONFIG_ENV_OFFSET=0xFFFFDE00 + CONFIG_MX6DL=y + CONFIG_TARGET_COLIBRI_IMX6=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_CMD_HDMIDETECT=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +@@ -69,6 +72,9 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_MXC_I2C3_SPEED=400000 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/colibri-imx6ull_defconfig u-boot/configs/colibri-imx6ull_defconfig +--- u-boot-2021.10/configs/colibri-imx6ull_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri-imx6ull_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -8,11 +8,11 @@ + CONFIG_ENV_OFFSET=0x380000 + CONFIG_MX6ULL=y + CONFIG_TARGET_COLIBRI_IMX6ULL=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,IMX_NAND" + CONFIG_BOOTDELAY=1 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_USE_PREBOOT=y +@@ -73,6 +73,7 @@ + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_MXS=y + CONFIG_NAND_MXS_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/colibri_imx7_defconfig u-boot/configs/colibri_imx7_defconfig +--- u-boot-2021.10/configs/colibri_imx7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_imx7_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0x8c000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x380000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand" + CONFIG_TARGET_COLIBRI_IMX7=y +@@ -12,7 +13,6 @@ + CONFIG_IMX_BOOTAUX=y + CONFIG_IMX_HAB=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" + CONFIG_BOOTDELAY=1 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_USE_PREBOOT=y +@@ -59,14 +59,15 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_ENV=y +-CONFIG_FSL_CAAM=y + CONFIG_DFU_NAND=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/colibri_imx7_emmc_defconfig u-boot/configs/colibri_imx7_emmc_defconfig +--- u-boot-2021.10/configs/colibri_imx7_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_imx7_emmc_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x8c000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc" + CONFIG_TARGET_COLIBRI_IMX7=y +@@ -14,7 +15,6 @@ + CONFIG_IMX_HAB=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" + CONFIG_BOOTDELAY=1 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_USE_PREBOOT=y +@@ -46,7 +46,6 @@ + # CONFIG_ISO_PARTITION is not set + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y +-CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +@@ -54,7 +53,6 @@ + CONFIG_TFTP_BLOCKSIZE=16352 + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_ENV=y +-CONFIG_FSL_CAAM=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x82000000 + CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +@@ -62,6 +60,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/colibri-imx8x_defconfig u-boot/configs/colibri-imx8x_defconfig +--- u-boot-2021.10/configs/colibri-imx8x_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri-imx8x_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -7,12 +7,13 @@ + CONFIG_SYS_MEMTEST_END=0x89000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" + CONFIG_TARGET_COLIBRI_IMX8X=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" + CONFIG_LOG=y + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_BOARD_EARLY_INIT_F=y +@@ -32,6 +33,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=4096 +diff -ruN u-boot-2021.10/configs/colibri_pxa270_defconfig u-boot/configs/colibri_pxa270_defconfig +--- u-boot-2021.10/configs/colibri_pxa270_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_pxa270_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -7,7 +7,9 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0xa0000000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" + CONFIG_SYS_DEVICE_NULLDEV=y +diff -ruN u-boot-2021.10/configs/colibri_t20_defconfig u-boot/configs/colibri_t20_defconfig +--- u-boot-2021.10/configs/colibri_t20_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_t20_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_COLIBRI_T20=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_STDIO_DEREGISTER=y + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -47,6 +48,7 @@ + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_DM_PMIC=y + CONFIG_DM_REGULATOR=y +diff -ruN u-boot-2021.10/configs/colibri_t30_defconfig u-boot/configs/colibri_t30_defconfig +--- u-boot-2021.10/configs/colibri_t30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_t30_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA30=y + CONFIG_TARGET_COLIBRI_T30=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/colibri_vf_defconfig u-boot/configs/colibri_vf_defconfig +--- u-boot-2021.10/configs/colibri_vf_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colibri_vf_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_VF610=y + CONFIG_SYS_TEXT_BASE=0x3f401000 +@@ -8,11 +9,12 @@ + CONFIG_SYS_MEMTEST_END=0x87c00000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x180000 ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" + CONFIG_TARGET_COLIBRI_VF=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,IMX_NAND" ++CONFIG_SYS_LOAD_ADDR=0x80008000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="setenv fdtfile ${soc}-colibri-${fdt_board}.dtb" +@@ -71,6 +73,7 @@ + CONFIG_NAND_VF610_NFC=y + CONFIG_NAND_VF610_NFC_DT=y + CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/Colombus_defconfig u-boot/configs/Colombus_defconfig +--- u-boot-2021.10/configs/Colombus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Colombus_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,7 +5,6 @@ + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_CLK=240 + CONFIG_DRAM_ZQ=251 +-CONFIG_USB1_VBUS_PIN="" + CONFIG_I2C0_ENABLE=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0" +@@ -13,10 +12,12 @@ + CONFIG_VIDEO_LCD_POWER="PH27" + CONFIG_VIDEO_LCD_BL_EN="PM1" + CONFIG_VIDEO_LCD_BL_PWM="PH13" +-CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" +-CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" + CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +@@ -25,3 +26,4 @@ + CONFIG_AXP_ALDO1_VOLT=3300 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/colorfly_e708_q1_defconfig u-boot/configs/colorfly_e708_q1_defconfig +--- u-boot-2021.10/configs/colorfly_e708_q1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/colorfly_e708_q1_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=251 + CONFIG_MMC0_CD_PIN="PA8" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PA15" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +@@ -19,3 +18,4 @@ + CONFIG_AXP_DLDO1_VOLT=3300 + CONFIG_AXP_DLDO2_VOLT=1800 + CONFIG_USB_MUSB_HOST=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/comtrend_ar5315u_ram_defconfig u-boot/configs/comtrend_ar5315u_ram_defconfig +--- u-boot-2021.10/configs/comtrend_ar5315u_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/comtrend_ar5315u_ram_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6318=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/comtrend_ar5387un_ram_defconfig u-boot/configs/comtrend_ar5387un_ram_defconfig +--- u-boot-2021.10/configs/comtrend_ar5387un_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/comtrend_ar5387un_ram_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6328=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/comtrend_ct5361_ram_defconfig u-boot/configs/comtrend_ct5361_ram_defconfig +--- u-boot-2021.10/configs/comtrend_ct5361_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/comtrend_ct5361_ram_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6348=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/comtrend_vr3032u_ram_defconfig u-boot/configs/comtrend_vr3032u_ram_defconfig +--- u-boot-2021.10/configs/comtrend_vr3032u_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/comtrend_vr3032u_ram_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM63268=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +@@ -45,6 +49,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_BRCMNAND=y + CONFIG_NAND_BRCMNAND_6368=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_ETH=y + CONFIG_BCM6368_ETH=y + CONFIG_PHY=y +diff -ruN u-boot-2021.10/configs/comtrend_wap5813n_ram_defconfig u-boot/configs/comtrend_wap5813n_ram_defconfig +--- u-boot-2021.10/configs/comtrend_wap5813n_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/comtrend_wap5813n_ram_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6368=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/controlcenterdc_defconfig u-boot/configs/controlcenterdc_defconfig +--- u-boot-2021.10/configs/controlcenterdc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/controlcenterdc_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y + CONFIG_SYS_TEXT_BASE=0x00800000 +@@ -12,13 +14,14 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + CONFIG_OF_BOARD_FIXUP=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/cortina_presidio-asic-base_defconfig u-boot/configs/cortina_presidio-asic-base_defconfig +--- u-boot-2021.10/configs/cortina_presidio-asic-base_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cortina_presidio-asic-base_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_TEXT_BASE=0x04000000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x820000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" + CONFIG_IDENT_STRING="Presidio-SoC" ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_SHOW_BOOT_PROGRESS=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/cortina_presidio-asic-emmc_defconfig u-boot/configs/cortina_presidio-asic-emmc_defconfig +--- u-boot-2021.10/configs/cortina_presidio-asic-emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cortina_presidio-asic-emmc_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_TEXT_BASE=0x04000000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x820000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" + CONFIG_IDENT_STRING="Presidio-SoC" ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_SHOW_BOOT_PROGRESS=y + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_R=y +diff -ruN u-boot-2021.10/configs/cortina_presidio-asic-pnand_defconfig u-boot/configs/cortina_presidio-asic-pnand_defconfig +--- u-boot-2021.10/configs/cortina_presidio-asic-pnand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cortina_presidio-asic-pnand_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_TEXT_BASE=0x04000000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x820000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" + CONFIG_IDENT_STRING="Presidio-SoC" ++CONFIG_SYS_LOAD_ADDR=0x10000000 + CONFIG_SHOW_BOOT_PROGRESS=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -27,6 +29,7 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_CORTINA_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SERIAL=y + CONFIG_CORTINA_UART=y + CONFIG_WDT=y +diff -ruN u-boot-2021.10/configs/corvus_defconfig u-boot/configs/corvus_defconfig +--- u-boot-2021.10/configs/corvus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/corvus_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SYS_THUMB_BUILD=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set +@@ -11,12 +13,14 @@ + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x460000 + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x180000 +-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" ++CONFIG_SYS_LOAD_ADDR=0x70000000 ++CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" +@@ -57,6 +61,12 @@ + CONFIG_MTD_RAW_NAND=y + # CONFIG_SYS_NAND_USE_FLASH_BBT is not set + CONFIG_NAND_ATMEL=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_PHYLIB=y + CONFIG_ATMEL_USART=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/crs305-1g-4s-bit_defconfig u-boot/configs/crs305-1g-4s-bit_defconfig +--- u-boot-2021.10/configs/crs305-1g-4s-bit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs305-1g-4s-bit_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s-bit" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/crs305-1g-4s_defconfig u-boot/configs/crs305-1g-4s_defconfig +--- u-boot-2021.10/configs/crs305-1g-4s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs305-1g-4s_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/crs326-24g-2s-bit_defconfig u-boot/configs/crs326-24g-2s-bit_defconfig +--- u-boot-2021.10/configs/crs326-24g-2s-bit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs326-24g-2s-bit_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s-bit" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/crs326-24g-2s_defconfig u-boot/configs/crs326-24g-2s_defconfig +--- u-boot-2021.10/configs/crs326-24g-2s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs326-24g-2s_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs326-24g-2s" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/crs328-4c-20s-4s-bit_defconfig u-boot/configs/crs328-4c-20s-4s-bit_defconfig +--- u-boot-2021.10/configs/crs328-4c-20s-4s-bit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs328-4c-20s-4s-bit_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s-bit" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/crs328-4c-20s-4s_defconfig u-boot/configs/crs328-4c-20s-4s_defconfig +--- u-boot-2021.10/configs/crs328-4c-20s-4s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/crs328-4c-20s-4s_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs328-4c-20s-4s" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +diff -ruN u-boot-2021.10/configs/CSQ_CS908_defconfig u-boot/configs/CSQ_CS908_defconfig +--- u-boot-2021.10/configs/CSQ_CS908_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/CSQ_CS908_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,8 +4,6 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_CLK=432 +-CONFIG_USB1_VBUS_PIN="" +-CONFIG_USB2_VBUS_PIN="" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +@@ -16,3 +14,4 @@ + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_MUSB_HOST=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Cubieboard2_defconfig u-boot/configs/Cubieboard2_defconfig +--- u-boot-2021.10/configs/Cubieboard2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Cubieboard2_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,6 +10,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -17,3 +20,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Cubieboard4_defconfig u-boot/configs/Cubieboard4_defconfig +--- u-boot-2021.10/configs/Cubieboard4_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Cubieboard4_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,10 +6,8 @@ + CONFIG_DRAM_CLK=672 + CONFIG_MMC0_CD_PIN="PH18" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH16" +-CONFIG_USB1_VBUS_PIN="PH14" +-CONFIG_USB3_VBUS_PIN="PH15" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + CONFIG_AXP809_POWER=y +diff -ruN u-boot-2021.10/configs/cubieboard7_defconfig u-boot/configs/cubieboard7_defconfig +--- u-boot-2021.10/configs/cubieboard7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/cubieboard7_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y + CONFIG_ARCH_OWL=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7" + CONFIG_MACH_S700=y + CONFIG_IDENT_STRING="\ncubieboard7" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x7ffc0 + CONFIG_BOOTDELAY=5 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyOWL3,115200n8" +diff -ruN u-boot-2021.10/configs/Cubieboard_defconfig u-boot/configs/Cubieboard_defconfig +--- u-boot-2021.10/configs/Cubieboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Cubieboard_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,8 +10,12 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Cubietruck_defconfig u-boot/configs/Cubietruck_defconfig +--- u-boot-2021.10/configs/Cubietruck_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Cubietruck_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PH17" +-CONFIG_USB0_VBUS_DET="PH22" +-CONFIG_USB0_ID_DET="PH19" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_VGA=y + CONFIG_SATAPWR="PH12" + CONFIG_GMAC_TX_DELAY=1 +@@ -19,6 +17,9 @@ + CONFIG_SCSI_AHCI=y + CONFIG_DFU_RAM=y + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +diff -ruN u-boot-2021.10/configs/Cubietruck_plus_defconfig u-boot/configs/Cubietruck_plus_defconfig +--- u-boot-2021.10/configs/Cubietruck_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Cubietruck_plus_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -7,15 +7,18 @@ + CONFIG_DRAM_ZQ=15355 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH11" +-CONFIG_USB1_VBUS_PIN="PD29" +-CONFIG_USB2_VBUS_PIN="PL6" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_I2C0_ENABLE=y + CONFIG_AXP_GPIO=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_SUN8I_EMAC=y + CONFIG_AXP_DLDO3_VOLT=2500 +diff -ruN u-boot-2021.10/configs/d2net_v2_defconfig u-boot/configs/d2net_v2_defconfig +--- u-boot-2021.10/configs/d2net_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/d2net_v2_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net" + CONFIG_IDENT_STRING=" D2 v2" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="d2v2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/da850evm_defconfig u-boot/configs/da850evm_defconfig +--- u-boot-2021.10/configs/da850evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/da850evm_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_DAVINCI=y + CONFIG_SYS_TEXT_BASE=0xc1080000 +@@ -11,14 +13,16 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x80000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x110000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="da850-evm" + CONFIG_SPL_TEXT_BASE=0x80000000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0xc0700000 + CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" +diff -ruN u-boot-2021.10/configs/da850evm_direct_nor_defconfig u-boot/configs/da850evm_direct_nor_defconfig +--- u-boot-2021.10/configs/da850evm_direct_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/da850evm_direct_nor_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_DAVINCI=y + CONFIG_SYS_TEXT_BASE=0x60000000 +@@ -9,9 +10,11 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2800 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x110000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="da850-evm" + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0xc0700000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" +diff -ruN u-boot-2021.10/configs/da850evm_nand_defconfig u-boot/configs/da850evm_nand_defconfig +--- u-boot-2021.10/configs/da850evm_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/da850evm_nand_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_DAVINCI=y + CONFIG_SYS_TEXT_BASE=0xc1080000 +@@ -9,14 +11,16 @@ + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x110000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="da850-evm" + CONFIG_SPL_TEXT_BASE=0x80000000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0xc0700000 + CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" +@@ -64,6 +68,10 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_DAVINCI=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/dalmore_defconfig u-boot/configs/dalmore_defconfig +--- u-boot-2021.10/configs/dalmore_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dalmore_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -4,10 +4,12 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA114=y + CONFIG_TARGET_DALMORE=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/db-88f6720_defconfig u-boot/configs/db-88f6720_defconfig +--- u-boot-2021.10/configs/db-88f6720_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/db-88f6720_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y + CONFIG_SYS_TEXT_BASE=0x00800000 +@@ -12,12 +13,13 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" + CONFIG_SPL_TEXT_BASE=0x40004030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xf1012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -45,6 +47,10 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_SPL_OF_TRANSLATE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + CONFIG_MISC=y + # CONFIG_MMC is not set + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/db-88f6820-amc_defconfig u-boot/configs/db-88f6820-amc_defconfig +--- u-boot-2021.10/configs/db-88f6820-amc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/db-88f6820-amc_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y + CONFIG_SYS_TEXT_BASE=0x00800000 +@@ -12,11 +13,12 @@ + CONFIG_ENV_SECT_SIZE=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=3 +@@ -57,6 +59,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_PXA3XX=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_SPI_FLASH_BAR=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/db-88f6820-gp_defconfig u-boot/configs/db-88f6820-gp_defconfig +--- u-boot-2021.10/configs/db-88f6820-gp_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/db-88f6820-gp_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y + CONFIG_SYS_TEXT_BASE=0x00800000 +@@ -12,12 +13,13 @@ + CONFIG_ENV_SECT_SIZE=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -48,6 +50,10 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_OF_TRANSLATE=y + CONFIG_AHCI_MVEBU=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_MV=y +diff -ruN u-boot-2021.10/configs/db-mv784mp-gp_defconfig u-boot/configs/db-mv784mp-gp_defconfig +--- u-boot-2021.10/configs/db-mv784mp-gp_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/db-mv784mp-gp_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -12,12 +12,13 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" + CONFIG_SPL_TEXT_BASE=0x40004030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -49,11 +50,16 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_OF_TRANSLATE=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_PXA3XX=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_PHY_MARVELL=y +diff -ruN u-boot-2021.10/configs/db-xc3-24g4xg_defconfig u-boot/configs/db-xc3-24g4xg_defconfig +--- u-boot-2021.10/configs/db-xc3-24g4xg_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/db-xc3-24g4xg_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -11,6 +11,7 @@ + CONFIG_ENV_SECT_SIZE=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg" + CONFIG_BUILD_TARGET="u-boot.kwb" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_BEST_MATCH=y +@@ -44,6 +45,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_PXA3XX=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SPI_FLASH_SFDP_SUPPORT=y + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPI_FLASH_STMICRO=y +diff -ruN u-boot-2021.10/configs/deneb_defconfig u-boot/configs/deneb_defconfig +--- u-boot-2021.10/configs/deneb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/deneb_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -8,20 +8,21 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" + CONFIG_SPL_TEXT_BASE=0x100000 + CONFIG_TARGET_DENEB=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x2000 + CONFIG_SPL_LOAD_IMX_CONTAINER=y + CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -32,7 +33,6 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SYS_MALLOC_SIMPLE=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/devkit3250_defconfig u-boot/configs/devkit3250_defconfig +--- u-boot-2021.10/configs/devkit3250_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/devkit3250_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y +@@ -9,9 +10,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xA0000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_SPL_TEXT_BASE=0x00000000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x80008000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +@@ -37,6 +40,9 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_VERSION_VARIABLE=y ++CONFIG_DMA_LPC32XX=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_LPC32XX=y + # CONFIG_MMC is not set + CONFIG_MTD=y +@@ -47,6 +53,13 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_LPC32XX_SLC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_PHYLIB=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_ADDR=31 +diff -ruN u-boot-2021.10/configs/devkit8000_defconfig u-boot/configs/devkit8000_defconfig +--- u-boot-2021.10/configs/devkit8000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/devkit8000_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_SYS_TEXT_BASE=0x80100000 + CONFIG_NR_DRAM_BANKS=2 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_SPL_TEXT_BASE=0x40200000 + CONFIG_TARGET_DEVKIT8000=y + CONFIG_SPL=y +@@ -34,10 +35,19 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_TWL4030_LED=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_CONS_INDEX=3 + CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/dh_imx6_defconfig u-boot/configs/dh_imx6_defconfig +--- u-boot-2021.10/configs/dh_imx6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dh_imx6_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -17,22 +17,21 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 + CONFIG_SPL=y + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_ENV_OFFSET_REDUND=0x110000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +diff -ruN u-boot-2021.10/configs/difrnce_dit4350_defconfig u-boot/configs/difrnce_dit4350_defconfig +--- u-boot-2021.10/configs/difrnce_dit4350_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/difrnce_dit4350_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=408 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0" +@@ -16,5 +14,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/display5_defconfig u-boot/configs/display5_defconfig +--- u-boot-2021.10/configs/display5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/display5_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -15,10 +15,11 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 + CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +@@ -26,13 +27,12 @@ + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_ENV_OFFSET_REDUND=0x130000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_MISC_INIT_R=y + CONFIG_SPL_BOOTCOUNT_LIMIT=y + # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +@@ -52,6 +52,10 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CRC32_VERIFY=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_BUS=2 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_SIZE=32768 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -82,16 +86,13 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_BOOTCOUNT_LIMIT=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 + CONFIG_SYS_I2C_MXC=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_I2C_EEPROM_BUS=2 +-CONFIG_SYS_EEPROM_SIZE=32768 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/display5_factory_defconfig u-boot/configs/display5_factory_defconfig +--- u-boot-2021.10/configs/display5_factory_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/display5_factory_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -15,21 +15,21 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x130000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTCOMMAND=y + CONFIG_BOOTCOMMAND="echo SDP Display5 recovery" +@@ -52,6 +52,10 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CRC32_VERIFY=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_BUS=2 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_SIZE=32768 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -86,16 +90,13 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y + CONFIG_DFU_SF=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 + CONFIG_SYS_I2C_MXC=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_I2C_EEPROM_BUS=2 +-CONFIG_SYS_EEPROM_SIZE=32768 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/dns325_defconfig u-boot/configs/dns325_defconfig +--- u-boot-2021.10/configs/dns325_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dns325_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325" + CONFIG_IDENT_STRING="\nD-Link DNS-325" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/dockstar_defconfig u-boot/configs/dockstar_defconfig +--- u-boot-2021.10/configs/dockstar_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dockstar_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar" + CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/dra7xx_evm_defconfig u-boot/configs/dra7xx_evm_defconfig +--- u-boot-2021.10/configs/dra7xx_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dra7xx_evm_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -12,7 +12,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -40,6 +40,7 @@ + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_DFU=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + # CONFIG_CMD_SETEXPR is not set +@@ -82,6 +83,7 @@ + CONFIG_PCF8575_GPIO=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +@@ -90,7 +92,14 @@ + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=76800000 +@@ -122,6 +131,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_GENERIC=y +diff -ruN u-boot-2021.10/configs/dra7xx_hs_evm_defconfig u-boot/configs/dra7xx_hs_evm_defconfig +--- u-boot-2021.10/configs/dra7xx_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dra7xx_hs_evm_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -15,7 +15,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -44,6 +44,7 @@ + CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_DFU=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_NAND=y + CONFIG_BOOTP_DNS2=y +@@ -85,6 +86,7 @@ + CONFIG_PCF8575_GPIO=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +@@ -93,7 +95,12 @@ + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=76800000 +@@ -125,6 +132,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_GENERIC=y +diff -ruN u-boot-2021.10/configs/dra7xx_hs_evm_usb_defconfig u-boot/configs/dra7xx_hs_evm_usb_defconfig +--- u-boot-2021.10/configs/dra7xx_hs_evm_usb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dra7xx_hs_evm_usb_defconfig 2021-11-01 17:10:14.172930741 +0100 +@@ -17,7 +17,7 @@ + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x280000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +@@ -44,6 +44,7 @@ + CONFIG_SPL_USB_GADGET=y + CONFIG_SPL_DFU=y + CONFIG_SPL_YMODEM_SUPPORT=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set + CONFIG_BOOTP_DNS2=y +@@ -81,6 +82,7 @@ + CONFIG_PCF8575_GPIO=y + CONFIG_DM_I2C=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +@@ -119,6 +121,7 @@ + CONFIG_SPL_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_XHCI_OMAP=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_GADGET=y +diff -ruN u-boot-2021.10/configs/draco_defconfig u-boot/configs/draco_defconfig +--- u-boot-2021.10/configs/draco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/draco_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -7,21 +7,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=300 + CONFIG_TARGET_DRACO=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x2E0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -76,10 +78,19 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/dragonboard410c_defconfig u-boot/configs/dragonboard410c_defconfig +--- u-boot-2021.10/configs/dragonboard410c_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dragonboard410c_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,9 +4,11 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x802000 + CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" + CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y +diff -ruN u-boot-2021.10/configs/dragonboard820c_defconfig u-boot/configs/dragonboard820c_defconfig +--- u-boot-2021.10/configs/dragonboard820c_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dragonboard820c_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -3,10 +3,12 @@ + CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x804000 + CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c" + CONFIG_TARGET_DRAGONBOARD820C=y + CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyMSM0,115200n8" + # CONFIG_USE_BOOTCOMMAND is not set +diff -ruN u-boot-2021.10/configs/dreamplug_defconfig u-boot/configs/dreamplug_defconfig +--- u-boot-2021.10/configs/dreamplug_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dreamplug_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug" + CONFIG_IDENT_STRING="\nMarvell-DreamPlug" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/ds109_defconfig u-boot/configs/ds109_defconfig +--- u-boot-2021.10/configs/ds109_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ds109_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,7 +1,13 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y ++CONFIG_SUPPORT_PASSING_ATAGS=y ++CONFIG_CMDLINE_TAG=y ++CONFIG_INITRD_TAG=y ++CONFIG_STATIC_MACH_TYPE=y ++CONFIG_MACH_TYPE=527 + CONFIG_SYS_TEXT_BASE=0x600000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_TARGET_DS109=y +@@ -10,6 +16,7 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_HUSH_PARSER=y + # CONFIG_CMD_FLASH is not set +diff -ruN u-boot-2021.10/configs/ds414_defconfig u-boot/configs/ds414_defconfig +--- u-boot-2021.10/configs/ds414_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ds414_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,22 +1,29 @@ + CONFIG_ARM=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y ++CONFIG_SUPPORT_PASSING_ATAGS=y ++CONFIG_CMDLINE_TAG=y ++CONFIG_INITRD_TAG=y ++CONFIG_STATIC_MACH_TYPE=y ++CONFIG_MACH_TYPE=3036 + CONFIG_SYS_TEXT_BASE=0x00800000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_TARGET_DS414=y ++CONFIG_DDR_32BIT=y + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x7E0000 + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" + CONFIG_SPL_TEXT_BASE=0x40004030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1" +@@ -46,6 +53,10 @@ + CONFIG_ENV_SPI_MAX_HZ=50000000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_OF_TRANSLATE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_SPI_FLASH_STMICRO=y +diff -ruN u-boot-2021.10/configs/dserve_dsrv9703c_defconfig u-boot/configs/dserve_dsrv9703c_defconfig +--- u-boot-2021.10/configs/dserve_dsrv9703c_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/dserve_dsrv9703c_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,9 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 + CONFIG_VIDEO_LCD_POWER="PH8" +@@ -15,4 +13,7 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/durian_defconfig u-boot/configs/durian_defconfig +--- u-boot-2021.10/configs/durian_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/durian_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_TEXT_BASE=0x500000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x101000 + CONFIG_DEFAULT_DEVICE_TREE="phytium-durian" + # CONFIG_PSCI_RESET is not set + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x90000000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/ea-lpc3250devkitv2_defconfig u-boot/configs/ea-lpc3250devkitv2_defconfig +--- u-boot-2021.10/configs/ea-lpc3250devkitv2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ea-lpc3250devkitv2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y +@@ -8,6 +9,7 @@ + CONFIG_TARGET_EA_LPC3250DEVKITV2=y + CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80100000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + # CONFIG_AUTOBOOT is not set + # CONFIG_USE_BOOTCOMMAND is not set +diff -ruN u-boot-2021.10/configs/eb_cpu5282_defconfig u-boot/configs/eb_cpu5282_defconfig +--- u-boot-2021.10/configs/eb_cpu5282_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/eb_cpu5282_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,6 +4,7 @@ + CONFIG_ENV_SECT_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282" + CONFIG_TARGET_EB_CPU5282=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -18,6 +19,10 @@ + CONFIG_CMD_MII=y + CONFIG_CMD_DATE=y + CONFIG_ENV_ADDR=0xFF040000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x300 ++CONFIG_SYS_I2C_SLAVE=0 + CONFIG_LED_STATUS=y + CONFIG_LED_STATUS0=y + CONFIG_LED_STATUS_BIT=8 +diff -ruN u-boot-2021.10/configs/eb_cpu5282_internal_defconfig u-boot/configs/eb_cpu5282_internal_defconfig +--- u-boot-2021.10/configs/eb_cpu5282_internal_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/eb_cpu5282_internal_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,6 +4,7 @@ + CONFIG_ENV_SECT_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal" + CONFIG_TARGET_EB_CPU5282=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -17,6 +18,10 @@ + CONFIG_CMD_MII=y + CONFIG_CMD_DATE=y + CONFIG_ENV_ADDR=0xFF040000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x300 ++CONFIG_SYS_I2C_SLAVE=0 + CONFIG_LED_STATUS=y + CONFIG_LED_STATUS0=y + CONFIG_LED_STATUS_BIT=8 +diff -ruN u-boot-2021.10/configs/edison_defconfig u-boot/configs/edison_defconfig +--- u-boot-2021.10/configs/edison_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/edison_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -3,12 +3,14 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_MALLOC_LEN=0x8000000 + CONFIG_DEFAULT_DEVICE_TREE="edison" + CONFIG_ENV_OFFSET_REDUND=0x600000 + CONFIG_VENDOR_INTEL=y + CONFIG_TARGET_EDISON=y + CONFIG_SMP=y + CONFIG_GENERATE_ACPI_TABLE=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_LAST_STAGE_INIT=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/edminiv2_defconfig u-boot/configs/edminiv2_defconfig +--- u-boot-2021.10/configs/edminiv2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/edminiv2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -8,11 +8,13 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_SPL_TEXT_BASE=0xffff0000 + CONFIG_TARGET_EDMINIV2=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_IDENT_STRING=" EDMiniV2" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_ARCH_MISC_INIT=y +@@ -31,6 +33,10 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xFFF84000 + CONFIG_NETCONSOLE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + # CONFIG_MMC is not set + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/elgin-rv1108_defconfig u-boot/configs/elgin-rv1108_defconfig +--- u-boot-2021.10/configs/elgin-rv1108_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/elgin-rv1108_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x60000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -10,6 +11,7 @@ + CONFIG_DEBUG_UART_BASE=0x10210000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x62000000 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/Empire_electronix_d709_defconfig u-boot/configs/Empire_electronix_d709_defconfig +--- u-boot-2021.10/configs/Empire_electronix_d709_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Empire_electronix_d709_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,9 +6,7 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_EMR1=0 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +@@ -17,5 +15,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/Empire_electronix_m712_defconfig u-boot/configs/Empire_electronix_m712_defconfig +--- u-boot-2021.10/configs/Empire_electronix_m712_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Empire_electronix_m712_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=408 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +@@ -16,5 +14,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/emsdp_defconfig u-boot/configs/emsdp_defconfig +--- u-boot-2021.10/configs/emsdp_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/emsdp_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,8 +4,10 @@ + CONFIG_TARGET_EMSDP=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="emsdp" + CONFIG_SYS_CLK_FREQ=40000000 ++CONFIG_SYS_LOAD_ADDR=0x10000000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/espresso7420_defconfig u-boot/configs/espresso7420_defconfig +--- u-boot-2021.10/configs/espresso7420_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/espresso7420_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,8 +6,10 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" + CONFIG_IDENT_STRING=" for ESPRESSO7420" ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + # CONFIG_AUTOBOOT is not set + CONFIG_SILENT_CONSOLE=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/etamin_defconfig u-boot/configs/etamin_defconfig +--- u-boot-2021.10/configs/etamin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/etamin_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -8,21 +8,23 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x980000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=300 + CONFIG_TARGET_ETAMIN=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0xB80000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -77,10 +79,20 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x80 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/ethernut5_defconfig u-boot/configs/ethernut5_defconfig +--- u-boot-2021.10/configs/ethernut5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ethernut5_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x27000000 +@@ -8,8 +9,10 @@ + CONFIG_ENV_SIZE=0x21000 + CONFIG_ENV_OFFSET=0x3DE000 + CONFIG_ENV_SECT_SIZE=0x21000 ++CONFIG_SYS_MALLOC_LEN=0x121000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ethernut5" ++CONFIG_SYS_LOAD_ADDR=0x020000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -55,6 +58,9 @@ + CONFIG_CLK=y + CONFIG_CLK_AT91=y + CONFIG_AT91_GPIO=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0 + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/evb-ast2500_defconfig u-boot/configs/evb-ast2500_defconfig +--- u-boot-2021.10/configs/evb-ast2500_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-ast2500_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,8 +6,10 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb" + CONFIG_PRE_CON_BUF_ADDR=0x1e720000 ++CONFIG_SYS_LOAD_ADDR=0x83000000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw" + CONFIG_USE_BOOTCOMMAND=y +diff -ruN u-boot-2021.10/configs/evb-ast2600_defconfig u-boot/configs/evb-ast2600_defconfig +--- u-boot-2021.10/configs/evb-ast2600_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-ast2600_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -9,12 +9,14 @@ + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SIZE_LIMIT=0x10000 + CONFIG_SPL=y + # CONFIG_ARMV7_NONSEC is not set + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x83000000 + CONFIG_FIT=y + # CONFIG_LEGACY_IMAGE_FORMAT is not set + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/evb-px30_defconfig u-boot/configs/evb-px30_defconfig +--- u-boot-2021.10/configs/evb-px30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-px30_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -16,6 +17,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/evb-px5_defconfig u-boot/configs/evb-px5_defconfig +--- u-boot-2021.10/configs/evb-px5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-px5_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -15,8 +16,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF1c0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/evb-rk3036_defconfig u-boot/configs/evb-rk3036_defconfig +--- u-boot-2021.10/configs/evb-rk3036_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3036_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_ROCKCHIP=y +@@ -13,6 +15,7 @@ + CONFIG_DEBUG_UART_BASE=0x20068000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x60800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" +diff -ruN u-boot-2021.10/configs/evb-rk3128_defconfig u-boot/configs/evb-rk3128_defconfig +--- u-boot-2021.10/configs/evb-rk3128_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3128_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x60000000 + CONFIG_NR_DRAM_BANKS=2 +@@ -8,6 +9,7 @@ + CONFIG_DEBUG_UART_BASE=0x20068000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x60800800 + CONFIG_FIT=y + CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/evb-rk3229_defconfig u-boot/configs/evb-rk3229_defconfig +--- u-boot-2021.10/configs/evb-rk3229_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3229_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,7 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x61000000 + CONFIG_NR_DRAM_BANKS=2 +@@ -13,6 +16,7 @@ + CONFIG_DEBUG_UART_BASE=0x11030000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x61800800 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_LOAD_FIT=y +@@ -24,7 +28,7 @@ + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +-CONFIG_SPL_OPTEE=y ++CONFIG_SPL_OPTEE_IMAGE=y + CONFIG_CMD_GPT=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB_MASS_STORAGE=y +diff -ruN u-boot-2021.10/configs/evb-rk3288_defconfig u-boot/configs/evb-rk3288_defconfig +--- u-boot-2021.10/configs/evb-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3288_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x01000000 + CONFIG_NR_DRAM_BANKS=2 +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -22,7 +25,7 @@ + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +-CONFIG_SPL_OPTEE=y ++CONFIG_SPL_OPTEE_IMAGE=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +diff -ruN u-boot-2021.10/configs/evb-rk3308_defconfig u-boot/configs/evb-rk3308_defconfig +--- u-boot-2021.10/configs/evb-rk3308_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3308_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00600000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -13,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF0C0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/evb-rk3328_defconfig u-boot/configs/evb-rk3328_defconfig +--- u-boot-2021.10/configs/evb-rk3328_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3328_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -15,6 +16,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/evb-rk3399_defconfig u-boot/configs/evb-rk3399_defconfig +--- u-boot-2021.10/configs/evb-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3399_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/evb-rk3568_defconfig u-boot/configs/evb-rk3568_defconfig +--- u-boot-2021.10/configs/evb-rk3568_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rk3568_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00a00000 + CONFIG_NR_DRAM_BANKS=2 +@@ -8,6 +9,7 @@ + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/evb-rv1108_defconfig u-boot/configs/evb-rv1108_defconfig +--- u-boot-2021.10/configs/evb-rv1108_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/evb-rv1108_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x60000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -7,6 +8,7 @@ + CONFIG_DEBUG_UART_BASE=0x10210000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x62000000 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/ev-imx280-nano-x-mb_defconfig u-boot/configs/ev-imx280-nano-x-mb_defconfig +--- u-boot-2021.10/configs/ev-imx280-nano-x-mb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ev-imx280-nano-x-mb_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -3,6 +3,7 @@ + CONFIG_SYS_TEXT_BASE=0x87800000 + CONFIG_MX6ULL=y + CONFIG_TARGET_O4_IMX6ULL_NANO=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_EV_IMX280_NANO_X_MB=y + CONFIG_IMX_MODULE_FUSE=y +diff -ruN u-boot-2021.10/configs/ficus-rk3399_defconfig u-boot/configs/ficus-rk3399_defconfig +--- u-boot-2021.10/configs/ficus-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ficus-rk3399_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ENV_OFFSET=0x3F8000 +@@ -10,6 +11,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set + CONFIG_SPL_STACK_R=y +diff -ruN u-boot-2021.10/configs/firefly-px30_defconfig u-boot/configs/firefly-px30_defconfig +--- u-boot-2021.10/configs/firefly-px30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/firefly-px30_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -17,6 +18,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/firefly-rk3288_defconfig u-boot/configs/firefly-rk3288_defconfig +--- u-boot-2021.10/configs/firefly-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/firefly-rk3288_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x01000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" +diff -ruN u-boot-2021.10/configs/firefly-rk3399_defconfig u-boot/configs/firefly-rk3399_defconfig +--- u-boot-2021.10/configs/firefly-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/firefly-rk3399_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/flea3_defconfig u-boot/configs/flea3_defconfig +--- u-boot-2021.10/configs/flea3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/flea3_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,50 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_SYS_DCACHE_OFF=y +-CONFIG_TARGET_FLEA3=y +-CONFIG_SYS_TEXT_BASE=0xA0000000 +-CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x10000 +-CONFIG_ENV_SECT_SIZE=0x10000 +-CONFIG_FIT=y +-CONFIG_OF_BOARD_SETUP=y +-CONFIG_BOOTDELAY=3 +-# CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_BOARD_EARLY_INIT_F=y +-CONFIG_HUSH_PARSER=y +-CONFIG_SYS_PROMPT="flea3 U-Boot > " +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_I2C=y +-CONFIG_CMD_SPI=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_DHCP=y +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_CACHE=y +-CONFIG_CMD_MTDPARTS=y +-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" +-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" +-CONFIG_ENV_OVERWRITE=y +-CONFIG_ENV_IS_IN_FLASH=y +-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +-CONFIG_ENV_ADDR=0xA0080000 +-CONFIG_ENV_ADDR_REDUND=0xA0090000 +-CONFIG_MXC_GPIO=y +-# CONFIG_MMC is not set +-CONFIG_MTD=y +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +-CONFIG_FLASH_CFI_MTD=y +-CONFIG_SYS_FLASH_PROTECTION=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_MTD_RAW_NAND=y +-CONFIG_NAND_MXC=y +-CONFIG_PHYLIB=y +-CONFIG_PHY_MICREL=y +-CONFIG_PHY_MICREL_KSZ8XXX=y +-CONFIG_MII=y +-CONFIG_MXC_UART=y +-CONFIG_SPI=y +-CONFIG_MXC_SPI=y +-CONFIG_OF_LIBFDT=y +-CONFIG_FDT_FIXUP_PARTITIONS=y +diff -ruN u-boot-2021.10/configs/ga10h_v1_1_defconfig u-boot/configs/ga10h_v1_1_defconfig +--- u-boot-2021.10/configs/ga10h_v1_1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ga10h_v1_1_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=15291 + CONFIG_DRAM_ODT_EN=y +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/gardena-smart-gateway-at91sam_defconfig u-boot/configs/gardena-smart-gateway-at91sam_defconfig +--- u-boot-2021.10/configs/gardena-smart-gateway-at91sam_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gardena-smart-gateway-at91sam_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x22900000 +@@ -8,20 +10,25 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MEMTEST_START=0x0 + CONFIG_ENV_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=0 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_STOP_STR="x" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -32,20 +39,26 @@ + CONFIG_SPL_NAND_DRIVERS=y + CONFIG_SPL_NAND_BASE=y + CONFIG_HUSH_PARSER=y ++CONFIG_CMD_LICENSE=y + CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MEMTEST=y ++CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_MTD=y + CONFIG_CMD_NAND=y + CONFIG_CMD_WDT=y +-# CONFIG_CMD_SETEXPR is not set + CONFIG_CMD_DHCP=y + CONFIG_CMD_PING=y + CONFIG_CMD_CACHE=y + CONFIG_CMD_TIME=y ++CONFIG_CMD_GETTIME=y ++CONFIG_CMD_UUID=y + CONFIG_CMD_FAT=y + CONFIG_CMD_MTDPARTS=y ++CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y + CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" + CONFIG_MTDPARTS_DEFAULT="atmel_nand:1536k(uboot),10752k(unused),-(ubi)" + CONFIG_CMD_UBI=y +@@ -58,6 +71,8 @@ + CONFIG_ENV_UBI_VOLUME="uboot_env0" + CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SPL_DM=y +@@ -71,6 +86,13 @@ + CONFIG_MTD=y + CONFIG_NAND_ATMEL=y + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_ETH=y + CONFIG_MACB=y + CONFIG_PINCTRL=y +@@ -84,3 +106,4 @@ + CONFIG_WDT=y + CONFIG_WDT_AT91=y + # CONFIG_UBIFS_SILENCE_MSG is not set ++CONFIG_LZMA=y +diff -ruN u-boot-2021.10/configs/gardena-smart-gateway-mt7688_defconfig u-boot/configs/gardena-smart-gateway-mt7688_defconfig +--- u-boot-2021.10/configs/gardena-smart-gateway-mt7688_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gardena-smart-gateway-mt7688_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 +@@ -6,8 +7,9 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0xA0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c + CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000 + CONFIG_SPL=y +@@ -15,10 +17,13 @@ + CONFIG_ENV_OFFSET_REDUND=0xB0000 + CONFIG_ARCH_MTMIPS=y + CONFIG_SOC_MT7628=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_LEGACY_IMAGE_FORMAT=y +diff -ruN u-boot-2021.10/configs/gazerbeam_defconfig u-boot/configs/gazerbeam_defconfig +--- u-boot-2021.10/configs/gazerbeam_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gazerbeam_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0x07e00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" + CONFIG_IDENT_STRING=" gazerbeam 0.01" +diff -ruN u-boot-2021.10/configs/ge_b1x5v2_defconfig u-boot/configs/ge_b1x5v2_defconfig +--- u-boot-2021.10/configs/ge_b1x5v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ge_b1x5v2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -12,22 +12,22 @@ + # CONFIG_GE_RTC is not set + CONFIG_MX6QDL=y + CONFIG_TARGET_GE_B1X5V2=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=10 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0x21ec000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DEBUG_UART=y + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=1 + CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb" + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +diff -ruN u-boot-2021.10/configs/ge_bx50v3_defconfig u-boot/configs/ge_bx50v3_defconfig +--- u-boot-2021.10/configs/ge_bx50v3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ge_bx50v3_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_MX6Q=y + CONFIG_TARGET_GE_BX50V3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" + CONFIG_BOOTCOUNT_BOOTLIMIT=10 +diff -ruN u-boot-2021.10/configs/geekbox_defconfig u-boot/configs/geekbox_defconfig +--- u-boot-2021.10/configs/geekbox_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/geekbox_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SYS_MALLOC_F_LEN=0x1000 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb" + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/giedi_defconfig u-boot/configs/giedi_defconfig +--- u-boot-2021.10/configs/giedi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/giedi_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -8,20 +8,21 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" + CONFIG_SPL_TEXT_BASE=0x100000 + CONFIG_TARGET_GIEDI=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x2000 + CONFIG_SPL_LOAD_IMX_CONTAINER=y + CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -32,7 +33,6 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SYS_MALLOC_SIMPLE=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/goflexhome_defconfig u-boot/configs/goflexhome_defconfig +--- u-boot-2021.10/configs/goflexhome_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/goflexhome_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet" + CONFIG_IDENT_STRING="\nSeagate GoFlex Home" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/gose_defconfig u-boot/configs/gose_defconfig +--- u-boot-2021.10/configs/gose_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gose_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Gose" + CONFIG_R8A7793=y + CONFIG_TARGET_GOSE=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/grpeach_defconfig u-boot/configs/grpeach_defconfig +--- u-boot-2021.10/configs/grpeach_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/grpeach_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,9 +6,11 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x80000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot" + CONFIG_RZA1=y ++CONFIG_SYS_LOAD_ADDR=0x20400000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="ignore_loglevel" +diff -ruN u-boot-2021.10/configs/gt90h_v4_defconfig u-boot/configs/gt90h_v4_defconfig +--- u-boot-2021.10/configs/gt90h_v4_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gt90h_v4_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=480 + CONFIG_DRAM_ZQ=32767 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/gurnard_defconfig u-boot/configs/gurnard_defconfig +--- u-boot-2021.10/configs/gurnard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gurnard_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,11 +1,14 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x73f00000 + CONFIG_TARGET_GURNARD=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" ++CONFIG_SYS_LOAD_ADDR=0x23000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/guruplug_defconfig u-boot/configs/guruplug_defconfig +--- u-boot-2021.10/configs/guruplug_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/guruplug_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus" + CONFIG_IDENT_STRING="\nMarvell-GuruPlug" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/gwventana_emmc_defconfig u-boot/configs/gwventana_emmc_defconfig +--- u-boot-2021.10/configs/gwventana_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gwventana_emmc_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -9,12 +9,16 @@ + CONFIG_ENV_OFFSET=0xB1400 + CONFIG_MX6QDL=y + CONFIG_TARGET_GW_VENTANA=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_CMD_EECONFIG=y + CONFIG_CMD_GSC=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_STACK_R_ADDR=0x18000000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0xD1400 +@@ -26,7 +30,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -76,10 +79,14 @@ + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_LED=y + CONFIG_LED_BLINK=y + CONFIG_LED_GPIO=y +@@ -96,8 +103,10 @@ + CONFIG_PCI=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_POWER_I2C=y + CONFIG_CONS_INDEX=2 + CONFIG_DM_SERIAL=y + CONFIG_MXC_UART=y +diff -ruN u-boot-2021.10/configs/gwventana_gw5904_defconfig u-boot/configs/gwventana_gw5904_defconfig +--- u-boot-2021.10/configs/gwventana_gw5904_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gwventana_gw5904_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -9,12 +9,16 @@ + CONFIG_ENV_OFFSET=0xB1400 + CONFIG_MX6QDL=y + CONFIG_TARGET_GW_VENTANA=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_CMD_EECONFIG=y + CONFIG_CMD_GSC=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_STACK_R_ADDR=0x18000000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0xD1400 +@@ -26,7 +30,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -76,10 +79,14 @@ + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_PART=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_LED=y + CONFIG_LED_BLINK=y + CONFIG_LED_GPIO=y +@@ -100,8 +107,10 @@ + CONFIG_PCI=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_POWER_I2C=y + CONFIG_CONS_INDEX=2 + CONFIG_DM_SERIAL=y + CONFIG_MXC_UART=y +diff -ruN u-boot-2021.10/configs/gwventana_nand_defconfig u-boot/configs/gwventana_nand_defconfig +--- u-boot-2021.10/configs/gwventana_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/gwventana_nand_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -9,12 +9,16 @@ + CONFIG_ENV_OFFSET=0x1000000 + CONFIG_MX6QDL=y + CONFIG_TARGET_GW_VENTANA=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_CMD_EECONFIG=y + CONFIG_CMD_GSC=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_STACK_R_ADDR=0x18000000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x1080000 +@@ -26,7 +30,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -78,10 +81,14 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_LED=y + CONFIG_LED_BLINK=y + CONFIG_LED_GPIO=y +@@ -93,6 +100,8 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y + CONFIG_NAND_MXS_DT=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xe00000 + CONFIG_PHYLIB=y + CONFIG_DM_ETH=y + CONFIG_DM_MDIO=y +@@ -102,8 +111,10 @@ + CONFIG_PCI=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_POWER_I2C=y + CONFIG_CONS_INDEX=2 + CONFIG_DM_SERIAL=y + CONFIG_MXC_UART=y +diff -ruN u-boot-2021.10/configs/h8_homlet_v2_defconfig u-boot/configs/h8_homlet_v2_defconfig +--- u-boot-2021.10/configs/h8_homlet_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/h8_homlet_v2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_CLK=480 + CONFIG_DRAM_ZQ=15355 + CONFIG_DRAM_ODT_EN=y +-CONFIG_USB0_VBUS_PIN="PL5" +-CONFIG_USB1_VBUS_PIN="PL6" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/harmony_defconfig u-boot/configs/harmony_defconfig +--- u-boot-2021.10/configs/harmony_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/harmony_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_HARMONY=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " +@@ -36,6 +37,7 @@ + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PCI=y + CONFIG_DM_PMIC=y +diff -ruN u-boot-2021.10/configs/helios4_defconfig u-boot/configs/helios4_defconfig +--- u-boot-2021.10/configs/helios4_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/helios4_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_MVEBU=y +@@ -12,13 +13,14 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/highbank_defconfig u-boot/configs/highbank_defconfig +--- u-boot-2021.10/configs/highbank_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/highbank_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,13 +1,16 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_HIGHBANK=y + CONFIG_SYS_TEXT_BASE=0x00008000 + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/hihope_rzg2_defconfig u-boot/configs/hihope_rzg2_defconfig +--- u-boot-2021.10/configs/hihope_rzg2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/hihope_rzg2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,11 +4,13 @@ + CONFIG_SYS_TEXT_BASE=0x50000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xFFFE0000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot" + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_HIHOPE_RZG2=y + # CONFIG_SPL is not set ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/hikey960_defconfig u-boot/configs/hikey960_defconfig +--- u-boot-2021.10/configs/hikey960_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/hikey960_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x801000 + CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960" + CONFIG_IDENT_STRING="\nHikey960" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw" +diff -ruN u-boot-2021.10/configs/hikey_defconfig u-boot/configs/hikey_defconfig +--- u-boot-2021.10/configs/hikey_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/hikey_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,9 +4,11 @@ + CONFIG_NR_DRAM_BANKS=6 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x801000 + CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" + CONFIG_IDENT_STRING="hikey" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80000 + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw" +@@ -24,6 +26,7 @@ + CONFIG_MMC_DW=y + CONFIG_MMC_DW_K3=y + CONFIG_DM_ETH=y ++CONFIG_POWER_LEGACY=y + CONFIG_CONS_INDEX=4 + CONFIG_USB=y + CONFIG_USB_DWC2=y +diff -ruN u-boot-2021.10/configs/hsdk_4xd_defconfig u-boot/configs/hsdk_4xd_defconfig +--- u-boot-2021.10/configs/hsdk_4xd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/hsdk_4xd_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -3,12 +3,14 @@ + CONFIG_TARGET_HSDK=y + CONFIG_BOARD_HSDK_4XD=y + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="hsdk-4xd" + CONFIG_DEBUG_UART_BASE=0xf0005000 + CONFIG_DEBUG_UART_CLOCK=33333333 + CONFIG_SYS_CLK_FREQ=500000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/hsdk_defconfig u-boot/configs/hsdk_defconfig +--- u-boot-2021.10/configs/hsdk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/hsdk_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -2,12 +2,14 @@ + CONFIG_ISA_ARCV2=y + CONFIG_TARGET_HSDK=y + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="hsdk" + CONFIG_DEBUG_UART_BASE=0xf0005000 + CONFIG_DEBUG_UART_CLOCK=33333333 + CONFIG_SYS_CLK_FREQ=500000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/huawei_hg556a_ram_defconfig u-boot/configs/huawei_hg556a_ram_defconfig +--- u-boot-2021.10/configs/huawei_hg556a_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/huawei_hg556a_ram_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6358=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/Hummingbird_A31_defconfig u-boot/configs/Hummingbird_A31_defconfig +--- u-boot-2021.10/configs/Hummingbird_A31_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Hummingbird_A31_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,8 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_ZQ=251 +-CONFIG_USB1_VBUS_PIN="PH24" +-CONFIG_USB2_VBUS_PIN="" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_VGA_VIA_LCD=y + CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/Hyundai_A7HD_defconfig u-boot/configs/Hyundai_A7HD_defconfig +--- u-boot-2021.10/configs/Hyundai_A7HD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Hyundai_A7HD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB09" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB1_VBUS_PIN="" +-CONFIG_USB2_VBUS_PIN="PH6" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH2" + CONFIG_VIDEO_LCD_BL_EN="PH9" +@@ -16,4 +13,7 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/i12-tvbox_defconfig u-boot/configs/i12-tvbox_defconfig +--- u-boot-2021.10/configs/i12-tvbox_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/i12-tvbox_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -8,9 +8,13 @@ + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y + CONFIG_SUN7I_GMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/ib62x0_defconfig u-boot/configs/ib62x0_defconfig +--- u-boot-2021.10/configs/ib62x0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ib62x0_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0" + CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/icnova-a20-swac_defconfig u-boot/configs/icnova-a20-swac_defconfig +--- u-boot-2021.10/configs/icnova-a20-swac_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/icnova-a20-swac_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,20 +1,27 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y ++CONFIG_SUPPORT_PASSING_ATAGS=y ++CONFIG_CMDLINE_TAG=y ++CONFIG_INITRD_TAG=y ++CONFIG_SERIAL_TAG=y ++CONFIG_STATIC_MACH_TYPE=y ++CONFIG_MACH_TYPE=4283 + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac" + CONFIG_SPL=y + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=384 + CONFIG_OLD_SUNXI_KERNEL_COMPAT=y + CONFIG_MMC0_CD_PIN="PI5" +-CONFIG_USB0_VBUS_PIN="PG11" +-CONFIG_USB0_VBUS_DET="PH7" +-CONFIG_USB1_VBUS_PIN="PG10" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH22" + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_CMD_UNZIP=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +diff -ruN u-boot-2021.10/configs/iconnect_defconfig u-boot/configs/iconnect_defconfig +--- u-boot-2021.10/configs/iconnect_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iconnect_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect" + CONFIG_IDENT_STRING=" Iomega iConnect" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/ids8313_defconfig u-boot/configs/ids8313_defconfig +--- u-boot-2021.10/configs/ids8313_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ids8313_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF00000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_SYS_BOOTCOUNT_ADDR=0x9 + CONFIG_SYS_CLK_FREQ=66000000 + CONFIG_MPC83xx=y +@@ -117,6 +118,7 @@ + CONFIG_ACR_RPTCNT_4=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_LEGACY_IMAGE_FORMAT=y +@@ -154,6 +156,11 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_I2C=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -163,6 +170,7 @@ + CONFIG_SYS_FLASH_PROTECTION=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y + CONFIG_PHY_ATHEROS=y + CONFIG_PHY_BROADCOM=y + CONFIG_PHY_DAVICOM=y +diff -ruN u-boot-2021.10/configs/igep00x0_defconfig u-boot/configs/igep00x0_defconfig +--- u-boot-2021.10/configs/igep00x0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/igep00x0_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -54,10 +54,17 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_VERSION_VARIABLE=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_SYS_MTDPARTS_RUNTIME=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_MTD_UBI_FASTMAP=y + CONFIG_SMC911X=y +diff -ruN u-boot-2021.10/configs/imgtec_xilfpga_defconfig u-boot/configs/imgtec_xilfpga_defconfig +--- u-boot-2021.10/configs/imgtec_xilfpga_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imgtec_xilfpga_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,10 +1,15 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_MALLOC_F_LEN=0x600 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr" + CONFIG_TARGET_XILFPGA=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y ++CONFIG_SYS_LOAD_ADDR=0x80500000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/imx28_xea_defconfig u-boot/configs/imx28_xea_defconfig +--- u-boot-2021.10/configs/imx28_xea_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx28_xea_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,19 +7,21 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_IMX_CONFIG="" + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="imx28-xea" + CONFIG_SPL_TEXT_BASE=0x1000 + CONFIG_TARGET_XEA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x90000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_SPL_PAYLOAD="u-boot.img" ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/imx6dl_icore_nand_defconfig u-boot/configs/imx6dl_icore_nand_defconfig +--- u-boot-2021.10/configs/imx6dl_icore_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6dl_icore_nand_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,16 +11,16 @@ + CONFIG_ENV_OFFSET=0x400000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_DMA=y + CONFIG_SPL_WATCHDOG=y +@@ -51,6 +51,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6dl_mamoj_defconfig u-boot/configs/imx6dl_mamoj_defconfig +--- u-boot-2021.10/configs/imx6dl_mamoj_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6dl_mamoj_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -8,12 +8,12 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6DL_MAMOJ=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj" + CONFIG_SPL_TEXT_BASE=0x00908000 + CONFIG_IMX_HAB=y + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_OS_BOOT=y + CONFIG_CMD_SPL=y +diff -ruN u-boot-2021.10/configs/imx6qdl_icore_mipi_defconfig u-boot/configs/imx6qdl_icore_mipi_defconfig +--- u-boot-2021.10/configs/imx6qdl_icore_mipi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6qdl_icore_mipi_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0x021f0000 + CONFIG_DEBUG_UART_CLOCK=24000000 +@@ -27,7 +28,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_WATCHDOG=y +diff -ruN u-boot-2021.10/configs/imx6qdl_icore_mmc_defconfig u-boot/configs/imx6qdl_icore_mmc_defconfig +--- u-boot-2021.10/configs/imx6qdl_icore_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6qdl_icore_mmc_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024 + CONFIG_SPL=y +@@ -30,7 +31,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_WATCHDOG=y +@@ -68,6 +68,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6qdl_icore_nand_defconfig u-boot/configs/imx6qdl_icore_nand_defconfig +--- u-boot-2021.10/configs/imx6qdl_icore_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6qdl_icore_nand_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x400000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_FIT=y +@@ -21,7 +22,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_DMA=y + CONFIG_SPL_WATCHDOG=y +@@ -52,6 +52,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6qdl_icore_rqs_defconfig u-boot/configs/imx6qdl_icore_rqs_defconfig +--- u-boot-2021.10/configs/imx6qdl_icore_rqs_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6qdl_icore_rqs_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set +@@ -24,7 +25,6 @@ + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_WATCHDOG=y +diff -ruN u-boot-2021.10/configs/imx6q_icore_nand_defconfig u-boot/configs/imx6q_icore_nand_defconfig +--- u-boot-2021.10/configs/imx6q_icore_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6q_icore_nand_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x400000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6Q_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_FIT=y +@@ -21,7 +22,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_DMA=y + CONFIG_SPL_WATCHDOG=y +@@ -52,6 +52,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6q_logic_defconfig u-boot/configs/imx6q_logic_defconfig +--- u-boot-2021.10/configs/imx6q_logic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6q_logic_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -12,16 +12,16 @@ + CONFIG_MX6Q=y + CONFIG_MX6_OCRAM_256KB=y + CONFIG_TARGET_MX6LOGICPD=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_LTO=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -81,6 +81,9 @@ + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_MXS=y + CONFIG_NAND_MXS_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_ATHEROS=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6ul_geam_mmc_defconfig u-boot/configs/imx6ul_geam_mmc_defconfig +--- u-boot-2021.10/configs/imx6ul_geam_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6ul_geam_mmc_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set +@@ -22,7 +23,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/imx6ul_geam_nand_defconfig u-boot/configs/imx6ul_geam_nand_defconfig +--- u-boot-2021.10/configs/imx6ul_geam_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6ul_geam_nand_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x400000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_FIT=y +@@ -21,7 +22,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_DMA=y + CONFIG_SPL_WATCHDOG=y +@@ -52,6 +52,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx6ul_isiot_emmc_defconfig u-boot/configs/imx6ul_isiot_emmc_defconfig +--- u-boot-2021.10/configs/imx6ul_isiot_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6ul_isiot_emmc_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set +@@ -22,7 +23,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/imx6ul_isiot_nand_defconfig u-boot/configs/imx6ul_isiot_nand_defconfig +--- u-boot-2021.10/configs/imx6ul_isiot_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx6ul_isiot_nand_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,9 +11,10 @@ + CONFIG_ENV_OFFSET=0x400000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_ENGICAM=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_FIT=y +@@ -21,7 +22,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_SPL_DMA=y + CONFIG_SPL_WATCHDOG=y +@@ -52,6 +52,9 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_FEC_MXC=y +diff -ruN u-boot-2021.10/configs/imx7_cm_defconfig u-boot/configs/imx7_cm_defconfig +--- u-boot-2021.10/configs/imx7_cm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx7_cm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,17 +10,17 @@ + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y + CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7-cm" + CONFIG_TARGET_IMX7_CM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="ask" + # CONFIG_BOARD_EARLY_INIT_F is not set +@@ -62,6 +62,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y +diff -ruN u-boot-2021.10/configs/imx8mm_beacon_defconfig u-boot/configs/imx8mm_beacon_defconfig +--- u-boot-2021.10/configs/imx8mm_beacon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm_beacon_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,24 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_BEACON=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -69,7 +67,6 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_SPL_MMC_IO_VOLTAGE=y +diff -ruN u-boot-2021.10/configs/imx8mm-cl-iot-gate_defconfig u-boot/configs/imx8mm-cl-iot-gate_defconfig +--- u-boot-2021.10/configs/imx8mm-cl-iot-gate_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm-cl-iot-gate_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,25 +9,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x4400 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_FIT_SIGNATURE=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -83,7 +81,6 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=2 + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_DM_KEYBOARD=y + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_SUPPORT_EMMC_BOOT=y +diff -ruN u-boot-2021.10/configs/imx8mm_evk_defconfig u-boot/configs/imx8mm_evk_defconfig +--- u-boot-2021.10/configs/imx8mm_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,24 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_EVK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -57,7 +55,6 @@ + CONFIG_CLK_IMX8MM=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mm-icore-mx8mm-ctouch2_defconfig u-boot/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +--- u-boot-2021.10/configs/imx8mm-icore-mx8mm-ctouch2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm-icore-mx8mm-ctouch2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,21 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -56,7 +57,6 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig u-boot/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +--- u-boot-2021.10/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,21 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -56,7 +57,6 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/imx8mm_venice_defconfig u-boot/configs/imx8mm_venice_defconfig +--- u-boot-2021.10/configs/imx8mm_venice_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mm_venice_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,27 +9,25 @@ + CONFIG_SYS_MEMTEST_END=0x80000000 + CONFIG_ENV_SIZE=0x8000 + CONFIG_ENV_OFFSET=0xff0000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MM_VENICE=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0xff8000 + CONFIG_LTO=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="gsc wd-disable" +@@ -72,7 +70,6 @@ + CONFIG_CLK_IMX8MM=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_LED=y + CONFIG_LED_BLINK=y + CONFIG_LED_GPIO=y +diff -ruN u-boot-2021.10/configs/imx8mn_beacon_2g_defconfig u-boot/configs/imx8mn_beacon_2g_defconfig +--- u-boot-2021.10/configs/imx8mn_beacon_2g_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mn_beacon_2g_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,26 +10,24 @@ + CONFIG_SYS_MEMTEST_END=0x44000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" + CONFIG_SPL_TEXT_BASE=0x912000 + CONFIG_TARGET_IMX8MN_BEACON=y + CONFIG_IMX8MN_BEACON_2GB_LPDDR=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" + CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -84,7 +82,6 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mn_beacon_defconfig u-boot/configs/imx8mn_beacon_defconfig +--- u-boot-2021.10/configs/imx8mn_beacon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mn_beacon_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,25 +10,23 @@ + CONFIG_SYS_MEMTEST_END=0x44000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" + CONFIG_SPL_TEXT_BASE=0x912000 + CONFIG_TARGET_IMX8MN_BEACON=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" + CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -84,7 +82,6 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mn_ddr4_evk_defconfig u-boot/configs/imx8mn_ddr4_evk_defconfig +--- u-boot-2021.10/configs/imx8mn_ddr4_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mn_ddr4_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,25 +7,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" + CONFIG_SPL_TEXT_BASE=0x912000 + CONFIG_TARGET_IMX8MN_DDR4_EVK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -60,7 +58,6 @@ + CONFIG_CLK_IMX8MN=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mn_evk_defconfig u-boot/configs/imx8mn_evk_defconfig +--- u-boot-2021.10/configs/imx8mn_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mn_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,24 +9,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" + CONFIG_SPL_TEXT_BASE=0x912000 + CONFIG_TARGET_IMX8MN_EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" + CONFIG_ARCH_MISC_INIT=y + CONFIG_BOARD_LATE_INIT=y +@@ -62,7 +60,6 @@ + CONFIG_CLK_IMX8MN=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mp_evk_defconfig u-boot/configs/imx8mp_evk_defconfig +--- u-boot-2021.10/configs/imx8mp_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mp_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,22 +10,23 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" + CONFIG_SPL_TEXT_BASE=0x920000 + CONFIG_TARGET_IMX8MP_EVK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_LATE_INIT=y +@@ -62,7 +63,7 @@ + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y + # CONFIG_SPL_DM_I2C is not set +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_LED=y + CONFIG_LED_GPIO=y + CONFIG_SUPPORT_EMMC_BOOT=y +@@ -80,9 +81,11 @@ + CONFIG_PINCTRL=y + CONFIG_SPL_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y ++CONFIG_SPL_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_SYSRESET=y + CONFIG_SPL_SYSRESET=y +diff -ruN u-boot-2021.10/configs/imx8mq_cm_defconfig u-boot/configs/imx8mq_cm_defconfig +--- u-boot-2021.10/configs/imx8mq_cm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mq_cm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,20 +9,21 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x600000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MQ_CM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_SPL_FIT_PRINT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +@@ -46,7 +47,7 @@ + CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/imx8mq_evk_defconfig u-boot/configs/imx8mq_evk_defconfig +--- u-boot-2021.10/configs/imx8mq_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mq_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -3,18 +3,22 @@ + CONFIG_SYS_TEXT_BASE=0x40200000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x600000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MQ_EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -38,7 +42,7 @@ + CONFIG_SYS_MMC_ENV_DEV=1 + CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +@@ -48,11 +52,13 @@ + CONFIG_PHY_IMX8MQ_USB=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y ++CONFIG_SPL_POWER_LEGACY=y + CONFIG_POWER_DOMAIN=y + CONFIG_IMX8M_POWER_DOMAIN=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_DM_RESET=y + CONFIG_MXC_UART=y + CONFIG_DM_THERMAL=y +diff -ruN u-boot-2021.10/configs/imx8mq_phanbell_defconfig u-boot/configs/imx8mq_phanbell_defconfig +--- u-boot-2021.10/configs/imx8mq_phanbell_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8mq_phanbell_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -4,17 +4,21 @@ + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x600000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_IMX8MQ_PHANBELL=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_BOARD_INIT=y +@@ -44,17 +48,19 @@ + CONFIG_SYS_MMC_ENV_DEV=1 + CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_DM_ETH=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y ++CONFIG_SPL_POWER_LEGACY=y + CONFIG_POWER_DOMAIN=y + CONFIG_IMX8M_POWER_DOMAIN=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_DM_RESET=y + CONFIG_MXC_UART=y + CONFIG_DM_THERMAL=y +diff -ruN u-boot-2021.10/configs/imx8qm_mek_defconfig u-boot/configs/imx8qm_mek_defconfig +--- u-boot-2021.10/configs/imx8qm_mek_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8qm_mek_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -8,25 +8,25 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2400000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" + CONFIG_SPL_TEXT_BASE=0x100000 + CONFIG_TARGET_IMX8QM_MEK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_LOAD_IMX_CONTAINER=y + CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_LOG=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SYS_MALLOC_SIMPLE=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +@@ -50,6 +50,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_SPL_DM=y + CONFIG_SPL_CLK=y + CONFIG_CLK_IMX8=y +diff -ruN u-boot-2021.10/configs/imx8qm_rom7720_a1_4G_defconfig u-boot/configs/imx8qm_rom7720_a1_4G_defconfig +--- u-boot-2021.10/configs/imx8qm_rom7720_a1_4G_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8qm_rom7720_a1_4G_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,23 +7,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1" + CONFIG_TARGET_IMX8QM_ROM7720_A1=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_rom7720_a1/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_LOG=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +@@ -46,6 +46,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_DEV=2 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_SPL_DM=y + CONFIG_SPL_CLK=y +diff -ruN u-boot-2021.10/configs/imx8qxp_mek_defconfig u-boot/configs/imx8qxp_mek_defconfig +--- u-boot-2021.10/configs/imx8qxp_mek_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8qxp_mek_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -8,25 +8,25 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_MALLOC_LEN=0x2400000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" + CONFIG_SPL_TEXT_BASE=0x100000 + CONFIG_TARGET_IMX8QXP_MEK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_LOAD_IMX_CONTAINER=y + CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" ++CONFIG_SYS_LOAD_ADDR=0x80280000 + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_LOG=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SYS_MALLOC_SIMPLE=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_CPU=y +@@ -50,6 +50,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_SPL_DM=y + CONFIG_SPL_CLK=y +diff -ruN u-boot-2021.10/configs/imx8ulp_evk_defconfig u-boot/configs/imx8ulp_evk_defconfig +--- u-boot-2021.10/configs/imx8ulp_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imx8ulp_evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,16 +7,19 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_IMX_CONFIG="" ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk" + CONFIG_SPL_TEXT_BASE=0x22020000 + CONFIG_TARGET_IMX8ULP_EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 + CONFIG_SPL_LOAD_IMX_CONTAINER=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80480000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=0 +@@ -37,6 +40,7 @@ + CONFIG_CMD_EXT4_WRITE=y + CONFIG_SPL_OF_CONTROL=y + CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_SPL_DM=y + CONFIG_IMX_RGPIO2P=y +diff -ruN u-boot-2021.10/configs/imxrt1020-evk_defconfig u-boot/configs/imxrt1020-evk_defconfig +--- u-boot-2021.10/configs/imxrt1020-evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imxrt1020-evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,15 +7,17 @@ + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk" + CONFIG_SPL_TEXT_BASE=0x20209000 + CONFIG_TARGET_IMXRT1020_EVK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SIZE_LIMIT=0x20000 + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x20209000 + CONFIG_SD_BOOT=y + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/imxrt1050-evk_defconfig u-boot/configs/imxrt1050-evk_defconfig +--- u-boot-2021.10/configs/imxrt1050-evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/imxrt1050-evk_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,15 +9,17 @@ + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" + CONFIG_SPL_TEXT_BASE=0x20209000 + CONFIG_TARGET_IMXRT1050_EVK=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SIZE_LIMIT=0x20000 + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x20209000 + CONFIG_SD_BOOT=y + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +diff -ruN u-boot-2021.10/configs/inet1_defconfig u-boot/configs/inet1_defconfig +--- u-boot-2021.10/configs/inet1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet1_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" +@@ -15,6 +13,9 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/iNet_3F_defconfig u-boot/configs/iNet_3F_defconfig +--- u-boot-2021.10/configs/iNet_3F_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iNet_3F_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_EMR1=4 + CONFIG_MMC0_CD_PIN="PH1" +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" +@@ -15,4 +14,7 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/iNet_3W_defconfig u-boot/configs/iNet_3W_defconfig +--- u-boot-2021.10/configs/iNet_3W_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iNet_3W_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -7,12 +7,14 @@ + CONFIG_DRAM_ZQ=127 + CONFIG_DRAM_EMR1=4 + CONFIG_MMC0_CD_PIN="PH20" +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/inet86dz_defconfig u-boot/configs/inet86dz_defconfig +--- u-boot-2021.10/configs/inet86dz_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet86dz_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=552 + CONFIG_DRAM_ZQ=63351 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/iNet_86VS_defconfig u-boot/configs/iNet_86VS_defconfig +--- u-boot-2021.10/configs/iNet_86VS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iNet_86VS_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -4,8 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=408 +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +@@ -14,5 +13,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/inet97fv2_defconfig u-boot/configs/inet97fv2_defconfig +--- u-boot-2021.10/configs/inet97fv2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet97fv2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,13 +5,14 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/inet98v_rev2_defconfig u-boot/configs/inet98v_rev2_defconfig +--- u-boot-2021.10/configs/inet98v_rev2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet98v_rev2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +@@ -16,5 +14,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/inet9f_rev03_defconfig u-boot/configs/inet9f_rev03_defconfig +--- u-boot-2021.10/configs/inet9f_rev03_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet9f_rev03_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,13 +5,14 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_EMR1=4 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" + CONFIG_VIDEO_LCD_BL_EN="PH7" + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/iNet_D978_rev2_defconfig u-boot/configs/iNet_D978_rev2_defconfig +--- u-boot-2021.10/configs/iNet_D978_rev2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iNet_D978_rev2_defconfig 2021-11-01 17:10:14.176263892 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=456 + CONFIG_DRAM_ZQ=15291 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/inet_q972_defconfig u-boot/configs/inet_q972_defconfig +--- u-boot-2021.10/configs/inet_q972_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inet_q972_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=384 + CONFIG_DRAM_ZQ=251 + CONFIG_MMC0_CD_PIN="PA8" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PA15" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +@@ -19,3 +18,4 @@ + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_MUSB_HOST=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/inetspace_v2_defconfig u-boot/configs/inetspace_v2_defconfig +--- u-boot-2021.10/configs/inetspace_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/inetspace_v2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2" + CONFIG_IDENT_STRING=" IS v2" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="ns2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/integratorap_cm720t_defconfig u-boot/configs/integratorap_cm720t_defconfig +--- u-boot-2021.10/configs/integratorap_cm720t_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorap_cm720t_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,6 +5,8 @@ + CONFIG_CM720T=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x28000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorap_cm920t_defconfig u-boot/configs/integratorap_cm920t_defconfig +--- u-boot-2021.10/configs/integratorap_cm920t_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorap_cm920t_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,6 +5,8 @@ + CONFIG_CM920T=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x28000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorap_cm926ejs_defconfig u-boot/configs/integratorap_cm926ejs_defconfig +--- u-boot-2021.10/configs/integratorap_cm926ejs_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorap_cm926ejs_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,6 +5,8 @@ + CONFIG_CM926EJ_S=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x28000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorap_cm946es_defconfig u-boot/configs/integratorap_cm946es_defconfig +--- u-boot-2021.10/configs/integratorap_cm946es_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorap_cm946es_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,6 +5,8 @@ + CONFIG_CM946ES=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x28000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorcp_cm1136_defconfig u-boot/configs/integratorcp_cm1136_defconfig +--- u-boot-2021.10/configs/integratorcp_cm1136_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorcp_cm1136_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,6 +6,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x22000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorcp_cm920t_defconfig u-boot/configs/integratorcp_cm920t_defconfig +--- u-boot-2021.10/configs/integratorcp_cm920t_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorcp_cm920t_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,6 +6,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x22000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorcp_cm926ejs_defconfig u-boot/configs/integratorcp_cm926ejs_defconfig +--- u-boot-2021.10/configs/integratorcp_cm926ejs_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorcp_cm926ejs_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,6 +6,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x22000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/integratorcp_cm946es_defconfig u-boot/configs/integratorcp_cm946es_defconfig +--- u-boot-2021.10/configs/integratorcp_cm946es_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/integratorcp_cm946es_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,6 +6,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x22000 ++CONFIG_SYS_LOAD_ADDR=0x7fc0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/iot2050_defconfig u-boot/configs/iot2050_defconfig +--- u-boot-2021.10/configs/iot2050_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/iot2050_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -0,0 +1,136 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_K3=y ++CONFIG_SPL_GPIO=y ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x8000 ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_SOC_K3_AM6=y ++CONFIG_TARGET_IOT2050_A53=y ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_ENV_OFFSET=0x680000 ++CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_DM_GPIO=y ++CONFIG_SPL_DM_SPI=y ++CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic" ++CONFIG_SPL_TEXT_BASE=0x80080000 ++CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_STACK_R_ADDR=0x82000000 ++CONFIG_ENV_OFFSET_REDUND=0x6a0000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_DISTRO_DEFAULTS=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_LOAD_FIT=y ++# CONFIG_USE_SPL_FIT_GENERATOR is not set ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_BOOTSTAGE=y ++CONFIG_CONSOLE_MUX=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_SPL_BOARD_INIT=y ++CONFIG_SPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SEPARATE_BSS=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 ++CONFIG_SPL_DM_MAILBOX=y ++CONFIG_SPL_DM_SPI_FLASH=y ++CONFIG_SPL_DM_RESET=y ++CONFIG_SPL_POWER_DOMAIN=y ++# CONFIG_SPL_SPI_FLASH_TINY is not set ++CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 ++CONFIG_SYS_PROMPT="IOT2050> " ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_DFU=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_REMOTEPROC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_WDT=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++# CONFIG_ISO_PARTITION is not set ++CONFIG_OF_CONTROL=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced" ++CONFIG_SPL_MULTI_DTB_FIT=y ++CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl" ++CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_DM=y ++CONFIG_SPL_DM=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_OF_TRANSLATE=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_CLK_TI_SCI=y ++CONFIG_DFU_MMC=y ++CONFIG_DFU_RAM=y ++CONFIG_DFU_SF=y ++CONFIG_DMA_CHANNELS=y ++CONFIG_TI_K3_NAVSS_UDMA=y ++CONFIG_TI_SCI_PROTOCOL=y ++CONFIG_DA8XX_GPIO=y ++CONFIG_DM_PCA953X=y ++CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_OMAP24XX=y ++CONFIG_LED=y ++CONFIG_SPL_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_SPL_LED_GPIO=y ++CONFIG_DM_MAILBOX=y ++CONFIG_K3_SEC_PROXY=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ADMA=y ++CONFIG_MMC_SDHCI_AM654=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_DM_ETH=y ++CONFIG_PCI=y ++CONFIG_PCI_KEYSTONE=y ++CONFIG_PHY=y ++CONFIG_AM654_PHY=y ++CONFIG_OMAP_USB2_PHY=y ++CONFIG_PINCTRL=y ++# CONFIG_PINCTRL_GENERIC is not set ++CONFIG_SPL_PINCTRL=y ++# CONFIG_SPL_PINCTRL_GENERIC is not set ++CONFIG_PINCTRL_SINGLE=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_TI_SCI_POWER_DOMAIN=y ++CONFIG_REMOTEPROC_TI_K3_R5F=y ++CONFIG_DM_RESET=y ++CONFIG_RESET_TI_SCI=y ++CONFIG_DM_SERIAL=y ++CONFIG_SOC_DEVICE=y ++CONFIG_SOC_DEVICE_TI_K3=y ++CONFIG_SOC_TI=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_CADENCE_QSPI=y ++CONFIG_SYSRESET=y ++CONFIG_SPL_SYSRESET=y ++CONFIG_SYSRESET_TI_SCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++# CONFIG_WATCHDOG is not set ++# CONFIG_WATCHDOG_AUTOSTART is not set ++CONFIG_WDT=y ++CONFIG_WDT_K3_RTI=y ++CONFIG_WDT_K3_RTI_LOAD_FW=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/iot_devkit_defconfig u-boot/configs/iot_devkit_defconfig +--- u-boot-2021.10/configs/iot_devkit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/iot_devkit_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -6,9 +6,11 @@ + CONFIG_TARGET_IOT_DEVKIT=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="iot_devkit" + CONFIG_SYS_CLK_FREQ=16000000 + CONFIG_LOCALVERSION="-iotdk-1.0" ++CONFIG_SYS_LOAD_ADDR=0x30000000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_SYS_PROMPT="IoTDK# " + # CONFIG_CMD_BOOTD is not set +diff -ruN u-boot-2021.10/configs/Itead_Ibox_A20_defconfig u-boot/configs/Itead_Ibox_A20_defconfig +--- u-boot-2021.10/configs/Itead_Ibox_A20_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Itead_Ibox_A20_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,6 +10,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -17,3 +20,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/j7200_evm_a72_defconfig u-boot/configs/j7200_evm_a72_defconfig +--- u-boot-2021.10/configs/j7200_evm_a72_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j7200_evm_a72_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,19 +9,20 @@ + CONFIG_TARGET_J7200_A72_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x6A0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +@@ -45,7 +46,6 @@ + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/j7200_evm_r5_defconfig u-boot/configs/j7200_evm_r5_defconfig +--- u-boot-2021.10/configs/j7200_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j7200_evm_r5_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -8,18 +8,19 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_J7200_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +@@ -42,7 +43,6 @@ + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/j721e_evm_a72_defconfig u-boot/configs/j721e_evm_a72_defconfig +--- u-boot-2021.10/configs/j721e_evm_a72_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j721e_evm_a72_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,19 +9,20 @@ + CONFIG_TARGET_J721E_A72_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x6A0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +@@ -42,7 +43,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/j721e_evm_r5_defconfig u-boot/configs/j721e_evm_r5_defconfig +--- u-boot-2021.10/configs/j721e_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j721e_evm_r5_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -8,18 +8,19 @@ + CONFIG_K3_EARLY_CONS=y + CONFIG_TARGET_J721E_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +@@ -40,7 +41,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/j721e_hs_evm_a72_defconfig u-boot/configs/j721e_hs_evm_a72_defconfig +--- u-boot-2021.10/configs/j721e_hs_evm_a72_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j721e_hs_evm_a72_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,18 +9,19 @@ + CONFIG_TARGET_J721E_A72_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x80080000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x700000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +@@ -40,7 +41,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + # CONFIG_SPL_SPI_FLASH_TINY is not set + CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +diff -ruN u-boot-2021.10/configs/j721e_hs_evm_r5_defconfig u-boot/configs/j721e_hs_evm_r5_defconfig +--- u-boot-2021.10/configs/j721e_hs_evm_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/j721e_hs_evm_r5_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -9,19 +9,20 @@ + CONFIG_TARGET_J721E_R5_EVM=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x680000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" + CONFIG_SPL_TEXT_BASE=0x41c00000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x82000000 + CONFIG_ENV_OFFSET_REDUND=0x700000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +@@ -38,7 +39,6 @@ + CONFIG_SPL_DM_MAILBOX=y + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_POWER=y + CONFIG_SPL_POWER_DOMAIN=y + CONFIG_SPL_RAM_SUPPORT=y + CONFIG_SPL_RAM_DEVICE=y +diff -ruN u-boot-2021.10/configs/jesurun_q5_defconfig u-boot/configs/jesurun_q5_defconfig +--- u-boot-2021.10/configs/jesurun_q5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/jesurun_q5_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,10 +5,13 @@ + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=312 + CONFIG_MACPWR="PH19" +-CONFIG_USB0_VBUS_PIN="PB9" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/jethub_j100_defconfig u-boot/configs/jethub_j100_defconfig +--- u-boot-2021.10/configs/jethub_j100_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/jethub_j100_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -0,0 +1,63 @@ ++CONFIG_ARM=y ++CONFIG_SYS_CONFIG_NAME="jethub" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100" ++CONFIG_MESON_AXG=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" jethubj100" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x01000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_GPIO=y ++CONFIG_RANDOM_UUID=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD_UBI=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MESON_GXL_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_AXG=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF8563=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_GXL=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/jethub_j80_defconfig u-boot/configs/jethub_j80_defconfig +--- u-boot-2021.10/configs/jethub_j80_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/jethub_j80_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -0,0 +1,71 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="jethub-j80" ++CONFIG_SYS_CONFIG_NAME="jethub" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" ++CONFIG_MESON_GXL=y ++CONFIG_DEBUG_UART_BASE=0xc81004c0 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" jethubj80" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x01000000 ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_CONSOLE_MUX=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_RANDOM_UUID=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SARADC_MESON=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD_UBI=y ++CONFIG_PHY_MESON_GXL=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MMIOREG=y ++CONFIG_MESON_GXL_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_GXL=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_PCF8563=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_GXL=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/jetson-tk1_defconfig u-boot/configs/jetson-tk1_defconfig +--- u-boot-2021.10/configs/jetson-tk1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/jetson-tk1_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -4,10 +4,12 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA124=y + CONFIG_TARGET_JETSON_TK1=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/k2e_evm_defconfig u-boot/configs/k2e_evm_defconfig +--- u-boot-2021.10/configs/k2e_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2e_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -11,12 +13,13 @@ + CONFIG_TARGET_K2E_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_USE_BOOTCOMMAND is not set +@@ -30,6 +33,9 @@ + CONFIG_SPL_POWER=y + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -50,9 +56,11 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SPL_DM=y ++CONFIG_TI_EDMA3=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2e_hs_evm_defconfig u-boot/configs/k2e_hs_evm_defconfig +--- u-boot-2021.10/configs/k2e_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2e_hs_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -10,6 +11,7 @@ + CONFIG_TARGET_K2E_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_IMAGE_POST_PROCESS=y +@@ -17,6 +19,9 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -35,9 +40,12 @@ + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y ++CONFIG_TI_EDMA3=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2g_evm_defconfig u-boot/configs/k2g_evm_defconfig +--- u-boot-2021.10/configs/k2g_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2g_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -10,12 +12,13 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_TARGET_K2G_EVM=y + CONFIG_ENV_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_USE_BOOTCOMMAND is not set +@@ -28,6 +31,9 @@ + CONFIG_SPL_POWER=y + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -51,8 +57,10 @@ + CONFIG_DM=y + CONFIG_SPL_DM=y + CONFIG_DFU_MMC=y ++CONFIG_TI_EDMA3=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2g_hs_evm_defconfig u-boot/configs/k2g_hs_evm_defconfig +--- u-boot-2021.10/configs/k2g_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2g_hs_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -9,6 +10,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_TARGET_K2G_EVM=y + CONFIG_ENV_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_IMAGE_POST_PROCESS=y +@@ -16,6 +18,9 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -37,8 +42,11 @@ + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_DM=y + CONFIG_DFU_MMC=y ++CONFIG_TI_EDMA3=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2hk_evm_defconfig u-boot/configs/k2hk_evm_defconfig +--- u-boot-2021.10/configs/k2hk_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2hk_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -11,12 +13,13 @@ + CONFIG_TARGET_K2HK_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_USE_BOOTCOMMAND is not set +@@ -30,6 +33,9 @@ + CONFIG_SPL_POWER=y + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -50,9 +56,11 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SPL_DM=y ++CONFIG_TI_EDMA3=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2hk_hs_evm_defconfig u-boot/configs/k2hk_hs_evm_defconfig +--- u-boot-2021.10/configs/k2hk_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2hk_hs_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -10,6 +11,7 @@ + CONFIG_TARGET_K2HK_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_IMAGE_POST_PROCESS=y +@@ -17,6 +19,9 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -35,9 +40,12 @@ + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y ++CONFIG_TI_EDMA3=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2l_evm_defconfig u-boot/configs/k2l_evm_defconfig +--- u-boot-2021.10/configs/k2l_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2l_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -11,12 +13,13 @@ + CONFIG_TARGET_K2L_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_USE_BOOTCOMMAND is not set +@@ -30,6 +33,9 @@ + CONFIG_SPL_POWER=y + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -50,9 +56,11 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SPL_DM=y ++CONFIG_TI_EDMA3=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/k2l_hs_evm_defconfig u-boot/configs/k2l_hs_evm_defconfig +--- u-boot-2021.10/configs/k2l_hs_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/k2l_hs_evm_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KEYSTONE=y +@@ -10,12 +11,16 @@ + CONFIG_TARGET_K2L_EVM=y + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" + CONFIG_FIT_IMAGE_POST_PROCESS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 + CONFIG_CMD_MX_CYCLIC=y + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_GPIO is not set +@@ -36,9 +41,12 @@ + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y ++CONFIG_TI_EDMA3=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_TI_AEMIF=y + CONFIG_MISC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/khadas-edge-captain-rk3399_defconfig u-boot/configs/khadas-edge-captain-rk3399_defconfig +--- u-boot-2021.10/configs/khadas-edge-captain-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-edge-captain-rk3399_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/khadas-edge-rk3399_defconfig u-boot/configs/khadas-edge-rk3399_defconfig +--- u-boot-2021.10/configs/khadas-edge-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-edge-rk3399_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/khadas-edge-v-rk3399_defconfig u-boot/configs/khadas-edge-v-rk3399_defconfig +--- u-boot-2021.10/configs/khadas-edge-v-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-edge-v-rk3399_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/khadas-vim2_defconfig u-boot/configs/khadas-vim2_defconfig +--- u-boot-2021.10/configs/khadas-vim2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-vim2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" khadas-vim2" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/khadas-vim3_defconfig u-boot/configs/khadas-vim3_defconfig +--- u-boot-2021.10/configs/khadas-vim3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-vim3_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" khadas-vim3" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/khadas-vim3l_defconfig u-boot/configs/khadas-vim3l_defconfig +--- u-boot-2021.10/configs/khadas-vim3l_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-vim3l_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" khadas-vim3l" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/khadas-vim_defconfig u-boot/configs/khadas-vim_defconfig +--- u-boot-2021.10/configs/khadas-vim_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/khadas-vim_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" khadas-vim" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/kmcent2_defconfig u-boot/configs/kmcent2_defconfig +--- u-boot-2021.10/configs/kmcent2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmcent2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -44,6 +44,7 @@ + CONFIG_DM=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_SYS_FSL_DDR3=y + CONFIG_DM_I2C=y + CONFIG_SYS_I2C_FSL=y +@@ -58,6 +59,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y + CONFIG_PHY_MARVELL=y +diff -ruN u-boot-2021.10/configs/kmcoge5ne_defconfig u-boot/configs/kmcoge5ne_defconfig +--- u-boot-2021.10/configs/kmcoge5ne_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmcoge5ne_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -156,6 +156,7 @@ + CONFIG_LCRR_DBYP_PLL_BYPASSED=y + CONFIG_LCRR_EADC_2=y + CONFIG_LCRR_CLKDIV_4=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -169,6 +170,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y + # CONFIG_CMD_PINMUX is not set +@@ -189,6 +193,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/kmcoge5un_defconfig u-boot/configs/kmcoge5un_defconfig +--- u-boot-2021.10/configs/kmcoge5un_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmcoge5un_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -14,6 +15,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0xD0000 + CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -28,6 +30,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -47,6 +52,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/kmeter1_defconfig u-boot/configs/kmeter1_defconfig +--- u-boot-2021.10/configs/kmeter1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmeter1_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -127,6 +127,7 @@ + CONFIG_LCRR_DBYP_PLL_BYPASSED=y + CONFIG_LCRR_EADC_2=y + CONFIG_LCRR_CLKDIV_4=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -140,6 +141,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + # CONFIG_CMD_PINMUX is not set + CONFIG_CMD_DHCP=y +@@ -159,6 +163,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/km_kirkwood_128m16_defconfig u-boot/configs/km_kirkwood_128m16_defconfig +--- u-boot-2021.10/configs/km_kirkwood_128m16_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/km_kirkwood_128m16_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0x2000 + CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -24,6 +26,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -43,6 +48,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/km_kirkwood_defconfig u-boot/configs/km_kirkwood_defconfig +--- u-boot-2021.10/configs/km_kirkwood_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/km_kirkwood_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0x2000 + CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -24,6 +26,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -43,6 +48,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/km_kirkwood_pci_defconfig u-boot/configs/km_kirkwood_pci_defconfig +--- u-boot-2021.10/configs/km_kirkwood_pci_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/km_kirkwood_pci_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0x2000 + CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -25,6 +27,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -44,6 +49,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/kmnusa_defconfig u-boot/configs/kmnusa_defconfig +--- u-boot-2021.10/configs/kmnusa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmnusa_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -14,6 +15,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0xD0000 + CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -28,6 +30,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -47,6 +52,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/kmopti2_defconfig u-boot/configs/kmopti2_defconfig +--- u-boot-2021.10/configs/kmopti2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmopti2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -139,6 +139,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -152,6 +153,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + # CONFIG_CMD_PINMUX is not set + CONFIG_CMD_DHCP=y +@@ -171,6 +174,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/kmsupx5_defconfig u-boot/configs/kmsupx5_defconfig +--- u-boot-2021.10/configs/kmsupx5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmsupx5_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -119,6 +119,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -132,6 +133,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y +@@ -150,6 +153,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/kmsuse2_defconfig u-boot/configs/kmsuse2_defconfig +--- u-boot-2021.10/configs/kmsuse2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmsuse2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -15,6 +16,7 @@ + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_ENV_OFFSET_REDUND=0xD0000 + CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2" + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" +@@ -29,6 +31,9 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y +@@ -48,6 +53,12 @@ + CONFIG_NETCONSOLE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x0 ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/kmtegr1_defconfig u-boot/configs/kmtegr1_defconfig +--- u-boot-2021.10/configs/kmtegr1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmtegr1_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -118,6 +118,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" +@@ -132,6 +133,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_NAND=y + CONFIG_CMD_DHCP=y +@@ -152,6 +155,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/kmtepr2_defconfig u-boot/configs/kmtepr2_defconfig +--- u-boot-2021.10/configs/kmtepr2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kmtepr2_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -139,6 +139,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -152,6 +153,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y +@@ -170,6 +173,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/koelsch_defconfig u-boot/configs/koelsch_defconfig +--- u-boot-2021.10/configs/koelsch_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/koelsch_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Koelsch" + CONFIG_R8A7791=y + CONFIG_TARGET_KOELSCH=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/kontron_sl28_defconfig u-boot/configs/kontron_sl28_defconfig +--- u-boot-2021.10/configs/kontron_sl28_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kontron_sl28_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -7,19 +7,21 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x3e0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" + CONFIG_SPL_TEXT_BASE=0x18010000 + CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SIZE_LIMIT=0x20000 + CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x3f0000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_PSCI_RESET is not set + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +@@ -31,7 +33,7 @@ + CONFIG_PCI_INIT_R=y + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_SEPARATE_BSS=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_SPI_LOAD=y + CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 + CONFIG_CMD_ASKENV=y +@@ -60,8 +62,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y +diff -ruN u-boot-2021.10/configs/kp_imx53_defconfig u-boot/configs/kp_imx53_defconfig +--- u-boot-2021.10/configs/kp_imx53_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kp_imx53_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_TARGET_KP_IMX53=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="imx53-kp" + CONFIG_ENV_OFFSET_REDUND=0x102000 + # CONFIG_CMD_BMODE is not set ++CONFIG_SYS_LOAD_ADDR=0x72000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" + CONFIG_SHOW_BOOT_PROGRESS=y + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_STOP_STR="." +@@ -38,6 +39,7 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/kp_imx6q_tpc_defconfig u-boot/configs/kp_imx6q_tpc_defconfig +--- u-boot-2021.10/configs/kp_imx6q_tpc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kp_imx6q_tpc_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -11,18 +11,15 @@ + CONFIG_MX6QDL=y + CONFIG_MX6_DDRCAL=y + CONFIG_TARGET_KP_IMX6Q_TPC=y +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x102000 + CONFIG_SPL_PAYLOAD="u-boot.img" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/kylin-rk3036_defconfig u-boot/configs/kylin-rk3036_defconfig +--- u-boot-2021.10/configs/kylin-rk3036_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kylin-rk3036_defconfig 2021-11-01 17:10:14.179597044 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_ROCKCHIP=y +@@ -15,6 +17,7 @@ + CONFIG_DEBUG_UART_BASE=0x20068000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x60800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" +diff -ruN u-boot-2021.10/configs/kzm9g_defconfig u-boot/configs/kzm9g_defconfig +--- u-boot-2021.10/configs/kzm9g_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/kzm9g_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,8 +6,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x60000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT" + CONFIG_TARGET_KZM9G=y ++CONFIG_SYS_LOAD_ADDR=0x43000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" +@@ -24,6 +26,8 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0x40000 + CONFIG_VERSION_VARIABLE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SH=y + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/lager_defconfig u-boot/configs/lager_defconfig +--- u-boot-2021.10/configs/lager_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lager_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Lager" + CONFIG_R8A7790=y + CONFIG_TARGET_LAGER=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/Lamobo_R1_defconfig u-boot/configs/Lamobo_R1_defconfig +--- u-boot-2021.10/configs/Lamobo_R1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Lamobo_R1_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -12,6 +12,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_B53_SWITCH=y + CONFIG_B53_PHY_PORTS=0x1f + CONFIG_PHY_REALTEK=y +@@ -22,3 +25,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/leez-rk3399_defconfig u-boot/configs/leez-rk3399_defconfig +--- u-boot-2021.10/configs/leez-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/leez-rk3399_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_STACK_R=y +diff -ruN u-boot-2021.10/configs/legoev3_defconfig u-boot/configs/legoev3_defconfig +--- u-boot-2021.10/configs/legoev3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/legoev3_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,10 +1,13 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_DAVINCI=y + CONFIG_SYS_TEXT_BASE=0xc1080000 + CONFIG_TARGET_LEGOEV3=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x110000 + CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3" ++CONFIG_SYS_LOAD_ADDR=0xc0700000 + CONFIG_BOOTDELAY=0 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n" +@@ -34,6 +37,7 @@ + # CONFIG_NET is not set + CONFIG_DM=y + # CONFIG_DM_DEVICE_REMOVE is not set ++CONFIG_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_DAVINCI=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/libretech-ac_defconfig u-boot/configs/libretech-ac_defconfig +--- u-boot-2021.10/configs/libretech-ac_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/libretech-ac_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -13,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" libretech-ac" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/libretech-cc_defconfig u-boot/configs/libretech-cc_defconfig +--- u-boot-2021.10/configs/libretech-cc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/libretech-cc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" libretech-cc" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/libretech-cc_v2_defconfig u-boot/configs/libretech-cc_v2_defconfig +--- u-boot-2021.10/configs/libretech-cc_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/libretech-cc_v2_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -12,6 +12,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" libretech-cc-v2" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/libretech-s905d-pc_defconfig u-boot/configs/libretech-s905d-pc_defconfig +--- u-boot-2021.10/configs/libretech-s905d-pc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/libretech-s905d-pc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -13,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" libretech-s905d-pc" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/libretech-s912-pc_defconfig u-boot/configs/libretech-s912-pc_defconfig +--- u-boot-2021.10/configs/libretech-s912-pc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/libretech-s912-pc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -12,6 +12,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" libretech-s912-pc" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/linkit-smart-7688_defconfig u-boot/configs/linkit-smart-7688_defconfig +--- u-boot-2021.10/configs/linkit-smart-7688_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/linkit-smart-7688_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,20 +1,25 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x80000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 + CONFIG_SPL=y + CONFIG_ARCH_MTMIPS=y + CONFIG_SOC_MT7628=y + CONFIG_BOARD_LINKIT_SMART_7688=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_LEGACY_IMAGE_FORMAT=y +diff -ruN u-boot-2021.10/configs/Linksprite_pcDuino3_defconfig u-boot/configs/Linksprite_pcDuino3_defconfig +--- u-boot-2021.10/configs/Linksprite_pcDuino3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Linksprite_pcDuino3_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,6 +10,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -17,3 +20,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Linksprite_pcDuino3_Nano_defconfig u-boot/configs/Linksprite_pcDuino3_Nano_defconfig +--- u-boot-2021.10/configs/Linksprite_pcDuino3_Nano_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Linksprite_pcDuino3_Nano_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,13 +5,16 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=122 +-CONFIG_USB1_VBUS_PIN="PH11" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SATAPWR="PH2" + CONFIG_GMAC_TX_DELAY=3 + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +diff -ruN u-boot-2021.10/configs/Linksprite_pcDuino_defconfig u-boot/configs/Linksprite_pcDuino_defconfig +--- u-boot-2021.10/configs/Linksprite_pcDuino_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Linksprite_pcDuino_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -3,11 +3,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y +-CONFIG_USB1_VBUS_PIN="" +-CONFIG_USB2_VBUS_PIN="" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/lion-rk3368_defconfig u-boot/configs/lion-rk3368_defconfig +--- u-boot-2021.10/configs/lion-rk3368_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lion-rk3368_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -14,8 +15,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF180000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/liteboard_defconfig u-boot/configs/liteboard_defconfig +--- u-boot-2021.10/configs/liteboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/liteboard_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -11,14 +11,14 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6UL=y + CONFIG_TARGET_LITEBOARD=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=1 + CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb" + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/ls1012a2g5rdb_qspi_defconfig u-boot/configs/ls1012a2g5rdb_qspi_defconfig +--- u-boot-2021.10/configs/ls1012a2g5rdb_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012a2g5rdb_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" + CONFIG_FSL_LS_PPA=y +@@ -17,7 +18,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -41,6 +41,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012a2g5rdb_tfa_defconfig u-boot/configs/ls1012a2g5rdb_tfa_defconfig +--- u-boot-2021.10/configs/ls1012a2g5rdb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012a2g5rdb_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" + CONFIG_QSPI_AHB_INIT=y +@@ -41,6 +42,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrdm_qspi_defconfig u-boot/configs/ls1012afrdm_qspi_defconfig +--- u-boot-2021.10/configs/ls1012afrdm_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrdm_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" + CONFIG_FSL_LS_PPA=y +@@ -16,7 +17,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -38,6 +38,7 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrdm_tfa_defconfig u-boot/configs/ls1012afrdm_tfa_defconfig +--- u-boot-2021.10/configs/ls1012afrdm_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrdm_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" + CONFIG_QSPI_AHB_INIT=y +@@ -38,6 +39,7 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrwy_qspi_defconfig u-boot/configs/ls1012afrwy_qspi_defconfig +--- u-boot-2021.10/configs/ls1012afrwy_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrwy_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x1D0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" + CONFIG_FSL_LS_PPA=y +@@ -16,7 +17,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -43,6 +43,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" + CONFIG_FSL_LS_PPA=y +@@ -15,7 +16,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -38,6 +38,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrwy_tfa_defconfig u-boot/configs/ls1012afrwy_tfa_defconfig +--- u-boot-2021.10/configs/ls1012afrwy_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrwy_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x1D0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +@@ -42,6 +43,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +@@ -38,6 +39,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012aqds_qspi_defconfig u-boot/configs/ls1012aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls1012aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012aqds_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" + CONFIG_FSL_LS_PPA=y +@@ -17,7 +18,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -26,8 +26,11 @@ + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPT=y +@@ -54,6 +57,8 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012aqds_tfa_defconfig u-boot/configs/ls1012aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls1012aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012aqds_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" + CONFIG_QSPI_AHB_INIT=y +@@ -26,8 +27,11 @@ + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPT=y +@@ -54,6 +58,8 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" + CONFIG_QSPI_AHB_INIT=y +@@ -24,8 +25,11 @@ + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPT=y +@@ -42,6 +46,8 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012ardb_qspi_defconfig u-boot/configs/ls1012ardb_qspi_defconfig +--- u-boot-2021.10/configs/ls1012ardb_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012ardb_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -17,7 +18,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -44,6 +44,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -16,7 +17,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -42,6 +42,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012ardb_tfa_defconfig u-boot/configs/ls1012ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls1012ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012ardb_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" + CONFIG_QSPI_AHB_INIT=y +@@ -43,6 +44,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" + CONFIG_QSPI_AHB_INIT=y +@@ -41,6 +42,7 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021aiot_qspi_defconfig u-boot/configs/ls1021aiot_qspi_defconfig +--- u-boot-2021.10/configs/ls1021aiot_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aiot_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -5,14 +5,21 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" + CONFIG_AHCI=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++CONFIG_SYS_LOAD_ADDR=0x82000000 ++CONFIG_QSPI_BOOT=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -31,6 +38,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x51 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/ls1021aiot_sdcard_defconfig u-boot/configs/ls1021aiot_sdcard_defconfig +--- u-boot-2021.10/configs/ls1021aiot_sdcard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aiot_sdcard_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -4,20 +4,31 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_AHCI=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_SYS_LOAD_ADDR=0x82000000 ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -37,6 +48,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x51 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_ddr4_nor_defconfig u-boot/configs/ls1021aqds_ddr4_nor_defconfig +--- u-boot-2021.10/configs/ls1021aqds_ddr4_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_ddr4_nor_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -18,10 +24,12 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -43,7 +51,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -51,6 +65,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_ddr4_nor_lpuart_defconfig u-boot/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +--- u-boot-2021.10/configs/ls1021aqds_ddr4_nor_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_ddr4_nor_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -19,10 +25,12 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -44,7 +52,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -52,6 +66,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_nand_defconfig u-boot/configs/ls1021aqds_nand_defconfig +--- u-boot-2021.10/configs/ls1021aqds_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_nand_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,36 +10,46 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x140000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg" + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -60,14 +72,25 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000 + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_nor_defconfig u-boot/configs/ls1021aqds_nor_defconfig +--- u-boot-2021.10/configs/ls1021aqds_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_nor_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -18,10 +24,12 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -43,8 +51,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -52,6 +66,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_nor_lpuart_defconfig u-boot/configs/ls1021aqds_nor_lpuart_defconfig +--- u-boot-2021.10/configs/ls1021aqds_nor_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_nor_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -19,10 +25,12 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -44,8 +52,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -53,6 +67,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_nor_SECURE_BOOT_defconfig u-boot/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1021aqds_nor_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_nor_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,11 +7,16 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -19,10 +25,12 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -41,8 +49,14 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -50,6 +64,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_qspi_defconfig u-boot/configs/ls1021aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls1021aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x40100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -7,23 +8,29 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -45,7 +52,12 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_sdcard_ifc_defconfig u-boot/configs/ls1021aqds_sdcard_ifc_defconfig +--- u-boot-2021.10/configs/ls1021aqds_sdcard_ifc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_sdcard_ifc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,34 +10,44 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -58,8 +70,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -67,6 +85,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_REALTEK=y + CONFIG_PHY_GIGE=y + CONFIG_E1000=y +diff -ruN u-boot-2021.10/configs/ls1021aqds_sdcard_qspi_defconfig u-boot/configs/ls1021aqds_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1021aqds_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021aqds_sdcard_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021AQDS=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,33 +10,43 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -57,7 +69,12 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1021atsn_qspi_defconfig u-boot/configs/ls1021atsn_qspi_defconfig +--- u-boot-2021.10/configs/ls1021atsn_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atsn_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -5,19 +5,25 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPT=y +@@ -32,6 +38,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x51 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atsn_sdcard_defconfig u-boot/configs/ls1021atsn_sdcard_defconfig +--- u-boot-2021.10/configs/ls1021atsn_sdcard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atsn_sdcard_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,29 +6,39 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" + CONFIG_SPL_TEXT_BASE=0x10000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_SYS_EXTRA_OPTIONS="SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPT=y +@@ -43,6 +53,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x51 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_nor_defconfig u-boot/configs/ls1021atwr_nor_defconfig +--- u-boot-2021.10/configs/ls1021atwr_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_nor_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -20,8 +26,10 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -38,6 +46,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_nor_lpuart_defconfig u-boot/configs/ls1021atwr_nor_lpuart_defconfig +--- u-boot-2021.10/configs/ls1021atwr_nor_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_nor_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,10 +7,15 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -22,8 +28,10 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -40,6 +48,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_nor_SECURE_BOOT_defconfig u-boot/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -6,11 +7,16 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -21,8 +27,10 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -36,6 +44,9 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_qspi_defconfig u-boot/configs/ls1021atwr_qspi_defconfig +--- u-boot-2021.10/configs/ls1021atwr_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x40100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -7,15 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1002000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -24,7 +29,9 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -41,6 +48,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_sdcard_ifc_defconfig u-boot/configs/ls1021atwr_sdcard_ifc_defconfig +--- u-boot-2021.10/configs/ls1021atwr_sdcard_ifc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_sdcard_ifc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,19 +10,27 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -28,15 +38,17 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -53,6 +65,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig u-boot/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,34 +10,44 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" + CONFIG_BOOTDELAY=0 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -52,6 +64,9 @@ + # CONFIG_SPL_BLK is not set + CONFIG_DM_I2C=y + # CONFIG_SPL_DM_I2C is not set ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + # CONFIG_SPL_DM_MMC is not set + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/ls1021atwr_sdcard_qspi_defconfig u-boot/configs/ls1021atwr_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1021atwr_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1021atwr_sdcard_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1021ATWR=y + CONFIG_SYS_TEXT_BASE=0x82000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -8,19 +10,27 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1020000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -28,14 +38,16 @@ + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -52,6 +64,9 @@ + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/ls1028aqds_tfa_defconfig u-boot/configs/ls1028aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls1028aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1028aqds_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LS1028AQDS=y + CONFIG_TFABOOT=y +@@ -9,6 +10,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" + CONFIG_FSPI_AHB_EN_4BYTE=y +@@ -23,7 +25,9 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y +@@ -46,11 +50,12 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1028aqds_tfa_lpuart_defconfig u-boot/configs/ls1028aqds_tfa_lpuart_defconfig +--- u-boot-2021.10/configs/ls1028aqds_tfa_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1028aqds_tfa_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_LS1028AQDS=y + CONFIG_TFABOOT=y + CONFIG_SYS_MALLOC_F_LEN=0x6000 +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart" + CONFIG_FSPI_AHB_EN_4BYTE=y +@@ -23,7 +25,9 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y +@@ -46,11 +50,12 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LS1028AQDS=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" + CONFIG_FSPI_AHB_EN_4BYTE=y +@@ -22,7 +24,9 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y +@@ -40,11 +44,12 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1028ardb_tfa_defconfig u-boot/configs/ls1028ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls1028ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1028ardb_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LS1028ARDB=y + CONFIG_TFABOOT=y +@@ -9,6 +10,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" + CONFIG_FSPI_AHB_EN_4BYTE=y +@@ -22,7 +24,9 @@ + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y +@@ -45,11 +49,12 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LS1028ARDB=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" + CONFIG_FSPI_AHB_EN_4BYTE=y +@@ -21,7 +23,9 @@ + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y +@@ -39,11 +43,12 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_defconfig u-boot/configs/ls1043aqds_defconfig +--- u-boot-2021.10/configs/ls1043aqds_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -22,6 +27,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -40,7 +46,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -48,6 +60,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_lpuart_defconfig u-boot/configs/ls1043aqds_lpuart_defconfig +--- u-boot-2021.10/configs/ls1043aqds_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -23,6 +28,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -41,7 +47,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -49,6 +61,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_nand_defconfig u-boot/configs/ls1043aqds_nand_defconfig +--- u-boot-2021.10/configs/ls1043aqds_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_nand_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,19 +8,27 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg" + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -32,12 +40,13 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -57,13 +66,24 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_nor_ddr3_defconfig u-boot/configs/ls1043aqds_nor_ddr3_defconfig +--- u-boot-2021.10/configs/ls1043aqds_nor_ddr3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_nor_ddr3_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -22,6 +27,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -40,8 +46,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -49,6 +61,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_qspi_defconfig u-boot/configs/ls1043aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls1043aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -15,7 +20,6 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -24,6 +28,7 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -42,7 +47,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_sdcard_ifc_defconfig u-boot/configs/ls1043aqds_sdcard_ifc_defconfig +--- u-boot-2021.10/configs/ls1043aqds_sdcard_ifc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_sdcard_ifc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,20 +8,28 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -33,11 +41,12 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -57,7 +66,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -65,6 +80,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_sdcard_qspi_defconfig u-boot/configs/ls1043aqds_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1043aqds_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_sdcard_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,20 +8,28 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -33,10 +41,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -55,7 +64,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_tfa_defconfig u-boot/configs/ls1043aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls1043aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,6 +30,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -49,7 +55,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +70,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -24,6 +29,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -39,7 +45,14 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -47,6 +60,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_defconfig u-boot/configs/ls1043ardb_defconfig +--- u-boot-2021.10/configs/ls1043ardb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -4,6 +4,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -15,6 +20,7 @@ + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" + CONFIG_MISC_INIT_R=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -31,7 +37,12 @@ + CONFIG_ENV_ADDR=0x60300000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -39,6 +50,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_nand_defconfig u-boot/configs/ls1043ardb_nand_defconfig +--- u-boot-2021.10/configs/ls1043ardb_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_nand_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,17 +6,25 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -29,10 +37,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -51,12 +60,20 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_nand_SECURE_BOOT_defconfig u-boot/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1043ardb_nand_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_nand_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -27,10 +31,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -48,12 +53,19 @@ + CONFIG_DM=y + CONFIG_SPL_DM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_sdcard_defconfig u-boot/configs/ls1043ardb_sdcard_defconfig +--- u-boot-2021.10/configs/ls1043ardb_sdcard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_sdcard_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,18 +6,26 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -28,10 +36,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 + CONFIG_SPL_ENV_SUPPORT=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -50,6 +59,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +69,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig u-boot/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,18 +6,22 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -27,10 +31,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -49,6 +54,8 @@ + CONFIG_SPL_DM=y + # CONFIG_SPL_BLK is not set + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + # CONFIG_SPL_DM_MMC is not set + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y +@@ -57,6 +64,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_REALTEK=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_SECURE_BOOT_defconfig u-boot/configs/ls1043ardb_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1043ardb_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -4,6 +4,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x20000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -15,6 +20,7 @@ + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" + CONFIG_MISC_INIT_R=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -28,7 +34,12 @@ + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y ++# CONFIG_DDR_SPD is not set ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -36,6 +47,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_REALTEK=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_tfa_defconfig u-boot/configs/ls1043ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls1043ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +@@ -18,6 +23,7 @@ + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" + CONFIG_MISC_INIT_R=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -36,7 +42,12 @@ + CONFIG_ENV_ADDR=0x60500000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -44,6 +55,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -5,6 +5,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" + CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +@@ -17,6 +22,7 @@ + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" + CONFIG_MISC_INIT_R=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -30,7 +36,12 @@ + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y ++# CONFIG_DDR_SPD is not set ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -38,6 +49,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHY_REALTEK=y +diff -ruN u-boot-2021.10/configs/ls1046afrwy_tfa_defconfig u-boot/configs/ls1046afrwy_tfa_defconfig +--- u-boot-2021.10/configs/ls1046afrwy_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046afrwy_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -20,6 +21,7 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -38,10 +40,15 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_STMICRO=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +diff -ruN u-boot-2021.10/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -18,6 +19,7 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -32,10 +34,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++# CONFIG_DDR_SPD is not set + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_STMICRO=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +diff -ruN u-boot-2021.10/configs/ls1046aqds_defconfig u-boot/configs/ls1046aqds_defconfig +--- u-boot-2021.10/configs/ls1046aqds_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -22,6 +27,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -41,7 +47,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -49,6 +60,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_lpuart_defconfig u-boot/configs/ls1046aqds_lpuart_defconfig +--- u-boot-2021.10/configs/ls1046aqds_lpuart_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_lpuart_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -23,6 +28,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -42,7 +48,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -50,6 +61,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_nand_defconfig u-boot/configs/ls1046aqds_nand_defconfig +--- u-boot-2021.10/configs/ls1046aqds_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_nand_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,18 +6,25 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg" + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -28,9 +35,11 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -50,13 +59,22 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_qspi_defconfig u-boot/configs/ls1046aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls1046aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -23,6 +28,7 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -42,7 +48,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_sdcard_ifc_defconfig u-boot/configs/ls1046aqds_sdcard_ifc_defconfig +--- u-boot-2021.10/configs/ls1046aqds_sdcard_ifc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_sdcard_ifc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,20 +8,27 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -34,11 +41,12 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -59,7 +67,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -67,6 +80,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_sdcard_qspi_defconfig u-boot/configs/ls1046aqds_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1046aqds_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_sdcard_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,20 +8,28 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT_QSPI" ++CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -34,10 +42,11 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -57,7 +66,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_SECURE_BOOT_defconfig u-boot/configs/ls1046aqds_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046aqds_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,6 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -22,6 +27,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -38,7 +44,12 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -46,6 +57,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_tfa_defconfig u-boot/configs/ls1046aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls1046aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_tfa_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -8,6 +8,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,6 +30,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -49,7 +55,13 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +69,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -7,6 +7,11 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -24,6 +29,7 @@ + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -40,7 +46,13 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -48,6 +60,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_SPI_FLASH_SPANSION=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_emmc_defconfig u-boot/configs/ls1046ardb_emmc_defconfig +--- u-boot-2021.10/configs/ls1046ardb_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_emmc_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -6,19 +6,27 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,EMMC_BOOT" ++CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -31,8 +39,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -52,10 +61,16 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y +@@ -70,6 +85,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_MMC=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_qspi_defconfig u-boot/configs/ls1046ardb_qspi_defconfig +--- u-boot-2021.10/configs/ls1046ardb_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_qspi_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -5,6 +5,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -13,11 +18,15 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -37,10 +46,16 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +@@ -56,6 +71,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.182930194 +0100 +@@ -4,6 +4,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_FSL_LS_PPA=y +@@ -12,11 +17,15 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -33,10 +42,16 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +@@ -52,6 +67,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_qspi_spl_defconfig u-boot/configs/ls1046ardb_qspi_spl_defconfig +--- u-boot-2021.10/configs/ls1046ardb_qspi_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_qspi_spl_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,13 +7,18 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y + CONFIG_SPL_FSL_LS_PPA=y + CONFIG_QSPI_AHB_INIT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y +@@ -22,6 +27,9 @@ + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_BOARD_SETUP=y ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -30,12 +38,13 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_SPL_OS_BOOT=y + CONFIG_SYS_OS_BASE=0x40980000 + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_SPL=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -56,10 +65,16 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y +@@ -74,6 +89,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_sdcard_defconfig u-boot/configs/ls1046ardb_sdcard_defconfig +--- u-boot-2021.10/configs/ls1046ardb_sdcard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_sdcard_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,19 +6,26 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -30,8 +37,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -51,10 +59,16 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y +@@ -69,6 +83,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_MMC=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig u-boot/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,18 +6,25 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_SPL_TEXT_BASE=0x10000000 + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046ardb/ls1046ardb_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -28,8 +35,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_WATCHDOG=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -48,12 +56,18 @@ + CONFIG_DM=y + CONFIG_SPL_DM=y + # CONFIG_SPL_BLK is not set ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + # CONFIG_SPL_DM_I2C is not set ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + # CONFIG_SPL_DM_MMC is not set + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set + CONFIG_PHYLIB=y +@@ -67,6 +81,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_SYS_QE_FMAN_FW_IN_MMC=y + CONFIG_SYS_NS16550=y + CONFIG_SPI=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_tfa_defconfig u-boot/configs/ls1046ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls1046ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_QSPI_AHB_INIT=y +@@ -19,6 +24,7 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -39,10 +45,16 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +@@ -58,6 +70,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y + CONFIG_SPI=y +diff -ruN u-boot-2021.10/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x102000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" + CONFIG_QSPI_AHB_INIT=y +@@ -18,6 +23,7 @@ + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" + CONFIG_MISC_INIT_R=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -33,10 +39,16 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x53 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +@@ -52,6 +64,8 @@ + CONFIG_PCI=y + CONFIG_PCIE_LAYERSCAPE_RC=y + CONFIG_PCIE_LAYERSCAPE_EP=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_DM_SCSI=y + CONFIG_SYS_NS16550=y + CONFIG_SPI=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_defconfig u-boot/configs/ls1088aqds_defconfig +--- u-boot-2021.10/configs/ls1088aqds_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -16,13 +17,13 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -44,6 +45,12 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -51,6 +58,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_qspi_defconfig u-boot/configs/ls1088aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls1088aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -19,13 +20,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" ++CONFIG_QSPI_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -45,9 +47,15 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -18,13 +19,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" ++CONFIG_QSPI_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -42,9 +44,15 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_sdcard_ifc_defconfig u-boot/configs/ls1088aqds_sdcard_ifc_defconfig +--- u-boot-2021.10/configs/ls1088aqds_sdcard_ifc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_sdcard_ifc_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,19 +9,19 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_F is not set + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_SD_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" +@@ -31,9 +31,10 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -55,6 +56,12 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -62,6 +69,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y + CONFIG_PHY_REALTEK=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_sdcard_qspi_defconfig u-boot/configs/ls1088aqds_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1088aqds_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_sdcard_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,13 +9,14 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y +@@ -34,8 +35,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_GPIO=y +@@ -55,9 +57,15 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088aqds_tfa_defconfig u-boot/configs/ls1088aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls1088aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088aqds_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -10,6 +10,7 @@ + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -21,13 +22,13 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -54,11 +55,14 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -66,6 +70,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_qspi_defconfig u-boot/configs/ls1088ardb_qspi_defconfig +--- u-boot-2021.10/configs/ls1088ardb_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -19,7 +20,7 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" ++CONFIG_QSPI_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set +@@ -27,6 +28,7 @@ + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -47,9 +49,17 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_MXC_I2C1_SPEED=40000000 ++CONFIG_SYS_MXC_I2C2_SPEED=40000000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -18,7 +19,7 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" ++CONFIG_QSPI_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set +@@ -26,6 +27,7 @@ + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -44,9 +46,17 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_MXC_I2C1_SPEED=40000000 ++CONFIG_SYS_MXC_I2C2_SPEED=40000000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_sdcard_qspi_defconfig u-boot/configs/ls1088ardb_sdcard_qspi_defconfig +--- u-boot-2021.10/configs/ls1088ardb_sdcard_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_sdcard_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,13 +9,14 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y +@@ -35,8 +36,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -57,9 +59,17 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_MXC_I2C1_SPEED=40000000 ++CONFIG_SYS_MXC_I2C2_SPEED=40000000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig u-boot/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,13 +9,14 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y +@@ -34,8 +35,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -56,10 +58,18 @@ + CONFIG_SPL_DM=y + CONFIG_SCSI_AHCI=y + # CONFIG_SPL_BLK is not set ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_MXC_I2C1_SPEED=40000000 ++CONFIG_SYS_MXC_I2C2_SPEED=40000000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + # CONFIG_SPL_DM_MMC is not set + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_tfa_defconfig u-boot/configs/ls1088ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls1088ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -10,6 +10,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -21,7 +22,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set +@@ -29,6 +29,7 @@ + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -51,14 +52,18 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SYS_MEMTEST_END=0x9fffffff + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -20,7 +21,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" + # CONFIG_USE_BOOTCOMMAND is not set +@@ -28,6 +28,7 @@ + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_DM=y +@@ -45,14 +46,18 @@ + CONFIG_DM=y + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls2080aqds_defconfig u-boot/configs/ls2080aqds_defconfig +--- u-boot-2021.10/configs/ls2080aqds_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080aqds_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +@@ -20,6 +21,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +42,11 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -46,6 +54,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls2080aqds_nand_defconfig u-boot/configs/ls2080aqds_nand_defconfig +--- u-boot-2021.10/configs/ls2080aqds_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080aqds_nand_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,10 +7,11 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xE0000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y +@@ -25,10 +26,12 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -50,8 +53,19 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/ls2080aqds_qspi_defconfig u-boot/configs/ls2080aqds_qspi_defconfig +--- u-boot-2021.10/configs/ls2080aqds_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080aqds_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_AHCI=y +@@ -13,7 +14,6 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -21,6 +21,8 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -41,9 +43,17 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/ls2080aqds_sdcard_defconfig u-boot/configs/ls2080aqds_sdcard_defconfig +--- u-boot-2021.10/configs/ls2080aqds_sdcard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080aqds_sdcard_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,19 +7,19 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=10 + CONFIG_USE_BOOTARGS=y +@@ -29,8 +29,9 @@ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_NAND=y +@@ -48,9 +49,17 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/ls2080aqds_SECURE_BOOT_defconfig u-boot/configs/ls2080aqds_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls2080aqds_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080aqds_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +@@ -20,6 +21,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -36,6 +39,11 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -43,6 +51,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls2080ardb_defconfig u-boot/configs/ls2080ardb_defconfig +--- u-boot-2021.10/configs/ls2080ardb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080ardb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +@@ -21,6 +22,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +42,11 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -46,6 +54,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls2080ardb_nand_defconfig u-boot/configs/ls2080ardb_nand_defconfig +--- u-boot-2021.10/configs/ls2080ardb_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080ardb_nand_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,10 +7,11 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x200000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" + CONFIG_SPL_TEXT_BASE=0x1800a000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_AHCI=y +@@ -26,11 +27,13 @@ + CONFIG_MISC_INIT_R=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -49,12 +52,22 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000 + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y + CONFIG_PHY_CORTINA=y +diff -ruN u-boot-2021.10/configs/ls2080ardb_SECURE_BOOT_defconfig u-boot/configs/ls2080ardb_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls2080ardb_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2080ardb_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +@@ -21,6 +22,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -36,6 +39,11 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -43,6 +51,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHY_AQUANTIA=y +diff -ruN u-boot-2021.10/configs/ls2081ardb_defconfig u-boot/configs/ls2081ardb_defconfig +--- u-boot-2021.10/configs/ls2081ardb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2081ardb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y + CONFIG_FSL_LS_PPA=y +@@ -22,6 +23,7 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +41,12 @@ + CONFIG_SCSI_AHCI=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls2088aqds_tfa_defconfig u-boot/configs/ls2088aqds_tfa_defconfig +--- u-boot-2021.10/configs/ls2088aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2088aqds_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -24,6 +25,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -49,11 +52,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -61,6 +67,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_PHYLIB=y + CONFIG_PHYLIB_10G=y +diff -ruN u-boot-2021.10/configs/ls2088ardb_qspi_defconfig u-boot/configs/ls2088ardb_qspi_defconfig +--- u-boot-2021.10/configs/ls2088ardb_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2088ardb_qspi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -23,6 +24,7 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -42,6 +44,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig u-boot/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -20,6 +21,7 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -35,6 +37,12 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_EARLY_INIT=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/ls2088ardb_tfa_defconfig u-boot/configs/ls2088ardb_tfa_defconfig +--- u-boot-2021.10/configs/ls2088ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2088ardb_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -26,6 +27,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -47,11 +50,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -59,6 +65,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,6 +7,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,6 +26,8 @@ + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -40,11 +43,14 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -52,6 +58,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + # CONFIG_SPI_FLASH_BAR is not set + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/lschlv2_defconfig u-boot/configs/lschlv2_defconfig +--- u-boot-2021.10/configs/lschlv2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lschlv2_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2" + CONFIG_IDENT_STRING=" LS-CHLv2" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_API=y + CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" + CONFIG_SHOW_BOOT_PROGRESS=y +diff -ruN u-boot-2021.10/configs/lsxhl_defconfig u-boot/configs/lsxhl_defconfig +--- u-boot-2021.10/configs/lsxhl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lsxhl_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl" + CONFIG_IDENT_STRING=" LS-XHL" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_API=y + CONFIG_SYS_EXTRA_OPTIONS="LSXHL" + CONFIG_SHOW_BOOT_PROGRESS=y +diff -ruN u-boot-2021.10/configs/lx2160aqds_tfa_defconfig u-boot/configs/lx2160aqds_tfa_defconfig +--- u-boot-2021.10/configs/lx2160aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2160aqds_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2160AQDS=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -27,6 +29,8 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -48,11 +52,14 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2160AQDS=y + CONFIG_TFABOOT=y +@@ -7,6 +8,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,6 +27,8 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -41,11 +45,14 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/lx2160ardb_tfa_defconfig u-boot/configs/lx2160ardb_tfa_defconfig +--- u-boot-2021.10/configs/lx2160ardb_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2160ardb_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2160ARDB=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -27,6 +29,8 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -47,9 +51,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y +diff -ruN u-boot-2021.10/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig u-boot/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2160ARDB=y + CONFIG_TFABOOT=y +@@ -7,6 +8,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,6 +27,8 @@ + CONFIG_MISC_INIT_R=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -39,9 +43,12 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/lx2160ardb_tfa_stmm_defconfig u-boot/configs/lx2160ardb_tfa_stmm_defconfig +--- u-boot-2021.10/configs/lx2160ardb_tfa_stmm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2160ardb_tfa_stmm_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2160ARDB=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -28,6 +30,8 @@ + CONFIG_CMD_GREPENV=y + CONFIG_CMD_NVEDIT_EFI=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -47,9 +51,12 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y +diff -ruN u-boot-2021.10/configs/lx2162aqds_tfa_defconfig u-boot/configs/lx2162aqds_tfa_defconfig +--- u-boot-2021.10/configs/lx2162aqds_tfa_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2162aqds_tfa_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2162AQDS=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -25,8 +27,11 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -49,12 +54,15 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_MPC8XXX_GPIO=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y +diff -ruN u-boot-2021.10/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig u-boot/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2162AQDS=y + CONFIG_TFABOOT=y +@@ -7,6 +8,7 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x2000 + CONFIG_NXP_ESBC=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -23,8 +25,11 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -42,12 +47,15 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_DM=y + CONFIG_SATA_CEVA=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_MPC8XXX_GPIO=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/lx2162aqds_tfa_verified_boot_defconfig u-boot/configs/lx2162aqds_tfa_verified_boot_defconfig +--- u-boot-2021.10/configs/lx2162aqds_tfa_verified_boot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/lx2162aqds_tfa_verified_boot_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_GIC_V3_ITS=y + CONFIG_TARGET_LX2162AQDS=y + CONFIG_TFABOOT=y +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x500000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" + CONFIG_FSL_USE_PCA9547_MUX=y +@@ -26,8 +28,11 @@ + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_MISC_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -50,12 +55,15 @@ + CONFIG_DM=y + CONFIG_SATA_CEVA=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_MPC8XXX_GPIO=y + CONFIG_DM_I2C=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +-CONFIG_I2C_DEFAULT_BUS_NUMBER=0 + CONFIG_I2C_MUX=y + CONFIG_I2C_MUX_PCA954x=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_ESDHC=y +diff -ruN u-boot-2021.10/configs/M5208EVBE_defconfig u-boot/configs/M5208EVBE_defconfig +--- u-boot-2021.10/configs/M5208EVBE_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5208EVBE_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x0 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE" + CONFIG_TARGET_M5208EVBE=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +@@ -17,6 +19,11 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0x2000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_PROTECTION=y +diff -ruN u-boot-2021.10/configs/M5235EVB_defconfig u-boot/configs/M5235EVB_defconfig +--- u-boot-2021.10/configs/M5235EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5235EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5235EVB" + CONFIG_TARGET_M5235EVB=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +@@ -22,6 +24,11 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xFFE04000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x300 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_PROTECTION=y +diff -ruN u-boot-2021.10/configs/M5235EVB_Flash32_defconfig u-boot/configs/M5235EVB_Flash32_defconfig +--- u-boot-2021.10/configs/M5235EVB_Flash32_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5235EVB_Flash32_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFC00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32" + CONFIG_TARGET_M5235EVB=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -22,6 +24,11 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xFFE04000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x300 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_PROTECTION=y +diff -ruN u-boot-2021.10/configs/M5249EVB_defconfig u-boot/configs/M5249EVB_defconfig +--- u-boot-2021.10/configs/M5249EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5249EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" + CONFIG_TARGET_M5249EVB=y ++CONFIG_SYS_LOAD_ADDR=0x200000 + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_SYS_DEVICE_NULLDEV=y +diff -ruN u-boot-2021.10/configs/M5253DEMO_defconfig u-boot/configs/M5253DEMO_defconfig +--- u-boot-2021.10/configs/M5253DEMO_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5253DEMO_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFF800000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO" + CONFIG_TARGET_M5253DEMO=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +@@ -18,4 +20,9 @@ + CONFIG_MAC_PARTITION=y + CONFIG_ENV_ADDR=0xFF804000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x280 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/M5272C3_defconfig u-boot/configs/M5272C3_defconfig +--- u-boot-2021.10/configs/M5272C3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5272C3_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="M5272C3" + CONFIG_TARGET_M5272C3=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +diff -ruN u-boot-2021.10/configs/M5275EVB_defconfig u-boot/configs/M5275EVB_defconfig +--- u-boot-2021.10/configs/M5275EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5275EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="M5275EVB" + CONFIG_TARGET_M5275EVB=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +@@ -20,6 +22,11 @@ + CONFIG_CMD_CACHE=y + CONFIG_ENV_ADDR=0xFFE04000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x300 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_CFI=y +diff -ruN u-boot-2021.10/configs/M5282EVB_defconfig u-boot/configs/M5282EVB_defconfig +--- u-boot-2021.10/configs/M5282EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5282EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xFFE00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="M5282EVB" + CONFIG_TARGET_M5282EVB=y ++CONFIG_SYS_LOAD_ADDR=0x20000 + CONFIG_BOOTDELAY=5 + # CONFIG_DISPLAY_BOARDINFO is not set + # CONFIG_CMDLINE_EDITING is not set +diff -ruN u-boot-2021.10/configs/M53017EVB_defconfig u-boot/configs/M53017EVB_defconfig +--- u-boot-2021.10/configs/M53017EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M53017EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x0 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_SECT_SIZE=0x8000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M53017EVB" + CONFIG_TARGET_M53017EVB=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2" +@@ -19,6 +21,11 @@ + CONFIG_CMD_DATE=y + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0x40000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +diff -ruN u-boot-2021.10/configs/M5329AFEE_defconfig u-boot/configs/M5329AFEE_defconfig +--- u-boot-2021.10/configs/M5329AFEE_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5329AFEE_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x0 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE" + CONFIG_TARGET_M5329EVB=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -20,6 +22,11 @@ + CONFIG_CMD_DATE=y + CONFIG_ENV_ADDR=0x4000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/M5329BFEE_defconfig u-boot/configs/M5329BFEE_defconfig +--- u-boot-2021.10/configs/M5329BFEE_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5329BFEE_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x0 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE" + CONFIG_TARGET_M5329EVB=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -20,6 +22,11 @@ + CONFIG_CMD_DATE=y + CONFIG_ENV_ADDR=0x4000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/M5373EVB_defconfig u-boot/configs/M5373EVB_defconfig +--- u-boot-2021.10/configs/M5373EVB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/M5373EVB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x0 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="M5373EVB" + CONFIG_TARGET_M5373EVB=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" + CONFIG_BOOTDELAY=1 + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -20,6 +22,11 @@ + CONFIG_CMD_DATE=y + CONFIG_ENV_ADDR=0x4000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x58000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=80000 + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/m53menlo_defconfig u-boot/configs/m53menlo_defconfig +--- u-boot-2021.10/configs/m53menlo_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/m53menlo_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,19 +9,23 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_TARGET_M53MENLO=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo" + CONFIG_SPL_TEXT_BASE=0x70008000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C + CONFIG_SPL=y + CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y + CONFIG_ENV_OFFSET_REDUND=0x180000 + # CONFIG_CMD_BMODE is not set ++CONFIG_SYS_LOAD_ADDR=0x70800000 + CONFIG_FIT=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttymxc0,115200" +@@ -66,11 +70,20 @@ + CONFIG_DM=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_MXC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000 + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y + CONFIG_PHY_MICREL_KSZ8XXX=y +diff -ruN u-boot-2021.10/configs/malta64_defconfig u-boot/configs/malta64_defconfig +--- u-boot-2021.10/configs/malta64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/malta64_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -2,9 +2,11 @@ + CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="mti,malta" + CONFIG_TARGET_MALTA=y + CONFIG_CPU_MIPS64_R2=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 + # CONFIG_AUTOBOOT is not set + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/malta64el_defconfig u-boot/configs/malta64el_defconfig +--- u-boot-2021.10/configs/malta64el_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/malta64el_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -2,11 +2,13 @@ + CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="mti,malta" + CONFIG_TARGET_MALTA=y + CONFIG_BUILD_TARGET="u-boot-swap.bin" + CONFIG_SYS_LITTLE_ENDIAN=y + CONFIG_CPU_MIPS64_R2=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 + # CONFIG_AUTOBOOT is not set + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/malta_defconfig u-boot/configs/malta_defconfig +--- u-boot-2021.10/configs/malta_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/malta_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0xBE000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="mti,malta" + CONFIG_TARGET_MALTA=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + # CONFIG_AUTOBOOT is not set + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/maltael_defconfig u-boot/configs/maltael_defconfig +--- u-boot-2021.10/configs/maltael_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/maltael_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -2,10 +2,12 @@ + CONFIG_SYS_TEXT_BASE=0xBE000000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="mti,malta" + CONFIG_TARGET_MALTA=y + CONFIG_BUILD_TARGET="u-boot-swap.bin" + CONFIG_SYS_LITTLE_ENDIAN=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + # CONFIG_AUTOBOOT is not set + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/Marsboard_A10_defconfig u-boot/configs/Marsboard_A10_defconfig +--- u-boot-2021.10/configs/Marsboard_A10_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Marsboard_A10_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,9 +6,13 @@ + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_SUNXI_NO_PMIC=y + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/marsboard_defconfig u-boot/configs/marsboard_defconfig +--- u-boot-2021.10/configs/marsboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/marsboard_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,12 +5,16 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" + CONFIG_MX6Q=y + CONFIG_TARGET_EMBESTMX6BOARDS=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard" + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" + CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -29,6 +33,9 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 +diff -ruN u-boot-2021.10/configs/maxbcm_defconfig u-boot/configs/maxbcm_defconfig +--- u-boot-2021.10/configs/maxbcm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/maxbcm_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -12,11 +12,12 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" + CONFIG_SPL_TEXT_BASE=0x40004030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +@@ -36,6 +37,10 @@ + CONFIG_ENV_SPI_MAX_HZ=50000000 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_OF_TRANSLATE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + # CONFIG_MMC is not set + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/mccmon6_nor_defconfig u-boot/configs/mccmon6_nor_defconfig +--- u-boot-2021.10/configs/mccmon6_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mccmon6_nor_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,20 +6,19 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_nor.cfg" + CONFIG_MX6QDL=y + CONFIG_TARGET_MCCMON6=y +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg" + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/mccmon6_sd_defconfig u-boot/configs/mccmon6_sd_defconfig +--- u-boot-2021.10/configs/mccmon6_sd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mccmon6_sd_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,21 +6,20 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_IMX_CONFIG="board/liebherr/mccmon6/mon6_imximage_sd.cfg" + CONFIG_MX6QDL=y + CONFIG_TARGET_MCCMON6=y +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-mccmon6" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg" + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/MCR3000_defconfig u-boot/configs/MCR3000_defconfig +--- u-boot-2021.10/configs/MCR3000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MCR3000_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -40,6 +40,7 @@ + CONFIG_SYS_BR7_PRELIM_BOOL=y + CONFIG_SYS_BR7_PRELIM=0x1C000001 + CONFIG_SYS_OR7_PRELIM=0xFFFF810A ++CONFIG_SYS_LOAD_ADDR=0x200000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTDELAY=5 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/medcom-wide_defconfig u-boot/configs/medcom-wide_defconfig +--- u-boot-2021.10/configs/medcom-wide_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/medcom-wide_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_MEDCOM_WIDE=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_STDIO_DEREGISTER=y +@@ -31,6 +32,7 @@ + CONFIG_SPL_DM=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_PMIC=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/meerkat96_defconfig u-boot/configs/meerkat96_defconfig +--- u-boot-2021.10/configs/meerkat96_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/meerkat96_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96" + CONFIG_TARGET_MEERKAT96=y +@@ -13,7 +14,6 @@ + # CONFIG_ARMV7_VIRT is not set + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg" + CONFIG_HUSH_PARSER=y + # CONFIG_CMD_BOOTD is not set + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/meesc_dataflash_defconfig u-boot/configs/meesc_dataflash_defconfig +--- u-boot-2021.10/configs/meesc_dataflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/meesc_dataflash_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -8,8 +9,10 @@ + CONFIG_ENV_SIZE=0x4200 + CONFIG_ENV_OFFSET=0x4200 + CONFIG_ENV_SECT_SIZE=0x210 ++CONFIG_SYS_MALLOC_LEN=0x2d000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" ++CONFIG_SYS_LOAD_ADDR=0x20100000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/meesc_defconfig u-boot/configs/meesc_defconfig +--- u-boot-2021.10/configs/meesc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/meesc_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21F00000 +@@ -6,8 +7,10 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" ++CONFIG_SYS_LOAD_ADDR=0x20100000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/Mele_A1000_defconfig u-boot/configs/Mele_A1000_defconfig +--- u-boot-2021.10/configs/Mele_A1000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_A1000_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,8 +10,12 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_MII=y + CONFIG_SUN4I_EMAC=y + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Mele_A1000G_quad_defconfig u-boot/configs/Mele_A1000G_quad_defconfig +--- u-boot-2021.10/configs/Mele_A1000G_quad_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_A1000G_quad_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,7 @@ + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_ZQ=120 + CONFIG_INITIAL_USB_SCAN_DELAY=2000 +-CONFIG_USB1_VBUS_PIN="PC27" +-CONFIG_USB2_VBUS_PIN="" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/Mele_I7_defconfig u-boot/configs/Mele_I7_defconfig +--- u-boot-2021.10/configs/Mele_I7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_I7_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,8 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_ZQ=120 +-CONFIG_USB1_VBUS_PIN="PC27" +-CONFIG_USB2_VBUS_PIN="" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/Mele_M3_defconfig u-boot/configs/Mele_M3_defconfig +--- u-boot-2021.10/configs/Mele_M3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_M3_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -10,9 +10,13 @@ + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y + CONFIG_SUN7I_GMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Mele_M5_defconfig u-boot/configs/Mele_M5_defconfig +--- u-boot-2021.10/configs/Mele_M5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_M5_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -11,6 +11,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_MII=y +@@ -18,3 +21,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Mele_M9_defconfig u-boot/configs/Mele_M9_defconfig +--- u-boot-2021.10/configs/Mele_M9_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mele_M9_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,8 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_ZQ=120 +-CONFIG_USB1_VBUS_PIN="PC27" +-CONFIG_USB2_VBUS_PIN="" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/Merrii_A80_Optimus_defconfig u-boot/configs/Merrii_A80_Optimus_defconfig +--- u-boot-2021.10/configs/Merrii_A80_Optimus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Merrii_A80_Optimus_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,10 +6,8 @@ + CONFIG_DRAM_CLK=672 + CONFIG_MMC0_CD_PIN="PH18" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH3" +-CONFIG_USB1_VBUS_PIN="PH4" +-CONFIG_USB3_VBUS_PIN="PH5" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + CONFIG_AXP809_POWER=y +diff -ruN u-boot-2021.10/configs/microblaze-generic_defconfig u-boot/configs/microblaze-generic_defconfig +--- u-boot-2021.10/configs/microblaze-generic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/microblaze-generic_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -4,8 +4,9 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0xc0000 + CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_TARGET_MICROBLAZE_GENERIC=y + CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 +@@ -13,6 +14,7 @@ + CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 + CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=-1 +diff -ruN u-boot-2021.10/configs/microchip_mpfs_icicle_defconfig u-boot/configs/microchip_mpfs_icicle_defconfig +--- u-boot-2021.10/configs/microchip_mpfs_icicle_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/microchip_mpfs_icicle_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,12 +1,14 @@ + CONFIG_RISCV=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" + CONFIG_TARGET_MICROCHIP_ICICLE=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_SBI_V01=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y +diff -ruN u-boot-2021.10/configs/Mini-X_defconfig u-boot/configs/Mini-X_defconfig +--- u-boot-2021.10/configs/Mini-X_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Mini-X_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -3,10 +3,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y +-CONFIG_USB0_VBUS_PIN="PB9" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/miqi-rk3288_defconfig u-boot/configs/miqi-rk3288_defconfig +--- u-boot-2021.10/configs/miqi-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/miqi-rk3288_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" +diff -ruN u-boot-2021.10/configs/mixtile_loftq_defconfig u-boot/configs/mixtile_loftq_defconfig +--- u-boot-2021.10/configs/mixtile_loftq_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mixtile_loftq_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,8 +6,7 @@ + CONFIG_DRAM_ZQ=251 + CONFIG_MACPWR="PA21" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB1_VBUS_PIN="PH24" +-CONFIG_USB2_VBUS_PIN="" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +diff -ruN u-boot-2021.10/configs/mk802_a10s_defconfig u-boot/configs/mk802_a10s_defconfig +--- u-boot-2021.10/configs/mk802_a10s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mk802_a10s_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,9 +5,12 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_EMR1=0 +-CONFIG_USB1_VBUS_PIN="PB10" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP152_POWER=y + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/mk802_defconfig u-boot/configs/mk802_defconfig +--- u-boot-2021.10/configs/mk802_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mk802_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -3,8 +3,11 @@ + CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y +-CONFIG_USB2_VBUS_PIN="PH12" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_SUNXI_NO_PMIC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y +diff -ruN u-boot-2021.10/configs/mk802ii_defconfig u-boot/configs/mk802ii_defconfig +--- u-boot-2021.10/configs/mk802ii_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mk802ii_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,5 +5,9 @@ + CONFIG_MACH_SUN4I=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/MK808C_defconfig u-boot/configs/MK808C_defconfig +--- u-boot-2021.10/configs/MK808C_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MK808C_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,5 +6,9 @@ + CONFIG_DRAM_CLK=384 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/MPC8349EMDS_defconfig u-boot/configs/MPC8349EMDS_defconfig +--- u-boot-2021.10/configs/MPC8349EMDS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8349EMDS_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,120 +0,0 @@ +-CONFIG_PPC=y +-CONFIG_SYS_TEXT_BASE=0xFE000000 +-CONFIG_ENV_SIZE=0x2000 +-CONFIG_ENV_SECT_SIZE=0x20000 +-CONFIG_SYS_CLK_FREQ=66000000 +-CONFIG_MPC83xx=y +-CONFIG_HIGH_BATS=y +-CONFIG_TARGET_MPC8349EMDS=y +-CONFIG_DDR_MC_CLOCK_MODE_1_1=y +-CONFIG_SYSTEM_PLL_FACTOR_4_1=y +-CONFIG_CORE_PLL_RATIO_2_1=y +-CONFIG_PCI_HOST_MODE_ENABLE=y +-CONFIG_PCI_INT_ARBITER1_ENABLE=y +-CONFIG_PCI_INT_ARBITER2_ENABLE=y +-CONFIG_BOOT_MEMORY_SPACE_LOW=y +-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +-CONFIG_TSEC1_MODE_GMII=y +-CONFIG_TSEC2_MODE_GMII=y +-CONFIG_BAT0=y +-CONFIG_BAT0_NAME="SDRAM" +-CONFIG_BAT0_BASE=0x00000000 +-CONFIG_BAT0_LENGTH_256_MBYTES=y +-CONFIG_BAT0_ACCESS_RW=y +-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_USER_MODE_VALID=y +-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT5=y +-CONFIG_BAT5_NAME="IMMR" +-CONFIG_BAT5_BASE=0xE0000000 +-CONFIG_BAT5_LENGTH_256_MBYTES=y +-CONFIG_BAT5_ACCESS_RW=y +-CONFIG_BAT5_ICACHE_INHIBITED=y +-CONFIG_BAT5_ICACHE_GUARDED=y +-CONFIG_BAT5_DCACHE_INHIBITED=y +-CONFIG_BAT5_DCACHE_GUARDED=y +-CONFIG_BAT5_USER_MODE_VALID=y +-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT6=y +-CONFIG_BAT6_NAME="STACK_IN_DCACHE" +-CONFIG_BAT6_BASE=0xF0000000 +-CONFIG_BAT6_LENGTH_256_MBYTES=y +-CONFIG_BAT6_ACCESS_RW=y +-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_ICACHE_GUARDED=y +-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_DCACHE_GUARDED=y +-CONFIG_BAT6_USER_MODE_VALID=y +-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +-CONFIG_LBLAW0=y +-CONFIG_LBLAW0_BASE=0xFE000000 +-CONFIG_LBLAW0_NAME="FLASH" +-CONFIG_LBLAW0_LENGTH_32_MBYTES=y +-CONFIG_LBLAW1=y +-CONFIG_LBLAW1_BASE=0xE2400000 +-CONFIG_LBLAW1_NAME="BCSR" +-CONFIG_LBLAW1_LENGTH_32_KBYTES=y +-CONFIG_ELBC_BR0_OR0=y +-CONFIG_BR0_OR0_NAME="FLASH" +-CONFIG_BR0_OR0_BASE=0xFE000000 +-CONFIG_BR0_PORTSIZE_16BIT=y +-CONFIG_OR0_AM_32_MBYTES=y +-CONFIG_OR0_XAM_SET=y +-CONFIG_OR0_SCY_15=y +-CONFIG_OR0_CSNT_EARLIER=y +-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +-CONFIG_OR0_XACS_EXTENDED=y +-CONFIG_OR0_TRLX_RELAXED=y +-CONFIG_OR0_EHTR_8_CYCLE=y +-CONFIG_OR0_EAD_EXTRA=y +-CONFIG_ELBC_BR1_OR1=y +-CONFIG_BR1_OR1_NAME="BCSR" +-CONFIG_BR1_OR1_BASE=0xE2400000 +-CONFIG_OR1_XAM_SET=y +-CONFIG_OR1_SCY_15=y +-CONFIG_OR1_CSNT_EARLIER=y +-CONFIG_HID0_FINAL_EMCP=y +-CONFIG_HID0_FINAL_ICE=y +-CONFIG_HID2_HBE=y +-CONFIG_ACR_PIPE_DEP_4=y +-CONFIG_ACR_RPTCNT_4=y +-CONFIG_SPCR_TSEC1EP_3=y +-CONFIG_SPCR_TSEC2EP_3=y +-CONFIG_LCRR_DBYP_PLL_BYPASSED=y +-CONFIG_LCRR_CLKDIV_4=y +-CONFIG_PCI_ONE_PCI1=y +-CONFIG_OF_BOARD_SETUP=y +-CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_BOOTDELAY=6 +-CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +-CONFIG_HUSH_PARSER=y +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_I2C=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_DATE=y +-CONFIG_ENV_OVERWRITE=y +-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +-CONFIG_ENV_ADDR=0xFE080000 +-CONFIG_ENV_ADDR_REDUND=0xFE0A0000 +-# CONFIG_MMC is not set +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_PROTECTION=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_PHY_ATHEROS=y +-CONFIG_PHY_BROADCOM=y +-CONFIG_PHY_DAVICOM=y +-CONFIG_PHY_LXT=y +-CONFIG_PHY_MARVELL=y +-CONFIG_PHY_NATSEMI=y +-CONFIG_PHY_REALTEK=y +-CONFIG_PHY_SMSC=y +-CONFIG_PHY_VITESSE=y +-CONFIG_TSEC_ENET=y +-CONFIG_SYS_NS16550=y +-CONFIG_SPI=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/MPC8349EMDS_PCI64_defconfig u-boot/configs/MPC8349EMDS_PCI64_defconfig +--- u-boot-2021.10/configs/MPC8349EMDS_PCI64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8349EMDS_PCI64_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,117 +0,0 @@ +-CONFIG_PPC=y +-CONFIG_SYS_TEXT_BASE=0xFE000000 +-CONFIG_ENV_SIZE=0x2000 +-CONFIG_ENV_SECT_SIZE=0x20000 +-CONFIG_SYS_CLK_FREQ=66000000 +-CONFIG_MPC83xx=y +-CONFIG_HIGH_BATS=y +-CONFIG_TARGET_MPC8349EMDS=y +-CONFIG_DDR_MC_CLOCK_MODE_1_1=y +-CONFIG_SYSTEM_PLL_FACTOR_4_1=y +-CONFIG_CORE_PLL_RATIO_2_1=y +-CONFIG_PCI_HOST_MODE_ENABLE=y +-CONFIG_PCI_64BIT_MODE_ENABLE=y +-CONFIG_PCI_INT_ARBITER1_ENABLE=y +-CONFIG_BOOT_MEMORY_SPACE_LOW=y +-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +-CONFIG_TSEC1_MODE_GMII=y +-CONFIG_TSEC2_MODE_GMII=y +-CONFIG_BAT0=y +-CONFIG_BAT0_NAME="SDRAM" +-CONFIG_BAT0_BASE=0x00000000 +-CONFIG_BAT0_LENGTH_256_MBYTES=y +-CONFIG_BAT0_ACCESS_RW=y +-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_USER_MODE_VALID=y +-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT5=y +-CONFIG_BAT5_NAME="IMMR" +-CONFIG_BAT5_BASE=0xE0000000 +-CONFIG_BAT5_LENGTH_256_MBYTES=y +-CONFIG_BAT5_ACCESS_RW=y +-CONFIG_BAT5_ICACHE_INHIBITED=y +-CONFIG_BAT5_ICACHE_GUARDED=y +-CONFIG_BAT5_DCACHE_INHIBITED=y +-CONFIG_BAT5_DCACHE_GUARDED=y +-CONFIG_BAT5_USER_MODE_VALID=y +-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT6=y +-CONFIG_BAT6_NAME="STACK_IN_DCACHE" +-CONFIG_BAT6_BASE=0xF0000000 +-CONFIG_BAT6_LENGTH_256_MBYTES=y +-CONFIG_BAT6_ACCESS_RW=y +-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_ICACHE_GUARDED=y +-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_DCACHE_GUARDED=y +-CONFIG_BAT6_USER_MODE_VALID=y +-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +-CONFIG_LBLAW0=y +-CONFIG_LBLAW0_BASE=0xFE000000 +-CONFIG_LBLAW0_NAME="FLASH" +-CONFIG_LBLAW0_LENGTH_32_MBYTES=y +-CONFIG_LBLAW1=y +-CONFIG_LBLAW1_BASE=0xE2400000 +-CONFIG_LBLAW1_NAME="BCSR" +-CONFIG_LBLAW1_LENGTH_32_KBYTES=y +-CONFIG_ELBC_BR0_OR0=y +-CONFIG_BR0_OR0_NAME="FLASH" +-CONFIG_BR0_OR0_BASE=0xFE000000 +-CONFIG_BR0_PORTSIZE_16BIT=y +-CONFIG_OR0_AM_32_MBYTES=y +-CONFIG_OR0_XAM_SET=y +-CONFIG_OR0_SCY_15=y +-CONFIG_OR0_CSNT_EARLIER=y +-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +-CONFIG_OR0_XACS_EXTENDED=y +-CONFIG_OR0_TRLX_RELAXED=y +-CONFIG_OR0_EHTR_8_CYCLE=y +-CONFIG_OR0_EAD_EXTRA=y +-CONFIG_ELBC_BR1_OR1=y +-CONFIG_BR1_OR1_NAME="BCSR" +-CONFIG_BR1_OR1_BASE=0xE2400000 +-CONFIG_OR1_XAM_SET=y +-CONFIG_OR1_SCY_15=y +-CONFIG_OR1_CSNT_EARLIER=y +-CONFIG_HID0_FINAL_EMCP=y +-CONFIG_HID0_FINAL_ICE=y +-CONFIG_HID2_HBE=y +-CONFIG_ACR_PIPE_DEP_4=y +-CONFIG_ACR_RPTCNT_4=y +-CONFIG_SPCR_TSEC1EP_3=y +-CONFIG_SPCR_TSEC2EP_3=y +-CONFIG_LCRR_DBYP_PLL_BYPASSED=y +-CONFIG_LCRR_CLKDIV_4=y +-CONFIG_OF_BOARD_SETUP=y +-CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_BOOTDELAY=6 +-CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +-CONFIG_HUSH_PARSER=y +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_I2C=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_DATE=y +-CONFIG_ENV_OVERWRITE=y +-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +-CONFIG_ENV_ADDR=0xFE080000 +-CONFIG_ENV_ADDR_REDUND=0xFE0A0000 +-# CONFIG_MMC is not set +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_PHY_ATHEROS=y +-CONFIG_PHY_BROADCOM=y +-CONFIG_PHY_DAVICOM=y +-CONFIG_PHY_LXT=y +-CONFIG_PHY_NATSEMI=y +-CONFIG_PHY_REALTEK=y +-CONFIG_PHY_SMSC=y +-CONFIG_PHY_VITESSE=y +-CONFIG_TSEC_ENET=y +-CONFIG_SYS_NS16550=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/MPC8349EMDS_SDRAM_defconfig u-boot/configs/MPC8349EMDS_SDRAM_defconfig +--- u-boot-2021.10/configs/MPC8349EMDS_SDRAM_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8349EMDS_SDRAM_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,128 +0,0 @@ +-CONFIG_PPC=y +-CONFIG_SYS_TEXT_BASE=0xFE000000 +-CONFIG_ENV_SIZE=0x2000 +-CONFIG_ENV_SECT_SIZE=0x20000 +-CONFIG_SYS_CLK_FREQ=66000000 +-CONFIG_MPC83xx=y +-CONFIG_HIGH_BATS=y +-CONFIG_TARGET_MPC8349EMDS_SDRAM=y +-CONFIG_DDR_MC_CLOCK_MODE_1_1=y +-CONFIG_SYSTEM_PLL_FACTOR_4_1=y +-CONFIG_CORE_PLL_RATIO_2_1=y +-CONFIG_PCI_HOST_MODE_ENABLE=y +-CONFIG_PCI_INT_ARBITER1_ENABLE=y +-CONFIG_PCI_INT_ARBITER2_ENABLE=y +-CONFIG_BOOT_MEMORY_SPACE_LOW=y +-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +-CONFIG_TSEC1_MODE_GMII=y +-CONFIG_TSEC2_MODE_GMII=y +-CONFIG_BAT0=y +-CONFIG_BAT0_NAME="SDRAM" +-CONFIG_BAT0_BASE=0x00000000 +-CONFIG_BAT0_LENGTH_256_MBYTES=y +-CONFIG_BAT0_ACCESS_RW=y +-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_USER_MODE_VALID=y +-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT5=y +-CONFIG_BAT5_NAME="IMMR" +-CONFIG_BAT5_BASE=0xE0000000 +-CONFIG_BAT5_LENGTH_256_MBYTES=y +-CONFIG_BAT5_ACCESS_RW=y +-CONFIG_BAT5_ICACHE_INHIBITED=y +-CONFIG_BAT5_ICACHE_GUARDED=y +-CONFIG_BAT5_DCACHE_INHIBITED=y +-CONFIG_BAT5_DCACHE_GUARDED=y +-CONFIG_BAT5_USER_MODE_VALID=y +-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT6=y +-CONFIG_BAT6_NAME="STACK_IN_DCACHE" +-CONFIG_BAT6_BASE=0xF0000000 +-CONFIG_BAT6_LENGTH_256_MBYTES=y +-CONFIG_BAT6_ACCESS_RW=y +-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_ICACHE_GUARDED=y +-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_DCACHE_GUARDED=y +-CONFIG_BAT6_USER_MODE_VALID=y +-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +-CONFIG_LBLAW0=y +-CONFIG_LBLAW0_BASE=0xFE000000 +-CONFIG_LBLAW0_NAME="FLASH" +-CONFIG_LBLAW0_LENGTH_32_MBYTES=y +-CONFIG_LBLAW1=y +-CONFIG_LBLAW1_BASE=0xE2400000 +-CONFIG_LBLAW1_NAME="BCSR" +-CONFIG_LBLAW1_LENGTH_32_KBYTES=y +-CONFIG_LBLAW2=y +-CONFIG_LBLAW2_BASE=0xF0000000 +-CONFIG_LBLAW2_NAME="SDRAM" +-CONFIG_LBLAW2_LENGTH_64_MBYTES=y +-CONFIG_ELBC_BR0_OR0=y +-CONFIG_BR0_OR0_NAME="FLASH" +-CONFIG_BR0_OR0_BASE=0xFE000000 +-CONFIG_BR0_PORTSIZE_16BIT=y +-CONFIG_OR0_AM_32_MBYTES=y +-CONFIG_OR0_XAM_SET=y +-CONFIG_OR0_SCY_15=y +-CONFIG_OR0_CSNT_EARLIER=y +-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +-CONFIG_OR0_XACS_EXTENDED=y +-CONFIG_OR0_TRLX_RELAXED=y +-CONFIG_OR0_EHTR_8_CYCLE=y +-CONFIG_OR0_EAD_EXTRA=y +-CONFIG_ELBC_BR1_OR1=y +-CONFIG_BR1_OR1_NAME="BCSR" +-CONFIG_BR1_OR1_BASE=0xE2400000 +-CONFIG_OR1_XAM_SET=y +-CONFIG_OR1_SCY_15=y +-CONFIG_OR1_CSNT_EARLIER=y +-CONFIG_ELBC_BR2_OR2=y +-CONFIG_BR2_OR2_NAME="SDRAM" +-CONFIG_BR2_OR2_BASE=0xF0000000 +-CONFIG_BR2_PORTSIZE_32BIT=y +-CONFIG_BR2_MACHINE_SDRAM=y +-CONFIG_OR2_COLS_9=y +-CONFIG_OR2_ROWS_13=y +-CONFIG_OR2_EAD_EXTRA=y +-CONFIG_HID0_FINAL_EMCP=y +-CONFIG_HID0_FINAL_ICE=y +-CONFIG_HID2_HBE=y +-CONFIG_ACR_PIPE_DEP_4=y +-CONFIG_ACR_RPTCNT_4=y +-CONFIG_LCRR_DBYP_PLL_BYPASSED=y +-CONFIG_LCRR_CLKDIV_4=y +-CONFIG_PCI_ONE_PCI1=y +-CONFIG_OF_BOARD_SETUP=y +-CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_BOOTDELAY=6 +-CONFIG_HUSH_PARSER=y +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_I2C=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_DATE=y +-CONFIG_ENV_OVERWRITE=y +-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +-CONFIG_ENV_ADDR=0xFE080000 +-CONFIG_ENV_ADDR_REDUND=0xFE0A0000 +-# CONFIG_MMC is not set +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_PHY_ATHEROS=y +-CONFIG_PHY_BROADCOM=y +-CONFIG_PHY_DAVICOM=y +-CONFIG_PHY_LXT=y +-CONFIG_PHY_MARVELL=y +-CONFIG_PHY_NATSEMI=y +-CONFIG_PHY_REALTEK=y +-CONFIG_PHY_SMSC=y +-CONFIG_PHY_VITESSE=y +-CONFIG_TSEC_ENET=y +-CONFIG_SYS_NS16550=y +-CONFIG_SPI=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/MPC8349EMDS_SLAVE_defconfig u-boot/configs/MPC8349EMDS_SLAVE_defconfig +--- u-boot-2021.10/configs/MPC8349EMDS_SLAVE_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8349EMDS_SLAVE_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,117 +0,0 @@ +-CONFIG_PPC=y +-CONFIG_SYS_TEXT_BASE=0xFE000000 +-CONFIG_ENV_SIZE=0x2000 +-CONFIG_ENV_SECT_SIZE=0x20000 +-CONFIG_SYS_CLK_FREQ=66666666 +-CONFIG_MPC83xx=y +-CONFIG_HIGH_BATS=y +-CONFIG_TARGET_MPC8349EMDS=y +-CONFIG_DDR_MC_CLOCK_MODE_1_1=y +-CONFIG_SYSTEM_PLL_FACTOR_4_1=y +-CONFIG_CORE_PLL_RATIO_2_1=y +-CONFIG_PCI_64BIT_MODE_ENABLE=y +-CONFIG_BOOT_MEMORY_SPACE_LOW=y +-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +-CONFIG_TSEC1_MODE_GMII=y +-CONFIG_TSEC2_MODE_GMII=y +-CONFIG_BAT0=y +-CONFIG_BAT0_NAME="SDRAM" +-CONFIG_BAT0_BASE=0x00000000 +-CONFIG_BAT0_LENGTH_256_MBYTES=y +-CONFIG_BAT0_ACCESS_RW=y +-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT0_USER_MODE_VALID=y +-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT5=y +-CONFIG_BAT5_NAME="IMMR" +-CONFIG_BAT5_BASE=0xE0000000 +-CONFIG_BAT5_LENGTH_256_MBYTES=y +-CONFIG_BAT5_ACCESS_RW=y +-CONFIG_BAT5_ICACHE_INHIBITED=y +-CONFIG_BAT5_ICACHE_GUARDED=y +-CONFIG_BAT5_DCACHE_INHIBITED=y +-CONFIG_BAT5_DCACHE_GUARDED=y +-CONFIG_BAT5_USER_MODE_VALID=y +-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +-CONFIG_BAT6=y +-CONFIG_BAT6_NAME="STACK_IN_DCACHE" +-CONFIG_BAT6_BASE=0xF0000000 +-CONFIG_BAT6_LENGTH_256_MBYTES=y +-CONFIG_BAT6_ACCESS_RW=y +-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_ICACHE_GUARDED=y +-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +-CONFIG_BAT6_DCACHE_GUARDED=y +-CONFIG_BAT6_USER_MODE_VALID=y +-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +-CONFIG_LBLAW0=y +-CONFIG_LBLAW0_BASE=0xFE000000 +-CONFIG_LBLAW0_NAME="FLASH" +-CONFIG_LBLAW0_LENGTH_32_MBYTES=y +-CONFIG_LBLAW1=y +-CONFIG_LBLAW1_BASE=0xE2400000 +-CONFIG_LBLAW1_NAME="BCSR" +-CONFIG_LBLAW1_LENGTH_32_KBYTES=y +-CONFIG_ELBC_BR0_OR0=y +-CONFIG_BR0_OR0_NAME="FLASH" +-CONFIG_BR0_OR0_BASE=0xFE000000 +-CONFIG_BR0_PORTSIZE_16BIT=y +-CONFIG_OR0_AM_32_MBYTES=y +-CONFIG_OR0_XAM_SET=y +-CONFIG_OR0_SCY_15=y +-CONFIG_OR0_CSNT_EARLIER=y +-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +-CONFIG_OR0_XACS_EXTENDED=y +-CONFIG_OR0_TRLX_RELAXED=y +-CONFIG_OR0_EHTR_8_CYCLE=y +-CONFIG_OR0_EAD_EXTRA=y +-CONFIG_ELBC_BR1_OR1=y +-CONFIG_BR1_OR1_NAME="BCSR" +-CONFIG_BR1_OR1_BASE=0xE2400000 +-CONFIG_OR1_XAM_SET=y +-CONFIG_OR1_SCY_15=y +-CONFIG_OR1_CSNT_EARLIER=y +-CONFIG_HID0_FINAL_EMCP=y +-CONFIG_HID0_FINAL_ICE=y +-CONFIG_HID2_HBE=y +-CONFIG_ACR_PIPE_DEP_4=y +-CONFIG_ACR_RPTCNT_4=y +-CONFIG_SPCR_TSEC1EP_3=y +-CONFIG_SPCR_TSEC2EP_3=y +-CONFIG_LCRR_DBYP_PLL_BYPASSED=y +-CONFIG_LCRR_CLKDIV_4=y +-CONFIG_PCI_ONE_PCI1=y +-CONFIG_OF_BOARD_SETUP=y +-CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +-CONFIG_BOOTDELAY=6 +-CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +-CONFIG_HUSH_PARSER=y +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_I2C=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_DATE=y +-CONFIG_ENV_OVERWRITE=y +-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +-CONFIG_ENV_ADDR=0xFE080000 +-CONFIG_ENV_ADDR_REDUND=0xFE0A0000 +-# CONFIG_MMC is not set +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_PHY_ATHEROS=y +-CONFIG_PHY_BROADCOM=y +-CONFIG_PHY_DAVICOM=y +-CONFIG_PHY_LXT=y +-CONFIG_PHY_NATSEMI=y +-CONFIG_PHY_REALTEK=y +-CONFIG_PHY_SMSC=y +-CONFIG_PHY_VITESSE=y +-CONFIG_TSEC_ENET=y +-CONFIG_SYS_NS16550=y +-CONFIG_OF_LIBFDT=y +diff -ruN u-boot-2021.10/configs/MPC837XERDB_defconfig u-boot/configs/MPC837XERDB_defconfig +--- u-boot-2021.10/configs/MPC837XERDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC837XERDB_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFE000000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" + CONFIG_SYS_CLK_FREQ=66666667 + CONFIG_MPC83xx=y +@@ -168,6 +169,11 @@ + CONFIG_ENV_ADDR=0xFE080000 + CONFIG_DM=y + CONFIG_FSL_SATA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_FSL_ESDHC=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/MPC8548CDS_36BIT_defconfig u-boot/configs/MPC8548CDS_36BIT_defconfig +--- u-boot-2021.10/configs/MPC8548CDS_36BIT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8548CDS_36BIT_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF80000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -12,8 +13,10 @@ + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_BOOTDELAY=10 + # CONFIG_MISC_INIT_R is not set ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_I2C=y + CONFIG_CMD_PCI=y + CONFIG_CMD_DHCP=y +@@ -24,7 +27,12 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_ADDR=0xFFF60000 + CONFIG_DM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + # CONFIG_MMC is not set + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/MPC8548CDS_defconfig u-boot/configs/MPC8548CDS_defconfig +--- u-boot-2021.10/configs/MPC8548CDS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8548CDS_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF80000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -11,8 +12,10 @@ + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_BOOTDELAY=10 + # CONFIG_MISC_INIT_R is not set ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_I2C=y + CONFIG_CMD_PCI=y + CONFIG_CMD_DHCP=y +@@ -23,7 +26,12 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_ADDR=0xFFF60000 + CONFIG_DM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + # CONFIG_MMC is not set + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/MPC8548CDS_legacy_defconfig u-boot/configs/MPC8548CDS_legacy_defconfig +--- u-boot-2021.10/configs/MPC8548CDS_legacy_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MPC8548CDS_legacy_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF80000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -12,8 +13,10 @@ + CONFIG_SYS_EXTRA_OPTIONS="LEGACY" + CONFIG_BOOTDELAY=10 + # CONFIG_MISC_INIT_R is not set ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_I2C=y + CONFIG_CMD_PCI=y + CONFIG_CMD_MII=y +@@ -23,7 +26,12 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_ADDR=0xFFF60000 + CONFIG_DM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + # CONFIG_MMC is not set + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/mscc_jr2_defconfig u-boot/configs/mscc_jr2_defconfig +--- u-boot-2021.10/configs/mscc_jr2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mscc_jr2_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1f0000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -16,6 +17,7 @@ + CONFIG_SOC_JR2=y + CONFIG_SYS_LITTLE_ENDIAN=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/mscc_luton_defconfig u-boot/configs/mscc_luton_defconfig +--- u-boot-2021.10/configs/mscc_luton_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mscc_luton_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1f0000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -18,6 +19,7 @@ + CONFIG_SYS_LITTLE_ENDIAN=y + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/mscc_ocelot_defconfig u-boot/configs/mscc_ocelot_defconfig +--- u-boot-2021.10/configs/mscc_ocelot_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mscc_ocelot_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1f0000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -15,6 +16,7 @@ + CONFIG_ARCH_MSCC=y + CONFIG_SYS_LITTLE_ENDIAN=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/mscc_serval_defconfig u-boot/configs/mscc_serval_defconfig +--- u-boot-2021.10/configs/mscc_serval_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mscc_serval_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1f0000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="serval_pcb106" + CONFIG_ENV_OFFSET_REDUND=0x140000 +@@ -13,6 +14,7 @@ + CONFIG_SOC_SERVAL=y + CONFIG_DDRTYPE_H5TQ1G63BFA=y + CONFIG_SYS_LITTLE_ENDIAN=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/mscc_servalt_defconfig u-boot/configs/mscc_servalt_defconfig +--- u-boot-2021.10/configs/mscc_servalt_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mscc_servalt_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,12 +6,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1f0000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="servalt_pcb116" + CONFIG_ENV_OFFSET_REDUND=0x140000 + CONFIG_ARCH_MSCC=y + CONFIG_SOC_SERVALT=y + CONFIG_SYS_LITTLE_ENDIAN=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/MSI_Primo73_defconfig u-boot/configs/MSI_Primo73_defconfig +--- u-boot-2021.10/configs/MSI_Primo73_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MSI_Primo73_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -11,3 +11,7 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/MSI_Primo81_defconfig u-boot/configs/MSI_Primo81_defconfig +--- u-boot-2021.10/configs/MSI_Primo81_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/MSI_Primo81_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,8 @@ + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_CLK=360 + CONFIG_DRAM_ZQ=122 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" + CONFIG_VIDEO_LCD_BL_EN="PA25" +@@ -22,3 +22,4 @@ + CONFIG_VIDEO_LCD_SPI_SCLK="PH10" + CONFIG_VIDEO_LCD_SPI_MOSI="PH11" + CONFIG_VIDEO_LCD_SPI_MISO="PH12" ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/mt7620_mt7530_rfb_defconfig u-boot/configs/mt7620_mt7530_rfb_defconfig +--- u-boot-2021.10/configs/mt7620_mt7530_rfb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7620_mt7530_rfb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,21 +1,26 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x30000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xb0000c00 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_ARCH_MTMIPS=y + CONFIG_BOARD_MT7620_MT7530_RFB=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x80010000 + CONFIG_FIT=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_SPL_SYS_MALLOC_SIMPLE=y +diff -ruN u-boot-2021.10/configs/mt7620_rfb_defconfig u-boot/configs/mt7620_rfb_defconfig +--- u-boot-2021.10/configs/mt7620_rfb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7620_rfb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,20 +1,25 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x30000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xb0000c00 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_ARCH_MTMIPS=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x80010000 + CONFIG_FIT=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_SPL_SYS_MALLOC_SIMPLE=y +diff -ruN u-boot-2021.10/configs/mt7622_rfb_defconfig u-boot/configs/mt7622_rfb_defconfig +--- u-boot-2021.10/configs/mt7622_rfb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7622_rfb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -8,6 +8,7 @@ + CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=25000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x4007ff28 + CONFIG_FIT=y + CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" + CONFIG_LOGLEVEL=7 +diff -ruN u-boot-2021.10/configs/mt7623a_unielec_u7623_02_defconfig u-boot/configs/mt7623a_unielec_u7623_02_defconfig +--- u-boot-2021.10/configs/mt7623a_unielec_u7623_02_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7623a_unielec_u7623_02_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" + CONFIG_TARGET_MT7623=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x84000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/mt7623n_bpir2_defconfig u-boot/configs/mt7623n_bpir2_defconfig +--- u-boot-2021.10/configs/mt7623n_bpir2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7623n_bpir2_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" + CONFIG_TARGET_MT7623=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x84000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/mt7628_rfb_defconfig u-boot/configs/mt7628_rfb_defconfig +--- u-boot-2021.10/configs/mt7628_rfb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7628_rfb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -1,19 +1,24 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x30000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 + CONFIG_SPL=y + CONFIG_ARCH_MTMIPS=y + CONFIG_SOC_MT7628=y + CONFIG_BOARD_MT7628_RFB=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + CONFIG_MIPS_BOOT_FDT=y ++CONFIG_SYS_LOAD_ADDR=0x80010000 + CONFIG_FIT=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/mt7629_rfb_defconfig u-boot/configs/mt7629_rfb_defconfig +--- u-boot-2021.10/configs/mt7629_rfb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt7629_rfb_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,12 +9,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" + CONFIG_SPL_TEXT_BASE=0x201000 + CONFIG_TARGET_MT7629=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_STACK_R_ADDR=0x40800000 + CONFIG_SPL_PAYLOAD="u-boot-lzma.img" + CONFIG_BUILD_TARGET="u-boot-mtk.bin" + CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" ++CONFIG_SYS_LOAD_ADDR=0x42007f1c + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/mt8183_pumpkin_defconfig u-boot/configs/mt8183_pumpkin_defconfig +--- u-boot-2021.10/configs/mt8183_pumpkin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt8183_pumpkin_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -13,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=26000000 + # CONFIG_PSCI_RESET is not set + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x4c000000 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +@@ -60,6 +61,7 @@ + CONFIG_DM_ETH=y + CONFIG_PHY=y + CONFIG_PHY_MTK_TPHY=y ++# CONFIG_POWER is not set + CONFIG_BAUDRATE=921600 + CONFIG_DM_SERIAL=y + CONFIG_DEBUG_UART_ANNOUNCE=y +diff -ruN u-boot-2021.10/configs/mt8512_bm1_emmc_defconfig u-boot/configs/mt8512_bm1_emmc_defconfig +--- u-boot-2021.10/configs/mt8512_bm1_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt8512_bm1_emmc_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,9 +5,11 @@ + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" + CONFIG_TARGET_MT8512=y ++CONFIG_SYS_LOAD_ADDR=0x41000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" +diff -ruN u-boot-2021.10/configs/mt8516_pumpkin_defconfig u-boot/configs/mt8516_pumpkin_defconfig +--- u-boot-2021.10/configs/mt8516_pumpkin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt8516_pumpkin_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -12,6 +12,7 @@ + CONFIG_DEBUG_UART_CLOCK=26000000 + # CONFIG_PSCI_RESET is not set + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x4c000000 + CONFIG_FIT=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" +diff -ruN u-boot-2021.10/configs/mt8518_ap1_emmc_defconfig u-boot/configs/mt8518_ap1_emmc_defconfig +--- u-boot-2021.10/configs/mt8518_ap1_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mt8518_ap1_emmc_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,8 +5,10 @@ + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="mt8518-ap1-emmc" + CONFIG_TARGET_MT8518=y ++CONFIG_SYS_LOAD_ADDR=0x41000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_DEFAULT_FDT_FILE="mt8518-ap1-emmc.dtb" +diff -ruN u-boot-2021.10/configs/mvebu_crb_cn9130_defconfig u-boot/configs/mvebu_crb_cn9130_defconfig +--- u-boot-2021.10/configs/mvebu_crb_cn9130_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_crb_cn9130_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -14,6 +14,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/mvebu_db-88f3720_defconfig u-boot/configs/mvebu_db-88f3720_defconfig +--- u-boot-2021.10/configs/mvebu_db-88f3720_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_db-88f3720_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -15,6 +15,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x6000000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/mvebu_db_armada8k_defconfig u-boot/configs/mvebu_db_armada8k_defconfig +--- u-boot-2021.10/configs/mvebu_db_armada8k_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_db_armada8k_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -15,6 +15,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/mvebu_db_cn9130_defconfig u-boot/configs/mvebu_db_cn9130_defconfig +--- u-boot-2021.10/configs/mvebu_db_cn9130_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_db_cn9130_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -16,6 +16,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +@@ -54,6 +55,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_PXA3XX=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SPI_FLASH_SFDP_SUPPORT=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/mvebu_espressobin-88f3720_defconfig u-boot/configs/mvebu_espressobin-88f3720_defconfig +--- u-boot-2021.10/configs/mvebu_espressobin-88f3720_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_espressobin-88f3720_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -15,6 +15,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x6000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/mvebu_mcbin-88f8040_defconfig u-boot/configs/mvebu_mcbin-88f8040_defconfig +--- u-boot-2021.10/configs/mvebu_mcbin-88f8040_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_mcbin-88f8040_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -16,6 +16,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/mvebu_puzzle-m801-88f8040_defconfig u-boot/configs/mvebu_puzzle-m801-88f8040_defconfig +--- u-boot-2021.10/configs/mvebu_puzzle-m801-88f8040_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mvebu_puzzle-m801-88f8040_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -16,6 +16,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n" + CONFIG_AUTOBOOT_STOP_STR="s" +diff -ruN u-boot-2021.10/configs/mx23evk_defconfig u-boot/configs/mx23evk_defconfig +--- u-boot-2021.10/configs/mx23evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx23evk_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,12 +7,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_IMX_CONFIG="" + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx23-evk" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX23EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_ARCH_MISC_INIT=y +diff -ruN u-boot-2021.10/configs/mx23_olinuxino_defconfig u-boot/configs/mx23_olinuxino_defconfig +--- u-boot-2021.10/configs/mx23_olinuxino_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx23_olinuxino_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,12 +7,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_IMX_CONFIG="" + CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX23_OLINUXINO=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_BOOTDELAY=3 + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_ARCH_MISC_INIT=y +diff -ruN u-boot-2021.10/configs/mx28evk_auart_console_defconfig u-boot/configs/mx28evk_auart_console_defconfig +--- u-boot-2021.10/configs/mx28evk_auart_console_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx28evk_auart_console_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,10 +7,12 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_IMX_CONFIG="" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX28EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/mx28evk_defconfig u-boot/configs/mx28evk_defconfig +--- u-boot-2021.10/configs/mx28evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx28evk_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,12 +7,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x40000 ++CONFIG_IMX_CONFIG="" + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx28-evk" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX28EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_FIT=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/mx28evk_nand_defconfig u-boot/configs/mx28evk_nand_defconfig +--- u-boot-2021.10/configs/mx28evk_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx28evk_nand_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -7,11 +7,13 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x300000 ++CONFIG_IMX_CONFIG="" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX28EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x380000 ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_ARCH_MISC_INIT=y +diff -ruN u-boot-2021.10/configs/mx28evk_spi_defconfig u-boot/configs/mx28evk_spi_defconfig +--- u-boot-2021.10/configs/mx28evk_spi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx28evk_spi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,10 +6,12 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_IMX_CONFIG="" + CONFIG_SPL_TEXT_BASE=0x00001000 + CONFIG_TARGET_MX28EVK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_ARCH_MISC_INIT=y +diff -ruN u-boot-2021.10/configs/mx51evk_defconfig u-boot/configs/mx51evk_defconfig +--- u-boot-2021.10/configs/mx51evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx51evk_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,10 +5,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_TARGET_MX51EVK=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage" + # CONFIG_CMD_BMODE is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x92000000 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -41,6 +42,7 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX5=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y +diff -ruN u-boot-2021.10/configs/mx53cx9020_defconfig u-boot/configs/mx53cx9020_defconfig +--- u-boot-2021.10/configs/mx53cx9020_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx53cx9020_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,11 +5,12 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x60000 + CONFIG_TARGET_MX53CX9020=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x70010000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_PREBOOT=y + CONFIG_CMD_MMC=y +diff -ruN u-boot-2021.10/configs/mx53loco_defconfig u-boot/configs/mx53loco_defconfig +--- u-boot-2021.10/configs/mx53loco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx53loco_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -6,11 +6,15 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_TARGET_MX53LOCO=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb" + # CONFIG_CMD_BMODE is not set ++CONFIG_SYS_LOAD_ADDR=0x72000000 + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -32,6 +36,8 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_PHYLIB=y +@@ -42,9 +48,11 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX5=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_USB=y + CONFIG_USB_EHCI_MX5=y +diff -ruN u-boot-2021.10/configs/mx53ppd_defconfig u-boot/configs/mx53ppd_defconfig +--- u-boot-2021.10/configs/mx53ppd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx53ppd_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -5,13 +5,14 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2800 + CONFIG_TARGET_MX53PPD=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd" + CONFIG_BOOTCOUNT_BOOTLIMIT=10 ++CONFIG_SYS_LOAD_ADDR=0x72000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" + CONFIG_BOOTDELAY=1 + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +diff -ruN u-boot-2021.10/configs/mx6cuboxi_defconfig u-boot/configs/mx6cuboxi_defconfig +--- u-boot-2021.10/configs/mx6cuboxi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6cuboxi_defconfig 2021-11-01 17:10:14.186263345 +0100 +@@ -9,11 +9,12 @@ + CONFIG_ENV_OFFSET=0xFE000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6CUBOXI=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set +@@ -21,7 +22,6 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" +@@ -52,6 +52,7 @@ + CONFIG_SPL_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y + CONFIG_PHY_ATHEROS=y +diff -ruN u-boot-2021.10/configs/mx6memcal_defconfig u-boot/configs/mx6memcal_defconfig +--- u-boot-2021.10/configs/mx6memcal_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6memcal_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,11 +10,11 @@ + CONFIG_MX6QDL=y + CONFIG_MX6_DDRCAL=y + CONFIG_TARGET_MX6MEMCAL=y ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL" + CONFIG_SPL_USB_HOST=y + CONFIG_SPL_WATCHDOG=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/mx6qsabrelite_defconfig u-boot/configs/mx6qsabrelite_defconfig +--- u-boot-2021.10/configs/mx6qsabrelite_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6qsabrelite_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -7,14 +7,19 @@ + CONFIG_SYS_MEMTEST_END=0x10010000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" + CONFIG_MX6Q=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=1024 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabrelite" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024,SABRELITE" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_USE_PREBOOT=y +@@ -48,6 +53,8 @@ + CONFIG_DWC_AHSATA=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6sabreauto_defconfig u-boot/configs/mx6sabreauto_defconfig +--- u-boot-2021.10/configs/mx6sabreauto_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sabreauto_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,11 +10,15 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6SABREAUTO=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_NXP_BOARD_REVISION=y +@@ -23,7 +27,6 @@ + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -68,10 +71,14 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y + CONFIG_DFU_SF=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=20000000 +@@ -84,7 +91,9 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_SPI=y + CONFIG_DM_SPI=y +diff -ruN u-boot-2021.10/configs/mx6sabresd_defconfig u-boot/configs/mx6sabresd_defconfig +--- u-boot-2021.10/configs/mx6sabresd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sabresd_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,11 +10,15 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6QDL=y + CONFIG_TARGET_MX6SABRESD=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_FIT=y +@@ -22,7 +26,6 @@ + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -77,6 +80,9 @@ + CONFIG_FASTBOOT_BUF_SIZE=0x10000000 + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=2 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -93,8 +99,10 @@ + CONFIG_PCI=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_SPI=y + CONFIG_DM_SPI=y +diff -ruN u-boot-2021.10/configs/mx6slevk_defconfig u-boot/configs/mx6slevk_defconfig +--- u-boot-2021.10/configs/mx6slevk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6slevk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,11 +6,11 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6SL=y + CONFIG_TARGET_MX6SLEVK=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -38,6 +38,7 @@ + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6slevk_spinor_defconfig u-boot/configs/mx6slevk_spinor_defconfig +--- u-boot-2021.10/configs/mx6slevk_spinor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6slevk_spinor_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -7,11 +7,11 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6SL=y + CONFIG_TARGET_MX6SLEVK=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" + CONFIG_SPI_BOOT=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y +@@ -38,6 +38,7 @@ + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6slevk_spl_defconfig u-boot/configs/mx6slevk_spl_defconfig +--- u-boot-2021.10/configs/mx6slevk_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6slevk_spl_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,16 +9,19 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6SL=y + CONFIG_TARGET_MX6SLEVK=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_FS_EXT4=y + CONFIG_SPL_I2C=y +@@ -47,6 +50,8 @@ + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6sllevk_defconfig u-boot/configs/mx6sllevk_defconfig +--- u-boot-2021.10/configs/mx6sllevk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sllevk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,11 +8,11 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6SLL=y + CONFIG_TARGET_MX6SLLEVK=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -36,6 +36,7 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/mx6sllevk_plugin_defconfig u-boot/configs/mx6sllevk_plugin_defconfig +--- u-boot-2021.10/configs/mx6sllevk_plugin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sllevk_plugin_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,12 +8,12 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6SLL=y + CONFIG_TARGET_MX6SLLEVK=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" + CONFIG_USE_IMXIMG_PLUGIN=y + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -37,6 +37,7 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/mx6sxsabreauto_defconfig u-boot/configs/mx6sxsabreauto_defconfig +--- u-boot-2021.10/configs/mx6sxsabreauto_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sxsabreauto_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,11 +6,11 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6SX=y + CONFIG_TARGET_MX6SXSABREAUTO=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + # CONFIG_CMD_FLASH is not set +@@ -37,10 +37,12 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_PCA953X=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_MXS=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=40000000 +diff -ruN u-boot-2021.10/configs/mx6sxsabresd_defconfig u-boot/configs/mx6sxsabresd_defconfig +--- u-boot-2021.10/configs/mx6sxsabresd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6sxsabresd_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,12 +6,12 @@ + CONFIG_ENV_OFFSET=0xE0000 + CONFIG_MX6SX=y + CONFIG_TARGET_MX6SXSABRESD=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" + # CONFIG_CMD_BMODE is not set + CONFIG_NXP_BOARD_REVISION=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -40,6 +40,7 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6ul_14x14_evk_defconfig u-boot/configs/mx6ul_14x14_evk_defconfig +--- u-boot-2021.10/configs/mx6ul_14x14_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6ul_14x14_evk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -11,15 +11,17 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_14X14_EVK=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y +@@ -57,6 +59,8 @@ + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6ul_9x9_evk_defconfig u-boot/configs/mx6ul_9x9_evk_defconfig +--- u-boot-2021.10/configs/mx6ul_9x9_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6ul_9x9_evk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -11,15 +11,17 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6UL=y + CONFIG_TARGET_MX6UL_9X9_EVK=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y +@@ -50,6 +52,8 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6ull_14x14_evk_defconfig u-boot/configs/mx6ull_14x14_evk_defconfig +--- u-boot-2021.10/configs/mx6ull_14x14_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6ull_14x14_evk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,10 +8,10 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6ULL=y + CONFIG_TARGET_MX6ULL_14X14_EVK=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -36,6 +36,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6ull_14x14_evk_plugin_defconfig u-boot/configs/mx6ull_14x14_evk_plugin_defconfig +--- u-boot-2021.10/configs/mx6ull_14x14_evk_plugin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6ull_14x14_evk_plugin_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,11 +8,11 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6ULL=y + CONFIG_TARGET_MX6ULL_14X14_EVK=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" + CONFIG_USE_IMXIMG_PLUGIN=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -37,6 +37,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx6ulz_14x14_evk_defconfig u-boot/configs/mx6ulz_14x14_evk_defconfig +--- u-boot-2021.10/configs/mx6ulz_14x14_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx6ulz_14x14_evk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,10 +8,10 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6ULL=y + CONFIG_TARGET_MX6ULL_14X14_EVK=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +@@ -35,6 +35,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/mx7dsabresd_defconfig u-boot/configs/mx7dsabresd_defconfig +--- u-boot-2021.10/configs/mx7dsabresd_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx7dsabresd_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" + CONFIG_TARGET_MX7DSABRESD=y +@@ -13,7 +14,6 @@ + CONFIG_IMX_BOOTAUX=y + CONFIG_IMX_HAB=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" + CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_CMD_BOOTD is not set +@@ -45,6 +45,7 @@ + CONFIG_DFU_RAM=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/mx7dsabresd_qspi_defconfig u-boot/configs/mx7dsabresd_qspi_defconfig +--- u-boot-2021.10/configs/mx7dsabresd_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx7dsabresd_qspi_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" + CONFIG_TARGET_MX7DSABRESD=y +@@ -12,7 +13,6 @@ + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" + CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + # CONFIG_CMD_BOOTD is not set +@@ -44,6 +44,7 @@ + CONFIG_DFU_RAM=y + CONFIG_DM_74X164=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y +diff -ruN u-boot-2021.10/configs/mx7ulp_com_defconfig u-boot/configs/mx7ulp_com_defconfig +--- u-boot-2021.10/configs/mx7ulp_com_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx7ulp_com_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -4,11 +4,12 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com" + CONFIG_LDO_ENABLED_MODE=y + CONFIG_TARGET_MX7ULP_COM=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x60800000 + CONFIG_DEFAULT_FDT_FILE="imx7ulp-com" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/mx7ulp_evk_defconfig u-boot/configs/mx7ulp_evk_defconfig +--- u-boot-2021.10/configs/mx7ulp_evk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx7ulp_evk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,11 +6,12 @@ + CONFIG_SYS_MEMTEST_END=0x9e000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" + CONFIG_TARGET_MX7ULP_EVK=y ++CONFIG_SYS_LOAD_ADDR=0x60800000 + CONFIG_OF_BOARD_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/mx7ulp_evk_plugin_defconfig u-boot/configs/mx7ulp_evk_plugin_defconfig +--- u-boot-2021.10/configs/mx7ulp_evk_plugin_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/mx7ulp_evk_plugin_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,10 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x9e000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" + CONFIG_TARGET_MX7ULP_EVK=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x60800000 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_MEMTEST=y +diff -ruN u-boot-2021.10/configs/myir_mys_6ulx_defconfig u-boot/configs/myir_mys_6ulx_defconfig +--- u-boot-2021.10/configs/myir_mys_6ulx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/myir_mys_6ulx_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,14 +9,14 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_MX6ULL=y + CONFIG_TARGET_MYS_6ULX=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval" + CONFIG_SPL_TEXT_BASE=0x908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/nanopc-t4-rk3399_defconfig u-boot/configs/nanopc-t4-rk3399_defconfig +--- u-boot-2021.10/configs/nanopc-t4-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopc-t4-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nanopi-k2_defconfig u-boot/configs/nanopi-k2_defconfig +--- u-boot-2021.10/configs/nanopi-k2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-k2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" nanopi-k2" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/nanopi-m4-2gb-rk3399_defconfig u-boot/configs/nanopi-m4-2gb-rk3399_defconfig +--- u-boot-2021.10/configs/nanopi-m4-2gb-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-m4-2gb-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nanopi-m4b-rk3399_defconfig u-boot/configs/nanopi-m4b-rk3399_defconfig +--- u-boot-2021.10/configs/nanopi-m4b-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-m4b-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nanopi-m4-rk3399_defconfig u-boot/configs/nanopi-m4-rk3399_defconfig +--- u-boot-2021.10/configs/nanopi-m4-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-m4-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nanopi-neo4-rk3399_defconfig u-boot/configs/nanopi-neo4-rk3399_defconfig +--- u-boot-2021.10/configs/nanopi-neo4-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-neo4-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nanopi-r2s-rk3328_defconfig u-boot/configs/nanopi-r2s-rk3328_defconfig +--- u-boot-2021.10/configs/nanopi-r2s-rk3328_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-r2s-rk3328_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -15,6 +16,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -66,6 +68,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_REGULATOR_PWM=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/nanopi-r4s-rk3399_defconfig u-boot/configs/nanopi-r4s-rk3399_defconfig +--- u-boot-2021.10/configs/nanopi-r4s-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nanopi-r4s-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/nas220_defconfig u-boot/configs/nas220_defconfig +--- u-boot-2021.10/configs/nas220_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nas220_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220" + CONFIG_IDENT_STRING="\nNAS 220" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/net2big_v2_defconfig u-boot/configs/net2big_v2_defconfig +--- u-boot-2021.10/configs/net2big_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/net2big_v2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big" + CONFIG_IDENT_STRING=" 2Big v2" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="2big2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/netgear_cg3100d_ram_defconfig u-boot/configs/netgear_cg3100d_ram_defconfig +--- u-boot-2021.10/configs/netgear_cg3100d_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netgear_cg3100d_ram_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,14 +1,18 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" + CONFIG_ARCH_BMIPS=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/netgear_dgnd3700v2_ram_defconfig u-boot/configs/netgear_dgnd3700v2_ram_defconfig +--- u-boot-2021.10/configs/netgear_dgnd3700v2_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netgear_dgnd3700v2_ram_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6362=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/netspace_lite_v2_defconfig u-boot/configs/netspace_lite_v2_defconfig +--- u-boot-2021.10/configs/netspace_lite_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netspace_lite_v2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite" + CONFIG_IDENT_STRING=" NS v2 Lite" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="ns2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/netspace_max_v2_defconfig u-boot/configs/netspace_max_v2_defconfig +--- u-boot-2021.10/configs/netspace_max_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netspace_max_v2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max" + CONFIG_IDENT_STRING=" NS Max v2" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="ns2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/netspace_mini_v2_defconfig u-boot/configs/netspace_mini_v2_defconfig +--- u-boot-2021.10/configs/netspace_mini_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netspace_mini_v2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini" + CONFIG_IDENT_STRING=" NS v2 Mini" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="ns2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + # CONFIG_CMD_SETEXPR is not set +@@ -42,6 +45,10 @@ + CONFIG_DM=y + CONFIG_SATA_MV=y + CONFIG_BLK=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/netspace_v2_defconfig u-boot/configs/netspace_v2_defconfig +--- u-boot-2021.10/configs/netspace_v2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/netspace_v2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2" + CONFIG_IDENT_STRING=" NS v2" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -22,6 +24,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="ns2> " + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_CMD_I2C=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y +@@ -43,6 +46,10 @@ + CONFIG_NETCONSOLE=y + CONFIG_DM=y + CONFIG_SATA_MV=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + # CONFIG_MMC is not set + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/nezha_defconfig u-boot/configs/nezha_defconfig +--- u-boot-2021.10/configs/nezha_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/nezha_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -0,0 +1,32 @@ ++CONFIG_RISCV=y ++CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-nezha" ++CONFIG_TARGET_SUNXI=y ++CONFIG_ARCH_RV64I=y ++CONFIG_RISCV_SMODE=y ++# CONFIG_SPL_SMP is not set ++CONFIG_SYS_LOAD_ADDR=0x4a000000 ++CONFIG_CMD_CLK=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_LSBLK=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_WDT=y ++CONFIG_CMD_TIMER=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_UBI=y ++# CONFIG_CMD_UBIFS is not set ++CONFIG_OF_PRIOR_STAGE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_PHY_REALTEK=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPI=y ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_USB_MUSB_GADGET=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_MASS_STORAGE=y +diff -ruN u-boot-2021.10/configs/Nintendo_NES_Classic_Edition_defconfig u-boot/configs/Nintendo_NES_Classic_Edition_defconfig +--- u-boot-2021.10/configs/Nintendo_NES_Classic_Edition_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Nintendo_NES_Classic_Edition_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -6,7 +6,7 @@ + CONFIG_DRAM_CLK=600 + CONFIG_DRAM_ZQ=15291 + CONFIG_DRAM_ODT_EN=y +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + # CONFIG_CMD_FLASH is not set +@@ -15,6 +15,7 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_PAGE_SIZE=0x800 + CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_AXP_DLDO1_VOLT=3300 +diff -ruN u-boot-2021.10/configs/nitrogen6dl2g_defconfig u-boot/configs/nitrogen6dl2g_defconfig +--- u-boot-2021.10/configs/nitrogen6dl2g_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6dl2g_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl2g.cfg" + CONFIG_MX6DL=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=2048 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,DDR_MB=2048" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -51,6 +56,8 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nitrogen6dl_defconfig u-boot/configs/nitrogen6dl_defconfig +--- u-boot-2021.10/configs/nitrogen6dl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6dl_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6dl.cfg" + CONFIG_MX6DL=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=1024 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,DDR_MB=1024" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -51,6 +56,8 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nitrogen6q2g_defconfig u-boot/configs/nitrogen6q2g_defconfig +--- u-boot-2021.10/configs/nitrogen6q2g_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6q2g_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q2g.cfg" + CONFIG_MX6Q=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=2048 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,DDR_MB=2048" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -53,6 +58,8 @@ + CONFIG_DWC_AHSATA=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nitrogen6q_defconfig u-boot/configs/nitrogen6q_defconfig +--- u-boot-2021.10/configs/nitrogen6q_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6q_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q.cfg" + CONFIG_MX6Q=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=1024 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -53,6 +58,8 @@ + CONFIG_DWC_AHSATA=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nitrogen6s1g_defconfig u-boot/configs/nitrogen6s1g_defconfig +--- u-boot-2021.10/configs/nitrogen6s1g_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6s1g_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" + CONFIG_MX6S=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=1024 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,DDR_MB=1024" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -51,6 +56,8 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nitrogen6s_defconfig u-boot/configs/nitrogen6s_defconfig +--- u-boot-2021.10/configs/nitrogen6s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nitrogen6s_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,14 +8,19 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s.cfg" + CONFIG_MX6S=y + CONFIG_TARGET_NITROGEN6X=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 ++CONFIG_DDR_MB=512 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,DDR_MB=512" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -51,6 +56,8 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/nokia_rx51_defconfig u-boot/configs/nokia_rx51_defconfig +--- u-boot-2021.10/configs/nokia_rx51_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nokia_rx51_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,12 +1,21 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_SYS_THUMB_BUILD is not set + CONFIG_ARCH_OMAP2PLUS=y ++CONFIG_SUPPORT_PASSING_ATAGS=y ++CONFIG_CMDLINE_TAG=y ++CONFIG_INITRD_TAG=y ++CONFIG_REVISION_TAG=y ++CONFIG_STATIC_MACH_TYPE=y ++CONFIG_MACH_TYPE=1955 + CONFIG_SYS_TEXT_BASE=0x80008000 + CONFIG_NR_DRAM_BANKS=2 ++CONFIG_SYS_MALLOC_LEN=0xc0000 + CONFIG_TARGET_NOKIA_RX51=y + CONFIG_OPTIMIZE_INLINING=y + CONFIG_LTO=y + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x80000000 + # CONFIG_FIT is not set + CONFIG_BOOTDELAY=30 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/novena_defconfig u-boot/configs/novena_defconfig +--- u-boot-2021.10/configs/novena_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/novena_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,10 +10,14 @@ + CONFIG_MX6Q=y + CONFIG_MX6_DDRCAL=y + CONFIG_TARGET_KOSAGI_NOVENA=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x84000 + CONFIG_SPL_FS_FAT=y +@@ -22,7 +26,6 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttymxc1,115200 " + CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs" +@@ -33,6 +36,8 @@ + CONFIG_SPL_WATCHDOG=y + CONFIG_CMD_ASKENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_BUS=2 ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -52,6 +57,9 @@ + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +@@ -61,6 +69,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_DM_THERMAL=y + CONFIG_IMX_THERMAL=y +diff -ruN u-boot-2021.10/configs/nsa310s_defconfig u-boot/configs/nsa310s_defconfig +--- u-boot-2021.10/configs/nsa310s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nsa310s_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -9,6 +10,7 @@ + CONFIG_ENV_OFFSET=0xE0000 + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s" + CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/nsim_700be_defconfig u-boot/configs/nsim_700be_defconfig +--- u-boot-2021.10/configs/nsim_700be_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nsim_700be_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -3,11 +3,13 @@ + CONFIG_TARGET_NSIM=y + CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape" + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="nsim" + CONFIG_DEBUG_UART_BASE=0xf0000000 + CONFIG_DEBUG_UART_CLOCK=70000000 + CONFIG_SYS_CLK_FREQ=70000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +diff -ruN u-boot-2021.10/configs/nsim_700_defconfig u-boot/configs/nsim_700_defconfig +--- u-boot-2021.10/configs/nsim_700_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nsim_700_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -2,11 +2,13 @@ + CONFIG_TARGET_NSIM=y + CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=arc700 -mlock -mswape" + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="nsim" + CONFIG_DEBUG_UART_BASE=0xf0000000 + CONFIG_DEBUG_UART_CLOCK=70000000 + CONFIG_SYS_CLK_FREQ=70000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +diff -ruN u-boot-2021.10/configs/nsim_hs38be_defconfig u-boot/configs/nsim_hs38be_defconfig +--- u-boot-2021.10/configs/nsim_hs38be_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nsim_hs38be_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -4,11 +4,13 @@ + CONFIG_TARGET_NSIM=y + CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs" + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="nsim" + CONFIG_DEBUG_UART_BASE=0xf0000000 + CONFIG_DEBUG_UART_CLOCK=70000000 + CONFIG_SYS_CLK_FREQ=70000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +diff -ruN u-boot-2021.10/configs/nsim_hs38_defconfig u-boot/configs/nsim_hs38_defconfig +--- u-boot-2021.10/configs/nsim_hs38_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nsim_hs38_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -3,11 +3,13 @@ + CONFIG_TARGET_NSIM=y + CONFIG_NSIM_BOARD_CPPFLAGS="-mcpu=archs" + CONFIG_SYS_TEXT_BASE=0x81000000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="nsim" + CONFIG_DEBUG_UART_BASE=0xf0000000 + CONFIG_DEBUG_UART_CLOCK=70000000 + CONFIG_SYS_CLK_FREQ=70000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +diff -ruN u-boot-2021.10/configs/nyan-big_defconfig u-boot/configs/nyan-big_defconfig +--- u-boot-2021.10/configs/nyan-big_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/nyan-big_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -4,6 +4,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000 +@@ -12,6 +13,7 @@ + CONFIG_TEGRA124=y + CONFIG_TARGET_NYAN_BIG=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x82408000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_OF_SYSTEM_SETUP=y +diff -ruN u-boot-2021.10/configs/o4-imx6ull-nano_defconfig u-boot/configs/o4-imx6ull-nano_defconfig +--- u-boot-2021.10/configs/o4-imx6ull-nano_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/o4-imx6ull-nano_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -3,6 +3,7 @@ + CONFIG_SYS_TEXT_BASE=0x87800000 + CONFIG_MX6ULL=y + CONFIG_TARGET_O4_IMX6ULL_NANO=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_MT41K256M16HA_125E=y + CONFIG_IMX_MODULE_FUSE=y +diff -ruN u-boot-2021.10/configs/octeon_ebb7304_defconfig u-boot/configs/octeon_ebb7304_defconfig +--- u-boot-2021.10/configs/octeon_ebb7304_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeon_ebb7304_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -4,6 +4,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEBUG_UART_BASE=0x8001180000000800 + CONFIG_DEBUG_UART_CLOCK=1200000000 + CONFIG_ARCH_OCTEON=y +@@ -12,6 +13,7 @@ + CONFIG_MIPS_RELOCATION_TABLE_SIZE=0xc000 + CONFIG_DEBUG_UART=y + CONFIG_OF_BOARD_FIXUP=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff80100000 + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_BOARD_LATE_INIT=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/octeon_nic23_defconfig u-boot/configs/octeon_nic23_defconfig +--- u-boot-2021.10/configs/octeon_nic23_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeon_nic23_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xe000 + CONFIG_ENV_SECT_SIZE=0x100 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEBUG_UART_BASE=0x8001180000000800 + CONFIG_DEBUG_UART_CLOCK=800000000 + CONFIG_ARCH_OCTEON=y +@@ -14,6 +15,7 @@ + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + CONFIG_OF_BOARD_FIXUP=y ++CONFIG_SYS_LOAD_ADDR=0xffffffff80100000 + CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y + # CONFIG_SYS_DEVICE_NULLDEV is not set + CONFIG_ARCH_MISC_INIT=y +diff -ruN u-boot-2021.10/configs/octeontx2_95xx_defconfig u-boot/configs/octeontx2_95xx_defconfig +--- u-boot-2021.10/configs/octeontx2_95xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeontx2_95xx_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,10 +10,12 @@ + CONFIG_ENV_OFFSET=0xF00000 + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_TARGET_OCTEONTX2_95XX=y ++CONFIG_SYS_MALLOC_LEN=0x4008000 + CONFIG_DM_GPIO=y + CONFIG_DEBUG_UART_BASE=0x87e028000000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x4000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_OF_BOARD_SETUP=y +diff -ruN u-boot-2021.10/configs/octeontx2_96xx_defconfig u-boot/configs/octeontx2_96xx_defconfig +--- u-boot-2021.10/configs/octeontx2_96xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeontx2_96xx_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,12 +8,14 @@ + CONFIG_ENV_OFFSET=0xF00000 + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_TARGET_OCTEONTX2_96XX=y ++CONFIG_SYS_MALLOC_LEN=0x4008000 + CONFIG_DM_GPIO=y + CONFIG_DEBUG_UART_BASE=0x87e028000000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x4000000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_OF_BOARD_SETUP=y +diff -ruN u-boot-2021.10/configs/octeontx_81xx_defconfig u-boot/configs/octeontx_81xx_defconfig +--- u-boot-2021.10/configs/octeontx_81xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeontx_81xx_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -10,11 +10,13 @@ + CONFIG_ENV_OFFSET=0xF00000 + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_TARGET_OCTEONTX_81XX=y ++CONFIG_SYS_MALLOC_LEN=0x4008000 + CONFIG_DM_GPIO=y + CONFIG_DEBUG_UART_BASE=0x87e028000000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x2800000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_SUPPORT_RAW_INITRD=y +diff -ruN u-boot-2021.10/configs/octeontx_83xx_defconfig u-boot/configs/octeontx_83xx_defconfig +--- u-boot-2021.10/configs/octeontx_83xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/octeontx_83xx_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,11 +8,13 @@ + CONFIG_ENV_OFFSET=0xF00000 + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_TARGET_OCTEONTX_83XX=y ++CONFIG_SYS_MALLOC_LEN=0x4008000 + CONFIG_DM_GPIO=y + CONFIG_DEBUG_UART_BASE=0x87e028000000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x2800000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_SUPPORT_RAW_INITRD=y +diff -ruN u-boot-2021.10/configs/odroid-c2_defconfig u-boot/configs/odroid-c2_defconfig +--- u-boot-2021.10/configs/odroid-c2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid-c2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" odroid-c2" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/odroid-c4_defconfig u-boot/configs/odroid-c4_defconfig +--- u-boot-2021.10/configs/odroid-c4_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid-c4_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" odroid-c4/hc4" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/odroid_defconfig u-boot/configs/odroid_defconfig +--- u-boot-2021.10/configs/odroid_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x43e00000 +@@ -7,9 +8,11 @@ + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x140000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/odroid-go2_defconfig u-boot/configs/odroid-go2_defconfig +--- u-boot-2021.10/configs/odroid-go2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid-go2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -19,6 +20,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -81,6 +83,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_REGULATOR_RK8XX=y +@@ -95,7 +98,7 @@ + CONFIG_DEBUG_UART_SKIP_INIT=y + CONFIG_SOUND=y + CONFIG_SYSRESET=y +-CONFIG_OPTEE=y ++CONFIG_OPTEE_LIB=y + CONFIG_DM_THERMAL=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/odroid-hc4_defconfig u-boot/configs/odroid-hc4_defconfig +--- u-boot-2021.10/configs/odroid-hc4_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/odroid-hc4_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -0,0 +1,93 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="odroid-n2" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" odroid-hc4" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_AHCI=y ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_ADC=y ++CONFIG_SARADC_MESON=y ++CONFIG_SATA=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_PCI=y ++CONFIG_PCIE_DW_MESON=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_RESET=y ++CONFIG_SCSI=y ++CONFIG_DM_SCSI=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MESON_SPIFC=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_BMP_RLE8=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/odroid-n2_defconfig u-boot/configs/odroid-n2_defconfig +--- u-boot-2021.10/configs/odroid-n2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid-n2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" odroid-n2/n2-plus" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/odroid-xu3_defconfig u-boot/configs/odroid-xu3_defconfig +--- u-boot-2021.10/configs/odroid-xu3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/odroid-xu3_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x43E00000 +@@ -6,10 +7,12 @@ + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x310000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" + CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2" + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -42,6 +45,7 @@ + CONFIG_DFU_MMC=y + CONFIG_SET_DFU_ALT_INFO=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_DW=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/omap35_logic_defconfig u-boot/configs/omap35_logic_defconfig +--- u-boot-2021.10/configs/omap35_logic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap35_logic_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -53,9 +53,15 @@ + CONFIG_SPL_DM=y + CONFIG_SPL_OF_TRANSLATE=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +diff -ruN u-boot-2021.10/configs/omap35_logic_somlv_defconfig u-boot/configs/omap35_logic_somlv_defconfig +--- u-boot-2021.10/configs/omap35_logic_somlv_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap35_logic_somlv_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -52,6 +52,7 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_SPL_DM=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -61,6 +62,11 @@ + CONFIG_SYS_FLASH_PROTECTION=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +@@ -81,6 +87,8 @@ + CONFIG_USB=y + # CONFIG_SPL_DM_USB is not set + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4 + CONFIG_USB_MUSB_HOST=y + CONFIG_USB_MUSB_OMAP2PLUS=y + CONFIG_TWL4030_USB=y +diff -ruN u-boot-2021.10/configs/omap3_beagle_defconfig u-boot/configs/omap3_beagle_defconfig +--- u-boot-2021.10/configs/omap3_beagle_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap3_beagle_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -56,6 +56,8 @@ + CONFIG_SPL_OF_TRANSLATE=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x82000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_LED_STATUS=y + CONFIG_LED_STATUS0=y + CONFIG_LED_STATUS_BIT=1 +@@ -72,6 +74,11 @@ + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +@@ -82,6 +89,8 @@ + CONFIG_USB=y + # CONFIG_SPL_DM_USB is not set + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=147 + CONFIG_USB_OMAP3=y + CONFIG_USB_MUSB_GADGET=y + CONFIG_USB_MUSB_OMAP2PLUS=y +diff -ruN u-boot-2021.10/configs/omap3_evm_defconfig u-boot/configs/omap3_evm_defconfig +--- u-boot-2021.10/configs/omap3_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap3_evm_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -57,9 +57,16 @@ + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x82000000 + CONFIG_GPIO_HOG=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +diff -ruN u-boot-2021.10/configs/omap3_logic_defconfig u-boot/configs/omap3_logic_defconfig +--- u-boot-2021.10/configs/omap3_logic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap3_logic_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -52,10 +52,16 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_SPL_DM=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MMC_OMAP36XX_PINS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +diff -ruN u-boot-2021.10/configs/omap3_logic_somlv_defconfig u-boot/configs/omap3_logic_somlv_defconfig +--- u-boot-2021.10/configs/omap3_logic_somlv_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap3_logic_somlv_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -52,6 +52,7 @@ + CONFIG_VERSION_VARIABLE=y + CONFIG_SPL_DM=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_MMC_OMAP_HS=y + CONFIG_MMC_OMAP36XX_PINS=y + CONFIG_MTD=y +@@ -62,6 +63,11 @@ + CONFIG_SYS_FLASH_PROTECTION=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +@@ -82,6 +88,8 @@ + CONFIG_USB=y + # CONFIG_SPL_DM_USB is not set + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4 + CONFIG_USB_MUSB_HOST=y + CONFIG_USB_MUSB_OMAP2PLUS=y + CONFIG_TWL4030_USB=y +diff -ruN u-boot-2021.10/configs/omap4_panda_defconfig u-boot/configs/omap4_panda_defconfig +--- u-boot-2021.10/configs/omap4_panda_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap4_panda_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -32,12 +32,18 @@ + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_VERSION_VARIABLE=y + CONFIG_DM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_DM_ETH=y + CONFIG_CONS_INDEX=3 + CONFIG_SYS_NS16550=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=1 ++CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=62 + CONFIG_USB_OMAP3=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_SMSC95XX=y +diff -ruN u-boot-2021.10/configs/omap4_sdp4430_defconfig u-boot/configs/omap4_sdp4430_defconfig +--- u-boot-2021.10/configs/omap4_sdp4430_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap4_sdp4430_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -33,6 +33,8 @@ + CONFIG_SYS_MMC_ENV_DEV=1 + CONFIG_VERSION_VARIABLE=y + CONFIG_DM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MMC_OMAP_HS=y + CONFIG_DM_ETH=y + CONFIG_CONS_INDEX=3 +diff -ruN u-boot-2021.10/configs/omap5_uevm_defconfig u-boot/configs/omap5_uevm_defconfig +--- u-boot-2021.10/configs/omap5_uevm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omap5_uevm_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -39,6 +39,8 @@ + CONFIG_DFU_MMC=y + CONFIG_DFU_RAM=y + CONFIG_CMD_TCA642X=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_OMAP_HS=y + CONFIG_DM_ETH=y +@@ -47,6 +49,10 @@ + CONFIG_SYS_NS16550=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y ++CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=80 ++CONFIG_HAS_OMAP_EHCI_PHY3_RESET_GPIO=y ++CONFIG_OMAP_EHCI_PHY3_RESET_GPIO=79 + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_OMAP=y + CONFIG_USB_DWC3_PHY_OMAP=y +diff -ruN u-boot-2021.10/configs/omapl138_lcdk_defconfig u-boot/configs/omapl138_lcdk_defconfig +--- u-boot-2021.10/configs/omapl138_lcdk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/omapl138_lcdk_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_DAVINCI=y + CONFIG_SYS_TEXT_BASE=0xc1080000 +@@ -12,12 +14,14 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x110000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk" + CONFIG_SPL_TEXT_BASE=0x80000000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0xc0700000 + CONFIG_BOOTDELAY=3 + CONFIG_LOGLEVEL=3 + # CONFIG_DISPLAY_CPUINFO is not set +@@ -61,6 +65,10 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_DAVINCI=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 +diff -ruN u-boot-2021.10/configs/openpiton_riscv64_defconfig u-boot/configs/openpiton_riscv64_defconfig +--- u-boot-2021.10/configs/openpiton_riscv64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/openpiton_riscv64_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,6 +1,7 @@ + CONFIG_RISCV=y + CONFIG_SYS_TEXT_BASE=0x80200000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x10000000 + CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" + CONFIG_TARGET_OPENPITON_RISCV64=y + CONFIG_ARCH_RV64I=y +@@ -10,6 +11,7 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_ENV_VARS_UBOOT_CONFIG=y + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x87000000 + # CONFIG_LEGACY_IMAGE_FORMAT is not set + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_SYS_PROMPT="openpiton$ " +diff -ruN u-boot-2021.10/configs/openpiton_riscv64_spl_defconfig u-boot/configs/openpiton_riscv64_spl_defconfig +--- u-boot-2021.10/configs/openpiton_riscv64_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/openpiton_riscv64_spl_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,8 +1,8 @@ + CONFIG_RISCV=y + CONFIG_SYS_TEXT_BASE=0x80000000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x10000000 + CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +-CONFIG_SPL_MMC_SUPPORT=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -15,6 +15,7 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_ENV_VARS_UBOOT_CONFIG=y + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x87000000 + # CONFIG_LEGACY_IMAGE_FORMAT is not set + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +@@ -23,7 +24,7 @@ + # CONFIG_SPL_BANNER_PRINT is not set + CONFIG_SPL_CPU=y + CONFIG_SPL_FS_EXT4=y +-CONFIG_SPL_RTC_SUPPORT=y ++CONFIG_SPL_RTC=y + CONFIG_SYS_PROMPT="openpiton$ " + # CONFIG_CMD_CPU is not set + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/openrd_base_defconfig u-boot/configs/openrd_base_defconfig +--- u-boot-2021.10/configs/openrd_base_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/openrd_base_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base" + CONFIG_IDENT_STRING="\nOpenRD-Base" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y +diff -ruN u-boot-2021.10/configs/openrd_client_defconfig u-boot/configs/openrd_client_defconfig +--- u-boot-2021.10/configs/openrd_client_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/openrd_client_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client" + CONFIG_IDENT_STRING="\nOpenRD-Client" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y +diff -ruN u-boot-2021.10/configs/openrd_ultimate_defconfig u-boot/configs/openrd_ultimate_defconfig +--- u-boot-2021.10/configs/openrd_ultimate_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/openrd_ultimate_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate" + CONFIG_IDENT_STRING="\nOpenRD-Ultimate" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y +diff -ruN u-boot-2021.10/configs/opos6uldev_defconfig u-boot/configs/opos6uldev_defconfig +--- u-boot-2021.10/configs/opos6uldev_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/opos6uldev_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,10 +9,11 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6UL=y + CONFIG_TARGET_OPOS6ULDEV=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x180000 +diff -ruN u-boot-2021.10/configs/orangepi_2_defconfig u-boot/configs/orangepi_2_defconfig +--- u-boot-2021.10/configs/orangepi_2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -5,9 +5,11 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN8I_H3=y + CONFIG_DRAM_CLK=672 +-CONFIG_USB1_VBUS_PIN="PG13" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/Orangepi_defconfig u-boot/configs/Orangepi_defconfig +--- u-boot-2021.10/configs/Orangepi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Orangepi_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,8 +5,7 @@ + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=432 + CONFIG_MACPWR="PH23" +-CONFIG_USB1_VBUS_PIN="PH26" +-CONFIG_USB2_VBUS_PIN="PH22" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_VGA=y + CONFIG_VIDEO_COMPOSITE=y + CONFIG_GMAC_TX_DELAY=3 +@@ -14,6 +13,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +diff -ruN u-boot-2021.10/configs/Orangepi_mini_defconfig u-boot/configs/Orangepi_mini_defconfig +--- u-boot-2021.10/configs/Orangepi_mini_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Orangepi_mini_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -8,14 +8,16 @@ + CONFIG_MMC0_CD_PIN="PH10" + CONFIG_MMC3_CD_PIN="PH11" + CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +-CONFIG_USB1_VBUS_PIN="PH26" +-CONFIG_USB2_VBUS_PIN="PH22" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_COMPOSITE=y + CONFIG_GMAC_TX_DELAY=3 + CONFIG_AHCI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +diff -ruN u-boot-2021.10/configs/orangepi_pc2_defconfig u-boot/configs/orangepi_pc2_defconfig +--- u-boot-2021.10/configs/orangepi_pc2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_pc2_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -9,6 +9,8 @@ + CONFIG_SPL_SPI_SUNXI=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_SY8106A_VOUT1_VOLT=1100 +diff -ruN u-boot-2021.10/configs/orangepi_pc_defconfig u-boot/configs/orangepi_pc_defconfig +--- u-boot-2021.10/configs/orangepi_pc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_pc_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,6 +6,8 @@ + CONFIG_DRAM_CLK=624 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/orangepi_pc_plus_defconfig u-boot/configs/orangepi_pc_plus_defconfig +--- u-boot-2021.10/configs/orangepi_pc_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_pc_plus_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -7,6 +7,8 @@ + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/orangepi_plus2e_defconfig u-boot/configs/orangepi_plus2e_defconfig +--- u-boot-2021.10/configs/orangepi_plus2e_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_plus2e_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -8,6 +8,8 @@ + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/orangepi_plus_defconfig u-boot/configs/orangepi_plus_defconfig +--- u-boot-2021.10/configs/orangepi_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_plus_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -6,10 +6,12 @@ + CONFIG_DRAM_CLK=672 + CONFIG_MACPWR="PD6" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB1_VBUS_PIN="PG13" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SATAPWR="PG11" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/orangepi-rk3399_defconfig u-boot/configs/orangepi-rk3399_defconfig +--- u-boot-2021.10/configs/orangepi-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi-rk3399_defconfig 2021-11-01 17:10:14.189596497 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +diff -ruN u-boot-2021.10/configs/orangepi_zero2_defconfig u-boot/configs/orangepi_zero2_defconfig +--- u-boot-2021.10/configs/orangepi_zero2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/orangepi_zero2_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,5 +11,10 @@ + CONFIG_R_I2C_ENABLE=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_SUN8I_EMAC=y +diff -ruN u-boot-2021.10/configs/origen_defconfig u-boot/configs/origen_defconfig +--- u-boot-2021.10/configs/origen_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/origen_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y +@@ -7,11 +9,13 @@ + CONFIG_TARGET_ORIGEN=y + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x4200 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" + CONFIG_SPL_TEXT_BASE=0x02021410 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for ORIGEN" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_36BIT_NAND_defconfig u-boot/configs/P1010RDB-PA_36BIT_NAND_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_36BIT_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_36BIT_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL_DRIVERS_MISC=y +@@ -29,11 +30,13 @@ + CONFIG_TPL_DRIVERS_MISC=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -49,7 +52,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +68,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_36BIT_NOR_defconfig u-boot/configs/P1010RDB-PA_36BIT_NOR_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_36BIT_NOR_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_36BIT_NOR_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PA=y +@@ -17,6 +18,8 @@ + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -32,7 +35,14 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_36BIT_SDCARD_defconfig u-boot/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_36BIT_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_36BIT_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -26,9 +27,11 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -44,7 +47,14 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig u-boot/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,13 +5,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PA=y + CONFIG_PHYS_64BIT=y +@@ -28,9 +29,11 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -46,7 +49,14 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_NAND_defconfig u-boot/configs/P1010RDB-PA_NAND_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL_DRIVERS_MISC=y +@@ -28,11 +29,13 @@ + CONFIG_TPL_DRIVERS_MISC=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -48,7 +51,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -56,6 +67,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_NOR_defconfig u-boot/configs/P1010RDB-PA_NOR_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_NOR_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_NOR_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PA=y +@@ -16,6 +17,8 @@ + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -31,7 +34,14 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_SDCARD_defconfig u-boot/configs/P1010RDB-PA_SDCARD_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -25,9 +26,11 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -43,7 +46,14 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PA_SPIFLASH_defconfig u-boot/configs/P1010RDB-PA_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1010RDB-PA_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PA_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,13 +5,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PA=y + CONFIG_FIT=y +@@ -27,9 +28,11 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -45,7 +48,14 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_36BIT_NAND_defconfig u-boot/configs/P1010RDB-PB_36BIT_NAND_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_36BIT_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_36BIT_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL_DRIVERS_MISC=y +@@ -22,6 +23,7 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_NAND_BOOT=y + CONFIG_SPL_NAND_SUPPORT=y +@@ -29,11 +31,13 @@ + CONFIG_TPL_DRIVERS_MISC=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -49,7 +53,16 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +70,9 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_36BIT_NOR_defconfig u-boot/configs/P1010RDB-PB_36BIT_NOR_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_36BIT_NOR_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_36BIT_NOR_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PB=y +@@ -15,8 +16,11 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -32,7 +36,15 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_36BIT_SDCARD_defconfig u-boot/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_36BIT_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_36BIT_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -22,13 +23,16 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -44,7 +48,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig u-boot/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,13 +5,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PB=y + CONFIG_PHYS_64BIT=y +@@ -24,13 +25,16 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -46,7 +50,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_NAND_defconfig u-boot/configs/P1010RDB-PB_NAND_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL_DRIVERS_MISC=y +@@ -21,6 +22,7 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_NAND_BOOT=y + CONFIG_SPL_NAND_SUPPORT=y +@@ -28,11 +30,13 @@ + CONFIG_TPL_DRIVERS_MISC=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -48,7 +52,16 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -56,6 +69,9 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_NOR_defconfig u-boot/configs/P1010RDB-PB_NOR_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_NOR_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_NOR_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PB=y +@@ -14,8 +15,11 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -31,7 +35,15 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_SDCARD_defconfig u-boot/configs/P1010RDB-PB_SDCARD_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -21,13 +22,16 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -43,7 +47,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1010RDB-PB_SPIFLASH_defconfig u-boot/configs/P1010RDB-PB_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1010RDB-PB_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1010RDB-PB_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,13 +5,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" + CONFIG_SPL_TEXT_BASE=0xD0001000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_P1010RDB_PB=y + CONFIG_FIT=y +@@ -23,13 +24,16 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -45,7 +49,15 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_36BIT_defconfig u-boot/configs/P1020RDB-PC_36BIT_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_36BIT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_36BIT_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -19,6 +20,8 @@ + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -33,7 +36,15 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_36BIT_NAND_defconfig u-boot/configs/P1020RDB-PC_36BIT_NAND_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_36BIT_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_36BIT_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL=y +@@ -28,12 +29,14 @@ + CONFIG_TPL=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -48,7 +51,16 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -56,6 +68,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_36BIT_SDCARD_defconfig u-boot/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_36BIT_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_36BIT_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -26,10 +27,12 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -44,7 +47,15 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig u-boot/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set + CONFIG_TARGET_P1020RDB_PC=y +@@ -28,10 +29,12 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -46,7 +49,15 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_defconfig u-boot/configs/P1020RDB-PC_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -18,6 +19,8 @@ + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -32,7 +35,15 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_NAND_defconfig u-boot/configs/P1020RDB-PC_NAND_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL=y +@@ -27,12 +28,14 @@ + CONFIG_TPL=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -47,7 +50,16 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -55,6 +67,8 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_SDCARD_defconfig u-boot/configs/P1020RDB-PC_SDCARD_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -25,10 +26,12 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -43,7 +46,15 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PC_SPIFLASH_defconfig u-boot/configs/P1020RDB-PC_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1020RDB-PC_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PC_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set + CONFIG_TARGET_P1020RDB_PC=y +@@ -27,10 +28,12 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -45,7 +48,15 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PD_defconfig u-boot/configs/P1020RDB-PD_defconfig +--- u-boot-2021.10/configs/P1020RDB-PD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -18,6 +19,8 @@ + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -35,7 +38,15 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PD_NAND_defconfig u-boot/configs/P1020RDB-PD_NAND_defconfig +--- u-boot-2021.10/configs/P1020RDB-PD_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PD_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL=y +@@ -27,12 +28,14 @@ + CONFIG_TPL=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -50,7 +53,16 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -59,6 +71,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P1020RDB-PD_SDCARD_defconfig u-boot/configs/P1020RDB-PD_SDCARD_defconfig +--- u-boot-2021.10/configs/P1020RDB-PD_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PD_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -25,10 +26,12 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -46,7 +49,15 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P1020RDB-PD_SPIFLASH_defconfig u-boot/configs/P1020RDB-PD_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P1020RDB-PD_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P1020RDB-PD_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set + CONFIG_TARGET_P1020RDB_PD=y +@@ -27,10 +28,12 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y +@@ -48,7 +51,15 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/p200_defconfig u-boot/configs/p200_defconfig +--- u-boot-2021.10/configs/p200_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p200_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" p200" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/p201_defconfig u-boot/configs/p201_defconfig +--- u-boot-2021.10/configs/p201_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p201_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" p201" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_36BIT_defconfig u-boot/configs/P2020RDB-PC_36BIT_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_36BIT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_36BIT_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -19,6 +20,8 @@ + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -37,7 +40,15 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_36BIT_NAND_defconfig u-boot/configs/P2020RDB-PC_36BIT_NAND_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_36BIT_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_36BIT_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL=y +@@ -28,12 +29,14 @@ + CONFIG_TPL=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -52,7 +55,16 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -61,6 +73,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_36BIT_SDCARD_defconfig u-boot/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_36BIT_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_36BIT_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -26,10 +27,12 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -48,7 +51,15 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig u-boot/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set + CONFIG_TARGET_P2020RDB=y +@@ -28,10 +29,12 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -50,7 +53,15 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_defconfig u-boot/configs/P2020RDB-PC_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -18,6 +19,8 @@ + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -36,7 +39,15 @@ + CONFIG_ENV_IS_IN_FLASH=y + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_NAND_defconfig u-boot/configs/P2020RDB-PC_NAND_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_NAND_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -2,9 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x11001000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xFF800000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_TPL_LIBCOMMON_SUPPORT=y + CONFIG_TPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL=y +@@ -27,12 +28,14 @@ + CONFIG_TPL=y + CONFIG_TPL_ENV_SUPPORT=y + CONFIG_TPL_I2C=y +-CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_TPL_MPC8XXX_INIT_DDR=y + CONFIG_TPL_NAND_SUPPORT=y +-CONFIG_TPL_SERIAL_SUPPORT=y ++CONFIG_TPL_SERIAL=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -51,7 +54,16 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_TPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -60,6 +72,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_SDCARD_defconfig u-boot/configs/P2020RDB-PC_SDCARD_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_SDCARD_defconfig 2021-11-01 17:10:14.162931288 +0100 +@@ -4,10 +4,11 @@ + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set +@@ -25,10 +26,12 @@ + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -47,7 +50,15 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2020RDB-PC_SPIFLASH_defconfig u-boot/configs/P2020RDB-PC_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P2020RDB-PC_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2020RDB-PC_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -5,12 +5,13 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" + CONFIG_SPL_TEXT_BASE=0xf8f81000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + # CONFIG_CMD_ERRATA is not set + CONFIG_TARGET_P2020RDB=y +@@ -27,10 +28,12 @@ + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + # CONFIG_AUTO_COMPLETE is not set + CONFIG_CMD_IMLS=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y +@@ -49,7 +52,15 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DDR_CLK_FREQ=66666666 + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x52 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2041RDB_defconfig u-boot/configs/P2041RDB_defconfig +--- u-boot-2021.10/configs/P2041RDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2041RDB_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" + CONFIG_MPC85xx=y + CONFIG_TARGET_P2041RDB=y +@@ -13,9 +14,11 @@ + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_DM=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -33,6 +36,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2041RDB_NAND_defconfig u-boot/configs/P2041RDB_NAND_defconfig +--- u-boot-2021.10/configs/P2041RDB_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2041RDB_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xE0000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" + CONFIG_MPC85xx=y + CONFIG_TARGET_P2041RDB=y +@@ -10,13 +11,17 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_DM=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -34,6 +39,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -41,6 +49,7 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P2041RDB_SDCARD_defconfig u-boot/configs/P2041RDB_SDCARD_defconfig +--- u-boot-2021.10/configs/P2041RDB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2041RDB_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xCF400 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" + CONFIG_MPC85xx=y + CONFIG_TARGET_P2041RDB=y +@@ -10,13 +11,18 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_DM=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -34,6 +40,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P2041RDB_SPIFLASH_defconfig u-boot/configs/P2041RDB_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P2041RDB_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P2041RDB_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" + CONFIG_MPC85xx=y + CONFIG_TARGET_P2041RDB=y +@@ -11,13 +12,18 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_DM=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -35,6 +41,9 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/p212_defconfig u-boot/configs/p212_defconfig +--- u-boot-2021.10/configs/p212_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p212_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" p212" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/p2371-0000_defconfig u-boot/configs/p2371-0000_defconfig +--- u-boot-2021.10/configs/p2371-0000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p2371-0000_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,8 +4,10 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" + CONFIG_TEGRA210=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/p2371-2180_defconfig u-boot/configs/p2371-2180_defconfig +--- u-boot-2021.10/configs/p2371-2180_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p2371-2180_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,9 +4,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180" + CONFIG_TEGRA210=y + CONFIG_TARGET_P2371_2180=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/p2571_defconfig u-boot/configs/p2571_defconfig +--- u-boot-2021.10/configs/p2571_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p2571_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,9 +4,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" + CONFIG_TEGRA210=y + CONFIG_TARGET_P2571=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/p2771-0000-000_defconfig u-boot/configs/p2771-0000-000_defconfig +--- u-boot-2021.10/configs/p2771-0000-000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p2771-0000-000_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_OFFSET=0xFFFFE000 + CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000" + CONFIG_TEGRA186=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/p2771-0000-500_defconfig u-boot/configs/p2771-0000-500_defconfig +--- u-boot-2021.10/configs/p2771-0000-500_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p2771-0000-500_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_OFFSET=0xFFFFE000 + CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500" + CONFIG_TEGRA186=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/P3041DS_defconfig u-boot/configs/P3041DS_defconfig +--- u-boot-2021.10/configs/P3041DS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P3041DS_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p3041ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P3041DS=y +@@ -13,6 +14,7 @@ + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -31,7 +33,12 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P3041DS_NAND_defconfig u-boot/configs/P3041DS_NAND_defconfig +--- u-boot-2021.10/configs/P3041DS_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P3041DS_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xE0000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p3041ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P3041DS=y +@@ -10,10 +11,13 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -32,7 +36,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -40,6 +49,7 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P3041DS_SDCARD_defconfig u-boot/configs/P3041DS_SDCARD_defconfig +--- u-boot-2021.10/configs/P3041DS_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P3041DS_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xCF400 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p3041ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P3041DS=y +@@ -10,10 +11,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -32,7 +37,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P3041DS_SPIFLASH_defconfig u-boot/configs/P3041DS_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P3041DS_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P3041DS_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p3041ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P3041DS=y +@@ -11,10 +12,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -33,7 +38,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/p3450-0000_defconfig u-boot/configs/p3450-0000_defconfig +--- u-boot-2021.10/configs/p3450-0000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/p3450-0000_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,9 +5,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" + CONFIG_TEGRA210=y + CONFIG_TARGET_P3450_0000=y ++CONFIG_SYS_LOAD_ADDR=0x80080000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/P4080DS_defconfig u-boot/configs/P4080DS_defconfig +--- u-boot-2021.10/configs/P4080DS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P4080DS_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p4080ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P4080DS=y +@@ -13,6 +14,7 @@ + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -31,7 +33,12 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/P4080DS_SDCARD_defconfig u-boot/configs/P4080DS_SDCARD_defconfig +--- u-boot-2021.10/configs/P4080DS_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P4080DS_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xCF400 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p4080ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P4080DS=y +@@ -10,10 +11,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -32,7 +37,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/P4080DS_SPIFLASH_defconfig u-boot/configs/P4080DS_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P4080DS_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P4080DS_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p4080ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P4080DS=y +@@ -11,10 +12,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -33,7 +38,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD_NOR_FLASH=y + CONFIG_FLASH_CFI_DRIVER=y +diff -ruN u-boot-2021.10/configs/P5040DS_defconfig u-boot/configs/P5040DS_defconfig +--- u-boot-2021.10/configs/P5040DS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P5040DS_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xEFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p5040ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P5040DS=y +@@ -13,6 +14,7 @@ + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -31,7 +33,12 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P5040DS_NAND_defconfig u-boot/configs/P5040DS_NAND_defconfig +--- u-boot-2021.10/configs/P5040DS_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P5040DS_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xE0000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p5040ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P5040DS=y +@@ -10,10 +11,13 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -33,7 +37,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -41,6 +50,7 @@ + CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_ELBC=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/P5040DS_SDCARD_defconfig u-boot/configs/P5040DS_SDCARD_defconfig +--- u-boot-2021.10/configs/P5040DS_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P5040DS_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -2,6 +2,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFF40000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xCF400 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p5040ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P5040DS=y +@@ -10,10 +11,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -32,7 +37,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/P5040DS_SPIFLASH_defconfig u-boot/configs/P5040DS_SPIFLASH_defconfig +--- u-boot-2021.10/configs/P5040DS_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/P5040DS_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="p5040ds" + CONFIG_MPC85xx=y + CONFIG_TARGET_P5040DS=y +@@ -11,10 +12,14 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -33,7 +38,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/parrot_r16_defconfig u-boot/configs/parrot_r16_defconfig +--- u-boot-2021.10/configs/parrot_r16_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/parrot_r16_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,10 +6,8 @@ + CONFIG_DRAM_CLK=600 + CONFIG_DRAM_ZQ=15291 + CONFIG_MMC0_CD_PIN="PD14" +-CONFIG_MMC2_PINS="PC" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_ID_DET="PD10" +-CONFIG_USB1_VBUS_PIN="PD12" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +diff -ruN u-boot-2021.10/configs/paz00_defconfig u-boot/configs/paz00_defconfig +--- u-boot-2021.10/configs/paz00_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/paz00_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_PAZ00=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # " +diff -ruN u-boot-2021.10/configs/pcm052_defconfig u-boot/configs/pcm052_defconfig +--- u-boot-2021.10/configs/pcm052_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pcm052_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_VF610=y + CONFIG_SYS_TEXT_BASE=0x3f401000 +@@ -7,11 +8,12 @@ + CONFIG_SYS_MEMTEST_END=0x87c00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xA0000 ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052" + CONFIG_ENV_OFFSET_REDUND=0xC0000 + CONFIG_TARGET_PCM052=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y +@@ -42,15 +44,12 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_I2C_EEPROM_BUS=2 +-CONFIG_SYS_EEPROM_SIZE=32768 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_NAND_VF610_NFC=y + CONFIG_NAND_VF610_NFC_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y +diff -ruN u-boot-2021.10/configs/pcm058_defconfig u-boot/configs/pcm058_defconfig +--- u-boot-2021.10/configs/pcm058_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pcm058_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,21 +11,21 @@ + CONFIG_MX6Q=y + CONFIG_MX6_OCRAM_256KB=y + CONFIG_TARGET_PCM058=y ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DM_GPIO=y + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x110000 + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_CMD_HDMIDETECT=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_DISPLAY_BOARDINFO_LATE=y +@@ -68,6 +68,7 @@ + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_MXS=y + CONFIG_NAND_MXS_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=20000000 +diff -ruN u-boot-2021.10/configs/peach-pi_defconfig u-boot/configs/peach-pi_defconfig +--- u-boot-2021.10/configs/peach-pi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/peach-pi_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x23E00000 +@@ -8,11 +10,13 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" + CONFIG_SPL_TEXT_BASE=0x02024410 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for Peach-Pi" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x23e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -38,6 +42,7 @@ + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_I2C_CROS_EC_TUNNEL=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y + CONFIG_CROS_EC_KEYB=y +diff -ruN u-boot-2021.10/configs/peach-pit_defconfig u-boot/configs/peach-pit_defconfig +--- u-boot-2021.10/configs/peach-pit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/peach-pit_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x23E00000 +@@ -7,11 +9,13 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" + CONFIG_SPL_TEXT_BASE=0x02024410 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for Peach-Pit" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x23e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -37,6 +41,7 @@ + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_I2C_CROS_EC_TUNNEL=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y + CONFIG_CROS_EC_KEYB=y +diff -ruN u-boot-2021.10/configs/pg_wcom_expu1_defconfig u-boot/configs/pg_wcom_expu1_defconfig +--- u-boot-2021.10/configs/pg_wcom_expu1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pg_wcom_expu1_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_PG_WCOM_EXPU1=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,11 +13,13 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1004000 + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -48,8 +51,9 @@ + CONFIG_ENV_ADDR_REDUND=0x60040000 + CONFIG_DM=y + CONFIG_BOOTCOUNT_LIMIT=y ++CONFIG_DDR_CLK_FREQ=50000000 + CONFIG_SYS_FSL_DDR3=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_LEGACY=y + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -58,6 +62,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_MARVELL=y + CONFIG_PHY_FIXED=y + CONFIG_DM_ETH=y +diff -ruN u-boot-2021.10/configs/pg_wcom_seli8_defconfig u-boot/configs/pg_wcom_seli8_defconfig +--- u-boot-2021.10/configs/pg_wcom_seli8_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pg_wcom_seli8_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_TARGET_PG_WCOM_SELI8=y + CONFIG_SYS_TEXT_BASE=0x60100000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,11 +13,13 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x1004000 + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8" + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +@@ -48,8 +51,9 @@ + CONFIG_ENV_ADDR_REDUND=0x60040000 + CONFIG_DM=y + CONFIG_BOOTCOUNT_LIMIT=y ++CONFIG_DDR_CLK_FREQ=50000000 + CONFIG_SYS_FSL_DDR3=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_LEGACY=y + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -58,6 +62,8 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_MARVELL=y + CONFIG_PHY_FIXED=y + CONFIG_DM_ETH=y +diff -ruN u-boot-2021.10/configs/phycore-am335x-r2-regor_defconfig u-boot/configs/phycore-am335x-r2-regor_defconfig +--- u-boot-2021.10/configs/phycore-am335x-r2-regor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore-am335x-r2-regor_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -9,8 +9,8 @@ + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=1000 + CONFIG_TARGET_PHYCORE_AM335X_R2=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -66,6 +66,11 @@ + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/phycore-am335x-r2-wega_defconfig u-boot/configs/phycore-am335x-r2-wega_defconfig +--- u-boot-2021.10/configs/phycore-am335x-r2-wega_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore-am335x-r2-wega_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -9,8 +9,8 @@ + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=1000 + CONFIG_TARGET_PHYCORE_AM335X_R2=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -66,6 +66,11 @@ + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y + CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +diff -ruN u-boot-2021.10/configs/phycore-imx8mm_defconfig u-boot/configs/phycore-imx8mm_defconfig +--- u-boot-2021.10/configs/phycore-imx8mm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore-imx8mm_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,24 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x10000 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x3C0000 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_PHYCORE_IMX8MM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x3E0000 ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + CONFIG_DEFAULT_FDT_FILE="oftree" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -38,6 +36,10 @@ + # CONFIG_CMD_IMPORTENV is not set + # CONFIG_CMD_CRC32 is not set + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_SIZE=4096 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_FUSE=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -66,14 +68,9 @@ + CONFIG_CLK_IMX8MM=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +-CONFIG_SYS_EEPROM_SIZE=4096 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y +diff -ruN u-boot-2021.10/configs/phycore-imx8mp_defconfig u-boot/configs/phycore-imx8mp_defconfig +--- u-boot-2021.10/configs/phycore-imx8mp_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore-imx8mp_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,21 +8,22 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x3C0000 + CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" + CONFIG_SPL_TEXT_BASE=0x920000 + CONFIG_TARGET_PHYCORE_IMX8MP=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" + CONFIG_DEFAULT_FDT_FILE="oftree" + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -38,6 +39,10 @@ + # CONFIG_CMD_IMPORTENV is not set + # CONFIG_CMD_CRC32 is not set + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_SIZE=4096 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_CLK=y + CONFIG_CMD_FUSE=y + CONFIG_CMD_GPIO=y +@@ -66,14 +71,10 @@ + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y + # CONFIG_SPL_DM_I2C is not set +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x51 +-CONFIG_SYS_EEPROM_SIZE=4096 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y +@@ -91,9 +92,11 @@ + CONFIG_PINCTRL=y + CONFIG_SPL_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y ++CONFIG_SPL_POWER_LEGACY=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_SYSRESET=y + CONFIG_SPL_SYSRESET=y +diff -ruN u-boot-2021.10/configs/phycore_pcl063_defconfig u-boot/configs/phycore_pcl063_defconfig +--- u-boot-2021.10/configs/phycore_pcl063_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore_pcl063_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -9,13 +9,13 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_MX6UL=y + CONFIG_TARGET_PCL063=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand" + CONFIG_SPL_TEXT_BASE=0x00909000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/phycore_pcl063_ull_defconfig u-boot/configs/phycore_pcl063_ull_defconfig +--- u-boot-2021.10/configs/phycore_pcl063_ull_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore_pcl063_ull_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,14 +7,14 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_MX6ULL=y + CONFIG_TARGET_PCL063_ULL=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc" + CONFIG_SPL_TEXT_BASE=0x908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/phycore-rk3288_defconfig u-boot/configs/phycore-rk3288_defconfig +--- u-boot-2021.10/configs/phycore-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/phycore-rk3288_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" +diff -ruN u-boot-2021.10/configs/pic32mzdask_defconfig u-boot/configs/pic32mzdask_defconfig +--- u-boot-2021.10/configs/pic32mzdask_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pic32mzdask_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,12 +4,14 @@ + CONFIG_SYS_MEMTEST_START=0x88000000 + CONFIG_SYS_MEMTEST_END=0x88080000 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" + CONFIG_MACH_PIC32=y + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x88500000 + CONFIG_BOOTDELAY=5 + CONFIG_SYS_PROMPT="dask # " + # CONFIG_CMD_SAVEENV is not set +diff -ruN u-boot-2021.10/configs/pico-dwarf-imx6ul_defconfig u-boot/configs/pico-dwarf-imx6ul_defconfig +--- u-boot-2021.10/configs/pico-dwarf-imx6ul_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-dwarf-imx6ul_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,14 +11,14 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6UL=y + CONFIG_TARGET_PICO_IMX6UL=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" +@@ -50,6 +50,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/pico-dwarf-imx7d_defconfig u-boot/configs/pico-dwarf-imx7d_defconfig +--- u-boot-2021.10/configs/pico-dwarf-imx7d_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-dwarf-imx7d_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" + CONFIG_SPL_I2C=y +@@ -53,6 +57,9 @@ + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -65,6 +72,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/pico-hobbit-imx6ul_defconfig u-boot/configs/pico-hobbit-imx6ul_defconfig +--- u-boot-2021.10/configs/pico-hobbit-imx6ul_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-hobbit-imx6ul_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,15 +11,15 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6UL=y + CONFIG_TARGET_PICO_IMX6UL=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" +@@ -51,6 +51,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/pico-hobbit-imx7d_defconfig u-boot/configs/pico-hobbit-imx7d_defconfig +--- u-boot-2021.10/configs/pico-hobbit-imx7d_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-hobbit-imx7d_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" + CONFIG_SPL_I2C=y +@@ -53,6 +57,9 @@ + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -65,6 +72,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/pico-imx6_defconfig u-boot/configs/pico-imx6_defconfig +--- u-boot-2021.10/configs/pico-imx6_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-imx6_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -9,11 +9,12 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6QDL=y + CONFIG_TARGET_PICO_IMX6=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-pico" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +@@ -21,7 +22,6 @@ + CONFIG_SPL_FIT_PRINT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run default_boot" + CONFIG_DEFAULT_FDT_FILE="ask" + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +diff -ruN u-boot-2021.10/configs/pico-imx6ul_defconfig u-boot/configs/pico-imx6ul_defconfig +--- u-boot-2021.10/configs/pico-imx6ul_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-imx6ul_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,15 +11,15 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6UL=y + CONFIG_TARGET_PICO_IMX6UL=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="ask" +@@ -54,6 +54,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/pico-imx7d_bl33_defconfig u-boot/configs/pico-imx7d_bl33_defconfig +--- u-boot-2021.10/configs/pico-imx7d_bl33_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-imx7d_bl33_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,17 +7,21 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_SPL_I2C=y + CONFIG_SPL_USB_HOST=y + CONFIG_SPL_USB_GADGET=y +@@ -48,6 +52,9 @@ + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y + CONFIG_PHYLIB=y +@@ -59,6 +66,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_CONS_INDEX=4 + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y +diff -ruN u-boot-2021.10/configs/pico-imx7d_defconfig u-boot/configs/pico-imx7d_defconfig +--- u-boot-2021.10/configs/pico-imx7d_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-imx7d_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="ask" + CONFIG_SPL_I2C=y +@@ -53,6 +57,9 @@ + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -65,6 +72,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/pico-imx8mq_defconfig u-boot/configs/pico-imx8mq_defconfig +--- u-boot-2021.10/configs/pico-imx8mq_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-imx8mq_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -3,17 +3,21 @@ + CONFIG_SYS_TEXT_BASE=0x40200000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x400000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x600000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_PICO_IMX8MQ=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_BOARD_INIT=y +@@ -42,17 +46,19 @@ + CONFIG_SYS_MMC_ENV_DEV=1 + CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_DM_ETH=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y ++CONFIG_SPL_POWER_LEGACY=y + CONFIG_POWER_DOMAIN=y + CONFIG_IMX8M_POWER_DOMAIN=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_POWER_I2C=y + CONFIG_DM_RESET=y + CONFIG_MXC_UART=y + CONFIG_DM_THERMAL=y +diff -ruN u-boot-2021.10/configs/pico-nymph-imx7d_defconfig u-boot/configs/pico-nymph-imx7d_defconfig +--- u-boot-2021.10/configs/pico-nymph-imx7d_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-nymph-imx7d_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" + CONFIG_SPL_I2C=y +@@ -53,6 +57,9 @@ + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -65,6 +72,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/pico-pi-imx6ul_defconfig u-boot/configs/pico-pi-imx6ul_defconfig +--- u-boot-2021.10/configs/pico-pi-imx6ul_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-pi-imx6ul_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -11,15 +11,15 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6UL=y + CONFIG_TARGET_PICO_IMX6UL=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" +@@ -51,6 +51,7 @@ + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/pico-pi-imx7d_defconfig u-boot/configs/pico-pi-imx7d_defconfig +--- u-boot-2021.10/configs/pico-pi-imx7d_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pico-pi-imx7d_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,17 +6,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_I2C_MXC_I2C4=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" + CONFIG_TARGET_PICO_IMX7D=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ARMV7_BOOT_SEC_DEFAULT=y + CONFIG_IMX_RDC=y + CONFIG_IMX_BOOTAUX=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" + CONFIG_SPL_I2C=y +@@ -53,6 +57,9 @@ + CONFIG_FASTBOOT_FLASH=y + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -65,6 +72,8 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX7=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/pine64_plus_defconfig u-boot/configs/pine64_plus_defconfig +--- u-boot-2021.10/configs/pine64_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pine64_plus_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,7 +8,6 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" + CONFIG_PHY_REALTEK=y +-CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y +diff -ruN u-boot-2021.10/configs/pinebook_defconfig u-boot/configs/pinebook_defconfig +--- u-boot-2021.10/configs/pinebook_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pinebook_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,6 +8,8 @@ + CONFIG_DRAM_ZQ=3881949 + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_PWM=y +diff -ruN u-boot-2021.10/configs/pinebook-pro-rk3399_defconfig u-boot/configs/pinebook-pro-rk3399_defconfig +--- u-boot-2021.10/configs/pinebook-pro-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pinebook-pro-rk3399_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,8 +10,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" +diff -ruN u-boot-2021.10/configs/pinecube_defconfig u-boot/configs/pinecube_defconfig +--- u-boot-2021.10/configs/pinecube_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pinecube_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,6 +8,11 @@ + CONFIG_DRAM_ODT_EN=y + CONFIG_I2C0_ENABLE=y + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_NETDEVICES is not set + CONFIG_AXP209_POWER=y + CONFIG_AXP_DCDC2_VOLT=1250 +diff -ruN u-boot-2021.10/configs/pine_h64_defconfig u-boot/configs/pine_h64_defconfig +--- u-boot-2021.10/configs/pine_h64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pine_h64_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,7 +7,7 @@ + CONFIG_MACPWR="PC16" + CONFIG_MMC0_CD_PIN="PF6" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB3_VBUS_PIN="PL5" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SPL_SPI_SUNXI=y + # CONFIG_PSCI_RESET is not set + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/plutux_defconfig u-boot/configs/plutux_defconfig +--- u-boot-2021.10/configs/plutux_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/plutux_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_PLUTUX=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +@@ -30,6 +31,7 @@ + CONFIG_SPL_DM=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NS16550=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/pm9261_defconfig u-boot/configs/pm9261_defconfig +--- u-boot-2021.10/configs/pm9261_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pm9261_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,8 +7,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x50000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek" ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/pm9263_defconfig u-boot/configs/pm9263_defconfig +--- u-boot-2021.10/configs/pm9263_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pm9263_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,8 +7,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x50000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/pm9g45_defconfig u-boot/configs/pm9g45_defconfig +--- u-boot-2021.10/configs/pm9g45_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pm9g45_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x73f00000 + CONFIG_TARGET_PM9G45=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x80000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/pogo_e02_defconfig u-boot/configs/pogo_e02_defconfig +--- u-boot-2021.10/configs/pogo_e02_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pogo_e02_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -10,6 +11,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02" + CONFIG_IDENT_STRING="\nPogo E02" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/polaroid_mid2407pxe03_defconfig u-boot/configs/polaroid_mid2407pxe03_defconfig +--- u-boot-2021.10/configs/polaroid_mid2407pxe03_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/polaroid_mid2407pxe03_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=63351 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/polaroid_mid2809pxe04_defconfig u-boot/configs/polaroid_mid2809pxe04_defconfig +--- u-boot-2021.10/configs/polaroid_mid2809pxe04_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/polaroid_mid2809pxe04_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=63351 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/poplar_defconfig u-boot/configs/poplar_defconfig +--- u-boot-2021.10/configs/poplar_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/poplar_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,9 +5,11 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x1F0000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" + CONFIG_IDENT_STRING="poplar" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_SYS_PROMPT="poplar# " + CONFIG_CMD_MMC=y +diff -ruN u-boot-2021.10/configs/popmetal-rk3288_defconfig u-boot/configs/popmetal-rk3288_defconfig +--- u-boot-2021.10/configs/popmetal-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/popmetal-rk3288_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" +diff -ruN u-boot-2021.10/configs/porter_defconfig u-boot/configs/porter_defconfig +--- u-boot-2021.10/configs/porter_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/porter_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Porter" + CONFIG_R8A7791=y + CONFIG_TARGET_PORTER=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/pov_protab2_ips9_defconfig u-boot/configs/pov_protab2_ips9_defconfig +--- u-boot-2021.10/configs/pov_protab2_ips9_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pov_protab2_ips9_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,9 +4,7 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN4I=y + CONFIG_DRAM_CLK=432 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="PH5" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 + CONFIG_VIDEO_LCD_POWER="PH8" +@@ -15,4 +13,7 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/puma-rk3399_defconfig u-boot/configs/puma-rk3399_defconfig +--- u-boot-2021.10/configs/puma-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/puma-rk3399_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -12,8 +13,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF180000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_MISC_INIT_R=y +@@ -44,6 +46,7 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_ROCKCHIP_GPIO=y + CONFIG_SYS_I2C_ROCKCHIP=y +@@ -67,6 +70,7 @@ + CONFIG_PHY_ROCKCHIP_TYPEC=y + CONFIG_DM_PMIC_FAN53555=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_REGULATOR_PWM=y + CONFIG_SPL_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/px30-core-ctouch2-px30_defconfig u-boot/configs/px30-core-ctouch2-px30_defconfig +--- u-boot-2021.10/configs/px30-core-ctouch2-px30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/px30-core-ctouch2-px30_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -17,6 +18,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/px30-core-edimm2.2-px30_defconfig u-boot/configs/px30-core-edimm2.2-px30_defconfig +--- u-boot-2021.10/configs/px30-core-edimm2.2-px30_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/px30-core-edimm2.2-px30_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -17,6 +18,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/pxm2_defconfig u-boot/configs/pxm2_defconfig +--- u-boot-2021.10/configs/pxm2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/pxm2_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,20 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=720 + CONFIG_TARGET_PXM2=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -75,10 +77,20 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/q8_a13_tablet_defconfig u-boot/configs/q8_a13_tablet_defconfig +--- u-boot-2021.10/configs/q8_a13_tablet_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/q8_a13_tablet_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PG0" +-CONFIG_USB0_VBUS_PIN="PG12" +-CONFIG_USB0_VBUS_DET="PG1" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +@@ -16,5 +14,8 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/q8_a23_tablet_800x480_defconfig u-boot/configs/q8_a23_tablet_800x480_defconfig +--- u-boot-2021.10/configs/q8_a23_tablet_800x480_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/q8_a23_tablet_800x480_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=63306 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/q8_a33_tablet_1024x600_defconfig u-boot/configs/q8_a33_tablet_1024x600_defconfig +--- u-boot-2021.10/configs/q8_a33_tablet_1024x600_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/q8_a33_tablet_1024x600_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=456 + CONFIG_DRAM_ZQ=15291 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/q8_a33_tablet_800x480_defconfig u-boot/configs/q8_a33_tablet_800x480_defconfig +--- u-boot-2021.10/configs/q8_a33_tablet_800x480_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/q8_a33_tablet_800x480_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=456 + CONFIG_DRAM_ZQ=15291 + CONFIG_MMC0_CD_PIN="PB4" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH8" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +diff -ruN u-boot-2021.10/configs/qemu_arm64_defconfig u-boot/configs/qemu_arm64_defconfig +--- u-boot-2021.10/configs/qemu_arm64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu_arm64_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,8 +4,10 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40200000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/qemu_arm_defconfig u-boot/configs/qemu_arm_defconfig +--- u-boot-2021.10/configs/qemu_arm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu_arm_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,10 +4,12 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_TARGET_QEMU_ARM_32BIT=y + CONFIG_ARMV7_LPAE=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40200000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/qemu-riscv32_defconfig u-boot/configs/qemu-riscv32_defconfig +--- u-boot-2021.10/configs/qemu-riscv32_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv32_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,8 +1,10 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y +diff -ruN u-boot-2021.10/configs/qemu-riscv32_smode_defconfig u-boot/configs/qemu-riscv32_smode_defconfig +--- u-boot-2021.10/configs/qemu-riscv32_smode_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv32_smode_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,9 +1,11 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y +@@ -13,3 +15,4 @@ + CONFIG_OF_PRIOR_STAGE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y ++CONFIG_SYSRESET_SBI=y +diff -ruN u-boot-2021.10/configs/qemu-riscv32_spl_defconfig u-boot/configs/qemu-riscv32_spl_defconfig +--- u-boot-2021.10/configs/qemu-riscv32_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv32_spl_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,11 +1,13 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" + CONFIG_SPL=y + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 + CONFIG_DISPLAY_CPUINFO=y +@@ -15,3 +17,4 @@ + CONFIG_OF_PRIOR_STAGE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y ++CONFIG_SYSRESET_SBI=y +diff -ruN u-boot-2021.10/configs/qemu-riscv64_defconfig u-boot/configs/qemu-riscv64_defconfig +--- u-boot-2021.10/configs/qemu-riscv64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv64_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,9 +1,11 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_ARCH_RV64I=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y +diff -ruN u-boot-2021.10/configs/qemu-riscv64_smode_defconfig u-boot/configs/qemu-riscv64_smode_defconfig +--- u-boot-2021.10/configs/qemu-riscv64_smode_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv64_smode_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,10 +1,12 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" +@@ -16,3 +18,4 @@ + CONFIG_OF_PRIOR_STAGE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y ++CONFIG_SYSRESET_SBI=y +diff -ruN u-boot-2021.10/configs/qemu-riscv64_spl_defconfig u-boot/configs/qemu-riscv64_spl_defconfig +--- u-boot-2021.10/configs/qemu-riscv64_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-riscv64_spl_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,12 +1,14 @@ + CONFIG_RISCV=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" + CONFIG_SPL=y + CONFIG_TARGET_QEMU_VIRT=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 + CONFIG_DISPLAY_CPUINFO=y +@@ -16,3 +18,4 @@ + CONFIG_OF_PRIOR_STAGE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y ++CONFIG_SYSRESET_SBI=y +diff -ruN u-boot-2021.10/configs/qemu-x86_64_defconfig u-boot/configs/qemu-x86_64_defconfig +--- u-boot-2021.10/configs/qemu-x86_64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/qemu-x86_64_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -34,10 +34,10 @@ + CONFIG_SPL_CPU=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_DM_SPI_FLASH=y +-CONFIG_SPL_NET_SUPPORT=y ++CONFIG_SPL_NET=y + CONFIG_SPL_PCI=y +-CONFIG_SPL_PCH_SUPPORT=y +-CONFIG_SPL_RTC_SUPPORT=y ++CONFIG_SPL_PCH=y ++CONFIG_SPL_RTC=y + CONFIG_CMD_CPU=y + CONFIG_CMD_BOOTEFI_SELFTEST=y + CONFIG_CMD_NVEDIT_EFI=y +diff -ruN u-boot-2021.10/configs/r2dplus_defconfig u-boot/configs/r2dplus_defconfig +--- u-boot-2021.10/configs/r2dplus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r2dplus_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -2,8 +2,10 @@ + CONFIG_SYS_TEXT_BASE=0x8FE00000 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus" + CONFIG_TARGET_R2DPLUS=y ++CONFIG_SYS_LOAD_ADDR=0x8e000000 + CONFIG_BOOTDELAY=-1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttySC0,115200" +diff -ruN u-boot-2021.10/configs/r7-tv-dongle_defconfig u-boot/configs/r7-tv-dongle_defconfig +--- u-boot-2021.10/configs/r7-tv-dongle_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r7-tv-dongle_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -4,9 +4,12 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=384 +-CONFIG_USB1_VBUS_PIN="PG13" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP152_POWER=y + CONFIG_CONS_INDEX=2 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/r8a774a1_beacon_defconfig u-boot/configs/r8a774a1_beacon_defconfig +--- u-boot-2021.10/configs/r8a774a1_beacon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a774a1_beacon_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -3,12 +3,14 @@ + CONFIG_SYS_TEXT_BASE=0x50000000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit" + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_BEACON_RZG2M=y + # CONFIG_SPL is not set + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +diff -ruN u-boot-2021.10/configs/r8a774b1_beacon_defconfig u-boot/configs/r8a774b1_beacon_defconfig +--- u-boot-2021.10/configs/r8a774b1_beacon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a774b1_beacon_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -3,12 +3,14 @@ + CONFIG_SYS_TEXT_BASE=0x50000000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit" + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_BEACON_RZG2N=y + # CONFIG_SPL is not set + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +diff -ruN u-boot-2021.10/configs/r8a774e1_beacon_defconfig u-boot/configs/r8a774e1_beacon_defconfig +--- u-boot-2021.10/configs/r8a774e1_beacon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a774e1_beacon_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -3,12 +3,14 @@ + CONFIG_SYS_TEXT_BASE=0x50000000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_OFFSET=0x0 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit" + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_BEACON_RZG2H=y + # CONFIG_SPL is not set + CONFIG_LTO=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +diff -ruN u-boot-2021.10/configs/r8a77970_eagle_defconfig u-boot/configs/r8a77970_eagle_defconfig +--- u-boot-2021.10/configs/r8a77970_eagle_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a77970_eagle_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,11 +6,13 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x700000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6318000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_EAGLE=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/r8a77980_condor_defconfig u-boot/configs/r8a77980_condor_defconfig +--- u-boot-2021.10/configs/r8a77980_condor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a77980_condor_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -6,11 +6,13 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x700000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6318000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_CONDOR=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/r8a77990_ebisu_defconfig u-boot/configs/r8a77990_ebisu_defconfig +--- u-boot-2021.10/configs/r8a77990_ebisu_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a77990_ebisu_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,11 +5,13 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xFFFE0000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6318000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_EBISU=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +@@ -18,6 +20,7 @@ + CONFIG_UPDATE_TFTP=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -54,10 +57,6 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x70 +-CONFIG_SYS_I2C_EEPROM_BUS=7 +-CONFIG_SYS_EEPROM_SIZE=128 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y + CONFIG_MMC_HS400_SUPPORT=y +diff -ruN u-boot-2021.10/configs/r8a77995_draak_defconfig u-boot/configs/r8a77995_draak_defconfig +--- u-boot-2021.10/configs/r8a77995_draak_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a77995_draak_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,11 +5,13 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xFFFE0000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6318000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_DRAAK=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/r8a779a0_falcon_defconfig u-boot/configs/r8a779a0_falcon_defconfig +--- u-boot-2021.10/configs/r8a779a0_falcon_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/r8a779a0_falcon_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC00000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6338000 +@@ -12,6 +13,7 @@ + CONFIG_TARGET_FALCON=y + # CONFIG_PSCI_RESET is not set + CONFIG_ARMV8_PSCI=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/radxa-zero_defconfig u-boot/configs/radxa-zero_defconfig +--- u-boot-2021.10/configs/radxa-zero_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/radxa-zero_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -0,0 +1,65 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" radxa-zero" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_ETH=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN u-boot-2021.10/configs/rastaban_defconfig u-boot/configs/rastaban_defconfig +--- u-boot-2021.10/configs/rastaban_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rastaban_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,21 +7,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=300 + CONFIG_TARGET_RASTABAN=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x2E0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -76,10 +78,19 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/rcar3_salvator-x_defconfig u-boot/configs/rcar3_salvator-x_defconfig +--- u-boot-2021.10/configs/rcar3_salvator-x_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rcar3_salvator-x_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -3,11 +3,13 @@ + CONFIG_ARCH_RMOBILE=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xFFFE0000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6338000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_SALVATOR_X=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +@@ -15,6 +17,7 @@ + CONFIG_UPDATE_TFTP=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -55,10 +58,6 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x70 +-CONFIG_SYS_I2C_EEPROM_BUS=7 +-CONFIG_SYS_EEPROM_SIZE=128 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y + CONFIG_MMC_HS400_SUPPORT=y +diff -ruN u-boot-2021.10/configs/rcar3_ulcb_defconfig u-boot/configs/rcar3_ulcb_defconfig +--- u-boot-2021.10/configs/rcar3_ulcb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rcar3_ulcb_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -5,11 +5,13 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xFFFE0000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6338000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_ULCB=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +@@ -17,6 +19,7 @@ + CONFIG_UPDATE_TFTP=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -56,10 +59,6 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x70 +-CONFIG_SYS_I2C_EEPROM_BUS=7 +-CONFIG_SYS_EEPROM_SIZE=128 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=7 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y + CONFIG_MMC_HS400_SUPPORT=y +diff -ruN u-boot-2021.10/configs/riotboard_defconfig u-boot/configs/riotboard_defconfig +--- u-boot-2021.10/configs/riotboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/riotboard_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -7,17 +7,21 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x60000 ++CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6s1g.cfg" + CONFIG_MX6S=y + CONFIG_TARGET_EMBESTMX6BOARDS=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" + CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -40,6 +44,9 @@ + CONFIG_SYS_MMC_ENV_DEV=2 + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/roc-cc-rk3308_defconfig u-boot/configs/roc-cc-rk3308_defconfig +--- u-boot-2021.10/configs/roc-cc-rk3308_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/roc-cc-rk3308_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00600000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -13,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF0C0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/roc-cc-rk3328_defconfig u-boot/configs/roc-cc-rk3328_defconfig +--- u-boot-2021.10/configs/roc-cc-rk3328_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/roc-cc-rk3328_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -15,6 +16,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -69,6 +71,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_REGULATOR_PWM=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/rock2_defconfig u-boot/configs/rock2_defconfig +--- u-boot-2021.10/configs/rock2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock2_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00000000 + CONFIG_NR_DRAM_BANKS=1 +@@ -12,6 +13,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" +diff -ruN u-boot-2021.10/configs/rock64-rk3328_defconfig u-boot/configs/rock64-rk3328_defconfig +--- u-boot-2021.10/configs/rock64-rk3328_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock64-rk3328_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -15,6 +16,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -68,6 +70,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_REGULATOR_PWM=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/rock960-rk3399_defconfig u-boot/configs/rock960-rk3399_defconfig +--- u-boot-2021.10/configs/rock960-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock960-rk3399_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ENV_OFFSET=0x3F8000 +@@ -8,6 +9,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/rock_defconfig u-boot/configs/rock_defconfig +--- u-boot-2021.10/configs/rock_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_ROCKCHIP=y +@@ -14,6 +16,7 @@ + CONFIG_DEBUG_UART_BASE=0x20064000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x60800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rock-pi-4c-rk3399_defconfig u-boot/configs/rock-pi-4c-rk3399_defconfig +--- u-boot-2021.10/configs/rock-pi-4c-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock-pi-4c-rk3399_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/rock-pi-4-rk3399_defconfig u-boot/configs/rock-pi-4-rk3399_defconfig +--- u-boot-2021.10/configs/rock-pi-4-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock-pi-4-rk3399_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -9,6 +10,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/rock-pi-e-rk3328_defconfig u-boot/configs/rock-pi-e-rk3328_defconfig +--- u-boot-2021.10/configs/rock-pi-e-rk3328_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock-pi-e-rk3328_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -16,6 +17,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y + CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -70,6 +72,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_REGULATOR_PWM=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/rock-pi-n10-rk3399pro_defconfig u-boot/configs/rock-pi-n10-rk3399pro_defconfig +--- u-boot-2021.10/configs/rock-pi-n10-rk3399pro_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock-pi-n10-rk3399pro_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -10,6 +11,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" + # CONFIG_CONSOLE_MUX is not set +diff -ruN u-boot-2021.10/configs/rock-pi-n8-rk3288_defconfig u-boot/configs/rock-pi-n8-rk3288_defconfig +--- u-boot-2021.10/configs/rock-pi-n8-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rock-pi-n8-rk3288_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_ROCKCHIP=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_SILENT_CONSOLE=y +diff -ruN u-boot-2021.10/configs/rockpro64-rk3399_defconfig u-boot/configs/rockpro64-rk3399_defconfig +--- u-boot-2021.10/configs/rockpro64-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rockpro64-rk3399_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -10,8 +11,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/roc-pc-mezzanine-rk3399_defconfig u-boot/configs/roc-pc-mezzanine-rk3399_defconfig +--- u-boot-2021.10/configs/roc-pc-mezzanine-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/roc-pc-mezzanine-rk3399_defconfig 2021-11-01 17:10:14.192929648 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -12,8 +13,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/roc-pc-rk3399_defconfig u-boot/configs/roc-pc-rk3399_defconfig +--- u-boot-2021.10/configs/roc-pc-rk3399_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/roc-pc-rk3399_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_SPL_GPIO=y +@@ -12,8 +13,9 @@ + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff -ruN u-boot-2021.10/configs/rpi_0_w_defconfig u-boot/configs/rpi_0_w_defconfig +--- u-boot-2021.10/configs/rpi_0_w_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_0_w_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rpi_2_defconfig u-boot/configs/rpi_2_defconfig +--- u-boot-2021.10/configs/rpi_2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_2_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_BCM283X=y + CONFIG_SYS_TEXT_BASE=0x00008000 +@@ -7,6 +8,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rpi_3_32b_defconfig u-boot/configs/rpi_3_32b_defconfig +--- u-boot-2021.10/configs/rpi_3_32b_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_3_32b_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_BCM283X=y + CONFIG_SYS_TEXT_BASE=0x00008000 +@@ -8,6 +9,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rpi_3_b_plus_defconfig u-boot/configs/rpi_3_b_plus_defconfig +--- u-boot-2021.10/configs/rpi_3_b_plus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_3_b_plus_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rpi_3_defconfig u-boot/configs/rpi_3_defconfig +--- u-boot-2021.10/configs/rpi_3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_3_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rpi_4_32b_defconfig u-boot/configs/rpi_4_32b_defconfig +--- u-boot-2021.10/configs/rpi_4_32b_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_4_32b_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="pci enum; usb start;" +diff -ruN u-boot-2021.10/configs/rpi_4_defconfig u-boot/configs/rpi_4_defconfig +--- u-boot-2021.10/configs/rpi_4_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_4_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="pci enum; usb start;" +diff -ruN u-boot-2021.10/configs/rpi_arm64_defconfig u-boot/configs/rpi_arm64_defconfig +--- u-boot-2021.10/configs/rpi_arm64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_arm64_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="pci enum; usb start;" +diff -ruN u-boot-2021.10/configs/rpi_defconfig u-boot/configs/rpi_defconfig +--- u-boot-2021.10/configs/rpi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rpi_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -7,6 +7,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/rut_defconfig u-boot/configs/rut_defconfig +--- u-boot-2021.10/configs/rut_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/rut_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -7,20 +7,22 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-rut" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=600 + CONFIG_TARGET_RUT=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -42,6 +44,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="U-Boot# " + CONFIG_CMD_ASKENV=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y +@@ -75,10 +78,19 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/s400_defconfig u-boot/configs/s400_defconfig +--- u-boot-2021.10/configs/s400_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/s400_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" s400" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/s5p4418_nanopi2_defconfig u-boot/configs/s5p4418_nanopi2_defconfig +--- u-boot-2021.10/configs/s5p4418_nanopi2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/s5p4418_nanopi2_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0xb0000000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x2E0200 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2" + CONFIG_TARGET_NANOPI2=y +@@ -14,6 +15,7 @@ + CONFIG_ROOT_DEV=1 + CONFIG_BOOT_PART=1 + CONFIG_ROOT_PART=2 ++CONFIG_SYS_LOAD_ADDR=0x71080000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SUPPORT_RAW_INITRD=y +diff -ruN u-boot-2021.10/configs/s5pc210_universal_defconfig u-boot/configs/s5pc210_universal_defconfig +--- u-boot-2021.10/configs/s5pc210_universal_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/s5pc210_universal_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x44800000 +@@ -7,8 +8,10 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x7000 ++CONFIG_SYS_MALLOC_LEN=0x5001000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x44800000 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="Please use defined boot" + # CONFIG_USE_BOOTCOMMAND is not set +diff -ruN u-boot-2021.10/configs/s5p_goni_defconfig u-boot/configs/s5p_goni_defconfig +--- u-boot-2021.10/configs/s5p_goni_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/s5p_goni_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -5,9 +5,11 @@ + CONFIG_NR_DRAM_BANKS=3 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x7000 ++CONFIG_SYS_MALLOC_LEN=0x5001000 + CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" + CONFIG_TARGET_S5P_GONI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x34000000 + # CONFIG_AUTOBOOT is not set + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}" +diff -ruN u-boot-2021.10/configs/sagem_f@st1704_ram_defconfig u-boot/configs/sagem_f@st1704_ram_defconfig +--- u-boot-2021.10/configs/sagem_f@st1704_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sagem_f@st1704_ram_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -6,10 +7,13 @@ + CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6338=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/sam9x60ek_mmc_defconfig u-boot/configs/sam9x60ek_mmc_defconfig +--- u-boot-2021.10/configs/sam9x60ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sam9x60ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,16 +1,19 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 + CONFIG_TARGET_SAM9X60EK=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfffff200 + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -44,6 +47,7 @@ + CONFIG_CLK_AT91=y + CONFIG_AT91_GENERIC_CLK=y + CONFIG_AT91_SAM9X60_PLL=y ++CONFIG_CPU=y + CONFIG_AT91_GPIO=y + CONFIG_DM_I2C=y + CONFIG_SYS_I2C_AT91=y +@@ -56,6 +60,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_MICREL=y + CONFIG_DM_ETH=y + CONFIG_MACB=y +diff -ruN u-boot-2021.10/configs/sam9x60ek_nandflash_defconfig u-boot/configs/sam9x60ek_nandflash_defconfig +--- u-boot-2021.10/configs/sam9x60ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sam9x60ek_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,9 +1,11 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 + CONFIG_TARGET_SAM9X60EK=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=8 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -11,6 +13,7 @@ + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -46,6 +49,7 @@ + CONFIG_CLK_AT91=y + CONFIG_AT91_GENERIC_CLK=y + CONFIG_AT91_SAM9X60_PLL=y ++CONFIG_CPU=y + CONFIG_AT91_GPIO=y + CONFIG_DM_I2C=y + CONFIG_SYS_I2C_AT91=y +@@ -57,6 +61,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_PHY_MICREL=y + CONFIG_DM_ETH=y + CONFIG_MACB=y +diff -ruN u-boot-2021.10/configs/sam9x60ek_qspiflash_defconfig u-boot/configs/sam9x60ek_qspiflash_defconfig +--- u-boot-2021.10/configs/sam9x60ek_qspiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sam9x60ek_qspiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,10 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 + CONFIG_TARGET_SAM9X60EK=y + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_NR_DRAM_BANKS=8 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x81000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_QSPI_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -54,6 +57,7 @@ + CONFIG_CLK_AT91=y + CONFIG_AT91_GENERIC_CLK=y + CONFIG_AT91_SAM9X60_PLL=y ++CONFIG_CPU=y + CONFIG_AT91_GPIO=y + CONFIG_DM_I2C=y + CONFIG_SYS_I2C_AT91=y +@@ -67,6 +71,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPI_FLASH_SPANSION=y +diff -ruN u-boot-2021.10/configs/sama5d27_giantboard_defconfig u-boot/configs/sama5d27_giantboard_defconfig +--- u-boot-2021.10/configs/sama5d27_giantboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_giantboard_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d27_som1_ek_mmc1_defconfig u-boot/configs/sama5d27_som1_ek_mmc1_defconfig +--- u-boot-2021.10/configs/sama5d27_som1_ek_mmc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_som1_ek_mmc1_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 +@@ -11,8 +12,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -22,6 +23,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d27_som1_ek_mmc_defconfig u-boot/configs/sama5d27_som1_ek_mmc_defconfig +--- u-boot-2021.10/configs/sama5d27_som1_ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_som1_ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d27_som1_ek_qspiflash_defconfig u-boot/configs/sama5d27_som1_ek_qspiflash_defconfig +--- u-boot-2021.10/configs/sama5d27_som1_ek_qspiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_som1_ek_qspiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_QSPI_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d27_wlsom1_ek_mmc_defconfig u-boot/configs/sama5d27_wlsom1_ek_mmc_defconfig +--- u-boot-2021.10/configs/sama5d27_wlsom1_ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_wlsom1_ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +@@ -10,8 +11,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -21,6 +22,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d27_wlsom1_ek_qspiflash_defconfig u-boot/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +--- u-boot-2021.10/configs/sama5d27_wlsom1_ek_qspiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d27_wlsom1_ek_qspiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 + CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +@@ -11,16 +12,17 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xf801c000 + CONFIG_DEBUG_UART_CLOCK=82000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_QSPI_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d2_icp_mmc_defconfig u-boot/configs/sama5d2_icp_mmc_defconfig +--- u-boot-2021.10/configs/sama5d2_icp_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_icp_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -10,8 +11,8 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -21,6 +22,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d2_icp_qspiflash_defconfig u-boot/configs/sama5d2_icp_qspiflash_defconfig +--- u-boot-2021.10/configs/sama5d2_icp_qspiflash_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/sama5d2_icp_qspiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -0,0 +1,104 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_CPU_INIT=y ++CONFIG_ARCH_AT91=y ++CONFIG_SYS_TEXT_BASE=0x26f00000 ++CONFIG_TARGET_SAMA5D2_ICP=y ++CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_SYS_MEMTEST_START=0x20000000 ++CONFIG_SYS_MEMTEST_END=0x40000000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" ++CONFIG_DEBUG_UART_BOARD_INIT=y ++CONFIG_DEBUG_UART_BASE=0xf801c000 ++CONFIG_DEBUG_UART_CLOCK=83000000 ++CONFIG_DEBUG_UART=y ++CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 ++CONFIG_SYS_BOOT_GET_CMDLINE=y ++CONFIG_SYS_BOOT_GET_KBD=y ++CONFIG_FIT=y ++CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" ++CONFIG_QSPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_BOOTDELAY=3 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyS0,115200 earlycon earlyprintk=serial,ttyS0, ignore_loglevel root=/dev/mmcblk0p2 memtest=0 rootfstype=ext4 rw rootwait" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_CONFIG=y ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MEMTEST=y ++CONFIG_SYS_ALT_MEMTEST=y ++CONFIG_CMD_CLK=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_I2C=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_SDRAM=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_GETTIME=y ++CONFIG_CMD_TIMER=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_OF_CONTROL=y ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_USE_ENV_SPI_BUS=y ++CONFIG_ENV_SPI_BUS=2 ++CONFIG_USE_ENV_SPI_CS=y ++CONFIG_ENV_SPI_CS=0 ++CONFIG_USE_ENV_SPI_MAX_HZ=y ++CONFIG_ENV_SPI_MAX_HZ=66000000 ++CONFIG_USE_ENV_SPI_MODE=y ++CONFIG_ENV_SPI_MODE=0x0 ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM=y ++CONFIG_CLK=y ++CONFIG_CLK_AT91=y ++CONFIG_AT91_UTMI=y ++CONFIG_AT91_H32MX=y ++CONFIG_AT91_GENERIC_CLK=y ++CONFIG_ATMEL_PIO4=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_AT91=y ++CONFIG_I2C_EEPROM=y ++CONFIG_MICROCHIP_FLEXCOM=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ATMEL=y ++CONFIG_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SF_DEFAULT_BUS=2 ++CONFIG_SF_DEFAULT_SPEED=66000000 ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_ATMEL=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_DM_ETH=y ++CONFIG_MACB=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_AT91PIO4=y ++CONFIG_DM_SERIAL=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_ATMEL_USART=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ATMEL_QSPI=y ++CONFIG_TIMER=y ++CONFIG_ATMEL_PIT_TIMER=y ++CONFIG_USB=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_ATMEL_USBA=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SPL_OF_LIBFDT=y ++# CONFIG_EFI_LOADER_HII is not set +diff -ruN u-boot-2021.10/configs/sama5d2_ptc_ek_mmc_defconfig u-boot/configs/sama5d2_ptc_ek_mmc_defconfig +--- u-boot-2021.10/configs/sama5d2_ptc_ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_ptc_ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -13,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=82000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_SD_BOOT=y +@@ -56,6 +58,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_ETH=y + CONFIG_MACB=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/sama5d2_ptc_ek_nandflash_defconfig u-boot/configs/sama5d2_ptc_ek_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d2_ptc_ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_ptc_ek_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -13,6 +14,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" + CONFIG_NAND_BOOT=y +@@ -56,6 +58,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_ETH=y + CONFIG_MACB=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/sama5d2_xplained_emmc_defconfig u-boot/configs/sama5d2_xplained_emmc_defconfig +--- u-boot-2021.10/configs/sama5d2_xplained_emmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_xplained_emmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -11,8 +12,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -22,6 +23,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d2_xplained_mmc_defconfig u-boot/configs/sama5d2_xplained_mmc_defconfig +--- u-boot-2021.10/configs/sama5d2_xplained_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_xplained_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" + CONFIG_SD_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d2_xplained_qspiflash_defconfig u-boot/configs/sama5d2_xplained_qspiflash_defconfig +--- u-boot-2021.10/configs/sama5d2_xplained_qspiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_xplained_qspiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" + CONFIG_QSPI_BOOT=y +diff -ruN u-boot-2021.10/configs/sama5d2_xplained_spiflash_defconfig u-boot/configs/sama5d2_xplained_spiflash_defconfig +--- u-boot-2021.10/configs/sama5d2_xplained_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d2_xplained_spiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -15,16 +16,17 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xf8020000 + CONFIG_DEBUG_UART_CLOCK=83000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +diff -ruN u-boot-2021.10/configs/sama5d36ek_cmp_mmc_defconfig u-boot/configs/sama5d36ek_cmp_mmc_defconfig +--- u-boot-2021.10/configs/sama5d36ek_cmp_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d36ek_cmp_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -13,6 +14,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -47,6 +49,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d36ek_cmp_nandflash_defconfig u-boot/configs/sama5d36ek_cmp_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d36ek_cmp_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d36ek_cmp_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -13,6 +14,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -47,6 +49,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_PMECC_CAP=4 + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d36ek_cmp_spiflash_defconfig u-boot/configs/sama5d36ek_cmp_spiflash_defconfig +--- u-boot-2021.10/configs/sama5d36ek_cmp_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d36ek_cmp_spiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -15,6 +16,7 @@ + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -49,6 +51,7 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d3xek_mmc_defconfig u-boot/configs/sama5d3xek_mmc_defconfig +--- u-boot-2021.10/configs/sama5d3xek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d3xek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -71,6 +73,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d3xek_nandflash_defconfig u-boot/configs/sama5d3xek_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d3xek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d3xek_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -11,7 +12,7 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -20,6 +21,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -69,6 +71,13 @@ + CONFIG_NAND_ATMEL=y + CONFIG_PMECC_CAP=4 + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d3xek_spiflash_defconfig u-boot/configs/sama5d3xek_spiflash_defconfig +--- u-boot-2021.10/configs/sama5d3xek_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d3xek_spiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -15,16 +16,17 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xffffee00 + CONFIG_DEBUG_UART_CLOCK=132000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -72,6 +74,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d3_xplained_mmc_defconfig u-boot/configs/sama5d3_xplained_mmc_defconfig +--- u-boot-2021.10/configs/sama5d3_xplained_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d3_xplained_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -68,6 +70,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=4 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_ETH=y + CONFIG_MACB=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/sama5d3_xplained_nandflash_defconfig u-boot/configs/sama5d3_xplained_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d3_xplained_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d3_xplained_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -11,7 +12,7 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" + CONFIG_SPL_TEXT_BASE=0x300000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -20,6 +21,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -67,6 +69,13 @@ + CONFIG_NAND_ATMEL=y + CONFIG_PMECC_CAP=4 + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_ETH=y + CONFIG_MACB=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/sama5d4ek_mmc_defconfig u-boot/configs/sama5d4ek_mmc_defconfig +--- u-boot-2021.10/configs/sama5d4ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -62,6 +64,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d4ek_nandflash_defconfig u-boot/configs/sama5d4ek_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d4ek_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4ek_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -11,7 +12,7 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -20,6 +21,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -62,6 +64,13 @@ + CONFIG_NAND_ATMEL=y + CONFIG_PMECC_CAP=8 + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d4ek_spiflash_defconfig u-boot/configs/sama5d4ek_spiflash_defconfig +--- u-boot-2021.10/configs/sama5d4ek_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4ek_spiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -15,16 +16,17 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfc00c000 + CONFIG_DEBUG_UART_CLOCK=88000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -65,6 +67,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d4_xplained_mmc_defconfig u-boot/configs/sama5d4_xplained_mmc_defconfig +--- u-boot-2021.10/configs/sama5d4_xplained_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4_xplained_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -12,8 +13,8 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -23,6 +24,7 @@ + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -64,6 +66,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d4_xplained_nandflash_defconfig u-boot/configs/sama5d4_xplained_nandflash_defconfig +--- u-boot-2021.10/configs/sama5d4_xplained_nandflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4_xplained_nandflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -11,7 +12,7 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y +@@ -20,6 +21,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x100000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_NAND_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -64,6 +66,13 @@ + CONFIG_NAND_ATMEL=y + CONFIG_PMECC_CAP=8 + CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x1000 ++CONFIG_SYS_NAND_OOBSIZE=0xe0 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama5d4_xplained_spiflash_defconfig u-boot/configs/sama5d4_xplained_spiflash_defconfig +--- u-boot-2021.10/configs/sama5d4_xplained_spiflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama5d4_xplained_spiflash_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x26f00000 +@@ -15,16 +16,17 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" + CONFIG_SPL_TEXT_BASE=0x200000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BOARD_INIT=y + CONFIG_DEBUG_UART_BASE=0xfc00c000 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 +@@ -70,6 +72,9 @@ + CONFIG_NAND_ATMEL=y + CONFIG_ATMEL_NAND_HW_PMECC=y + CONFIG_PMECC_CAP=8 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ATMEL=y +diff -ruN u-boot-2021.10/configs/sama7g5ek_mmc1_defconfig u-boot/configs/sama7g5ek_mmc1_defconfig +--- u-boot-2021.10/configs/sama7g5ek_mmc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama7g5ek_mmc1_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -14,10 +14,13 @@ + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x62000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" + CONFIG_MISC_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/sama7g5ek_mmc_defconfig u-boot/configs/sama7g5ek_mmc_defconfig +--- u-boot-2021.10/configs/sama7g5ek_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sama7g5ek_mmc_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -14,10 +14,13 @@ + CONFIG_DEBUG_UART_CLOCK=200000000 + CONFIG_DEBUG_UART=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x62000000 + CONFIG_FIT=y + CONFIG_SD_BOOT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7g5ek.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" + CONFIG_MISC_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/sandbox64_defconfig u-boot/configs/sandbox64_defconfig +--- u-boot-2021.10/configs/sandbox64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sandbox64_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -3,12 +3,14 @@ + CONFIG_SYS_MEMTEST_START=0x00100000 + CONFIG_SYS_MEMTEST_END=0x00101000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox64" + CONFIG_PRE_CON_BUF_ADDR=0x100000 + CONFIG_BOOTSTAGE_STASH_ADDR=0x0 + CONFIG_SANDBOX64=y + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -223,7 +225,9 @@ + CONFIG_SANDBOX_OSD=y + CONFIG_SPLASH_SCREEN_ALIGN=y + CONFIG_VIDEO_BMP_RLE8=y ++# CONFIG_WATCHDOG_AUTOSTART is not set + CONFIG_WDT=y ++CONFIG_WDT_GPIO=y + CONFIG_WDT_SANDBOX=y + CONFIG_FS_CBFS=y + CONFIG_FS_CRAMFS=y +diff -ruN u-boot-2021.10/configs/sandbox_defconfig u-boot/configs/sandbox_defconfig +--- u-boot-2021.10/configs/sandbox_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sandbox_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -3,11 +3,13 @@ + CONFIG_SYS_MEMTEST_START=0x00100000 + CONFIG_SYS_MEMTEST_END=0x00101000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" + CONFIG_PRE_CON_BUF_ADDR=0xf0000 + CONFIG_BOOTSTAGE_STASH_ADDR=0x0 + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_RSASSA_PSS=y +@@ -281,7 +283,9 @@ + CONFIG_W1_GPIO=y + CONFIG_W1_EEPROM=y + CONFIG_W1_EEPROM_SANDBOX=y ++# CONFIG_WATCHDOG_AUTOSTART is not set + CONFIG_WDT=y ++CONFIG_WDT_GPIO=y + CONFIG_WDT_SANDBOX=y + CONFIG_FS_CBFS=y + CONFIG_FS_CRAMFS=y +diff -ruN u-boot-2021.10/configs/sandbox_flattree_defconfig u-boot/configs/sandbox_flattree_defconfig +--- u-boot-2021.10/configs/sandbox_flattree_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sandbox_flattree_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -3,10 +3,12 @@ + CONFIG_SYS_MEMTEST_START=0x00100000 + CONFIG_SYS_MEMTEST_END=0x00101000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" + CONFIG_BOOTSTAGE_STASH_ADDR=0x0 + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/sandbox_noinst_defconfig u-boot/configs/sandbox_noinst_defconfig +--- u-boot-2021.10/configs/sandbox_noinst_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sandbox_noinst_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,12 +1,14 @@ + CONFIG_SYS_TEXT_BASE=0x200000 ++CONFIG_SPL_GPIO=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SYS_MEMTEST_START=0x00100000 + CONFIG_SYS_MEMTEST_END=0x00101000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y +@@ -14,6 +16,7 @@ + CONFIG_SANDBOX_SPL=y + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -31,7 +34,7 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_RTC_SUPPORT=y ++CONFIG_SPL_RTC=y + CONFIG_CMD_CPU=y + CONFIG_CMD_LICENSE=y + CONFIG_CMD_BOOTZ=y +@@ -120,6 +123,7 @@ + CONFIG_I2C_CROS_EC_TUNNEL=y + CONFIG_I2C_CROS_EC_LDO=y + CONFIG_DM_I2C_GPIO=y ++# CONFIG_SPL_DM_I2C_GPIO is not set + CONFIG_SYS_I2C_SANDBOX=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y +diff -ruN u-boot-2021.10/configs/sandbox_spl_defconfig u-boot/configs/sandbox_spl_defconfig +--- u-boot-2021.10/configs/sandbox_spl_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sandbox_spl_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,12 +1,14 @@ + CONFIG_SYS_TEXT_BASE=0x200000 ++CONFIG_SPL_GPIO=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SYS_MEMTEST_START=0x00100000 + CONFIG_SYS_MEMTEST_END=0x00101000 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y +@@ -14,6 +16,7 @@ + CONFIG_SANDBOX_SPL=y + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -32,7 +35,7 @@ + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_RTC_SUPPORT=y ++CONFIG_SPL_RTC=y + CONFIG_CMD_CPU=y + CONFIG_CMD_LICENSE=y + CONFIG_CMD_BOOTZ=y +@@ -122,6 +125,7 @@ + CONFIG_I2C_CROS_EC_TUNNEL=y + CONFIG_I2C_CROS_EC_LDO=y + CONFIG_DM_I2C_GPIO=y ++# CONFIG_SPL_DM_I2C_GPIO is not set + CONFIG_SYS_I2C_SANDBOX=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y +diff -ruN u-boot-2021.10/configs/SBx81LIFKW_defconfig u-boot/configs/SBx81LIFKW_defconfig +--- u-boot-2021.10/configs/SBx81LIFKW_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/SBx81LIFKW_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw" + CONFIG_IDENT_STRING="\nSBx81LIFKW" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SILENT_U_BOOT_ONLY=y +diff -ruN u-boot-2021.10/configs/SBx81LIFXCAT_defconfig u-boot/configs/SBx81LIFXCAT_defconfig +--- u-boot-2021.10/configs/SBx81LIFXCAT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/SBx81LIFXCAT_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_KIRKWOOD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat" + CONFIG_IDENT_STRING="\nSBx81LIFXCAT" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_BOOTDELAY=3 + CONFIG_SILENT_CONSOLE=y + CONFIG_SILENT_U_BOOT_ONLY=y +diff -ruN u-boot-2021.10/configs/seaboard_defconfig u-boot/configs/seaboard_defconfig +--- u-boot-2021.10/configs/seaboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/seaboard_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_SEABOARD=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " +@@ -34,6 +35,7 @@ + CONFIG_TEGRA_KEYBOARD=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_PMIC=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/seeed_npi_imx6ull_defconfig u-boot/configs/seeed_npi_imx6ull_defconfig +--- u-boot-2021.10/configs/seeed_npi_imx6ull_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/seeed_npi_imx6ull_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -10,14 +10,14 @@ + CONFIG_ENV_OFFSET=0x3c00000 + CONFIG_MX6ULL=y + CONFIG_TARGET_NPI_IMX6ULL=y ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board" + CONFIG_SPL_TEXT_BASE=0x908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_BOARD_EARLY_INIT_F=y +diff -ruN u-boot-2021.10/configs/sei510_defconfig u-boot/configs/sei510_defconfig +--- u-boot-2021.10/configs/sei510_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sei510_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -6,6 +6,7 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0xFFFF0000 ++CONFIG_SYS_MALLOC_LEN=0x8000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510" + CONFIG_MESON_G12A=y +@@ -14,6 +15,7 @@ + CONFIG_IDENT_STRING=" sei510" + # CONFIG_PSCI_RESET is not set + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="run load_logo" +diff -ruN u-boot-2021.10/configs/sei610_defconfig u-boot/configs/sei610_defconfig +--- u-boot-2021.10/configs/sei610_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sei610_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -6,6 +6,7 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0xFFFF0000 ++CONFIG_SYS_MALLOC_LEN=0x8000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610" + CONFIG_MESON_G12A=y +@@ -14,6 +15,7 @@ + CONFIG_IDENT_STRING=" sei610" + # CONFIG_PSCI_RESET is not set + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_PREBOOT="run load_logo" +diff -ruN u-boot-2021.10/configs/sfr_nb4-ser_ram_defconfig u-boot/configs/sfr_nb4-ser_ram_defconfig +--- u-boot-2021.10/configs/sfr_nb4-ser_ram_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sfr_nb4-ser_ram_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_TEXT_BASE=0x80010000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 +@@ -7,10 +8,13 @@ + CONFIG_ARCH_BMIPS=y + CONFIG_SOC_BMIPS_BCM6358=y + CONFIG_BOARD_SFR_NB4_SER=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set + # CONFIG_MIPS_BOOT_ENV_LEGACY is not set + CONFIG_MIPS_BOOT_FDT=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_DISPLAY_CPUINFO=y + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/sheep-rk3368_defconfig u-boot/configs/sheep-rk3368_defconfig +--- u-boot-2021.10/configs/sheep-rk3368_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sheep-rk3368_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 +@@ -8,6 +9,7 @@ + CONFIG_DEBUG_UART_BASE=0xFF1b0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb" + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/sheevaplug_defconfig u-boot/configs/sheevaplug_defconfig +--- u-boot-2021.10/configs/sheevaplug_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sheevaplug_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SYS_THUMB_BUILD=y +@@ -11,6 +12,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" + CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" + # CONFIG_SYS_MALLOC_F is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_BOARDINFO is not set +diff -ruN u-boot-2021.10/configs/sifive_unleashed_defconfig u-boot/configs/sifive_unleashed_defconfig +--- u-boot-2021.10/configs/sifive_unleashed_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sifive_unleashed_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -2,16 +2,18 @@ + CONFIG_SPL_GPIO=y + CONFIG_SYS_MALLOC_F_LEN=0x3000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_TARGET_SIFIVE_UNLEASHED=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb" +@@ -22,7 +24,6 @@ + CONFIG_SPL_DM_SPI_FLASH=y + CONFIG_SPL_DM_RESET=y + CONFIG_SPL_SPI_LOAD=y +-CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_SPL_CLK=y +diff -ruN u-boot-2021.10/configs/sifive_unmatched_defconfig u-boot/configs/sifive_unmatched_defconfig +--- u-boot-2021.10/configs/sifive_unmatched_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sifive_unmatched_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -2,26 +2,28 @@ + CONFIG_SPL_GPIO=y + CONFIG_SYS_MALLOC_F_LEN=0x3000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_AHCI=y + CONFIG_TARGET_SIFIVE_UNMATCHED=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + # CONFIG_SPL_USE_ARCH_MEMMOVE is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y + CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_ID_EEPROM=y + CONFIG_SPL_SEPARATE_BSS=y + CONFIG_SPL_DM_RESET=y +-CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_CMD_EEPROM=y + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_PWM=y +@@ -32,6 +34,7 @@ + CONFIG_SCSI_AHCI=y + CONFIG_AHCI_PCI=y + CONFIG_SPL_CLK=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x54 + CONFIG_E1000=y + CONFIG_NVME=y + CONFIG_PCI=y +diff -ruN u-boot-2021.10/configs/silinux_ek874_defconfig u-boot/configs/silinux_ek874_defconfig +--- u-boot-2021.10/configs/silinux_ek874_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/silinux_ek874_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -6,11 +6,13 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x3F0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6318000 + CONFIG_RCAR_GEN3=y + CONFIG_TARGET_SILINUX_EK874=y ++CONFIG_SYS_LOAD_ADDR=0x58000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/silk_defconfig u-boot/configs/silk_defconfig +--- u-boot-2021.10/configs/silk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/silk_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Silk" + CONFIG_R8A7794=y + CONFIG_TARGET_SILK=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/Sinlinx_SinA31s_defconfig u-boot/configs/Sinlinx_SinA31s_defconfig +--- u-boot-2021.10/configs/Sinlinx_SinA31s_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Sinlinx_SinA31s_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,10 +6,7 @@ + CONFIG_DRAM_CLK=432 + CONFIG_DRAM_ZQ=251 + CONFIG_MMC0_CD_PIN="PA4" +-CONFIG_MMC3_PINS="PC" + CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +-CONFIG_USB1_VBUS_PIN="" +-CONFIG_USB2_VBUS_PIN="" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +@@ -18,3 +15,4 @@ + CONFIG_AXP_DLDO1_VOLT=3300 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Sinlinx_SinA33_defconfig u-boot/configs/Sinlinx_SinA33_defconfig +--- u-boot-2021.10/configs/Sinlinx_SinA33_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Sinlinx_SinA33_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,7 +7,6 @@ + CONFIG_DRAM_ZQ=15291 + CONFIG_MMC0_CD_PIN="PB4" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_ID_DET="PH8" + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 + CONFIG_VIDEO_LCD_BL_EN="PH6" +diff -ruN u-boot-2021.10/configs/Sinovoip_BPI_M2_defconfig u-boot/configs/Sinovoip_BPI_M2_defconfig +--- u-boot-2021.10/configs/Sinovoip_BPI_M2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Sinovoip_BPI_M2_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -4,8 +4,6 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN6I=y + CONFIG_DRAM_CLK=432 +-CONFIG_USB1_VBUS_PIN="" +-CONFIG_USB2_VBUS_PIN="" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y +@@ -17,3 +15,4 @@ + CONFIG_AXP_DLDO1_VOLT=3000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Sinovoip_BPI_M3_defconfig u-boot/configs/Sinovoip_BPI_M3_defconfig +--- u-boot-2021.10/configs/Sinovoip_BPI_M3_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Sinovoip_BPI_M3_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,10 +9,9 @@ + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + CONFIG_INITIAL_USB_SCAN_DELAY=500 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH11" +-CONFIG_USB1_VBUS_PIN="PD24" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + CONFIG_SATAPWR="PD25" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/sipeed_maix_bitm_defconfig u-boot/configs/sipeed_maix_bitm_defconfig +--- u-boot-2021.10/configs/sipeed_maix_bitm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sipeed_maix_bitm_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -2,8 +2,10 @@ + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0xfff000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_TARGET_SIPEED_MAIX=y + CONFIG_ARCH_RV64I=y ++CONFIG_SYS_LOAD_ADDR=0x80000000 + CONFIG_STACK_SIZE=0x100000 + CONFIG_USE_BOOTCOMMAND=y + CONFIG_BOOTCOMMAND="run k210_bootcmd" +diff -ruN u-boot-2021.10/configs/sipeed_maix_smode_defconfig u-boot/configs/sipeed_maix_smode_defconfig +--- u-boot-2021.10/configs/sipeed_maix_smode_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sipeed_maix_smode_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -3,9 +3,11 @@ + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0xfff000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_TARGET_SIPEED_MAIX=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y ++CONFIG_SYS_LOAD_ADDR=0x80000000 + CONFIG_STACK_SIZE=0x100000 + CONFIG_USE_BOOTCOMMAND=y + CONFIG_BOOTCOMMAND="run k210_bootcmd" +diff -ruN u-boot-2021.10/configs/smartweb_defconfig u-boot/configs/smartweb_defconfig +--- u-boot-2021.10/configs/smartweb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smartweb_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SPL_SYS_ICACHE_OFF=y + CONFIG_SPL_SYS_DCACHE_OFF=y + CONFIG_SPL_SYS_THUMB_BUILD=y +@@ -13,10 +15,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x460000 + CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x180000 ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" + CONFIG_BOOTDELAY=3 +@@ -59,6 +63,12 @@ + CONFIG_MTD_RAW_NAND=y + # CONFIG_SYS_NAND_USE_FLASH_BBT is not set + CONFIG_NAND_ATMEL=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_PHYLIB=y + CONFIG_ATMEL_USART=y + CONFIG_USB=y +diff -ruN u-boot-2021.10/configs/smdk5250_defconfig u-boot/configs/smdk5250_defconfig +--- u-boot-2021.10/configs/smdk5250_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smdk5250_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set +@@ -10,11 +12,13 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" + CONFIG_SPL_TEXT_BASE=0x02023400 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for SMDK5250" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -38,6 +42,7 @@ + CONFIG_USE_ENV_SPI_BUS=y + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_DW=y + CONFIG_MMC_SDHCI=y +diff -ruN u-boot-2021.10/configs/smdk5420_defconfig u-boot/configs/smdk5420_defconfig +--- u-boot-2021.10/configs/smdk5420_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smdk5420_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x23E00000 +@@ -8,11 +10,13 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" + CONFIG_SPL_TEXT_BASE=0x02024410 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for SMDK5420" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x23e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -33,6 +37,7 @@ + CONFIG_USE_ENV_SPI_BUS=y + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_DW=y + CONFIG_MMC_SDHCI=y +diff -ruN u-boot-2021.10/configs/smdkc100_defconfig u-boot/configs/smdkc100_defconfig +--- u-boot-2021.10/configs/smdkc100_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smdkc100_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_TEXT_BASE=0x34800000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" + CONFIG_TARGET_SMDKC100=y + CONFIG_IDENT_STRING=" for SMDKC100" ++CONFIG_SYS_LOAD_ADDR=0x30000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)" +diff -ruN u-boot-2021.10/configs/smdkv310_defconfig u-boot/configs/smdkv310_defconfig +--- u-boot-2021.10/configs/smdkv310_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smdkv310_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,15 +1,19 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x43E00000 + CONFIG_ARCH_EXYNOS4=y + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x4200 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" + CONFIG_SPL_TEXT_BASE=0x02021410 + CONFIG_SPL=y + CONFIG_IDENT_STRING=" for SMDKC210/V310" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SYS_PROMPT="SMDKV310 # " +diff -ruN u-boot-2021.10/configs/smegw01_defconfig u-boot/configs/smegw01_defconfig +--- u-boot-2021.10/configs/smegw01_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/smegw01_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01" + CONFIG_TARGET_SMEGW01=y +@@ -14,7 +15,6 @@ + CONFIG_IMX_BOOTAUX=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/storopack/smegw01/imximage.cfg" + CONFIG_HUSH_PARSER=y + # CONFIG_CMD_BOOTD is not set + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/snapper9260_defconfig u-boot/configs/snapper9260_defconfig +--- u-boot-2021.10/configs/snapper9260_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/snapper9260_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -6,6 +7,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x100000 ++CONFIG_SYS_LOAD_ADDR=0x23000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" + CONFIG_BOOTDELAY=3 +@@ -33,6 +36,9 @@ + CONFIG_TFTP_TSIZE=y + CONFIG_AT91_GPIO=y + CONFIG_CMD_PCA953X=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x7F + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/snapper9g20_defconfig u-boot/configs/snapper9g20_defconfig +--- u-boot-2021.10/configs/snapper9g20_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/snapper9g20_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x21f00000 +@@ -6,6 +7,8 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x100000 ++CONFIG_SYS_LOAD_ADDR=0x23000000 + CONFIG_FIT=y + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" + CONFIG_BOOTDELAY=3 +@@ -32,6 +35,9 @@ + CONFIG_TFTP_TSIZE=y + CONFIG_AT91_GPIO=y + CONFIG_CMD_PCA953X=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SOFT=y ++CONFIG_SYS_I2C_SOFT_SLAVE=0x7F + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y +diff -ruN u-boot-2021.10/configs/sniper_defconfig u-boot/configs/sniper_defconfig +--- u-boot-2021.10/configs/sniper_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sniper_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_SYS_TEXT_BASE=0x80100000 + CONFIG_NR_DRAM_BANKS=2 ++CONFIG_SYS_MALLOC_LEN=0x120000 + CONFIG_SPL_TEXT_BASE=0x40200000 + CONFIG_TARGET_SNIPER=y + CONFIG_SPL=y +@@ -22,7 +23,9 @@ + # CONFIG_CMD_NFS is not set + CONFIG_ENV_OVERWRITE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y +-CONFIG_SYS_OMAP24_I2C_SPEED=400000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_TWL4030_INPUT=y + CONFIG_MMC_OMAP_HS=y + CONFIG_CONS_INDEX=3 +diff -ruN u-boot-2021.10/configs/snow_defconfig u-boot/configs/snow_defconfig +--- u-boot-2021.10/configs/snow_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/snow_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set +@@ -10,6 +12,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" + CONFIG_SPL_TEXT_BASE=0x02023400 + CONFIG_SPL=y +@@ -18,6 +21,7 @@ + CONFIG_IDENT_STRING=" for snow" + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -43,6 +47,7 @@ + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_I2C_CROS_EC_LDO=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y + CONFIG_CROS_EC_KEYB=y +diff -ruN u-boot-2021.10/configs/socfpga_agilex_atf_defconfig u-boot/configs/socfpga_agilex_atf_defconfig +--- u-boot-2021.10/configs/socfpga_agilex_atf_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_agilex_atf_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -6,12 +6,14 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 + CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y + CONFIG_IDENT_STRING="socfpga_agilex" + CONFIG_SPL_FS_FAT=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_SPL_FIT_SIGNATURE=y + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/socfpga_agilex_defconfig u-boot/configs/socfpga_agilex_defconfig +--- u-boot-2021.10/configs/socfpga_agilex_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_agilex_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x3fe00000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +@@ -14,6 +15,7 @@ + CONFIG_IDENT_STRING="socfpga_agilex" + CONFIG_SPL_FS_FAT=y + # CONFIG_PSCI_RESET is not set ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_BOOTDELAY=5 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="earlycon" +diff -ruN u-boot-2021.10/configs/socfpga_agilex_vab_defconfig u-boot/configs/socfpga_agilex_vab_defconfig +--- u-boot-2021.10/configs/socfpga_agilex_vab_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_agilex_vab_defconfig 2021-11-01 17:10:14.196262799 +0100 +@@ -6,6 +6,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +@@ -13,6 +14,7 @@ + CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y + CONFIG_IDENT_STRING="socfpga_agilex" + CONFIG_SPL_FS_FAT=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_SPL_FIT_SIGNATURE=y + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/socfpga_arria10_defconfig u-boot/configs/socfpga_arria10_defconfig +--- u-boot-2021.10/configs/socfpga_arria10_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_arria10_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +diff -ruN u-boot-2021.10/configs/socfpga_arria5_defconfig u-boot/configs/socfpga_arria5_defconfig +--- u-boot-2021.10/configs/socfpga_arria5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_arria5_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_cyclone5_defconfig u-boot/configs/socfpga_cyclone5_defconfig +--- u-boot-2021.10/configs/socfpga_cyclone5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_cyclone5_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_dbm_soc1_defconfig u-boot/configs/socfpga_dbm_soc1_defconfig +--- u-boot-2021.10/configs/socfpga_dbm_soc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_dbm_soc1_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_de0_nano_soc_defconfig u-boot/configs/socfpga_de0_nano_soc_defconfig +--- u-boot-2021.10/configs/socfpga_de0_nano_soc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_de0_nano_soc_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_de10_nano_defconfig u-boot/configs/socfpga_de10_nano_defconfig +--- u-boot-2021.10/configs/socfpga_de10_nano_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_de10_nano_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_de1_soc_defconfig u-boot/configs/socfpga_de1_soc_defconfig +--- u-boot-2021.10/configs/socfpga_de1_soc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_de1_soc_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_is1_defconfig u-boot/configs/socfpga_is1_defconfig +--- u-boot-2021.10/configs/socfpga_is1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_is1_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_mcvevk_defconfig u-boot/configs/socfpga_mcvevk_defconfig +--- u-boot-2021.10/configs/socfpga_mcvevk_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_mcvevk_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_n5x_atf_defconfig u-boot/configs/socfpga_n5x_atf_defconfig +--- u-boot-2021.10/configs/socfpga_n5x_atf_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_n5x_atf_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,6 +6,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +diff -ruN u-boot-2021.10/configs/socfpga_n5x_defconfig u-boot/configs/socfpga_n5x_defconfig +--- u-boot-2021.10/configs/socfpga_n5x_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_n5x_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,6 +5,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +diff -ruN u-boot-2021.10/configs/socfpga_n5x_vab_defconfig u-boot/configs/socfpga_n5x_vab_defconfig +--- u-boot-2021.10/configs/socfpga_n5x_vab_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_n5x_vab_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,6 +6,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +diff -ruN u-boot-2021.10/configs/socfpga_secu1_defconfig u-boot/configs/socfpga_secu1_defconfig +--- u-boot-2021.10/configs/socfpga_secu1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_secu1_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -3,17 +3,19 @@ + CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +-# CONFIG_SPL_MMC_SUPPORT is not set ++# CONFIG_SPL_MMC is not set + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_TARGET_SOCFPGA_ARRIA5_SECU1=y + CONFIG_ENV_OFFSET_REDUND=0x120000 + # CONFIG_SPL_LIBDISK_SUPPORT is not set +-# CONFIG_SPL_SPI_SUPPORT is not set ++# CONFIG_SPL_SPI is not set + CONFIG_BUILD_TARGET="u-boot-with-nand-spl.sfp" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\"" +@@ -31,6 +33,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_SIZE=1024 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -61,14 +65,15 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_EEPROM_SIZE=1024 +-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_MMC_DW=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_DENALI_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_SPL_NAND_DENALI=y + CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2 + # CONFIG_DM_SPI_FLASH is not set +diff -ruN u-boot-2021.10/configs/socfpga_sockit_defconfig u-boot/configs/socfpga_sockit_defconfig +--- u-boot-2021.10/configs/socfpga_sockit_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_sockit_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_socrates_defconfig u-boot/configs/socfpga_socrates_defconfig +--- u-boot-2021.10/configs/socfpga_socrates_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_socrates_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,6 +2,7 @@ + CONFIG_ARCH_SOCFPGA=y + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x4400 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_sr1500_defconfig u-boot/configs/socfpga_sr1500_defconfig +--- u-boot-2021.10/configs/socfpga_sr1500_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_sr1500_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0xE0000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +diff -ruN u-boot-2021.10/configs/socfpga_stratix10_atf_defconfig u-boot/configs/socfpga_stratix10_atf_defconfig +--- u-boot-2021.10/configs/socfpga_stratix10_atf_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_stratix10_atf_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,12 +6,14 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 + CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y + CONFIG_IDENT_STRING="socfpga_stratix10" + CONFIG_SPL_FS_FAT=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_FIT=y + CONFIG_SPL_FIT_SIGNATURE=y + CONFIG_SPL_LOAD_FIT=y +diff -ruN u-boot-2021.10/configs/socfpga_stratix10_defconfig u-boot/configs/socfpga_stratix10_defconfig +--- u-boot-2021.10/configs/socfpga_stratix10_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_stratix10_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -7,6 +7,7 @@ + CONFIG_SYS_MEMTEST_END=0x3fe00000 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x200 ++CONFIG_SYS_MALLOC_LEN=0x500000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" + CONFIG_SPL_TEXT_BASE=0xFFE00000 +@@ -16,6 +17,7 @@ + # CONFIG_PSCI_RESET is not set + CONFIG_OPTIMIZE_INLINING=y + CONFIG_SPL_OPTIMIZE_INLINING=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_BOOTDELAY=5 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="earlycon" +diff -ruN u-boot-2021.10/configs/socfpga_vining_fpga_defconfig u-boot/configs/socfpga_vining_fpga_defconfig +--- u-boot-2021.10/configs/socfpga_vining_fpga_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/socfpga_vining_fpga_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -3,6 +3,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x4000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" + CONFIG_SPL_TEXT_BASE=0xFFFF0000 +@@ -27,6 +28,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 + CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y +@@ -71,8 +74,6 @@ + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 + CONFIG_MMC_DW=y + CONFIG_MTD=y + CONFIG_SF_DEFAULT_MODE=0x0 +diff -ruN u-boot-2021.10/configs/somlabs_visionsom_6ull_defconfig u-boot/configs/somlabs_visionsom_6ull_defconfig +--- u-boot-2021.10/configs/somlabs_visionsom_6ull_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/somlabs_visionsom_6ull_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,10 +8,10 @@ + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_MX6ULL=y + CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom" + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y +diff -ruN u-boot-2021.10/configs/spring_defconfig u-boot/configs/spring_defconfig +--- u-boot-2021.10/configs/spring_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/spring_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set +@@ -10,6 +12,7 @@ + CONFIG_ENV_SIZE=0x4000 + CONFIG_ENV_OFFSET=0x3FC000 + CONFIG_ENV_SECT_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x5004000 + CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring" + CONFIG_SPL_TEXT_BASE=0x02023400 + CONFIG_SPL=y +@@ -18,6 +21,7 @@ + CONFIG_IDENT_STRING=" for spring" + CONFIG_DEBUG_UART=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_BEST_MATCH=y + CONFIG_SILENT_CONSOLE=y +@@ -43,6 +47,7 @@ + CONFIG_ENV_SPI_BUS=1 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_I2C_CROS_EC_LDO=y ++CONFIG_SYS_I2C_S3C24X0=y + CONFIG_I2C_MUX=y + CONFIG_I2C_ARB_GPIO_CHALLENGE=y + CONFIG_CROS_EC_KEYB=y +diff -ruN u-boot-2021.10/configs/stemmy_defconfig u-boot/configs/stemmy_defconfig +--- u-boot-2021.10/configs/stemmy_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stemmy_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,8 +1,16 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_U8500=y ++CONFIG_SUPPORT_PASSING_ATAGS=y ++# CONFIG_SETUP_MEMORY_TAGS is not set ++CONFIG_INITRD_TAG=y + CONFIG_SYS_TEXT_BASE=0x100000 + CONFIG_NR_DRAM_BANKS=2 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="ste-ux500-samsung-stemmy" ++CONFIG_SYS_LOAD_ADDR=0x100000 ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="run fastbootcmd" + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_CONFIG=y +@@ -14,5 +22,17 @@ + CONFIG_CMD_GETTIME=y + CONFIG_EFI_PARTITION=y + # CONFIG_NET is not set ++CONFIG_USB_FUNCTION_FASTBOOT=y ++CONFIG_FASTBOOT_BUF_ADDR=0x18100000 ++CONFIG_FASTBOOT_FLASH=y ++CONFIG_FASTBOOT_FLASH_MMC_DEV=0 + # CONFIG_MMC_HW_PARTITIONING is not set ++CONFIG_USB=y ++CONFIG_USB_MUSB_GADGET=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 ++CONFIG_USB_GADGET_PRODUCT_NUM=0x685d ++CONFIG_DM_VIDEO=y ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MCDE_SIMPLE=y + # CONFIG_EFI_LOADER is not set +diff -ruN u-boot-2021.10/configs/stih410-b2260_defconfig u-boot/configs/stih410-b2260_defconfig +--- u-boot-2021.10/configs/stih410-b2260_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stih410-b2260_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,11 +1,14 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_STI=y + CONFIG_SYS_TEXT_BASE=0x7D600000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x4000 ++CONFIG_SYS_MALLOC_LEN=0x1800000 + CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260" + CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/stm32f429-discovery_defconfig u-boot/configs/stm32f429-discovery_defconfig +--- u-boot-2021.10/configs/stm32f429-discovery_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32f429-discovery_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,10 +5,12 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco" + CONFIG_STM32F4=y + CONFIG_TARGET_STM32F429_DISCOVERY=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x90400000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +diff -ruN u-boot-2021.10/configs/stm32f429-evaluation_defconfig u-boot/configs/stm32f429-evaluation_defconfig +--- u-boot-2021.10/configs/stm32f429-evaluation_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32f429-evaluation_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0xF00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval" + CONFIG_STM32F4=y + CONFIG_TARGET_STM32F429_EVALUATION=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x400000 + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/stm32f469-discovery_defconfig u-boot/configs/stm32f469-discovery_defconfig +--- u-boot-2021.10/configs/stm32f469-discovery_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32f469-discovery_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0xF00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco" + CONFIG_STM32F4=y + CONFIG_TARGET_STM32F469_DISCOVERY=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x400000 + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/stm32f746-disco_defconfig u-boot/configs/stm32f746-disco_defconfig +--- u-boot-2021.10/configs/stm32f746-disco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32f746-disco_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,11 +4,13 @@ + CONFIG_SYS_MALLOC_F_LEN=0xE00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" + CONFIG_SPL_TEXT_BASE=0x8000000 + CONFIG_STM32F7=y + CONFIG_TARGET_STM32F746_DISCO=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x8008000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +diff -ruN u-boot-2021.10/configs/stm32f769-disco_defconfig u-boot/configs/stm32f769-disco_defconfig +--- u-boot-2021.10/configs/stm32f769-disco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32f769-disco_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,11 +4,13 @@ + CONFIG_SYS_MALLOC_F_LEN=0xE00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" + CONFIG_SPL_TEXT_BASE=0x8000000 + CONFIG_STM32F7=y + CONFIG_TARGET_STM32F746_DISCO=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x8008000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +diff -ruN u-boot-2021.10/configs/stm32h743-disco_defconfig u-boot/configs/stm32h743-disco_defconfig +--- u-boot-2021.10/configs/stm32h743-disco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32h743-disco_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0xF00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco" + CONFIG_STM32H7=y + CONFIG_TARGET_STM32H743_DISCO=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xd0400000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +diff -ruN u-boot-2021.10/configs/stm32h743-eval_defconfig u-boot/configs/stm32h743-eval_defconfig +--- u-boot-2021.10/configs/stm32h743-eval_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32h743-eval_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0xF00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval" + CONFIG_STM32H7=y + CONFIG_TARGET_STM32H743_EVAL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xd0400000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +diff -ruN u-boot-2021.10/configs/stm32h750-art-pi_defconfig u-boot/configs/stm32h750-art-pi_defconfig +--- u-boot-2021.10/configs/stm32h750-art-pi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32h750-art-pi_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,10 +4,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0xF00 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi" + CONFIG_STM32H7=y + CONFIG_TARGET_STM32H750_ART_PI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc1800000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/stm32mp15_basic_defconfig u-boot/configs/stm32mp15_basic_defconfig +--- u-boot-2021.10/configs/stm32mp15_basic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15_basic_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,7 +8,7 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_ST_STM32MP15x=y + CONFIG_CMD_STM32KEY=y +@@ -16,9 +16,10 @@ + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + CONFIG_TYPEC_STUSB160X=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +@@ -111,6 +112,7 @@ + CONFIG_SYS_MTDPARTS_RUNTIME=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_STM32_FMC2=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_SPI_NAND=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/stm32mp15_defconfig u-boot/configs/stm32mp15_defconfig +--- u-boot-2021.10/configs/stm32mp15_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -13,6 +13,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x4C0000 + CONFIG_TYPEC_STUSB160X=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +@@ -91,6 +92,7 @@ + CONFIG_SYS_MTDPARTS_RUNTIME=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_STM32_FMC2=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_SPI_NAND=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/stm32mp15_dhcom_basic_defconfig u-boot/configs/stm32mp15_dhcom_basic_defconfig +--- u-boot-2021.10/configs/stm32mp15_dhcom_basic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15_dhcom_basic_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,13 +8,14 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_DH_STM32MP1_PDK2=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its" +@@ -35,6 +36,7 @@ + # CONFIG_CMD_ELF is not set + # CONFIG_CMD_EXPORTENV is not set + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_BUS=3 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_UNZIP=y +@@ -93,7 +95,6 @@ + CONFIG_STM32_IPCC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +-CONFIG_SYS_I2C_EEPROM_BUS=3 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_STM32_SDMMC2=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/stm32mp15_dhcor_basic_defconfig u-boot/configs/stm32mp15_dhcor_basic_defconfig +--- u-boot-2021.10/configs/stm32mp15_dhcor_basic_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15_dhcor_basic_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,13 +6,14 @@ + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_DH_STM32MP1_PDK2=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its" +@@ -33,6 +34,7 @@ + # CONFIG_CMD_ELF is not set + # CONFIG_CMD_EXPORTENV is not set + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_BUS=2 + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_UNZIP=y +@@ -89,7 +91,6 @@ + CONFIG_STM32_IPCC=y + CONFIG_I2C_EEPROM=y + CONFIG_SYS_I2C_EEPROM_ADDR=0x53 +-CONFIG_SYS_I2C_EEPROM_BUS=2 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_STM32_SDMMC2=y + CONFIG_MTD=y +diff -ruN u-boot-2021.10/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig u-boot/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +--- u-boot-2021.10/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,12 +6,13 @@ + CONFIG_ENV_OFFSET=0x280000 + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_ICORE_STM32MP1=y + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +diff -ruN u-boot-2021.10/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig u-boot/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +--- u-boot-2021.10/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,12 +6,13 @@ + CONFIG_ENV_OFFSET=0x280000 + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_ICORE_STM32MP1=y + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +diff -ruN u-boot-2021.10/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig u-boot/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +--- u-boot-2021.10/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,12 +6,13 @@ + CONFIG_ENV_OFFSET=0x280000 + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_MICROGEA_STM32MP1=y + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +diff -ruN u-boot-2021.10/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig u-boot/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +--- u-boot-2021.10/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,12 +6,13 @@ + CONFIG_ENV_OFFSET=0x280000 + CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7" + CONFIG_SPL_TEXT_BASE=0x2FFC2500 +-CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL_MMC=y + CONFIG_SPL=y + CONFIG_TARGET_MICROGEA_STM32MP1=y + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + # CONFIG_ARMV7_VIRT is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +diff -ruN u-boot-2021.10/configs/stm32mp15_trusted_defconfig u-boot/configs/stm32mp15_trusted_defconfig +--- u-boot-2021.10/configs/stm32mp15_trusted_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stm32mp15_trusted_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -14,6 +14,7 @@ + CONFIG_ENV_OFFSET_REDUND=0x2C0000 + CONFIG_TYPEC_STUSB160X=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0xc2000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=1 + CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +@@ -92,6 +93,7 @@ + CONFIG_SYS_MTDPARTS_RUNTIME=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_STM32_FMC2=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_MTD_SPI_NAND=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/stmark2_defconfig u-boot/configs/stmark2_defconfig +--- u-boot-2021.10/configs/stmark2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stmark2_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -3,8 +3,10 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x40000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="stmark2" + CONFIG_TARGET_STMARK2=y ++CONFIG_SYS_LOAD_ADDR=0x40010000 + CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/bin/init devtmpfs.mount=1" +diff -ruN u-boot-2021.10/configs/stout_defconfig u-boot/configs/stout_defconfig +--- u-boot-2021.10/configs/stout_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stout_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -12,17 +12,19 @@ + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot" + CONFIG_SPL_TEXT_BASE=0xe6300000 + CONFIG_ARCH_RMOBILE_BOARD_STRING="Stout" + CONFIG_R8A7790=y + CONFIG_TARGET_STOUT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_SPL_BOARD_INIT=y +diff -ruN u-boot-2021.10/configs/stv0991_defconfig u-boot/configs/stv0991_defconfig +--- u-boot-2021.10/configs/stv0991_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/stv0991_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -9,7 +9,9 @@ + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x30000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x14000 + CONFIG_DEFAULT_DEVICE_TREE="stv0991" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_SYS_EXTRA_OPTIONS="STV0991" + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/sun8i_a23_evb_defconfig u-boot/configs/sun8i_a23_evb_defconfig +--- u-boot-2021.10/configs/sun8i_a23_evb_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sun8i_a23_evb_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,9 +5,7 @@ + CONFIG_MACH_SUN8I_A23=y + CONFIG_DRAM_CLK=552 + CONFIG_DRAM_ZQ=63351 +-CONFIG_USB0_VBUS_PIN="axp_drivebus" +-CONFIG_USB0_VBUS_DET="axp_vbus_detect" +-CONFIG_USB1_VBUS_PIN="PH7" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONS_INDEX=5 + CONFIG_USB_EHCI_HCD=y +diff -ruN u-boot-2021.10/configs/Sunchip_CX-A99_defconfig u-boot/configs/Sunchip_CX-A99_defconfig +--- u-boot-2021.10/configs/Sunchip_CX-A99_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Sunchip_CX-A99_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,7 +8,5 @@ + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="PH17" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="PH15" +-CONFIG_USB1_VBUS_PIN="PL7" +-CONFIG_USB3_VBUS_PIN="PL8" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff -ruN u-boot-2021.10/configs/sunxi_Gemei_G9_defconfig u-boot/configs/sunxi_Gemei_G9_defconfig +--- u-boot-2021.10/configs/sunxi_Gemei_G9_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/sunxi_Gemei_G9_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -12,5 +12,9 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/synquacer_developerbox_defconfig u-boot/configs/synquacer_developerbox_defconfig +--- u-boot-2021.10/configs/synquacer_developerbox_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/synquacer_developerbox_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,14 +1,15 @@ + CONFIG_ARM=y +-CONFIG_POSITION_INDEPENDENT=y + CONFIG_ARCH_SYNQUACER=y +-CONFIG_SYS_TEXT_BASE=0x00000000 ++CONFIG_SYS_TEXT_BASE=0x08200000 + CONFIG_ENV_SIZE=0x30000 + CONFIG_ENV_OFFSET=0x300000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" + CONFIG_TARGET_DEVELOPERBOX=y + CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x80000000 + CONFIG_FIT=y + CONFIG_BOOTSTAGE_STASH_SIZE=4096 + CONFIG_HUSH_PARSER=y +diff -ruN u-boot-2021.10/configs/syzygy_hub_defconfig u-boot/configs/syzygy_hub_defconfig +--- u-boot-2021.10/configs/syzygy_hub_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/syzygy_hub_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -16,6 +16,7 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +diff -ruN u-boot-2021.10/configs/T1024RDB_defconfig u-boot/configs/T1024RDB_defconfig +--- u-boot-2021.10/configs/T1024RDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1024RDB_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0x00400000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" + CONFIG_MPC85xx=y + CONFIG_TARGET_T1024RDB=y +@@ -17,9 +18,13 @@ + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -41,7 +46,16 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T1024RDB_NAND_defconfig u-boot/configs/T1024RDB_NAND_defconfig +--- u-boot-2021.10/configs/T1024RDB_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1024RDB_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,9 +6,10 @@ + CONFIG_SYS_MEMTEST_END=0x00400000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -19,22 +20,28 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_NAND_BOOT=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -55,7 +62,16 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -64,6 +80,9 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/T1024RDB_SDCARD_defconfig u-boot/configs/T1024RDB_SDCARD_defconfig +--- u-boot-2021.10/configs/T1024RDB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1024RDB_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,10 +6,11 @@ + CONFIG_SYS_MEMTEST_END=0x00400000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -18,21 +19,28 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_MMC_BOOT=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -53,7 +61,16 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T1024RDB_SPIFLASH_defconfig u-boot/configs/T1024RDB_SPIFLASH_defconfig +--- u-boot-2021.10/configs/T1024RDB_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1024RDB_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,34 +7,42 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_T1024RDB=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_ID_EEPROM=y + # CONFIG_SPL_FRAMEWORK is not set + CONFIG_SPL_SPI_BOOT=y + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -55,7 +63,16 @@ + CONFIG_DM=y + CONFIG_FSL_CAAM=y + CONFIG_SYS_FSL_DDR3=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T1042D4RDB_defconfig u-boot/configs/T1042D4RDB_defconfig +--- u-boot-2021.10/configs/T1042D4RDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1042D4RDB_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -36,7 +36,20 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T1042D4RDB_NAND_defconfig u-boot/configs/T1042D4RDB_NAND_defconfig +--- u-boot-2021.10/configs/T1042D4RDB_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1042D4RDB_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,7 +6,7 @@ + CONFIG_ENV_OFFSET=0x180000 + CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -17,7 +17,9 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -28,7 +30,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y +@@ -50,7 +52,20 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -59,6 +74,9 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/T1042D4RDB_SDCARD_defconfig u-boot/configs/T1042D4RDB_SDCARD_defconfig +--- u-boot-2021.10/configs/T1042D4RDB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1042D4RDB_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,8 +6,8 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -16,7 +16,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -27,7 +30,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -48,7 +51,20 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T1042D4RDB_SPIFLASH_defconfig u-boot/configs/T1042D4RDB_SPIFLASH_defconfig +--- u-boot-2021.10/configs/T1042D4RDB_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T1042D4RDB_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,18 +7,21 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_T1042D4RDB=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_SILENT_CONSOLE=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -29,7 +32,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -50,7 +53,20 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=66666666 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080QDS_defconfig u-boot/configs/T2080QDS_defconfig +--- u-boot-2021.10/configs/T2080QDS_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -34,7 +34,20 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080QDS_NAND_defconfig u-boot/configs/T2080QDS_NAND_defconfig +--- u-boot-2021.10/configs/T2080QDS_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,7 +7,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="t2080qds" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -18,7 +18,9 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -26,7 +28,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y +@@ -48,7 +50,20 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -57,6 +72,9 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/T2080QDS_SDCARD_defconfig u-boot/configs/T2080QDS_SDCARD_defconfig +--- u-boot-2021.10/configs/T2080QDS_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,8 +7,8 @@ + CONFIG_DEFAULT_DEVICE_TREE="t2080qds" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -17,7 +17,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -25,7 +28,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -46,7 +49,20 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080QDS_SECURE_BOOT_defconfig u-boot/configs/T2080QDS_SECURE_BOOT_defconfig +--- u-boot-2021.10/configs/T2080QDS_SECURE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_SECURE_BOOT_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -33,7 +33,20 @@ + CONFIG_ENV_OVERWRITE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080QDS_SPIFLASH_defconfig u-boot/configs/T2080QDS_SPIFLASH_defconfig +--- u-boot-2021.10/configs/T2080QDS_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,18 +8,21 @@ + CONFIG_DEFAULT_DEVICE_TREE="t2080qds" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 + CONFIG_FSL_USE_PCA9547_MUX=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_T2080QDS=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -27,7 +30,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -48,7 +51,20 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig u-boot/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +--- u-boot-2021.10/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -31,7 +31,20 @@ + CONFIG_ENV_ADDR=0xFFE20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DYNAMIC_DDR_CLK_FREQ=y ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x57 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_DM_SPI_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_defconfig u-boot/configs/T2080RDB_defconfig +--- u-boot-2021.10/configs/T2080RDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -16,6 +16,7 @@ + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -38,7 +39,21 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_NAND_defconfig u-boot/configs/T2080RDB_NAND_defconfig +--- u-boot-2021.10/configs/T2080RDB_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,7 +8,7 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -19,7 +19,9 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -27,10 +29,11 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -52,7 +55,21 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -61,6 +78,9 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/T2080RDB_revD_defconfig u-boot/configs/T2080RDB_revD_defconfig +--- u-boot-2021.10/configs/T2080RDB_revD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_revD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -17,6 +17,7 @@ + CONFIG_BOARD_EARLY_INIT_R=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -39,7 +40,21 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_revD_NAND_defconfig u-boot/configs/T2080RDB_revD_NAND_defconfig +--- u-boot-2021.10/configs/T2080RDB_revD_NAND_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_revD_NAND_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,7 +8,7 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -20,7 +20,9 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -28,10 +30,11 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_SPL_NAND_SUPPORT=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -53,7 +56,21 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +@@ -62,6 +79,9 @@ + CONFIG_FLASH_CFI_MTD=y + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_FSL_IFC=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_SPI_FLASH=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=10000000 +diff -ruN u-boot-2021.10/configs/T2080RDB_revD_SDCARD_defconfig u-boot/configs/T2080RDB_revD_SDCARD_defconfig +--- u-boot-2021.10/configs/T2080RDB_revD_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_revD_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,8 +8,8 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -19,7 +19,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -27,9 +30,10 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -51,7 +55,21 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_revD_SPIFLASH_defconfig u-boot/configs/T2080RDB_revD_SPIFLASH_defconfig +--- u-boot-2021.10/configs/T2080RDB_revD_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_revD_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,11 +9,11 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_T2080RDB=y + CONFIG_T2080RDB_REV_D=y +@@ -21,7 +21,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -29,9 +32,10 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -53,7 +57,21 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_SDCARD_defconfig u-boot/configs/T2080RDB_SDCARD_defconfig +--- u-boot-2021.10/configs/T2080RDB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -8,8 +8,8 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -18,7 +18,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -26,9 +29,10 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -50,7 +54,21 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T2080RDB_SPIFLASH_defconfig u-boot/configs/T2080RDB_SPIFLASH_defconfig +--- u-boot-2021.10/configs/T2080RDB_SPIFLASH_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T2080RDB_SPIFLASH_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -9,18 +9,21 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_MPC85xx=y + CONFIG_TARGET_T2080RDB=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" ++CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -28,9 +31,10 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_DM=y +@@ -52,7 +56,21 @@ + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133330000 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 ++CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y ++CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 ++CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y ++CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T4240RDB_defconfig u-boot/configs/T4240RDB_defconfig +--- u-boot-2021.10/configs/T4240RDB_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T4240RDB_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -31,7 +31,16 @@ + CONFIG_ENV_ADDR=0xEFF20000 + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/T4240RDB_SDCARD_defconfig u-boot/configs/T4240RDB_SDCARD_defconfig +--- u-boot-2021.10/configs/T4240RDB_SDCARD_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/T4240RDB_SDCARD_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,8 +6,8 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" + CONFIG_SPL_TEXT_BASE=0xFFFD8000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_MPC85xx=y +@@ -16,7 +16,10 @@ + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y +-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" ++CONFIG_SYS_EXTRA_OPTIONS="SDCARD" ++CONFIG_RAMBOOT_PBL=y ++CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg" ++CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg" + CONFIG_BOOTDELAY=10 + CONFIG_BOARD_EARLY_INIT_R=y + # CONFIG_SPL_FRAMEWORK is not set +@@ -24,7 +27,7 @@ + CONFIG_SPL_FSL_PBL=y + CONFIG_SPL_ENV_SUPPORT=y + CONFIG_SPL_I2C=y +-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y ++CONFIG_SPL_MPC8XXX_INIT_DDR=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_IMLS=y + CONFIG_CMD_GREPENV=y +@@ -43,7 +46,16 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM=y + CONFIG_FSL_CAAM=y ++CONFIG_DDR_CLK_FREQ=133333333 ++CONFIG_DDR_ECC=y ++CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x118000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 + CONFIG_FSL_ESDHC=y + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/taurus_defconfig u-boot/configs/taurus_defconfig +--- u-boot-2021.10/configs/taurus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/taurus_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_SPL_SYS_ICACHE_OFF=y + CONFIG_SPL_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y +@@ -16,6 +18,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x460000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +@@ -24,9 +27,10 @@ + CONFIG_DEBUG_UART_CLOCK=18432000 + CONFIG_ENV_OFFSET_REDUND=0x180000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y +-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067" ++CONFIG_SYS_LOAD_ADDR=0x22000000 ++CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" +@@ -75,6 +79,12 @@ + CONFIG_MTD_RAW_NAND=y + # CONFIG_SYS_NAND_USE_FLASH_BBT is not set + CONFIG_NAND_ATMEL=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/tb100_defconfig u-boot/configs/tb100_defconfig +--- u-boot-2021.10/configs/tb100_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tb100_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -2,8 +2,10 @@ + CONFIG_TARGET_TB100=y + CONFIG_SYS_TEXT_BASE=0x84000000 + CONFIG_ENV_SIZE=0x800 ++CONFIG_SYS_MALLOC_LEN=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" + CONFIG_SYS_CLK_FREQ=500000000 ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200n8" +diff -ruN u-boot-2021.10/configs/tbs2910_defconfig u-boot/configs/tbs2910_defconfig +--- u-boot-2021.10/configs/tbs2910_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tbs2910_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,6 +8,7 @@ + CONFIG_ENV_OFFSET=0x60000 + CONFIG_MX6Q=y + CONFIG_TARGET_TBS2910=y ++CONFIG_SYS_MALLOC_LEN=0x8000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910" + CONFIG_PRE_CON_BUF_ADDR=0x7c000000 +diff -ruN u-boot-2021.10/configs/tbs_a711_defconfig u-boot/configs/tbs_a711_defconfig +--- u-boot-2021.10/configs/tbs_a711_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tbs_a711_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,9 +8,8 @@ + CONFIG_DRAM_ZQ=15355 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH11" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +diff -ruN u-boot-2021.10/configs/tec_defconfig u-boot/configs/tec_defconfig +--- u-boot-2021.10/configs/tec_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tec_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_TEC=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_STDIO_DEREGISTER=y +@@ -31,6 +32,7 @@ + CONFIG_SPL_DM=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_DM_PMIC=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/tec-ng_defconfig u-boot/configs/tec-ng_defconfig +--- u-boot-2021.10/configs/tec-ng_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tec-ng_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA30=y + CONFIG_TARGET_TEC_NG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_FIT=y + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y +diff -ruN u-boot-2021.10/configs/teres_i_defconfig u-boot/configs/teres_i_defconfig +--- u-boot-2021.10/configs/teres_i_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/teres_i_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,9 +6,10 @@ + CONFIG_DRAM_CLK=552 + CONFIG_DRAM_ZQ=3881949 + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB1_VBUS_PIN="PL7" + CONFIG_I2C0_ENABLE=y + CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_PWM=y +diff -ruN u-boot-2021.10/configs/theadorable_debug_defconfig u-boot/configs/theadorable_debug_defconfig +--- u-boot-2021.10/configs/theadorable_debug_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/theadorable_debug_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -13,12 +13,13 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" + CONFIG_SPL_TEXT_BASE=0x40004030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y +@@ -57,6 +58,10 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_BOOTCOUNT_RAM=y + CONFIG_FPGA_ALTERA=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x0 + # CONFIG_MMC is not set + CONFIG_SF_DEFAULT_SPEED=27777777 + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/thuban_defconfig u-boot/configs/thuban_defconfig +--- u-boot-2021.10/configs/thuban_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/thuban_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -7,21 +7,23 @@ + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_SPL_DM_SPI=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" + CONFIG_AM33XX=y + CONFIG_SYS_MPUCLK=300 + CONFIG_TARGET_THUBAN=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_BOOTCOUNT_BOOTLIMIT=3 + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x2E0000 + CONFIG_SPL_FS_FAT=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_BOOTDELAY=3 + CONFIG_AUTOBOOT_KEYED=y + CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" +@@ -76,10 +78,19 @@ + CONFIG_BOOTCOUNT_ENV=y + CONFIG_DFU_NAND=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + # CONFIG_SPL_DM_MMC is not set + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 + CONFIG_DM_SPI_FLASH=y + CONFIG_SPI_FLASH_WINBOND=y + CONFIG_MTD_UBI_FASTMAP=y +diff -ruN u-boot-2021.10/configs/thunderx_88xx_defconfig u-boot/configs/thunderx_88xx_defconfig +--- u-boot-2021.10/configs/thunderx_88xx_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/thunderx_88xx_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -3,11 +3,13 @@ + CONFIG_SYS_TEXT_BASE=0x00500000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x101000 + CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" + CONFIG_DEBUG_UART_BASE=0x87e024000000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x500000 + CONFIG_BOOTDELAY=5 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e024000000 debug maxcpus=48 rootwait rw root=/dev/sda2 coherent_pool=16M" +diff -ruN u-boot-2021.10/configs/ti816x_evm_defconfig u-boot/configs/ti816x_evm_defconfig +--- u-boot-2021.10/configs/ti816x_evm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ti816x_evm_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_SPL_GPIO=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y +@@ -10,8 +11,8 @@ + CONFIG_SPL_TEXT_BASE=0x40400000 + CONFIG_TI816X=y + CONFIG_TARGET_TI816X_EVM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x1E0000 + CONFIG_SPL_FS_FAT=y +@@ -53,11 +54,19 @@ + CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_DM=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_OMAP24XX=y + CONFIG_MMC_OMAP_HS=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_PAGE_COUNT=0x40 ++CONFIG_SYS_NAND_PAGE_SIZE=0x800 ++CONFIG_SYS_NAND_OOBSIZE=0x40 + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 + CONFIG_DM_ETH=y + CONFIG_MII=y + CONFIG_DRIVER_TI_EMAC=y +diff -ruN u-boot-2021.10/configs/tinker-rk3288_defconfig u-boot/configs/tinker-rk3288_defconfig +--- u-boot-2021.10/configs/tinker-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tinker-rk3288_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x01000000 + CONFIG_SPL_GPIO=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" +@@ -64,6 +67,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SPL_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/tinker-s-rk3288_defconfig u-boot/configs/tinker-s-rk3288_defconfig +--- u-boot-2021.10/configs/tinker-s-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tinker-s-rk3288_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x01000000 + CONFIG_SPL_GPIO=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" +@@ -64,6 +67,7 @@ + CONFIG_SPL_PINCTRL=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y + CONFIG_SPL_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_SPL_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/tools-only_defconfig u-boot/configs/tools-only_defconfig +--- u-boot-2021.10/configs/tools-only_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tools-only_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,6 +1,8 @@ + CONFIG_SYS_TEXT_BASE=0 + CONFIG_ENV_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y +diff -ruN u-boot-2021.10/configs/topic_miami_defconfig u-boot/configs/topic_miami_defconfig +--- u-boot-2021.10/configs/topic_miami_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/topic_miami_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -18,6 +18,7 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_BOOTDELAY=0 + CONFIG_USE_PREBOOT=y + CONFIG_SPL_STACK_R=y +diff -ruN u-boot-2021.10/configs/topic_miamilite_defconfig u-boot/configs/topic_miamilite_defconfig +--- u-boot-2021.10/configs/topic_miamilite_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/topic_miamilite_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -18,6 +18,7 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_BOOTDELAY=0 + CONFIG_USE_PREBOOT=y + CONFIG_SPL_STACK_R=y +diff -ruN u-boot-2021.10/configs/topic_miamiplus_defconfig u-boot/configs/topic_miamiplus_defconfig +--- u-boot-2021.10/configs/topic_miamiplus_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/topic_miamiplus_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -18,6 +18,7 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_BOOTDELAY=0 + CONFIG_USE_PREBOOT=y + CONFIG_SPL_STACK_R=y +diff -ruN u-boot-2021.10/configs/total_compute_defconfig u-boot/configs/total_compute_defconfig +--- u-boot-2021.10/configs/total_compute_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/total_compute_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,8 +6,10 @@ + CONFIG_SYS_MEMTEST_START=0x80000000 + CONFIG_SYS_MEMTEST_END=0xff000000 + CONFIG_ENV_SIZE=0x2a00000 ++CONFIG_SYS_MALLOC_LEN=0x3200000 + CONFIG_DEFAULT_DEVICE_TREE="total_compute" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x90000000 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y +diff -ruN u-boot-2021.10/configs/tplink_wdr4300_defconfig u-boot/configs/tplink_wdr4300_defconfig +--- u-boot-2021.10/configs/tplink_wdr4300_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tplink_wdr4300_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -4,9 +4,11 @@ + CONFIG_SYS_MEMTEST_START=0x80100000 + CONFIG_SYS_MEMTEST_END=0x83f00000 + CONFIG_ENV_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" + CONFIG_ARCH_ATH79=y + CONFIG_BOARD_TPLINK_WDR4300=y ++CONFIG_SYS_LOAD_ADDR=0xa1000000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +diff -ruN u-boot-2021.10/configs/tqma6dl_mba6_mmc_defconfig u-boot/configs/tqma6dl_mba6_mmc_defconfig +--- u-boot-2021.10/configs/tqma6dl_mba6_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6dl_mba6_mmc_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6DL=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -15,6 +16,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -35,6 +37,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/tqma6dl_mba6_spi_defconfig u-boot/configs/tqma6dl_mba6_spi_defconfig +--- u-boot-2021.10/configs/tqma6dl_mba6_spi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6dl_mba6_spi_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6DL=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_TQMA6X_SPI_BOOT=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" + CONFIG_ENV_OFFSET_REDUND=0x90000 +@@ -18,6 +19,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +41,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/tqma6q_mba6_mmc_defconfig u-boot/configs/tqma6q_mba6_mmc_defconfig +--- u-boot-2021.10/configs/tqma6q_mba6_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6q_mba6_mmc_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6Q=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -15,6 +16,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -35,6 +37,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/tqma6q_mba6_spi_defconfig u-boot/configs/tqma6q_mba6_spi_defconfig +--- u-boot-2021.10/configs/tqma6q_mba6_spi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6q_mba6_spi_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6Q=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_TQMA6X_SPI_BOOT=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" + CONFIG_ENV_OFFSET_REDUND=0x90000 +@@ -18,6 +19,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +41,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/tqma6s_mba6_mmc_defconfig u-boot/configs/tqma6s_mba6_mmc_defconfig +--- u-boot-2021.10/configs/tqma6s_mba6_mmc_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6s_mba6_mmc_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -5,6 +5,7 @@ + CONFIG_ENV_OFFSET=0x100000 + CONFIG_MX6S=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +@@ -15,6 +16,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -35,6 +37,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/tqma6s_mba6_spi_defconfig u-boot/configs/tqma6s_mba6_spi_defconfig +--- u-boot-2021.10/configs/tqma6s_mba6_spi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tqma6s_mba6_spi_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -6,6 +6,7 @@ + CONFIG_ENV_SECT_SIZE=0x10000 + CONFIG_MX6S=y + CONFIG_TARGET_TQMA6=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_TQMA6X_SPI_BOOT=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" + CONFIG_ENV_OFFSET_REDUND=0x90000 +@@ -18,6 +19,7 @@ + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +@@ -39,6 +41,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_I2C_SET_DEFAULT_BUS_NUM=y + CONFIG_SYS_I2C_MXC=y ++CONFIG_SYS_I2C_EEPROM_ADDR=0x50 + CONFIG_FSL_USDHC=y + CONFIG_SF_DEFAULT_MODE=0 + CONFIG_SF_DEFAULT_SPEED=50000000 +diff -ruN u-boot-2021.10/configs/trats2_defconfig u-boot/configs/trats2_defconfig +--- u-boot-2021.10/configs/trats2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/trats2_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x43e00000 +@@ -6,9 +7,11 @@ + CONFIG_TARGET_TRATS2=y + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x7000 ++CONFIG_SYS_MALLOC_LEN=0x5001000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x43e00000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/trats_defconfig u-boot/configs/trats_defconfig +--- u-boot-2021.10/configs/trats_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/trats_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_EXYNOS=y + CONFIG_SYS_TEXT_BASE=0x63300000 +@@ -6,8 +7,10 @@ + CONFIG_TARGET_TRATS=y + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x7000 ++CONFIG_SYS_MALLOC_LEN=0x5001000 + CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x44800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/trimslice_defconfig u-boot/configs/trimslice_defconfig +--- u-boot-2021.10/configs/trimslice_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/trimslice_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -9,6 +9,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_TRIMSLICE=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/tuge1_defconfig u-boot/configs/tuge1_defconfig +--- u-boot-2021.10/configs/tuge1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tuge1_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -119,6 +119,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -132,6 +133,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y +@@ -150,6 +153,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/turris_mox_defconfig u-boot/configs/turris_mox_defconfig +--- u-boot-2021.10/configs/turris_mox_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/turris_mox_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -16,6 +16,7 @@ + CONFIG_OF_BOARD_FIXUP=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +diff -ruN u-boot-2021.10/configs/turris_omnia_defconfig u-boot/configs/turris_omnia_defconfig +--- u-boot-2021.10/configs/turris_omnia_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/turris_omnia_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_SPL_SYS_THUMB_BUILD=y + CONFIG_ARCH_MVEBU=y +@@ -17,13 +18,14 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x800000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_OF_BOARD_SETUP=y +diff -ruN u-boot-2021.10/configs/tuxx1_defconfig u-boot/configs/tuxx1_defconfig +--- u-boot-2021.10/configs/tuxx1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/tuxx1_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -141,6 +141,7 @@ + CONFIG_ACR_PARKM_USB_I2C1_BOOT=y + CONFIG_LCRR_EADC_1=y + CONFIG_LCRR_CLKDIV_2=y ++CONFIG_SYS_LOAD_ADDR=0x100000 + CONFIG_OF_BOARD_SETUP=y + CONFIG_OF_STDOUT_VIA_ALIAS=y + CONFIG_AUTOBOOT_KEYED=y +@@ -154,6 +155,8 @@ + CONFIG_CMD_ASKENV=y + CONFIG_CMD_GREPENV=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_I2C=y + CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y +@@ -172,6 +175,13 @@ + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DM_BOOTCOUNT=y + CONFIG_BOOTCOUNT_MEM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_FSL=y ++CONFIG_SYS_FSL_I2C_OFFSET=0x3000 ++CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y ++CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 ++CONFIG_SYS_I2C_SLAVE=0x7F ++CONFIG_SYS_I2C_SPEED=200000 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_NOR_FLASH=y +diff -ruN u-boot-2021.10/configs/u200_defconfig u-boot/configs/u200_defconfig +--- u-boot-2021.10/configs/u200_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/u200_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" u200" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/udoo_defconfig u-boot/configs/udoo_defconfig +--- u-boot-2021.10/configs/udoo_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/udoo_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -9,16 +9,16 @@ + CONFIG_ENV_OFFSET=0x60000 + CONFIG_MX6QDL=y + CONFIG_TARGET_UDOO=y ++CONFIG_SYS_MALLOC_LEN=0x0200000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" + CONFIG_BOARD_EARLY_INIT_F=y +@@ -39,6 +39,7 @@ + CONFIG_DM=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/udoo_neo_defconfig u-boot/configs/udoo_neo_defconfig +--- u-boot-2021.10/configs/udoo_neo_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/udoo_neo_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -9,16 +9,17 @@ + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6SX=y + CONFIG_TARGET_UDOO_NEO=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_SPL_ENV_SUPPORT=y +@@ -36,6 +37,9 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_BOUNCE_BUFFER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +@@ -46,5 +50,7 @@ + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_IMX_THERMAL=y +diff -ruN u-boot-2021.10/configs/uDPU_defconfig u-boot/configs/uDPU_defconfig +--- u-boot-2021.10/configs/uDPU_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/uDPU_defconfig 2021-11-01 17:10:14.199595949 +0100 +@@ -14,6 +14,7 @@ + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SYS_LOAD_ADDR=0x6000000 + CONFIG_FIT=y + CONFIG_SPI_BOOT=y + CONFIG_USE_PREBOOT=y +diff -ruN u-boot-2021.10/configs/uniphier_ld4_sld8_defconfig u-boot/configs/uniphier_ld4_sld8_defconfig +--- u-boot-2021.10/configs/uniphier_ld4_sld8_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/uniphier_ld4_sld8_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,10 +6,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref" + CONFIG_SPL_TEXT_BASE=0x00040000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MICRO_SUPPORT_CARD=y ++CONFIG_SYS_LOAD_ADDR=0x85000000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" + CONFIG_USE_PREBOOT=y +@@ -19,6 +20,7 @@ + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_CMD_CONFIG=y + # CONFIG_CMD_XIMG is not set ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -39,12 +41,14 @@ + CONFIG_GPIO_UNIPHIER=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_UNIPHIER=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_DENALI_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_SPL_NAND_DENALI=y + CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 + CONFIG_SMC911X=y +diff -ruN u-boot-2021.10/configs/uniphier_v7_defconfig u-boot/configs/uniphier_v7_defconfig +--- u-boot-2021.10/configs/uniphier_v7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/uniphier_v7_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,10 +6,11 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" + CONFIG_SPL_TEXT_BASE=0x00100000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_MICRO_SUPPORT_CARD=y ++CONFIG_SYS_LOAD_ADDR=0x85000000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" + CONFIG_USE_PREBOOT=y +@@ -19,6 +20,7 @@ + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_CMD_CONFIG=y + # CONFIG_CMD_XIMG is not set ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -40,12 +42,14 @@ + CONFIG_GPIO_UNIPHIER=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_UNIPHIER=y + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_DENALI_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 + CONFIG_SPL_NAND_DENALI=y + CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 + CONFIG_SNI_AVE=y +diff -ruN u-boot-2021.10/configs/uniphier_v8_defconfig u-boot/configs/uniphier_v8_defconfig +--- u-boot-2021.10/configs/uniphier_v8_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/uniphier_v8_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -9,6 +9,7 @@ + CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" + CONFIG_ARCH_UNIPHIER_V8_MULTI=y + CONFIG_MICRO_SUPPORT_CARD=y ++CONFIG_SYS_LOAD_ADDR=0x85000000 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" + CONFIG_USE_PREBOOT=y +@@ -16,6 +17,7 @@ + CONFIG_LOGLEVEL=6 + CONFIG_CMD_CONFIG=y + # CONFIG_CMD_XIMG is not set ++CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -35,7 +37,6 @@ + CONFIG_GPIO_UNIPHIER=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_HS400_SUPPORT=y +@@ -46,6 +47,7 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_DENALI_DT=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SNI_AVE=y + CONFIG_PINCONF=y + CONFIG_SPI=y +diff -ruN u-boot-2021.10/configs/usb_a9263_dataflash_defconfig u-boot/configs/usb_a9263_dataflash_defconfig +--- u-boot-2021.10/configs/usb_a9263_dataflash_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/usb_a9263_dataflash_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x23f00000 +@@ -8,8 +9,10 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x2000 + CONFIG_ENV_SECT_SIZE=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x26000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="usb_a9263" ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/usbarmory_defconfig u-boot/configs/usbarmory_defconfig +--- u-boot-2021.10/configs/usbarmory_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/usbarmory_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -7,10 +7,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x60000 + CONFIG_TARGET_USBARMORY=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory" + # CONFIG_CMD_BMODE is not set + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x72000000 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_CMD_MEMTEST=y + CONFIG_CMD_FUSE=y +@@ -23,6 +27,8 @@ + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_PINCTRL=y +diff -ruN u-boot-2021.10/configs/UTOO_P66_defconfig u-boot/configs/UTOO_P66_defconfig +--- u-boot-2021.10/configs/UTOO_P66_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/UTOO_P66_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -7,9 +7,7 @@ + CONFIG_DRAM_EMR1=0 + CONFIG_MMC0_CD_PIN="PG0" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_USB0_VBUS_PIN="PB04" +-CONFIG_USB0_VBUS_DET="PG01" +-CONFIG_USB0_ID_DET="PG2" ++CONFIG_DM_REGULATOR_FIXED=y + CONFIG_AXP_GPIO=y + # CONFIG_VIDEO_HDMI is not set + CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0" +@@ -21,6 +19,9 @@ + CONFIG_VIDEO_LCD_TL059WV5C0=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_CONS_INDEX=2 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/variscite_dart6ul_defconfig u-boot/configs/variscite_dart6ul_defconfig +--- u-boot-2021.10/configs/variscite_dart6ul_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/variscite_dart6ul_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -8,14 +8,14 @@ + CONFIG_ENV_SIZE=0x2000 + CONFIG_MX6ULL=y + CONFIG_TARGET_DART_6UL=y ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTDELAY=3 + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_SPL_USB_HOST=y +diff -ruN u-boot-2021.10/configs/venice2_defconfig u-boot/configs/venice2_defconfig +--- u-boot-2021.10/configs/venice2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/venice2_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -4,10 +4,12 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFE000 ++CONFIG_SYS_MALLOC_LEN=0x2500000 + CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_TEGRA124=y + CONFIG_TARGET_VENICE2=y ++CONFIG_SYS_LOAD_ADDR=0x81000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff -ruN u-boot-2021.10/configs/ventana_defconfig u-boot/configs/ventana_defconfig +--- u-boot-2021.10/configs/ventana_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/ventana_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -8,6 +8,7 @@ + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_TEGRA20=y + CONFIG_TARGET_VENTANA=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_USE_PREBOOT=y + CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " +diff -ruN u-boot-2021.10/configs/verdin-imx8mm_defconfig u-boot/configs/verdin-imx8mm_defconfig +--- u-boot-2021.10/configs/verdin-imx8mm_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/verdin-imx8mm_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -9,24 +9,22 @@ + CONFIG_SYS_MEMTEST_END=0x80000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xFFFFDE00 +-CONFIG_SYS_I2C_MXC_I2C1=y +-CONFIG_SYS_I2C_MXC_I2C2=y +-CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin" + CONFIG_SPL_TEXT_BASE=0x7E1000 + CONFIG_TARGET_VERDIN_IMX8MM=y +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" + CONFIG_OF_SYSTEM_SETUP=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg" + # CONFIG_USE_BOOTCOMMAND is not set + CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb" + CONFIG_LOG=y +@@ -73,7 +71,6 @@ + CONFIG_CLK_IMX8MM=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y +-CONFIG_SYS_I2C_MXC=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y + CONFIG_SUPPORT_EMMC_BOOT=y +diff -ruN u-boot-2021.10/configs/vexpress_aemv8a_juno_defconfig u-boot/configs/vexpress_aemv8a_juno_defconfig +--- u-boot-2021.10/configs/vexpress_aemv8a_juno_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vexpress_aemv8a_juno_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -7,8 +7,10 @@ + CONFIG_SYS_MEMTEST_END=0xff000000 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_SECT_SIZE=0x10000 ++CONFIG_SYS_MALLOC_LEN=0x810000 + CONFIG_IDENT_STRING=" vexpress_aemv8a" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x90000000 + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" +diff -ruN u-boot-2021.10/configs/vexpress_aemv8a_semi_defconfig u-boot/configs/vexpress_aemv8a_semi_defconfig +--- u-boot-2021.10/configs/vexpress_aemv8a_semi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vexpress_aemv8a_semi_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -7,8 +7,10 @@ + CONFIG_SYS_MEMTEST_END=0xff000000 + CONFIG_ENV_SIZE=0x40000 + CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_SYS_MALLOC_LEN=0x840000 + CONFIG_IDENT_STRING=" vexpress_aemv8a" + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x90000000 + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/vexpress_ca9x4_defconfig u-boot/configs/vexpress_ca9x4_defconfig +--- u-boot-2021.10/configs/vexpress_ca9x4_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/configs/vexpress_ca9x4_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -0,0 +1,46 @@ ++CONFIG_ARM=y ++CONFIG_TARGET_VEXPRESS_CA9X4=y ++CONFIG_SYS_TEXT_BASE=0x60800000 ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SECT_SIZE=0x40000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9" ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x90000000 ++CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" ++CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_DISPLAY_BOARDINFO is not set ++# CONFIG_CMD_CONSOLE is not set ++# CONFIG_CMD_BOOTD is not set ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_LOADB is not set ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SETEXPR is not set ++# CONFIG_CMD_NFS is not set ++# CONFIG_CMD_SLEEP is not set ++CONFIG_CMD_UBI=y ++CONFIG_OF_CONTROL=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_FLASH=y ++CONFIG_ENV_ADDR=0x47F80000 ++CONFIG_DM=y ++CONFIG_CLK=y ++CONFIG_ARM_PL180_MMCI=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_NOR_FLASH=y ++CONFIG_CFI_FLASH=y ++CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y ++CONFIG_SYS_FLASH_PROTECTION=y ++CONFIG_SYS_FLASH_CFI=y ++CONFIG_DM_ETH=y ++CONFIG_SMC911X=y ++CONFIG_SMC911X_32_BIT=y ++CONFIG_BAUDRATE=38400 ++CONFIG_CONS_INDEX=0 +diff -ruN u-boot-2021.10/configs/vf610twr_defconfig u-boot/configs/vf610twr_defconfig +--- u-boot-2021.10/configs/vf610twr_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vf610twr_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_VF610=y + CONFIG_SYS_TEXT_BASE=0x3f401000 +@@ -7,9 +8,12 @@ + CONFIG_SYS_MEMTEST_END=0x87c00000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x202000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_LOGLEVEL=3 + CONFIG_BOARD_EARLY_INIT_F=y +@@ -37,9 +41,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_VYBRID_GPIO=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_NAND_VF610_NFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/vf610twr_nand_defconfig u-boot/configs/vf610twr_nand_defconfig +--- u-boot-2021.10/configs/vf610twr_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vf610twr_nand_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_THUMB_BUILD=y + CONFIG_ARCH_VF610=y + CONFIG_SYS_TEXT_BASE=0x3f401000 +@@ -7,9 +8,12 @@ + CONFIG_SYS_MEMTEST_END=0x87c00000 + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x180000 ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x0220000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="vf610-twr" +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" ++CONFIG_SYS_LOAD_ADDR=0x82000000 + CONFIG_BOOTDELAY=3 + CONFIG_LOGLEVEL=3 + CONFIG_BOARD_EARLY_INIT_F=y +@@ -37,9 +41,12 @@ + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM=y + CONFIG_VYBRID_GPIO=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_ESDHC_IMX=y + CONFIG_MTD=y + CONFIG_NAND_VF610_NFC=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_BUSWIDTH_16BIT=y + CONFIG_PHYLIB=y + CONFIG_PHY_MICREL=y +diff -ruN u-boot-2021.10/configs/vinco_defconfig u-boot/configs/vinco_defconfig +--- u-boot-2021.10/configs/vinco_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vinco_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_AT91=y + CONFIG_SYS_TEXT_BASE=0x20f00000 +@@ -9,6 +10,7 @@ + CONFIG_ENV_SECT_SIZE=0x1000 + CONFIG_DEFAULT_DEVICE_TREE="at91-vinco" + CONFIG_ENV_VARS_UBOOT_CONFIG=y ++CONFIG_SYS_LOAD_ADDR=0x22000000 + CONFIG_SPI_BOOT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +diff -ruN u-boot-2021.10/configs/vining_2000_defconfig u-boot/configs/vining_2000_defconfig +--- u-boot-2021.10/configs/vining_2000_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vining_2000_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -11,11 +11,14 @@ + CONFIG_MX6SX=y + CONFIG_MX6_DDRCAL=y + CONFIG_TARGET_SOFTING_VINING_2000=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0x300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x90000 + CONFIG_SPL_LIBDISK_SUPPORT=y +@@ -23,7 +26,6 @@ + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" + CONFIG_BOOTDELAY=0 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_BOARD_EARLY_INIT_F=y +@@ -61,6 +63,9 @@ + CONFIG_SYS_MMC_ENV_PART=1 + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_BOUNCE_BUFFER=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_RPMB=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y +@@ -73,6 +78,8 @@ + CONFIG_PCI=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_PWM_IMX=y + CONFIG_DM_SERIAL=y + CONFIG_MXC_UART=y +diff -ruN u-boot-2021.10/configs/vocore2_defconfig u-boot/configs/vocore2_defconfig +--- u-boot-2021.10/configs/vocore2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vocore2_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,10 +1,12 @@ + CONFIG_MIPS=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x1000 + CONFIG_ENV_OFFSET=0x04e000 + CONFIG_ENV_SECT_SIZE=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x1000000 + CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" + CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c + CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +@@ -13,11 +15,14 @@ + CONFIG_ARCH_MTMIPS=y + CONFIG_SOC_MT7628=y + CONFIG_BOARD_VOCORE2=y ++CONFIG_MIPS_CACHE_SETUP=y ++CONFIG_MIPS_CACHE_DISABLE=y + CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y + CONFIG_MIPS_BOOT_FDT=y + CONFIG_ENV_VARS_UBOOT_CONFIG=y + CONFIG_SYS_BOOT_GET_CMDLINE=y + CONFIG_SYS_BOOT_GET_KBD=y ++CONFIG_SYS_LOAD_ADDR=0x80100000 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_LEGACY_IMAGE_FORMAT=y +diff -ruN u-boot-2021.10/configs/vyasa-rk3288_defconfig u-boot/configs/vyasa-rk3288_defconfig +--- u-boot-2021.10/configs/vyasa-rk3288_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/vyasa-rk3288_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,6 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y ++CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y + # CONFIG_SPL_USE_ARCH_MEMCPY is not set + # CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_ROCKCHIP=y +@@ -12,6 +14,7 @@ + CONFIG_DEBUG_UART_BASE=0xff690000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 + CONFIG_USE_PREBOOT=y + CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" + CONFIG_SILENT_CONSOLE=y +diff -ruN u-boot-2021.10/configs/wandboard_defconfig u-boot/configs/wandboard_defconfig +--- u-boot-2021.10/configs/wandboard_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/wandboard_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -12,11 +12,12 @@ + CONFIG_SYS_I2C_MXC_I2C1=y + CONFIG_SYS_I2C_MXC_I2C2=y + CONFIG_SYS_I2C_MXC_I2C3=y ++CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1" + CONFIG_SPL_TEXT_BASE=0x00908000 +-CONFIG_SPL_MMC_SUPPORT=y +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_MMC=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_SPL_LIBDISK_SUPPORT=y + CONFIG_CMD_HDMIDETECT=y +@@ -26,7 +27,6 @@ + CONFIG_SPL_FIT_PRINT=y + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" + CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" + # CONFIG_CONSOLE_MUX is not set + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +@@ -57,6 +57,7 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DWC_AHSATA=y + CONFIG_DM_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +diff -ruN u-boot-2021.10/configs/warp7_bl33_defconfig u-boot/configs/warp7_bl33_defconfig +--- u-boot-2021.10/configs/warp7_bl33_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/warp7_bl33_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -4,6 +4,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x80000 ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" + CONFIG_TARGET_WARP7=y +@@ -12,7 +13,6 @@ + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" + CONFIG_HUSH_PARSER=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_MEMTEST=y +@@ -32,11 +32,13 @@ + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -67,4 +69,3 @@ + CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_OPTEE_TZDRAM_SIZE=0x02000000 +-CONFIG_OPTEE_TZDRAM_BASE=0x9e000000 +diff -ruN u-boot-2021.10/configs/warp7_defconfig u-boot/configs/warp7_defconfig +--- u-boot-2021.10/configs/warp7_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/warp7_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MEMTEST_END=0xa0000000 + CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0xC0000 ++CONFIG_SYS_MALLOC_LEN=0x2300000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" + CONFIG_TARGET_WARP7=y +@@ -15,7 +16,6 @@ + CONFIG_IMX_HAB=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" + CONFIG_HUSH_PARSER=y + # CONFIG_CMD_BOOTD is not set + CONFIG_CMD_BOOTZ=y +@@ -38,11 +38,13 @@ + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 + CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +@@ -71,7 +73,5 @@ + CONFIG_USB_ETHER=y + CONFIG_USB_ETH_CDC=y + CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" +-CONFIG_OPTEE_LOAD_ADDR=0x84000000 + CONFIG_OPTEE_TZDRAM_SIZE=0x3000000 +-CONFIG_OPTEE_TZDRAM_BASE=0x9d000000 + CONFIG_BOOTM_OPTEE=y +diff -ruN u-boot-2021.10/configs/warp_defconfig u-boot/configs/warp_defconfig +--- u-boot-2021.10/configs/warp_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/warp_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,9 +6,11 @@ + CONFIG_ENV_OFFSET=0x60000 + CONFIG_MX6SL=y + CONFIG_TARGET_WARP=y ++CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_SYS_I2C_MXC_I2C2=y ++CONFIG_SYS_MALLOC_LEN=0x2300000 + # CONFIG_CMD_BMODE is not set + CONFIG_SUPPORT_RAW_INITRD=y +-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg" + CONFIG_BOOTDELAY=3 + CONFIG_BOARD_EARLY_INIT_F=y + CONFIG_HUSH_PARSER=y +@@ -32,8 +34,12 @@ + CONFIG_BOUNCE_BUFFER=y + CONFIG_DFU_MMC=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MXC=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_FSL_USDHC=y ++CONFIG_POWER_LEGACY=y ++CONFIG_POWER_I2C=y + CONFIG_MXC_UART=y + CONFIG_USB=y + CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 +diff -ruN u-boot-2021.10/configs/wetek-core2_defconfig u-boot/configs/wetek-core2_defconfig +--- u-boot-2021.10/configs/wetek-core2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/wetek-core2_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -10,6 +10,7 @@ + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_IDENT_STRING=" wetek-core2" + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_OF_BOARD_SETUP=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_MISC_INIT_R=y +diff -ruN u-boot-2021.10/configs/Wexler_TAB7200_defconfig u-boot/configs/Wexler_TAB7200_defconfig +--- u-boot-2021.10/configs/Wexler_TAB7200_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Wexler_TAB7200_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -4,9 +4,8 @@ + CONFIG_SPL=y + CONFIG_MACH_SUN7I=y + CONFIG_DRAM_CLK=384 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PH4" ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_POWER="PH8" +@@ -14,6 +13,9 @@ + CONFIG_VIDEO_LCD_BL_PWM="PB2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/Wits_Pro_A20_DKT_defconfig u-boot/configs/Wits_Pro_A20_DKT_defconfig +--- u-boot-2021.10/configs/Wits_Pro_A20_DKT_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Wits_Pro_A20_DKT_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -14,6 +14,9 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y + CONFIG_SCSI_AHCI=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_PHY_REALTEK=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y +@@ -22,3 +25,4 @@ + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/Wobo_i5_defconfig u-boot/configs/Wobo_i5_defconfig +--- u-boot-2021.10/configs/Wobo_i5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Wobo_i5_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -5,9 +5,12 @@ + CONFIG_MACH_SUN5I=y + CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PB3" +-CONFIG_USB1_VBUS_PIN="PG12" ++CONFIG_DM_REGULATOR_FIXED=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_AXP_ALDO3_VOLT=3300 + CONFIG_AXP_ALDO4_VOLT=3300 + CONFIG_CONS_INDEX=2 +diff -ruN u-boot-2021.10/configs/work_92105_defconfig u-boot/configs/work_92105_defconfig +--- u-boot-2021.10/configs/work_92105_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/work_92105_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_CPU_INIT=y +@@ -12,10 +13,12 @@ + CONFIG_CMD_MAX6957=y + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0x100000 ++CONFIG_SYS_MALLOC_LEN=0x100000 + CONFIG_SPL_TEXT_BASE=0x00000000 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_ENV_OFFSET_REDUND=0x120000 ++CONFIG_SYS_LOAD_ADDR=0x80008000 + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS2,115200n8" +@@ -29,6 +32,7 @@ + CONFIG_SPL_NAND_BASE=y + CONFIG_HUSH_PARSER=y + CONFIG_CMD_EEPROM=y ++CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -42,10 +46,17 @@ + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_VERSION_VARIABLE=y ++CONFIG_SYS_I2C_LEGACY=y ++CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_LPC32XX=y ++CONFIG_SYS_I2C_SPEED=350000 ++CONFIG_SYS_I2C_EEPROM_ADDR=0x56 + # CONFIG_MMC is not set + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y ++CONFIG_NAND_LPC32XX_MLC=y ++CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y ++CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 + CONFIG_PHYLIB=y + CONFIG_PHY_ADDR_ENABLE=y + CONFIG_PHY_SMSC=y +diff -ruN u-boot-2021.10/configs/x530_defconfig u-boot/configs/x530_defconfig +--- u-boot-2021.10/configs/x530_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/x530_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,4 +1,5 @@ + CONFIG_ARM=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_CPU_INIT=y + CONFIG_ARCH_MVEBU=y + CONFIG_SYS_TEXT_BASE=0x00800000 +@@ -13,11 +14,12 @@ + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530" + CONFIG_SPL_TEXT_BASE=0x40000030 +-CONFIG_SPL_SERIAL_SUPPORT=y ++CONFIG_SPL_SERIAL=y + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xd0012000 + CONFIG_DEBUG_UART_CLOCK=250000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SILENT_CONSOLE=y +@@ -58,6 +60,7 @@ + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_NAND_PXA3XX=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_BUS=1 + CONFIG_SF_DEFAULT_SPEED=50000000 + CONFIG_SPI_FLASH_MACRONIX=y +diff -ruN u-boot-2021.10/configs/xenguest_arm64_defconfig u-boot/configs/xenguest_arm64_defconfig +--- u-boot-2021.10/configs/xenguest_arm64_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xenguest_arm64_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -3,7 +3,9 @@ + CONFIG_TARGET_XENGUEST_ARM64=y + CONFIG_SYS_TEXT_BASE=0x40080000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_IDENT_STRING=" xenguest" ++CONFIG_SYS_LOAD_ADDR=0x40000000 + CONFIG_BOOTDELAY=10 + CONFIG_SYS_PROMPT="xenguest# " + # CONFIG_CMD_BDI is not set +diff -ruN u-boot-2021.10/configs/xilinx_versal_mini_defconfig u-boot/configs/xilinx_versal_mini_defconfig +--- u-boot-2021.10/configs/xilinx_versal_mini_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_versal_mini_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -13,6 +13,7 @@ + CONFIG_COUNTER_FREQUENCY=100000000 + # CONFIG_PSCI_RESET is not set + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + # CONFIG_LEGACY_IMAGE_FORMAT is not set + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y +diff -ruN u-boot-2021.10/configs/xilinx_versal_mini_emmc0_defconfig u-boot/configs/xilinx_versal_mini_emmc0_defconfig +--- u-boot-2021.10/configs/xilinx_versal_mini_emmc0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_versal_mini_emmc0_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -10,6 +10,7 @@ + CONFIG_COUNTER_FREQUENCY=100000000 + # CONFIG_PSCI_RESET is not set + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/xilinx_versal_mini_emmc1_defconfig u-boot/configs/xilinx_versal_mini_emmc1_defconfig +--- u-boot-2021.10/configs/xilinx_versal_mini_emmc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_versal_mini_emmc1_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -10,6 +10,7 @@ + CONFIG_COUNTER_FREQUENCY=100000000 + # CONFIG_PSCI_RESET is not set + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + # CONFIG_AUTOBOOT is not set + CONFIG_SYS_CONSOLE_INFO_QUIET=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/xilinx_versal_virt_defconfig u-boot/configs/xilinx_versal_virt_defconfig +--- u-boot-2021.10/configs/xilinx_versal_virt_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_versal_virt_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -11,6 +11,7 @@ + CONFIG_DEFINE_TCM_OCM_MMAP=y + CONFIG_COUNTER_FREQUENCY=100000000 + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +@@ -61,7 +62,6 @@ + CONFIG_SYS_I2C_CADENCE=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_I2C_EEPROM_ADDR=0x0 + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_defconfig u-boot/configs/xilinx_zynqmp_mini_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,10 +6,12 @@ + CONFIG_SYS_MEMTEST_START=0x00000000 + CONFIG_SYS_MEMTEST_END=0x00001000 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x1a00 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" + CONFIG_SYS_MEM_RSVD_FOR_MMU=y + CONFIG_ZYNQMP_PSU_INIT_ENABLED=y + # CONFIG_CMD_ZYNQMP is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + # CONFIG_LEGACY_IMAGE_FORMAT is not set + # CONFIG_AUTOBOOT is not set + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_emmc0_defconfig u-boot/configs/xilinx_zynqmp_mini_emmc0_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_emmc0_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_emmc0_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,10 +6,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0x1000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 + CONFIG_SPL=y + # CONFIG_CMD_ZYNQMP is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_AUTOBOOT is not set +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_emmc1_defconfig u-boot/configs/xilinx_zynqmp_mini_emmc1_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_emmc1_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_emmc1_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -6,10 +6,12 @@ + CONFIG_SYS_MALLOC_F_LEN=0x1000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1" + CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 + CONFIG_SPL=y + # CONFIG_CMD_ZYNQMP is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_AUTOBOOT is not set +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_nand_defconfig u-boot/configs/xilinx_zynqmp_mini_nand_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_nand_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -5,8 +5,10 @@ + CONFIG_SYS_TEXT_BASE=0x10000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" + # CONFIG_CMD_ZYNQMP is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_AUTOBOOT is not set +@@ -52,6 +54,7 @@ + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ARASAN=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_MAX_CHIPS=2 + CONFIG_ARM_DCC=y + CONFIG_PANIC_HANG=y +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_nand_single_defconfig u-boot/configs/xilinx_zynqmp_mini_nand_single_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_nand_single_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_nand_single_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -5,8 +5,10 @@ + CONFIG_SYS_TEXT_BASE=0x10000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x800000 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" + # CONFIG_CMD_ZYNQMP is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_SUPPORT_RAW_INITRD=y + # CONFIG_AUTOBOOT is not set +@@ -52,6 +54,7 @@ + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ARASAN=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_ARM_DCC=y + CONFIG_PANIC_HANG=y + # CONFIG_GZIP is not set +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_mini_qspi_defconfig u-boot/configs/xilinx_zynqmp_mini_qspi_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_mini_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_mini_qspi_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_TEXT_BASE=0xFFFC0000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x80 ++CONFIG_SYS_MALLOC_LEN=0x1a00 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" + CONFIG_SPL=y + CONFIG_SYS_MEM_RSVD_FOR_MMU=y +@@ -12,6 +13,7 @@ + # CONFIG_CMD_ZYNQMP is not set + # CONFIG_PSCI_RESET is not set + # CONFIG_EXPERT is not set ++CONFIG_SYS_LOAD_ADDR=0x8000000 + # CONFIG_LEGACY_IMAGE_FORMAT is not set + # CONFIG_AUTOBOOT is not set + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_r5_defconfig u-boot/configs/xilinx_zynqmp_r5_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_r5_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_r5_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,13 +1,16 @@ + CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y + CONFIG_ARCH_ZYNQMP_R5=y + CONFIG_SYS_TEXT_BASE=0x10000000 + CONFIG_SYS_MALLOC_F_LEN=0x1000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x1400000 + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5" + CONFIG_DEBUG_UART_BASE=0xff010000 + CONFIG_DEBUG_UART_CLOCK=100000000 + CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_BOOTSTAGE=y + # CONFIG_DISPLAY_CPUINFO is not set + CONFIG_SYS_PROMPT="ZynqMP r5> " +diff -ruN u-boot-2021.10/configs/xilinx_zynqmp_virt_defconfig u-boot/configs/xilinx_zynqmp_virt_defconfig +--- u-boot-2021.10/configs/xilinx_zynqmp_virt_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynqmp_virt_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -5,6 +5,7 @@ + CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SYS_MEMTEST_START=0x00000000 + CONFIG_SYS_MEMTEST_END=0x00001000 ++CONFIG_SYS_MALLOC_LEN=0x4040000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" + CONFIG_SPL_STACK_R_ADDR=0x18000000 +@@ -12,13 +13,14 @@ + CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 + CONFIG_SPL=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_SPL_SPI=y + CONFIG_ZYNQ_MAC_IN_EEPROM=y + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 + CONFIG_CMD_FRU=y + CONFIG_ZYNQMP_USB=y + CONFIG_AHCI=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x8000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_LOAD_FIT=y +@@ -122,7 +124,6 @@ + CONFIG_LED_GPIO=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_I2C_EEPROM_ADDR=0x0 + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y +@@ -134,6 +135,7 @@ + CONFIG_DM_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ARASAN=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SYS_NAND_MAX_CHIPS=2 + CONFIG_SPI_FLASH_BAR=y + CONFIG_SF_DUAL_FLASH=y +diff -ruN u-boot-2021.10/configs/xilinx_zynq_virt_defconfig u-boot/configs/xilinx_zynq_virt_defconfig +--- u-boot-2021.10/configs/xilinx_zynq_virt_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xilinx_zynq_virt_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -14,6 +14,7 @@ + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y + CONFIG_FIT_VERBOSE=y +@@ -49,6 +50,7 @@ + # CONFIG_CMD_SETEXPR is not set + CONFIG_CMD_TFTPPUT=y + CONFIG_CMD_CACHE=y ++CONFIG_CMD_EFIDEBUG=y + CONFIG_CMD_TIME=y + CONFIG_CMD_TIMER=y + CONFIG_CMD_EXT4_WRITE=y +@@ -69,6 +71,8 @@ + CONFIG_DFU_TIMEOUT=y + CONFIG_DFU_MMC=y + CONFIG_DFU_RAM=y ++CONFIG_DFU_SF=y ++CONFIG_SET_DFU_ALT_INFO=y + CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 + CONFIG_FPGA_XILINX=y + CONFIG_FPGA_ZYNQPL=y +@@ -80,7 +84,6 @@ + CONFIG_LED_GPIO=y + CONFIG_MISC=y + CONFIG_I2C_EEPROM=y +-CONFIG_SYS_I2C_EEPROM_ADDR=0x0 + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ZYNQ=y +@@ -91,6 +94,7 @@ + CONFIG_SYS_FLASH_CFI=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ZYNQ=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_SF_DEFAULT_SPEED=30000000 + CONFIG_SPI_FLASH_ISSI=y + CONFIG_SPI_FLASH_MACRONIX=y +@@ -122,3 +126,6 @@ + CONFIG_USB_FUNCTION_THOR=y + CONFIG_DISPLAY=y + CONFIG_SPL_GZIP=y ++CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +diff -ruN u-boot-2021.10/configs/xtfpga_defconfig u-boot/configs/xtfpga_defconfig +--- u-boot-2021.10/configs/xtfpga_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/xtfpga_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -2,7 +2,9 @@ + CONFIG_SYS_CPU="dc233c" + CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_SECT_SIZE=0x20000 ++CONFIG_SYS_MALLOC_LEN=0x40000 + CONFIG_XTFPGA_KC705=y ++CONFIG_SYS_LOAD_ADDR=0x02000000 + CONFIG_SHOW_BOOT_PROGRESS=y + CONFIG_BOOTDELAY=10 + CONFIG_AUTOBOOT_KEYED=y +diff -ruN u-boot-2021.10/configs/Yones_Toptech_BD1078_defconfig u-boot/configs/Yones_Toptech_BD1078_defconfig +--- u-boot-2021.10/configs/Yones_Toptech_BD1078_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Yones_Toptech_BD1078_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,10 +6,10 @@ + CONFIG_DRAM_CLK=408 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_MMC1_CD_PIN="PH2" +-CONFIG_MMC1_PINS="PH" ++CONFIG_MMC1_PINS_PH=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +-CONFIG_USB0_VBUS_PIN="PB9" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +@@ -20,4 +20,7 @@ + CONFIG_VIDEO_LCD_PANEL_LVDS=y + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL_I2C=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 + CONFIG_USB_MUSB_HOST=y +diff -ruN u-boot-2021.10/configs/Yones_Toptech_BS1078_V2_defconfig u-boot/configs/Yones_Toptech_BS1078_V2_defconfig +--- u-boot-2021.10/configs/Yones_Toptech_BS1078_V2_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/Yones_Toptech_BS1078_V2_defconfig 2021-11-01 17:10:14.166264440 +0100 +@@ -6,9 +6,8 @@ + CONFIG_DRAM_CLK=420 + CONFIG_DRAM_ZQ=251 + CONFIG_MMC0_CD_PIN="PA8" +-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +-CONFIG_USB0_ID_DET="PA15" ++CONFIG_REGULATOR_AXP=y ++CONFIG_REGULATOR_AXP_USB_POWER=y + CONFIG_AXP_GPIO=y + CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0" + CONFIG_VIDEO_LCD_DCLK_PHASE=0 +@@ -18,3 +17,4 @@ + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_AXP_DLDO1_VOLT=3300 + CONFIG_USB_MUSB_HOST=y ++CONFIG_DM_REGULATOR_FIXED=y +diff -ruN u-boot-2021.10/configs/zmx25_defconfig u-boot/configs/zmx25_defconfig +--- u-boot-2021.10/configs/zmx25_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/zmx25_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,35 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_ARCH_MX25=y +-CONFIG_SYS_TEXT_BASE=0xA0000000 +-CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x20000 +-CONFIG_ENV_SECT_SIZE=0x20000 +-CONFIG_TARGET_ZMX25=y +-CONFIG_BOOTDELAY=5 +-CONFIG_AUTOBOOT_KEYED=y +-CONFIG_AUTOBOOT_PROMPT="boot in %d s\n" +-CONFIG_AUTOBOOT_DELAY_STR="delaygs" +-CONFIG_AUTOBOOT_STOP_STR="stopgs" +-CONFIG_USE_PREBOOT=y +-# CONFIG_DISPLAY_CPUINFO is not set +-# CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_HUSH_PARSER=y +-# CONFIG_AUTO_COMPLETE is not set +-CONFIG_SYS_PROMPT="zmx25> " +-CONFIG_CMD_IMLS=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_DHCP=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_CACHE=y +-CONFIG_CMD_FAT=y +-CONFIG_ENV_IS_IN_FLASH=y +-CONFIG_ENV_ADDR=0xA0040000 +-# CONFIG_MMC is not set +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_FLASH_CFI_DRIVER=y +-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +-CONFIG_SYS_FLASH_CFI=y +-CONFIG_MII=y +-CONFIG_MXC_UART=y +-CONFIG_USB=y +-CONFIG_LZO=y +diff -ruN u-boot-2021.10/configs/zynq_cse_nand_defconfig u-boot/configs/zynq_cse_nand_defconfig +--- u-boot-2021.10/configs/zynq_cse_nand_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/zynq_cse_nand_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,5 +1,7 @@ + CONFIG_ARM=y + CONFIG_SYS_CONFIG_NAME="zynq_cse" ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_ZYNQ=y +@@ -11,6 +13,7 @@ + CONFIG_SPL=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + # CONFIG_AUTOBOOT is not set + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +@@ -57,5 +60,6 @@ + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_NAND_ZYNQ=y ++CONFIG_SYS_NAND_ONFI_DETECTION=y + CONFIG_ARM_DCC=y + # CONFIG_GZIP is not set +diff -ruN u-boot-2021.10/configs/zynq_cse_nor_defconfig u-boot/configs/zynq_cse_nor_defconfig +--- u-boot-2021.10/configs/zynq_cse_nor_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/zynq_cse_nor_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,5 +1,7 @@ + CONFIG_ARM=y + CONFIG_SYS_CONFIG_NAME="zynq_cse" ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_ZYNQ=y +@@ -11,6 +13,7 @@ + CONFIG_SPL=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + # CONFIG_AUTOBOOT is not set + CONFIG_USE_PREBOOT=y + # CONFIG_DISPLAY_CPUINFO is not set +diff -ruN u-boot-2021.10/configs/zynq_cse_qspi_defconfig u-boot/configs/zynq_cse_qspi_defconfig +--- u-boot-2021.10/configs/zynq_cse_qspi_defconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/configs/zynq_cse_qspi_defconfig 2021-11-01 17:10:14.202929101 +0100 +@@ -1,5 +1,7 @@ + CONFIG_ARM=y + CONFIG_SYS_CONFIG_NAME="zynq_cse" ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SPL_SKIP_LOWLEVEL_INIT=y + CONFIG_SYS_ICACHE_OFF=y + CONFIG_SYS_DCACHE_OFF=y + CONFIG_ARCH_ZYNQ=y +@@ -16,6 +18,7 @@ + CONFIG_DEBUG_UART=y + CONFIG_SYS_CUSTOM_LDSCRIPT=y + CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" ++CONFIG_SYS_LOAD_ADDR=0x0 + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set + # CONFIG_AUTOBOOT is not set + CONFIG_USE_PREBOOT=y +diff -ruN u-boot-2021.10/disk/Makefile u-boot/disk/Makefile +--- u-boot-2021.10/disk/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/disk/Makefile 2021-11-01 17:10:14.202929101 +0100 +@@ -5,7 +5,7 @@ + + #ccflags-y += -DET_DEBUG -DDEBUG + +-obj-$(CONFIG_PARTITIONS) += part.o ++obj-$(CONFIG_PARTITIONS) += part.o + obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o + obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o + obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o +diff -ruN u-boot-2021.10/disk/part_efi.c u-boot/disk/part_efi.c +--- u-boot-2021.10/disk/part_efi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/disk/part_efi.c 2021-11-01 17:10:14.202929101 +0100 +@@ -23,12 +23,11 @@ + #include + #include + #include ++#include + #include + #include + #include + +-DECLARE_GLOBAL_DATA_PTR; +- + #ifdef CONFIG_HAVE_BLOCK_DEVICE + + /* GUID for basic data partitons */ +@@ -563,9 +562,8 @@ + * from the start of the device) to be specified as a property + * of the device tree '/config' node. + */ +- config_offset = fdtdec_get_config_int(gd->fdt_blob, +- "u-boot,efi-partition-entries-offset", +- -EINVAL); ++ config_offset = ofnode_conf_read_int( ++ "u-boot,efi-partition-entries-offset", -EINVAL); + if (config_offset != -EINVAL) { + offset_bytes = PAD_TO_BLOCKSIZE(config_offset, dev_desc); + offset_blks = offset_bytes / dev_desc->blksz; +diff -ruN u-boot-2021.10/disk/part_iso.c u-boot/disk/part_iso.c +--- u-boot-2021.10/disk/part_iso.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/disk/part_iso.c 2021-11-01 17:10:14.202929101 +0100 +@@ -220,7 +220,7 @@ + printf("Part Start Sect x Size Type\n"); + i=1; + do { +- printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n", ++ printf(" %2d %8" LBAFlength "u %8" LBAFlength "u %6ld %.32s\n", + i, info.start, info.size, info.blksz, info.type); + i++; + } while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1); +diff -ruN u-boot-2021.10/doc/board/amlogic/index.rst u-boot/doc/board/amlogic/index.rst +--- u-boot-2021.10/doc/board/amlogic/index.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/board/amlogic/index.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -10,68 +10,69 @@ + + This matrix concerns the actual source code version. + +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 | +-| | | S805X | S905D | | S905D2 | A311D | S905D3 | +-| | | | | | S905Y2 | | | +-+===============================+===========+=================+==============+============+============+=============+==============+ +-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | +-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | +-| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | +-| | P201 | LibreTech-AC v2 | | | | | | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Infrared Decoder | No | No | No | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| SPI (CC) | No | No | No | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| NAND | No | No | No | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| CEC | No | No | No | *N/A* | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| Thermal Sensor | No | No | No | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +-| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** | +-+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 | ++| | | S805X | S905D | | S905D2 | A311D | S905D3 | ++| | | S905W | | | S905Y2 | | | +++===============================+===========+=================+==============+=============+============+=============+==============+ ++| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | ++| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L | ++| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 | ++| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | ++| | | JetHub J80 | | | | | BananaPi-M5 | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Infrared Decoder | No | No | No | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| SPI (CC) | No | No | No | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| NAND | No | No | No | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| CEC | No | No | No | *N/A* | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| Thermal Sensor | No | No | No | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| LCD/LVDS Output | No | *N/A* | No | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ ++| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** | +++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ + + Board Documentation + ------------------- +@@ -81,6 +82,8 @@ + + beelink-gtking + beelink-gtkingpro ++ jethub-j100 ++ jethub-j80 + khadas-vim2 + khadas-vim3l + khadas-vim3 +@@ -95,6 +98,7 @@ + p201 + p212 + q200 ++ radxa-zero + s400 + sei510 + sei610 +diff -ruN u-boot-2021.10/doc/board/amlogic/jethub-j100.rst u-boot/doc/board/amlogic/jethub-j100.rst +--- u-boot-2021.10/doc/board/amlogic/jethub-j100.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/amlogic/jethub-j100.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -0,0 +1,108 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for JetHub J100 ++======================= ++ ++JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation ++controller manufactured by JetHome with the following specifications: ++ ++ - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz ++ - no video out ++ - 512Mb/1GB DDR3 ++ - 8/16GB eMMC flash ++ - 1 x USB 2.0 ++ - 1 x 10/100Mbps ethernet ++ - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE ++ 802.11a/b/g/n/ac, Bluetooth 4.2. ++ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output ++ power and Zigbee 3.0 support. ++ - 2 x gpio LEDS ++ - GPIO user Button ++ - 1 x 1-Wire ++ - 2 x RS-485 ++ - 4 x dry contact digital GPIO inputs ++ - 3 x relay GPIO outputs ++ - DC source with a voltage of 9 to 56 V / Passive POE ++ - DIN Rail Mounting case ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make jethub_j100_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic doesn't provide sources for the firmware and for tools needed ++to create the bootloader image, so it is necessary to obtain binaries ++from the git tree published by the board vendor: ++ ++.. code-block:: bash ++ ++ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot ++ $ cd jethub-u-boot ++ $ export FIPDIR=$PWD ++ ++Go back to mainline U-boot source tree then : ++ ++.. code-block:: bash ++ ++ $ mkdir fip ++ ++ $ cp $FIPDIR/j100/bl2.bin fip/ ++ $ cp $FIPDIR/j100/acs.bin fip/ ++ $ cp $FIPDIR/j100/bl21.bin fip/ ++ $ cp $FIPDIR/j100/bl30.bin fip/ ++ $ cp $FIPDIR/j100/bl301.bin fip/ ++ $ cp $FIPDIR/j100/bl31.img fip/ ++ $ cp u-boot.bin fip/bl33.bin ++ ++ $ $FIPDIR/blx_fix.sh \ ++ fip/bl30.bin \ ++ fip/zero_tmp \ ++ fip/bl30_zero.bin \ ++ fip/bl301.bin \ ++ fip/bl301_zero.bin \ ++ fip/bl30_new.bin \ ++ bl30 ++ ++ $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 ++ ++ $ $FIPDIR/blx_fix.sh \ ++ fip/bl2_acs.bin \ ++ fip/zero_tmp \ ++ fip/bl2_zero.bin \ ++ fip/bl21.bin \ ++ fip/bl21_zero.bin \ ++ fip/bl2_new.bin \ ++ bl2 ++ ++ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ ++ --output fip/bl30_new.bin.enc \ ++ --level v3 --type bl30 ++ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \ ++ --output fip/bl31.img.enc \ ++ --level v3 --type bl31 ++ $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ ++ --output fip/bl33.bin.enc \ ++ --level v3 --type bl33 ++ $ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ ++ --output fip/bl2.n.bin.sig ++ $ $FIPDIR/j100/aml_encrypt_axg --bootmk \ ++ --output fip/u-boot.bin \ ++ --bl2 fip/bl2.n.bin.sig \ ++ --bl30 fip/bl30_new.bin.enc \ ++ --bl31 fip/bl31.img.enc \ ++ --bl33 fip/bl33.bin.enc --level v3 ++ ++and then write the image to eMMC with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_emmc_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 +diff -ruN u-boot-2021.10/doc/board/amlogic/jethub-j80.rst u-boot/doc/board/amlogic/jethub-j80.rst +--- u-boot-2021.10/doc/board/amlogic/jethub-j80.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/amlogic/jethub-j80.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -0,0 +1,97 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for JetHub J80 ++====================== ++ ++JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation ++controller manufactured by JetHome with the following specifications: ++ ++ - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz ++ - No video out ++ - 1GB DDR3 ++ - 8/16GB eMMC flash ++ - 2 x USB 2.0 ++ - 1 x 10/100Mbps ethernet ++ - SDIO WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0. ++ - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output ++ power and Zigbee 3.0 support. ++ - MicroSD 2.x/3.x/4.x DS/HS cards. ++ - 1 x gpio LED ++ - ADC user Button ++ - DC source 5V microUSB ++ - Square plastic case ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make jethub_j80_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic doesn't provide sources for the firmware and for tools needed ++to create the bootloader image, so it is necessary to obtain binaries ++from the git tree published by the board vendor: ++ ++.. code-block:: bash ++ ++ $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot ++ $ cd jethub-u-boot ++ $ export FIPDIR=$PWD ++ ++Go back to mainline U-Boot source tree then : ++ ++.. code-block:: bash ++ ++ $ mkdir fip ++ ++ $ cp $FIPDIR/j80/bl2.bin fip/ ++ $ cp $FIPDIR/j80/acs.bin fip/ ++ $ cp $FIPDIR/j80/bl21.bin fip/ ++ $ cp $FIPDIR/j80/bl30.bin fip/ ++ $ cp $FIPDIR/j80/bl301.bin fip/ ++ $ cp $FIPDIR/j80/bl31.img fip/ ++ $ cp u-boot.bin fip/bl33.bin ++ ++ $ $FIPDIR/blx_fix.sh \ ++ fip/bl30.bin \ ++ fip/zero_tmp \ ++ fip/bl30_zero.bin \ ++ fip/bl301.bin \ ++ fip/bl301_zero.bin \ ++ fip/bl30_new.bin \ ++ bl30 ++ ++ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 ++ ++ $ $FIPDIR/blx_fix.sh \ ++ fip/bl2_acs.bin \ ++ fip/zero_tmp \ ++ fip/bl2_zero.bin \ ++ fip/bl21.bin \ ++ fip/bl21_zero.bin \ ++ fip/bl2_new.bin \ ++ bl2 ++ ++ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin ++ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl31.img ++ $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4 ++ $ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig ++ $ $FIPDIR/j80/aml_encrypt_gxl --bootmk \ ++ --output fip/u-boot.bin \ ++ --bl2 fip/bl2.n.bin.sig \ ++ --bl30 fip/bl30_new.bin.enc \ ++ --bl31 fip/bl31.img.enc \ ++ --bl33 fip/bl33.bin.enc ++ ++and then write the image to SD/eMMC with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_sd_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 +diff -ruN u-boot-2021.10/doc/board/amlogic/odroid-c4.rst u-boot/doc/board/amlogic/odroid-c4.rst +--- u-boot-2021.10/doc/board/amlogic/odroid-c4.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/board/amlogic/odroid-c4.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -17,6 +17,9 @@ + - UART serial + - Infrared receiver + ++The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands ++applies for HC4. ++ + Schematics are available on the manufacturer website. + + U-Boot compilation +diff -ruN u-boot-2021.10/doc/board/amlogic/radxa-zero.rst u-boot/doc/board/amlogic/radxa-zero.rst +--- u-boot-2021.10/doc/board/amlogic/radxa-zero.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/amlogic/radxa-zero.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -0,0 +1,74 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for Radxa Zero ++===================== ++ ++Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 ++chipset that ships in a number of RAM/eMMC configurations: ++ ++Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436 ++wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB ++eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac). ++ ++- Amlogic S905Y2 quad-core Cortex-A53 ++- Mali G31-MP2 GPU ++- HDMI 2.1 output (micro) ++- 1x USB 2.0 port - Type C (OTG) ++- 1x USB 3.0 port - Type C (Host) ++- 1x micro SD Card slot ++- 40 Pin GPIO header ++ ++Schematics are available on the manufacturer website: ++ ++https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make radxa-zero_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic does not provide sources for the firmware and for tools needed ++to create the bootloader image, so it is necessary to obtain them from ++git trees published by the board vendor: ++ ++.. code-block:: bash ++ ++ $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git ++ $ git clone https://github.com/radxa/fip.git ++ ++ $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev ++ $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools ++ ++ $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz ++ $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt ++ ++ $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf- ++ $ export ARCH=arm ++ $ cd u-boot ++ $ make radxa-zero_defconfig ++ $ make ++ ++ $ cp u-boot.bin ../fip/radxa-zero/bl33.bin ++ $ cd ../fip/radxa-zero ++ $ make ++ ++This will generate: ++ ++.. code-block:: bash ++ ++ $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl ++ ++Then write the image to SD with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_sd_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 +diff -ruN u-boot-2021.10/doc/board/AndesTech/adp-ag101p.rst u-boot/doc/board/AndesTech/adp-ag101p.rst +--- u-boot-2021.10/doc/board/AndesTech/adp-ag101p.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/board/AndesTech/adp-ag101p.rst 2021-11-01 17:10:14.212928554 +0100 +@@ -23,8 +23,8 @@ + + CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from SPI ROM and bypass e-bios (the +- other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT +- in "include/configs/adp-ag101p.h". ++ other boot loader on ROM). You should enable CONFIG_SKIP_LOWLEVEL_INIT ++ when running menuconfig or similar. + + Build and boot steps + -------------------- +diff -ruN u-boot-2021.10/doc/board/index.rst u-boot/doc/board/index.rst +--- u-boot-2021.10/doc/board/index.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/board/index.rst 2021-11-01 17:10:14.216261705 +0100 +@@ -22,10 +22,12 @@ + openpiton/index + qualcomm/index + rockchip/index ++ siemens/index + sifive/index + sipeed/index + socionext/index + st/index ++ ste/index + tbs/index + ti/index + toradex/index +diff -ruN u-boot-2021.10/doc/board/siemens/index.rst u-boot/doc/board/siemens/index.rst +--- u-boot-2021.10/doc/board/siemens/index.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/siemens/index.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -0,0 +1,9 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++Siemens ++======= ++ ++.. toctree:: ++ :maxdepth: 2 ++ ++ iot2050 +diff -ruN u-boot-2021.10/doc/board/siemens/iot2050.rst u-boot/doc/board/siemens/iot2050.rst +--- u-boot-2021.10/doc/board/siemens/iot2050.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/siemens/iot2050.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -0,0 +1,78 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++.. sectionauthor:: Jan Kiszka ++ ++SIMATIC IOT2050 BASIC and ADVANCED ++================================== ++ ++The SIMATIC IOT2050 is an open industrial IoT gateway that is using the TI ++AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced ++variant is prepared for secure boot. ++ ++The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader ++called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and ++OP-TEE, before booting U-Boot on the A53 cores. This describes how to build all ++open artifacts into a flashable image for the OSPI flash. The flash image will ++work on both variants. ++ ++Dependencies ++------------ ++ ++ATF: Upstream release 2.4 or newer ++OP-TEE: Upstream release 3.10.0 or newer ++ ++Binary dependencies can be found in ++https://github.com/siemens/meta-iot2050/tree/master/recipes-bsp/u-boot/files/prebuild. ++The following binaries from that source need to be present in the build folder: ++ ++ - tiboot3.bin ++ - sysfw.itb ++ - sysfw.itb_HS ++ - sysfw_sr2.itb ++ - sysfw_sr2.itb_HS ++ ++Building ++-------- ++ ++Make sure that CROSS_COMPILE is set appropriately: ++ ++.. code-block:: text ++ ++ $ export CROSS_COMPILE=aarch64-linux-gnu- ++ ++ATF: ++ ++.. code-block:: text ++ ++ $ make PLAT=k3 SPD=opteed K3_USART=1 ++ ++OP-TEE: ++ ++.. code-block:: text ++ ++ $ make PLATFORM=k3-am65x CFG_ARM64_core=y CFG_TEE_CORE_LOG_LEVEL=2 CFG_CONSOLE_UART=1 ++ ++U-Boot: ++ ++.. code-block:: text ++ ++ $ export ATF=/path/to/bl31.bin ++ $ export TEE=/path/to/tee-pager_v2.bin ++ $ make iot2050_defconfig ++ $ make ++ ++Flashing ++-------- ++ ++Via U-Boot: ++ ++.. code-block:: text ++ ++ IOT2050> sf probe ++ IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin ++ IOT2050> sf update $loadaddr 0x0 $filesize ++ ++Via external programmer Dediprog SF100 or SF600: ++ ++.. code-block:: text ++ ++ $ dpcmd --vcc 2 -v -u flash.bin +diff -ruN u-boot-2021.10/doc/board/ste/index.rst u-boot/doc/board/ste/index.rst +--- u-boot-2021.10/doc/board/ste/index.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/ste/index.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -0,0 +1,9 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++ST-Ericsson ++=========== ++ ++.. toctree:: ++ :maxdepth: 2 ++ ++ stemmy +diff -ruN u-boot-2021.10/doc/board/ste/stemmy.rst u-boot/doc/board/ste/stemmy.rst +--- u-boot-2021.10/doc/board/ste/stemmy.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/ste/stemmy.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -0,0 +1,81 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++.. sectionauthor:: Stephan Gerhold ++ ++ST-Ericsson U8500 Samsung "stemmy" board ++======================================== ++ ++The "stemmy" board supports Samsung smartphones released with ++the ST-Ericsson NovaThor U8500 SoC, e.g. ++ ++ +---------------------------+----------+--------------+----------------+ ++ | Device | Model | Codename | U-Boot | ++ +===========================+==========+==============+================+ ++ | Samsung Galaxy Ace 2 | GT-I8160 | codina | ``u-boot.bin`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy Amp | SGH-I407 | kyle | ``u-boot.img`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy Beam | GT-I8530 | gavini | ``u-boot.bin`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy Exhibit | SGH-T599 | codina (TMO) | ``u-boot.bin`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy S Advance | GT-I9070 | janice | ``u-boot.bin`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy S III mini | GT-I8190 | golden | ``u-boot.img`` | ++ +---------------------------+----------+--------------+----------------+ ++ | Samsung Galaxy Xcover 2 | GT-S7710 | skomer | ``u-boot.img`` | ++ +---------------------------+----------+--------------+----------------+ ++ ++At the moment, U-Boot is intended to be chain-loaded from ++the original Samsung bootloader, not replacing it entirely. ++ ++Installation ++------------ ++First, setup ``CROSS_COMPILE`` for ARMv7. Then, build U-Boot for ``stemmy``:: ++ ++ $ export CROSS_COMPILE=arm-none-eabi- ++ $ make stemmy_defconfig ++ $ make ++ ++This will build ``u-boot.bin`` in the configured output directory. ++ ++For newer devices (check ``u-boot.img`` in the table above), the U-Boot binary ++has to be packed into an Android boot image. Devices with ``u-boot.bin`` boot ++the raw U-Boot binary from the boot partition. You can build the Android boot ++image with ``mkbootimg``, e.g. from from android-7.1.2_r37_:: ++ ++ $ mkbootimg \ ++ --kernel=u-boot.bin \ ++ --base=0x00000000 \ ++ --kernel_offset=0x00100000 \ ++ --ramdisk_offset=0x02000000 \ ++ --tags_offset=0x00000100 \ ++ --output=u-boot.img ++ ++.. _android-7.1.2_r37: https://android.googlesource.com/platform/system/core/+/refs/tags/android-7.1.2_r37/mkbootimg/mkbootimg ++ ++To flash the U-Boot binary, enter the Samsung download mode ++(press Power + Home + Volume Down). Use Heimdall_ to flash the U-Boot image to ++the Android boot partition:: ++ ++ $ heimdall flash --Kernel u-boot.(bin|img) ++ ++If this is not working but there are messages like ``Android recovery image`` in ++the UART console, you can try flashing to the recovery partition instead:: ++ ++ $ heimdall flash --Kernel2 u-boot.(bin|img) ++ ++.. _Heimdall: https://gitlab.com/BenjaminDobell/Heimdall ++ ++After a reboot the U-Boot prompt should appear via UART. Unless interrupted it ++automatically boots to USB Fastboot mode where Android boot images can be booted ++via ``fastboot boot boot.img``. It is mainly intended to boot mainline Linux, ++but booting original Samsung Android boot images is also supported (e.g. for ++charging). ++ ++UART ++---- ++UART is available through the micro USB port, similar to the Carkit standard. ++With a ~619kOhm resistor between ID and GND, 1.8V RX/TX is available at D+/D-. ++ ++.. note:: ++ Make sure to connect the UART cable **before** turning on the phone. +diff -ruN u-boot-2021.10/doc/board/ti/am335x_evm.rst u-boot/doc/board/ti/am335x_evm.rst +--- u-boot-2021.10/doc/board/ti/am335x_evm.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/board/ti/am335x_evm.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -0,0 +1,200 @@ ++.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++.. sectionauthor:: Tom Rini ++ ++Summary ++======= ++ ++This document covers various features of the `am335x_evm` default ++configuration, some of the related defconfigs, and how to enable hardware ++features not present by default in the defconfigs. ++ ++Hardware ++-------- ++ ++The binary produced by this board supports, based on parsing of the EEPROM ++documented in TI's reference designs: ++* AM335x GP EVM ++* AM335x EVM SK ++* The Beaglebone family of designs ++ ++Customization ++------------- ++ ++Given that all of the above boards are reference platforms (and the ++Beaglebone platforms are OSHA), it is likely that this platform code and ++configuration will be used as the basis of a custom platform. It is ++worth noting that aside from things such as NAND or MMC only being ++required if a custom platform makes use of these blocks, the following ++are required, depending on design: ++ ++* GPIO is only required if DDR3 power is controlled in a way similar to EVM SK ++* SPI is only required for SPI flash, or exposing the SPI bus. ++ ++The following blocks are required: ++ ++* I2C, to talk with the PMIC and ensure that we do not run afoul of ++ errata 1.0.24. ++ ++When removing options as part of customization, note that you will likely need ++to look at both `include/configs/am335x_evm.h`, ++`include/configs/ti_am335x_common.h` and `include/configs/am335x_evm.h` as the ++migration to Kconfig is not yet complete. ++ ++NAND ++---- ++ ++The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In ++this example to program the NAND we assume that an SD card has been ++inserted with the files to write in the first SD slot and that mtdparts ++have been configured correctly for the board. All images are first loaded ++into memory, then written to NAND. ++ ++Step-1: Building u-boot for NAND boot ++ Set following CONFIGxx options for NAND device. ++ CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page ++ CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page ++ CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block ++ CONFIG_SYS_NAND_ECCPOS ECC map for NAND page ++ CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) ++ ++Step-2: Flashing NAND via MMC/SD ++ ++.. code-block:: text ++ ++ # select BOOTSEL to MMC/SD boot and boot from MMC/SD card ++ U-Boot # mmc rescan ++ # erase flash ++ U-Boot # nand erase.chip ++ U-Boot # env default -f -a ++ U-Boot # saveenv ++ # flash MLO. Redundant copies of MLO are kept for failsafe ++ U-Boot # load mmc 0 0x82000000 MLO ++ U-Boot # nand write 0x82000000 0x00000 0x20000 ++ U-Boot # nand write 0x82000000 0x20000 0x20000 ++ U-Boot # nand write 0x82000000 0x40000 0x20000 ++ U-Boot # nand write 0x82000000 0x60000 0x20000 ++ # flash u-boot.img ++ U-Boot # load mmc 0 0x82000000 u-boot.img ++ U-Boot # nand write 0x82000000 0x80000 0x60000 ++ # flash kernel image ++ U-Boot # load mmc 0 0x82000000 uImage ++ U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} ++ # flash filesystem image ++ U-Boot # load mmc 0 0x82000000 filesystem.img ++ U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 ++ ++Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. ++ The device should boot from images flashed on NAND device. ++ ++ ++Falcon Mode ++----------- ++ ++The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, ++eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is ++to read a 'c' on the console while in SPL at any point prior to loading the ++OS payload (so as soon as possible) to opt to booting full U-Boot. Also ++note that while one can program Falcon Mode "in place" great care needs to ++be taken by the user to not 'brick' their setup. As these are all eval ++boards with multiple boot methods, recovery should not be an issue in this ++worst-case however. ++ ++Falcon Mode: eMMC ++----------------- ++ ++The recommended layout in this case is: ++ ++.. code-block:: text ++ ++ MMC BLOCKS |--------------------------------| LOCATION IN BYTES ++ 0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 ++ 0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 ++ 0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 ++ 0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 ++ 0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 ++ 0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 ++ 0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 ++ ++Note that when we run 'spl export' it will prepare to boot the kernel. ++This includes relocation of the uImage from where we loaded it to the entry ++point defined in the header. As these locations overlap by default, it ++would leave us with an image that if written to MMC will not boot, so ++instead of using the loadaddr variable we use 0x81000000 in the following ++example. In this example we are loading from the network, for simplicity, ++and assume a valid partition table already exists and 'mmc dev' has already ++been run to select the correct device. Also note that if you previously ++had a FAT partition (such as on a Beaglebone Black) it is not enough to ++write garbage into the area, you must delete it from the partition table ++first. ++ ++.. code-block:: text ++ ++ # Ensure we are able to talk with this mmc device ++ U-Boot # mmc rescan ++ U-Boot # tftp 81000000 am335x/MLO ++ # Write to two of the backup locations ROM uses ++ U-Boot # mmc write 81000000 100 100 ++ U-Boot # mmc write 81000000 200 100 ++ # Write U-Boot to the location set in the config ++ U-Boot # tftp 81000000 am335x/u-boot.img ++ U-Boot # mmc write 81000000 300 400 ++ # Load kernel and device tree into memory, perform export ++ U-Boot # tftp 81000000 am335x/uImage ++ U-Boot # run findfdt ++ U-Boot # tftp ${fdtaddr} am335x/${fdtfile} ++ U-Boot # run mmcargs ++ U-Boot # spl export fdt 81000000 - ${fdtaddr} ++ # Write the updated device tree to MMC ++ U-Boot # mmc write ${fdtaddr} 80 80 ++ # Write the uImage to MMC ++ U-Boot # mmc write 81000000 900 2000 ++ ++Falcon Mode: FAT SD cards ++------------------------- ++ ++In this case the additional file is written to the filesystem. In this ++example we assume that the uImage and device tree to be used are already on ++the FAT filesystem (only the uImage MUST be for this to function ++afterwards) along with a Falcon Mode aware MLO and the FAT partition has ++already been created and marked bootable: ++ ++.. code-block:: text ++ ++ U-Boot # mmc rescan ++ # Load kernel and device tree into memory, perform export ++ U-Boot # load mmc 0:1 ${loadaddr} uImage ++ U-Boot # run findfdt ++ U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} ++ U-Boot # run mmcargs ++ U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} ++ ++This will print a number of lines and then end with something like: ++ ++.. code-block:: text ++ ++ Using Device Tree in place at 80f80000, end 80f85928 ++ Using Device Tree in place at 80f80000, end 80f88928 ++ ++So then you: ++ ++.. code-block:: text ++ ++ U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 ++ ++Falcon Mode: NAND ++----------------- ++ ++In this case the additional data is written to another partition of the ++NAND. In this example we assume that the uImage and device tree to be are ++already located on the NAND somewhere (such as filesystem or mtd partition) ++along with a Falcon Mode aware MLO written to the correct locations for ++booting and mtdparts have been configured correctly for the board: ++ ++.. code-block:: text ++ ++ U-Boot # nand read ${loadaddr} kernel ++ U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb ++ U-Boot # run nandargs ++ U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} ++ U-Boot # nand erase.part u-boot-spl-os ++ U-Boot # nand write ${fdtaddr} u-boot-spl-os +diff -ruN u-boot-2021.10/doc/board/ti/index.rst u-boot/doc/board/ti/index.rst +--- u-boot-2021.10/doc/board/ti/index.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/board/ti/index.rst 2021-11-01 17:10:14.219594856 +0100 +@@ -6,4 +6,5 @@ + .. toctree:: + :maxdepth: 2 + ++ am335x_evm + j721e_evm +diff -ruN u-boot-2021.10/doc/develop/checkpatch.rst u-boot/doc/develop/checkpatch.rst +--- u-boot-2021.10/doc/develop/checkpatch.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/develop/checkpatch.rst 2021-11-01 17:10:14.222928007 +0100 +@@ -0,0 +1,755 @@ ++.. SPDX-License-Identifier: GPL-2.0-only ++ ++========== ++Checkpatch ++========== ++ ++Checkpatch (scripts/checkpatch.pl) is a perl script which checks for trivial ++style violations in patches and optionally corrects them. Checkpatch can ++also be run on file contexts and without the kernel tree. ++ ++Checkpatch is not always right. Your judgement takes precedence over checkpatch ++messages. If your code looks better with the violations, then its probably ++best left alone. ++ ++ ++Options ++======= ++ ++This section will describe the options checkpatch can be run with. ++ ++Usage:: ++ ++ ./scripts/checkpatch.pl [OPTION]... [FILE]... ++ ++Available options: ++ ++ - -q, --quiet ++ ++ Enable quiet mode. ++ ++ - -v, --verbose ++ Enable verbose mode. Additional verbose test descriptions are output ++ so as to provide information on why that particular message is shown. ++ ++ - --no-tree ++ ++ Run checkpatch without the kernel tree. ++ ++ - --no-signoff ++ ++ Disable the 'Signed-off-by' line check. The sign-off is a simple line at ++ the end of the explanation for the patch, which certifies that you wrote it ++ or otherwise have the right to pass it on as an open-source patch. ++ ++ Example:: ++ ++ Signed-off-by: Random J Developer ++ ++ Setting this flag effectively stops a message for a missing signed-off-by ++ line in a patch context. ++ ++ - --patch ++ ++ Treat FILE as a patch. This is the default option and need not be ++ explicitly specified. ++ ++ - --emacs ++ ++ Set output to emacs compile window format. This allows emacs users to jump ++ from the error in the compile window directly to the offending line in the ++ patch. ++ ++ - --terse ++ ++ Output only one line per report. ++ ++ - --showfile ++ ++ Show the diffed file position instead of the input file position. ++ ++ - -g, --git ++ ++ Treat FILE as a single commit or a git revision range. ++ ++ Single commit with: ++ ++ - ++ - ^ ++ - ~n ++ ++ Multiple commits with: ++ ++ - .. ++ - ... ++ - - ++ ++ - -f, --file ++ ++ Treat FILE as a regular source file. This option must be used when running ++ checkpatch on source files in the kernel. ++ ++ - --subjective, --strict ++ ++ Enable stricter tests in checkpatch. By default the tests emitted as CHECK ++ do not activate by default. Use this flag to activate the CHECK tests. ++ ++ - --list-types ++ ++ Every message emitted by checkpatch has an associated TYPE. Add this flag ++ to display all the types in checkpatch. ++ ++ Note that when this flag is active, checkpatch does not read the input FILE, ++ and no message is emitted. Only a list of types in checkpatch is output. ++ ++ - --types TYPE(,TYPE2...) ++ ++ Only display messages with the given types. ++ ++ Example:: ++ ++ ./scripts/checkpatch.pl mypatch.patch --types EMAIL_SUBJECT,BRACES ++ ++ - --ignore TYPE(,TYPE2...) ++ ++ Checkpatch will not emit messages for the specified types. ++ ++ Example:: ++ ++ ./scripts/checkpatch.pl mypatch.patch --ignore EMAIL_SUBJECT,BRACES ++ ++ - --show-types ++ ++ By default checkpatch doesn't display the type associated with the messages. ++ Set this flag to show the message type in the output. ++ ++ - --max-line-length=n ++ ++ Set the max line length (default 100). If a line exceeds the specified ++ length, a LONG_LINE message is emitted. ++ ++ ++ The message level is different for patch and file contexts. For patches, ++ a WARNING is emitted. While a milder CHECK is emitted for files. So for ++ file contexts, the --strict flag must also be enabled. ++ ++ - --min-conf-desc-length=n ++ ++ Set the Kconfig entry minimum description length, if shorter, warn. ++ ++ - --tab-size=n ++ ++ Set the number of spaces for tab (default 8). ++ ++ - --root=PATH ++ ++ PATH to the kernel tree root. ++ ++ This option must be specified when invoking checkpatch from outside ++ the kernel root. ++ ++ - --no-summary ++ ++ Suppress the per file summary. ++ ++ - --mailback ++ ++ Only produce a report in case of Warnings or Errors. Milder Checks are ++ excluded from this. ++ ++ - --summary-file ++ ++ Include the filename in summary. ++ ++ - --debug KEY=[0|1] ++ ++ Turn on/off debugging of KEY, where KEY is one of 'values', 'possible', ++ 'type', and 'attr' (default is all off). ++ ++ - --fix ++ ++ This is an EXPERIMENTAL feature. If correctable errors exists, a file ++ .EXPERIMENTAL-checkpatch-fixes is created which has the ++ automatically fixable errors corrected. ++ ++ - --fix-inplace ++ ++ EXPERIMENTAL - Similar to --fix but input file is overwritten with fixes. ++ ++ DO NOT USE this flag unless you are absolutely sure and you have a backup ++ in place. ++ ++ - --ignore-perl-version ++ ++ Override checking of perl version. Runtime errors maybe encountered after ++ enabling this flag if the perl version does not meet the minimum specified. ++ ++ - --codespell ++ ++ Use the codespell dictionary for checking spelling errors. ++ ++ - --codespellfile ++ ++ Use the specified codespell file. ++ Default is '/usr/share/codespell/dictionary.txt'. ++ ++ - --typedefsfile ++ ++ Read additional types from this file. ++ ++ - --color[=WHEN] ++ ++ Use colors 'always', 'never', or only when output is a terminal ('auto'). ++ Default is 'auto'. ++ ++ - --kconfig-prefix=WORD ++ ++ Use WORD as a prefix for Kconfig symbols (default is `CONFIG_`). ++ ++ - -h, --help, --version ++ ++ Display the help text. ++ ++Message Levels ++============== ++ ++Messages in checkpatch are divided into three levels. The levels of messages ++in checkpatch denote the severity of the error. They are: ++ ++ - ERROR ++ ++ This is the most strict level. Messages of type ERROR must be taken ++ seriously as they denote things that are very likely to be wrong. ++ ++ - WARNING ++ ++ This is the next stricter level. Messages of type WARNING requires a ++ more careful review. But it is milder than an ERROR. ++ ++ - CHECK ++ ++ This is the mildest level. These are things which may require some thought. ++ ++Type Descriptions ++================= ++ ++This section contains a description of all the message types in checkpatch. ++ ++.. Types in this section are also parsed by checkpatch. ++.. The types are grouped into subsections based on use. ++ ++ ++Allocation style ++---------------- ++ ++ **ALLOC_ARRAY_ARGS** ++ The first argument for kcalloc or kmalloc_array should be the ++ number of elements. sizeof() as the first argument is generally ++ wrong. ++ See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html ++ ++ **ALLOC_SIZEOF_STRUCT** ++ The allocation style is bad. In general for family of ++ allocation functions using sizeof() to get memory size, ++ constructs like:: ++ ++ p = alloc(sizeof(struct foo), ...) ++ ++ should be:: ++ ++ p = alloc(sizeof(*p), ...) ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#allocating-memory ++ ++ **ALLOC_WITH_MULTIPLY** ++ Prefer kmalloc_array/kcalloc over kmalloc/kzalloc with a ++ sizeof multiply. ++ See: https://www.kernel.org/doc/html/latest/core-api/memory-allocation.html ++ ++ ++API usage ++--------- ++ ++ **ARCH_DEFINES** ++ Architecture specific defines should be avoided wherever ++ possible. ++ ++ **ARCH_INCLUDE_LINUX** ++ Whenever asm/file.h is included and linux/file.h exists, a ++ conversion can be made when linux/file.h includes asm/file.h. ++ However this is not always the case (See signal.h). ++ This message type is emitted only for includes from arch/. ++ ++ **AVOID_BUG** ++ BUG() or BUG_ON() should be avoided totally. ++ Use WARN() and WARN_ON() instead, and handle the "impossible" ++ error condition as gracefully as possible. ++ See: https://www.kernel.org/doc/html/latest/process/deprecated.html#bug-and-bug-on ++ ++ **CONSIDER_KSTRTO** ++ The simple_strtol(), simple_strtoll(), simple_strtoul(), and ++ simple_strtoull() functions explicitly ignore overflows, which ++ may lead to unexpected results in callers. The respective kstrtol(), ++ kstrtoll(), kstrtoul(), and kstrtoull() functions tend to be the ++ correct replacements. ++ See: https://www.kernel.org/doc/html/latest/process/deprecated.html#simple-strtol-simple-strtoll-simple-strtoul-simple-strtoull ++ ++ **LOCKDEP** ++ The lockdep_no_validate class was added as a temporary measure to ++ prevent warnings on conversion of device->sem to device->mutex. ++ It should not be used for any other purpose. ++ See: https://lore.kernel.org/lkml/1268959062.9440.467.camel@laptop/ ++ ++ **MALFORMED_INCLUDE** ++ The #include statement has a malformed path. This has happened ++ because the author has included a double slash "//" in the pathname ++ accidentally. ++ ++ **USE_LOCKDEP** ++ lockdep_assert_held() annotations should be preferred over ++ assertions based on spin_is_locked() ++ See: https://www.kernel.org/doc/html/latest/locking/lockdep-design.html#annotations ++ ++ **UAPI_INCLUDE** ++ No #include statements in include/uapi should use a uapi/ path. ++ ++ ++Comment style ++------------- ++ ++ **BLOCK_COMMENT_STYLE** ++ The comment style is incorrect. The preferred style for multi- ++ line comments is:: ++ ++ /* ++ * This is the preferred style ++ * for multi line comments. ++ */ ++ ++ The networking comment style is a bit different, with the first line ++ not empty like the former:: ++ ++ /* This is the preferred comment style ++ * for files in net/ and drivers/net/ ++ */ ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting ++ ++ **C99_COMMENTS** ++ C99 style single line comments (//) should not be used. ++ Prefer the block comment style instead. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#commenting ++ ++ ++Commit message ++-------------- ++ ++ **BAD_SIGN_OFF** ++ The signed-off-by line does not fall in line with the standards ++ specified by the community. ++ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1 ++ ++ **BAD_STABLE_ADDRESS_STYLE** ++ The email format for stable is incorrect. ++ Some valid options for stable address are:: ++ ++ 1. stable@vger.kernel.org ++ 2. stable@kernel.org ++ ++ For adding version info, the following comment style should be used:: ++ ++ stable@vger.kernel.org # version info ++ ++ **COMMIT_COMMENT_SYMBOL** ++ Commit log lines starting with a '#' are ignored by git as ++ comments. To solve this problem addition of a single space ++ infront of the log line is enough. ++ ++ **COMMIT_MESSAGE** ++ The patch is missing a commit description. A brief ++ description of the changes made by the patch should be added. ++ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes ++ ++ **MISSING_SIGN_OFF** ++ The patch is missing a Signed-off-by line. A signed-off-by ++ line should be added according to Developer's certificate of ++ Origin. ++ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin ++ ++ **NO_AUTHOR_SIGN_OFF** ++ The author of the patch has not signed off the patch. It is ++ required that a simple sign off line should be present at the ++ end of explanation of the patch to denote that the author has ++ written it or otherwise has the rights to pass it on as an open ++ source patch. ++ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin ++ ++ **DIFF_IN_COMMIT_MSG** ++ Avoid having diff content in commit message. ++ This causes problems when one tries to apply a file containing both ++ the changelog and the diff because patch(1) tries to apply the diff ++ which it found in the changelog. ++ See: https://lore.kernel.org/lkml/20150611134006.9df79a893e3636019ad2759e@linux-foundation.org/ ++ ++ **GERRIT_CHANGE_ID** ++ To be picked up by gerrit, the footer of the commit message might ++ have a Change-Id like:: ++ ++ Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b ++ Signed-off-by: A. U. Thor ++ ++ The Change-Id line must be removed before submitting. ++ ++ **GIT_COMMIT_ID** ++ The proper way to reference a commit id is: ++ commit <12+ chars of sha1> ("") ++ ++ An example may be:: ++ ++ Commit e21d2170f36602ae2708 ("video: remove unnecessary ++ platform_set_drvdata()") removed the unnecessary ++ platform_set_drvdata(), but left the variable "dev" unused, ++ delete it. ++ ++ See: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes ++ ++ ++Comparison style ++---------------- ++ ++ **ASSIGN_IN_IF** ++ Do not use assignments in if condition. ++ Example:: ++ ++ if ((foo = bar(...)) < BAZ) { ++ ++ should be written as:: ++ ++ foo = bar(...); ++ if (foo < BAZ) { ++ ++ **BOOL_COMPARISON** ++ Comparisons of A to true and false are better written ++ as A and !A. ++ See: https://lore.kernel.org/lkml/1365563834.27174.12.camel@joe-AO722/ ++ ++ **COMPARISON_TO_NULL** ++ Comparisons to NULL in the form (foo == NULL) or (foo != NULL) ++ are better written as (!foo) and (foo). ++ ++ **CONSTANT_COMPARISON** ++ Comparisons with a constant or upper case identifier on the left ++ side of the test should be avoided. ++ ++ ++Macros, Attributes and Symbols ++------------------------------ ++ ++ **ARRAY_SIZE** ++ The ARRAY_SIZE(foo) macro should be preferred over ++ sizeof(foo)/sizeof(foo[0]) for finding number of elements in an ++ array. ++ ++ The macro is defined in include/linux/kernel.h:: ++ ++ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++ ++ **AVOID_EXTERNS** ++ Function prototypes don't need to be declared extern in .h ++ files. It's assumed by the compiler and is unnecessary. ++ ++ **AVOID_L_PREFIX** ++ Local symbol names that are prefixed with `.L` should be avoided, ++ as this has special meaning for the assembler; a symbol entry will ++ not be emitted into the symbol table. This can prevent `objtool` ++ from generating correct unwind info. ++ ++ Symbols with STB_LOCAL binding may still be used, and `.L` prefixed ++ local symbol names are still generally usable within a function, ++ but `.L` prefixed local symbol names should not be used to denote ++ the beginning or end of code regions via ++ `SYM_CODE_START_LOCAL`/`SYM_CODE_END` ++ ++ **BIT_MACRO** ++ Defines like: 1 << <digit> could be BIT(digit). ++ The BIT() macro is defined in include/linux/bitops.h:: ++ ++ #define BIT(nr) (1UL << (nr)) ++ ++ **CONST_READ_MOSTLY** ++ When a variable is tagged with the __read_mostly annotation, it is a ++ signal to the compiler that accesses to the variable will be mostly ++ reads and rarely(but NOT never) a write. ++ ++ const __read_mostly does not make any sense as const data is already ++ read-only. The __read_mostly annotation thus should be removed. ++ ++ **DATE_TIME** ++ It is generally desirable that building the same source code with ++ the same set of tools is reproducible, i.e. the output is always ++ exactly the same. ++ ++ The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros, ++ and enables warnings if they are used as they can lead to ++ non-deterministic builds. ++ See: https://www.kernel.org/doc/html/latest/kbuild/reproducible-builds.html#timestamps ++ ++ **DEFINE_ARCH_HAS** ++ The ARCH_HAS_xyz and ARCH_HAVE_xyz patterns are wrong. ++ ++ For big conceptual features use Kconfig symbols instead. And for ++ smaller things where we have compatibility fallback functions but ++ want architectures able to override them with optimized ones, we ++ should either use weak functions (appropriate for some cases), or ++ the symbol that protects them should be the same symbol we use. ++ See: https://lore.kernel.org/lkml/CA+55aFycQ9XJvEOsiM3txHL5bjUc8CeKWJNR_H+MiicaddB42Q@mail.gmail.com/ ++ ++ **INIT_ATTRIBUTE** ++ Const init definitions should use __initconst instead of ++ __initdata. ++ ++ Similarly init definitions without const require a separate ++ use of const. ++ ++ **INLINE_LOCATION** ++ The inline keyword should sit between storage class and type. ++ ++ For example, the following segment:: ++ ++ inline static int example_function(void) ++ { ++ ... ++ } ++ ++ should be:: ++ ++ static inline int example_function(void) ++ { ++ ... ++ } ++ ++ **MULTISTATEMENT_MACRO_USE_DO_WHILE** ++ Macros with multiple statements should be enclosed in a ++ do - while block. Same should also be the case for macros ++ starting with `if` to avoid logic defects:: ++ ++ #define macrofun(a, b, c) \ ++ do { \ ++ if (a == 5) \ ++ do_this(b, c); \ ++ } while (0) ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#macros-enums-and-rtl ++ ++ **WEAK_DECLARATION** ++ Using weak declarations like __attribute__((weak)) or __weak ++ can have unintended link defects. Avoid using them. ++ ++ ++Functions and Variables ++----------------------- ++ ++ **CAMELCASE** ++ Avoid CamelCase Identifiers. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#naming ++ ++ **FUNCTION_WITHOUT_ARGS** ++ Function declarations without arguments like:: ++ ++ int foo() ++ ++ should be:: ++ ++ int foo(void) ++ ++ **GLOBAL_INITIALISERS** ++ Global variables should not be initialized explicitly to ++ 0 (or NULL, false, etc.). Your compiler (or rather your ++ loader, which is responsible for zeroing out the relevant ++ sections) automatically does it for you. ++ ++ **INITIALISED_STATIC** ++ Static variables should not be initialized explicitly to zero. ++ Your compiler (or rather your loader) automatically does ++ it for you. ++ ++ **RETURN_PARENTHESES** ++ return is not a function and as such doesn't need parentheses:: ++ ++ return (bar); ++ ++ can simply be:: ++ ++ return bar; ++ ++ ++Spacing and Brackets ++-------------------- ++ ++ **ASSIGNMENT_CONTINUATIONS** ++ Assignment operators should not be written at the start of a ++ line but should follow the operand at the previous line. ++ ++ **BRACES** ++ The placement of braces is stylistically incorrect. ++ The preferred way is to put the opening brace last on the line, ++ and put the closing brace first:: ++ ++ if (x is true) { ++ we do y ++ } ++ ++ This applies for all non-functional blocks. ++ However, there is one special case, namely functions: they have the ++ opening brace at the beginning of the next line, thus:: ++ ++ int function(int x) ++ { ++ body of function ++ } ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces ++ ++ **BRACKET_SPACE** ++ Whitespace before opening bracket '[' is prohibited. ++ There are some exceptions: ++ ++ 1. With a type on the left:: ++ ++ ;int [] a; ++ ++ 2. At the beginning of a line for slice initialisers:: ++ ++ [0...10] = 5, ++ ++ 3. Inside a curly brace:: ++ ++ = { [0...10] = 5 } ++ ++ **CODE_INDENT** ++ Code indent should use tabs instead of spaces. ++ Outside of comments, documentation and Kconfig, ++ spaces are never used for indentation. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation ++ ++ **CONCATENATED_STRING** ++ Concatenated elements should have a space in between. ++ Example:: ++ ++ printk(KERN_INFO"bar"); ++ ++ should be:: ++ ++ printk(KERN_INFO "bar"); ++ ++ **ELSE_AFTER_BRACE** ++ `else {` should follow the closing block `}` on the same line. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces ++ ++ **LINE_SPACING** ++ Vertical space is wasted given the limited number of lines an ++ editor window can display when multiple blank lines are used. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces ++ ++ **OPEN_BRACE** ++ The opening brace should be following the function definitions on the ++ next line. For any non-functional block it should be on the same line ++ as the last construct. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces ++ ++ **POINTER_LOCATION** ++ When using pointer data or a function that returns a pointer type, ++ the preferred use of * is adjacent to the data name or function name ++ and not adjacent to the type name. ++ Examples:: ++ ++ char *linux_banner; ++ unsigned long long memparse(char *ptr, char **retptr); ++ char *match_strdup(substring_t *s); ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces ++ ++ **SPACING** ++ Whitespace style used in the kernel sources is described in kernel docs. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces ++ ++ **SWITCH_CASE_INDENT_LEVEL** ++ switch should be at the same indent as case. ++ Example:: ++ ++ switch (suffix) { ++ case 'G': ++ case 'g': ++ mem <<= 30; ++ break; ++ case 'M': ++ case 'm': ++ mem <<= 20; ++ break; ++ case 'K': ++ case 'k': ++ mem <<= 10; ++ /* fall through */ ++ default: ++ break; ++ } ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#indentation ++ ++ **TRAILING_WHITESPACE** ++ Trailing whitespace should always be removed. ++ Some editors highlight the trailing whitespace and cause visual ++ distractions when editing files. ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#spaces ++ ++ **WHILE_AFTER_BRACE** ++ while should follow the closing bracket on the same line:: ++ ++ do { ++ ... ++ } while(something); ++ ++ See: https://www.kernel.org/doc/html/latest/process/coding-style.html#placing-braces-and-spaces ++ ++ ++Others ++------ ++ ++ **CONFIG_DESCRIPTION** ++ Kconfig symbols should have a help text which fully describes ++ it. ++ ++ **CORRUPTED_PATCH** ++ The patch seems to be corrupted or lines are wrapped. ++ Please regenerate the patch file before sending it to the maintainer. ++ ++ **DOS_LINE_ENDINGS** ++ For DOS-formatted patches, there are extra ^M symbols at the end of ++ the line. These should be removed. ++ ++ **EXECUTE_PERMISSIONS** ++ There is no reason for source files to be executable. The executable ++ bit can be removed safely. ++ ++ **NON_OCTAL_PERMISSIONS** ++ Permission bits should use 4 digit octal permissions (like 0700 or 0444). ++ Avoid using any other base like decimal. ++ ++ **NOT_UNIFIED_DIFF** ++ The patch file does not appear to be in unified-diff format. Please ++ regenerate the patch file before sending it to the maintainer. ++ ++ **PRINTF_0XDECIMAL** ++ Prefixing 0x with decimal output is defective and should be corrected. ++ ++ **TRAILING_STATEMENTS** ++ Trailing statements (for example after any conditional) should be ++ on the next line. ++ Like:: ++ ++ if (x == y) break; ++ ++ should be:: ++ ++ if (x == y) ++ break; +diff -ruN u-boot-2021.10/doc/develop/driver-model/of-plat.rst u-boot/doc/develop/driver-model/of-plat.rst +--- u-boot-2021.10/doc/develop/driver-model/of-plat.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/develop/driver-model/of-plat.rst 2021-11-01 17:10:14.222928007 +0100 +@@ -215,16 +215,16 @@ + + static int mmc_of_to_plat(struct udevice *dev) + { +- #if !CONFIG_IS_ENABLED(OF_PLATDATA) ++ if (CONFIG_IS_ENABLED(OF_REAL)) { + /* Decode the devicetree data */ + struct mmc_plat *plat = dev_get_plat(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + + plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); +- #endif ++ } + +- return 0; ++ return 0; + } + + static int mmc_probe(struct udevice *dev) +@@ -600,6 +600,11 @@ + Problems + -------- + ++This section shows some common problems and how to fix them. ++ ++Driver not found ++~~~~~~~~~~~~~~~~ ++ + In some cases you will you see something like this:: + + WARNING: the driver rockchip_rk3188_grf was not found in the driver list +@@ -633,8 +638,11 @@ + then dtoc looks at the first compatible string ("rockchip,rk3188-grf"), + converts that to a C identifier (rockchip_rk3188_grf) and then looks for that. + ++Missing .compatible or Missing .id ++~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ + Various things can cause dtoc to fail to find the driver and it tries to +-warn about these. For example: ++warn about these. For example:: + + rockchip_rk3188_uart: Missing .compatible in drivers/serial/serial_rockchip.c + : WARNING: the driver rockchip_rk3188_uart was not found in the driver list +@@ -649,6 +657,130 @@ + member and a .id member. The first provides the array of compatible strings and + the second provides the uclass ID. + ++Missing parent ++~~~~~~~~~~~~~~ ++ ++When a device is used, its parent must be present as well. If you see an error ++like:: ++ ++ Node '/i2c@0/emul/emul0' requires parent node '/i2c@0/emul' but it is not in ++ the valid list ++ ++it indicates that you are using a node whose parent is not present in the ++devicetree. In this example, if you look at the device tree output ++(e.g. fdtdump tpl/u-boot-tpl.dtb in your build directory), you may see something ++like this:: ++ ++ emul { ++ emul0 { ++ compatible = "sandbox,i2c-rtc-emul"; ++ #emul-cells = <0x00000000>; ++ phandle = <0x00000003>; ++ }; ++ }; ++ ++In this example, 'emul0' exists but its parent 'emul' has no properties. These ++have been dropped by fdtgrep in an effort to reduce the devicetree size. This ++indicates that the two nodes have different phase settings. Looking at the ++source .dts:: ++ ++ i2c_emul: emul { ++ u-boot,dm-spl; ++ reg = <0xff>; ++ compatible = "sandbox,i2c-emul-parent"; ++ emul0: emul0 { ++ u-boot,dm-pre-reloc; ++ compatible = "sandbox,i2c-rtc-emul"; ++ #emul-cells = <0>; ++ }; ++ }; ++ ++you can see that the child node 'emul0' usees 'u-boot,dm-pre-reloc', indicating ++that the node is present in all SPL builds, but its parent uses 'u-boot,dm-spl' ++indicating it is only present in SPL, not TPL. For a TPL build, this will fail ++with the above message. The fix is to change 'emul0' to use the same ++'u-boot,dm-spl' condition, so that it is not present in TPL, like its parent. ++ ++Link errors / undefined reference ++~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++Sometimes dtoc does not find the problem for you, but something is wrong and ++you get a link error, e.g.:: ++ ++ :(.u_boot_list_2_udevice_2_spl_test5+0x0): undefined reference to ++ `_u_boot_list_2_driver_2_sandbox_spl_test' ++ /usr/bin/ld: dts/dt-uclass.o:(.u_boot_list_2_uclass_2_misc+0x8): ++ undefined reference to `_u_boot_list_2_uclass_driver_2_misc' ++ ++The first one indicates that the device cannot find its driver. This means that ++there is a driver 'sandbox_spl_test' but it is not compiled into the build. ++Check your Kconfig settings to make sure it is. If you don't want that in the ++build, adjust your phase settings, e.g. by using 'u-boot,dm-spl' in the node ++to exclude it from the TPL build:: ++ ++ spl-test5 { ++ u-boot,dm-tpl; ++ compatible = "sandbox,spl-test"; ++ stringarray = "tpl"; ++ }; ++ ++We can drop the 'u-boot,dm-tpl' line so this node won't appear in the TPL ++devicetree and thus the driver won't be needed. ++ ++The second error above indicates that the MISC uclass is needed by the driver ++(since it is in the MISC uclass) but that uclass is not compiled in the build. ++The fix above would fix this error too. But if you do want this uclass in the ++build, check your Kconfig settings to make sure the uclass is being built ++(CONFIG_MISC in this case). ++ ++Another error that can crop up is something like:: ++ ++ spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to ++ incomplete type ‘struct sandbox_irq_priv’ ++ 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)] ++ | ^~~~~~ ++ ++This indicates that `struct sandbox_irq_priv` is not defined anywhere. The ++solution is to add a DM_HEADER() line, as below, so this is included in the ++dt-device.c file:: ++ ++ U_BOOT_DRIVER(sandbox_irq) = { ++ .name = "sandbox_irq", ++ .id = UCLASS_IRQ, ++ .of_match = sandbox_irq_ids, ++ .ops = &sandbox_irq_ops, ++ .priv_auto = sizeof(struct sandbox_irq_priv), ++ DM_HEADER(<asm/irq.h>) ++ }; ++ ++Note that there is no dependency checking on the above, so U-Boot will not ++regenerate the dt-device.c file when you update the source file (here, ++`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build. ++ ++Another error that can crop up is something like:: ++ ++ spl/dts/dt-device.c:257:38: error: invalid application of ‘sizeof’ to ++ incomplete type ‘struct sandbox_irq_priv’ ++ 257 | u8 _sandbox_irq_priv_irq_sbox[sizeof(struct sandbox_irq_priv)] ++ | ^~~~~~ ++ ++This indicates that `struct sandbox_irq_priv` is not defined anywhere. The ++solution is to add a DM_HEADER() line, as below, so this is included in the ++dt-device.c file:: ++ ++ U_BOOT_DRIVER(sandbox_irq) = { ++ .name = "sandbox_irq", ++ .id = UCLASS_IRQ, ++ .of_match = sandbox_irq_ids, ++ .ops = &sandbox_irq_ops, ++ .priv_auto = sizeof(struct sandbox_irq_priv), ++ DM_HEADER(<asm/irq.h>) ++ }; ++ ++Note that there is no dependency checking on the above, so U-Boot will not ++regenerate the dt-device.c file when you update the source file (here, ++`irq_sandbox.c`). You need to run `make mrproper` first to get a fresh build. ++ + + Caveats + ------- +@@ -697,7 +829,7 @@ + --------- + + Generated files +-``````````````` ++~~~~~~~~~~~~~~~ + + When enabled, dtoc generates the following five files: + +@@ -738,7 +870,7 @@ + + + CONFIG options +-`````````````` ++~~~~~~~~~~~~~~ + + Several CONFIG options are used to control the behaviour of of-platdata, all + available for both SPL and TPL: +@@ -793,7 +925,7 @@ + the nodes cannot be updated, OF_PLATDATA_NO_BIND is enabled. + + Data structures +-``````````````` ++~~~~~~~~~~~~~~~ + + A few extra data structures are used with of-platdata: + +@@ -821,7 +953,7 @@ + `device_get_by_ofplat_idx()`. + + Other changes +-````````````` ++~~~~~~~~~~~~~ + + Some other changes are made with of-platdata: + +diff -ruN u-boot-2021.10/doc/develop/index.rst u-boot/doc/develop/index.rst +--- u-boot-2021.10/doc/develop/index.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/develop/index.rst 2021-11-01 17:10:14.226261158 +0100 +@@ -56,5 +56,6 @@ + .. toctree:: + :maxdepth: 1 + ++ checkpatch + coccinelle + moveconfig +diff -ruN u-boot-2021.10/doc/develop/py_testing.rst u-boot/doc/develop/py_testing.rst +--- u-boot-2021.10/doc/develop/py_testing.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/develop/py_testing.rst 2021-11-01 17:10:14.226261158 +0100 +@@ -103,6 +103,36 @@ + browser, but may be read directly as plain text, perhaps with the aid of the + `html2text` utility. + ++Running tests in parallel ++~~~~~~~~~~~~~~~~~~~~~~~~~ ++ ++Note: This does not fully work yet and is documented only so you can try to ++fix the problems. ++ ++First install support for parallel tests:: ++ ++ pip3 install pytest-xdist ++ ++Then build sandbox in a suitable build directory. It is not possible to use ++the --build flag with xdist. ++ ++Finally, run the tests in parallel using the -n flag:: ++ ++ # build sandbox first, in a suitable build directory. It is not possible ++ # to use the --build flag with -n ++ test/py/test.py -B sandbox --build-dir /tmp/b/sandbox -q -k 'not slow' -n32 ++ ++At least the following non-slow tests are known to fail: ++ ++- test_fit_ecdsa ++- test_bind_unbind_with_uclass ++- ut_dm_spi_flash ++- test_gpt_rename_partition ++- test_gpt_swap_partitions ++- test_pinmux_status ++- test_sqfs_load ++ ++ + Testing under a debugger + ~~~~~~~~~~~~~~~~~~~~~~~~ + +diff -ruN u-boot-2021.10/doc/develop/version.rst u-boot/doc/develop/version.rst +--- u-boot-2021.10/doc/develop/version.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/develop/version.rst 2021-11-01 17:10:14.226261158 +0100 +@@ -60,15 +60,6 @@ + + This is used as part of the banner string when U-Boot starts. + +- U_BOOT_VERSION_STRING (string #define) +- U_BOOT_VERSION followed by build-time information +- and CONFIG_IDENT_STRING. +- +- Examples:: +- +- U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700) +- U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring +- + U_BOOT_VERSION_NUM (integer #define) + Release year, e.g. 2021 for release 2021.01. Note + this is an integer, not a string. +@@ -77,6 +68,18 @@ + Patch number, e.g. 1 for release 2020.01. Note + this is an integer, not a string. + ++Human readable U-Boot version string is available in header file ++include/version_string.h in following variable: ++ ++ version_string (const char[]) ++ U_BOOT_VERSION followed by build-time information ++ and CONFIG_IDENT_STRING. ++ ++ Examples:: ++ ++ U-Boot 2020.10 (Jan 06 2021 - 08:50:36 -0700) ++ U-Boot 2021.01-rc5-00248-g60dd854f3ba-dirty (Jan 06 2021 - 08:50:36 -0700) for spring ++ + Build date/time is also included. See the generated file + include/generated/timestamp_autogenerated.h for the available + fields. For example:: +@@ -84,7 +87,6 @@ + #define U_BOOT_DATE "Jan 06 2021" (US format only) + #define U_BOOT_TIME "08:50:36" (24-hour clock) + #define U_BOOT_TZ "-0700" (Time zone in hours) +- #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format) + #define U_BOOT_EPOCH 1609948236 + + The Epoch is the number of seconds since midnight on 1/1/70. You can convert +diff -ruN u-boot-2021.10/doc/device-tree-bindings/config.txt u-boot/doc/device-tree-bindings/config.txt +--- u-boot-2021.10/doc/device-tree-bindings/config.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/config.txt 2021-11-01 17:10:14.226261158 +0100 +@@ -2,8 +2,8 @@ + ---------------------------------------- + + A number of run-time configuration options are provided in the /config node +-of the control device tree. You can access these using fdtdec_get_config_int(), +-fdtdec_get_config_bool() and fdtdec_get_config_string(). ++of the control device tree. You can access these using ofnode_conf_read_int(), ++ofnode_conf_read_bool() and ofnode_conf_read_str(). + + These options are designed to affect the operation of U-Boot at runtime. + Runtime-configuration items can help avoid proliferation of different builds +diff -ruN u-boot-2021.10/doc/device-tree-bindings/firmware/linaro,optee-tz.txt u-boot/doc/device-tree-bindings/firmware/linaro,optee-tz.txt +--- u-boot-2021.10/doc/device-tree-bindings/firmware/linaro,optee-tz.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/firmware/linaro,optee-tz.txt 2021-11-01 17:10:14.229594309 +0100 +@@ -21,7 +21,6 @@ + in drivers/tee/optee/optee_smc.h + + +- + Example: + firmware { + optee { +diff -ruN u-boot-2021.10/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt u-boot/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt +--- u-boot-2021.10/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/mailbox/k3-secure-proxy.txt 2021-11-01 17:10:14.229594309 +0100 +@@ -10,7 +10,7 @@ + Required properties: + -------------------- + - compatible: Shall be: "ti,am654-secure-proxy" +-- reg-names data - Map the data region ++- reg-names data - Map the data region + scfg - Map the secure configuration region + rt - Map the Realtime region. + - reg: Contains the register map per reg-names. +diff -ruN u-boot-2021.10/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt u-boot/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt +--- u-boot-2021.10/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt 2021-11-01 17:10:14.229594309 +0100 +@@ -11,7 +11,7 @@ + -------------------- + - compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200 + "ti,am64-ddrss" for am642 +-- reg-names cfg - Map the controller configuration region ++- reg-names cfg - Map the controller configuration region + ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr + - reg: Contains the register map per reg-names. + - power-domains: Should contain two entries: +diff -ruN u-boot-2021.10/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt u-boot/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt +--- u-boot-2021.10/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt 2021-11-01 17:10:14.229594309 +0100 +@@ -14,7 +14,7 @@ + Required properties: + -------------------- + - compatible: Shall be: "ti,am654-ddrss" +-- reg-names ss - Map the sub system wrapper logic region ++- reg-names ss - Map the sub system wrapper logic region + ctl - Map the controller region + phy - Map the PHY region + - reg: Contains the register map per reg-names. +diff -ruN u-boot-2021.10/doc/device-tree-bindings/mmc/snps,dw-mmc.txt u-boot/doc/device-tree-bindings/mmc/snps,dw-mmc.txt +--- u-boot-2021.10/doc/device-tree-bindings/mmc/snps,dw-mmc.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/mmc/snps,dw-mmc.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -30,4 +30,3 @@ + clock-names = "biu", "ciu"; + max-frequency = <25000000>; + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/net/altera_tse.txt u-boot/doc/device-tree-bindings/net/altera_tse.txt +--- u-boot-2021.10/doc/device-tree-bindings/net/altera_tse.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/net/altera_tse.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -90,7 +90,7 @@ + + tse_sub_1_eth_tse_0: ethernet@0x1,00001000 { + compatible = "altr,tse-msgdma-1.0"; +- reg = <0x00000001 0x00001000 0x00000400>, ++ reg = <0x00000001 0x00001000 0x00000400>, + <0x00000001 0x00001460 0x00000020>, + <0x00000001 0x00001480 0x00000020>, + <0x00000001 0x000014A0 0x00000008>, +diff -ruN u-boot-2021.10/doc/device-tree-bindings/net/ethernet.txt u-boot/doc/device-tree-bindings/net/ethernet.txt +--- u-boot-2021.10/doc/device-tree-bindings/net/ethernet.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/net/ethernet.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -41,7 +41,17 @@ + * "2500base-x", + * "rxaui" + * "xaui" +- * "10gbase-kr" (10GBASE-KR, XFI, SFI) ++ * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol ++ used with various different mediums. Please refer to the IEEE standard for ++ a definition of this. Note: 10GBASE-R is just one protocol that can be used ++ with XFI and SFI. XFI and SFI permit multiple protocols over a single ++ SERDES lane, and also defines the electrical characteristics of the signals ++ with a host compliance board plugged into the host XFP/SFP connector. ++ Therefore, XFI and SFI are not PHY interface types in their own right.) ++ * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with ++ Clause 73 autonegotiation. Please refer to the IEEE standard for further ++ information. Note: due to legacy usage, some 10GBASE-R usage incorrectly ++ makes use of this definition). + - phy-connection-type: the same as "phy-mode" property but described in the + Devicetree Specification; + - phy-handle: phandle, specifies a reference to a node representing a PHY +diff -ruN u-boot-2021.10/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt u-boot/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt +--- u-boot-2021.10/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -21,7 +21,7 @@ + + fec0: ethernet@9000 { + compatible = "fsl,mcf-dma-fec"; +- reg = <0x9000 0x800>; ++ reg = <0x9000 0x800>; + mii-base = <0>; + phy-addr = <0>; + timeout-loop = <5000>; +diff -ruN u-boot-2021.10/doc/device-tree-bindings/net/fsl,mcf-fec.txt u-boot/doc/device-tree-bindings/net/fsl,mcf-fec.txt +--- u-boot-2021.10/doc/device-tree-bindings/net/fsl,mcf-fec.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/net/fsl,mcf-fec.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -15,7 +15,7 @@ + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; +- reg = <0xfc030000 0x400>; ++ reg = <0xfc030000 0x400>; + mii-base = <0>; + phy-addr = <0>; + timeout-loop = <5000>; +diff -ruN u-boot-2021.10/doc/device-tree-bindings/net/mdio.txt u-boot/doc/device-tree-bindings/net/mdio.txt +--- u-boot-2021.10/doc/device-tree-bindings/net/mdio.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/net/mdio.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -33,4 +33,3 @@ + reg = <2>; + }; + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt u-boot/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt +--- u-boot-2021.10/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -2,7 +2,7 @@ + + Required properties for the pinctrl driver: + - compatible: "brcm,bcm6838-pinctrl" +-- regmap: specify the gpio test port syscon ++- regmap: specify the gpio test port syscon + - brcm,pins-count: the number of pin + - brcm,functions-count: the number of function + +diff -ruN u-boot-2021.10/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt u-boot/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt +--- u-boot-2021.10/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -3,19 +3,19 @@ + ---------------------------------------------------------------------- + MPP# 0x1 0x2 0x3 0x4 + ---------------------------------------------------------------------- +-0 SDIO_CLK - SPI0_CLK - ++0 SDIO_CLK - SPI0_CLK - + 1 SDIO_CMD - SPI0_MISO - +-2 SDIO_D[0] - SPI0_MOSI - +-3 SDIO_D[1] - SPI0_CS0n - ++2 SDIO_D[0] - SPI0_MOSI - ++3 SDIO_D[1] - SPI0_CS0n - + 4 SDIO_D[2] - I2C0_SDA SPI0_CS1n + 5 SDIO_D[3] - I2C0_SCK - + 6 SDIO_DS - - - + 7 SDIO_D[4] - UART1_RXD - +-8 SDIO_D[5] - UART1_TXD - +-9 SDIO_D[6] - SPI0_CS1n - ++8 SDIO_D[5] - UART1_TXD - ++9 SDIO_D[6] - SPI0_CS1n - + 10 SDIO_D[7] - - - +-11 - - UART0_TXD - +-12 SDIO_CARD_PW_OFF SDIO_HW_RST - - ++11 - - UART0_TXD - ++12 SDIO_CARD_PW_OFF SDIO_HW_RST - - + 13 - - - - + 14 - - - - + 15 - - - - +diff -ruN u-boot-2021.10/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt u-boot/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt +--- u-boot-2021.10/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -11,7 +11,7 @@ + "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" + - bank-name: A string defining the pinc controller bank name +-- reg: A pair of values defining the pin controller base address ++- reg: A pair of values defining the pin controller base address + and the address space + - pin-count: Numeric value defining the amount of multi purpose pins + included in this bank +diff -ruN u-boot-2021.10/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt u-boot/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt +--- u-boot-2021.10/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt 2021-11-01 17:10:14.232927460 +0100 +@@ -8,21 +8,21 @@ + - anatop-reg-offset: u32 value representing the anatop MFD register offset. + - anatop-vol-bit-shift: u32 value representing the bit shift for the register. + - anatop-vol-bit-width: u32 value representing the number of bits used in the +- register. ++ register. + - anatop-min-bit-val: u32 value representing the minimum value of this +- register. ++ register. + - anatop-min-voltage: u32 value representing the minimum voltage of this +- regulator. ++ regulator. + - anatop-max-voltage: u32 value representing the maximum voltage of this +- regulator. ++ regulator. + + Optional properties: + - anatop-delay-reg-offset: u32 value representing the anatop MFD step time +- register offset. ++ register offset. + - anatop-delay-bit-shift: u32 value representing the bit shift for the step +- time register. ++ time register. + - anatop-delay-bit-width: u32 value representing the number of bits used in +- the step time register. ++ the step time register. + - anatop-enable-bit: u32 value representing regulator enable bit offset. + - vin-supply: input supply phandle. + +diff -ruN u-boot-2021.10/doc/device-tree-bindings/spi/spi-bus.txt u-boot/doc/device-tree-bindings/spi/spi-bus.txt +--- u-boot-2021.10/doc/device-tree-bindings/spi/spi-bus.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/spi/spi-bus.txt 2021-11-01 17:10:14.236260611 +0100 +@@ -8,10 +8,10 @@ + + The SPI master node requires the following properties: + - #address-cells - number of cells required to define a chip select +- address on the SPI bus. ++ address on the SPI bus. + - #size-cells - should be zero. + - compatible - name of SPI bus controller following generic names +- recommended practice. ++ recommended practice. + - cs-gpios - (optional) gpios chip select. + No other properties are required in the SPI bus node. It is assumed + that a driver for an SPI bus device will understand that it is an SPI bus. +@@ -45,16 +45,16 @@ + contain the following properties. + - reg - (required) chip select address of device. + - compatible - (required) name of SPI device following generic names +- recommended practice ++ recommended practice + - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz + - spi-cpol - (optional) Empty property indicating device requires +- inverse clock polarity (CPOL) mode ++ inverse clock polarity (CPOL) mode + - spi-cpha - (optional) Empty property indicating device requires +- shifted clock phase (CPHA) mode ++ shifted clock phase (CPHA) mode + - spi-cs-high - (optional) Empty property indicating device requires +- chip select active high ++ chip select active high + - spi-3wire - (optional) Empty property indicating device requires +- 3-wire mode. ++ 3-wire mode. + - spi-tx-bus-width - (optional) The bus width(number of data wires) that + used for MOSI. Defaults to 1 if not present. + - spi-rx-bus-width - (optional) The bus width(number of data wires) that +diff -ruN u-boot-2021.10/doc/device-tree-bindings/spi/spi-qup.txt u-boot/doc/device-tree-bindings/spi/spi-qup.txt +--- u-boot-2021.10/doc/device-tree-bindings/spi/spi-qup.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/spi/spi-qup.txt 2021-11-01 17:10:14.236260611 +0100 +@@ -7,7 +7,7 @@ + - reg : Physical base address and size of SPI registers map. + - clock : Clock phandle (see clock bindings for details). + - #address-cells : Number of cells required to define a chip select +- address on the SPI bus. Should be set to 1. ++ address on the SPI bus. Should be set to 1. + - #size-cells : Should be zero. + - pinctrl-names : Must be "default" + - pinctrl-n : At least one pinctrl phandle +diff -ruN u-boot-2021.10/doc/device-tree-bindings/tpm2/sandbox.txt u-boot/doc/device-tree-bindings/tpm2/sandbox.txt +--- u-boot-2021.10/doc/device-tree-bindings/tpm2/sandbox.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/tpm2/sandbox.txt 2021-11-01 17:10:14.236260611 +0100 +@@ -7,5 +7,5 @@ + Example: + + tpm { +- compatible = "sandbox,tpm2"; ++ compatible = "sandbox,tpm2"; + }; +diff -ruN u-boot-2021.10/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt u-boot/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt +--- u-boot-2021.10/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt 2021-11-01 17:10:14.236260611 +0100 +@@ -6,7 +6,8 @@ + - reg : SPI Chip select + + Optional properties: +-- gpio-reset : Reset GPIO (if not connected to the SoC reset line) ++- reset-gpios : Reset GPIO (if not connected to the SoC reset line) ++- gpio-reset : Reset GPIO (deprecated, use reset-gpios instead) + - spi-max-frequency : See spi-bus.txt + + Example: +diff -ruN u-boot-2021.10/doc/device-tree-bindings/w1/w1-gpio.txt u-boot/doc/device-tree-bindings/w1/w1-gpio.txt +--- u-boot-2021.10/doc/device-tree-bindings/w1/w1-gpio.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/w1/w1-gpio.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -37,4 +37,3 @@ + compatible = "maxim,ds24xxx"; + } + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt u-boot/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt +--- u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -34,4 +34,3 @@ + compatible = "maxim,ds24xxx"; + } + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/ds2502.txt u-boot/doc/device-tree-bindings/w1-eeprom/ds2502.txt +--- u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/ds2502.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/w1-eeprom/ds2502.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -30,4 +30,3 @@ + compatible = "maxim,ds2502"; + }; + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt u-boot/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt +--- u-boot-2021.10/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -31,4 +31,3 @@ + compatible = "sandbox,w1-eeprom"; + } + }; +- +diff -ruN u-boot-2021.10/doc/device-tree-bindings/watchdog/gpio-wdt.txt u-boot/doc/device-tree-bindings/watchdog/gpio-wdt.txt +--- u-boot-2021.10/doc/device-tree-bindings/watchdog/gpio-wdt.txt 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/doc/device-tree-bindings/watchdog/gpio-wdt.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -0,0 +1,19 @@ ++GPIO watchdog timer ++ ++Describes a simple watchdog timer which is reset by toggling a gpio. ++ ++Required properties: ++ ++- compatible: Must be "linux,wdt-gpio". ++- gpios: gpio to toggle when wdt driver reset method is called. ++- always-running: Boolean property indicating that the watchdog cannot ++ be disabled. At present, U-Boot only supports this kind of GPIO ++ watchdog. ++ ++Example: ++ ++ gpio-wdt { ++ gpios = <&gpio0 1 0>; ++ compatible = "linux,wdt-gpio"; ++ always-running; ++ }; +diff -ruN u-boot-2021.10/doc/imx/common/imx25.txt u-boot/doc/imx/common/imx25.txt +--- u-boot-2021.10/doc/imx/common/imx25.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/imx/common/imx25.txt 1970-01-01 01:00:00.000000000 +0100 +@@ -1,10 +0,0 @@ +-U-Boot for Freescale i.MX25 +- +-This file contains information for the port of U-Boot to the Freescale i.MX25 +-SoC. +- +-1. CONVENTIONS FOR FUSE ASSIGNMENTS +------------------------------------ +- +-1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the +- natural MAC byte order (i.e. MSB first). +diff -ruN u-boot-2021.10/doc/imx/common/imx6.txt u-boot/doc/imx/common/imx6.txt +--- u-boot-2021.10/doc/imx/common/imx6.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/imx/common/imx6.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -9,7 +9,7 @@ + 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the + 16 msbs in word 3[15:0]. + For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address +- is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in ++ is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in + word 4. + + Example: +diff -ruN u-boot-2021.10/doc/kwboot.1 u-boot/doc/kwboot.1 +--- u-boot-2021.10/doc/kwboot.1 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/kwboot.1 2021-11-01 17:10:14.239593762 +0100 +@@ -1,21 +1,22 @@ +-.TH KWBOOT 1 "2012-05-19" ++.TH KWBOOT 1 "2021-08-25" + + .SH NAME +-kwboot \- Boot Marvell Kirkwood SoCs over a serial link. ++kwboot \- Boot Marvell Kirkwood (and others 32-bit) SoCs over a serial link. + .SH SYNOPSIS + .B kwboot + .RB [ "-b \fIimage\fP" ] +-.RB [ "-p" ] + .RB [ "-t" ] + .RB [ "-B \fIbaudrate\fP" ] + .RB \fITTY\fP + .SH "DESCRIPTION" + +-The \fBmkimage\fP program boots boards based on Marvell's Kirkwood +-platform over their integrated UART. Boot image files will typically ++The \fBkwboot\fP program boots boards based on Marvell's 32-bit ++platforms including Kirkwood, Dove, A370, AXP, A375, A38x ++and A39x over their integrated UART. Boot image files will typically + contain a second stage boot loader, such as U-Boot. The image file + must conform to Marvell's BootROM firmware image format +-(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP. ++(\fIkwbimage v0\fP or \fIv1\fP), created using a tool such as ++\fBmkimage\fP. + + Following power-up or a system reset, system BootROM code polls the + UART for a brief period of time, sensing a handshake message which +@@ -36,25 +37,23 @@ + Handshake; then upload file \fIimage\fP over \fITTY\fP. + + Note that for the encapsulated boot code to be executed, \fIimage\fP +-must be of type "UART boot" (0x69). Boot images of different types, +-such as backup images of vendor firmware downloaded from flash memory +-(type 0x8B), will not work (or not as expected). See \fB-p\fP for a +-workaround. ++must be of type "UART boot" (0x69). The \fBkwboot\fP program changes ++this type automatically, unless the \fIimage\fP is signed, in which ++case it cannot be changed. + + This mode writes handshake status and upload progress indication to +-stdout. ++stdout. It is possible that \fIimage\fP contains an optional binary ++code in it's header which may also print some output via UART (for ++example U-Boot SPL does this). In such a case, this output is also ++written to stdout after the header is sent. + + .TP + .BI "\-p" +-In combination with \fB-b\fP, patches the header in \fIimage\fP prior +-to upload, to "UART boot" type. ++Obsolete. Does nothing. + +-This option attempts on-the-fly conversion of some none-UART image +-types, such as images which were originally formatted to be stored in +-flash memory. +- +-Conversion is performed in memory. The contents of \fIimage\fP will +-not be altered. ++In the past, when this option was used, the program patched the header ++in the image prior upload, to "UART boot" type. This is now done by ++default. + + .TP + .BI "\-t" +@@ -65,11 +64,26 @@ + immediately following a successful image upload. + + If standard I/O streams connect to a console, this mode will terminate +-after receiving 'ctrl-\\' followed by 'c' from console input. ++after receiving \fBctrl-\e\fP followed by \fBc\fP from console input. + + .TP + .BI "\-B \fIbaudrate\fP" +-Adjust the baud rate on \fITTY\fP. Default rate is 115200. ++If used in combination with \fB-b\fP, inject into the image header ++code that changes baud rate to \fIbaudrate\fP after uploading image ++header, and code that changes the baud rate back to the default ++(115200 Bd) before executing payload, and also adjust the baud rate ++on \fITTY\fP correspondingly. This can make the upload significantly ++faster. ++ ++If used in combination with \fB-t\fP, adjust the baud rate to ++\fIbaudrate\fP on \fITTY\fP before starting terminal. ++ ++If both \fB-b\fP and \fB-t\fP are used, the baud rate is changed ++back to 115200 after the upload. ++ ++Tested values for \fIbaudrate\fP for Armada 38x include: 115200, ++230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000, ++2000000, 2500000, 3125000, 4000000 and 5200000. + + .SH "SEE ALSO" + .PP +@@ -82,3 +96,7 @@ + Luka Perkov <luka@openwrt.org> + .br + David Purdy <david.c.purdy@gmail.com> ++.br ++Pali Rohár <pali@kernel.org> ++.br ++Marek Behún <marek.behun@nic.cz> +diff -ruN u-boot-2021.10/doc/mvebu/armada-8k-memory.txt u-boot/doc/mvebu/armada-8k-memory.txt +--- u-boot-2021.10/doc/mvebu/armada-8k-memory.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/mvebu/armada-8k-memory.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -53,4 +53,3 @@ + 0xFFF00000 0xFFFFFFFF Bootrom + + 0x100000000 <DRAM Size>-1 DRAM +- +diff -ruN u-boot-2021.10/doc/mvebu/cmd/bubt.txt u-boot/doc/mvebu/cmd/bubt.txt +--- u-boot-2021.10/doc/mvebu/cmd/bubt.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/mvebu/cmd/bubt.txt 2021-11-01 17:10:14.239593762 +0100 +@@ -52,4 +52,3 @@ + - NAND: # nand write <load_address> 0 <ATF Size> + - SPI: # sf write <load_address> 0 <ATF Size> + - SD/eMMC: # mmc write <load_address> [0|1] <ATF Size>/<block_size> +- +diff -ruN u-boot-2021.10/doc/README.commands.spl u-boot/doc/README.commands.spl +--- u-boot-2021.10/doc/README.commands.spl 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.commands.spl 2021-11-01 17:10:14.206262252 +0100 +@@ -17,14 +17,14 @@ + + on OMAP3: + nandecc hw +-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +-spl export atags /* export ATAGS */ ++nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ ++spl export atags /* export ATAGS */ + nand erase 0x680000 0x20000 /* erase - one page */ + nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ + + call with FDT: + nandecc hw +-nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ ++nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ + tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ + spl export fdt 0x82000000 - 0x80000100 /* export FDT */ + nand erase 0x680000 0x20000 /* erase - one page */ +diff -ruN u-boot-2021.10/doc/README.dfutftp u-boot/doc/README.dfutftp +--- u-boot-2021.10/doc/README.dfutftp 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.dfutftp 2021-11-01 17:10:14.206262252 +0100 +@@ -88,7 +88,6 @@ + possible to set large enough default buffer (8 MiB @ BBB) + + +- + FIT image format for download + ----------------------------- + +@@ -110,7 +109,6 @@ + where "u-boot.bin" is the DFU entity name to be stored. + + +- + To do + ----- + +diff -ruN u-boot-2021.10/doc/README.distro u-boot/doc/README.distro +--- u-boot-2021.10/doc/README.distro 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.distro 2021-11-01 17:10:14.206262252 +0100 +@@ -233,7 +233,7 @@ + the DTB with a different DTB. fdtfile will automatically be set for you if + it matches the format ${soc}-${board}.dtb which covers most 32 bit use cases. + AArch64 generally does not match as the Linux kernel put the dtb files under +- SoC vendor directories. ++ SoC vendor directories. + + ramdisk_addr_r: + +diff -ruN u-boot-2021.10/doc/README.falcon u-boot/doc/README.falcon +--- u-boot-2021.10/doc/README.falcon 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.falcon 2021-11-01 17:10:14.206262252 +0100 +@@ -69,7 +69,7 @@ + + CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved. + +-CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied ++CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied + + CONFIG_SPL_OS_BOOT Activate Falcon Mode. + +@@ -89,7 +89,7 @@ + A board may chose to look at the environment for decisions about falcon + mode. In this case the following variables may be supported: + +-boot_os : Set to yes/Yes/true/True/1 to enable booting to OS, ++boot_os : Set to yes/Yes/true/True/1 to enable booting to OS, + any other value to fall back to U-Boot (including + unset) + falcon_args_file : Filename to load as the 'args' portion of falcon mode +diff -ruN u-boot-2021.10/doc/README.nand u-boot/doc/README.nand +--- u-boot-2021.10/doc/README.nand 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.nand 2021-11-01 17:10:14.209595403 +0100 +@@ -175,11 +175,6 @@ + flexibility, so that one day we can eliminate the old mechanism. + + +- CONFIG_SYS_NAND_ONFI_DETECTION +- Enables detection of ONFI compliant devices during probe. +- And fetching device parameters flashed on device, by parsing +- ONFI parameter page. +- + Platform specific options + ========================= + CONFIG_NAND_OMAP_GPMC +@@ -205,72 +200,6 @@ + so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling + SPL-NAND driver with software ECC correction support. + +- CONFIG_NAND_OMAP_ECCSCHEME +- On OMAP platforms, this CONFIG specifies NAND ECC scheme. +- It can take following values: +- OMAP_ECC_HAM1_CODE_SW +- 1-bit Hamming code using software lib. +- (for legacy devices only) +- OMAP_ECC_HAM1_CODE_HW +- 1-bit Hamming code using GPMC hardware. +- (for legacy devices only) +- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW +- 4-bit BCH code (unsupported) +- OMAP_ECC_BCH4_CODE_HW +- 4-bit BCH code (unsupported) +- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +- 8-bit BCH code with +- - ecc calculation using GPMC hardware engine, +- - error detection using software library. +- - requires CONFIG_BCH to enable software BCH library +- (For legacy device which do not have ELM h/w engine) +- OMAP_ECC_BCH8_CODE_HW +- 8-bit BCH code with +- - ecc calculation using GPMC hardware engine, +- - error detection using ELM hardware engine. +- OMAP_ECC_BCH16_CODE_HW +- 16-bit BCH code with +- - ecc calculation using GPMC hardware engine, +- - error detection using ELM hardware engine. +- +- How to select ECC scheme on OMAP and AMxx platforms ? +- ----------------------------------------------------- +- Though higher ECC schemes have more capability to detect and correct +- bit-flips, but still selection of ECC scheme is dependent on following +- - hardware engines present in SoC. +- Some legacy OMAP SoC do not have ELM h/w engine thus such +- SoC cannot support BCHx_HW ECC schemes. +- - size of OOB/Spare region +- With higher ECC schemes, more OOB/Spare area is required to +- store ECC. So choice of ECC scheme is limited by NAND oobsize. +- +- In general following expression can help: +- NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES +- where +- NAND_OOBSIZE = number of bytes available in +- OOB/spare area per NAND page. +- NAND_PAGESIZE = bytes in main-area of NAND page. +- ECC_BYTES = number of ECC bytes generated to +- protect 512 bytes of data, which is: +- 3 for HAM1_xx ecc schemes +- 7 for BCH4_xx ecc schemes +- 14 for BCH8_xx ecc schemes +- 26 for BCH16_xx ecc schemes +- +- example to check for BCH16 on 2K page NAND +- NAND_PAGESIZE = 2048 +- NAND_OOBSIZE = 64 +- 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE +- Thus BCH16 cannot be supported on 2K page NAND. +- +- However, for 4K pagesize NAND +- NAND_PAGESIZE = 4096 +- NAND_OOBSIZE = 224 +- ECC_BYTES = 26 +- 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE +- Thus BCH16 can be supported on 4K page NAND. +- +- + CONFIG_NAND_OMAP_GPMC_PREFETCH + On OMAP platforms that use the GPMC controller + (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that +diff -ruN u-boot-2021.10/doc/README.odroid u-boot/doc/README.odroid +--- u-boot-2021.10/doc/README.odroid 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.odroid 2021-11-01 17:10:14.209595403 +0100 +@@ -296,8 +296,8 @@ + Partition Map for USB device 0 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type +- 1 3072 263168 000c4046-01 06 +- 2 266240 13457408 000c4046-02 83 ++ 1 3072 263168 000c4046-01 06 ++ 2 266240 13457408 000c4046-02 83 + + Odroid # ls usb 0:2 /boot + <DIR> 4096 . +diff -ruN u-boot-2021.10/doc/README.pcap u-boot/doc/README.pcap +--- u-boot-2021.10/doc/README.pcap 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.pcap 2021-11-01 17:10:14.209595403 +0100 +@@ -59,4 +59,3 @@ + + # pcap stop + # tftpput 0xffffffff80100000 $pcapsize 10.0.2.2:capture.pcap +- +diff -ruN u-boot-2021.10/doc/README.SPL u-boot/doc/README.SPL +--- u-boot-2021.10/doc/README.SPL 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/README.SPL 2021-11-01 17:10:14.206262252 +0100 +@@ -49,10 +49,10 @@ + CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o) + CONFIG_SPL_I2C (drivers/i2c/libi2c.o) + CONFIG_SPL_GPIO (drivers/gpio/libgpio.o) +-CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o) +-CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) ++CONFIG_SPL_MMC (drivers/mmc/libmmc.o) ++CONFIG_SPL_SERIAL (drivers/serial/libserial.o) + CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) +-CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) ++CONFIG_SPL_SPI (drivers/spi/libspi.o) + CONFIG_SPL_FS_FAT (fs/fat/libfat.o) + CONFIG_SPL_FS_EXT4 + CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) +diff -ruN u-boot-2021.10/doc/SPL/README.am335x-network u-boot/doc/SPL/README.am335x-network +--- u-boot-2021.10/doc/SPL/README.am335x-network 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/SPL/README.am335x-network 2021-11-01 17:10:14.212928554 +0100 +@@ -7,7 +7,7 @@ + + I. Building the required images + 1. You have to enable generic SPL configuration options (see +-doc/README.SPL) as well as CONFIG_SPL_NET_SUPPORT, ++doc/README.SPL) as well as CONFIG_SPL_NET, + CONFIG_SPL_ETH, CONFIG_SPL_LIBGENERIC_SUPPORT and + CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build + SPL with support for booting over the network. Also you have to enable +diff -ruN u-boot-2021.10/doc/usage/qfw.rst u-boot/doc/usage/qfw.rst +--- u-boot-2021.10/doc/usage/qfw.rst 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/doc/usage/qfw.rst 2021-11-01 17:10:14.242926913 +0100 +@@ -26,7 +26,7 @@ + kernel_addr + address to which the file specified by the -kernel parameter of QEMU shall + be loaded. Defaults to environment variable *loadaddr* and further to +- the value of *CONFIG_LOADADDR*. ++ the value of *CONFIG_SYS_LOAD_ADDR*. + + initrd_addr + address to which the file specified by the -initrd parameter of QEMU shall +diff -ruN u-boot-2021.10/drivers/ata/Kconfig u-boot/drivers/ata/Kconfig +--- u-boot-2021.10/drivers/ata/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ata/Kconfig 2021-11-01 17:10:14.246260064 +0100 +@@ -36,10 +36,17 @@ + + config AHCI_PCI + bool "Support for PCI-based AHCI controller" ++ depends on PCI + depends on DM_SCSI + help + Enables support for the PCI-based AHCI controller. + ++config SPL_AHCI_PCI ++ bool "Support for PCI-based AHCI controller for SPL" ++ depends on SPL ++ depends on SPL_PCI ++ depends on SPL_SATA_SUPPORT && DM_SCSI ++ + config SATA_CEVA + bool "Ceva Sata controller" + depends on AHCI +diff -ruN u-boot-2021.10/drivers/ata/Makefile u-boot/drivers/ata/Makefile +--- u-boot-2021.10/drivers/ata/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ata/Makefile 2021-11-01 17:10:14.246260064 +0100 +@@ -5,7 +5,7 @@ + + obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o + obj-$(CONFIG_AHCI) += ahci-uclass.o +-obj-$(CONFIG_AHCI_PCI) += ahci-pci.o ++obj-$(CONFIG_$(SPL_)AHCI_PCI) += ahci-pci.o + obj-$(CONFIG_SCSI_AHCI) += ahci.o + obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o + obj-$(CONFIG_FSL_SATA) += fsl_sata.o +diff -ruN u-boot-2021.10/drivers/axi/axi-uclass.c u-boot/drivers/axi/axi-uclass.c +--- u-boot-2021.10/drivers/axi/axi-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/axi/axi-uclass.c 2021-11-01 17:10:14.249593215 +0100 +@@ -38,4 +38,3 @@ + .post_bind = dm_scan_fdt_dev, + .flags = DM_UC_FLAG_SEQ_ALIAS, + }; +- +diff -ruN u-boot-2021.10/drivers/block/Kconfig u-boot/drivers/block/Kconfig +--- u-boot-2021.10/drivers/block/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/block/Kconfig 2021-11-01 17:10:14.252926366 +0100 +@@ -52,14 +52,12 @@ + config SPL_BLOCK_CACHE + bool "Use block device cache in SPL" + depends on SPL_BLK +- default n + help + This option enables the disk-block cache in SPL + + config TPL_BLOCK_CACHE + bool "Use block device cache in TPL" + depends on TPL_BLK +- default n + help + This option enables the disk-block cache in TPL + +diff -ruN u-boot-2021.10/drivers/cache/cache-v5l2.c u-boot/drivers/cache/cache-v5l2.c +--- u-boot-2021.10/drivers/cache/cache-v5l2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/cache/cache-v5l2.c 2021-11-01 17:10:14.256259517 +0100 +@@ -68,8 +68,8 @@ + struct l2cache *regs; + u32 iprefetch; + u32 dprefetch; +- u32 tram_ctl[2]; +- u32 dram_ctl[2]; ++ u32 tram_ctl[2]; ++ u32 dram_ctl[2]; + }; + + static int v5l2_enable(struct udevice *dev) +diff -ruN u-boot-2021.10/drivers/cache/sandbox_cache.c u-boot/drivers/cache/sandbox_cache.c +--- u-boot-2021.10/drivers/cache/sandbox_cache.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/cache/sandbox_cache.c 2021-11-01 17:10:14.256259517 +0100 +@@ -31,7 +31,7 @@ + + static const struct cache_ops sandbox_cache_ops = { + .get_info = sandbox_get_info, +- .enable = sandbox_enable, ++ .enable = sandbox_enable, + .disable = snadbox_disable, + }; + +diff -ruN u-boot-2021.10/drivers/clk/at91/clk-master.c u-boot/drivers/clk/at91/clk-master.c +--- u-boot-2021.10/drivers/clk/at91/clk-master.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/at91/clk-master.c 2021-11-01 17:10:14.256259517 +0100 +@@ -12,13 +12,15 @@ + #include <asm/processor.h> + #include <clk-uclass.h> + #include <common.h> ++#include <div64.h> + #include <dm.h> + #include <linux/clk-provider.h> + #include <linux/clk/at91_pmc.h> + + #include "pmc.h" + +-#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk" ++#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres" ++#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div" + #define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk" + + #define MASTER_PRES_MASK 0x7 +@@ -73,7 +75,7 @@ + return 0; + } + +-static ulong clk_master_get_rate(struct clk *clk) ++static ulong clk_master_pres_get_rate(struct clk *clk) + { + struct clk_master *master = to_clk_master(clk); + const struct clk_master_layout *layout = master->layout; +@@ -81,7 +83,7 @@ + master->characteristics; + ulong rate = clk_get_parent_rate(clk); + unsigned int mckr; +- u8 pres, div; ++ u8 pres; + + if (!rate) + return 0; +@@ -90,29 +92,21 @@ + mckr &= layout->mask; + + pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; +- div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + + if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) +- rate /= 3; ++ pres = 3; + else +- rate >>= pres; +- +- rate /= characteristics->divisors[div]; +- +- if (rate < characteristics->output.min) +- pr_warn("master clk is underclocked"); +- else if (rate > characteristics->output.max) +- pr_warn("master clk is overclocked"); ++ pres = (1 << pres); + +- return rate; ++ return DIV_ROUND_CLOSEST_ULL(rate, pres); + } + +-static const struct clk_ops master_ops = { ++static const struct clk_ops master_pres_ops = { + .enable = clk_master_enable, +- .get_rate = clk_master_get_rate, ++ .get_rate = clk_master_pres_get_rate, + }; + +-struct clk *at91_clk_register_master(void __iomem *base, ++struct clk *at91_clk_register_master_pres(void __iomem *base, + const char *name, const char * const *parent_names, + int num_parents, const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, +@@ -140,7 +134,7 @@ + pmc_read(master->base, master->layout->offset, &val); + clk = &master->clk; + clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; +- ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name, ++ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name, + parent_names[val & AT91_PMC_CSS]); + if (ret) { + kfree(master); +@@ -150,10 +144,81 @@ + return clk; + } + +-U_BOOT_DRIVER(at91_master_clk) = { +- .name = UBOOT_DM_CLK_AT91_MASTER, ++U_BOOT_DRIVER(at91_master_pres_clk) = { ++ .name = UBOOT_DM_CLK_AT91_MASTER_PRES, ++ .id = UCLASS_CLK, ++ .ops = &master_pres_ops, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++static ulong clk_master_div_get_rate(struct clk *clk) ++{ ++ struct clk_master *master = to_clk_master(clk); ++ const struct clk_master_layout *layout = master->layout; ++ const struct clk_master_characteristics *characteristics = ++ master->characteristics; ++ ulong rate = clk_get_parent_rate(clk); ++ unsigned int mckr; ++ u8 div; ++ ++ if (!rate) ++ return 0; ++ ++ pmc_read(master->base, master->layout->offset, &mckr); ++ mckr &= layout->mask; ++ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; ++ ++ rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]); ++ if (rate < characteristics->output.min) ++ pr_warn("master clk is underclocked"); ++ else if (rate > characteristics->output.max) ++ pr_warn("master clk is overclocked"); ++ ++ return rate; ++} ++ ++static const struct clk_ops master_div_ops = { ++ .enable = clk_master_enable, ++ .get_rate = clk_master_div_get_rate, ++}; ++ ++struct clk *at91_clk_register_master_div(void __iomem *base, ++ const char *name, const char *parent_name, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics) ++{ ++ struct clk_master *master; ++ struct clk *clk; ++ int ret; ++ ++ if (!base || !name || !parent_name || !layout || !characteristics) ++ return ERR_PTR(-EINVAL); ++ ++ master = kzalloc(sizeof(*master), GFP_KERNEL); ++ if (!master) ++ return ERR_PTR(-ENOMEM); ++ ++ master->layout = layout; ++ master->characteristics = characteristics; ++ master->base = base; ++ master->num_parents = 1; ++ ++ clk = &master->clk; ++ clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; ++ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name, ++ parent_name); ++ if (ret) { ++ kfree(master); ++ clk = ERR_PTR(ret); ++ } ++ ++ return clk; ++} ++ ++U_BOOT_DRIVER(at91_master_div_clk) = { ++ .name = UBOOT_DM_CLK_AT91_MASTER_DIV, + .id = UCLASS_CLK, +- .ops = &master_ops, ++ .ops = &master_div_ops, + .flags = DM_FLAG_PRE_RELOC, + }; + +diff -ruN u-boot-2021.10/drivers/clk/at91/clk-sam9x60-pll.c u-boot/drivers/clk/at91/clk-sam9x60-pll.c +--- u-boot-2021.10/drivers/clk/at91/clk-sam9x60-pll.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/at91/clk-sam9x60-pll.c 2021-11-01 17:10:14.259592668 +0100 +@@ -439,4 +439,3 @@ + .ops = &sam9x60_frac_pll_ops, + .flags = DM_FLAG_PRE_RELOC, + }; +- +diff -ruN u-boot-2021.10/drivers/clk/at91/pmc.h u-boot/drivers/clk/at91/pmc.h +--- u-boot-2021.10/drivers/clk/at91/pmc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/at91/pmc.h 2021-11-01 17:10:14.259592668 +0100 +@@ -97,12 +97,17 @@ + const struct clk_pll_characteristics *characteristics, + const struct clk_pll_layout *layout, bool critical); + struct clk * +-at91_clk_register_master(void __iomem *base, const char *name, ++at91_clk_register_master_pres(void __iomem *base, const char *name, + const char * const *parent_names, int num_parents, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, + const u32 *mux_table); + struct clk * ++at91_clk_register_master_div(void __iomem *base, ++ const char *name, const char *parent_name, ++ const struct clk_master_layout *layout, ++ const struct clk_master_characteristics *characteristics); ++struct clk * + at91_clk_sama7g5_register_master(void __iomem *base, const char *name, + const char * const *parent_names, int num_parents, + const u32 *mux_table, const u32 *clk_mux_table, +diff -ruN u-boot-2021.10/drivers/clk/at91/sam9x60.c u-boot/drivers/clk/at91/sam9x60.c +--- u-boot-2021.10/drivers/clk/at91/sam9x60.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/at91/sam9x60.c 2021-11-01 17:10:14.259592668 +0100 +@@ -31,7 +31,7 @@ + * @ID_PLL_A_FRAC: APLL fractional clock identifier + * @ID_PLL_A_DIV: APLL divider clock identifier + +- * @ID_MCK: MCK clock identifier ++ * @ID_MCK_DIV: MCK DIV clock identifier + + * @ID_UTMI: UTMI clock identifier + +@@ -43,6 +43,8 @@ + * @ID_DDR: DDR system clock identifier + * @ID_QSPI: QSPI system clock identifier + * ++ * @ID_MCK_PRES: MCK PRES clock identifier ++ * + * Note: if changing the values of this enums please sync them with + * device tree + */ +@@ -60,7 +62,7 @@ + ID_PLL_A_FRAC = 9, + ID_PLL_A_DIV = 10, + +- ID_MCK = 11, ++ ID_MCK_DIV = 11, + + ID_UTMI = 12, + +@@ -73,6 +75,8 @@ + ID_DDR = 17, + ID_QSPI = 18, + ++ ID_MCK_PRES = 19, ++ + ID_MAX, + }; + +@@ -93,7 +97,8 @@ + [ID_MAINCK] = "mainck", + [ID_PLL_U_DIV] = "upll_divpmcck", + [ID_PLL_A_DIV] = "plla_divpmcck", +- [ID_MCK] = "mck", ++ [ID_MCK_PRES] = "mck_pres", ++ [ID_MCK_DIV] = "mck_div", + }; + + /* Fractional PLL output range. */ +@@ -260,10 +265,10 @@ + u8 id; + u8 cid; + } sam9x60_systemck[] = { +- { .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, }, ++ { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, }, + { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, + { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, +- { .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, }, ++ { .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, }, + }; + + /** +@@ -508,7 +513,7 @@ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c); + } + +- /* Register MCK clock. */ ++ /* Register MCK pres clock. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_MAINCK]; + p[2] = clk_names[ID_PLL_A_DIV]; +@@ -519,25 +524,36 @@ + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4, + fail); +- c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout, +- &mck_characteristics, tmpclkmux); ++ c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4, ++ &mck_layout, &mck_characteristics, ++ tmpclkmux); ++ if (IS_ERR(c)) { ++ ret = PTR_ERR(c); ++ goto fail; ++ } ++ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c); ++ ++ /* Register MCK div clock. */ ++ c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV], ++ clk_names[ID_MCK_PRES], ++ &mck_layout, &mck_characteristics); + if (IS_ERR(c)) { + ret = PTR_ERR(c); + goto fail; + } +- clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c); ++ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c); + + /* Register programmable clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; +- p[3] = clk_names[ID_MCK]; ++ p[3] = clk_names[ID_MCK_DIV]; + p[4] = clk_names[ID_PLL_A_DIV]; + p[5] = clk_names[ID_PLL_U_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); +- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); ++ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); + for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) { +@@ -572,7 +588,7 @@ + for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { + c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout, + sam9x60_periphck[i].n, +- clk_names[ID_MCK], ++ clk_names[ID_MCK_DIV], + sam9x60_periphck[i].id, + &r); + if (IS_ERR(c)) { +@@ -587,7 +603,7 @@ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; +- p[3] = clk_names[ID_MCK]; ++ p[3] = clk_names[ID_MCK_DIV]; + p[4] = clk_names[ID_PLL_A_DIV]; + p[5] = clk_names[ID_PLL_U_DIV]; + m[0] = 0; +@@ -599,7 +615,7 @@ + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); +- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); ++ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); + for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { +diff -ruN u-boot-2021.10/drivers/clk/at91/sama7g5.c u-boot/drivers/clk/at91/sama7g5.c +--- u-boot-2021.10/drivers/clk/at91/sama7g5.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/at91/sama7g5.c 2021-11-01 17:10:14.259592668 +0100 +@@ -44,7 +44,8 @@ + * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier + * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier + +- * @ID_MCK0: MCK0 clock identifier ++ * @ID_MCK0_PRES: MCK0 PRES clock identifier ++ * @ID_MCK0_DIV: MCK0 DIV clock identifier + * @ID_MCK1: MCK1 clock identifier + * @ID_MCK2: MCK2 clock identifier + * @ID_MCK3: MCK3 clock identifier +@@ -95,7 +96,7 @@ + ID_PLL_ETH_FRAC = 20, + ID_PLL_ETH_DIV = 21, + +- ID_MCK0 = 22, ++ ID_MCK0_DIV = 22, + ID_MCK1 = 23, + ID_MCK2 = 24, + ID_MCK3 = 25, +@@ -121,6 +122,8 @@ + ID_PCK6 = 42, + ID_PCK7 = 43, + ++ ID_MCK0_PRES = 44, ++ + ID_MAX, + }; + +@@ -147,7 +150,8 @@ + [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", + [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", + [ID_PLL_ETH_DIV] = "ethpll_divpmcck", +- [ID_MCK0] = "mck0", ++ [ID_MCK0_DIV] = "mck0_div", ++ [ID_MCK0_PRES] = "mck0_pres", + }; + + /* Fractional PLL output range. */ +@@ -504,7 +508,7 @@ + struct clk_range r; + u8 id; + } sama7g5_periphck[] = { +- { .n = "pioA_clk", .p = "mck0", .id = 11, }, ++ { .n = "pioA_clk", .p = "mck0_div", .id = 11, }, + { .n = "sfr_clk", .p = "mck1", .id = 19, }, + { .n = "hsmc_clk", .p = "mck1", .id = 21, }, + { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, +@@ -514,7 +518,7 @@ + { .n = "aes_clk", .p = "mck1", .id = 27, }, + { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, + { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, +- { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, ++ { .n = "cpkcc_clk", .p = "mck0_div", .id = 32, }, + { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, }, + { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, }, + { .n = "eic_clk", .p = "mck1", .id = 37, }, +@@ -1210,7 +1214,7 @@ + sama7g5_plls[i].c)); + } + +- /* Register MCK0 clock. */ ++ /* Register MCK0_PRES clock. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_MAINCK]; + p[2] = clk_names[ID_PLL_CPU_DIV]; +@@ -1221,15 +1225,19 @@ + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); +- clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0), +- at91_clk_register_master(base, clk_names[ID_MCK0], p, ++ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), ++ at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p, + 4, &mck0_layout, &mck0_characteristics, tmpclkmux)); + ++ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), ++ at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], ++ clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics)); ++ + /* Register MCK1-4 clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; +- p[3] = clk_names[ID_MCK0]; ++ p[3] = clk_names[ID_MCK0_DIV]; + m[0] = 0; + m[1] = 1; + m[2] = 2; +@@ -1237,7 +1245,7 @@ + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); +- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); ++ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { + for (j = 0; j < sama7g5_mckx[i].ep_count; j++) { + p[4 + j] = sama7g5_mckx[i].ep[j]; +@@ -1267,7 +1275,7 @@ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; +- p[3] = clk_names[ID_MCK0]; ++ p[3] = clk_names[ID_MCK0_DIV]; + p[4] = clk_names[ID_PLL_SYS_DIV]; + p[5] = clk_names[ID_PLL_DDR_DIV]; + p[6] = clk_names[ID_PLL_IMG_DIV]; +@@ -1277,7 +1285,7 @@ + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); +- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); ++ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV); + cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV); +@@ -1315,7 +1323,7 @@ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; +- p[3] = clk_names[ID_MCK0]; ++ p[3] = clk_names[ID_MCK0_DIV]; + m[0] = 0; + m[1] = 1; + m[2] = 2; +@@ -1323,7 +1331,7 @@ + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); +- cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); ++ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { + for (j = 0; j < sama7g5_gck[i].ep_count; j++) { + p[4 + j] = sama7g5_gck[i].ep[j]; +diff -ruN u-boot-2021.10/drivers/clk/clk_fixed_factor.c u-boot/drivers/clk/clk_fixed_factor.c +--- u-boot-2021.10/drivers/clk/clk_fixed_factor.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/clk_fixed_factor.c 2021-11-01 17:10:14.259592668 +0100 +@@ -40,17 +40,17 @@ + + static int clk_fixed_factor_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- int err; +- struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ int err; ++ struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); + +- err = clk_get_by_index(dev, 0, &ff->parent); +- if (err) +- return err; ++ err = clk_get_by_index(dev, 0, &ff->parent); ++ if (err) ++ return err; + +- ff->div = dev_read_u32_default(dev, "clock-div", 1); +- ff->mult = dev_read_u32_default(dev, "clock-mult", 1); +-#endif ++ ff->div = dev_read_u32_default(dev, "clock-div", 1); ++ ff->mult = dev_read_u32_default(dev, "clock-mult", 1); ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/clk/clk_fixed_rate.c u-boot/drivers/clk/clk_fixed_rate.c +--- u-boot-2021.10/drivers/clk/clk_fixed_rate.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/clk_fixed_rate.c 2021-11-01 17:10:14.259592668 +0100 +@@ -26,15 +26,17 @@ + const struct clk_ops clk_fixed_rate_ops = { + .get_rate = clk_fixed_rate_get_rate, + .enable = dummy_enable, ++ .disable = dummy_enable, + }; + + void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, + struct clk_fixed_rate *plat) + { + struct clk *clk = &plat->clk; +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0); +-#endif ++ if (CONFIG_IS_ENABLED(OF_REAL)) ++ plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", ++ 0); ++ + /* Make fixed rate clock accessible from higher level struct clk */ + /* FIXME: This is not allowed */ + dev_set_uclass_priv(dev, clk); +diff -ruN u-boot-2021.10/drivers/clk/clk_kendryte.c u-boot/drivers/clk/clk_kendryte.c +--- u-boot-2021.10/drivers/clk/clk_kendryte.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/clk_kendryte.c 2021-11-01 17:10:14.259592668 +0100 +@@ -709,6 +709,10 @@ + * Whether we swapped r and od while enforcing frequency limits + */ + bool swapped = false; ++ /* ++ * Whether the intermediate frequencies are out-of-spec ++ */ ++ bool out_of_spec; + u64 last_od = od; + u64 last_r = r; + +@@ -767,76 +771,95 @@ + * aren't in spec, try swapping r and od. If everything is + * in-spec, calculate the relative error. + */ +- while (true) { ++again: ++ out_of_spec = false; ++ if (r > max_r) { ++ out_of_spec = true; ++ } else { + /* +- * Whether the intermediate frequencies are out-of-spec ++ * There is no way to only divide once; we need ++ * to examine the frequency with and without the ++ * effect of od. + */ +- bool out_of_spec = false; ++ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); + +- if (r > max_r) { ++ if (vco > 1750000000 || vco < 340000000) + out_of_spec = true; +- } else { +- /* +- * There is no way to only divide once; we need +- * to examine the frequency with and without the +- * effect of od. +- */ +- u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); ++ } ++ ++ if (out_of_spec) { ++ u64 new_r, new_od; ++ ++ if (!swapped) { ++ u64 tmp = r; + +- if (vco > 1750000000 || vco < 340000000) +- out_of_spec = true; ++ r = od; ++ od = tmp; ++ swapped = true; ++ goto again; ++ } ++ ++ /* ++ * Try looking ahead to see if there are additional ++ * factors for the same product. ++ */ ++ if (i + 1 < ARRAY_SIZE(factors)) { ++ i++; ++ new_r = UNPACK_R(factors[i]); ++ new_od = UNPACK_OD(factors[i]); ++ if (r * od == new_r * new_od) { ++ r = new_r; ++ od = new_od; ++ swapped = false; ++ goto again; ++ } ++ i--; + } + +- if (out_of_spec) { +- if (!swapped) { +- u64 tmp = r; +- +- r = od; +- od = tmp; +- swapped = true; +- continue; +- } else { +- /* +- * Try looking ahead to see if there are +- * additional factors for the same +- * product. +- */ +- if (i + 1 < ARRAY_SIZE(factors)) { +- u64 new_r, new_od; +- +- i++; +- new_r = UNPACK_R(factors[i]); +- new_od = UNPACK_OD(factors[i]); +- if (r * od == new_r * new_od) { +- r = new_r; +- od = new_od; +- swapped = false; +- continue; +- } +- i--; ++ /* ++ * Try looking back to see if there is a worse ratio ++ * that we could try anyway ++ */ ++ while (i > 0) { ++ i--; ++ new_r = UNPACK_R(factors[i]); ++ new_od = UNPACK_OD(factors[i]); ++ /* ++ * Don't loop over factors for the same product ++ * to avoid getting stuck because of the above ++ * clause ++ */ ++ if (r * od != new_r * new_od) { ++ if (new_r * new_od > last_r * last_od) { ++ r = new_r; ++ od = new_od; ++ swapped = false; ++ goto again; + } + break; + } + } + +- error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); +- /* The lower 16 bits are spurious */ +- error = abs((error - BIT(32))) >> 16; +- +- if (error < best_error) { +- best->r = r; +- best->f = f; +- best->od = od; +- best_error = error; +- } +- break; ++ /* We ran out of things to try */ ++ continue; ++ } ++ ++ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); ++ /* The lower 16 bits are spurious */ ++ error = abs((error - BIT(32))) >> 16; ++ ++ if (error < best_error) { ++ best->r = r; ++ best->f = f; ++ best->od = od; ++ best_error = error; + } + } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0); + ++ log_debug("best error %lld\n", best_error); + if (best_error == S64_MAX) + return -EINVAL; + +- log_debug("best error %lld\n", best_error); + return 0; + } + +@@ -849,9 +872,6 @@ + u32 reg; + ulong calc_rate; + +- if (rate_in < 0) +- return rate_in; +- + err = k210_pll_calc_config(rate, rate_in, &config); + if (err) + return err; +@@ -895,7 +915,7 @@ + u64 r, f, od; + u32 reg = readl(priv->base + k210_plls[id].off); + +- if (rate_in < 0 || (reg & K210_PLL_BYPASS)) ++ if (reg & K210_PLL_BYPASS) + return rate_in; + + if (!(reg & K210_PLL_PWRD)) +@@ -1029,6 +1049,8 @@ + + parent = k210_clk_get_parent(priv, id); + parent_rate = do_k210_clk_get_rate(priv, parent); ++ if (IS_ERR_VALUE(parent_rate)) ++ return parent_rate; + + if (k210_clks[id].flags & K210_CLKF_PLL) + return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate); +@@ -1099,6 +1121,8 @@ + + parent = k210_clk_get_parent(priv, clk->id); + rate_in = do_k210_clk_get_rate(priv, parent); ++ if (IS_ERR_VALUE(rate_in)) ++ return rate_in; + + log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in); + +diff -ruN u-boot-2021.10/drivers/clk/clk-uclass.c u-boot/drivers/clk/clk-uclass.c +--- u-boot-2021.10/drivers/clk/clk-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/clk-uclass.c 2021-11-01 17:10:14.259592668 +0100 +@@ -35,10 +35,9 @@ + return (struct clk *)dev_get_uclass_priv(dev); + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) +-# if CONFIG_IS_ENABLED(OF_PLATDATA) +-int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, +- struct clk *clk) ++#if CONFIG_IS_ENABLED(OF_PLATDATA) ++int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, ++ struct clk *clk) + { + int ret; + +@@ -49,7 +48,9 @@ + + return 0; + } +-# else ++#endif ++ ++#if CONFIG_IS_ENABLED(OF_REAL) + static int clk_of_xlate_default(struct clk *clk, + struct ofnode_phandle_args *args) + { +@@ -412,7 +413,7 @@ + + return clk_get_by_index(dev, index, clk); + } +-# endif /* OF_PLATDATA */ ++#endif /* OF_REAL */ + + int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) + { +@@ -465,8 +466,6 @@ + return 0; + } + +-#endif /* OF_CONTROL */ +- + int clk_request(struct udevice *dev, struct clk *clk) + { + const struct clk_ops *ops; +diff -ruN u-boot-2021.10/drivers/clk/clk_versal.c u-boot/drivers/clk/clk_versal.c +--- u-boot-2021.10/drivers/clk/clk_versal.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/clk_versal.c 2021-11-01 17:10:14.262925819 +0100 +@@ -725,7 +725,10 @@ + + clk_id = priv->clk[clk->id].clk_id; + +- return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); ++ if (versal_clock_gate(clk_id)) ++ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); ++ ++ return 0; + } + + static struct clk_ops versal_clk_ops = { +diff -ruN u-boot-2021.10/drivers/clk/imx/clk-pllv3.c u-boot/drivers/clk/imx/clk-pllv3.c +--- u-boot-2021.10/drivers/clk/imx/clk-pllv3.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/imx/clk-pllv3.c 2021-11-01 17:10:14.262925819 +0100 +@@ -160,7 +160,7 @@ + } + + static const struct clk_ops clk_pllv3_sys_ops = { +- .enable = clk_pllv3_generic_enable, ++ .enable = clk_pllv3_generic_enable, + .disable = clk_pllv3_generic_disable, + .get_rate = clk_pllv3_sys_get_rate, + .set_rate = clk_pllv3_sys_set_rate, +diff -ruN u-boot-2021.10/drivers/clk/Makefile u-boot/drivers/clk/Makefile +--- u-boot-2021.10/drivers/clk/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/Makefile 2021-11-01 17:10:14.256259517 +0100 +@@ -36,9 +36,9 @@ + obj-$(CONFIG_CLK_RENESAS) += renesas/ + obj-$(CONFIG_CLK_SCMI) += clk_scmi.o + obj-$(CONFIG_CLK_SIFIVE) += sifive/ +-obj-$(CONFIG_ARCH_SUNXI) += sunxi/ + obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o + obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o ++obj-$(CONFIG_CLK_SUNXI) += sunxi/ + obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ + obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o + obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o +diff -ruN u-boot-2021.10/drivers/clk/meson/Makefile u-boot/drivers/clk/meson/Makefile +--- u-boot-2021.10/drivers/clk/meson/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/meson/Makefile 2021-11-01 17:10:14.266258970 +0100 +@@ -7,4 +7,3 @@ + obj-$(CONFIG_CLK_MESON_AXG) += axg.o + obj-$(CONFIG_CLK_MESON_G12A) += g12a.o + obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o +- +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_pll.c u-boot/drivers/clk/rockchip/clk_pll.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_pll.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_pll.c 2021-11-01 17:10:14.269592122 +0100 +@@ -359,4 +359,3 @@ + else + return ps; + } +- +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_px30.c u-boot/drivers/clk/rockchip/clk_px30.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_px30.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_px30.c 2021-11-01 17:10:14.269592122 +0100 +@@ -1367,7 +1367,7 @@ + return ret; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) + { + struct px30_clk_priv *priv = dev_get_priv(clk->dev); +@@ -1418,7 +1418,7 @@ + static struct clk_ops px30_clk_ops = { + .get_rate = px30_clk_get_rate, + .set_rate = px30_clk_set_rate, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .set_parent = px30_clk_set_parent, + #endif + .enable = px30_clk_enable, +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_rk3188.c u-boot/drivers/clk/rockchip/clk_rk3188.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_rk3188.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_rk3188.c 2021-11-01 17:10:14.269592122 +0100 +@@ -540,11 +540,11 @@ + + static int rk3188_clk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3188_clk_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3188_clk_priv *priv = dev_get_priv(dev); + +- priv->cru = dev_read_addr_ptr(dev); +-#endif ++ priv->cru = dev_read_addr_ptr(dev); ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_rk3288.c u-boot/drivers/clk/rockchip/clk_rk3288.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_rk3288.c 2021-11-01 17:10:14.269592122 +0100 +@@ -950,18 +950,18 @@ + static struct clk_ops rk3288_clk_ops = { + .get_rate = rk3288_clk_get_rate, + .set_rate = rk3288_clk_set_rate, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .set_parent = rk3288_clk_set_parent, + #endif + }; + + static int rk3288_clk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3288_clk_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3288_clk_priv *priv = dev_get_priv(dev); + +- priv->cru = dev_read_addr_ptr(dev); +-#endif ++ priv->cru = dev_read_addr_ptr(dev); ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_rk3308.c u-boot/drivers/clk/rockchip/clk_rk3308.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_rk3308.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_rk3308.c 2021-11-01 17:10:14.269592122 +0100 +@@ -939,7 +939,7 @@ + return ret; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent) + { + struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); +@@ -976,7 +976,7 @@ + static struct clk_ops rk3308_clk_ops = { + .get_rate = rk3308_clk_get_rate, + .set_rate = rk3308_clk_set_rate, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .set_parent = rk3308_clk_set_parent, + #endif + }; +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_rk3368.c u-boot/drivers/clk/rockchip/clk_rk3368.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_rk3368.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_rk3368.c 2021-11-01 17:10:14.272925272 +0100 +@@ -158,7 +158,7 @@ + } + #endif + +-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) ++#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) + static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) + { + u32 div, con, con_id, rate; +@@ -470,7 +470,7 @@ + case SCLK_SPI0 ... SCLK_SPI2: + rate = rk3368_spi_get_clk(priv->cru, clk->id); + break; +-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) ++#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) + case HCLK_SDMMC: + case HCLK_EMMC: + rate = rk3368_mmc_get_clk(priv->cru, clk->id); +@@ -501,7 +501,7 @@ + ret = rk3368_ddr_set_clk(priv->cru, rate); + break; + #endif +-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) ++#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) + case HCLK_SDMMC: + case HCLK_EMMC: + ret = rk3368_mmc_set_clk(clk, rate); +@@ -574,7 +574,7 @@ + static struct clk_ops rk3368_clk_ops = { + .get_rate = rk3368_clk_get_rate, + .set_rate = rk3368_clk_set_rate, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .set_parent = rk3368_clk_set_parent, + #endif + }; +@@ -596,11 +596,11 @@ + + static int rk3368_clk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3368_clk_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3368_clk_priv *priv = dev_get_priv(dev); + +- priv->cru = dev_read_addr_ptr(dev); +-#endif ++ priv->cru = dev_read_addr_ptr(dev); ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/clk/rockchip/clk_rk3399.c u-boot/drivers/clk/rockchip/clk_rk3399.c +--- u-boot-2021.10/drivers/clk/rockchip/clk_rk3399.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/rockchip/clk_rk3399.c 2021-11-01 17:10:14.272925272 +0100 +@@ -1289,7 +1289,7 @@ + static struct clk_ops rk3399_clk_ops = { + .get_rate = rk3399_clk_get_rate, + .set_rate = rk3399_clk_set_rate, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .set_parent = rk3399_clk_set_parent, + #endif + .enable = rk3399_clk_enable, +@@ -1402,11 +1402,12 @@ + + static int rk3399_clk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3399_clk_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3399_clk_priv *priv = dev_get_priv(dev); ++ ++ priv->cru = dev_read_addr_ptr(dev); ++ } + +- priv->cru = dev_read_addr_ptr(dev); +-#endif + return 0; + } + +@@ -1614,11 +1615,12 @@ + + static int rk3399_pmuclk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); ++ ++ priv->pmucru = dev_read_addr_ptr(dev); ++ } + +- priv->pmucru = dev_read_addr_ptr(dev); +-#endif + return 0; + } + +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a10.c u-boot/drivers/clk/sunxi/clk_a10.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a10.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a10.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun4i-a10-ccu.h> + #include <dt-bindings/reset/sun4i-a10-ccu.h> + #include <linux/bitops.h> +@@ -31,6 +31,11 @@ + + [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), + ++ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), ++ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)), ++ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)), + [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a10s.c u-boot/drivers/clk/sunxi/clk_a10s.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a10s.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a10s.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun5i-ccu.h> + #include <dt-bindings/reset/sun5i-ccu.h> + #include <linux/bitops.h> +@@ -25,6 +25,9 @@ + [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), + [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), + ++ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), + [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a23.c u-boot/drivers/clk/sunxi/clk_a23.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a23.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a23.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> + #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> + #include <linux/bitops.h> +@@ -23,6 +23,9 @@ + [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), + [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -53,6 +56,9 @@ + [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), + [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a31.c u-boot/drivers/clk/sunxi/clk_a31.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a31.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a31.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun6i-a31-ccu.h> + #include <dt-bindings/reset/sun6i-a31-ccu.h> + #include <linux/bitops.h> +@@ -30,6 +30,10 @@ + [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), + [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), + ++ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), ++ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), + [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), +@@ -71,6 +75,10 @@ + [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), + [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), + ++ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), ++ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), + [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), + [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), + [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a31_r.c u-boot/drivers/clk/sunxi/clk_a31_r.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a31_r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/clk/sunxi/clk_a31_r.c 2021-11-01 17:10:14.272925272 +0100 +@@ -0,0 +1,59 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) Samuel Holland <samuel@sholland.org> ++ */ ++ ++#include <clk-uclass.h> ++#include <dm.h> ++#include <clk/sunxi.h> ++#include <dt-bindings/clock/sun8i-r-ccu.h> ++#include <dt-bindings/reset/sun8i-r-ccu.h> ++#include <linux/bitops.h> ++ ++static struct ccu_clk_gate a31_r_gates[] = { ++ [CLK_APB0_PIO] = GATE(0x028, BIT(0)), ++ [CLK_APB0_IR] = GATE(0x028, BIT(1)), ++ [CLK_APB0_TIMER] = GATE(0x028, BIT(2)), ++ [CLK_APB0_RSB] = GATE(0x028, BIT(3)), ++ [CLK_APB0_UART] = GATE(0x028, BIT(4)), ++ [CLK_APB0_I2C] = GATE(0x028, BIT(6)), ++ [CLK_APB0_TWD] = GATE(0x028, BIT(7)), ++}; ++ ++static struct ccu_reset a31_r_resets[] = { ++ [RST_APB0_IR] = RESET(0x0b0, BIT(1)), ++ [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)), ++ [RST_APB0_RSB] = RESET(0x0b0, BIT(3)), ++ [RST_APB0_UART] = RESET(0x0b0, BIT(4)), ++ [RST_APB0_I2C] = RESET(0x0b0, BIT(6)), ++}; ++ ++static const struct ccu_desc a31_r_ccu_desc = { ++ .gates = a31_r_gates, ++ .resets = a31_r_resets, ++}; ++ ++static int a31_r_clk_bind(struct udevice *dev) ++{ ++ return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets)); ++} ++ ++static const struct udevice_id a31_r_clk_ids[] = { ++ { .compatible = "allwinner,sun8i-a83t-r-ccu", ++ .data = (ulong)&a31_r_ccu_desc }, ++ { .compatible = "allwinner,sun8i-h3-r-ccu", ++ .data = (ulong)&a31_r_ccu_desc }, ++ { .compatible = "allwinner,sun50i-a64-r-ccu", ++ .data = (ulong)&a31_r_ccu_desc }, ++ { } ++}; ++ ++U_BOOT_DRIVER(clk_sun6i_a31_r) = { ++ .name = "sun6i_a31_r_ccu", ++ .id = UCLASS_CLK, ++ .of_match = a31_r_clk_ids, ++ .priv_auto = sizeof(struct ccu_priv), ++ .ops = &sunxi_clk_ops, ++ .probe = sunxi_clk_probe, ++ .bind = a31_r_clk_bind, ++}; +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a64.c u-boot/drivers/clk/sunxi/clk_a64.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a64.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a64.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun50i-a64-ccu.h> + #include <dt-bindings/reset/sun50i-a64-ccu.h> + #include <linux/bitops.h> +@@ -26,6 +26,9 @@ + [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), + [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -60,6 +63,9 @@ + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), + [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a80.c u-boot/drivers/clk/sunxi/clk_a80.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a80.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a80.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun9i-a80-ccu.h> + #include <dt-bindings/reset/sun9i-a80-ccu.h> + #include <linux/bitops.h> +@@ -25,6 +25,11 @@ + [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), + [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), + ++ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)), ++ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)), ++ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)), + [CLK_BUS_UART0] = GATE(0x594, BIT(16)), + [CLK_BUS_UART1] = GATE(0x594, BIT(17)), + [CLK_BUS_UART2] = GATE(0x594, BIT(18)), +@@ -40,6 +45,11 @@ + [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)), + [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)), + ++ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)), ++ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)), ++ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)), + [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), + [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), + [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_a83t.c u-boot/drivers/clk/sunxi/clk_a83t.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_a83t.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_a83t.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun8i-a83t-ccu.h> + #include <dt-bindings/reset/sun8i-a83t-ccu.h> + #include <linux/bitops.h> +@@ -25,6 +25,9 @@ + [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), + [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -57,6 +60,9 @@ + [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_d1.c u-boot/drivers/clk/sunxi/clk_d1.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_d1.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/clk/sunxi/clk_d1.c 2021-11-01 17:10:14.272925272 +0100 +@@ -0,0 +1,101 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#include <common.h> ++#include <clk-uclass.h> ++#include <dm.h> ++#include <errno.h> ++#include <clk/sunxi.h> ++#include <dt-bindings/clock/sun20i-d1-ccu.h> ++#include <dt-bindings/reset/sun20i-d1-ccu.h> ++#include <linux/bitops.h> ++ ++static struct ccu_clk_gate d1_gates[] = { ++ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), ++ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), ++ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), ++ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), ++ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), ++ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), ++ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), ++ [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), ++ [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), ++ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), ++ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), ++ [CLK_SPI0] = GATE(0x940, BIT(31)), ++ [CLK_SPI1] = GATE(0x944, BIT(31)), ++ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), ++ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), ++ ++ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)), ++ ++ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), ++ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)), ++ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), ++ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)), ++ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), ++ [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)), ++ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), ++ [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)), ++ ++ [CLK_RISCV] = GATE(0xd04, BIT(31)), ++}; ++ ++static struct ccu_reset d1_resets[] = { ++ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), ++ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), ++ [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), ++ [RST_BUS_UART0] = RESET(0x90c, BIT(16)), ++ [RST_BUS_UART1] = RESET(0x90c, BIT(17)), ++ [RST_BUS_UART2] = RESET(0x90c, BIT(18)), ++ [RST_BUS_UART3] = RESET(0x90c, BIT(19)), ++ [RST_BUS_UART4] = RESET(0x90c, BIT(20)), ++ [RST_BUS_UART5] = RESET(0x90c, BIT(21)), ++ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), ++ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), ++ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), ++ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), ++ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), ++ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), ++ ++ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)), ++ ++ [RST_USB_PHY0] = RESET(0xa70, BIT(30)), ++ [RST_USB_PHY1] = RESET(0xa74, BIT(30)), ++ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), ++ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)), ++ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), ++ [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)), ++ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), ++ [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)), ++}; ++ ++static const struct ccu_desc d1_ccu_desc = { ++ .gates = d1_gates, ++ .resets = d1_resets, ++}; ++ ++static int d1_clk_bind(struct udevice *dev) ++{ ++ return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets)); ++} ++ ++static const struct udevice_id d1_ccu_ids[] = { ++ { .compatible = "allwinner,sun20i-d1-ccu", ++ .data = (ulong)&d1_ccu_desc }, ++ { } ++}; ++ ++U_BOOT_DRIVER(clk_sun50i_d1) = { ++ .name = "sun50i_d1_ccu", ++ .id = UCLASS_CLK, ++ .of_match = d1_ccu_ids, ++ .priv_auto = sizeof(struct ccu_priv), ++ .ops = &sunxi_clk_ops, ++ .probe = sunxi_clk_probe, ++ .bind = d1_clk_bind, ++}; +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_h3.c u-boot/drivers/clk/sunxi/clk_h3.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_h3.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_h3.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun8i-h3-ccu.h> + #include <dt-bindings/reset/sun8i-h3-ccu.h> + #include <linux/bitops.h> +@@ -30,6 +30,9 @@ + [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), + [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -74,6 +77,9 @@ + + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_h616.c u-boot/drivers/clk/sunxi/clk_h616.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_h616.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_h616.c 2021-11-01 17:10:14.272925272 +0100 +@@ -7,7 +7,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun50i-h616-ccu.h> + #include <dt-bindings/reset/sun50i-h616-ccu.h> + #include <linux/bitops.h> +@@ -24,6 +24,12 @@ + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), + ++ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), ++ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), ++ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)), ++ + [CLK_SPI0] = GATE(0x940, BIT(31)), + [CLK_SPI1] = GATE(0x944, BIT(31)), + +@@ -68,6 +74,12 @@ + [RST_BUS_UART4] = RESET(0x90c, BIT(20)), + [RST_BUS_UART5] = RESET(0x90c, BIT(21)), + ++ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), ++ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), ++ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), ++ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), ++ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)), ++ + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), + +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_h6.c u-boot/drivers/clk/sunxi/clk_h6.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_h6.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_h6.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun50i-h6-ccu.h> + #include <dt-bindings/reset/sun50i-h6-ccu.h> + #include <linux/bitops.h> +@@ -22,6 +22,11 @@ + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), + ++ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), ++ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), ++ + [CLK_SPI0] = GATE(0x940, BIT(31)), + [CLK_SPI1] = GATE(0x944, BIT(31)), + +@@ -57,6 +62,11 @@ + [RST_BUS_UART2] = RESET(0x90c, BIT(18)), + [RST_BUS_UART3] = RESET(0x90c, BIT(19)), + ++ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), ++ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), ++ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), ++ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), ++ + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), + +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_h6_r.c u-boot/drivers/clk/sunxi/clk_h6_r.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_h6_r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/clk/sunxi/clk_h6_r.c 2021-11-01 17:10:14.272925272 +0100 +@@ -0,0 +1,61 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) Samuel Holland <samuel@sholland.org> ++ */ ++ ++#include <clk-uclass.h> ++#include <dm.h> ++#include <clk/sunxi.h> ++#include <dt-bindings/clock/sun50i-h6-r-ccu.h> ++#include <dt-bindings/reset/sun50i-h6-r-ccu.h> ++#include <linux/bitops.h> ++ ++static struct ccu_clk_gate h6_r_gates[] = { ++ [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)), ++ [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)), ++ [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)), ++ [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)), ++ [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)), ++ [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)), ++ [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)), ++ [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)), ++}; ++ ++static struct ccu_reset h6_r_resets[] = { ++ [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)), ++ [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)), ++ [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)), ++ [RST_R_APB2_UART] = RESET(0x18c, BIT(16)), ++ [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)), ++ [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)), ++ [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)), ++ [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)), ++}; ++ ++static const struct ccu_desc h6_r_ccu_desc = { ++ .gates = h6_r_gates, ++ .resets = h6_r_resets, ++}; ++ ++static int h6_r_clk_bind(struct udevice *dev) ++{ ++ return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets)); ++} ++ ++static const struct udevice_id h6_r_clk_ids[] = { ++ { .compatible = "allwinner,sun50i-h6-r-ccu", ++ .data = (ulong)&h6_r_ccu_desc }, ++ { .compatible = "allwinner,sun50i-h616-r-ccu", ++ .data = (ulong)&h6_r_ccu_desc }, ++ { } ++}; ++ ++U_BOOT_DRIVER(clk_sun6i_h6_r) = { ++ .name = "sun6i_h6_r_ccu", ++ .id = UCLASS_CLK, ++ .of_match = h6_r_clk_ids, ++ .priv_auto = sizeof(struct ccu_priv), ++ .ops = &sunxi_clk_ops, ++ .probe = sunxi_clk_probe, ++ .bind = h6_r_clk_bind, ++}; +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_r40.c u-boot/drivers/clk/sunxi/clk_r40.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_r40.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_r40.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun8i-r40-ccu.h> + #include <dt-bindings/reset/sun8i-r40-ccu.h> + #include <linux/bitops.h> +@@ -32,6 +32,11 @@ + + [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), ++ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), ++ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)), ++ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -77,6 +82,11 @@ + + [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), ++ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), ++ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)), ++ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_sunxi.c u-boot/drivers/clk/sunxi/clk_sunxi.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_sunxi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_sunxi.c 2021-11-01 17:10:14.272925272 +0100 +@@ -11,7 +11,7 @@ + #include <log.h> + #include <reset.h> + #include <asm/io.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <linux/bitops.h> + #include <linux/log2.h> + +diff -ruN u-boot-2021.10/drivers/clk/sunxi/clk_v3s.c u-boot/drivers/clk/sunxi/clk_v3s.c +--- u-boot-2021.10/drivers/clk/sunxi/clk_v3s.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/clk_v3s.c 2021-11-01 17:10:14.272925272 +0100 +@@ -8,7 +8,7 @@ + #include <clk-uclass.h> + #include <dm.h> + #include <errno.h> +-#include <asm/arch/ccu.h> ++#include <clk/sunxi.h> + #include <dt-bindings/clock/sun8i-v3s-ccu.h> + #include <dt-bindings/reset/sun8i-v3s-ccu.h> + #include <linux/bitops.h> +@@ -20,6 +20,8 @@ + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + ++ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), ++ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), +@@ -38,6 +40,8 @@ + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + ++ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), ++ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), +diff -ruN u-boot-2021.10/drivers/clk/sunxi/Kconfig u-boot/drivers/clk/sunxi/Kconfig +--- u-boot-2021.10/drivers/clk/sunxi/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/Kconfig 2021-11-01 17:10:14.272925272 +0100 +@@ -1,7 +1,8 @@ + config CLK_SUNXI + bool "Clock support for Allwinner SoCs" +- depends on CLK && ARCH_SUNXI ++ depends on CLK && (ARCH_SUNXI || TARGET_SUNXI) + select DM_RESET ++ select SPL_DM_RESET if SPL_CLK + default y + help + This enables support for common clock driver API on Allwinner +@@ -30,6 +31,13 @@ + This enables common clock driver support for platforms based + on Allwinner A31/A31s SoC. + ++config CLK_SUN6I_A31_R ++ bool "Clock driver for Allwinner A31 generation PRCM" ++ default SUNXI_GEN_SUN6I ++ help ++ This enables common clock driver support for the PRCM ++ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs. ++ + config CLK_SUN8I_A23 + bool "Clock driver for Allwinner A23/A33" + default MACH_SUN8I_A23 || MACH_SUN8I_A33 +@@ -72,6 +80,13 @@ + This enables common clock driver support for platforms based + on Allwinner H3/H5 SoC. + ++config CLK_SUN20I_D1 ++ bool "Clock driver for Allwinner D1" ++ default MACH_SUN20I ++ help ++ This enables common clock driver support for platforms based ++ on Allwinner D1 SoC. ++ + config CLK_SUN50I_H6 + bool "Clock driver for Allwinner H6" + default MACH_SUN50I_H6 +@@ -79,6 +94,13 @@ + This enables common clock driver support for platforms based + on Allwinner H6 SoC. + ++config CLK_SUN50I_H6_R ++ bool "Clock driver for Allwinner H6 generation PRCM" ++ default SUN50I_GEN_H6 ++ help ++ This enables common clock driver support for the PRCM ++ in Allwinner H6/H616 SoCs. ++ + config CLK_SUN50I_H616 + bool "Clock driver for Allwinner H616" + default MACH_SUN50I_H616 +diff -ruN u-boot-2021.10/drivers/clk/sunxi/Makefile u-boot/drivers/clk/sunxi/Makefile +--- u-boot-2021.10/drivers/clk/sunxi/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/clk/sunxi/Makefile 2021-11-01 17:10:14.272925272 +0100 +@@ -11,12 +11,15 @@ + obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o + obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o + obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o ++obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o + obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o + obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o + obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o + obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o + obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o + obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o ++obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o + obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o ++obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o + obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o + obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o +diff -ruN u-boot-2021.10/drivers/core/device.c u-boot/drivers/core/device.c +--- u-boot-2021.10/drivers/core/device.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/device.c 2021-11-01 17:10:14.276258423 +0100 +@@ -670,7 +670,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /** + * device_find_by_ofnode() - Return device associated with given ofnode + * +@@ -1074,7 +1074,7 @@ + dev->uclass_plat_ = uclass_plat; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + bool device_is_compatible(const struct udevice *dev, const char *compat) + { + return ofnode_device_is_compatible(dev_ofnode(dev), compat); +diff -ruN u-boot-2021.10/drivers/core/fdtaddr.c u-boot/drivers/core/fdtaddr.c +--- u-boot-2021.10/drivers/core/fdtaddr.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/fdtaddr.c 2021-11-01 17:10:14.276258423 +0100 +@@ -20,7 +20,7 @@ + + fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) + { +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + fdt_addr_t addr; + + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { +diff -ruN u-boot-2021.10/drivers/core/Kconfig u-boot/drivers/core/Kconfig +--- u-boot-2021.10/drivers/core/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/Kconfig 2021-11-01 17:10:14.272925272 +0100 +@@ -80,7 +80,6 @@ + config SPL_DM_DEVICE_REMOVE + bool "Support device removal in SPL" + depends on SPL_DM +- default n + help + We can save some code space by dropping support for removing a + device. This is not normally required in SPL, so by default this +@@ -107,7 +106,6 @@ + config SPL_DM_SEQ_ALIAS + bool "Support numbered aliases in device tree in SPL" + depends on SPL_DM +- default n + help + Most boards will have a '/aliases' node containing the path to + numbered devices (e.g. serial0 = &serial0). This feature can be +@@ -132,7 +130,6 @@ + config DM_DMA + bool "Support per-device DMA constraints" + depends on DM +- default n + help + Enable this to extract per-device DMA constraints, only supported on + device-tree systems for now. This is needed in order translate +@@ -274,7 +271,6 @@ + config SPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address in SPL" + depends on SPL_DM && SPL_OF_CONTROL +- default n + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary +diff -ruN u-boot-2021.10/drivers/core/lists.c u-boot/drivers/core/lists.c +--- u-boot-2021.10/drivers/core/lists.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/lists.c 2021-11-01 17:10:14.276258423 +0100 +@@ -154,7 +154,7 @@ + return ret; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /** + * driver_check_compatible() - Check if a driver matches a compatible string + * +diff -ruN u-boot-2021.10/drivers/core/ofnode.c u-boot/drivers/core/ofnode.c +--- u-boot-2021.10/drivers/core/ofnode.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/ofnode.c 2021-11-01 17:10:14.276258423 +0100 +@@ -1103,3 +1103,36 @@ + else + return ofnode_write_string(node, "status", "disabled"); + } ++ ++bool ofnode_conf_read_bool(const char *prop_name) ++{ ++ ofnode node; ++ ++ node = ofnode_path("/config"); ++ if (!ofnode_valid(node)) ++ return false; ++ ++ return ofnode_read_bool(node, prop_name); ++} ++ ++int ofnode_conf_read_int(const char *prop_name, int default_val) ++{ ++ ofnode node; ++ ++ node = ofnode_path("/config"); ++ if (!ofnode_valid(node)) ++ return default_val; ++ ++ return ofnode_read_u32_default(node, prop_name, default_val); ++} ++ ++const char *ofnode_conf_read_str(const char *prop_name) ++{ ++ ofnode node; ++ ++ node = ofnode_path("/config"); ++ if (!ofnode_valid(node)) ++ return NULL; ++ ++ return ofnode_read_string(node, prop_name); ++} +diff -ruN u-boot-2021.10/drivers/core/root.c u-boot/drivers/core/root.c +--- u-boot-2021.10/drivers/core/root.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/root.c 2021-11-01 17:10:14.276258423 +0100 +@@ -245,7 +245,7 @@ + return ret; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /** + * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node + * +@@ -372,7 +372,7 @@ + return ret; + } + +- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ++ if (CONFIG_IS_ENABLED(OF_REAL)) { + ret = dm_extended_scan(pre_reloc_only); + if (ret) { + debug("dm_extended_scan() failed: %d\n", ret); +diff -ruN u-boot-2021.10/drivers/core/simple-bus.c u-boot/drivers/core/simple-bus.c +--- u-boot-2021.10/drivers/core/simple-bus.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/simple-bus.c 2021-11-01 17:10:14.276258423 +0100 +@@ -65,7 +65,7 @@ + .per_device_plat_auto = sizeof(struct simple_bus_plat), + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id generic_simple_bus_ids[] = { + { .compatible = "simple-bus" }, + { .compatible = "simple-mfd" }, +diff -ruN u-boot-2021.10/drivers/core/syscon-uclass.c u-boot/drivers/core/syscon-uclass.c +--- u-boot-2021.10/drivers/core/syscon-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/syscon-uclass.c 2021-11-01 17:10:14.276258423 +0100 +@@ -186,7 +186,7 @@ + U_BOOT_DRIVER(generic_syscon) = { + .name = "syscon", + .id = UCLASS_SYSCON, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .of_match = generic_syscon_ids, +diff -ruN u-boot-2021.10/drivers/core/uclass.c u-boot/drivers/core/uclass.c +--- u-boot-2021.10/drivers/core/uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/uclass.c 2021-11-01 17:10:14.276258423 +0100 +@@ -397,7 +397,7 @@ + return ret; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp) + { +diff -ruN u-boot-2021.10/drivers/core/util.c u-boot/drivers/core/util.c +--- u-boot-2021.10/drivers/core/util.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/core/util.c 2021-11-01 17:10:14.276258423 +0100 +@@ -22,7 +22,7 @@ + return count; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int pci_get_devfn(struct udevice *dev) + { + struct fdt_pci_addr addr; +diff -ruN u-boot-2021.10/drivers/cpu/at91_cpu.c u-boot/drivers/cpu/at91_cpu.c +--- u-boot-2021.10/drivers/cpu/at91_cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/cpu/at91_cpu.c 2021-11-01 17:10:14.276258423 +0100 +@@ -70,6 +70,7 @@ + + static const struct udevice_id at91_cpu_ids[] = { + { .compatible = "arm,cortex-a7" }, ++ { .compatible = "arm,arm926ej-s" }, + { /* Sentinel. */ } + }; + +diff -ruN u-boot-2021.10/drivers/cpu/cpu_sandbox.c u-boot/drivers/cpu/cpu_sandbox.c +--- u-boot-2021.10/drivers/cpu/cpu_sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/cpu/cpu_sandbox.c 2021-11-01 17:10:14.276258423 +0100 +@@ -38,7 +38,7 @@ + return 0; + } + +-static const char *cpu_current = "cpu-test1"; ++static const char *cpu_current = "cpu@1"; + + void cpu_sandbox_set_current(const char *name) + { +diff -ruN u-boot-2021.10/drivers/crypto/hash/hash_sw.c u-boot/drivers/crypto/hash/hash_sw.c +--- u-boot-2021.10/drivers/crypto/hash/hash_sw.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/crypto/hash/hash_sw.c 2021-11-01 17:10:14.279591574 +0100 +@@ -0,0 +1,301 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2021 ASPEED Technology Inc. ++ * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> ++ */ ++#include <config.h> ++#include <common.h> ++#include <dm.h> ++#include <log.h> ++#include <malloc.h> ++#include <watchdog.h> ++#include <u-boot/hash.h> ++#include <u-boot/crc.h> ++#include <u-boot/md5.h> ++#include <u-boot/sha1.h> ++#include <u-boot/sha256.h> ++#include <u-boot/sha512.h> ++ ++/* CRC16-CCITT */ ++static void hash_init_crc16_ccitt(void *ctx) ++{ ++ *((uint16_t *)ctx) = 0; ++} ++ ++static void hash_update_crc16_ccitt(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), ibuf, ilen); ++} ++ ++static void hash_finish_crc16_ccitt(void *ctx, void *obuf) ++{ ++ *((uint16_t *)obuf) = *((uint16_t *)ctx); ++} ++ ++/* CRC32 */ ++static void hash_init_crc32(void *ctx) ++{ ++ *((uint32_t *)ctx) = 0; ++} ++ ++static void hash_update_crc32(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), ibuf, ilen); ++} ++ ++static void hash_finish_crc32(void *ctx, void *obuf) ++{ ++ *((uint32_t *)obuf) = *((uint32_t *)ctx); ++} ++ ++/* MD5 */ ++static void hash_init_md5(void *ctx) ++{ ++ MD5Init((struct MD5Context *)ctx); ++} ++ ++static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ MD5Update((struct MD5Context *)ctx, ibuf, ilen); ++} ++ ++static void hash_finish_md5(void *ctx, void *obuf) ++{ ++ MD5Final(obuf, (struct MD5Context *)ctx); ++} ++ ++/* SHA1 */ ++static void hash_init_sha1(void *ctx) ++{ ++ sha1_starts((sha1_context *)ctx); ++} ++ ++static void hash_update_sha1(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ sha1_update((sha1_context *)ctx, ibuf, ilen); ++} ++ ++static void hash_finish_sha1(void *ctx, void *obuf) ++{ ++ sha1_finish((sha1_context *)ctx, obuf); ++} ++ ++/* SHA256 */ ++static void hash_init_sha256(void *ctx) ++{ ++ sha256_starts((sha256_context *)ctx); ++} ++ ++static void hash_update_sha256(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ sha256_update((sha256_context *)ctx, ibuf, ilen); ++} ++ ++static void hash_finish_sha256(void *ctx, void *obuf) ++{ ++ sha256_finish((sha256_context *)ctx, obuf); ++} ++ ++/* SHA384 */ ++static void hash_init_sha384(void *ctx) ++{ ++ sha384_starts((sha512_context *)ctx); ++} ++ ++static void hash_update_sha384(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ sha384_update((sha512_context *)ctx, ibuf, ilen); ++} ++ ++static void hash_finish_sha384(void *ctx, void *obuf) ++{ ++ sha384_finish((sha512_context *)ctx, obuf); ++} ++ ++/* SHA512 */ ++static void hash_init_sha512(void *ctx) ++{ ++ sha512_starts((sha512_context *)ctx); ++} ++ ++static void hash_update_sha512(void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ sha512_update((sha512_context *)ctx, ibuf, ilen); ++} ++ ++static void hash_finish_sha512(void *ctx, void *obuf) ++{ ++ sha512_finish((sha512_context *)ctx, obuf); ++} ++ ++struct sw_hash_ctx { ++ enum HASH_ALGO algo; ++ uint8_t algo_ctx[]; ++}; ++ ++struct sw_hash_impl { ++ void (*init)(void *ctx); ++ void (*update)(void *ctx, const void *ibuf, uint32_t ilen); ++ void (*finish)(void *ctx, void *obuf); ++ uint32_t ctx_alloc_sz; ++}; ++ ++static struct sw_hash_impl sw_hash_impl[HASH_ALGO_NUM] = { ++ [HASH_ALGO_CRC16_CCITT] = { ++ .init = hash_init_crc16_ccitt, ++ .update = hash_update_crc16_ccitt, ++ .finish = hash_finish_crc16_ccitt, ++ .ctx_alloc_sz = sizeof(uint16_t), ++ }, ++ ++ [HASH_ALGO_CRC32] = { ++ .init = hash_init_crc32, ++ .update = hash_update_crc32, ++ .finish = hash_finish_crc32, ++ .ctx_alloc_sz = sizeof(uint32_t), ++ }, ++ ++ [HASH_ALGO_MD5] = { ++ .init = hash_init_md5, ++ .update = hash_update_md5, ++ .finish = hash_finish_md5, ++ .ctx_alloc_sz = sizeof(struct MD5Context), ++ }, ++ ++ [HASH_ALGO_SHA1] = { ++ .init = hash_init_sha1, ++ .update = hash_update_sha1, ++ .finish = hash_finish_sha1, ++ .ctx_alloc_sz = sizeof(sha1_context), ++ }, ++ ++ [HASH_ALGO_SHA256] = { ++ .init = hash_init_sha256, ++ .update = hash_update_sha256, ++ .finish = hash_finish_sha256, ++ .ctx_alloc_sz = sizeof(sha256_context), ++ }, ++ ++ [HASH_ALGO_SHA384] = { ++ .init = hash_init_sha384, ++ .update = hash_update_sha384, ++ .finish = hash_finish_sha384, ++ .ctx_alloc_sz = sizeof(sha512_context), ++ }, ++ ++ [HASH_ALGO_SHA512] = { ++ .init = hash_init_sha512, ++ .update = hash_update_sha512, ++ .finish = hash_finish_sha512, ++ .ctx_alloc_sz = sizeof(sha512_context), ++ }, ++}; ++ ++static int sw_hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) ++{ ++ struct sw_hash_ctx *hash_ctx; ++ struct sw_hash_impl *hash_impl = &sw_hash_impl[algo]; ++ ++ hash_ctx = malloc(sizeof(hash_ctx->algo) + hash_impl->ctx_alloc_sz); ++ if (!hash_ctx) ++ return -ENOMEM; ++ ++ hash_ctx->algo = algo; ++ ++ hash_impl->init(hash_ctx->algo_ctx); ++ ++ *ctxp = hash_ctx; ++ ++ return 0; ++} ++ ++static int sw_hash_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen) ++{ ++ struct sw_hash_ctx *hash_ctx = ctx; ++ struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; ++ ++ hash_impl->update(hash_ctx->algo_ctx, ibuf, ilen); ++ ++ return 0; ++} ++ ++static int sw_hash_finish(struct udevice *dev, void *ctx, void *obuf) ++{ ++ struct sw_hash_ctx *hash_ctx = ctx; ++ struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; ++ ++ hash_impl->finish(hash_ctx->algo_ctx, obuf); ++ ++ free(ctx); ++ ++ return 0; ++} ++ ++static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf, uint32_t chunk_sz) ++{ ++ int rc; ++ void *ctx; ++ const void *cur, *end; ++ uint32_t chunk; ++ ++ rc = sw_hash_init(dev, algo, &ctx); ++ if (rc) ++ return rc; ++ ++ if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { ++ cur = ibuf; ++ end = ibuf + ilen; ++ ++ while (cur < end) { ++ chunk = end - cur; ++ if (chunk > chunk_sz) ++ chunk = chunk_sz; ++ ++ rc = sw_hash_update(dev, ctx, cur, chunk); ++ if (rc) ++ return rc; ++ ++ cur += chunk; ++ WATCHDOG_RESET(); ++ } ++ } else { ++ rc = sw_hash_update(dev, ctx, ibuf, ilen); ++ if (rc) ++ return rc; ++ } ++ ++ rc = sw_hash_finish(dev, ctx, obuf); ++ if (rc) ++ return rc; ++ ++ return 0; ++} ++ ++static int sw_hash_digest(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf) ++{ ++ /* re-use the watchdog version with input length as the chunk_sz */ ++ return sw_hash_digest_wd(dev, algo, ibuf, ilen, obuf, ilen); ++} ++ ++static const struct hash_ops hash_ops_sw = { ++ .hash_init = sw_hash_init, ++ .hash_update = sw_hash_update, ++ .hash_finish = sw_hash_finish, ++ .hash_digest_wd = sw_hash_digest_wd, ++ .hash_digest = sw_hash_digest, ++}; ++ ++U_BOOT_DRIVER(hash_sw) = { ++ .name = "hash_sw", ++ .id = UCLASS_HASH, ++ .ops = &hash_ops_sw, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++ ++U_BOOT_DRVINFO(hash_sw) = { ++ .name = "hash_sw", ++}; +diff -ruN u-boot-2021.10/drivers/crypto/hash/hash-uclass.c u-boot/drivers/crypto/hash/hash-uclass.c +--- u-boot-2021.10/drivers/crypto/hash/hash-uclass.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/crypto/hash/hash-uclass.c 2021-11-01 17:10:14.279591574 +0100 +@@ -0,0 +1,121 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2021 ASPEED Technology Inc. ++ * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> ++ */ ++ ++#define LOG_CATEGORY UCLASS_HASH ++ ++#include <common.h> ++#include <dm.h> ++#include <asm/global_data.h> ++#include <u-boot/hash.h> ++#include <errno.h> ++#include <fdtdec.h> ++#include <malloc.h> ++#include <asm/io.h> ++#include <linux/list.h> ++ ++struct hash_info { ++ char *name; ++ uint32_t digest_size; ++}; ++ ++static const struct hash_info hash_info[HASH_ALGO_NUM] = { ++ [HASH_ALGO_CRC16_CCITT] = { "crc16-ccitt", 2 }, ++ [HASH_ALGO_CRC32] = { "crc32", 4 }, ++ [HASH_ALGO_MD5] = { "md5", 16 }, ++ [HASH_ALGO_SHA1] = { "sha1", 20 }, ++ [HASH_ALGO_SHA256] = { "sha256", 32 }, ++ [HASH_ALGO_SHA384] = { "sha384", 48 }, ++ [HASH_ALGO_SHA512] = { "sha512", 64}, ++}; ++ ++enum HASH_ALGO hash_algo_lookup_by_name(const char *name) ++{ ++ int i; ++ ++ if (!name) ++ return HASH_ALGO_INVALID; ++ ++ for (i = 0; i < HASH_ALGO_NUM; ++i) ++ if (!strcmp(name, hash_info[i].name)) ++ return i; ++ ++ return HASH_ALGO_INVALID; ++} ++ ++ssize_t hash_algo_digest_size(enum HASH_ALGO algo) ++{ ++ if (algo >= HASH_ALGO_NUM) ++ return -EINVAL; ++ ++ return hash_info[algo].digest_size; ++} ++ ++const char *hash_algo_name(enum HASH_ALGO algo) ++{ ++ if (algo >= HASH_ALGO_NUM) ++ return NULL; ++ ++ return hash_info[algo].name; ++} ++ ++int hash_digest(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf) ++{ ++ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); ++ ++ if (!ops->hash_digest) ++ return -ENOSYS; ++ ++ return ops->hash_digest(dev, algo, ibuf, ilen, obuf); ++} ++ ++int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf, uint32_t chunk_sz) ++{ ++ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); ++ ++ if (!ops->hash_digest_wd) ++ return -ENOSYS; ++ ++ return ops->hash_digest_wd(dev, algo, ibuf, ilen, obuf, chunk_sz); ++} ++ ++int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) ++{ ++ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); ++ ++ if (!ops->hash_init) ++ return -ENOSYS; ++ ++ return ops->hash_init(dev, algo, ctxp); ++} ++ ++int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen) ++{ ++ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); ++ ++ if (!ops->hash_update) ++ return -ENOSYS; ++ ++ return ops->hash_update(dev, ctx, ibuf, ilen); ++} ++ ++int hash_finish(struct udevice *dev, void *ctx, void *obuf) ++{ ++ struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); ++ ++ if (!ops->hash_finish) ++ return -ENOSYS; ++ ++ return ops->hash_finish(dev, ctx, obuf); ++} ++ ++UCLASS_DRIVER(hash) = { ++ .id = UCLASS_HASH, ++ .name = "hash", ++}; +diff -ruN u-boot-2021.10/drivers/crypto/hash/Kconfig u-boot/drivers/crypto/hash/Kconfig +--- u-boot-2021.10/drivers/crypto/hash/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/crypto/hash/Kconfig 2021-11-01 17:10:14.279591574 +0100 +@@ -0,0 +1,16 @@ ++config DM_HASH ++ bool "Enable Driver Model for Hash" ++ depends on DM ++ help ++ If you want to use driver model for Hash, say Y. ++ ++config HASH_SOFTWARE ++ bool "Enable driver for Hash in software" ++ depends on DM_HASH ++ depends on MD5 ++ depends on SHA1 ++ depends on SHA256 ++ depends on SHA512_ALGO ++ help ++ Enable driver for hashing operations in software. Currently ++ it support multiple hash algorithm including CRC/MD5/SHA. +diff -ruN u-boot-2021.10/drivers/crypto/hash/Makefile u-boot/drivers/crypto/hash/Makefile +--- u-boot-2021.10/drivers/crypto/hash/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/crypto/hash/Makefile 2021-11-01 17:10:14.279591574 +0100 +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (c) 2021 ASPEED Technology Inc. ++ ++obj-$(CONFIG_DM_HASH) += hash-uclass.o ++obj-$(CONFIG_HASH_SOFTWARE) += hash_sw.o +diff -ruN u-boot-2021.10/drivers/crypto/Kconfig u-boot/drivers/crypto/Kconfig +--- u-boot-2021.10/drivers/crypto/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/crypto/Kconfig 2021-11-01 17:10:14.276258423 +0100 +@@ -1,5 +1,7 @@ + menu "Hardware crypto devices" + ++source drivers/crypto/hash/Kconfig ++ + source drivers/crypto/fsl/Kconfig + + endmenu +diff -ruN u-boot-2021.10/drivers/crypto/Makefile u-boot/drivers/crypto/Makefile +--- u-boot-2021.10/drivers/crypto/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/crypto/Makefile 2021-11-01 17:10:14.276258423 +0100 +@@ -1,8 +1,9 @@ + # SPDX-License-Identifier: GPL-2.0+ + # + # Copyright (c) 2013 Samsung Electronics Co., Ltd. +-# http://www.samsung.com ++# http://www.samsung.com + + obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o + obj-y += rsa_mod_exp/ + obj-y += fsl/ ++obj-y += hash/ +diff -ruN u-boot-2021.10/drivers/ddr/altera/sdram_s10.c u-boot/drivers/ddr/altera/sdram_s10.c +--- u-boot-2021.10/drivers/ddr/altera/sdram_s10.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/altera/sdram_s10.c 2021-11-01 17:10:14.279591574 +0100 +@@ -335,4 +335,3 @@ + debug("DDR: HMC init success\n"); + return 0; + } +- +diff -ruN u-boot-2021.10/drivers/ddr/fsl/ddr3_dimm_params.c u-boot/drivers/ddr/fsl/ddr3_dimm_params.c +--- u-boot-2021.10/drivers/ddr/fsl/ddr3_dimm_params.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/fsl/ddr3_dimm_params.c 2021-11-01 17:10:14.282924726 +0100 +@@ -36,18 +36,18 @@ + * 0110 16Gb 2GB + * + * SPD byte8 - module memory bus width +- * bit[2:0] primary bus width ++ * bit[2:0] primary bus width + * 000 8bits +- * 001 16bits +- * 010 32bits +- * 011 64bits ++ * 001 16bits ++ * 010 32bits ++ * 011 64bits + * + * SPD byte7 - module organiztion +- * bit[2:0] sdram device width +- * 000 4bits +- * 001 8bits +- * 010 16bits +- * 011 32bits ++ * bit[2:0] sdram device width ++ * 000 4bits ++ * 001 8bits ++ * 010 16bits ++ * 011 32bits + * + */ + static unsigned long long +diff -ruN u-boot-2021.10/drivers/ddr/fsl/Kconfig u-boot/drivers/ddr/fsl/Kconfig +--- u-boot-2021.10/drivers/ddr/fsl/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/fsl/Kconfig 2021-11-01 17:10:14.282924726 +0100 +@@ -10,6 +10,8 @@ + help + Select Freescale Multi Mode DDR controller (MMDC). + ++if SYS_FSL_DDR || SYS_FSL_MMDC ++ + config SYS_FSL_DDR_BE + bool + help +@@ -116,28 +118,51 @@ + config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + depends on SYS_FSL_HAS_DDR4 ++ imply DDR_SPD + select SYS_FSL_DDRC_GEN4 + + config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on SYS_FSL_HAS_DDR3 ++ imply DDR_SPD + select SYS_FSL_DDRC_GEN3 if PPC + select SYS_FSL_DDRC_ARM_GEN3 if ARM + + config SYS_FSL_DDR2 + bool "Freescale DDR2 controller" + depends on SYS_FSL_HAS_DDR2 ++ imply DDR_SPD + select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) + + config SYS_FSL_DDR1 + bool "Freescale DDR1 controller" + depends on SYS_FSL_HAS_DDR1 ++ imply DDR_SPD + select SYS_FSL_DDRC_GEN1 + + endchoice + + endmenu + ++config FSL_DMA ++ def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER ++ ++config DDR_ECC ++ bool "ECC DDR memory support" ++ ++config DDR_ECC_CMD ++ bool "Access the ECC features of the memory controller" ++ depends on DDR_ECC && MPC83xx ++ default y ++ ++config ECC_INIT_VIA_DDRCONTROLLER ++ bool "DDR Memory controller initializes memory." ++ help ++ Use the DDR controller to auto initialize memory. If not enabled, ++ the DMA controller is responsible for doing this. ++ ++endif ++ + config SYS_FSL_ERRATUM_A008378 + bool + +diff -ruN u-boot-2021.10/drivers/ddr/Kconfig u-boot/drivers/ddr/Kconfig +--- u-boot-2021.10/drivers/ddr/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/Kconfig 2021-11-01 17:10:14.279591574 +0100 +@@ -1,2 +1,34 @@ ++choice ++ prompt "Method to determine DDR clock frequency" ++ default STATIC_DDR_CLK_FREQ ++ depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \ ++ || ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \ ++ || FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2 ++ help ++ The DDR clock frequency can either be defined statically now at ++ build time, or can be determined at run-time via the ++ get_board_ddr_clk function. ++ ++config DYNAMIC_DDR_CLK_FREQ ++ bool "Run-time DDR clock frequency" ++ ++config STATIC_DDR_CLK_FREQ ++ bool "Build-time static DDR clock frequency" ++ ++endchoice ++ ++config DDR_CLK_FREQ ++ int "DDR clock frequency in Hz" ++ depends on STATIC_DDR_CLK_FREQ ++ default 100000000 ++ help ++ The DDR clock frequency, specified in Hz. ++ ++config DDR_SPD ++ bool "JEDEC Serial Presence Detect (SPD) support" ++ help ++ For memory controllers that can utilize it, add enable support for ++ using the JEDEC SDP standard. ++ + source "drivers/ddr/altera/Kconfig" + source "drivers/ddr/imx/Kconfig" +diff -ruN u-boot-2021.10/drivers/ddr/marvell/a38x/ddr3_training.c u-boot/drivers/ddr/marvell/a38x/ddr3_training.c +--- u-boot-2021.10/drivers/ddr/marvell/a38x/ddr3_training.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/marvell/a38x/ddr3_training.c 2021-11-01 17:10:14.286257876 +0100 +@@ -2895,4 +2895,3 @@ + + return odt_n; + } +- +diff -ruN u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_axp_config.h u-boot/drivers/ddr/marvell/axp/ddr3_axp_config.h +--- u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_axp_config.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/marvell/axp/ddr3_axp_config.h 2021-11-01 17:10:14.289591027 +0100 +@@ -16,11 +16,7 @@ + * Level 3: Provides the windows margin of each DQ as a results of DQS + * centeralization + */ +-#ifdef CONFIG_DDR_LOG_LEVEL + #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL +-#else +-#define DDR3_LOG_LEVEL 0 +-#endif + + #define DDR3_PBS 1 + +diff -ruN u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_axp.h u-boot/drivers/ddr/marvell/axp/ddr3_axp.h +--- u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_axp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/marvell/axp/ddr3_axp.h 2021-11-01 17:10:14.289591027 +0100 +@@ -19,10 +19,10 @@ + #define FAR_END_DIMM_ADDR 0x50 + #define MAX_DIMM_ADDR 0x60 + +-#ifndef CONFIG_DDR_FIXED_SIZE ++#ifndef CONFIG_SYS_SDRAM_SIZE + #define SDRAM_CS_SIZE 0xFFFFFFF + #else +-#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) ++#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) + #endif + #define SDRAM_CS_BASE 0x0 + #define SDRAM_DIMM_SIZE 0x80000000 +diff -ruN u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_spd.c u-boot/drivers/ddr/marvell/axp/ddr3_spd.c +--- u-boot-2021.10/drivers/ddr/marvell/axp/ddr3_spd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ddr/marvell/axp/ddr3_spd.c 2021-11-01 17:10:14.292924178 +0100 +@@ -46,7 +46,7 @@ + #define SPD_COL_NUM_MASK (7 << SPD_COL_NUM_OFF) + + #define SPD_MODULE_ORG_BYTE 7 +-#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0 ++#define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0 + #define SPD_MODULE_SDRAM_DEV_WIDTH_MASK (7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF) + #define SPD_MODULE_BANK_NUM_MIN 1 + #define SPD_MODULE_BANK_NUM_OFF 3 +diff -ruN u-boot-2021.10/drivers/demo/demo-uclass.c u-boot/drivers/demo/demo-uclass.c +--- u-boot-2021.10/drivers/demo/demo-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/demo/demo-uclass.c 2021-11-01 17:10:14.292924178 +0100 +@@ -10,15 +10,11 @@ + #include <dm.h> + #include <dm-demo.h> + #include <errno.h> +-#include <fdtdec.h> + #include <log.h> + #include <malloc.h> +-#include <asm/global_data.h> + #include <asm/io.h> + #include <linux/list.h> + +-DECLARE_GLOBAL_DATA_PTR; +- + UCLASS_DRIVER(demo) = { + .name = "demo", + .id = UCLASS_DEMO, +@@ -67,10 +63,9 @@ + int demo_parse_dt(struct udevice *dev) + { + struct dm_demo_pdata *pdata = dev_get_plat(dev); +- int dn = dev_of_offset(dev); + +- pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0); +- pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL); ++ pdata->sides = dev_read_s32_default(dev, "sides", 0); ++ pdata->colour = dev_read_string(dev, "colour"); + if (!pdata->sides || !pdata->colour) { + debug("%s: Invalid device tree data\n", __func__); + return -EINVAL; +diff -ruN u-boot-2021.10/drivers/dfu/Kconfig u-boot/drivers/dfu/Kconfig +--- u-boot-2021.10/drivers/dfu/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dfu/Kconfig 2021-11-01 17:10:14.292924178 +0100 +@@ -16,7 +16,6 @@ + if DFU + config DFU_WRITE_ALT + bool +- default n + + config DFU_TFTP + bool "DFU via TFTP" +diff -ruN u-boot-2021.10/drivers/dma/fsl_dma.c u-boot/drivers/dma/fsl_dma.c +--- u-boot-2021.10/drivers/dma/fsl_dma.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dma/fsl_dma.c 2021-11-01 17:10:14.296257330 +0100 +@@ -130,11 +130,9 @@ + + /* + * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER +- * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA + */ + #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ +- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ +- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) ++ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) + void dma_meminit(uint val, uint size) + { + uint *p = 0; +diff -ruN u-boot-2021.10/drivers/dma/Kconfig u-boot/drivers/dma/Kconfig +--- u-boot-2021.10/drivers/dma/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dma/Kconfig 2021-11-01 17:10:14.296257330 +0100 +@@ -35,19 +35,40 @@ + This driver support data transfer from devices to + memory and from memory to devices. + ++config DMA_LPC32XX ++ bool "LPC32XX DMA driver" ++ select DMA_LEGACY ++ help ++ Enable some legacy DMA code for lpc32xx. It provides some direct ++ functions likes lpc32xx_dma_wait_status() which can be called from ++ other code. ++ ++ This should be converted to use driver model and UCLASS_DMA. ++ + config TI_EDMA3 + bool "TI EDMA3 driver" ++ select DMA_LEGACY + help + Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. + This driver support data transfer between memory + regions. + ++config TI_KSNAV ++ bool "TI Keystone Navigator DMA driver" ++ depends on ARCH_KEYSTONE ++ default y ++ select DMA_LEGACY ++ help ++ Enable the Keystone Navigator driver for Keystone 2 platforms. ++ + config APBH_DMA + bool "Support APBH DMA" + depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M ++ select DMA_LEGACY + help + Enable APBH DMA driver. + ++ + if APBH_DMA + config APBH_DMA_BURST + bool "Enable DMA BURST" +@@ -57,6 +78,15 @@ + + endif + ++config DMA_LEGACY ++ bool "Legacy DMA support" ++ default y if FSLDMAFEC ++ help ++ Enable legacy DMA support. This does not use driver model and should ++ be migrated to the new API. ++ ++ It is required for some PowerPC boards. ++ + source "drivers/dma/ti/Kconfig" + + endmenu # menu "DMA Support" +diff -ruN u-boot-2021.10/drivers/dma/keystone_nav.c u-boot/drivers/dma/keystone_nav.c +--- u-boot-2021.10/drivers/dma/keystone_nav.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dma/keystone_nav.c 2021-11-01 17:10:14.296257330 +0100 +@@ -11,20 +11,20 @@ + #include <linux/delay.h> + + struct qm_config qm_memmap = { +- .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE, +- .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE, +- .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS, +- .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE, +- .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE, +- .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE, +- .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE, +- .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE, +- .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE, +- .region_num = CONFIG_KSNAV_QM_REGION_NUM, +- .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE, +- .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE, +- .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE, +- .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM, ++ .stat_cfg = KS2_QM_QUEUE_STATUS_BASE, ++ .queue = (void *)KS2_QM_MANAGER_QUEUES_BASE, ++ .mngr_vbusm = KS2_QM_BASE_ADDRESS, ++ .i_lram = KS2_QM_LINK_RAM_BASE, ++ .proxy = (void *)KS2_QM_MANAGER_Q_PROXY_BASE, ++ .status_ram = KS2_QM_STATUS_RAM_BASE, ++ .mngr_cfg = (void *)KS2_QM_CONF_BASE, ++ .intd_cfg = KS2_QM_INTD_CONF_BASE, ++ .desc_mem = (void *)KS2_QM_DESC_SETUP_BASE, ++ .region_num = KS2_QM_REGION_NUM, ++ .pdsp_cmd = KS2_QM_PDSP1_CMD_BASE, ++ .pdsp_ctl = KS2_QM_PDSP1_CTRL_BASE, ++ .pdsp_iram = KS2_QM_PDSP1_IRAM_BASE, ++ .qpool_num = KS2_QM_QPOOL_NUM, + }; + + /* +@@ -252,7 +252,7 @@ + writel(0, &pktdma->global->emulation_control); + + /* Set QM base address, only for K2x devices */ +- writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); ++ writel(KS2_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); + + /* Enable all channels. The current state isn't important */ + for (j = 0; j < pktdma->tx_ch_num; j++) { +diff -ruN u-boot-2021.10/drivers/dma/keystone_nav_cfg.c u-boot/drivers/dma/keystone_nav_cfg.c +--- u-boot-2021.10/drivers/dma/keystone_nav_cfg.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dma/keystone_nav_cfg.c 2021-11-01 17:10:14.296257330 +0100 +@@ -8,19 +8,17 @@ + + #include <asm/ti-common/keystone_nav.h> + +-#ifdef CONFIG_KSNAV_PKTDMA_NETCP + /* NETCP Pktdma */ + struct pktdma_cfg netcp_pktdma = { +- .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, +- .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, +- .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, +- .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, +- .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, +- .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, +- .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, +- .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, +- .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, +- .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, +- .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, ++ .global = (void *)KS2_NETCP_PDMA_CTRL_BASE, ++ .tx_ch = (void *)KS2_NETCP_PDMA_TX_BASE, ++ .tx_ch_num = KS2_NETCP_PDMA_TX_CH_NUM, ++ .rx_ch = (void *)KS2_NETCP_PDMA_RX_BASE, ++ .rx_ch_num = KS2_NETCP_PDMA_RX_CH_NUM, ++ .tx_sched = (u32 *)KS2_NETCP_PDMA_SCHED_BASE, ++ .rx_flows = (void *)KS2_NETCP_PDMA_RX_FLOW_BASE, ++ .rx_flow_num = KS2_NETCP_PDMA_RX_FLOW_NUM, ++ .rx_free_q = KS2_NETCP_PDMA_RX_FREE_QUEUE, ++ .rx_rcv_q = KS2_NETCP_PDMA_RX_RCV_QUEUE, ++ .tx_snd_q = KS2_NETCP_PDMA_TX_SND_QUEUE, + }; +-#endif +diff -ruN u-boot-2021.10/drivers/dma/ti/Kconfig u-boot/drivers/dma/ti/Kconfig +--- u-boot-2021.10/drivers/dma/ti/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/dma/ti/Kconfig 2021-11-01 17:10:14.296257330 +0100 +@@ -9,7 +9,6 @@ + select TI_K3_NAVSS_RINGACC + select TI_K3_NAVSS_PSILCFG + select TI_K3_PSIL +- default n + help + Support for UDMA used in K3 devices. + endif +diff -ruN u-boot-2021.10/drivers/fastboot/Kconfig u-boot/drivers/fastboot/Kconfig +--- u-boot-2021.10/drivers/fastboot/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/fastboot/Kconfig 2021-11-01 17:10:14.296257330 +0100 +@@ -74,7 +74,6 @@ + + config FASTBOOT_UUU_SUPPORT + bool "Enable FASTBOOT i.MX UUU special command" +- default n + help + The fastboot protocol includes "UCmd" and "ACmd" command. + Be aware that you provide full access to any U-Boot command, +diff -ruN u-boot-2021.10/drivers/firmware/firmware-uclass.c u-boot/drivers/firmware/firmware-uclass.c +--- u-boot-2021.10/drivers/firmware/firmware-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/firmware/firmware-uclass.c 2021-11-01 17:10:14.299590480 +0100 +@@ -9,7 +9,7 @@ + UCLASS_DRIVER(firmware) = { + .id = UCLASS_FIRMWARE, + .name = "firmware", +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/drivers/firmware/scmi/Makefile u-boot/drivers/firmware/scmi/Makefile +--- u-boot-2021.10/drivers/firmware/scmi/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/firmware/scmi/Makefile 2021-11-01 17:10:14.299590480 +0100 +@@ -1,5 +1,5 @@ + obj-y += scmi_agent-uclass.o + obj-y += smt.o +-obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o ++obj-$(CONFIG_ARM_SMCCC) += smccc_agent.o + obj-$(CONFIG_DM_MAILBOX) += mailbox_agent.o + obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o +diff -ruN u-boot-2021.10/drivers/fpga/socfpga.c u-boot/drivers/fpga/socfpga.c +--- u-boot-2021.10/drivers/fpga/socfpga.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/fpga/socfpga.c 2021-11-01 17:10:14.302923631 +0100 +@@ -69,4 +69,3 @@ + : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); + } +- +diff -ruN u-boot-2021.10/drivers/gpio/axp_gpio.c u-boot/drivers/gpio/axp_gpio.c +--- u-boot-2021.10/drivers/gpio/axp_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/axp_gpio.c 2021-11-01 17:10:14.302923631 +0100 +@@ -6,174 +6,157 @@ + */ + + #include <common.h> +-#include <asm/arch/gpio.h> +-#include <asm/arch/pmic_bus.h> + #include <asm/gpio.h> +-#include <axp_pmic.h> + #include <dm.h> + #include <dm/device-internal.h> +-#include <dm/lists.h> +-#include <dm/root.h> + #include <errno.h> ++#include <power/pmic.h> + +-static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val); ++#define AXP_GPIO_PREFIX "AXP0-" ++#define AXP_GPIO_COUNT 4 + +-static u8 axp_get_gpio_ctrl_reg(unsigned pin) +-{ +- switch (pin) { +- case 0: return AXP_GPIO0_CTRL; +- case 1: return AXP_GPIO1_CTRL; +-#ifdef AXP_GPIO2_CTRL +- case 2: return AXP_GPIO2_CTRL; +-#endif +-#ifdef AXP_GPIO3_CTRL +- case 3: return AXP_GPIO3_CTRL; +-#endif +- } +- return 0; +-} ++#define AXP_GPIO_CTRL_MASK 0x7 ++#define AXP_GPIO_CTRL_OUTPUT_LOW 0 ++#define AXP_GPIO_CTRL_OUTPUT_HIGH 1 ++ ++struct axp_gpio_desc { ++ const u8 *pins; ++ u8 npins; ++ u8 status_reg; ++ u8 status_offset; ++ u8 pull_reg; ++ u8 input_mux; ++}; + +-static int axp_gpio_direction_input(struct udevice *dev, unsigned pin) ++static int axp_gpio_get_value(struct udevice *dev, unsigned pin) + { +- u8 reg; ++ const struct axp_gpio_desc *desc = dev_get_priv(dev); ++ int ret; + +- switch (pin) { +-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */ +- case SUNXI_GPIO_AXP0_VBUS_DETECT: +- return 0; +-#endif +- default: +- reg = axp_get_gpio_ctrl_reg(pin); +- if (reg == 0) +- return -EINVAL; ++ ret = pmic_reg_read(dev->parent, desc->status_reg); ++ if (ret < 0) ++ return ret; + +- return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT); +- } ++ return !!(ret & BIT(desc->status_offset + pin)); + } + +-static int axp_gpio_direction_output(struct udevice *dev, unsigned pin, +- int val) ++static int axp_gpio_get_function(struct udevice *dev, unsigned pin) + { +- __maybe_unused int ret; +- u8 reg; ++ const struct axp_gpio_desc *desc = dev_get_priv(dev); ++ int ret; + +- switch (pin) { +-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +- /* Only available on later PMICs */ +- case SUNXI_GPIO_AXP0_VBUS_ENABLE: +- ret = pmic_bus_clrbits(AXP_MISC_CTRL, +- AXP_MISC_CTRL_N_VBUSEN_FUNC); +- if (ret) +- return ret; ++ ret = pmic_reg_read(dev->parent, desc->pins[pin]); ++ if (ret < 0) ++ return ret; + +- return axp_gpio_set_value(dev, pin, val); +-#endif +- default: +- reg = axp_get_gpio_ctrl_reg(pin); +- if (reg == 0) +- return -EINVAL; ++ ret &= AXP_GPIO_CTRL_MASK; ++ if (ret == desc->input_mux) ++ return GPIOF_INPUT; ++ if (ret == AXP_GPIO_CTRL_OUTPUT_HIGH || ret == AXP_GPIO_CTRL_OUTPUT_LOW) ++ return GPIOF_OUTPUT; + +- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : +- AXP_GPIO_CTRL_OUTPUT_LOW); +- } ++ return GPIOF_UNKNOWN; + } + +-static int axp_gpio_get_value(struct udevice *dev, unsigned pin) ++static int axp_gpio_set_flags(struct udevice *dev, unsigned pin, ulong flags) + { +- u8 reg, val, mask; ++ const struct axp_gpio_desc *desc = dev_get_priv(dev); ++ bool pull_down = flags & GPIOD_PULL_DOWN; + int ret; ++ u8 mux; + +- switch (pin) { +-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */ +- case SUNXI_GPIO_AXP0_VBUS_DETECT: +- ret = pmic_bus_read(AXP_POWER_STATUS, &val); +- mask = AXP_POWER_STATUS_VBUS_PRESENT; +- break; +-#endif +-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +- /* Only available on later PMICs */ +- case SUNXI_GPIO_AXP0_VBUS_ENABLE: +- ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val); +- mask = AXP_VBUS_IPSOUT_DRIVEBUS; +- break; +-#endif +- default: +- reg = axp_get_gpio_ctrl_reg(pin); +- if (reg == 0) +- return -EINVAL; +- +- ret = pmic_bus_read(AXP_GPIO_STATE, &val); +- mask = 1 << (pin + AXP_GPIO_STATE_OFFSET); ++ if (flags & (GPIOD_MASK_DSTYPE | GPIOD_PULL_UP)) ++ return -EINVAL; ++ if (pull_down && !desc->pull_reg) ++ return -EINVAL; ++ ++ if (desc->pull_reg) { ++ ret = pmic_clrsetbits(dev->parent, desc->pull_reg, ++ BIT(pin), pull_down ? BIT(pin) : 0); ++ if (ret) ++ return ret; + } +- if (ret) +- return ret; + +- return (val & mask) ? 1 : 0; +-} ++ if (flags & GPIOD_IS_IN) ++ mux = desc->input_mux; ++ else if (flags & GPIOD_IS_OUT_ACTIVE) ++ mux = AXP_GPIO_CTRL_OUTPUT_HIGH; ++ else ++ mux = AXP_GPIO_CTRL_OUTPUT_LOW; + +-static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val) +-{ +- u8 reg; +- +- switch (pin) { +-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +- /* Only available on later PMICs */ +- case SUNXI_GPIO_AXP0_VBUS_ENABLE: +- if (val) +- return pmic_bus_setbits(AXP_VBUS_IPSOUT, +- AXP_VBUS_IPSOUT_DRIVEBUS); +- else +- return pmic_bus_clrbits(AXP_VBUS_IPSOUT, +- AXP_VBUS_IPSOUT_DRIVEBUS); +-#endif +- default: +- reg = axp_get_gpio_ctrl_reg(pin); +- if (reg == 0) +- return -EINVAL; +- +- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : +- AXP_GPIO_CTRL_OUTPUT_LOW); +- } ++ return pmic_clrsetbits(dev->parent, desc->pins[pin], ++ AXP_GPIO_CTRL_MASK, mux); + } + +-static const struct dm_gpio_ops gpio_axp_ops = { +- .direction_input = axp_gpio_direction_input, +- .direction_output = axp_gpio_direction_output, ++static const struct dm_gpio_ops axp_gpio_ops = { + .get_value = axp_gpio_get_value, +- .set_value = axp_gpio_set_value, ++ .get_function = axp_gpio_get_function, ++ .xlate = gpio_xlate_offs_flags, ++ .set_flags = axp_gpio_set_flags, + }; + +-static int gpio_axp_probe(struct udevice *dev) ++static int axp_gpio_probe(struct udevice *dev) + { ++ struct axp_gpio_desc *desc = (void *)dev_get_driver_data(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + ++ dev_set_priv(dev, desc); ++ + /* Tell the uclass how many GPIOs we have */ +- uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX); +- uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT; ++ uc_priv->bank_name = AXP_GPIO_PREFIX; ++ uc_priv->gpio_count = desc->npins; + + return 0; + } + +-U_BOOT_DRIVER(gpio_axp) = { +- .name = "gpio_axp", +- .id = UCLASS_GPIO, +- .ops = &gpio_axp_ops, +- .probe = gpio_axp_probe, ++static const u8 axp152_gpio_pins[] = { ++ 0x90, 0x91, 0x92, 0x93, + }; + +-int axp_gpio_init(void) +-{ +- struct udevice *dev; +- int ret; ++static const struct axp_gpio_desc axp152_gpio_desc = { ++ .pins = axp152_gpio_pins, ++ .npins = ARRAY_SIZE(axp152_gpio_pins), ++ .status_reg = 0x97, ++ .status_offset = 4, ++ .input_mux = 3, ++}; + +- ret = pmic_bus_init(); +- if (ret) +- return ret; ++static const u8 axp209_gpio_pins[] = { ++ 0x90, 0x92, 0x93, ++}; + +- /* There is no devicetree support for the axp yet, so bind directly */ +- ret = device_bind_driver(dm_root(), "gpio_axp", "AXP-gpio", &dev); +- if (ret) +- return ret; ++static const struct axp_gpio_desc axp209_gpio_desc = { ++ .pins = axp209_gpio_pins, ++ .npins = ARRAY_SIZE(axp209_gpio_pins), ++ .status_reg = 0x94, ++ .status_offset = 4, ++ .input_mux = 2, ++}; + +- return 0; +-} ++static const u8 axp221_gpio_pins[] = { ++ 0x90, 0x92, ++}; ++ ++static const struct axp_gpio_desc axp221_gpio_desc = { ++ .pins = axp221_gpio_pins, ++ .npins = ARRAY_SIZE(axp221_gpio_pins), ++ .status_reg = 0x94, ++ .pull_reg = 0x97, ++ .input_mux = 2, ++}; ++ ++static const struct udevice_id axp_gpio_ids[] = { ++ { .compatible = "x-powers,axp152-gpio", .data = (ulong)&axp152_gpio_desc }, ++ { .compatible = "x-powers,axp209-gpio", .data = (ulong)&axp209_gpio_desc }, ++ { .compatible = "x-powers,axp221-gpio", .data = (ulong)&axp221_gpio_desc }, ++ { .compatible = "x-powers,axp813-gpio", .data = (ulong)&axp221_gpio_desc }, ++ { } ++}; ++ ++U_BOOT_DRIVER(axp_gpio) = { ++ .name = "axp_gpio", ++ .id = UCLASS_GPIO, ++ .of_match = axp_gpio_ids, ++ .probe = axp_gpio_probe, ++ .ops = &axp_gpio_ops, ++}; +diff -ruN u-boot-2021.10/drivers/gpio/gpio-uclass.c u-boot/drivers/gpio/gpio-uclass.c +--- u-boot-2021.10/drivers/gpio/gpio-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/gpio-uclass.c 2021-11-01 17:10:14.302923631 +0100 +@@ -7,6 +7,7 @@ + + #include <common.h> + #include <dm.h> ++#include <dt-structs.h> + #include <log.h> + #include <dm/devres.h> + #include <dm/device_compat.h> +@@ -140,7 +141,8 @@ + + if (!strncasecmp(name, uc_priv->bank_name, len)) { + if (!strict_strtoul(name + len, 10, &offset)) +- break; ++ if (offset < uc_priv->gpio_count) ++ break; + } + + /* +@@ -184,38 +186,50 @@ + return 0; + } + +-int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc, +- struct ofnode_phandle_args *args) ++unsigned long gpio_flags_xlate(uint32_t arg) + { +- if (args->args_count < 1) +- return -EINVAL; ++ unsigned long flags = 0; + +- desc->offset = args->args[0]; +- +- if (args->args_count < 2) +- return 0; +- +- desc->flags = 0; +- if (args->args[1] & GPIO_ACTIVE_LOW) +- desc->flags |= GPIOD_ACTIVE_LOW; ++ if (arg & GPIO_ACTIVE_LOW) ++ flags |= GPIOD_ACTIVE_LOW; + + /* + * need to test 2 bits for gpio output binding: + * OPEN_DRAIN (0x6) = SINGLE_ENDED (0x2) | LINE_OPEN_DRAIN (0x4) + * OPEN_SOURCE (0x2) = SINGLE_ENDED (0x2) | LINE_OPEN_SOURCE (0x0) + */ +- if (args->args[1] & GPIO_SINGLE_ENDED) { +- if (args->args[1] & GPIO_LINE_OPEN_DRAIN) +- desc->flags |= GPIOD_OPEN_DRAIN; ++ if (arg & GPIO_SINGLE_ENDED) { ++ if (arg & GPIO_LINE_OPEN_DRAIN) ++ flags |= GPIOD_OPEN_DRAIN; + else +- desc->flags |= GPIOD_OPEN_SOURCE; ++ flags |= GPIOD_OPEN_SOURCE; + } + +- if (args->args[1] & GPIO_PULL_UP) +- desc->flags |= GPIOD_PULL_UP; ++ if (arg & GPIO_PULL_UP) ++ flags |= GPIOD_PULL_UP; ++ ++ if (arg & GPIO_PULL_DOWN) ++ flags |= GPIOD_PULL_DOWN; ++ ++ return flags; ++} ++ ++int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc, ++ struct ofnode_phandle_args *args) ++{ ++ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); ++ ++ if (args->args_count < 1) ++ return -EINVAL; ++ ++ desc->offset = args->args[0]; ++ if (desc->offset >= uc_priv->gpio_count) ++ return -EINVAL; ++ ++ if (args->args_count < 2) ++ return 0; + +- if (args->args[1] & GPIO_PULL_DOWN) +- desc->flags |= GPIOD_PULL_DOWN; ++ desc->flags = gpio_flags_xlate(args->args[1]); + + return 0; + } +@@ -231,7 +245,7 @@ + return gpio_xlate_offs_flags(desc->dev, desc, args); + } + +-#if defined(CONFIG_GPIO_HOG) ++#if CONFIG_IS_ENABLED(GPIO_HOG) + + struct gpio_hog_priv { + struct gpio_desc gpiod; +@@ -1137,7 +1151,7 @@ + return ret; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int _gpio_request_by_name_nodev(ofnode node, const char *list_name, + int index, struct gpio_desc *desc, + int flags, bool add_index) +@@ -1226,6 +1240,27 @@ + } + #endif /* OF_PLATDATA */ + ++#if CONFIG_IS_ENABLED(OF_PLATDATA) ++int gpio_request_by_phandle(struct udevice *dev, ++ const struct phandle_2_arg *cells, ++ struct gpio_desc *desc, int flags) ++{ ++ struct ofnode_phandle_args args; ++ struct udevice *gpio_dev; ++ const int index = 0; ++ int ret; ++ ++ ret = device_get_by_ofplat_idx(cells->idx, &gpio_dev); ++ if (ret) ++ return ret; ++ args.args[0] = cells->arg[0]; ++ args.args[1] = cells->arg[1]; ++ ++ return gpio_request_tail(ret, NULL, &args, NULL, index, desc, flags, ++ index > 0, gpio_dev); ++} ++#endif ++ + int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc) + { + /* For now, we don't do any checking of dev */ +@@ -1430,7 +1465,7 @@ + } + #endif + +- if (IS_ENABLED(CONFIG_GPIO_HOG)) { ++ if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) { + dev_for_each_subnode(node, dev) { + if (ofnode_read_bool(node, "gpio-hog")) { + const char *name = ofnode_get_name(node); +diff -ruN u-boot-2021.10/drivers/gpio/hi6220_gpio.c u-boot/drivers/gpio/hi6220_gpio.c +--- u-boot-2021.10/drivers/gpio/hi6220_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/hi6220_gpio.c 2021-11-01 17:10:14.302923631 +0100 +@@ -54,8 +54,6 @@ + return !!readb(bank->base + (BIT(gpio + 2))); + } + +- +- + static const struct dm_gpio_ops gpio_hi6220_ops = { + .direction_input = hi6220_gpio_direction_input, + .direction_output = hi6220_gpio_direction_output, +@@ -91,5 +89,3 @@ + .probe = hi6220_gpio_probe, + .priv_auto = sizeof(struct gpio_bank), + }; +- +- +diff -ruN u-boot-2021.10/drivers/gpio/intel_gpio.c u-boot/drivers/gpio/intel_gpio.c +--- u-boot-2021.10/drivers/gpio/intel_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/intel_gpio.c 2021-11-01 17:10:14.302923631 +0100 +@@ -204,7 +204,7 @@ + #endif + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id intel_intel_gpio_ids[] = { + { .compatible = "intel,gpio" }, + { } +diff -ruN u-boot-2021.10/drivers/gpio/Kconfig u-boot/drivers/gpio/Kconfig +--- u-boot-2021.10/drivers/gpio/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/Kconfig 2021-11-01 17:10:14.302923631 +0100 +@@ -2,7 +2,19 @@ + # GPIO infrastructure and drivers + # + +-menu "GPIO Support" ++menuconfig GPIO ++ bool "GPIO support" ++ default y ++ help ++ Enable support for GPIOs (General-purpose Input/Output) in U-Boot. ++ GPIOs allow U-Boot to read the state of an input line (high or ++ low) and set the state of an output line. This can be used to ++ drive LEDs, control power to various system parts and read user ++ input. GPIOs can be useful to enable a 'sign-of-life' LED, ++ for example. Enable this option to build the drivers in ++ drivers/gpio as part of an U-Boot build. ++ ++if GPIO + + config DM_GPIO + bool "Enable Driver Model for GPIO drivers" +@@ -39,7 +51,6 @@ + config GPIO_HOG + bool "Enable GPIO hog support" + depends on DM_GPIO +- default n + help + Enable gpio hog support + The GPIO chip may contain GPIO hog definitions. GPIO hogging +@@ -73,6 +84,13 @@ + Select this to enable PIO for Altera devices. Please find + details on the "Embedded Peripherals IP User Guide" of Altera. + ++config AXP_GPIO ++ bool "X-Powers AXP PMICs GPIO driver" ++ depends on DM_GPIO && PMIC_AXP ++ help ++ This driver supports the GPIO pins on ++ X-Powers AXP152, AXP2xx, and AXP8xx PMICs. ++ + config BCM6345_GPIO + bool "BCM6345 GPIO driver" + depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ +@@ -91,13 +109,11 @@ + config DWAPB_GPIO + bool "DWAPB GPIO driver" + depends on DM && DM_GPIO +- default n + help + Support for the Designware APB GPIO driver. + + config AT91_GPIO + bool "AT91 PIO GPIO driver" +- default n + help + Say yes here to select AT91 PIO GPIO driver. AT91 PIO + controller manages up to 32 fully programmable input/output +@@ -110,7 +126,6 @@ + config ATMEL_PIO4 + bool "ATMEL PIO4 driver" + depends on DM_GPIO +- default n + help + Say yes here to support the Atmel PIO4 driver. + The PIO4 is new version of Atmel PIO controller, which manages +@@ -150,13 +165,11 @@ + config IMX_RGPIO2P + bool "i.MX7ULP RGPIO2P driver" + depends on DM +- default n + help + This driver supports i.MX7ULP Rapid GPIO2P controller. + + config IPROC_GPIO + bool "Broadcom iProc GPIO driver(without pinconf)" +- default n + help + The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray, + use the same GPIO Controller IP hence this driver could be used +@@ -168,14 +181,12 @@ + config HSDK_CREG_GPIO + bool "HSDK CREG GPIO griver" + depends on DM_GPIO +- default n + help + This driver supports CREG GPIOs on Synopsys HSDK SOC. + + config LPC32XX_GPIO + bool "LPC32XX GPIO driver" + depends on DM +- default n + help + Support for the LPC32XX GPIO driver. + +@@ -203,7 +214,6 @@ + config MSM_GPIO + bool "Qualcomm GPIO driver" + depends on DM_GPIO +- default n + help + Support GPIO controllers on Qualcomm Snapdragon family of SoCs. + This controller have single bank (default name "soc"), every +@@ -302,7 +312,7 @@ + + config SUNXI_GPIO + bool "Allwinner GPIO driver" +- depends on ARCH_SUNXI ++ depends on (ARCH_SUNXI || TARGET_SUNXI) + help + Support the GPIO device in Allwinner SoCs. + +@@ -345,7 +355,6 @@ + config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM +- default n + help + Say yes here to support Vybrid vf610 GPIOs. + +@@ -513,4 +522,4 @@ + into a number of banks each with 32 GPIOs. The GPIOs for a device are + defined in the device tree with one node for each bank. + +-endmenu ++endif +diff -ruN u-boot-2021.10/drivers/gpio/Makefile u-boot/drivers/gpio/Makefile +--- u-boot-2021.10/drivers/gpio/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/Makefile 2021-11-01 17:10:14.302923631 +0100 +@@ -23,7 +23,6 @@ + obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o + obj-$(CONFIG_KONA_GPIO) += kona_gpio.o + obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o +-obj-$(CONFIG_MARVELL_MFP) += mvmfp.o + obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o + obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o + obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o +@@ -33,7 +32,7 @@ + obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o + obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o + obj-$(CONFIG_S5P) += s5p_gpio.o +-obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o ++obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o + obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o + obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o + obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o +@@ -62,7 +61,7 @@ + obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o + obj-$(CONFIG_MSM_GPIO) += msm_gpio.o + obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o +-obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o ++obj-$(CONFIG_$(SPL_TPL_)PM8916_GPIO) += pm8916_gpio.o + obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o + obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o + obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o +diff -ruN u-boot-2021.10/drivers/gpio/mvmfp.c u-boot/drivers/gpio/mvmfp.c +--- u-boot-2021.10/drivers/gpio/mvmfp.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/mvmfp.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,55 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor <www.marvell.com> +- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, +- */ +- +-#include <common.h> +-#include <asm/io.h> +-#include <mvmfp.h> +-#include <asm/arch/mfp.h> +- +-/* +- * mfp_config +- * +- * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin +- * configuration registers to configure each GPIO/Function pin on the +- * SoC. +- * +- * This function reads the array of values for +- * MFPR_X registers and programms them into respective +- * Multi-Function Pin registers. +- * It supports - Alternate Function Selection programming. +- * +- * Whereas, +- * The Configureation value is constructed using MFP() +- * array consists of 32bit values as defined in MFP(xx,xx..) macro +- */ +-void mfp_config(u32 *mfp_cfgs) +-{ +- u32 *p_mfpr = NULL; +- u32 cfg_val, val; +- +- do { +- cfg_val = *mfp_cfgs++; +- /* exit if End of configuration table detected */ +- if (cfg_val == MFP_EOC) +- break; +- +- p_mfpr = (u32 *)(MV_MFPR_BASE +- + MFP_REG_GET_OFFSET(cfg_val)); +- +- /* Write a mfg register as per configuration */ +- val = 0; +- if (cfg_val & MFP_VALUE_MASK) +- val |= cfg_val & MFP_VALUE_MASK; +- +- writel(val, p_mfpr); +- } while (1); +- /* +- * perform a read-back of any MFPR register to make sure the +- * previous writings are finished +- */ +- readl(p_mfpr); +-} +diff -ruN u-boot-2021.10/drivers/gpio/mxc_gpio.c u-boot/drivers/gpio/mxc_gpio.c +--- u-boot-2021.10/drivers/gpio/mxc_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/mxc_gpio.c 2021-11-01 17:10:14.306256783 +0100 +@@ -44,7 +44,7 @@ + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, +-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ ++#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ + defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) +@@ -352,7 +352,7 @@ + { 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, + { 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, + { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, +-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ ++#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) + { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, +@@ -376,7 +376,7 @@ + { "gpio_mxc", &mxc_plat[0] }, + { "gpio_mxc", &mxc_plat[1] }, + { "gpio_mxc", &mxc_plat[2] }, +-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ ++#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) + { "gpio_mxc", &mxc_plat[3] }, +diff -ruN u-boot-2021.10/drivers/gpio/mxs_gpio.c u-boot/drivers/gpio/mxs_gpio.c +--- u-boot-2021.10/drivers/gpio/mxs_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/mxs_gpio.c 2021-11-01 17:10:14.306256783 +0100 +@@ -262,7 +262,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int mxs_of_to_plat(struct udevice *dev) + { + struct mxs_gpio_plat *plat = dev_get_plat(dev); +@@ -301,7 +301,7 @@ + .probe = mxs_gpio_probe, + .priv_auto = sizeof(struct mxs_gpio_priv), + .plat_auto = sizeof(struct mxs_gpio_plat), +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = mxs_gpio_ids, + .of_to_plat = mxs_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/gpio/omap_gpio.c u-boot/drivers/gpio/omap_gpio.c +--- u-boot-2021.10/drivers/gpio/omap_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/omap_gpio.c 2021-11-01 17:10:14.306256783 +0100 +@@ -336,7 +336,7 @@ + } + #endif + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id omap_gpio_ids[] = { + { .compatible = "ti,omap3-gpio" }, + { .compatible = "ti,omap4-gpio" }, +@@ -362,7 +362,7 @@ + .name = "gpio_omap", + .id = UCLASS_GPIO, + #if CONFIG_IS_ENABLED(OF_CONTROL) +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = omap_gpio_ids, + .of_to_plat = of_match_ptr(omap_gpio_of_to_plat), + .plat_auto = sizeof(struct omap_gpio_plat), +diff -ruN u-boot-2021.10/drivers/gpio/sandbox.c u-boot/drivers/gpio/sandbox.c +--- u-boot-2021.10/drivers/gpio/sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/sandbox.c 2021-11-01 17:10:14.306256783 +0100 +@@ -323,11 +323,13 @@ + + static int sandbox_gpio_of_to_plat(struct udevice *dev) + { +- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + +- uc_priv->gpio_count = dev_read_u32_default(dev, "sandbox,gpio-count", +- 0); +- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); ++ uc_priv->gpio_count = ++ dev_read_u32_default(dev, "sandbox,gpio-count", 0); ++ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); ++ } + + return 0; + } +@@ -371,6 +373,8 @@ + + DM_DRIVER_ALIAS(sandbox_gpio, sandbox_gpio_alias) + ++#if CONFIG_IS_ENABLED(PINCTRL) ++ + /* pincontrol: used only to check GPIO pin configuration (pinmux command) */ + + struct sb_pinctrl_priv { +@@ -579,3 +583,5 @@ + .priv_auto = sizeof(struct sb_pinctrl_priv), + ACPI_OPS_PTR(&pinctrl_sandbox_acpi_ops) + }; ++ ++#endif /* PINCTRL */ +diff -ruN u-boot-2021.10/drivers/gpio/sandbox_test.c u-boot/drivers/gpio/sandbox_test.c +--- u-boot-2021.10/drivers/gpio/sandbox_test.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/gpio/sandbox_test.c 2021-11-01 17:10:14.306256783 +0100 +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Sandbox driver for testing GPIOs with of-platdata ++ * ++ * Copyright 2021 Google LLC ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <asm-generic/gpio.h> ++ ++static const struct udevice_id sandbox_gpio_test_ids[] = { ++ { .compatible = "sandbox,gpio-test" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sandbox_gpio_test) = { ++ .name = "sandbox_gpio_test", ++ .id = UCLASS_MISC, ++ .of_match = sandbox_gpio_test_ids, ++}; +diff -ruN u-boot-2021.10/drivers/gpio/sunxi_gpio.c u-boot/drivers/gpio/sunxi_gpio.c +--- u-boot-2021.10/drivers/gpio/sunxi_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/sunxi_gpio.c 2021-11-01 17:10:14.306256783 +0100 +@@ -14,19 +14,13 @@ + #include <errno.h> + #include <fdtdec.h> + #include <malloc.h> +-#include <asm/arch/gpio.h> + #include <asm/io.h> + #include <asm/gpio.h> + #include <dm/device-internal.h> + #include <dt-bindings/gpio/gpio.h> + +-#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR +- +-struct sunxi_gpio_plat { +- struct sunxi_gpio *regs; +- const char *bank_name; /* Name of bank, e.g. "B" */ +- int gpio_count; +-}; ++#include "../../arch/arm/include/asm/arch-sunxi/gpio.h" ++#include "../../arch/arm/mach-sunxi/pinmux.c" + + #if !CONFIG_IS_ENABLED(DM_GPIO) + static int sunxi_gpio_output(u32 pin, u32 val) +@@ -118,65 +112,18 @@ + } + #endif /* DM_GPIO */ + +-int sunxi_name_to_gpio_bank(const char *name) +-{ +- int group = 0; +- +- if (*name == 'P' || *name == 'p') +- name++; +- if (*name >= 'A') { +- group = *name - (*name > 'a' ? 'a' : 'A'); +- return group; +- } +- +- return -1; +-} +- + #if CONFIG_IS_ENABLED(DM_GPIO) + /* TODO(sjg@chromium.org): Remove this function and use device tree */ + int sunxi_name_to_gpio(const char *name) + { + unsigned int gpio; + int ret; +-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +- char lookup[8]; + +- if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) { +- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d", +- SUNXI_GPIO_AXP0_VBUS_DETECT); +- name = lookup; +- } else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) { +- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d", +- SUNXI_GPIO_AXP0_VBUS_ENABLE); +- name = lookup; +- } +-#endif + ret = gpio_lookup_name(name, NULL, NULL, &gpio); + + return ret ? ret : gpio; + } + +-static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset) +-{ +- struct sunxi_gpio_plat *plat = dev_get_plat(dev); +- +- sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT); +- +- return 0; +-} +- +-static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset, +- int value) +-{ +- struct sunxi_gpio_plat *plat = dev_get_plat(dev); +- u32 num = GPIO_NUM(offset); +- +- sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); +- clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); +- +- return 0; +-} +- + static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) + { + struct sunxi_gpio_plat *plat = dev_get_plat(dev); +@@ -189,16 +136,6 @@ + return dat & 0x1; + } + +-static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset, +- int value) +-{ +- struct sunxi_gpio_plat *plat = dev_get_plat(dev); +- u32 num = GPIO_NUM(offset); +- +- clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); +- return 0; +-} +- + static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) + { + struct sunxi_gpio_plat *plat = dev_get_plat(dev); +@@ -222,42 +159,43 @@ + if (ret) + return ret; + desc->offset = args->args[1]; +- desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; ++ desc->flags = gpio_flags_xlate(args->args[2]); ++ ++ return 0; ++} ++ ++static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, ++ ulong flags) ++{ ++ struct sunxi_gpio_plat *plat = dev_get_plat(dev); ++ ++ if (flags & GPIOD_IS_OUT) { ++ u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); ++ u32 num = GPIO_NUM(offset); ++ ++ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); ++ clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); ++ } else if (flags & GPIOD_IS_IN) { ++ u32 pull = 0; ++ ++ if (flags & GPIOD_PULL_UP) ++ pull = 1; ++ else if (flags & GPIOD_PULL_DOWN) ++ pull = 2; ++ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT); ++ sunxi_gpio_set_pull_bank(plat->regs, offset, pull); ++ } + + return 0; + } + + static const struct dm_gpio_ops gpio_sunxi_ops = { +- .direction_input = sunxi_gpio_direction_input, +- .direction_output = sunxi_gpio_direction_output, + .get_value = sunxi_gpio_get_value, +- .set_value = sunxi_gpio_set_value, + .get_function = sunxi_gpio_get_function, + .xlate = sunxi_gpio_xlate, ++ .set_flags = sunxi_gpio_set_flags, + }; + +-/** +- * Returns the name of a GPIO bank +- * +- * GPIO banks are named A, B, C, ... +- * +- * @bank: Bank number (0, 1..n-1) +- * @return allocated string containing the name +- */ +-static char *gpio_bank_name(int bank) +-{ +- char *name; +- +- name = malloc(3); +- if (name) { +- name[0] = 'P'; +- name[1] = 'A' + bank; +- name[2] = '\0'; +- } +- +- return name; +-} +- + static int gpio_sunxi_probe(struct udevice *dev) + { + struct sunxi_gpio_plat *plat = dev_get_plat(dev); +@@ -265,114 +203,17 @@ + + /* Tell the uclass how many GPIOs we have */ + if (plat) { +- uc_priv->gpio_count = plat->gpio_count; ++ uc_priv->gpio_count = SUNXI_GPIOS_PER_BANK; + uc_priv->bank_name = plat->bank_name; + } + + return 0; + } + +-struct sunxi_gpio_soc_data { +- int start; +- int no_banks; +-}; +- +-/** +- * We have a top-level GPIO device with no actual GPIOs. It has a child +- * device for each Sunxi bank. +- */ +-static int gpio_sunxi_bind(struct udevice *parent) +-{ +- struct sunxi_gpio_soc_data *soc_data = +- (struct sunxi_gpio_soc_data *)dev_get_driver_data(parent); +- struct sunxi_gpio_plat *plat = dev_get_plat(parent); +- struct sunxi_gpio_reg *ctlr; +- int bank, ret; +- +- /* If this is a child device, there is nothing to do here */ +- if (plat) +- return 0; +- +- ctlr = dev_read_addr_ptr(parent); +- for (bank = 0; bank < soc_data->no_banks; bank++) { +- struct sunxi_gpio_plat *plat; +- struct udevice *dev; +- +- plat = calloc(1, sizeof(*plat)); +- if (!plat) +- return -ENOMEM; +- plat->regs = &ctlr->gpio_bank[bank]; +- plat->bank_name = gpio_bank_name(soc_data->start + bank); +- plat->gpio_count = SUNXI_GPIOS_PER_BANK; +- +- ret = device_bind(parent, parent->driver, plat->bank_name, plat, +- dev_ofnode(parent), &dev); +- if (ret) +- return ret; +- } +- +- return 0; +-} +- +-static const struct sunxi_gpio_soc_data soc_data_a_all = { +- .start = 0, +- .no_banks = SUNXI_GPIO_BANKS, +-}; +- +-static const struct sunxi_gpio_soc_data soc_data_l_1 = { +- .start = 'L' - 'A', +- .no_banks = 1, +-}; +- +-static const struct sunxi_gpio_soc_data soc_data_l_2 = { +- .start = 'L' - 'A', +- .no_banks = 2, +-}; +- +-static const struct sunxi_gpio_soc_data soc_data_l_3 = { +- .start = 'L' - 'A', +- .no_banks = 3, +-}; +- +-#define ID(_compat_, _soc_data_) \ +- { .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ } +- +-static const struct udevice_id sunxi_gpio_ids[] = { +- ID("allwinner,sun4i-a10-pinctrl", a_all), +- ID("allwinner,sun5i-a10s-pinctrl", a_all), +- ID("allwinner,sun5i-a13-pinctrl", a_all), +- ID("allwinner,sun50i-h5-pinctrl", a_all), +- ID("allwinner,sun6i-a31-pinctrl", a_all), +- ID("allwinner,sun6i-a31s-pinctrl", a_all), +- ID("allwinner,sun7i-a20-pinctrl", a_all), +- ID("allwinner,sun8i-a23-pinctrl", a_all), +- ID("allwinner,sun8i-a33-pinctrl", a_all), +- ID("allwinner,sun8i-a83t-pinctrl", a_all), +- ID("allwinner,sun8i-h3-pinctrl", a_all), +- ID("allwinner,sun8i-r40-pinctrl", a_all), +- ID("allwinner,sun8i-v3-pinctrl", a_all), +- ID("allwinner,sun8i-v3s-pinctrl", a_all), +- ID("allwinner,sun9i-a80-pinctrl", a_all), +- ID("allwinner,sun50i-a64-pinctrl", a_all), +- ID("allwinner,sun50i-h6-pinctrl", a_all), +- ID("allwinner,sun50i-h616-pinctrl", a_all), +- ID("allwinner,sun6i-a31-r-pinctrl", l_2), +- ID("allwinner,sun8i-a23-r-pinctrl", l_1), +- ID("allwinner,sun8i-a83t-r-pinctrl", l_1), +- ID("allwinner,sun8i-h3-r-pinctrl", l_1), +- ID("allwinner,sun9i-a80-r-pinctrl", l_3), +- ID("allwinner,sun50i-a64-r-pinctrl", l_1), +- ID("allwinner,sun50i-h6-r-pinctrl", l_2), +- ID("allwinner,sun50i-h616-r-pinctrl", l_1), +- { } +-}; +- + U_BOOT_DRIVER(gpio_sunxi) = { + .name = "gpio_sunxi", + .id = UCLASS_GPIO, +- .ops = &gpio_sunxi_ops, +- .of_match = sunxi_gpio_ids, +- .bind = gpio_sunxi_bind, + .probe = gpio_sunxi_probe, ++ .ops = &gpio_sunxi_ops, + }; + #endif /* DM_GPIO */ +diff -ruN u-boot-2021.10/drivers/gpio/tegra_gpio.c u-boot/drivers/gpio/tegra_gpio.c +--- u-boot-2021.10/drivers/gpio/tegra_gpio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/gpio/tegra_gpio.c 2021-11-01 17:10:14.306256783 +0100 +@@ -23,8 +23,8 @@ + #include <dm/device-internal.h> + #include <dt-bindings/gpio/gpio.h> + +-static const int CONFIG_SFIO = 0; +-static const int CONFIG_GPIO = 1; ++static const int CFG_SFIO = 0; ++static const int CFG_GPIO = 1; + static const int DIRECTION_INPUT = 0; + static const int DIRECTION_OUTPUT = 1; + +@@ -54,7 +54,7 @@ + debug("get_config: port = %d, bit = %d is %s\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); + +- return type ? CONFIG_GPIO : CONFIG_SFIO; ++ return type ? CFG_GPIO : CFG_SFIO; + } + + /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ +@@ -68,7 +68,7 @@ + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); + + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); +- if (type != CONFIG_SFIO) ++ if (type != CFG_SFIO) + u |= 1 << GPIO_BIT(gpio); + else + u &= ~(1 << GPIO_BIT(gpio)); +@@ -216,7 +216,7 @@ + set_direction(config[i].gpio, DIRECTION_OUTPUT); + break; + } +- set_config(config[i].gpio, CONFIG_GPIO); ++ set_config(config[i].gpio, CFG_GPIO); + } + } + +diff -ruN u-boot-2021.10/drivers/i2c/designware_i2c.c u-boot/drivers/i2c/designware_i2c.c +--- u-boot-2021.10/drivers/i2c/designware_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/designware_i2c.c 2021-11-01 17:10:14.309589934 +0100 +@@ -674,24 +674,6 @@ + dw_i2c_write, dw_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) + +-#if CONFIG_SYS_I2C_BUS_MAX >= 2 +-U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, +- dw_i2c_write, dw_i2c_set_bus_speed, +- CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) +-#endif +- +-#if CONFIG_SYS_I2C_BUS_MAX >= 3 +-U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, +- dw_i2c_write, dw_i2c_set_bus_speed, +- CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) +-#endif +- +-#if CONFIG_SYS_I2C_BUS_MAX >= 4 +-U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, +- dw_i2c_write, dw_i2c_set_bus_speed, +- CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) +-#endif +- + #else /* CONFIG_DM_I2C */ + /* The DM I2C functions */ + +diff -ruN u-boot-2021.10/drivers/i2c/designware_i2c.h u-boot/drivers/i2c/designware_i2c.h +--- u-boot-2021.10/drivers/i2c/designware_i2c.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/designware_i2c.h 2021-11-01 17:10:14.309589934 +0100 +@@ -112,7 +112,7 @@ + #define IC_TX_EMPTY 0x0010 + #define IC_TX_OVER 0x0008 + #define IC_RX_FULL 0x0004 +-#define IC_RX_OVER 0x0002 ++#define IC_RX_OVER 0x0002 + #define IC_RX_UNDER 0x0001 + + /* fifo threshold register definitions */ +diff -ruN u-boot-2021.10/drivers/i2c/fsl_i2c.c u-boot/drivers/i2c/fsl_i2c.c +--- u-boot-2021.10/drivers/i2c/fsl_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/fsl_i2c.c 2021-11-01 17:10:14.309589934 +0100 +@@ -538,24 +538,24 @@ + */ + U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, +- CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, ++ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 0) + #ifdef CONFIG_SYS_FSL_I2C2_OFFSET + U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, +- CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, ++ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 1) + #endif + #ifdef CONFIG_SYS_FSL_I2C3_OFFSET + U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, +- CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE, ++ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 2) + #endif + #ifdef CONFIG_SYS_FSL_I2C4_OFFSET + U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, + fsl_i2c_write, fsl_i2c_set_bus_speed, +- CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE, ++ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + 3) + #endif + #else /* CONFIG_DM_I2C */ +diff -ruN u-boot-2021.10/drivers/i2c/i2c_core.c u-boot/drivers/i2c/i2c_core.c +--- u-boot-2021.10/drivers/i2c/i2c_core.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/i2c_core.c 2021-11-01 17:10:14.309589934 +0100 +@@ -190,11 +190,6 @@ + { + } + +-/* implement possible for i2c specific early i2c init */ +-__weak void i2c_early_init_f(void) +-{ +-} +- + /* + * i2c_init_all(): + * +diff -ruN u-boot-2021.10/drivers/i2c/i2c-emul-uclass.c u-boot/drivers/i2c/i2c-emul-uclass.c +--- u-boot-2021.10/drivers/i2c/i2c-emul-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/i2c-emul-uclass.c 2021-11-01 17:10:14.309589934 +0100 +@@ -79,7 +79,7 @@ + UCLASS_DRIVER(i2c_emul_parent) = { + .id = UCLASS_I2C_EMUL_PARENT, + .name = "i2c_emul_parent", +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/drivers/i2c/i2c-uclass.c u-boot/drivers/i2c/i2c-uclass.c +--- u-boot-2021.10/drivers/i2c/i2c-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/i2c-uclass.c 2021-11-01 17:10:14.309589934 +0100 +@@ -633,7 +633,7 @@ + return ops->deblock(bus); + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip) + { + int addr; +@@ -655,7 +655,7 @@ + + static int i2c_pre_probe(struct udevice *dev) + { +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); + unsigned int max = 0; + ofnode node; +@@ -678,7 +678,7 @@ + + static int i2c_post_probe(struct udevice *dev) + { +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); + + i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency", +@@ -692,7 +692,7 @@ + + static int i2c_child_post_bind(struct udevice *dev) + { +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct dm_i2c_chip *plat = dev_get_parent_plat(dev); + + if (!dev_has_ofnode(dev)) +@@ -709,7 +709,7 @@ + + debug("%s: %s, seq=%d\n", __func__, dev->name, dev_seq(dev)); + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + ret = dm_scan_fdt_dev(dev); + #endif + return ret; +diff -ruN u-boot-2021.10/drivers/i2c/ihs_i2c.c u-boot/drivers/i2c/ihs_i2c.c +--- u-boot-2021.10/drivers/i2c/ihs_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/ihs_i2c.c 2021-11-01 17:10:14.309589934 +0100 +@@ -6,19 +6,14 @@ + + #include <common.h> + #include <i2c.h> +-#if CONFIG_IS_ENABLED(DM_I2C) + #include <dm.h> + #include <regmap.h> +-#else +-#include <gdsys_fpga.h> +-#endif + #include <log.h> + #include <asm/global_data.h> + #include <asm/unaligned.h> + #include <linux/bitops.h> + #include <linux/delay.h> + +-#if CONFIG_IS_ENABLED(DM_I2C) + struct ihs_i2c_priv { + uint speed; + struct regmap *map; +@@ -39,37 +34,6 @@ + #define ihs_i2c_get(map, member, valp) \ + regmap_get(map, struct ihs_i2c_regs, member, valp) + +-#else /* !CONFIG_DM_I2C */ +-DECLARE_GLOBAL_DATA_PTR; +- +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +- +-#define I2C_SET_REG(fld, val) \ +- do { \ +- if (I2C_ADAP_HWNR & 0x10) \ +- FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ +- else \ +- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ +- } while (0) +-#else +-#define I2C_SET_REG(fld, val) \ +- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) +-#endif +- +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +-#define I2C_GET_REG(fld, val) \ +- do { \ +- if (I2C_ADAP_HWNR & 0x10) \ +- FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ +- else \ +- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ +- } while (0) +-#else +-#define I2C_GET_REG(fld, val) \ +- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) +-#endif +-#endif /* CONFIG_DM_I2C */ +- + enum { + I2CINT_ERROR_EV = BIT(13), + I2CINT_TRANSMIT_EV = BIT(14), +@@ -91,23 +55,13 @@ + I2COP_READ = 1, + }; + +-#if CONFIG_IS_ENABLED(DM_I2C) + static int wait_for_int(struct udevice *dev, int read) +-#else +-static int wait_for_int(bool read) +-#endif + { + u16 val; + uint ctr = 0; +-#if CONFIG_IS_ENABLED(DM_I2C) + struct ihs_i2c_priv *priv = dev_get_priv(dev); +-#endif + +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_get(priv->map, interrupt_status, &val); +-#else +- I2C_GET_REG(interrupt_status, &val); +-#endif + /* Wait until error or receive/transmit interrupt was raised */ + while (!(val & (I2CINT_ERROR_EV + | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { +@@ -116,40 +70,24 @@ + debug("%s: timed out\n", __func__); + return -ETIMEDOUT; + } +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_get(priv->map, interrupt_status, &val); +-#else +- I2C_GET_REG(interrupt_status, &val); +-#endif + } + + return (val & I2CINT_ERROR_EV) ? -EIO : 0; + } + +-#if CONFIG_IS_ENABLED(DM_I2C) + static int ihs_i2c_transfer(struct udevice *dev, uchar chip, + uchar *buffer, int len, int read, bool is_last) +-#else +-static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, +- bool is_last) +-#endif + { + u16 val; + u16 data; + int res; +-#if CONFIG_IS_ENABLED(DM_I2C) + struct ihs_i2c_priv *priv = dev_get_priv(dev); +-#endif + + /* Clear interrupt status */ + data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_set(priv->map, interrupt_status, data); + ihs_i2c_get(priv->map, interrupt_status, &val); +-#else +- I2C_SET_REG(interrupt_status, data); +- I2C_GET_REG(interrupt_status, &val); +-#endif + + /* If we want to write and have data, write the bytes to the mailbox */ + if (!read && len) { +@@ -157,11 +95,7 @@ + + if (len > 1) + val |= buffer[1] << 8; +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_set(priv->map, write_mailbox_ext, val); +-#else +- I2C_SET_REG(write_mailbox_ext, val); +-#endif + } + + data = I2CMB_NATIVE +@@ -170,17 +104,9 @@ + | ((len > 1) ? I2CMB_2BYTE : 0) + | (is_last ? 0 : I2CMB_HOLD_BUS); + +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_set(priv->map, write_mailbox, data); +-#else +- I2C_SET_REG(write_mailbox, data); +-#endif + +-#if CONFIG_IS_ENABLED(DM_I2C) + res = wait_for_int(dev, read); +-#else +- res = wait_for_int(read); +-#endif + if (res) { + if (res == -ETIMEDOUT) + debug("%s: time out while waiting for event\n", __func__); +@@ -190,11 +116,7 @@ + + /* If we want to read, get the bytes from the mailbox */ + if (read) { +-#if CONFIG_IS_ENABLED(DM_I2C) + ihs_i2c_get(priv->map, read_mailbox_ext, &val); +-#else +- I2C_GET_REG(read_mailbox_ext, &val); +-#endif + buffer[0] = val & 0xff; + if (len > 1) + buffer[1] = val >> 8; +@@ -203,12 +125,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(DM_I2C) + static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read) +-#else +-static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, +- int read) +-#endif + { + int res; + +@@ -216,13 +133,8 @@ + int transfer = min(len, 2); + bool is_last = len <= transfer; + +-#if CONFIG_IS_ENABLED(DM_I2C) + res = ihs_i2c_transfer(dev, chip, data, transfer, read, + hold_bus ? false : is_last); +-#else +- res = ihs_i2c_transfer(chip, data, transfer, read, +- hold_bus ? false : is_last); +-#endif + if (res) + return res; + +@@ -233,27 +145,14 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(DM_I2C) + static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, + bool hold_bus) +-#else +-static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) +-#endif + { +-#if CONFIG_IS_ENABLED(DM_I2C) + return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE); +-#else +- return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE); +-#endif + } + +-#if CONFIG_IS_ENABLED(DM_I2C) + static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, + int alen, uchar *buffer, int len, int read) +-#else +-static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, +- int alen, uchar *buffer, int len, int read) +-#endif + { + int res; + +@@ -261,23 +160,13 @@ + if (len <= 0) + return -EINVAL; + +-#if CONFIG_IS_ENABLED(DM_I2C) + res = ihs_i2c_address(dev, chip, addr, alen, len); +-#else +- res = ihs_i2c_address(chip, addr, alen, len); +-#endif + if (res) + return res; + +-#if CONFIG_IS_ENABLED(DM_I2C) + return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); +-#else +- return ihs_i2c_send_buffer(chip, buffer, len, false, read); +-#endif + } + +-#if CONFIG_IS_ENABLED(DM_I2C) +- + int ihs_i2c_probe(struct udevice *bus) + { + struct ihs_i2c_priv *priv = dev_get_priv(bus); +@@ -358,120 +247,3 @@ + .priv_auto = sizeof(struct ihs_i2c_priv), + .ops = &ihs_i2c_ops, + }; +- +-#else /* CONFIG_DM_I2C */ +- +-static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +-{ +-#ifdef CONFIG_SYS_I2C_INIT_BOARD +- /* +- * Call board specific i2c bus reset routine before accessing the +- * environment, which might be in a chip on that bus. For details +- * about this problem see doc/I2C_Edge_Conditions. +- */ +- i2c_init_board(); +-#endif +-} +- +-static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) +-{ +- uchar buffer[2]; +- int res; +- +- res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true); +- if (res) +- return res; +- +- return 0; +-} +- +-static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, +- int alen, uchar *buffer, int len) +-{ +- u8 addr_bytes[4]; +- +- put_unaligned_le32(addr, addr_bytes); +- +- return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, +- I2COP_READ); +-} +- +-static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, +- int alen, uchar *buffer, int len) +-{ +- u8 addr_bytes[4]; +- +- put_unaligned_le32(addr, addr_bytes); +- +- return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, +- I2COP_WRITE); +-} +- +-static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, +- unsigned int speed) +-{ +- if (speed != adap->speed) +- return -EINVAL; +- return speed; +-} +- +-/* +- * Register IHS i2c adapters +- */ +-#ifdef CONFIG_SYS_I2C_IHS_CH0 +-U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_0, +- CONFIG_SYS_I2C_IHS_SLAVE_0, 0) +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +-U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_0_1, +- CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) +-#endif +-#endif +-#ifdef CONFIG_SYS_I2C_IHS_CH1 +-U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_1, +- CONFIG_SYS_I2C_IHS_SLAVE_1, 1) +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +-U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_1_1, +- CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) +-#endif +-#endif +-#ifdef CONFIG_SYS_I2C_IHS_CH2 +-U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_2, +- CONFIG_SYS_I2C_IHS_SLAVE_2, 2) +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +-U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_2_1, +- CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) +-#endif +-#endif +-#ifdef CONFIG_SYS_I2C_IHS_CH3 +-U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_3, +- CONFIG_SYS_I2C_IHS_SLAVE_3, 3) +-#ifdef CONFIG_SYS_I2C_IHS_DUAL +-U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, +- ihs_i2c_read, ihs_i2c_write, +- ihs_i2c_set_bus_speed, +- CONFIG_SYS_I2C_IHS_SPEED_3_1, +- CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) +-#endif +-#endif +-#endif /* CONFIG_DM_I2C */ +diff -ruN u-boot-2021.10/drivers/i2c/Kconfig u-boot/drivers/i2c/Kconfig +--- u-boot-2021.10/drivers/i2c/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/Kconfig 2021-11-01 17:10:14.309589934 +0100 +@@ -47,6 +47,35 @@ + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. + ++config SYS_I2C_LEGACY ++ bool "Enable legacy I2C subsystem and drivers" ++ depends on !DM_I2C ++ help ++ Enable the legacy I2C subsystem and drivers. While this is ++ deprecated in U-Boot itself, this can be useful in some situations ++ in SPL or TPL. ++ ++config SPL_SYS_I2C_LEGACY ++ bool "Enable legacy I2C subsystem and drivers in SPL" ++ depends on SUPPORT_SPL && !SPL_DM_I2C ++ help ++ Enable the legacy I2C subsystem and drivers in SPL. This is useful ++ in some size constrained situations. ++ ++config TPL_SYS_I2C_LEGACY ++ bool "Enable legacy I2C subsystem and drivers in TPL" ++ depends on SUPPORT_TPL && !SPL_DM_I2C ++ help ++ Enable the legacy I2C subsystem and drivers in TPL. This is useful ++ in some size constrained situations. ++ ++config SYS_I2C_EARLY_INIT ++ bool "Enable legacy I2C subsystem early in boot" ++ depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC ++ help ++ Add the function prototype for i2c_early_init_f which is called in ++ board_early_init_f. ++ + config I2C_CROS_EC_TUNNEL + tristate "Chrome OS EC tunnel I2C bus" + depends on CROS_EC +@@ -124,11 +153,36 @@ + + config SYS_I2C_FSL + bool "Freescale I2C bus driver" +- depends on DM_I2C + help + Add support for Freescale I2C busses as used on MPC8240, MPC8245, and + MPC85xx processors. + ++if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) ++config SYS_FSL_I2C_OFFSET ++ hex "Offset from the IMMR of the address of the first I2C controller" ++ ++config SYS_FSL_HAS_I2C2_OFFSET ++ bool "Support a second I2C controller" ++ ++config SYS_FSL_I2C2_OFFSET ++ hex "Offset from the IMMR of the address of the second I2C controller" ++ depends on SYS_FSL_HAS_I2C2_OFFSET ++ ++config SYS_FSL_HAS_I2C3_OFFSET ++ bool "Support a third I2C controller" ++ ++config SYS_FSL_I2C3_OFFSET ++ hex "Offset from the IMMR of the address of the third I2C controller" ++ depends on SYS_FSL_HAS_I2C3_OFFSET ++ ++config SYS_FSL_HAS_I2C4_OFFSET ++ bool "Support a fourth I2C controller" ++ ++config SYS_FSL_I2C4_OFFSET ++ hex "Offset from the IMMR of the address of the fourth I2C controller" ++ depends on SYS_FSL_HAS_I2C4_OFFSET ++endif ++ + config SYS_I2C_CADENCE + tristate "Cadence I2C Controller" + depends on DM_I2C +@@ -139,7 +193,6 @@ + config SYS_I2C_CA + tristate "Cortina-Access I2C Controller" + depends on DM_I2C && CORTINA_PLATFORM +- default n + help + Add support for the Cortina Access I2C host controller. + Say yes here to select Cortina-Access I2C Host Controller. +@@ -152,7 +205,6 @@ + + config SYS_I2C_DW + bool "Designware I2C Controller" +- default n + help + Say yes here to select the Designware I2C Host Controller. This + controller is used in various SoCs, e.g. the ST SPEAr, Altera +@@ -205,10 +257,7 @@ + channels and operating on standard mode up to 100 kbits/s and fast + mode up to 400 kbits/s. + +-# These settings are not used with DM_I2C, however SPL doesn't use +-# DM_I2C even if DM_I2C is enabled, and so might use these settings even +-# when main u-boot does not! +-if SYS_I2C_MXC && (!DM_I2C || SPL) ++if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) + config SYS_I2C_MXC_I2C1 + bool "NXP MXC I2C1" + help +@@ -267,7 +316,7 @@ + MXC I2C Channel 1 speed + + config SYS_MXC_I2C1_SLAVE +- int "I2C1 Slave" ++ hex "I2C1 Slave" + default 0 + help + MXC I2C1 Slave +@@ -282,7 +331,7 @@ + MXC I2C Channel 2 speed + + config SYS_MXC_I2C2_SLAVE +- int "I2C2 Slave" ++ hex "I2C2 Slave" + default 0 + help + MXC I2C2 Slave +@@ -296,7 +345,7 @@ + MXC I2C Channel 3 speed + + config SYS_MXC_I2C3_SLAVE +- int "I2C3 Slave" ++ hex "I2C3 Slave" + default 0 + help + MXC I2C3 Slave +@@ -310,7 +359,7 @@ + MXC I2C Channel 4 speed + + config SYS_MXC_I2C4_SLAVE +- int "I2C4 Slave" ++ hex "I2C4 Slave" + default 0 + help + MXC I2C4 Slave +@@ -324,7 +373,7 @@ + MXC I2C Channel 5 speed + + config SYS_MXC_I2C5_SLAVE +- int "I2C5 Slave" ++ hex "I2C5 Slave" + default 0 + help + MXC I2C5 Slave +@@ -338,7 +387,7 @@ + MXC I2C Channel 6 speed + + config SYS_MXC_I2C6_SLAVE +- int "I2C6 Slave" ++ hex "I2C6 Slave" + default 0 + help + MXC I2C6 Slave +@@ -352,7 +401,7 @@ + MXC I2C Channel 7 speed + + config SYS_MXC_I2C7_SLAVE +- int "I2C7 Slave" ++ hex "I2C7 Slave" + default 0 + help + MXC I2C7 Slave +@@ -366,7 +415,7 @@ + MXC I2C Channel 8 speed + + config SYS_MXC_I2C8_SLAVE +- int "I2C8 Slave" ++ hex "I2C8 Slave" + default 0 + help + MXC I2C8 Slave +@@ -394,20 +443,6 @@ + help + Add support for the OMAP2+ I2C driver. + +-if SYS_I2C_OMAP24XX +-config SYS_OMAP24_I2C_SLAVE +- int "I2C Slave addr channel 0" +- default 1 +- help +- OMAP24xx I2C Slave address channel 0 +- +-config SYS_OMAP24_I2C_SPEED +- int "I2C Slave channel 0 speed" +- default 100000 +- help +- OMAP24xx Slave speed channel 0 +-endif +- + config SYS_I2C_RCAR_I2C + bool "Renesas RCar I2C driver" + depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C +@@ -437,6 +472,73 @@ + bus. Devices can be attached to the bus using the device tree + which specifies the driver to use. See sandbox.dts as an example. + ++config SYS_I2C_SH ++ bool "Legacy SuperH I2C interface" ++ depends on ARCH_RMOBILE && SYS_I2C_LEGACY ++ help ++ Enable the legacy SuperH I2C interface. ++ ++if SYS_I2C_SH ++config SYS_I2C_SH_NUM_CONTROLLERS ++ int ++ default 5 ++ ++config SYS_I2C_SH_BASE0 ++ hex ++ default 0xE6820000 ++ ++config SYS_I2C_SH_BASE1 ++ hex ++ default 0xE6822000 ++ ++config SYS_I2C_SH_BASE2 ++ hex ++ default 0xE6824000 ++ ++config SYS_I2C_SH_BASE3 ++ hex ++ default 0xE6826000 ++ ++config SYS_I2C_SH_BASE4 ++ hex ++ default 0xE6828000 ++ ++config SH_I2C_8BIT ++ bool ++ default y ++ ++config SH_I2C_DATA_HIGH ++ int ++ default 4 ++ ++config SH_I2C_DATA_LOW ++ int ++ default 5 ++ ++config SH_I2C_CLOCK ++ int ++ default 104000000 ++endif ++ ++config SYS_I2C_SOFT ++ bool "Legacy software I2C interface" ++ help ++ Enable the legacy software defined I2C interface ++ ++config SYS_I2C_SOFT_SPEED ++ int "Software I2C bus speed" ++ depends on SYS_I2C_SOFT ++ default 100000 ++ help ++ Speed of the software I2C bus ++ ++config SYS_I2C_SOFT_SLAVE ++ hex "Software I2C slave address" ++ depends on SYS_I2C_SOFT ++ default 0xfe ++ help ++ Slave address of the software I2C bus ++ + config SYS_I2C_OCTEON + bool "Octeon II/III/TX/TX2 I2C driver" + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C +@@ -449,7 +551,7 @@ + + config SYS_I2C_S3C24X0 + bool "Samsung I2C driver" +- depends on ARCH_EXYNOS4 && DM_I2C ++ depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C + help + Support for Samsung I2C controller as Samsung SoCs. + +@@ -473,6 +575,22 @@ + _ Optional clock stretching + _ Software reset + ++config SUN6I_P2WI ++ bool "Allwinner sun6i P2WI controller" ++ depends on ARCH_SUNXI ++ help ++ Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded ++ in the Allwinner A31 and A31s SOCs. This interface is used to connect ++ to specific devices like the X-Powers AXP221 PMIC. ++ ++config SUN8I_RSB ++ bool "Allwinner sun8i Reduced Serial Bus controller" ++ depends on ARCH_SUNXI ++ help ++ Support for Allwinner's Reduced Serial Bus (RSB) controller. This ++ controller is responsible for communicating with various RSB based ++ devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. ++ + config SYS_I2C_SYNQUACER + bool "Socionext SynQuacer I2C controller" + depends on ARCH_SYNQUACER && DM_I2C +@@ -511,7 +629,6 @@ + + config SYS_I2C_MVTWSI + bool "Marvell I2C driver" +- depends on DM_I2C + help + Support for Marvell I2C controllers as used on the orion5x and + kirkwood SoC families. +@@ -526,6 +643,25 @@ + by the BPMP, and can only be accessed by the main CPU via IPC + requests to the BPMP. This driver covers the latter case. + ++config SYS_I2C_SLAVE ++ hex "I2C Slave address channel (all buses)" ++ depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY ++ default 0xfe ++ help ++ I2C Slave address channel 0 for all buses in the legacy drivers. ++ Many boards/controllers/drivers don't support an I2C slave ++ interface so provide a default slave address for them for use in ++ common code. A real value for CONFIG_SYS_I2C_SLAVE should be ++ defined for any board which does support a slave interface and ++ this default used otherwise. ++ ++config SYS_I2C_SPEED ++ int "I2C Slave channel 0 speed (all buses)" ++ depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY ++ default 100000 ++ help ++ I2C Slave speed channel 0 for all buses in the legacy drivers. ++ + config SYS_I2C_BUS_MAX + int "Max I2C busses" + depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA +diff -ruN u-boot-2021.10/drivers/i2c/Makefile u-boot/drivers/i2c/Makefile +--- u-boot-2021.10/drivers/i2c/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/Makefile 2021-11-01 17:10:14.309589934 +0100 +@@ -11,7 +11,7 @@ + obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o + + obj-$(CONFIG_I2C_MV) += mv_i2c.o +-obj-$(CONFIG_SYS_I2C_LEGACY) += i2c_core.o ++obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o + obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o + obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o + obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o +@@ -43,6 +43,8 @@ + obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o + obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o + obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o ++obj-$(CONFIG_SUN6I_P2WI) += sun6i_p2wi.o ++obj-$(CONFIG_SUN8I_RSB) += sun8i_rsb.o + obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o + obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o + obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o +diff -ruN u-boot-2021.10/drivers/i2c/mv_i2c.c u-boot/drivers/i2c/mv_i2c.c +--- u-boot-2021.10/drivers/i2c/mv_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/mv_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -80,7 +80,7 @@ + + i2c_clk_enable(); + +- writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ ++ writel(0x0, &base->isar); /* set our slave address */ + /* set control reg values */ + writel(I2C_ICR_INIT | icr_mode, &base->icr); + writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ +diff -ruN u-boot-2021.10/drivers/i2c/mvtwsi.c u-boot/drivers/i2c/mvtwsi.c +--- u-boot-2021.10/drivers/i2c/mvtwsi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/mvtwsi.c 2021-11-01 17:10:14.312923085 +0100 +@@ -17,7 +17,9 @@ + #include <linux/bitops.h> + #include <linux/compat.h> + #if CONFIG_IS_ENABLED(DM_I2C) ++#include <clk.h> + #include <dm.h> ++#include <reset.h> + #endif + + DECLARE_GLOBAL_DATA_PTR; +@@ -835,7 +837,18 @@ + static int mvtwsi_i2c_probe(struct udevice *bus) + { + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); ++ struct reset_ctl reset; ++ struct clk clk; + uint actual_speed; ++ int ret; ++ ++ ret = reset_get_by_index(bus, 0, &reset); ++ if (!ret) ++ reset_deassert(&reset); ++ ++ ret = clk_get_by_index(bus, 0, &clk); ++ if (!ret) ++ clk_enable(&clk); + + __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); + dev->speed = actual_speed; +diff -ruN u-boot-2021.10/drivers/i2c/mxc_i2c.c u-boot/drivers/i2c/mxc_i2c.c +--- u-boot-2021.10/drivers/i2c/mxc_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/mxc_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -110,32 +110,6 @@ + }; + #endif + +-#ifndef CONFIG_SYS_MXC_I2C1_SPEED +-#define CONFIG_SYS_MXC_I2C1_SPEED 100000 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C2_SPEED +-#define CONFIG_SYS_MXC_I2C2_SPEED 100000 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C3_SPEED +-#define CONFIG_SYS_MXC_I2C3_SPEED 100000 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C4_SPEED +-#define CONFIG_SYS_MXC_I2C4_SPEED 100000 +-#endif +- +-#ifndef CONFIG_SYS_MXC_I2C1_SLAVE +-#define CONFIG_SYS_MXC_I2C1_SLAVE 0 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C2_SLAVE +-#define CONFIG_SYS_MXC_I2C2_SLAVE 0 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C3_SLAVE +-#define CONFIG_SYS_MXC_I2C3_SLAVE 0 +-#endif +-#ifndef CONFIG_SYS_MXC_I2C4_SLAVE +-#define CONFIG_SYS_MXC_I2C4_SLAVE 0 +-#endif +- + /* + * Calculate and set proper clock divider + */ +@@ -798,8 +772,6 @@ + bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); + } + +- +- + /* + * Init I2C Bus + */ +diff -ruN u-boot-2021.10/drivers/i2c/omap24xx_i2c.c u-boot/drivers/i2c/omap24xx_i2c.c +--- u-boot-2021.10/drivers/i2c/omap24xx_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/omap24xx_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -936,62 +936,34 @@ + return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); + } + +-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) +-#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED +-#endif +-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) +-#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE +-#endif +- + U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, +- CONFIG_SYS_OMAP24_I2C_SPEED, +- CONFIG_SYS_OMAP24_I2C_SLAVE, ++ CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE, + 0) + U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, +- CONFIG_SYS_OMAP24_I2C_SPEED1, +- CONFIG_SYS_OMAP24_I2C_SLAVE1, ++ CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE, + 1) + + #if (CONFIG_SYS_I2C_BUS_MAX > 2) +-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) +-#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED +-#endif +-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) +-#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE +-#endif +- + U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, +- CONFIG_SYS_OMAP24_I2C_SPEED2, +- CONFIG_SYS_OMAP24_I2C_SLAVE2, ++ CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE, + 2) + #if (CONFIG_SYS_I2C_BUS_MAX > 3) +-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) +-#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED +-#endif +-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) +-#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE +-#endif +- + U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, +- CONFIG_SYS_OMAP24_I2C_SPEED3, +- CONFIG_SYS_OMAP24_I2C_SLAVE3, ++ CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE, + 3) + #if (CONFIG_SYS_I2C_BUS_MAX > 4) +-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) +-#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED +-#endif +-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) +-#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE +-#endif +- + U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, +- CONFIG_SYS_OMAP24_I2C_SPEED4, +- CONFIG_SYS_OMAP24_I2C_SLAVE4, ++ CONFIG_SYS_I2C_SPEED, ++ CONFIG_SYS_I2C_SLAVE, + 4) + #endif + #endif +@@ -1062,7 +1034,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int omap_i2c_of_to_plat(struct udevice *bus) + { + struct omap_i2c_plat *plat = dev_get_plat(bus); +@@ -1091,7 +1063,7 @@ + U_BOOT_DRIVER(i2c_omap) = { + .name = "i2c_omap", + .id = UCLASS_I2C, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = omap_i2c_ids, + .of_to_plat = omap_i2c_of_to_plat, + .plat_auto = sizeof(struct omap_i2c_plat), +diff -ruN u-boot-2021.10/drivers/i2c/rcar_i2c.c u-boot/drivers/i2c/rcar_i2c.c +--- u-boot-2021.10/drivers/i2c/rcar_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/rcar_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -64,6 +64,8 @@ + struct rcar_i2c_priv { + void __iomem *base; + struct clk clk; ++ u32 fall_ns; ++ u32 rise_ns; + u32 intdelay; + u32 icccr; + enum rcar_i2c_type type; +@@ -278,7 +280,7 @@ + * = F[sum * ick / 1000000000] + * = F[(ick / 1000000) * sum / 1000] + */ +- sum = 35 + 200 + priv->intdelay; ++ sum = priv->fall_ns + priv->rise_ns + priv->intdelay; + round = (ick + 500000) / 1000000 * sum; + round = (round + 500) / 1000; + +@@ -323,6 +325,10 @@ + int ret; + + priv->base = dev_read_addr_ptr(dev); ++ priv->rise_ns = dev_read_u32_default(dev, ++ "i2c-scl-rising-time-ns", 200); ++ priv->fall_ns = dev_read_u32_default(dev, ++ "i2c-scl-falling-time-ns", 35); + priv->intdelay = dev_read_u32_default(dev, + "i2c-scl-internal-delay-ns", 5); + priv->type = dev_get_driver_data(dev); +diff -ruN u-boot-2021.10/drivers/i2c/s3c24x0_i2c.c u-boot/drivers/i2c/s3c24x0_i2c.c +--- u-boot-2021.10/drivers/i2c/s3c24x0_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/s3c24x0_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -21,12 +21,6 @@ + #include <i2c.h> + #include "s3c24x0_i2c.h" + +-#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE +-#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 +-#else +-#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE +-#endif +- + DECLARE_GLOBAL_DATA_PTR; + + /* +@@ -83,6 +77,8 @@ + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + } + ++#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 ++ + static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) + { + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); +diff -ruN u-boot-2021.10/drivers/i2c/sh_i2c.c u-boot/drivers/i2c/sh_i2c.c +--- u-boot-2021.10/drivers/i2c/sh_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/sh_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -294,20 +294,20 @@ + * Register RCAR i2c adapters + */ + U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, +- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) ++ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0) + #ifdef CONFIG_SYS_I2C_SH_BASE1 + U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, +- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) ++ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1) + #endif + #ifdef CONFIG_SYS_I2C_SH_BASE2 + U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, +- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) ++ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2) + #endif + #ifdef CONFIG_SYS_I2C_SH_BASE3 + U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, +- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) ++ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3) + #endif + #ifdef CONFIG_SYS_I2C_SH_BASE4 + U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, +- sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) ++ sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4) + #endif +diff -ruN u-boot-2021.10/drivers/i2c/soft_i2c.c u-boot/drivers/i2c/soft_i2c.c +--- u-boot-2021.10/drivers/i2c/soft_i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/i2c/soft_i2c.c 2021-11-01 17:10:14.312923085 +0100 +@@ -438,80 +438,3 @@ + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE, + 0) +-#if defined(I2C_SOFT_DECLARATIONS2) +-U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_2, +- CONFIG_SYS_I2C_SOFT_SLAVE_2, +- 1) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS3) +-U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_3, +- CONFIG_SYS_I2C_SOFT_SLAVE_3, +- 2) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS4) +-U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_4, +- CONFIG_SYS_I2C_SOFT_SLAVE_4, +- 3) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS5) +-U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_5, +- CONFIG_SYS_I2C_SOFT_SLAVE_5, +- 4) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS6) +-U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_6, +- CONFIG_SYS_I2C_SOFT_SLAVE_6, +- 5) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS7) +-U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_7, +- CONFIG_SYS_I2C_SOFT_SLAVE_7, +- 6) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS8) +-U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_8, +- CONFIG_SYS_I2C_SOFT_SLAVE_8, +- 7) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS9) +-U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_9, +- CONFIG_SYS_I2C_SOFT_SLAVE_9, +- 8) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS10) +-U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_10, +- CONFIG_SYS_I2C_SOFT_SLAVE_10, +- 9) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS11) +-U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_11, +- CONFIG_SYS_I2C_SOFT_SLAVE_11, +- 10) +-#endif +-#if defined(I2C_SOFT_DECLARATIONS12) +-U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe, +- soft_i2c_read, soft_i2c_write, NULL, +- CONFIG_SYS_I2C_SOFT_SPEED_12, +- CONFIG_SYS_I2C_SOFT_SLAVE_12, +- 11) +-#endif +diff -ruN u-boot-2021.10/drivers/i2c/sun6i_p2wi.c u-boot/drivers/i2c/sun6i_p2wi.c +--- u-boot-2021.10/drivers/i2c/sun6i_p2wi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/i2c/sun6i_p2wi.c 2021-11-01 17:10:14.316256235 +0100 +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <axp_pmic.h> ++#include <dm.h> ++#include <i2c.h> ++#include <asm/arch/p2wi.h> ++ ++#if CONFIG_IS_ENABLED(DM_I2C) ++ ++static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) ++{ ++ /* The hardware only supports SMBus-style transfers. */ ++ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1) ++ return p2wi_read(msg[0].buf[0], msg[1].buf); ++ ++ if (nmsgs == 1 && msg[0].len == 2) ++ return p2wi_write(msg[0].buf[0], msg[0].buf[1]); ++ ++ return -EINVAL; ++} ++ ++static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr, ++ uint chip_flags) ++{ ++ return p2wi_change_to_p2wi_mode(chip_addr, ++ AXP_PMIC_MODE_REG, ++ AXP_PMIC_MODE_P2WI); ++} ++ ++static int sun6i_p2wi_probe(struct udevice *bus) ++{ ++ p2wi_init(); ++ ++ return 0; ++} ++ ++static int sun6i_p2wi_child_pre_probe(struct udevice *child) ++{ ++ struct dm_i2c_chip *chip = dev_get_parent_plat(child); ++ ++ /* Ensure each transfer is for a single register. */ ++ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; ++ ++ return 0; ++} ++ ++static const struct dm_i2c_ops sun6i_p2wi_ops = { ++ .xfer = sun6i_p2wi_xfer, ++ .probe_chip = sun6i_p2wi_probe_chip, ++}; ++ ++static const struct udevice_id sun6i_p2wi_ids[] = { ++ { .compatible = "allwinner,sun6i-a31-p2wi" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(sun6i_p2wi) = { ++ .name = "sun6i_p2wi", ++ .id = UCLASS_I2C, ++ .of_match = sun6i_p2wi_ids, ++ .probe = sun6i_p2wi_probe, ++ .child_pre_probe = sun6i_p2wi_child_pre_probe, ++ .ops = &sun6i_p2wi_ops, ++}; ++ ++#endif /* CONFIG_IS_ENABLED(DM_I2C) */ +diff -ruN u-boot-2021.10/drivers/i2c/sun8i_rsb.c u-boot/drivers/i2c/sun8i_rsb.c +--- u-boot-2021.10/drivers/i2c/sun8i_rsb.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/i2c/sun8i_rsb.c 2021-11-01 17:10:14.316256235 +0100 +@@ -0,0 +1,86 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <axp_pmic.h> ++#include <dm.h> ++#include <i2c.h> ++#include <asm/arch/rsb.h> ++ ++#if CONFIG_IS_ENABLED(DM_I2C) ++ ++/* ++ * The mapping from hardware address to runtime address is fixed, and shared ++ * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux. ++ */ ++static int sun8i_rsb_get_runtime_address(u16 device_addr) ++{ ++ if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR) ++ return AXP_PMIC_PRI_RUNTIME_ADDR; ++ if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR) ++ return AXP_PMIC_SEC_RUNTIME_ADDR; ++ ++ return -ENOTSUPP; ++} ++ ++static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) ++{ ++ int rtaddr = sun8i_rsb_get_runtime_address(msg->addr); ++ ++ if (rtaddr < 0) ++ return rtaddr; ++ ++ /* The hardware only supports SMBus-style transfers. */ ++ if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1) ++ return rsb_read(rtaddr, msg[0].buf[0], msg[1].buf); ++ ++ if (nmsgs == 1 && msg[0].len == 2) ++ return rsb_write(rtaddr, msg[0].buf[0], msg[0].buf[1]); ++ ++ return -EINVAL; ++} ++ ++static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr, ++ uint chip_flags) ++{ ++ int rtaddr = sun8i_rsb_get_runtime_address(chip_addr); ++ ++ if (rtaddr < 0) ++ return rtaddr; ++ ++ return rsb_set_device_address(chip_addr, rtaddr); ++} ++ ++static int sun8i_rsb_probe(struct udevice *bus) ++{ ++ return rsb_init(); ++} ++ ++static int sun8i_rsb_child_pre_probe(struct udevice *child) ++{ ++ struct dm_i2c_chip *chip = dev_get_parent_plat(child); ++ ++ /* Ensure each transfer is for a single register. */ ++ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; ++ ++ return 0; ++} ++ ++static const struct dm_i2c_ops sun8i_rsb_ops = { ++ .xfer = sun8i_rsb_xfer, ++ .probe_chip = sun8i_rsb_probe_chip, ++}; ++ ++static const struct udevice_id sun8i_rsb_ids[] = { ++ { .compatible = "allwinner,sun8i-a23-rsb" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(sun8i_rsb) = { ++ .name = "sun8i_rsb", ++ .id = UCLASS_I2C, ++ .of_match = sun8i_rsb_ids, ++ .probe = sun8i_rsb_probe, ++ .child_pre_probe = sun8i_rsb_child_pre_probe, ++ .ops = &sun8i_rsb_ops, ++}; ++ ++#endif /* CONFIG_IS_ENABLED(DM_I2C) */ +diff -ruN u-boot-2021.10/drivers/input/i8042.c u-boot/drivers/input/i8042.c +--- u-boot-2021.10/drivers/input/i8042.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/input/i8042.c 2021-11-01 17:10:14.316256235 +0100 +@@ -150,8 +150,8 @@ + else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR) + config = kbd_cmd_read(CMD_RD_CONFIG); + +- config |= CONFIG_AT_TRANS; +- config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN); ++ config |= CFG_AT_TRANS; ++ config &= ~(CFG_KIRQ_EN | CFG_MIRQ_EN); + if (kbd_cmd_write(CMD_WR_CONFIG, config)) + goto err; + +diff -ruN u-boot-2021.10/drivers/Makefile u-boot/drivers/Makefile +--- u-boot-2021.10/drivers/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/Makefile 2021-11-01 17:10:14.246260064 +0100 +@@ -1,9 +1,12 @@ + # SPDX-License-Identifier: GPL-2.0+ + ++obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ + obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ + obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ + obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ + obj-$(CONFIG_$(SPL_TPL_)DM) += core/ ++obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/ ++obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/ + obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ + obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/ + obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/ +@@ -12,48 +15,40 @@ + obj-$(CONFIG_$(SPL_TPL_)I2C) += i2c/ + obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ + obj-$(CONFIG_$(SPL_TPL_)LED) += led/ +-obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ ++obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/ + obj-y += mtd/ + obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux/ +-obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/ ++obj-$(CONFIG_$(SPL_TPL_)ETH) += net/ ++obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/ + obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ + obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ + obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ ++obj-$(CONFIG_$(SPL_TPL_)POWER) += power/ + obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ +-obj-$(CONFIG_$(SPL_TPL_)RTC_SUPPORT) += rtc/ +-obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ +-obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ ++obj-$(CONFIG_$(SPL_TPL_)RTC) += rtc/ ++obj-$(CONFIG_$(SPL_TPL_)SERIAL) += serial/ ++obj-$(CONFIG_$(SPL_TPL_)SPI) += spi/ + obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ + obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ + obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ + obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ + obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ + obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ +-obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/ + obj-$(CONFIG_XEN) += xen/ + obj-$(CONFIG_$(SPL_)FPGA) += fpga/ + + ifndef CONFIG_TPL_BUILD + ifdef CONFIG_SPL_BUILD + +-obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ +-obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/ + obj-$(CONFIG_SPL_CPU) += cpu/ + obj-$(CONFIG_SPL_CRYPTO) += crypto/ +-obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ ++obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/ + obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ + obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ + obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ + obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ + obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ +-obj-$(CONFIG_SPL_POWER) += power/ power/pmic/ +-obj-$(CONFIG_SPL_POWER) += power/regulator/ +-obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ + obj-$(CONFIG_SPL_DM_RESET) += reset/ +-obj-$(CONFIG_SPL_DMA) += dma/ +-obj-$(CONFIG_SPL_ETH) += net/ +-obj-$(CONFIG_SPL_ETH) += net/phy/ +-obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ + obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ + obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ + obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ +@@ -61,7 +56,7 @@ + obj-$(CONFIG_SPL_WATCHDOG) += watchdog/ + obj-$(CONFIG_SPL_USB_HOST) += usb/host/ + obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ +-obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ ++obj-$(CONFIG_SPL_SATA) += ata/ scsi/ + obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ + obj-$(CONFIG_SPL_THERMAL) += thermal/ + +@@ -70,8 +65,7 @@ + + ifdef CONFIG_TPL_BUILD + +-obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/ +-obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ ++obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/ + + endif + +@@ -83,7 +77,6 @@ + obj-$(CONFIG_DM_DEMO) += demo/ + obj-$(CONFIG_BIOSEMU) += bios_emulator/ + obj-y += block/ +-obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ + obj-y += cache/ + obj-$(CONFIG_CPU) += cpu/ + obj-y += crypto/ +diff -ruN u-boot-2021.10/drivers/memory/ti-aemif.c u-boot/drivers/memory/ti-aemif.c +--- u-boot-2021.10/drivers/memory/ti-aemif.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/memory/ti-aemif.c 2021-11-01 17:10:14.316256235 +0100 +@@ -9,11 +9,10 @@ + #include <common.h> + #include <asm/ti-common/ti-aemif.h> + +-#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4) +-#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60) +-#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c) +-#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ +- + (cs * 4)) ++#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4) ++#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60) ++#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c) ++#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4)) + + #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) + #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +diff -ruN u-boot-2021.10/drivers/misc/atsha204a-i2c.c u-boot/drivers/misc/atsha204a-i2c.c +--- u-boot-2021.10/drivers/misc/atsha204a-i2c.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/atsha204a-i2c.c 2021-11-01 17:10:14.319589387 +0100 +@@ -2,8 +2,8 @@ + * I2C Driver for Atmel ATSHA204 over I2C + * + * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com +- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com +- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz ++ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com ++ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as +@@ -40,11 +40,11 @@ + * + * int i, j; + * for (i = 0; i < 256; ++i) { +- * u8 c = 0; +- * for (j = 0; j < 8; ++j) { +- * c = (c << 1) | ((i >> j) & 1); +- * } +- * bitreverse_table[i] = c; ++ * u8 c = 0; ++ * for (j = 0; j < 8; ++j) { ++ * c = (c << 1) | ((i >> j) & 1); ++ * } ++ * bitreverse_table[i] = c; + * } + */ + +@@ -88,14 +88,14 @@ + * + * int i, j; + * for (i = 0; i < 256; ++i) { +- * u16 c = i << 8; +- * for (j = 0; j < 8; ++j) { +- * int b = c >> 15; +- * c <<= 1; +- * if (b) +- * c ^= 0x8005; +- * } +- * crc16_table[i] = c; ++ * u16 c = i << 8; ++ * for (j = 0; j < 8; ++j) { ++ * int b = c >> 15; ++ * c <<= 1; ++ * if (b) ++ * c ^= 0x8005; ++ * } ++ * crc16_table[i] = c; + * } + */ + static u16 const crc16_table[256] = { +@@ -339,7 +339,7 @@ + retry--; + atsha204a_wakeup(dev); + } while (retry >= 0); +- ++ + if (res) { + debug("ATSHA204A read failed\n"); + return res; +diff -ruN u-boot-2021.10/drivers/misc/cros_ec.c u-boot/drivers/misc/cros_ec.c +--- u-boot-2021.10/drivers/misc/cros_ec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/cros_ec.c 2021-11-01 17:10:14.319589387 +0100 +@@ -414,7 +414,7 @@ + + int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan) + { +- if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, ++ if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan, + sizeof(scan->data)) != sizeof(scan->data)) + return -1; + +@@ -1671,7 +1671,7 @@ + .id = UCLASS_CROS_EC, + .name = "cros-ec", + .per_device_auto = sizeof(struct cros_ec_dev), +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + .flags = DM_UC_FLAG_ALLOC_PRIV_DMA, +diff -ruN u-boot-2021.10/drivers/misc/fsl_devdis.c u-boot/drivers/misc/fsl_devdis.c +--- u-boot-2021.10/drivers/misc/fsl_devdis.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/fsl_devdis.c 2021-11-01 17:10:14.319589387 +0100 +@@ -25,4 +25,3 @@ + tbl[i].mask); + } + } +- +diff -ruN u-boot-2021.10/drivers/misc/irq_sandbox.c u-boot/drivers/misc/irq_sandbox.c +--- u-boot-2021.10/drivers/misc/irq_sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/irq_sandbox.c 2021-11-01 17:10:14.319589387 +0100 +@@ -9,19 +9,9 @@ + #include <dm.h> + #include <irq.h> + #include <acpi/acpi_device.h> ++#include <asm/irq.h> + #include <asm/test.h> + +-/** +- * struct sandbox_irq_priv - private data for this driver +- * +- * @count: Counts the number calls to the read_and_clear() method +- * @pending: true if an interrupt is pending, else false +- */ +-struct sandbox_irq_priv { +- int count; +- bool pending; +-}; +- + static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low) + { + if (irq > 10) +@@ -103,10 +93,11 @@ + { } + }; + +-U_BOOT_DRIVER(sandbox_irq_drv) = { ++U_BOOT_DRIVER(sandbox_irq) = { + .name = "sandbox_irq", + .id = UCLASS_IRQ, + .of_match = sandbox_irq_ids, + .ops = &sandbox_irq_ops, + .priv_auto = sizeof(struct sandbox_irq_priv), ++ DM_HEADER(<asm/irq.h>) + }; +diff -ruN u-boot-2021.10/drivers/misc/irq_sandbox_test.c u-boot/drivers/misc/irq_sandbox_test.c +--- u-boot-2021.10/drivers/misc/irq_sandbox_test.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/misc/irq_sandbox_test.c 2021-11-01 17:10:14.319589387 +0100 +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Sandbox driver for testing interrupts with of-platdata ++ * ++ * Copyright 2021 Google LLC ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <irq.h> ++#include <asm/irq.h> ++ ++static const struct udevice_id sandbox_irq_test_ids[] = { ++ { .compatible = "sandbox,irq-test" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sandbox_irq_test) = { ++ .name = "sandbox_irq_test", ++ .id = UCLASS_MISC, ++ .of_match = sandbox_irq_test_ids, ++}; +diff -ruN u-boot-2021.10/drivers/misc/irq-uclass.c u-boot/drivers/misc/irq-uclass.c +--- u-boot-2021.10/drivers/misc/irq-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/irq-uclass.c 2021-11-01 17:10:14.319589387 +0100 +@@ -64,8 +64,8 @@ + } + + #if CONFIG_IS_ENABLED(OF_PLATDATA) +-int irq_get_by_driver_info(struct udevice *dev, +- struct phandle_1_arg *cells, struct irq *irq) ++int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells, ++ struct irq *irq) + { + int ret; + +@@ -74,6 +74,12 @@ + return ret; + irq->id = cells->arg[0]; + ++ /* ++ * Note: we could call irq_of_xlate_default() here to do this properly. ++ * For now, this is good enough for existing cases. ++ */ ++ irq->flags = cells->arg[1]; ++ + return 0; + } + #else +diff -ruN u-boot-2021.10/drivers/misc/Kconfig u-boot/drivers/misc/Kconfig +--- u-boot-2021.10/drivers/misc/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/Kconfig 2021-11-01 17:10:14.316256235 +0100 +@@ -398,36 +398,12 @@ + This option is an SPL-variant of the I2C_EEPROM option. + See the help of I2C_EEPROM for details. + +-if I2C_EEPROM +- + config SYS_I2C_EEPROM_ADDR + hex "Chip address of the EEPROM device" ++ depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM + default 0 + +-config SYS_I2C_EEPROM_BUS +- int "I2C bus of the EEPROM device." +- default 0 +- +-config SYS_EEPROM_SIZE +- int "Size in bytes of the EEPROM device" +- default 256 +- +-config SYS_EEPROM_PAGE_WRITE_BITS +- int "Number of bits used to address bytes in a single page" +- default 0 +- help +- The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. +- A 64 byte page, for example would require six bits. +- +-config SYS_EEPROM_PAGE_WRITE_DELAY_MS +- int "Number of milliseconds to delay between page writes" +- default 0 +- +-config SYS_I2C_EEPROM_ADDR_LEN +- int "Length in bytes of the EEPROM memory array address" +- default 1 +- help +- Note: This is NOT the chip address length! ++if I2C_EEPROM + + config SYS_I2C_EEPROM_ADDR_OVERFLOW + hex "EEPROM Address Overflow" +diff -ruN u-boot-2021.10/drivers/misc/Makefile u-boot/drivers/misc/Makefile +--- u-boot-2021.10/drivers/misc/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/Makefile 2021-11-01 17:10:14.316256235 +0100 +@@ -42,7 +42,7 @@ + obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o + obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o + obj-$(CONFIG_IRQ) += irq-uclass.o +-obj-$(CONFIG_SANDBOX) += irq_sandbox.o ++obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o + obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o + obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o + obj-$(CONFIG_IMX8) += imx8/ +diff -ruN u-boot-2021.10/drivers/misc/misc-uclass.c u-boot/drivers/misc/misc-uclass.c +--- u-boot-2021.10/drivers/misc/misc-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/misc-uclass.c 2021-11-01 17:10:14.319589387 +0100 +@@ -70,7 +70,7 @@ + UCLASS_DRIVER(misc) = { + .id = UCLASS_MISC, + .name = "misc", +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/drivers/misc/p2sb-uclass.c u-boot/drivers/misc/p2sb-uclass.c +--- u-boot-2021.10/drivers/misc/p2sb-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/misc/p2sb-uclass.c 2021-11-01 17:10:14.322922538 +0100 +@@ -183,16 +183,16 @@ + + static int p2sb_child_post_bind(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); +- int ret; +- u32 pid; ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); ++ int ret; ++ u32 pid; + +- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); +- if (ret) +- return ret; +- pplat->pid = pid; +-#endif ++ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); ++ if (ret) ++ return ret; ++ pplat->pid = pid; ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/mmc/fsl_esdhc_imx.c u-boot/drivers/mmc/fsl_esdhc_imx.c +--- u-boot-2021.10/drivers/mmc/fsl_esdhc_imx.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/fsl_esdhc_imx.c 2021-11-01 17:10:14.326255689 +0100 +@@ -1411,7 +1411,6 @@ + + static int fsl_esdhc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + #if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *vqmmc_dev; +@@ -1419,10 +1418,12 @@ + #endif + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); +- + fdt_addr_t addr; + unsigned int val; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; +@@ -1494,7 +1495,7 @@ + priv->vs18_enable = 1; + } + #endif +-#endif ++ + return 0; + } + +@@ -1598,11 +1599,11 @@ + return ret; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- ret = mmc_of_parse(dev, &plat->cfg); +- if (ret) +- return ret; +-#endif ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ ret = mmc_of_parse(dev, &plat->cfg); ++ if (ret) ++ return ret; ++ } + + mmc = &plat->mmc; + mmc->cfg = &plat->cfg; +diff -ruN u-boot-2021.10/drivers/mmc/ftsdc010_mci.c u-boot/drivers/mmc/ftsdc010_mci.c +--- u-boot-2021.10/drivers/mmc/ftsdc010_mci.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/ftsdc010_mci.c 2021-11-01 17:10:14.326255689 +0100 +@@ -30,8 +30,6 @@ + #include <syscon.h> + #include <linux/err.h> + +-DECLARE_GLOBAL_DATA_PTR; +- + #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ + #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ + +@@ -392,34 +390,29 @@ + + static int ftsdc010_mmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct ftsdc_priv *priv = dev_get_priv(dev); + struct ftsdc010_chip *chip = &priv->chip; +- chip->name = dev->name; +- chip->ioaddr = dev_read_addr_ptr(dev); +- chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), +- "bus-width", 4); +- chip->priv = dev; +- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), +- "fifo-depth", 0); +- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), +- "fifo-mode"); +- if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), +- "clock-freq-min-max", priv->minmax, 2)) { +- int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), +- "max-frequency", -EINVAL); +- if (val < 0) +- return val; + +- priv->minmax[0] = 400000; /* 400 kHz */ +- priv->minmax[1] = val; +- } else { +- debug("%s: 'clock-freq-min-max' property was deprecated.\n", +- __func__); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ chip->name = dev->name; ++ chip->ioaddr = dev_read_addr_ptr(dev); ++ chip->buswidth = dev_read_u32_default(dev, "bus-width", 4); ++ chip->priv = dev; ++ priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); ++ priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); ++ if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { ++ if (dev_read_u32(dev, "max-frequency", &priv->minmax[1])) ++ return -EINVAL; ++ ++ priv->minmax[0] = 400000; /* 400 kHz */ ++ } else { ++ debug("%s: 'clock-freq-min-max' property was deprecated.\n", ++ __func__); ++ } + } +-#endif + chip->sclk = priv->minmax[1]; + chip->regs = chip->ioaddr; ++ + return 0; + } + +@@ -440,7 +433,7 @@ + chip->priv = dev; + chip->dev_index = 1; + memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); +- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); ++ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; + #endif +diff -ruN u-boot-2021.10/drivers/mmc/Kconfig u-boot/drivers/mmc/Kconfig +--- u-boot-2021.10/drivers/mmc/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/Kconfig 2021-11-01 17:10:14.322922538 +0100 +@@ -123,7 +123,6 @@ + + config SPL_MMC_IO_VOLTAGE + bool "Support IO voltage configuration in SPL" +- default n + help + IO voltage configuration allows selecting the voltage level of the IO + lines (not the level of main supply). This is required for UHS +@@ -193,7 +192,6 @@ + + config MMC_TRACE + bool "MMC debugging" +- default n + help + This is an option for use by developer. Enable MMC core debugging. + +@@ -221,7 +219,6 @@ + depends on DM_MMC + depends on MMC_DW + depends on BLK +- default n + help + This selects support for Cortina SoC specific extensions to the + Synopsys DesignWare Memory Card Interface driver. Select this option +@@ -723,7 +720,8 @@ + + config MMC_SUNXI + bool "Allwinner sunxi SD/MMC Host Controller support" +- depends on ARCH_SUNXI && !UART0_PORT_F ++ depends on (ARCH_SUNXI || TARGET_SUNXI) && !UART0_PORT_F ++ depends on DM_GPIO || !DM_MMC + default y + help + This selects support for the SD/MMC Host Controller on +@@ -770,7 +768,6 @@ + + config FTSDC010_SDIO + bool "Support ftsdc010 sdio" +- default n + depends on FTSDC010 + help + This can enable ftsdc010 sdio function. +@@ -805,7 +802,6 @@ + config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND + bool "enable eSDHC workaround for 3.3v IO reliability issue" + depends on FSL_ESDHC && DM_MMC +- default n + help + When eSDHC operates at 3.3v, damage can accumulate in an internal + level shifter at a higher than expected rate. The faster the interface +diff -ruN u-boot-2021.10/drivers/mmc/Makefile u-boot/drivers/mmc/Makefile +--- u-boot-2021.10/drivers/mmc/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/Makefile 2021-11-01 17:10:14.322922538 +0100 +@@ -65,7 +65,7 @@ + obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o + obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o + obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o +-obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o ++obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o + obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o + obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o + obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o +diff -ruN u-boot-2021.10/drivers/mmc/mmc.c u-boot/drivers/mmc/mmc.c +--- u-boot-2021.10/drivers/mmc/mmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/mmc.c 2021-11-01 17:10:14.326255689 +0100 +@@ -699,7 +699,7 @@ + mmc_go_idle(mmc); + + start = get_timer(0); +- /* Asking to the card its capabilities */ ++ /* Asking to the card its capabilities */ + for (i = 0; ; i++) { + err = mmc_send_op_cond_iter(mmc, i != 0); + if (err) +diff -ruN u-boot-2021.10/drivers/mmc/mv_sdhci.c u-boot/drivers/mmc/mv_sdhci.c +--- u-boot-2021.10/drivers/mmc/mv_sdhci.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/mv_sdhci.c 2021-11-01 17:10:14.326255689 +0100 +@@ -44,29 +44,6 @@ + + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS + static struct sdhci_ops mv_ops; +- +-#if defined(CONFIG_SHEEVA_88SV331xV5) +-#define SD_CE_ATA_2 0xEA +-#define MMC_CARD 0x1000 +-#define MMC_WIDTH 0x0100 +-static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) +-{ +- struct mmc *mmc = host->mmc; +- u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; +- +- if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) { +- if (mmc->bus_width == 8) +- writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); +- else +- writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); +- } +- +- writeb(val, host->ioaddr + reg); +-} +- +-#else +-#define mv_sdhci_writeb NULL +-#endif /* CONFIG_SHEEVA_88SV331xV5 */ + #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ + + int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) +@@ -84,7 +61,6 @@ + host->max_clk = max_clk; + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS + memset(&mv_ops, 0, sizeof(struct sdhci_ops)); +- mv_ops.write_b = mv_sdhci_writeb; + host->ops = &mv_ops; + #endif + +diff -ruN u-boot-2021.10/drivers/mmc/mxsmmc.c u-boot/drivers/mmc/mxsmmc.c +--- u-boot-2021.10/drivers/mmc/mxsmmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/mxsmmc.c 2021-11-01 17:10:14.329588839 +0100 +@@ -665,7 +665,7 @@ + .set_ios = mxsmmc_set_ios, + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int mxsmmc_of_to_plat(struct udevice *bus) + { + struct mxsmmc_plat *plat = dev_get_plat(bus); +@@ -709,7 +709,7 @@ + U_BOOT_DRIVER(fsl_imx23_mmc) = { + .name = "fsl_imx23_mmc", + .id = UCLASS_MMC, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = mxsmmc_ids, + .of_to_plat = mxsmmc_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/mmc/omap_hsmmc.c u-boot/drivers/mmc/omap_hsmmc.c +--- u-boot-2021.10/drivers/mmc/omap_hsmmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/omap_hsmmc.c 2021-11-01 17:10:14.329588839 +0100 +@@ -42,7 +42,7 @@ + #include <asm/arch/mux_dra7xx.h> + #include <asm/arch/dra7xx_iodelay.h> + #endif +-#if !defined(CONFIG_SOC_KEYSTONE) ++#if !defined(CONFIG_ARCH_KEYSTONE) + #include <asm/gpio.h> + #include <asm/arch/sys_proto.h> + #endif +@@ -1559,7 +1559,7 @@ + priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; + #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ + defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ +- defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ ++ defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \ + defined(CONFIG_HSMMC2_8BIT) + /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ + host_caps_val |= MMC_MODE_8BIT; +@@ -1891,7 +1891,7 @@ + } + #endif + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + #ifdef CONFIG_OMAP54XX + __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) + { +@@ -2009,7 +2009,7 @@ + return omap_hsmmc_init_setup(mmc); + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + + static const struct omap_mmc_of_data dra7_mmc_of_data = { + .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, +@@ -2027,7 +2027,7 @@ + U_BOOT_DRIVER(omap_hsmmc) = { + .name = "omap_hsmmc", + .id = UCLASS_MMC, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = omap_hsmmc_ids, + .of_to_plat = omap_hsmmc_of_to_plat, + .plat_auto = sizeof(struct omap_hsmmc_plat), +diff -ruN u-boot-2021.10/drivers/mmc/rockchip_dw_mmc.c u-boot/drivers/mmc/rockchip_dw_mmc.c +--- u-boot-2021.10/drivers/mmc/rockchip_dw_mmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/rockchip_dw_mmc.c 2021-11-01 17:10:14.329588839 +0100 +@@ -52,10 +52,12 @@ + + static int rockchip_dwmmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + host->name = dev->name; + host->ioaddr = dev_read_addr_ptr(dev); + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); +@@ -95,7 +97,7 @@ + debug("%s: 'clock-freq-min-max' property was deprecated.\n", + __func__); + } +-#endif ++ + return 0; + } + +@@ -121,7 +123,7 @@ + priv->minmax[0] = 400000; /* 400 kHz */ + priv->minmax[1] = dtplat->max_frequency; + +- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); ++ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; + #else +diff -ruN u-boot-2021.10/drivers/mmc/sunxi_mmc.c u-boot/drivers/mmc/sunxi_mmc.c +--- u-boot-2021.10/drivers/mmc/sunxi_mmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mmc/sunxi_mmc.c 2021-11-01 17:10:14.332921991 +0100 +@@ -15,18 +15,36 @@ + #include <mmc.h> + #include <clk.h> + #include <reset.h> ++#include <asm/gpio.h> + #include <asm/io.h> ++#if !CONFIG_IS_ENABLED(DM_MMC) + #include <asm/arch/clock.h> + #include <asm/arch/cpu.h> +-#include <asm/arch/gpio.h> + #include <asm/arch/mmc.h> +-#include <asm-generic/gpio.h> ++#endif + #include <linux/delay.h> + ++#include "sunxi_mmc.h" ++ + #ifndef CCM_MMC_CTRL_MODE_SEL_NEW + #define CCM_MMC_CTRL_MODE_SEL_NEW 0 + #endif + ++#include "../../arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h" ++ ++unsigned int clock_get_pll6(void) ++{ ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)0x2001000UL; ++ ++ uint32_t rval = readl(&ccm->pll6_cfg); ++ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; ++ int m = ((rval >> 1) & 0x1) + 1; ++ int p0 = ((rval >> 16) & 0x7) + 1; ++ /* The register defines PLL6-2X, not plain PLL6 */ ++ return 24000000 / n / m / p0; ++} ++ + struct sunxi_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +@@ -112,7 +130,8 @@ + return IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H5) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || +- IS_ENABLED(CONFIG_MACH_SUN8I_R40); ++ IS_ENABLED(CONFIG_MACH_SUN8I_R40) || ++ IS_ENABLED(CONFIG_MACH_SUN20I); + } + + static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) +@@ -246,7 +265,7 @@ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + writel(rval, &priv->reg->clkcr); + +-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) ++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_MACH_SUN20I) + /* A64 supports calibration of delays on MMC controller and we + * have to set delay of zero before starting calibration. + * Allwinner BSP driver sets a delay only in the case of +@@ -685,6 +704,7 @@ + return ret; + ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node); + ++#define SUNXI_MMC0_BASE 0x4020000 + priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; + priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4; + +@@ -701,12 +721,8 @@ + return ret; + + /* This GPIO is optional */ +- if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, +- GPIOD_IS_IN)) { +- int cd_pin = gpio_get_number(&priv->cd_gpio); +- +- sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); +- } ++ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, ++ GPIOD_IS_IN | GPIOD_PULL_UP); + + upriv->mmc = &plat->mmc; + +@@ -730,6 +746,7 @@ + { .compatible = "allwinner,sun7i-a20-mmc" }, + { .compatible = "allwinner,sun8i-a83t-emmc" }, + { .compatible = "allwinner,sun9i-a80-mmc" }, ++ { .compatible = "allwinner,sun20i-d1-mmc" }, + { .compatible = "allwinner,sun50i-a64-mmc" }, + { .compatible = "allwinner,sun50i-a64-emmc" }, + { .compatible = "allwinner,sun50i-h6-mmc" }, +diff -ruN u-boot-2021.10/drivers/mmc/sunxi_mmc.h u-boot/drivers/mmc/sunxi_mmc.h +--- u-boot-2021.10/drivers/mmc/sunxi_mmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/mmc/sunxi_mmc.h 2021-11-01 17:10:14.332921991 +0100 +@@ -0,0 +1,136 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2007-2011 ++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com> ++ * Aaron <leafy.myeh@allwinnertech.com> ++ * ++ * MMC register definition for allwinner sunxi platform. ++ */ ++ ++#ifndef _SUNXI_MMC_H ++#define _SUNXI_MMC_H ++ ++#include <linux/types.h> ++ ++struct sunxi_mmc { ++ u32 gctrl; /* 0x00 global control */ ++ u32 clkcr; /* 0x04 clock control */ ++ u32 timeout; /* 0x08 time out */ ++ u32 width; /* 0x0c bus width */ ++ u32 blksz; /* 0x10 block size */ ++ u32 bytecnt; /* 0x14 byte count */ ++ u32 cmd; /* 0x18 command */ ++ u32 arg; /* 0x1c argument */ ++ u32 resp0; /* 0x20 response 0 */ ++ u32 resp1; /* 0x24 response 1 */ ++ u32 resp2; /* 0x28 response 2 */ ++ u32 resp3; /* 0x2c response 3 */ ++ u32 imask; /* 0x30 interrupt mask */ ++ u32 mint; /* 0x34 masked interrupt status */ ++ u32 rint; /* 0x38 raw interrupt status */ ++ u32 status; /* 0x3c status */ ++ u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ ++ u32 funcsel; /* 0x44 function select */ ++ u32 cbcr; /* 0x48 CIU byte count */ ++ u32 bbcr; /* 0x4c BIU byte count */ ++ u32 dbgc; /* 0x50 debug enable */ ++ u32 res0; /* 0x54 reserved */ ++ u32 a12a; /* 0x58 Auto command 12 argument */ ++ u32 ntsr; /* 0x5c New timing set register */ ++ u32 res1[8]; ++ u32 dmac; /* 0x80 internal DMA control */ ++ u32 dlba; /* 0x84 internal DMA descr list base address */ ++ u32 idst; /* 0x88 internal DMA status */ ++ u32 idie; /* 0x8c internal DMA interrupt enable */ ++ u32 chda; /* 0x90 */ ++ u32 cbda; /* 0x94 */ ++ u32 res2[26]; ++ u32 res3[17]; ++ u32 samp_dl; ++ u32 res4[46]; ++ u32 fifo; /* 0x100 / 0x200 FIFO access address */ ++}; ++ ++#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) ++#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) ++#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) ++ ++#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) ++#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) ++#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) ++#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ ++ SUNXI_MMC_GCTRL_FIFO_RESET|\ ++ SUNXI_MMC_GCTRL_DMA_RESET) ++#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) ++#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) ++ ++#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) ++#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) ++#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) ++#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) ++#define SUNXI_MMC_CMD_WRITE (0x1 << 10) ++#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) ++#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) ++#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) ++#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) ++#define SUNXI_MMC_CMD_START (0x1 << 31) ++ ++#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) ++#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) ++#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) ++#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) ++#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) ++#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) ++#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) ++#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) ++#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) ++#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) ++#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) ++#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) ++#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) ++#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) ++#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) ++#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) ++#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) ++#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) ++#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ ++ (SUNXI_MMC_RINT_RESP_ERROR | \ ++ SUNXI_MMC_RINT_RESP_CRC_ERROR | \ ++ SUNXI_MMC_RINT_DATA_CRC_ERROR | \ ++ SUNXI_MMC_RINT_RESP_TIMEOUT | \ ++ SUNXI_MMC_RINT_DATA_TIMEOUT | \ ++ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ ++ SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ ++ SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ ++ SUNXI_MMC_RINT_START_BIT_ERROR | \ ++ SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ ++#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ ++ (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ ++ SUNXI_MMC_RINT_DATA_OVER | \ ++ SUNXI_MMC_RINT_COMMAND_DONE | \ ++ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) ++ ++#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) ++#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) ++#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) ++#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) ++#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) ++#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) ++#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) ++#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff) ++ ++#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) ++ ++#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) ++#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) ++#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) ++ ++#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) ++#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) ++ ++#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) ++#define SUNXI_MMC_COMMON_RESET (1 << 18) ++ ++#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) ++ ++#endif /* _SUNXI_MMC_H */ +diff -ruN u-boot-2021.10/drivers/mtd/Kconfig u-boot/drivers/mtd/Kconfig +--- u-boot-2021.10/drivers/mtd/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/Kconfig 2021-11-01 17:10:14.332921991 +0100 +@@ -111,6 +111,14 @@ + + source "drivers/mtd/nand/Kconfig" + ++config SYS_NAND_MAX_CHIPS ++ int "NAND max chips" ++ depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \ ++ SPL_OMAP3_ID_NAND ++ default 1 ++ help ++ The maximum number of NAND chips per device to be supported. ++ + source "drivers/mtd/spi/Kconfig" + + source "drivers/mtd/ubi/Kconfig" +diff -ruN u-boot-2021.10/drivers/mtd/mtdcore.c u-boot/drivers/mtd/mtdcore.c +--- u-boot-2021.10/drivers/mtd/mtdcore.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/mtdcore.c 2021-11-01 17:10:14.336255142 +0100 +@@ -4,7 +4,7 @@ + * drivers and users. + * + * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> +- * Copyright © 2006 Red Hat UK Limited ++ * Copyright © 2006 Red Hat UK Limited + * + */ + +@@ -123,7 +123,7 @@ + } else { + *next = 0; + } +- ++ + return ret; + } + +@@ -799,8 +799,8 @@ + * device name + * @name: MTD device name to open + * +- * This function returns MTD device description structure in case of +- * success and an error code in case of failure. ++ * This function returns MTD device description structure in case of ++ * success and an error code in case of failure. + */ + struct mtd_info *get_mtd_device_nm(const char *name) + { +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/am335x_spl_bch.c u-boot/drivers/mtd/nand/raw/am335x_spl_bch.c +--- u-boot-2021.10/drivers/mtd/nand/raw/am335x_spl_bch.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/am335x_spl_bch.c 2021-11-01 17:10:14.336255142 +0100 +@@ -14,6 +14,7 @@ + #include <asm/io.h> + #include <linux/delay.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + + static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; + static struct mtd_info *mtd; +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/atmel_nand.c u-boot/drivers/mtd/nand/raw/atmel_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/atmel_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/atmel_nand.c 2021-11-01 17:10:14.336255142 +0100 +@@ -24,6 +24,7 @@ + #include <nand.h> + #include <watchdog.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + + #ifdef CONFIG_ATMEL_NAND_HWECC + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/brcmnand/brcmnand.c u-boot/drivers/mtd/nand/raw/brcmnand/brcmnand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/brcmnand/brcmnand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/brcmnand/brcmnand.c 2021-11-01 17:10:14.336255142 +0100 +@@ -26,6 +26,7 @@ + #include <linux/completion.h> + #include <linux/errno.h> + #include <linux/log2.h> ++#include <linux/mtd/rawnand.h> + #include <asm/processor.h> + #include <dm.h> + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/cortina_nand.c u-boot/drivers/mtd/nand/raw/cortina_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/cortina_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/cortina_nand.c 2021-11-01 17:10:14.336255142 +0100 +@@ -16,6 +16,7 @@ + #include <linux/delay.h> + #include <linux/iopoll.h> + #include <linux/errno.h> ++#include <linux/mtd/rawnand.h> + #include <asm/gpio.h> + #include <fdtdec.h> + #include <bouncebuf.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/davinci_nand.c u-boot/drivers/mtd/nand/raw/davinci_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/davinci_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/davinci_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -30,6 +30,7 @@ + + #include <common.h> + #include <log.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #include <nand.h> + #include <dm/uclass.h> +@@ -39,7 +40,7 @@ + #define NAND_TIMEOUT 10240 + #define NAND_ECC_BUSY 0xC + #define NAND_4BITECC_MASK 0x03FF03FF +-#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 ++#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 + #define ECC_STATE_NO_ERR 0x0 + #define ECC_STATE_TOO_MANY_ERRS 0x1 + #define ECC_STATE_ERR_CORR_COMP_P 0x2 +@@ -347,9 +348,9 @@ + }; + + #ifdef CONFIG_SYS_NAND_PAGE_2K +-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 ++#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11) + #elif defined(CONFIG_SYS_NAND_PAGE_4K) +-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 ++#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12) + #endif + + /** +@@ -371,7 +372,7 @@ + struct nand_ecclayout *saved_ecc_layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ +- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { ++ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { + saved_ecc_layout = chip->ecc.layout; + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; +@@ -402,7 +403,7 @@ + + err: + /* restore ECC layout */ +- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { ++ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } +@@ -433,7 +434,7 @@ + struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ +- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { ++ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; + } +@@ -463,7 +464,7 @@ + } + + /* restore ECC layout */ +- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { ++ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/fsl_elbc_nand.c u-boot/drivers/mtd/nand/raw/fsl_elbc_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/fsl_elbc_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/fsl_elbc_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -716,7 +716,7 @@ + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; + +- /* set up nand options */ ++ /* set up nand options */ + nand->options = NAND_NO_SUBPAGE_WRITE; + nand->bbt_options = NAND_BBT_USE_FLASH; + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/fsl_elbc_spl.c u-boot/drivers/mtd/nand/raw/fsl_elbc_spl.c +--- u-boot-2021.10/drivers/mtd/nand/raw/fsl_elbc_spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/fsl_elbc_spl.c 2021-11-01 17:10:14.339588293 +0100 +@@ -11,6 +11,7 @@ + + #include <common.h> + #include <cpu_func.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #include <asm/fsl_lbc.h> + #include <nand.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/fsl_upm.c u-boot/drivers/mtd/nand/raw/fsl_upm.c +--- u-boot-2021.10/drivers/mtd/nand/raw/fsl_upm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/fsl_upm.c 2021-11-01 17:10:14.339588293 +0100 +@@ -13,6 +13,7 @@ + #include <linux/delay.h> + #include <linux/errno.h> + #include <linux/mtd/mtd.h> ++#include <linux/mtd/rawnand.h> + #include <linux/mtd/fsl_upm.h> + #include <nand.h> + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/fsmc_nand.c u-boot/drivers/mtd/nand/raw/fsmc_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/fsmc_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/fsmc_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -13,6 +13,7 @@ + #include <linux/bitops.h> + #include <linux/err.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + #include <linux/mtd/fsmc_nand.h> + #include <asm/arch/hardware.h> + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/kb9202_nand.c u-boot/drivers/mtd/nand/raw/kb9202_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/kb9202_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/kb9202_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -8,6 +8,7 @@ + */ + + #include <common.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #include <asm/arch/AT91RM9200.h> + #include <asm/arch/hardware.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/Kconfig u-boot/drivers/mtd/nand/raw/Kconfig +--- u-boot-2021.10/drivers/mtd/nand/raw/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/Kconfig 2021-11-01 17:10:14.336255142 +0100 +@@ -31,12 +31,10 @@ + + config ATMEL_NAND_HWECC + bool "Atmel Hardware ECC" +- default n + + config ATMEL_NAND_HW_PMECC + bool "Atmel Programmable Multibit ECC (PMECC)" + select ATMEL_NAND_HWECC +- default n + help + The Programmable Multibit ECC (PMECC) controller is a programmable + binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. +@@ -59,7 +57,6 @@ + bool "Atmel PMECC Header Generation" + select ATMEL_NAND_HWECC + select ATMEL_NAND_HW_PMECC +- default n + help + Generate Programmable Multibit ECC (PMECC) header for SPL image. + +@@ -108,6 +105,14 @@ + Enable this driver for NAND flash controllers available in TI Davinci + and Keystone2 platforms + ++config KEYSTONE_RBL_NAND ++ depends on ARCH_KEYSTONE ++ def_bool y ++ ++config SPL_NAND_LOAD ++ def_bool y ++ depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT ++ + config NAND_DENALI + bool + select SYS_NAND_SELF_INIT +@@ -121,6 +126,22 @@ + Enable the driver for NAND flash on platforms using a Denali NAND + controller as a DT device. + ++config NAND_FSL_ELBC ++ bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver" ++ depends on FSL_ELBC ++ help ++ Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. ++ ++config NAND_FSL_IFC ++ bool "Support Freescale Integrated Flash Controller NAND driver" ++ help ++ Enable the Freescale Integrated Flash Controller NAND driver. ++ ++config NAND_LPC32XX_MLC ++ bool "Support LPC32XX_MLC controller" ++ help ++ Enable the LPC32XX MLC NAND controller. ++ + config NAND_LPC32XX_SLC + bool "Support LPC32XX_SLC controller" + help +@@ -135,9 +156,10 @@ + do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 + and BCH16 ECC algorithms. + ++if NAND_OMAP_GPMC ++ + config NAND_OMAP_GPMC_PREFETCH + bool "Enable GPMC Prefetch" +- depends on NAND_OMAP_GPMC + default y + help + On OMAP platforms that use the GPMC controller +@@ -146,7 +168,7 @@ + + config NAND_OMAP_ELM + bool "Enable ELM driver for OMAPxx and AMxx platforms." +- depends on NAND_OMAP_GPMC && !OMAP34XX ++ depends on !OMAP34XX + help + ELM controller is used for ECC error detection (not ECC calculation) + of BCH4, BCH8 and BCH16 ECC algorithms. +@@ -155,6 +177,104 @@ + detection. However ECC calculation on such plaforms would still be + done by GPMC controller. + ++choice ++ prompt "ECC scheme" ++ default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW ++ help ++ On OMAP platforms, this CONFIG specifies NAND ECC scheme. ++ It can take following values: ++ OMAP_ECC_HAM1_CODE_SW ++ 1-bit Hamming code using software lib. ++ (for legacy devices only) ++ OMAP_ECC_HAM1_CODE_HW ++ 1-bit Hamming code using GPMC hardware. ++ (for legacy devices only) ++ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ++ 4-bit BCH code (unsupported) ++ OMAP_ECC_BCH4_CODE_HW ++ 4-bit BCH code (unsupported) ++ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW ++ 8-bit BCH code with ++ - ecc calculation using GPMC hardware engine, ++ - error detection using software library. ++ - requires CONFIG_BCH to enable software BCH library ++ (For legacy device which do not have ELM h/w engine) ++ OMAP_ECC_BCH8_CODE_HW ++ 8-bit BCH code with ++ - ecc calculation using GPMC hardware engine, ++ - error detection using ELM hardware engine. ++ OMAP_ECC_BCH16_CODE_HW ++ 16-bit BCH code with ++ - ecc calculation using GPMC hardware engine, ++ - error detection using ELM hardware engine. ++ ++ How to select ECC scheme on OMAP and AMxx platforms ? ++ ----------------------------------------------------- ++ Though higher ECC schemes have more capability to detect and correct ++ bit-flips, but still selection of ECC scheme is dependent on following ++ - hardware engines present in SoC. ++ Some legacy OMAP SoC do not have ELM h/w engine thus such ++ SoC cannot support BCHx_HW ECC schemes. ++ - size of OOB/Spare region ++ With higher ECC schemes, more OOB/Spare area is required to ++ store ECC. So choice of ECC scheme is limited by NAND oobsize. ++ ++ In general following expression can help: ++ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES ++ where ++ NAND_OOBSIZE = number of bytes available in ++ OOB/spare area per NAND page. ++ NAND_PAGESIZE = bytes in main-area of NAND page. ++ ECC_BYTES = number of ECC bytes generated to ++ protect 512 bytes of data, which is: ++ 3 for HAM1_xx ecc schemes ++ 7 for BCH4_xx ecc schemes ++ 14 for BCH8_xx ecc schemes ++ 26 for BCH16_xx ecc schemes ++ ++ example to check for BCH16 on 2K page NAND ++ NAND_PAGESIZE = 2048 ++ NAND_OOBSIZE = 64 ++ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE ++ Thus BCH16 cannot be supported on 2K page NAND. ++ ++ However, for 4K pagesize NAND ++ NAND_PAGESIZE = 4096 ++ NAND_OOBSIZE = 224 ++ ECC_BYTES = 26 ++ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE ++ Thus BCH16 can be supported on 4K page NAND. ++ ++config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW ++ bool "1-bit Hamming code using software lib" ++ ++config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW ++ bool "1-bit Hamming code using GPMC hardware" ++ ++config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW ++ bool "8-bit BCH code with HW calculation SW error detection" ++ ++config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW ++ bool "8-bit BCH code with HW calculation and error detection" ++ ++config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW ++ bool "16-bit BCH code with HW calculation and error detection" ++ ++endchoice ++ ++config NAND_OMAP_ECCSCHEME ++ int ++ default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW ++ default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW ++ default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW ++ default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW ++ default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW ++ help ++ This must be kept in sync with the enum in ++ include/linux/mtd/omap_gpmc.h ++ ++endif ++ + config NAND_VF610_NFC + bool "Support for Freescale NFC for VF610" + select SYS_NAND_SELF_INIT +@@ -353,22 +473,43 @@ + + config SYS_NAND_BLOCK_SIZE + hex "NAND chip eraseblock size" +- depends on ARCH_SUNXI ++ depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT ++ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC + help + Number of data bytes in one eraseblock for the NAND chip on the + board. This is the multiple of NAND_PAGE_SIZE and the number of + pages. + ++config SYS_NAND_ONFI_DETECTION ++ bool "Enable detection of ONFI compliant devices during probe" ++ help ++ Enables detection of ONFI compliant devices during probe. ++ And fetching device parameters flashed on device, by parsing ++ ONFI parameter page. ++ ++config SYS_NAND_PAGE_COUNT ++ hex "NAND chip page count" ++ depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ ++ SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE) ++ help ++ Number of pages in the NAND chip. ++ + config SYS_NAND_PAGE_SIZE + hex "NAND chip page size" +- depends on ARCH_SUNXI ++ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ ++ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ ++ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER ++ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC + help + Number of data bytes in one page for the NAND chip on the + board, not including the OOB area. + + config SYS_NAND_OOBSIZE + hex "NAND chip OOB size" +- depends on ARCH_SUNXI ++ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ ++ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ ++ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER ++ depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC + help + Number of bytes in the Out-Of-Band area for the NAND chip on + the board. +@@ -392,14 +533,37 @@ + not available while configuring controller. So a static CONFIG_NAND_xx + is needed to know the device's bus-width in advance. + +-config SYS_NAND_MAX_CHIPS +- int "NAND max chips" +- default 1 +- depends on NAND_ARASAN ++if SPL ++ ++config SYS_NAND_5_ADDR_CYCLE ++ bool "Wait 5 address cycles during NAND commands" ++ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \ ++ (SPL_NAND_SUPPORT && NAND_ATMEL) ++ default y + help +- The maximum number of NAND chips per device to be supported. ++ Some controllers require waiting for 5 address cycles when issuing ++ some commands, on NAND chips larger than 128MiB. + +-if SPL ++choice ++ prompt "NAND bad block marker/indicator position in the OOB" ++ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \ ++ SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC) ++ default HAS_NAND_LARGE_BADBLOCK_POS ++ help ++ In the OOB, which position contains the badblock information. ++ ++config HAS_NAND_LARGE_BADBLOCK_POS ++ bool "Set the bad block marker/indicator to the 'large' position" ++ ++config HAS_NAND_SMALL_BADBLOCK_POS ++ bool "Set the bad block marker/indicator to the 'small' position" ++ ++endchoice ++ ++config SYS_NAND_BAD_BLOCK_POS ++ int ++ default 0 if HAS_NAND_LARGE_BADBLOCK_POS ++ default 5 if HAS_NAND_SMALL_BADBLOCK_POS + + config SYS_NAND_U_BOOT_LOCATIONS + bool "Define U-boot binaries locations in NAND" +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/kirkwood_nand.c u-boot/drivers/mtd/nand/raw/kirkwood_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/kirkwood_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/kirkwood_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -6,6 +6,7 @@ + */ + + #include <common.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #include <asm/arch/soc.h> + #include <asm/arch/mpp.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/kmeter1_nand.c u-boot/drivers/mtd/nand/raw/kmeter1_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/kmeter1_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/kmeter1_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -8,6 +8,7 @@ + #include <nand.h> + #include <asm/io.h> + #include <linux/delay.h> ++#include <linux/mtd/rawnand.h> + + #define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000) + #define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000) +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c u-boot/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +--- u-boot-2021.10/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c 2021-11-01 17:10:14.339588293 +0100 +@@ -23,6 +23,7 @@ + #include <nand.h> + #include <linux/delay.h> + #include <linux/errno.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #include <nand.h> + #include <asm/arch/clk.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/lpc32xx_nand_slc.c u-boot/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +--- u-boot-2021.10/drivers/mtd/nand/raw/lpc32xx_nand_slc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/lpc32xx_nand_slc.c 2021-11-01 17:10:14.339588293 +0100 +@@ -15,6 +15,7 @@ + #include <nand.h> + #include <linux/bug.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + #include <linux/errno.h> + #include <asm/io.h> + #include <asm/arch/config.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand.c u-boot/drivers/mtd/nand/raw/mxc_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/mxc_nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -10,8 +10,9 @@ + #include <nand.h> + #include <linux/delay.h> + #include <linux/err.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> +-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ ++#if defined(CONFIG_MX27) || \ + defined(CONFIG_MX51) || defined(CONFIG_MX53) + #include <asm/arch/imx-regs.h> + #endif +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand.h u-boot/drivers/mtd/nand/raw/mxc_nand.h +--- u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/mxc_nand.h 2021-11-01 17:10:14.339588293 +0100 +@@ -29,11 +29,6 @@ + #define is_mxc_nfc_1() 1 + #define is_mxc_nfc_21() 0 + #define is_mxc_nfc_32() 0 +-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +-#define MXC_NFC_V2_1 +-#define is_mxc_nfc_1() 0 +-#define is_mxc_nfc_21() 1 +-#define is_mxc_nfc_32() 0 + #elif defined(CONFIG_MX51) || defined(CONFIG_MX53) + #define MXC_NFC_V3 + #define MXC_NFC_V3_2 +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand_spl.c u-boot/drivers/mtd/nand/raw/mxc_nand_spl.c +--- u-boot-2021.10/drivers/mtd/nand/raw/mxc_nand_spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/mxc_nand_spl.c 2021-11-01 17:10:14.339588293 +0100 +@@ -13,6 +13,7 @@ + #include <common.h> + #include <hang.h> + #include <nand.h> ++#include <linux/mtd/rawnand.h> + #include <asm/arch/imx-regs.h> + #include <asm/io.h> + #include "mxc_nand.h" +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/mxs_nand_spl.c u-boot/drivers/mtd/nand/raw/mxs_nand_spl.c +--- u-boot-2021.10/drivers/mtd/nand/raw/mxs_nand_spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/mxs_nand_spl.c 2021-11-01 17:10:14.339588293 +0100 +@@ -13,6 +13,7 @@ + #include <linux/bitops.h> + #include <linux/delay.h> + #include <linux/err.h> ++#include <linux/mtd/rawnand.h> + + static struct mtd_info *mtd; + static struct nand_chip nand_chip; +@@ -295,4 +296,3 @@ + void nand_deselect(void) + { + } +- +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand_base.c u-boot/drivers/mtd/nand/raw/nand_base.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand_base.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand_base.c 2021-11-01 17:10:14.342921444 +0100 +@@ -263,7 +263,7 @@ + static void ioread16_rep(void *addr, void *buf, int len) + { + int i; +- u16 *p = (u16 *) buf; ++ u16 *p = (u16 *) buf; + + for (i = 0; i < len; i++) + p[i] = readw(addr); +@@ -905,11 +905,11 @@ + if (ret) + return ret; + +- u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; +- u32 time_start; +- +- time_start = get_timer(0); +- while (get_timer(time_start) < timer) { ++ u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; ++ u32 time_start; ++ ++ time_start = get_timer(0); ++ while (get_timer(time_start) < timer) { + if (chip->dev_ready) { + if (chip->dev_ready(mtd)) + break; +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand.c u-boot/drivers/mtd/nand/raw/nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand.c 2021-11-01 17:10:14.339588293 +0100 +@@ -9,6 +9,7 @@ + #include <nand.h> + #include <errno.h> + #include <linux/mtd/concat.h> ++#include <linux/mtd/rawnand.h> + + #ifndef CONFIG_SYS_NAND_BASE_LIST + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand_ids.c u-boot/drivers/mtd/nand/raw/nand_ids.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand_ids.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand_ids.c 2021-11-01 17:10:14.342921444 +0100 +@@ -30,7 +30,7 @@ + LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), +- LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), ++ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), + + LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), + #endif +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand_plat.c u-boot/drivers/mtd/nand/raw/nand_plat.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand_plat.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand_plat.c 2021-11-01 17:10:14.342921444 +0100 +@@ -15,6 +15,7 @@ + */ + + #include <common.h> ++#include <linux/mtd/rawnand.h> + #include <asm/io.h> + #ifdef NAND_PLAT_GPIO_DEV_READY + # include <asm/gpio.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand_spl_simple.c u-boot/drivers/mtd/nand/raw/nand_spl_simple.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand_spl_simple.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand_spl_simple.c 2021-11-01 17:10:14.342921444 +0100 +@@ -8,6 +8,7 @@ + #include <nand.h> + #include <asm/io.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + + static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; + static struct mtd_info *mtd; +@@ -39,11 +40,6 @@ + this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ + this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, + NAND_CTRL_ALE); /* A[24:17] */ +-#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE +- /* One more address cycle for devices > 32MiB */ +- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, +- NAND_CTRL_ALE); /* A[28:25] */ +-#endif + /* Latch in address */ + this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/nand_util.c u-boot/drivers/mtd/nand/raw/nand_util.c +--- u-boot-2021.10/drivers/mtd/nand/raw/nand_util.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/nand_util.c 2021-11-01 17:10:14.342921444 +0100 +@@ -30,6 +30,7 @@ + + #include <linux/errno.h> + #include <linux/mtd/mtd.h> ++#include <linux/mtd/rawnand.h> + #include <nand.h> + #include <jffs2/jffs2.h> + +@@ -189,7 +190,7 @@ + + #define NAND_CMD_LOCK_TIGHT 0x2c + #define NAND_CMD_LOCK_STATUS 0x7a +- ++ + /****************************************************************************** + * Support for locking / unlocking operations of some NAND devices + *****************************************************************************/ +@@ -545,8 +546,6 @@ + return rval ? -EIO : 0; + } + +- +- + /** + * nand_write_skip_bad: + * +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/octeontx_nand.c u-boot/drivers/mtd/nand/raw/octeontx_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/octeontx_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/octeontx_nand.c 2021-11-01 17:10:14.342921444 +0100 +@@ -23,6 +23,7 @@ + #include <linux/mtd/mtd.h> + #include <linux/mtd/nand_bch.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + #include <asm/global_data.h> + #include <asm/io.h> + #include <asm/types.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/omap_gpmc.c u-boot/drivers/mtd/nand/raw/omap_gpmc.c +--- u-boot-2021.10/drivers/mtd/nand/raw/omap_gpmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/omap_gpmc.c 2021-11-01 17:10:14.342921444 +0100 +@@ -11,6 +11,7 @@ + #include <asm/arch/mem.h> + #include <linux/mtd/omap_gpmc.h> + #include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/rawnand.h> + #include <linux/bch.h> + #include <linux/compiler.h> + #include <nand.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/rockchip_nfc.c u-boot/drivers/mtd/nand/raw/rockchip_nfc.c +--- u-boot-2021.10/drivers/mtd/nand/raw/rockchip_nfc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/rockchip_nfc.c 2021-11-01 17:10:14.342921444 +0100 +@@ -21,6 +21,7 @@ + #include <linux/mtd/mtd.h> + #include <linux/mtd/nand.h> + #include <linux/mtd/partitions.h> ++#include <linux/mtd/rawnand.h> + #include <memalign.h> + #include <nand.h> + +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/stm32_fmc2_nand.c u-boot/drivers/mtd/nand/raw/stm32_fmc2_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/stm32_fmc2_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/stm32_fmc2_nand.c 2021-11-01 17:10:14.346254595 +0100 +@@ -19,6 +19,7 @@ + #include <linux/err.h> + #include <linux/iopoll.h> + #include <linux/ioport.h> ++#include <linux/mtd/rawnand.h> + + /* Bad block marker length */ + #define FMC2_BBM_LEN 2 +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/sunxi_nand_spl.c u-boot/drivers/mtd/nand/raw/sunxi_nand_spl.c +--- u-boot-2021.10/drivers/mtd/nand/raw/sunxi_nand_spl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/sunxi_nand_spl.c 2021-11-01 17:10:14.346254595 +0100 +@@ -12,6 +12,7 @@ + #include <linux/bitops.h> + #include <linux/ctype.h> + #include <linux/delay.h> ++#include <linux/mtd/rawnand.h> + + /* registers */ + #define NFC_CTL 0x00000000 +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/tegra_nand.c u-boot/drivers/mtd/nand/raw/tegra_nand.c +--- u-boot-2021.10/drivers/mtd/nand/raw/tegra_nand.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/tegra_nand.c 2021-11-01 17:10:14.346254595 +0100 +@@ -19,6 +19,7 @@ + #include <linux/bug.h> + #include <linux/delay.h> + #include <linux/errno.h> ++#include <linux/mtd/rawnand.h> + #include <asm/gpio.h> + #include <fdtdec.h> + #include <bouncebuf.h> +diff -ruN u-boot-2021.10/drivers/mtd/nand/raw/vf610_nfc.c u-boot/drivers/mtd/nand/raw/vf610_nfc.c +--- u-boot-2021.10/drivers/mtd/nand/raw/vf610_nfc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/nand/raw/vf610_nfc.c 2021-11-01 17:10:14.346254595 +0100 +@@ -109,19 +109,19 @@ + #define STATUS_BYTE1_MASK 0x000000FF + + /* NFC_FLASH_CONFIG Field */ +-#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 +-#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 +-#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) +-#define CONFIG_DMA_REQ_BIT (1<<20) +-#define CONFIG_ECC_MODE_MASK 0x000E0000 +-#define CONFIG_ECC_MODE_SHIFT 17 +-#define CONFIG_FAST_FLASH_BIT (1<<16) +-#define CONFIG_16BIT (1<<7) +-#define CONFIG_BOOT_MODE_BIT (1<<6) +-#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) +-#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) +-#define CONFIG_PAGE_CNT_MASK 0xF +-#define CONFIG_PAGE_CNT_SHIFT 0 ++#define CFG_ECC_SRAM_ADDR_MASK 0x7FC00000 ++#define CFG_ECC_SRAM_ADDR_SHIFT 22 ++#define CFG_ECC_SRAM_REQ_BIT (1<<21) ++#define CFG_DMA_REQ_BIT (1<<20) ++#define CFG_ECC_MODE_MASK 0x000E0000 ++#define CFG_ECC_MODE_SHIFT 17 ++#define CFG_FAST_FLASH_BIT (1<<16) ++#define CFG_16BIT (1<<7) ++#define CFG_BOOT_MODE_BIT (1<<6) ++#define CFG_ADDR_AUTO_INCR_BIT (1<<5) ++#define CFG_BUFNO_AUTO_INCR_BIT (1<<4) ++#define CFG_PAGE_CNT_MASK 0xF ++#define CFG_PAGE_CNT_SHIFT 0 + + /* NFC_IRQ_STATUS Field */ + #define IDLE_IRQ_BIT (1<<29) +@@ -342,8 +342,8 @@ + static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) + { + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, +- CONFIG_ECC_MODE_MASK, +- CONFIG_ECC_MODE_SHIFT, ecc_mode); ++ CFG_ECC_MODE_MASK, ++ CFG_ECC_MODE_SHIFT, ecc_mode); + } + + static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) +@@ -666,16 +666,16 @@ + chip->ecc.size = PAGE_2K; + + /* Set configuration register. */ +- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); +- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); +- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); +- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); +- vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); +- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); ++ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT); ++ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT); ++ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT); ++ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT); ++ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT); ++ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT); + + /* Disable virtual pages, only one elementary transfer unit */ +- vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, +- CONFIG_PAGE_CNT_SHIFT, 1); ++ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK, ++ CFG_PAGE_CNT_SHIFT, 1); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { +@@ -684,7 +684,7 @@ + } + + if (cfg.width == 16) +- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); ++ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT); + + /* Bad block options. */ + if (cfg.flash_bbt) +@@ -734,12 +734,12 @@ + + /* Set ECC_STATUS offset */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, +- CONFIG_ECC_SRAM_ADDR_MASK, +- CONFIG_ECC_SRAM_ADDR_SHIFT, ++ CFG_ECC_SRAM_ADDR_MASK, ++ CFG_ECC_SRAM_ADDR_SHIFT, + ECC_SRAM_ADDR >> 3); + + /* Enable ECC status in SRAM */ +- vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); ++ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT); + } + + /* second phase scan */ +diff -ruN u-boot-2021.10/drivers/mtd/onenand/onenand_base.c u-boot/drivers/mtd/onenand/onenand_base.c +--- u-boot-2021.10/drivers/mtd/onenand/onenand_base.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/onenand/onenand_base.c 2021-11-01 17:10:14.346254595 +0100 +@@ -2306,8 +2306,8 @@ + + /** + * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info +- * boundary[], diesize[], mtd->size, mtd->erasesize, +- * mtd->eraseregions ++ * boundary[], diesize[], mtd->size, mtd->erasesize, ++ * mtd->eraseregions + * @param mtd - MTD device structure + */ + static void flexonenand_get_size(struct mtd_info *mtd) +diff -ruN u-boot-2021.10/drivers/mtd/spi/Kconfig u-boot/drivers/mtd/spi/Kconfig +--- u-boot-2021.10/drivers/mtd/spi/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/spi/Kconfig 2021-11-01 17:10:14.349587746 +0100 +@@ -99,7 +99,6 @@ + + config SPI_FLASH_SOFT_RESET + bool "Software Reset support for SPI NOR flashes" +- default n + help + Enable support for xSPI Software Reset. It will be used to switch from + Octal DTR mode to legacy mode on shutdown and boot (if enabled). +@@ -107,7 +106,6 @@ + config SPI_FLASH_SOFT_RESET_ON_BOOT + bool "Perform a Software Reset on boot on flashes that boot in stateful mode" + depends on SPI_FLASH_SOFT_RESET +- default n + help + Perform a Software Reset on boot to allow detecting flashes that are + handed to us in Octal DTR mode. Do not enable this config on flashes +diff -ruN u-boot-2021.10/drivers/mtd/spi/spi-nor-ids.c u-boot/drivers/mtd/spi/spi-nor-ids.c +--- u-boot-2021.10/drivers/mtd/spi/spi-nor-ids.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/spi/spi-nor-ids.c 2021-11-01 17:10:14.349587746 +0100 +@@ -76,7 +76,7 @@ + { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, + { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, +- { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, ++ { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, + #endif + #ifdef CONFIG_SPI_FLASH_EON /* EON */ + /* EON -- en25xxx */ +diff -ruN u-boot-2021.10/drivers/mtd/ubi/build.c u-boot/drivers/mtd/ubi/build.c +--- u-boot-2021.10/drivers/mtd/ubi/build.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/ubi/build.c 2021-11-01 17:10:14.349587746 +0100 +@@ -115,7 +115,7 @@ + #else + struct ubi_device *ubi_devices[UBI_MAX_DEVICES]; + #endif +- ++ + #ifndef __UBOOT__ + /* Serializes UBI devices creations and removals */ + DEFINE_MUTEX(ubi_devices_mutex); +diff -ruN u-boot-2021.10/drivers/mtd/ubi/crc32.c u-boot/drivers/mtd/ubi/crc32.c +--- u-boot-2021.10/drivers/mtd/ubi/crc32.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/ubi/crc32.c 2021-11-01 17:10:14.349587746 +0100 +@@ -293,8 +293,8 @@ + * + * A big-endian CRC written this way would be coded like: + * for (i = 0; i < input_bits; i++) { +- * multiple = remainder & 0x80000000 ? CRCPOLY : 0; +- * remainder = (remainder << 1 | next_input_bit()) ^ multiple; ++ * multiple = remainder & 0x80000000 ? CRCPOLY : 0; ++ * remainder = (remainder << 1 | next_input_bit()) ^ multiple; + * } + * Notice how, to get at bit 32 of the shifted remainder, we look + * at bit 31 of the remainder *before* shifting it. +@@ -313,14 +313,14 @@ + * This changes the code to: + * for (i = 0; i < input_bits; i++) { + * remainder ^= next_input_bit() << 31; +- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; +- * remainder = (remainder << 1) ^ multiple; ++ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; ++ * remainder = (remainder << 1) ^ multiple; + * } + * With this optimization, the little-endian code is simpler: + * for (i = 0; i < input_bits; i++) { + * remainder ^= next_input_bit(); +- * multiple = (remainder & 1) ? CRCPOLY : 0; +- * remainder = (remainder >> 1) ^ multiple; ++ * multiple = (remainder & 1) ? CRCPOLY : 0; ++ * remainder = (remainder >> 1) ^ multiple; + * } + * + * Note that the other details of endianness have been hidden in CRCPOLY +@@ -330,19 +330,19 @@ + * order, we can actually do the merging 8 or more bits at a time rather + * than one bit at a time: + * for (i = 0; i < input_bytes; i++) { +- * remainder ^= next_input_byte() << 24; +- * for (j = 0; j < 8; j++) { +- * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; +- * remainder = (remainder << 1) ^ multiple; +- * } ++ * remainder ^= next_input_byte() << 24; ++ * for (j = 0; j < 8; j++) { ++ * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; ++ * remainder = (remainder << 1) ^ multiple; ++ * } + * } + * Or in little-endian: + * for (i = 0; i < input_bytes; i++) { +- * remainder ^= next_input_byte(); +- * for (j = 0; j < 8; j++) { +- * multiple = (remainder & 1) ? CRCPOLY : 0; +- * remainder = (remainder << 1) ^ multiple; +- * } ++ * remainder ^= next_input_byte(); ++ * for (j = 0; j < 8; j++) { ++ * multiple = (remainder & 1) ? CRCPOLY : 0; ++ * remainder = (remainder << 1) ^ multiple; ++ * } + * } + * If the input is a multiple of 32 bits, you can even XOR in a 32-bit + * word at a time and increase the inner loop count to 32. +diff -ruN u-boot-2021.10/drivers/mtd/ubi/Kconfig u-boot/drivers/mtd/ubi/Kconfig +--- u-boot-2021.10/drivers/mtd/ubi/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/mtd/ubi/Kconfig 2021-11-01 17:10:14.349587746 +0100 +@@ -68,7 +68,6 @@ + + config MTD_UBI_FASTMAP + bool "UBI Fastmap (Experimental feature)" +- default n + help + Important: this feature is experimental so far and the on-flash + format for fastmap may change in the next kernel versions +diff -ruN u-boot-2021.10/drivers/net/armada100_fec.c u-boot/drivers/net/armada100_fec.c +--- u-boot-2021.10/drivers/net/armada100_fec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/armada100_fec.c 2021-11-01 17:10:14.356254048 +0100 +@@ -717,7 +717,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smi_reg_read; + mdiodev->write = smi_reg_write; + +diff -ruN u-boot-2021.10/drivers/net/at91_emac.c u-boot/drivers/net/at91_emac.c +--- u-boot-2021.10/drivers/net/at91_emac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/at91_emac.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,519 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG +- * Jens Scharsig (esw@bus-elektronik.de) +- * +- * (C) Copyright 2003 +- * Author : Hamid Ikdoumi (Atmel) +- */ +- +-#include <common.h> +-#include <log.h> +-#include <asm/io.h> +-#include <asm/arch/hardware.h> +-#include <asm/arch/at91_emac.h> +-#include <asm/arch/clk.h> +-#include <asm/arch/at91_pio.h> +-#include <net.h> +-#include <netdev.h> +-#include <malloc.h> +-#include <miiphy.h> +-#include <linux/delay.h> +-#include <linux/mii.h> +- +-#undef MII_DEBUG +-#undef ET_DEBUG +- +-#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) +-#error AT91 EMAC supports max 1024 RX buffers. \ +- Please decrease the CONFIG_SYS_RX_ETH_BUFFER value +-#endif +- +-#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR +-#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 +-#endif +- +-/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ +-#if (AT91C_MASTER_CLOCK > 80000000) +- #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 +-#elif (AT91C_MASTER_CLOCK > 40000000) +- #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 +-#elif (AT91C_MASTER_CLOCK > 20000000) +- #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 +-#else +- #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 +-#endif +- +-#ifdef ET_DEBUG +-#define DEBUG_AT91EMAC 1 +-#else +-#define DEBUG_AT91EMAC 0 +-#endif +- +-#ifdef MII_DEBUG +-#define DEBUG_AT91PHY 1 +-#else +-#define DEBUG_AT91PHY 0 +-#endif +- +-#ifndef CONFIG_DRIVER_AT91EMAC_QUIET +-#define VERBOSEP 1 +-#else +-#define VERBOSEP 0 +-#endif +- +-#define RBF_ADDR 0xfffffffc +-#define RBF_OWNER (1<<0) +-#define RBF_WRAP (1<<1) +-#define RBF_BROADCAST (1<<31) +-#define RBF_MULTICAST (1<<30) +-#define RBF_UNICAST (1<<29) +-#define RBF_EXTERNAL (1<<28) +-#define RBF_UNKNOWN (1<<27) +-#define RBF_SIZE 0x07ff +-#define RBF_LOCAL4 (1<<26) +-#define RBF_LOCAL3 (1<<25) +-#define RBF_LOCAL2 (1<<24) +-#define RBF_LOCAL1 (1<<23) +- +-#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER +-#define RBF_FRAMELEN 0x600 +- +-typedef struct { +- unsigned long addr, size; +-} rbf_t; +- +-typedef struct { +- rbf_t rbfdt[RBF_FRAMEMAX]; +- unsigned long rbindex; +-} emac_device; +- +-void at91emac_EnableMDIO(at91_emac_t *at91mac) +-{ +- /* Mac CTRL reg set for MDIO enable */ +- writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); +-} +- +-void at91emac_DisableMDIO(at91_emac_t *at91mac) +-{ +- /* Mac CTRL reg set for MDIO disable */ +- writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); +-} +- +-int at91emac_read(at91_emac_t *at91mac, unsigned char addr, +- unsigned char reg, unsigned short *value) +-{ +- unsigned long netstat; +- at91emac_EnableMDIO(at91mac); +- +- writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | +- AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | +- AT91_EMAC_MAN_PHYA(addr), +- &at91mac->man); +- +- do { +- netstat = readl(&at91mac->sr); +- debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); +- } while (!(netstat & AT91_EMAC_SR_IDLE)); +- +- *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; +- +- at91emac_DisableMDIO(at91mac); +- +- debug_cond(DEBUG_AT91PHY, +- "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value); +- +- return 0; +-} +- +-int at91emac_write(at91_emac_t *at91mac, unsigned char addr, +- unsigned char reg, unsigned short value) +-{ +- unsigned long netstat; +- debug_cond(DEBUG_AT91PHY, +- "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value); +- +- at91emac_EnableMDIO(at91mac); +- +- writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | +- AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | +- AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), +- &at91mac->man); +- +- do { +- netstat = readl(&at91mac->sr); +- debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); +- } while (!(netstat & AT91_EMAC_SR_IDLE)); +- +- at91emac_DisableMDIO(at91mac); +- +- return 0; +-} +- +-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +- +-at91_emac_t *get_emacbase_by_name(const char *devname) +-{ +- struct eth_device *netdev; +- +- netdev = eth_get_dev_by_name(devname); +- return (at91_emac_t *) netdev->iobase; +-} +- +-int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg) +-{ +- unsigned short value = 0; +- at91_emac_t *emac; +- +- emac = get_emacbase_by_name(bus->name); +- at91emac_read(emac , addr, reg, &value); +- return value; +-} +- +- +-int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg, +- u16 value) +-{ +- at91_emac_t *emac; +- +- emac = get_emacbase_by_name(bus->name); +- at91emac_write(emac, addr, reg, value); +- return 0; +-} +- +-#endif +- +-static int at91emac_phy_reset(struct eth_device *netdev) +-{ +- int i; +- u16 status, adv; +- at91_emac_t *emac; +- +- emac = (at91_emac_t *) netdev->iobase; +- +- adv = ADVERTISE_CSMA | ADVERTISE_ALL; +- at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_ADVERTISE, adv); +- debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name); +- at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, +- (BMCR_ANENABLE | BMCR_ANRESTART)); +- +- for (i = 0; i < 30000; i++) { +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_BMSR, &status); +- if (status & BMSR_ANEGCOMPLETE) +- break; +- udelay(100); +- } +- +- if (status & BMSR_ANEGCOMPLETE) { +- debug_cond(VERBOSEP, +- "%s: Autonegotiation complete\n", netdev->name); +- } else { +- printf("%s: Autonegotiation timed out (status=0x%04x)\n", +- netdev->name, status); +- return -1; +- } +- return 0; +-} +- +-static int at91emac_phy_init(struct eth_device *netdev) +-{ +- u16 phy_id, status, adv, lpa; +- int media, speed, duplex; +- int i; +- at91_emac_t *emac; +- +- emac = (at91_emac_t *) netdev->iobase; +- +- /* Check if the PHY is up to snuff... */ +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_PHYSID1, &phy_id); +- if (phy_id == 0xffff) { +- printf("%s: No PHY present\n", netdev->name); +- return -1; +- } +- +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_BMSR, &status); +- +- if (!(status & BMSR_LSTATUS)) { +- /* Try to re-negotiate if we don't have link already. */ +- if (at91emac_phy_reset(netdev)) +- return -2; +- +- for (i = 0; i < 100000 / 100; i++) { +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_BMSR, &status); +- if (status & BMSR_LSTATUS) +- break; +- udelay(100); +- } +- } +- if (!(status & BMSR_LSTATUS)) { +- debug_cond(VERBOSEP, "%s: link down\n", netdev->name); +- return -3; +- } else { +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_ADVERTISE, &adv); +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, +- MII_LPA, &lpa); +- media = mii_nway_result(lpa & adv); +- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) +- ? 1 : 0); +- duplex = (media & ADVERTISE_FULL) ? 1 : 0; +- debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n", +- netdev->name, +- speed ? "100" : "10", +- duplex ? "full" : "half"); +- } +- return 0; +-} +- +-int at91emac_UpdateLinkSpeed(at91_emac_t *emac) +-{ +- unsigned short stat1; +- +- at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); +- +- if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ +- return -1; +- +- if (stat1 & BMSR_100FULL) { +- /*set Emac for 100BaseTX and Full Duplex */ +- writel(readl(&emac->cfg) | +- AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, +- &emac->cfg); +- return 0; +- } +- +- if (stat1 & BMSR_10FULL) { +- /*set MII for 10BaseT and Full Duplex */ +- writel((readl(&emac->cfg) & +- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) +- ) | AT91_EMAC_CFG_FD, +- &emac->cfg); +- return 0; +- } +- +- if (stat1 & BMSR_100HALF) { +- /*set MII for 100BaseTX and Half Duplex */ +- writel((readl(&emac->cfg) & +- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) +- ) | AT91_EMAC_CFG_SPD, +- &emac->cfg); +- return 0; +- } +- +- if (stat1 & BMSR_10HALF) { +- /*set MII for 10BaseT and Half Duplex */ +- writel((readl(&emac->cfg) & +- ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), +- &emac->cfg); +- return 0; +- } +- return 0; +-} +- +-static int at91emac_init(struct eth_device *netdev, struct bd_info *bd) +-{ +- int i; +- u32 value; +- emac_device *dev; +- at91_emac_t *emac; +- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; +- +- emac = (at91_emac_t *) netdev->iobase; +- dev = (emac_device *) netdev->priv; +- +- /* PIO Disable Register */ +- value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | +- ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | +- ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | +- ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | +- ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; +- +- writel(value, &pio->pioa.pdr); +- writel(value, &pio->pioa.mux.pio2.asr); +- +-#ifdef CONFIG_RMII +- value = ATMEL_PMX_BA_ERXCK; +-#else +- value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | +- ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | +- ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | +- ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; +-#endif +- writel(value, &pio->piob.pdr); +- writel(value, &pio->piob.mux.pio2.bsr); +- +- at91_periph_clk_enable(ATMEL_ID_EMAC); +- +- writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); +- +- /* Init Ethernet buffers */ +- for (i = 0; i < RBF_FRAMEMAX; i++) { +- dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i]; +- dev->rbfdt[i].size = 0; +- } +- dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; +- dev->rbindex = 0; +- writel((u32) &(dev->rbfdt[0]), &emac->rbqp); +- +- writel(readl(&emac->rsr) & +- ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), +- &emac->rsr); +- +- value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | +- HCLK_DIV; +-#ifdef CONFIG_RMII +- value |= AT91_EMAC_CFG_RMII; +-#endif +- writel(value, &emac->cfg); +- +- writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, +- &emac->ctl); +- +- if (!at91emac_phy_init(netdev)) { +- at91emac_UpdateLinkSpeed(emac); +- return 0; +- } +- return -1; +-} +- +-static void at91emac_halt(struct eth_device *netdev) +-{ +- at91_emac_t *emac; +- +- emac = (at91_emac_t *) netdev->iobase; +- writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), +- &emac->ctl); +- debug_cond(DEBUG_AT91EMAC, "halt MAC\n"); +-} +- +-static int at91emac_send(struct eth_device *netdev, void *packet, int length) +-{ +- at91_emac_t *emac; +- +- emac = (at91_emac_t *) netdev->iobase; +- +- while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) +- ; +- writel((u32) packet, &emac->tar); +- writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); +- while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) +- ; +- debug_cond(DEBUG_AT91EMAC, "Send %d\n", length); +- writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); +- return 0; +-} +- +-static int at91emac_recv(struct eth_device *netdev) +-{ +- emac_device *dev; +- at91_emac_t *emac; +- rbf_t *rbfp; +- int size; +- +- emac = (at91_emac_t *) netdev->iobase; +- dev = (emac_device *) netdev->priv; +- +- rbfp = &dev->rbfdt[dev->rbindex]; +- while (rbfp->addr & RBF_OWNER) { +- size = rbfp->size & RBF_SIZE; +- net_process_received_packet(net_rx_packets[dev->rbindex], size); +- +- debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n", +- dev->rbindex, size, rbfp->addr); +- +- rbfp->addr &= ~RBF_OWNER; +- rbfp->size = 0; +- if (dev->rbindex < (RBF_FRAMEMAX-1)) +- dev->rbindex++; +- else +- dev->rbindex = 0; +- +- rbfp = &(dev->rbfdt[dev->rbindex]); +- if (!(rbfp->addr & RBF_OWNER)) +- writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, +- &emac->rsr); +- } +- +- if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { +- /* EMAC silicon bug 41.3.1 workaround 1 */ +- writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); +- writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); +- dev->rbindex = 0; +- printf("%s: reset receiver (EMAC dead lock bug)\n", +- netdev->name); +- } +- return 0; +-} +- +-static int at91emac_write_hwaddr(struct eth_device *netdev) +-{ +- at91_emac_t *emac; +- emac = (at91_emac_t *) netdev->iobase; +- +- at91_periph_clk_enable(ATMEL_ID_EMAC); +- +- debug_cond(DEBUG_AT91EMAC, +- "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", +- netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], +- netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); +- writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | +- netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), +- &emac->sa2l); +- writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); +- debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n", +- readl(&emac->sa2h), readl(&emac->sa2l)); +- return 0; +-} +- +-int at91emac_register(struct bd_info *bis, unsigned long iobase) +-{ +- emac_device *emac; +- emac_device *emacfix; +- struct eth_device *dev; +- +- if (iobase == 0) +- iobase = ATMEL_BASE_EMAC; +- emac = malloc(sizeof(*emac)+512); +- if (emac == NULL) +- return -1; +- dev = malloc(sizeof(*dev)); +- if (dev == NULL) { +- free(emac); +- return -1; +- } +- /* alignment as per Errata (64 bytes) is insufficient! */ +- emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); +- memset(emacfix, 0, sizeof(emac_device)); +- +- memset(dev, 0, sizeof(*dev)); +- strcpy(dev->name, "emac"); +- dev->iobase = iobase; +- dev->priv = emacfix; +- dev->init = at91emac_init; +- dev->halt = at91emac_halt; +- dev->send = at91emac_send; +- dev->recv = at91emac_recv; +- dev->write_hwaddr = at91emac_write_hwaddr; +- +- eth_register(dev); +- +-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +- int retval; +- struct mii_dev *mdiodev = mdio_alloc(); +- if (!mdiodev) +- return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); +- mdiodev->read = at91emac_mii_read; +- mdiodev->write = at91emac_mii_write; +- +- retval = mdio_register(mdiodev); +- if (retval < 0) +- return retval; +-#endif +- return 1; +-} +diff -ruN u-boot-2021.10/drivers/net/bcm-sf2-eth.c u-boot/drivers/net/bcm-sf2-eth.c +--- u-boot-2021.10/drivers/net/bcm-sf2-eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/bcm-sf2-eth.c 2021-11-01 17:10:14.356254048 +0100 +@@ -250,7 +250,7 @@ + + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = eth->miiphy_read; + mdiodev->write = eth->miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/calxedaxgmac.c u-boot/drivers/net/calxedaxgmac.c +--- u-boot-2021.10/drivers/net/calxedaxgmac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/calxedaxgmac.c 2021-11-01 17:10:14.356254048 +0100 +@@ -587,7 +587,7 @@ + .start = xgmac_eth_start, + .send = xgmac_tx, + .recv = xgmac_rx, +- .free_pkt = xgmac_free_pkt, ++ .free_pkt = xgmac_free_pkt, + .stop = xgmac_eth_stop, + .write_hwaddr = xgmac_eth_write_hwaddr, + .read_rom_hwaddr = xgmac_eth_read_rom_hwaddr, +diff -ruN u-boot-2021.10/drivers/net/dm9000x.c u-boot/drivers/net/dm9000x.c +--- u-boot-2021.10/drivers/net/dm9000x.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/dm9000x.c 2021-11-01 17:10:14.359587199 +0100 +@@ -28,7 +28,7 @@ + -------------------------------------- + + 12/15/2003 Initial port to u-boot by +- Sascha Hauer <saschahauer@web.de> ++ Sascha Hauer <saschahauer@web.de> + + 06/03/2008 Remy Bohmer <linux@bohmer.net> + - Fixed the driver to work with DM9000A. +@@ -66,7 +66,7 @@ + #define DM9000_DBG(fmt,args...) printf(fmt, ##args) + #define DM9000_DMP_PACKET(func,packet,length) \ + do { \ +- int i; \ ++ int i; \ + printf("%s: length: %d\n", func, length); \ + for (i = 0; i < length; i++) { \ + if (i % 8 == 0) \ +diff -ruN u-boot-2021.10/drivers/net/dsa_sandbox.c u-boot/drivers/net/dsa_sandbox.c +--- u-boot-2021.10/drivers/net/dsa_sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/dsa_sandbox.c 2021-11-01 17:10:14.359587199 +0100 +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + #include <asm/eth.h> +diff -ruN u-boot-2021.10/drivers/net/e1000.c u-boot/drivers/net/e1000.c +--- u-boot-2021.10/drivers/net/e1000.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/e1000.c 2021-11-01 17:10:14.359587199 +0100 +@@ -5251,11 +5251,7 @@ + mdelay(20); + } + +- +- + E1000_WRITE_REG(hw, TCTL, tctl); +- +- + } + + /** +diff -ruN u-boot-2021.10/drivers/net/e1000.h u-boot/drivers/net/e1000.h +--- u-boot-2021.10/drivers/net/e1000.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/e1000.h 2021-11-01 17:10:14.362920350 +0100 +@@ -249,7 +249,7 @@ + #define E1000_ERR_MASTER_REQUESTS_PENDING 10 + #define E1000_ERR_HOST_INTERFACE_COMMAND 11 + #define E1000_BLK_PHY_RESET 12 +-#define E1000_ERR_SWFW_SYNC 13 ++#define E1000_ERR_SWFW_SYNC 13 + + /* PCI Device IDs */ + #define E1000_DEV_ID_82542 0x1000 +diff -ruN u-boot-2021.10/drivers/net/eepro100.c u-boot/drivers/net/eepro100.c +--- u-boot-2021.10/drivers/net/eepro100.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/eepro100.c 2021-11-01 17:10:14.362920350 +0100 +@@ -493,7 +493,7 @@ + if (!mdiodev) + return -ENOMEM; + +- strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, priv->name, MDIO_NAME_LEN); + mdiodev->read = eepro100_miiphy_read; + mdiodev->write = eepro100_miiphy_write; + mdiodev->priv = priv; +diff -ruN u-boot-2021.10/drivers/net/ep93xx_eth.c u-boot/drivers/net/ep93xx_eth.c +--- u-boot-2021.10/drivers/net/ep93xx_eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/ep93xx_eth.c 2021-11-01 17:10:14.362920350 +0100 +@@ -427,7 +427,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); + mdiodev->read = ep93xx_miiphy_read; + mdiodev->write = ep93xx_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/fec_mxc.c u-boot/drivers/net/fec_mxc.c +--- u-boot-2021.10/drivers/net/fec_mxc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fec_mxc.c 2021-11-01 17:10:14.362920350 +0100 +@@ -521,7 +521,7 @@ + &fec->eth->ecntrl); + #endif + +-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) ++#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + udelay(100); + + /* setup the MII gasket for RMII mode */ +diff -ruN u-boot-2021.10/drivers/net/fec_mxc.h u-boot/drivers/net/fec_mxc.h +--- u-boot-2021.10/drivers/net/fec_mxc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fec_mxc.h 2021-11-01 17:10:14.362920350 +0100 +@@ -128,7 +128,7 @@ + + uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ + +-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) ++#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ + uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ + uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ +@@ -196,7 +196,7 @@ + #define FEC_X_DES_ACTIVE_TDAR 0x01000000 + #define FEC_R_DES_ACTIVE_RDAR 0x01000000 + +-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) ++#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + /* defines for MIIGSK */ + /* RMII frequency control: 0=50MHz, 1=5MHz */ + #define MIIGSK_CFGR_FRCONT (1 << 6) +diff -ruN u-boot-2021.10/drivers/net/fm/b4860.c u-boot/drivers/net/fm/b4860.c +--- u-boot-2021.10/drivers/net/fm/b4860.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/b4860.c 2021-11-01 17:10:14.362920350 +0100 +@@ -100,7 +100,7 @@ + env_get_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + +- /* check if XFI interface enable in hwconfig for 10g */ ++ /* check if 10GBase-R interface enable in hwconfig for 10g */ + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { + if ((port == FM1_10GEC1 || +diff -ruN u-boot-2021.10/drivers/net/fm/eth.c u-boot/drivers/net/fm/eth.c +--- u-boot-2021.10/drivers/net/fm/eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/eth.c 2021-11-01 17:10:14.362920350 +0100 +@@ -50,7 +50,7 @@ + u32 value; + struct mii_dev bus; + bool sgmii_2500 = (priv->enet_if == +- PHY_INTERFACE_MODE_SGMII_2500) ? true : false; ++ PHY_INTERFACE_MODE_2500BASEX) ? true : false; + int i = 0, j; + + #ifndef CONFIG_DM_ETH +@@ -133,7 +133,7 @@ + + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || +- fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ++ fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) + dtsec_configure_serdes(fm_eth); + } + +@@ -432,7 +432,7 @@ + + /* For some reason we need to set SPEED_100 */ + if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || +- (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) || ++ (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && + mac->set_if_mode) + mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); +@@ -829,7 +829,7 @@ + + if (fm_eth->type == FM_ETH_10G_E) + supported = PHY_10G_FEATURES; +- if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ++ if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) + supported |= SUPPORTED_2500baseX_Full; + #endif + +@@ -1090,7 +1090,7 @@ + if (fm_eth->num != 0) + break; + case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + fm_eth->pcs_mdio = fm_get_internal_mdio(dev); + break; + default: +diff -ruN u-boot-2021.10/drivers/net/fm/ls1043.c u-boot/drivers/net/fm/ls1043.c +--- u-boot-2021.10/drivers/net/fm/ls1043.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/ls1043.c 2021-11-01 17:10:14.362920350 +0100 +@@ -79,7 +79,7 @@ + case FM1_DTSEC2: + if ((port == FM1_DTSEC2) && + is_serdes_configured(SGMII_2500_FM1_DTSEC2)) +- return PHY_INTERFACE_MODE_SGMII_2500; ++ return PHY_INTERFACE_MODE_2500BASEX; + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: +@@ -87,7 +87,7 @@ + return PHY_INTERFACE_MODE_SGMII; + else if ((port == FM1_DTSEC9) && + is_serdes_configured(SGMII_2500_FM1_DTSEC9)) +- return PHY_INTERFACE_MODE_SGMII_2500; ++ return PHY_INTERFACE_MODE_2500BASEX; + break; + default: + break; +diff -ruN u-boot-2021.10/drivers/net/fm/ls1046.c u-boot/drivers/net/fm/ls1046.c +--- u-boot-2021.10/drivers/net/fm/ls1046.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/ls1046.c 2021-11-01 17:10:14.362920350 +0100 +@@ -99,7 +99,7 @@ + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + + port - FM1_DTSEC5)) +- return PHY_INTERFACE_MODE_SGMII_2500; ++ return PHY_INTERFACE_MODE_2500BASEX; + break; + default: + break; +diff -ruN u-boot-2021.10/drivers/net/fm/memac.c u-boot/drivers/net/fm/memac.c +--- u-boot-2021.10/drivers/net/fm/memac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/memac.c 2021-11-01 17:10:14.362920350 +0100 +@@ -93,12 +93,12 @@ + if_mode |= (IF_MODE_GMII | IF_MODE_RM); + break; + case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_QSGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= (IF_MODE_GMII); + break; +- case PHY_INTERFACE_MODE_XFI: ++ case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; +@@ -107,7 +107,7 @@ + break; + } + /* Enable automatic speed selection for Non-XGMII */ +- if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI) ++ if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER) + if_mode |= IF_MODE_EN_AUTO; + + if (type == PHY_INTERFACE_MODE_RGMII || +diff -ruN u-boot-2021.10/drivers/net/fm/t1024.c u-boot/drivers/net/fm/t1024.c +--- u-boot-2021.10/drivers/net/fm/t1024.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fm/t1024.c 2021-11-01 17:10:14.362920350 +0100 +@@ -63,7 +63,7 @@ + return PHY_INTERFACE_MODE_SGMII; + else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + + port - FM1_DTSEC1)) +- return PHY_INTERFACE_MODE_SGMII_2500; ++ return PHY_INTERFACE_MODE_2500BASEX; + break; + default: + break; +diff -ruN u-boot-2021.10/drivers/net/fsl_enetc.c u-boot/drivers/net/fsl_enetc.c +--- u-boot-2021.10/drivers/net/fsl_enetc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fsl_enetc.c 2021-11-01 17:10:14.366253501 +0100 +@@ -144,7 +144,7 @@ + if (!enetc_has_imdio(dev)) + return 0; + +- if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500) ++ if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX) + is2500 = true; + + /* +@@ -226,9 +226,8 @@ + case PHY_INTERFACE_MODE_RGMII_TXID: + enetc_init_rgmii(dev, phydev); + break; +- case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: +- case PHY_INTERFACE_MODE_XFI: ++ case PHY_INTERFACE_MODE_10GBASER: + /* set ifmode to (US)XGMII */ + if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); + if_mode &= ~ENETC_PM_IF_IFMODE_MASK; +@@ -270,7 +269,7 @@ + priv->imdio.read = enetc_mdio_read; + priv->imdio.write = enetc_mdio_write; + priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; +- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); ++ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); + if (!miiphy_get_dev_by_name(priv->imdio.name)) + mdio_register(&priv->imdio); + } +@@ -291,12 +290,11 @@ + + switch (priv->if_type) { + case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + enetc_init_sgmii(dev); + break; +- case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: +- case PHY_INTERFACE_MODE_XFI: ++ case PHY_INTERFACE_MODE_10GBASER: + enetc_init_sxgmii(dev); + break; + }; +diff -ruN u-boot-2021.10/drivers/net/fsl-mc/dpni.c u-boot/drivers/net/fsl-mc/dpni.c +--- u-boot-2021.10/drivers/net/fsl-mc/dpni.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fsl-mc/dpni.c 2021-11-01 17:10:14.366253501 +0100 +@@ -525,4 +525,3 @@ + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); + } +- +diff -ruN u-boot-2021.10/drivers/net/fsl_mcdmafec.c u-boot/drivers/net/fsl_mcdmafec.c +--- u-boot-2021.10/drivers/net/fsl_mcdmafec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/fsl_mcdmafec.c 2021-11-01 17:10:14.366253501 +0100 +@@ -541,7 +541,7 @@ + info->bus = mdio_alloc(); + if (!info->bus) + return -ENOMEM; +- strncpy(info->bus->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN); + info->bus->read = mcffec_miiphy_read; + info->bus->write = mcffec_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/ftmac110.c u-boot/drivers/net/ftmac110.c +--- u-boot-2021.10/drivers/net/ftmac110.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/ftmac110.c 2021-11-01 17:10:14.366253501 +0100 +@@ -476,7 +476,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = ftmac110_mdio_read; + mdiodev->write = ftmac110_mdio_write; + +diff -ruN u-boot-2021.10/drivers/net/Kconfig u-boot/drivers/net/Kconfig +--- u-boot-2021.10/drivers/net/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/Kconfig 2021-11-01 17:10:14.356254048 +0100 +@@ -2,6 +2,9 @@ + source "drivers/net/pfe_eth/Kconfig" + source "drivers/net/fsl-mc/Kconfig" + ++config ETH ++ def_bool y ++ + config DM_ETH + bool "Enable Driver Model for Ethernet drivers" + depends on DM +@@ -557,7 +560,6 @@ + + config SMC911X_32_BIT + bool "Enable SMC911X 32-bit interface" +- default n + help + Define this if data bus is 32 bits. If your processor use a + narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit +@@ -711,7 +713,6 @@ + config PHY_NORXERR + bool "PHY_NORXERR" + depends on ETHER_ON_FEC1 +- default n + help + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). +@@ -736,7 +737,6 @@ + config FEC2_PHY_NORXERR + bool "PHY_NORXERR" + depends on ETHER_ON_FEC2 +- default n + help + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). +diff -ruN u-boot-2021.10/drivers/net/lpc32xx_eth.c u-boot/drivers/net/lpc32xx_eth.c +--- u-boot-2021.10/drivers/net/lpc32xx_eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/lpc32xx_eth.c 2021-11-01 17:10:14.369586652 +0100 +@@ -638,7 +638,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = mii_reg_read; + mdiodev->write = mii_reg_write; + +diff -ruN u-boot-2021.10/drivers/net/macb.c u-boot/drivers/net/macb.c +--- u-boot-2021.10/drivers/net/macb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/macb.c 2021-11-01 17:10:14.369586652 +0100 +@@ -1245,7 +1245,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); + mdiodev->read = macb_miiphy_read; + mdiodev->write = macb_miiphy_write; + +@@ -1403,7 +1403,7 @@ + macb->bus = mdio_alloc(); + if (!macb->bus) + return -ENOMEM; +- strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN); + macb->bus->read = macb_miiphy_read; + macb->bus->write = macb_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/Makefile u-boot/drivers/net/Makefile +--- u-boot-2021.10/drivers/net/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/Makefile 2021-11-01 17:10:14.356254048 +0100 +@@ -3,13 +3,14 @@ + # (C) Copyright 2006 + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. + ++obj-y += phy/ ++ + obj-$(CONFIG_ALTERA_TSE) += altera_tse.o + obj-$(CONFIG_AG7XXX) += ag7xxx.o + obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o + obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o + obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o + obj-$(CONFIG_BCMGENET) += bcmgenet.o +-obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o + obj-$(CONFIG_DRIVER_AX88180) += ax88180.o + obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o + obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o +@@ -33,6 +34,7 @@ + obj-$(CONFIG_EP93XX) += ep93xx_eth.o + obj-$(CONFIG_ETHOC) += ethoc.o + obj-$(CONFIG_FEC_MXC) += fec_mxc.o ++obj-$(CONFIG_FMAN_ENET) += fm/ + obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o + obj-$(CONFIG_FTGMAC100) += ftgmac100.o + obj-$(CONFIG_FTMAC110) += ftmac110.o +diff -ruN u-boot-2021.10/drivers/net/mpc8xx_fec.c u-boot/drivers/net/mpc8xx_fec.c +--- u-boot-2021.10/drivers/net/mpc8xx_fec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/mpc8xx_fec.c 2021-11-01 17:10:14.369586652 +0100 +@@ -160,7 +160,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec8xx_miiphy_read; + mdiodev->write = fec8xx_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/mscc_eswitch/felix_switch.c u-boot/drivers/net/mscc_eswitch/felix_switch.c +--- u-boot-2021.10/drivers/net/mscc_eswitch/felix_switch.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/mscc_eswitch/felix_switch.c 2021-11-01 17:10:14.369586652 +0100 +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + /* + * Felix (VSC9959) Ethernet switch driver +- * Copyright 2018-2021 NXP Semiconductors ++ * Copyright 2018-2021 NXP + */ + + /* +@@ -213,17 +213,16 @@ + bool autoneg = true; + + if (phy->phy_id == PHY_FIXED_ID || +- phy->interface == PHY_INTERFACE_MODE_SGMII_2500) ++ phy->interface == PHY_INTERFACE_MODE_2500BASEX) + autoneg = false; + + switch (phy->interface) { + case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_QSGMII: + felix_init_sgmii(imdio, port, autoneg); + break; +- case PHY_INTERFACE_MODE_XGMII: +- case PHY_INTERFACE_MODE_XFI: ++ case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_USXGMII: + if (felix_init_sxgmii(imdio, port)) + dev_err(dev, "PCS reset timeout on port %d\n", port); +@@ -233,7 +232,7 @@ + } + } + +-void felix_init(struct udevice *dev) ++static void felix_init(struct udevice *dev) + { + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + struct felix_priv *priv = dev_get_priv(dev); +@@ -258,7 +257,7 @@ + priv->imdio.read = felix_mdio_read; + priv->imdio.write = felix_mdio_write; + priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; +- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); ++ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); + + /* set up CPU port */ + out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG, +@@ -276,6 +275,7 @@ + static int felix_probe(struct udevice *dev) + { + struct felix_priv *priv = dev_get_priv(dev); ++ int err; + + if (ofnode_valid(dev_ofnode(dev)) && + !ofnode_is_available(dev_ofnode(dev))) { +@@ -300,11 +300,18 @@ + struct mii_dev *mii_bus; + + mii_bus = mdio_alloc(); ++ if (!mii_bus) ++ return -ENOMEM; ++ + mii_bus->read = felix_mdio_read; + mii_bus->write = felix_mdio_write; + mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE; +- strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN); +- mdio_register(mii_bus); ++ strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN); ++ err = mdio_register(mii_bus); ++ if (err) { ++ mdio_free(mii_bus); ++ return err; ++ } + } + + dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); +@@ -317,10 +324,23 @@ + return 0; + } + ++static int felix_port_probe(struct udevice *dev, int port, ++ struct phy_device *phy) ++{ ++ int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; ++ struct felix_priv *priv = dev_get_priv(dev); ++ ++ phy->supported &= supported; ++ phy->advertising &= supported; ++ ++ felix_start_pcs(dev, port, phy, &priv->imdio); ++ ++ return phy_config(phy); ++} ++ + static int felix_port_enable(struct udevice *dev, int port, + struct phy_device *phy) + { +- int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; + struct felix_priv *priv = dev_get_priv(dev); + void *base = priv->regs_base; + +@@ -339,15 +359,7 @@ + FELIX_QSYS_SYSTEM_SW_PORT_LOSSY | + FELIX_QSYS_SYSTEM_SW_PORT_SCH(1)); + +- felix_start_pcs(dev, port, phy, &priv->imdio); +- +- phy->supported &= supported; +- phy->advertising &= supported; +- phy_config(phy); +- +- phy_startup(phy); +- +- return 0; ++ return phy_startup(phy); + } + + static void felix_port_disable(struct udevice *dev, int pidx, +@@ -392,6 +404,7 @@ + } + + static const struct dsa_ops felix_dsa_ops = { ++ .port_probe = felix_port_probe, + .port_enable = felix_port_enable, + .port_disable = felix_port_disable, + .xmit = felix_xmit, +diff -ruN u-boot-2021.10/drivers/net/mvgbe.c u-boot/drivers/net/mvgbe.c +--- u-boot-2021.10/drivers/net/mvgbe.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/mvgbe.c 2021-11-01 17:10:14.372919803 +0100 +@@ -883,7 +883,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smi_reg_read; + mdiodev->write = smi_reg_write; + +diff -ruN u-boot-2021.10/drivers/net/mvmdio.c u-boot/drivers/net/mvmdio.c +--- u-boot-2021.10/drivers/net/mvmdio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/mvmdio.c 2021-11-01 17:10:14.372919803 +0100 +@@ -234,4 +234,3 @@ + .ops = &mvmdio_ops, + .priv_auto = sizeof(struct mvmdio_priv), + }; +- +diff -ruN u-boot-2021.10/drivers/net/octeontx/nic_main.c u-boot/drivers/net/octeontx/nic_main.c +--- u-boot-2021.10/drivers/net/octeontx/nic_main.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/octeontx/nic_main.c 2021-11-01 17:10:14.376252954 +0100 +@@ -775,4 +775,3 @@ + }; + + U_BOOT_PCI_DEVICE(octeontx_nic, octeontx_nic_supported); +- +diff -ruN u-boot-2021.10/drivers/net/octeontx2/Makefile u-boot/drivers/net/octeontx2/Makefile +--- u-boot-2021.10/drivers/net/octeontx2/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/octeontx2/Makefile 2021-11-01 17:10:14.376252954 +0100 +@@ -5,4 +5,3 @@ + + obj-$(CONFIG_NET_OCTEONTX2) += cgx.o nix_af.o nix.o rvu_pf.o \ + rvu_af.o rvu_common.o +- +diff -ruN u-boot-2021.10/drivers/net/octeontx2/nix.c u-boot/drivers/net/octeontx2/nix.c +--- u-boot-2021.10/drivers/net/octeontx2/nix.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/octeontx2/nix.c 2021-11-01 17:10:14.376252954 +0100 +@@ -828,4 +828,3 @@ + printf(" CGX%d LMAC%d [%s]", lmac->cgx->cgx_id, lmac->lmac_id, + lmac_type_to_str[lmac->lmac_type]); + } +- +diff -ruN u-boot-2021.10/drivers/net/octeontx2/npc.h u-boot/drivers/net/octeontx2/npc.h +--- u-boot-2021.10/drivers/net/octeontx2/npc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/octeontx2/npc.h 2021-11-01 17:10:14.379586105 +0100 +@@ -87,4 +87,3 @@ + } + + #endif /* __NPC_H__ */ +- +diff -ruN u-boot-2021.10/drivers/net/octeontx2/rvu.h u-boot/drivers/net/octeontx2/rvu.h +--- u-boot-2021.10/drivers/net/octeontx2/rvu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/octeontx2/rvu.h 2021-11-01 17:10:14.379586105 +0100 +@@ -116,4 +116,3 @@ + void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid); + + #endif /* __RVU_H__ */ +- +diff -ruN u-boot-2021.10/drivers/net/pfe_eth/pfe_mdio.c u-boot/drivers/net/pfe_eth/pfe_mdio.c +--- u-boot-2021.10/drivers/net/pfe_eth/pfe_mdio.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/pfe_eth/pfe_mdio.c 2021-11-01 17:10:14.379586105 +0100 +@@ -161,7 +161,7 @@ + int value, sgmii_2500 = 0; + struct gemac_s *gem = priv->gem; + +- if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) ++ if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) + sgmii_2500 = 1; + + +@@ -220,7 +220,7 @@ + + /* Configure SGMII PCS */ + if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII || +- gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) { ++ gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { + out_be32(&scfg->mdioselcr, 0x00000000); + pfe_configure_serdes(priv); + } +diff -ruN u-boot-2021.10/drivers/net/phy/aquantia.c u-boot/drivers/net/phy/aquantia.c +--- u-boot-2021.10/drivers/net/phy/aquantia.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/phy/aquantia.c 2021-11-01 17:10:14.379586105 +0100 +@@ -308,9 +308,9 @@ + } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = { + [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, + AQUANTIA_VND1_GSTART_RATE_1G}, +- [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, ++ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, + AQUANTIA_VND1_GSTART_RATE_2_5G}, +- [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, ++ [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, + AQUANTIA_VND1_GSTART_RATE_10G}, + [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, + AQUANTIA_VND1_GSTART_RATE_10G}, +@@ -443,18 +443,18 @@ + return ret; + } + /* +- * for backward compatibility convert XGMII into either XFI or USX based +- * on FW config ++ * for backward compatibility convert XGMII into either 10GBase-R or ++ * USXGMII based on FW config + */ + if (interface == PHY_INTERFACE_MODE_XGMII) { +- debug("use XFI or USXGMII SI protos, XGMII is not valid\n"); ++ debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); + + reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_SYSTEM_INTERFACE_SR); + if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) + interface = PHY_INTERFACE_MODE_USXGMII; + else +- interface = PHY_INTERFACE_MODE_XFI; ++ interface = PHY_INTERFACE_MODE_10GBASER; + } + + /* +@@ -494,7 +494,7 @@ + case PHY_INTERFACE_MODE_USXGMII: + usx_an = 1; + /* FALLTHROUGH */ +- case PHY_INTERFACE_MODE_XFI: ++ case PHY_INTERFACE_MODE_10GBASER: + /* 10GBASE-T mode */ + phydev->advertising = SUPPORTED_10000baseT_Full; + phydev->supported = phydev->advertising; +@@ -515,14 +515,14 @@ + phydev->dev->name); + } else { + reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; +- debug("%s: system interface XFI\n", ++ debug("%s: system interface 10GBase-R\n", + phydev->dev->name); + } + + phy_write(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); + break; +- case PHY_INTERFACE_MODE_SGMII_2500: ++ case PHY_INTERFACE_MODE_2500BASEX: + /* 2.5GBASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; +diff -ruN u-boot-2021.10/drivers/net/phy/Kconfig u-boot/drivers/net/phy/Kconfig +--- u-boot-2021.10/drivers/net/phy/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/phy/Kconfig 2021-11-01 17:10:14.379586105 +0100 +@@ -15,14 +15,14 @@ + + config PHY_ADDR_ENABLE + bool "Limit phy address" +- default y if ARCH_SUNXI ++ default y if (ARCH_SUNXI || TARGET_SUNXI) + help + Select this if you want to control which phy address is used + + if PHY_ADDR_ENABLE + config PHY_ADDR + int "PHY address" +- default 1 if ARCH_SUNXI ++ default 1 if (ARCH_SUNXI || TARGET_SUNXI) + default 0 + help + The address of PHY on MII bus. Usually in range of 0 to 31. +@@ -71,7 +71,6 @@ + + config PHY_AQUANTIA_UPLOAD_FW + bool "Aquantia firmware loading support" +- default n + depends on PHY_AQUANTIA + help + Aquantia PHYs use firmware which can be either loaded automatically +@@ -102,7 +101,6 @@ + + config SYS_CORTINA_NO_FW_UPLOAD + bool "Cortina firmware loading support" +- default n + depends on PHY_CORTINA + help + Cortina phy has provision to store phy firmware in attached dedicated +@@ -216,16 +214,6 @@ + config PHY_REALTEK + bool "Realtek Ethernet PHYs support" + +-config RTL8211E_PINE64_GIGABIT_FIX +- bool "Fix gigabit throughput on some Pine64+ models" +- depends on PHY_REALTEK +- help +- Configure the Realtek RTL8211E found on some Pine64+ models differently to +- fix throughput on Gigabit links, turning off all internal delays in the +- process. The settings that this touches are not documented in the CONFREG +- section of the RTL8211E datasheet, but come from Realtek by way of the +- Pine64 engineering team. +- + config RTL8211X_PHY_FORCE_MASTER + bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode" + depends on PHY_REALTEK +@@ -250,7 +238,6 @@ + config RTL8211F_PHY_FORCE_EEE_RXC_ON + bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" + depends on PHY_REALTEK +- default n + help + The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate + transitions to/from a lower power consumption level (Low Power Idle +diff -ruN u-boot-2021.10/drivers/net/phy/meson-gxl.c u-boot/drivers/net/phy/meson-gxl.c +--- u-boot-2021.10/drivers/net/phy/meson-gxl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/phy/meson-gxl.c 2021-11-01 17:10:14.379586105 +0100 +@@ -73,7 +73,7 @@ + + if (!(wol & BIT(12)) || + ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { +- ++ + /* Looks like aneg failed after all */ + if (!retries) { + printf("%s LPA corruption max attempts\n", +diff -ruN u-boot-2021.10/drivers/net/phy/phy.c u-boot/drivers/net/phy/phy.c +--- u-boot-2021.10/drivers/net/phy/phy.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/phy/phy.c 2021-11-01 17:10:14.382919256 +0100 +@@ -463,7 +463,7 @@ + .shutdown = genphy_shutdown, + }; + +-int genphy_init(void) ++static int genphy_init(void) + { + return phy_register(&genphy_driver); + } +diff -ruN u-boot-2021.10/drivers/net/phy/realtek.c u-boot/drivers/net/phy/realtek.c +--- u-boot-2021.10/drivers/net/phy/realtek.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/phy/realtek.c 2021-11-01 17:10:14.382919256 +0100 +@@ -12,7 +12,6 @@ + #include <linux/delay.h> + + #define PHY_RTL8211x_FORCE_MASTER BIT(1) +-#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) + #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3) + #define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4) + +@@ -49,10 +48,10 @@ + #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800 + #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004 + +-#define MIIM_RTL8211E_CONFREG 0x1c +-#define MIIM_RTL8211E_CONFREG_TXD 0x0002 +-#define MIIM_RTL8211E_CONFREG_RXD 0x0004 +-#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */ ++#define MIIM_RTL8211E_CONFREG 0x1c ++#define MIIM_RTL8211E_CTRL_DELAY BIT(13) ++#define MIIM_RTL8211E_TX_DELAY BIT(12) ++#define MIIM_RTL8211E_RX_DELAY BIT(11) + + #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e + +@@ -108,10 +107,6 @@ + + static int rtl8211e_probe(struct phy_device *phydev) + { +-#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX +- phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX; +-#endif +- + return 0; + } + +@@ -154,22 +149,6 @@ + reg |= MIIM_RTL8211x_CTRL1000T_MASTER; + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); + } +- if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) { +- unsigned int reg; +- +- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, +- 7); +- phy_write(phydev, MDIO_DEVAD_NONE, +- MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4); +- reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); +- /* Ensure both internal delays are turned off */ +- reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD); +- /* Flip the magic undocumented bits */ +- reg |= MIIM_RTL8211E_CONFREG_MAGIC; +- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg); +- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, +- 0); +- } + /* read interrupt status just to clear it */ + phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); + +@@ -201,6 +180,44 @@ + return 0; + } + ++static int rtl8211e_config(struct phy_device *phydev) ++{ ++ int reg, val; ++ ++ /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ ++ switch (phydev->interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ val = MIIM_RTL8211E_CTRL_DELAY; ++ break; ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY | ++ MIIM_RTL8211E_RX_DELAY; ++ break; ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY; ++ break; ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_RX_DELAY; ++ break; ++ default: /* the rest of the modes imply leaving delays as is. */ ++ goto default_delay; ++ } ++ ++ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7); ++ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4); ++ ++ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); ++ reg &= ~(MIIM_RTL8211E_TX_DELAY | MIIM_RTL8211E_RX_DELAY); ++ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg | val); ++ ++ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0); ++ ++default_delay: ++ genphy_config_aneg(phydev); ++ ++ return 0; ++} ++ + static int rtl8211f_config(struct phy_device *phydev) + { + u16 reg; +@@ -410,7 +427,7 @@ + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .probe = &rtl8211e_probe, +- .config = &rtl8211x_config, ++ .config = &rtl8211e_config, + .startup = &rtl8211e_startup, + .shutdown = &genphy_shutdown, + }; +diff -ruN u-boot-2021.10/drivers/net/sh_eth.c u-boot/drivers/net/sh_eth.c +--- u-boot-2021.10/drivers/net/sh_eth.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/sh_eth.c 2021-11-01 17:10:14.386252408 +0100 +@@ -657,7 +657,7 @@ + mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/smc91111.h u-boot/drivers/net/smc91111.h +--- u-boot-2021.10/drivers/net/smc91111.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/smc91111.h 2021-11-01 17:10:14.386252408 +0100 +@@ -251,18 +251,14 @@ + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +-#ifdef CONFIG_ADNPESC1 +-#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) +-#elif CONFIG_ARM64 ++#if CONFIG_ARM64 + #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) + #else + #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) + #endif + #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) + +-#ifdef CONFIG_ADNPESC1 +-#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) +-#elif CONFIG_ARM64 ++#if CONFIG_ARM64 + #define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+((dword)(r)))) = d) + #else +@@ -442,11 +438,6 @@ + #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +-#elif defined(CONFIG_ADNPESC1) +-/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ +-#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ +- | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ +- | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) + #else + /* SMSC reference design: LEDa --> green, LEDb --> yellow */ + #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ +diff -ruN u-boot-2021.10/drivers/net/smc911x.c u-boot/drivers/net/smc911x.c +--- u-boot-2021.10/drivers/net/smc911x.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/smc911x.c 2021-11-01 17:10:14.386252408 +0100 +@@ -425,7 +425,7 @@ + if (!mdiodev) + return -ENOMEM; + +- strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); + mdiodev->read = smc911x_miiphy_read; + mdiodev->write = smc911x_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/net/smc911x.h u-boot/drivers/net/smc911x.h +--- u-boot-2021.10/drivers/net/smc911x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/smc911x.h 2021-11-01 17:10:14.386252408 +0100 +@@ -13,9 +13,9 @@ + /* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +-#define RX_DATA_FIFO 0x00 ++#define RX_DATA_FIFO 0x00 + +-#define TX_DATA_FIFO 0x20 ++#define TX_DATA_FIFO 0x20 + #define TX_CMD_A_INT_ON_COMP 0x80000000 + #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 + #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 +diff -ruN u-boot-2021.10/drivers/net/sun8i_emac.c u-boot/drivers/net/sun8i_emac.c +--- u-boot-2021.10/drivers/net/sun8i_emac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/sun8i_emac.c 2021-11-01 17:10:14.386252408 +0100 +@@ -14,9 +14,11 @@ + #include <log.h> + #include <asm/cache.h> + #include <asm/global_data.h> ++#include <asm/gpio.h> + #include <asm/io.h> ++#if 0 + #include <asm/arch/clock.h> +-#include <asm/arch/gpio.h> ++#endif + #include <common.h> + #include <clk.h> + #include <dm.h> +@@ -29,11 +31,7 @@ + #include <miiphy.h> + #include <net.h> + #include <reset.h> +-#include <dt-bindings/pinctrl/sun4i-a10.h> + #include <wait_bit.h> +-#if CONFIG_IS_ENABLED(DM_GPIO) +-#include <asm-generic/gpio.h> +-#endif + + #define MDIO_CMD_MII_BUSY BIT(0) + #define MDIO_CMD_MII_WRITE BIT(1) +@@ -84,13 +82,6 @@ + + #define AHB_GATE_OFFSET_EPHY 0 + +-/* IO mux settings */ +-#define SUN8I_IOMUX_H3 2 +-#define SUN8I_IOMUX_R40 5 +-#define SUN8I_IOMUX_H6 5 +-#define SUN8I_IOMUX_H616 2 +-#define SUN8I_IOMUX 4 +- + /* H3/A64 EMAC Register's offset */ + #define EMAC_CTL0 0x00 + #define EMAC_CTL0_FULL_DUPLEX BIT(0) +@@ -174,7 +165,7 @@ + + enum emac_variant variant; + void *mac_reg; +- phys_addr_t sysctl_reg; ++ void *sysctl_reg; + struct phy_device *phydev; + struct mii_dev *bus; + struct clk tx_clk; +@@ -330,6 +321,7 @@ + u32 reg; + + if (priv->variant == R40_GMAC) { ++#define CONFIG_GMAC_TX_DELAY 0 + /* Select RGMII for R40 */ + reg = readl(priv->sysctl_reg + 0x164); + reg |= SC_ETCS_INT_GMII | +@@ -403,7 +395,7 @@ + } + + #define cache_clean_descriptor(desc) \ +- flush_dcache_range((uintptr_t)(desc), \ ++ flush_dcache_range((uintptr_t)(desc), \ + (uintptr_t)(desc) + sizeof(struct emac_dma_desc)) + + #define cache_inv_descriptor(desc) \ +@@ -522,85 +514,6 @@ + return 0; + } + +-static int parse_phy_pins(struct udevice *dev) +-{ +- int offset; +- const char *pin_name; +- int drive, pull = SUN4I_PINCTRL_NO_PULL, i; +- u32 iomux; +- +- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), +- "pinctrl-0"); +- if (offset < 0) { +- printf("WARNING: emac: cannot find pinctrl-0 node\n"); +- return offset; +- } +- +- drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, +- "drive-strength", ~0); +- if (drive != ~0) { +- if (drive <= 10) +- drive = SUN4I_PINCTRL_10_MA; +- else if (drive <= 20) +- drive = SUN4I_PINCTRL_20_MA; +- else if (drive <= 30) +- drive = SUN4I_PINCTRL_30_MA; +- else +- drive = SUN4I_PINCTRL_40_MA; +- } +- +- if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL)) +- pull = SUN4I_PINCTRL_PULL_UP; +- else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL)) +- pull = SUN4I_PINCTRL_PULL_DOWN; +- +- /* +- * The GPIO pinmux value is an integration choice, so depends on the +- * SoC, not the EMAC variant. +- */ +- if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) +- iomux = SUN8I_IOMUX_H3; +- else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) +- iomux = SUN8I_IOMUX_R40; +- else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) +- iomux = SUN8I_IOMUX_H6; +- else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) +- iomux = SUN8I_IOMUX_H616; +- else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T)) +- iomux = SUN8I_IOMUX; +- else if (IS_ENABLED(CONFIG_MACH_SUN50I)) +- iomux = SUN8I_IOMUX; +- else +- BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins"); +- +- for (i = 0; ; i++) { +- int pin; +- +- pin_name = fdt_stringlist_get(gd->fdt_blob, offset, +- "pins", i, NULL); +- if (!pin_name) +- break; +- +- pin = sunxi_name_to_gpio(pin_name); +- if (pin < 0) +- continue; +- +- sunxi_gpio_set_cfgpin(pin, iomux); +- +- if (drive != ~0) +- sunxi_gpio_set_drv(pin, drive); +- if (pull != ~0) +- sunxi_gpio_set_pull(pin, pull); +- } +- +- if (!i) { +- printf("WARNING: emac: cannot find pins property\n"); +- return -2; +- } +- +- return 0; +-} +- + static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) + { + struct emac_eth_dev *priv = dev_get_priv(dev); +@@ -931,9 +844,9 @@ + __func__); + return -EINVAL; + } +- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, ++ priv->sysctl_reg = (void *)fdt_translate_address((void *)gd->fdt_blob, + offset, reg); +- if (priv->sysctl_reg == FDT_ADDR_T_NONE) { ++ if (priv->sysctl_reg == (void *)FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; + } +@@ -953,7 +866,7 @@ + + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); +- printf("phy interface%d\n", pdata->phy_interface); ++ debug("phy interface %d\n", pdata->phy_interface); + + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); +@@ -968,9 +881,6 @@ + + priv->interface = pdata->phy_interface; + +- if (!priv->use_internal_phy) +- parse_phy_pins(dev); +- + sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,tx-delay-ps", 0); + if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700) +@@ -1005,6 +915,8 @@ + + static const struct udevice_id sun8i_emac_eth_ids[] = { + {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, ++ {.compatible = "allwinner,sun20i-d1-emac", ++ .data = (uintptr_t)A64_EMAC }, + {.compatible = "allwinner,sun50i-a64-emac", + .data = (uintptr_t)A64_EMAC }, + {.compatible = "allwinner,sun8i-a83t-emac", +diff -ruN u-boot-2021.10/drivers/net/sunxi_emac.c u-boot/drivers/net/sunxi_emac.c +--- u-boot-2021.10/drivers/net/sunxi_emac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/sunxi_emac.c 2021-11-01 17:10:14.386252408 +0100 +@@ -17,7 +17,6 @@ + #include <net.h> + #include <asm/io.h> + #include <asm/arch/clock.h> +-#include <asm/arch/gpio.h> + + /* EMAC register */ + struct emac_regs { +@@ -516,10 +515,6 @@ + /* Map SRAM to EMAC */ + setbits_le32(&sram->ctrl1, 0x5 << 2); + +- /* Configure pin mux settings for MII Ethernet */ +- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) +- sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); +- + /* Set up clock gating */ + ret = clk_enable(&priv->clk); + if (ret) { +diff -ruN u-boot-2021.10/drivers/net/ti/davinci_emac.c u-boot/drivers/net/ti/davinci_emac.c +--- u-boot-2021.10/drivers/net/ti/davinci_emac.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/ti/davinci_emac.c 2021-11-01 17:10:14.389585558 +0100 +@@ -816,7 +816,7 @@ + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); + mdiodev->read = davinci_mii_phy_read; + mdiodev->write = davinci_mii_phy_write; + +diff -ruN u-boot-2021.10/drivers/net/tsec.c u-boot/drivers/net/tsec.c +--- u-boot-2021.10/drivers/net/tsec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/net/tsec.c 2021-11-01 17:10:14.389585558 +0100 +@@ -638,7 +638,7 @@ + return priv->phydev->link ? 0 : -1; + } + +-static phy_interface_t tsec_get_interface(struct tsec_private *priv) ++static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv) + { + struct tsec __iomem *regs = priv->regs; + u32 ecntrl; +@@ -701,8 +701,6 @@ + /* Assign a Physical address to the TBI */ + out_be32(®s->tbipa, priv->tbiaddr); + +- priv->interface = tsec_get_interface(priv); +- + if (priv->interface == PHY_INTERFACE_MODE_SGMII) + tsec_configure_serdes(priv); + +@@ -886,12 +884,13 @@ + priv->tbiaddr = tbiaddr; + + phy_mode = dev_read_prop(dev, "phy-connection-type", NULL); ++ if (!phy_mode) ++ phy_mode = dev_read_prop(dev, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); +- if (pdata->phy_interface == -1) { +- printf("Invalid PHY interface '%s'\n", phy_mode); +- return -EINVAL; +- } ++ if (pdata->phy_interface == -1) ++ pdata->phy_interface = tsec_get_interface(priv); ++ + priv->interface = pdata->phy_interface; + + /* Check for speed limit, default is 1000Mbps */ +diff -ruN u-boot-2021.10/drivers/pch/pch-uclass.c u-boot/drivers/pch/pch-uclass.c +--- u-boot-2021.10/drivers/pch/pch-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pch/pch-uclass.c 2021-11-01 17:10:14.392918709 +0100 +@@ -66,7 +66,7 @@ + UCLASS_DRIVER(pch) = { + .id = UCLASS_PCH, + .name = "pch", +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/drivers/pci/fsl_pci_init.c u-boot/drivers/pci/fsl_pci_init.c +--- u-boot-2021.10/drivers/pci/fsl_pci_init.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/fsl_pci_init.c 2021-11-01 17:10:14.392918709 +0100 +@@ -885,7 +885,7 @@ + setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ + #endif + +- return busno; ++ return busno; + } + #else + int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, +diff -ruN u-boot-2021.10/drivers/pci/Kconfig u-boot/drivers/pci/Kconfig +--- u-boot-2021.10/drivers/pci/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/Kconfig 2021-11-01 17:10:14.392918709 +0100 +@@ -21,7 +21,6 @@ + + config PCI_AARDVARK + bool "Enable Aardvark PCIe driver" +- default n + depends on DM_GPIO + depends on ARMADA_3700 + help +@@ -37,7 +36,6 @@ + + config PCI_REGION_MULTI_ENTRY + bool "Enable Multiple entries of region type MEMORY in ranges for PCI" +- default n + help + Enable PCI memory regions to be of multiple entry. Multiple entry + here refers to allow more than one count of address ranges for MEMORY +@@ -47,7 +45,6 @@ + config PCI_MAP_SYSTEM_MEMORY + bool "Map local system memory from a virtual base address" + depends on MIPS +- default n + help + Say Y if base address of system memory is being used as a virtual address + instead of a physical address (e.g. on MIPS). The PCI core will then remap +@@ -58,7 +55,6 @@ + + config PCI_SRIOV + bool "Enable Single Root I/O Virtualization support for PCI" +- default n + help + Say Y here if you want to enable PCI Single Root I/O Virtualization + capability support. This helps to enumerate Virtual Function devices +@@ -67,7 +63,6 @@ + + config PCI_ARID + bool "Enable Alternate Routing-ID support for PCI" +- default n + help + Say Y here if you want to enable Alternate Routing-ID capability + support on PCI devices. This helps to skip some devices in BDF +@@ -75,14 +70,12 @@ + + config PCIE_ECAM_GENERIC + bool "Generic ECAM-based PCI host controller support" +- default n + help + Say Y here if you want to enable support for generic ECAM-based + PCIe host controllers, such as the one emulated by QEMU. + + config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" +- default n + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help +@@ -186,7 +179,6 @@ + + config PCIE_LAYERSCAPE + bool +- default n + + config PCIE_LAYERSCAPE_RC + bool "Layerscape PCIe Root Complex mode support" +diff -ruN u-boot-2021.10/drivers/pci/pci_auto.c u-boot/drivers/pci/pci_auto.c +--- u-boot-2021.10/drivers/pci/pci_auto.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pci_auto.c 2021-11-01 17:10:14.392918709 +0100 +@@ -12,6 +12,7 @@ + #include <errno.h> + #include <log.h> + #include <pci.h> ++#include "pci_internal.h" + + /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ + #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE +@@ -165,6 +166,7 @@ + struct pci_region *pci_prefetch; + struct pci_region *pci_io; + u16 cmdstat, prefechable_64; ++ u8 io_32; + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); + +@@ -175,6 +177,8 @@ + dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); + dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; ++ dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); ++ io_32 &= PCI_IO_RANGE_TYPE_MASK; + + /* Configure bus number registers */ + dm_pci_write_config8(dev, PCI_PRIMARY_BUS, +@@ -191,7 +195,8 @@ + * I/O space + */ + dm_pci_write_config16(dev, PCI_MEMORY_BASE, +- (pci_mem->bus_lower & 0xfff00000) >> 16); ++ ((pci_mem->bus_lower & 0xfff00000) >> 16) & ++ PCI_MEMORY_RANGE_MASK); + + cmdstat |= PCI_COMMAND_MEMORY; + } +@@ -205,7 +210,8 @@ + * I/O space + */ + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, +- (pci_prefetch->bus_lower & 0xfff00000) >> 16); ++ (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & ++ PCI_PREF_RANGE_MASK) | prefechable_64); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) + #ifdef CONFIG_SYS_PCI_64BIT + dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, +@@ -217,8 +223,10 @@ + cmdstat |= PCI_COMMAND_MEMORY; + } else { + /* We don't support prefetchable memory for now, so disable */ +- dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); +- dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); ++ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | ++ prefechable_64); ++ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | ++ prefechable_64); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { + dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); + dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); +@@ -230,8 +238,10 @@ + pciauto_region_align(pci_io, 0x1000); + + dm_pci_write_config8(dev, PCI_IO_BASE, +- (pci_io->bus_lower & 0x0000f000) >> 8); +- dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, ++ (((pci_io->bus_lower & 0x0000f000) >> 8) & ++ PCI_IO_RANGE_MASK) | io_32); ++ if (io_32 == PCI_IO_RANGE_TYPE_32) ++ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, + (pci_io->bus_lower & 0xffff0000) >> 16); + + cmdstat |= PCI_COMMAND_IO; +@@ -261,7 +271,8 @@ + pciauto_region_align(pci_mem, 0x100000); + + dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, +- (pci_mem->bus_lower - 1) >> 16); ++ ((pci_mem->bus_lower - 1) >> 16) & ++ PCI_MEMORY_RANGE_MASK); + } + + if (pci_prefetch) { +@@ -275,7 +286,8 @@ + pciauto_region_align(pci_prefetch, 0x100000); + + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, +- (pci_prefetch->bus_lower - 1) >> 16); ++ (((pci_prefetch->bus_lower - 1) >> 16) & ++ PCI_PREF_RANGE_MASK) | prefechable_64); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) + #ifdef CONFIG_SYS_PCI_64BIT + dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, +@@ -286,12 +298,20 @@ + } + + if (pci_io) { ++ u8 io_32; ++ ++ dm_pci_read_config8(dev, PCI_IO_LIMIT, ++ &io_32); ++ io_32 &= PCI_IO_RANGE_TYPE_MASK; ++ + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + dm_pci_write_config8(dev, PCI_IO_LIMIT, +- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); +- dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, ++ ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & ++ PCI_IO_RANGE_MASK) | io_32); ++ if (io_32 == PCI_IO_RANGE_TYPE_32) ++ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, + ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); + } + } +diff -ruN u-boot-2021.10/drivers/pci/pcie_dw_meson.c u-boot/drivers/pci/pcie_dw_meson.c +--- u-boot-2021.10/drivers/pci/pcie_dw_meson.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pcie_dw_meson.c 2021-11-01 17:10:14.396251860 +0100 +@@ -319,15 +319,9 @@ + + pcie_dw_setup_host(&priv->dw); + +- ret = meson_pcie_link_up(priv, LINK_SPEED_GEN_2); +- if (ret < 0) +- goto err_link_up; ++ meson_pcie_link_up(priv, LINK_SPEED_GEN_2); + + return 0; +-err_link_up: +- clk_disable(&priv->clk_port); +- clk_disable(&priv->clk_general); +- clk_disable(&priv->clk_pclk); + err_deassert_bulk: + reset_assert_bulk(&priv->rsts); + err_power_off_phy: +diff -ruN u-boot-2021.10/drivers/pci/pcie_iproc.c u-boot/drivers/pci/pcie_iproc.c +--- u-boot-2021.10/drivers/pci/pcie_iproc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pcie_iproc.c 2021-11-01 17:10:14.396251860 +0100 +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Copyright (C) 2020 Broadcom ++ * Copyright (C) 2020-2021 Broadcom + * + */ + +@@ -12,6 +12,7 @@ + #include <malloc.h> + #include <asm/io.h> + #include <dm/device_compat.h> ++#include <linux/delay.h> + #include <linux/log2.h> + + #define EP_PERST_SOURCE_SELECT_SHIFT 2 +@@ -884,7 +885,7 @@ + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == PCI_REGION_MEM || + hose->regions[i].flags == PCI_REGION_PREFETCH) { +- debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n", ++ debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n", + i, &hose->regions[i].bus_start, + &hose->regions[i].phys_start, + hose->regions[i].size); +@@ -1049,7 +1050,7 @@ + + while (!pci_get_dma_regions(pcie->dev, ®ions, i)) { + dev_dbg(pcie->dev, +- "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n", ++ "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n", + i, regions.bus_start, regions.phys_start, regions.size); + + /* Each range entry corresponds to an inbound mapping region */ +diff -ruN u-boot-2021.10/drivers/pci/pcie_layerscape_fixup_common.c u-boot/drivers/pci/pcie_layerscape_fixup_common.c +--- u-boot-2021.10/drivers/pci/pcie_layerscape_fixup_common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pcie_layerscape_fixup_common.c 2021-11-01 17:10:14.396251860 +0100 +@@ -12,6 +12,7 @@ + #include <asm/arch/clock.h> + #include <asm/arch/soc.h> + #include <linux/libfdt.h> ++#include <fdt_support.h> + #include "pcie_layerscape_fixup_common.h" + + void ft_pci_setup(void *blob, struct bd_info *bd) +@@ -29,7 +30,7 @@ + } + + #if defined(CONFIG_FSL_LAYERSCAPE) +-int lx2_board_fix_fdt(void *fdt) ++static int lx2_board_fix_fdt(void *fdt) + { + char *reg_name, *old_str, *new_str; + const char *reg_names; +diff -ruN u-boot-2021.10/drivers/pci/pcie_layerscape_rc.c u-boot/drivers/pci/pcie_layerscape_rc.c +--- u-boot-2021.10/drivers/pci/pcie_layerscape_rc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pcie_layerscape_rc.c 2021-11-01 17:10:14.399585012 +0100 +@@ -143,8 +143,8 @@ + return 0; + } + +-int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf, +- uint offset, void **paddress) ++static int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf, ++ uint offset, void **paddress) + { + struct ls_pcie_rc *pcie_rc = dev_get_priv(bus); + struct ls_pcie *pcie = pcie_rc->pcie; +diff -ruN u-boot-2021.10/drivers/pci/pci-uclass.c u-boot/drivers/pci/pci-uclass.c +--- u-boot-2021.10/drivers/pci/pci-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pci/pci-uclass.c 2021-11-01 17:10:14.392918709 +0100 +@@ -304,8 +304,8 @@ + return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32); + } + +-int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, +- enum pci_size_t size) ++static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, ++ enum pci_size_t size) + { + struct udevice *bus; + int ret; +@@ -369,8 +369,8 @@ + return ops->read_config(bus, bdf, offset, valuep, size); + } + +-int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, +- enum pci_size_t size) ++static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, ++ enum pci_size_t size) + { + struct udevice *bus; + int ret; +@@ -856,10 +856,7 @@ + /* Check only the first access, we don't expect problems */ + ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, + PCI_SIZE_16); +- if (ret) +- goto error; +- +- if (vendor == 0xffff || vendor == 0x0000) ++ if (ret || vendor == 0xffff || vendor == 0x0000) + continue; + + pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, +@@ -940,10 +937,6 @@ + } + + return 0; +-error: +- printf("Cannot read bus configuration: %d\n", ret); +- +- return ret; + } + + static void decode_regions(struct pci_controller *hose, ofnode parent_node, +@@ -1433,9 +1426,9 @@ + return phys_addr; + } + +-int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, +- unsigned long flags, unsigned long skip_mask, +- pci_addr_t *ba) ++static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, ++ unsigned long flags, unsigned long skip_mask, ++ pci_addr_t *ba) + { + struct pci_region *res; + struct udevice *ctlr; +diff -ruN u-boot-2021.10/drivers/phy/allwinner/Kconfig u-boot/drivers/phy/allwinner/Kconfig +--- u-boot-2021.10/drivers/phy/allwinner/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/phy/allwinner/Kconfig 2021-11-01 17:10:14.399585012 +0100 +@@ -3,7 +3,8 @@ + # + config PHY_SUN4I_USB + bool "Allwinner Sun4I USB PHY driver" +- depends on ARCH_SUNXI ++ depends on (ARCH_SUNXI || TARGET_SUNXI) ++ select DM_REGULATOR + select PHY + help + Enable this to support the transceiver that is part of Allwinner +@@ -12,6 +13,16 @@ + This driver controls the entire USB PHY block, both the USB OTG + parts, as well as the 2 regular USB 2 host PHYs. + ++config INITIAL_USB_SCAN_DELAY ++ int "delay initial usb scan by x ms to allow builtin devices to init" ++ depends on PHY_SUN4I_USB ++ default 0 ++ ---help--- ++ Some boards have on board usb devices which need longer than the ++ USB spec's 1 second to connect from board powerup. Set this config ++ option to a non 0 value to add an extra delay before the first usb ++ bus scan. ++ + config PHY_SUN50I_USB3 + bool "Allwinner sun50i USB3 PHY driver" + depends on ARCH_SUNXI +diff -ruN u-boot-2021.10/drivers/phy/allwinner/phy-sun4i-usb.c u-boot/drivers/phy/allwinner/phy-sun4i-usb.c +--- u-boot-2021.10/drivers/phy/allwinner/phy-sun4i-usb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/phy/allwinner/phy-sun4i-usb.c 2021-11-01 17:10:14.399585012 +0100 +@@ -20,12 +20,15 @@ + #include <reset.h> + #include <asm/gpio.h> + #include <asm/io.h> ++#if 0 + #include <asm/arch/clock.h> + #include <asm/arch/cpu.h> ++#endif + #include <dm/device_compat.h> + #include <linux/bitops.h> + #include <linux/delay.h> + #include <linux/err.h> ++#include <power/regulator.h> + + #define REG_ISCR 0x00 + #define REG_PHYCTL_A10 0x04 +@@ -33,7 +36,8 @@ + #define REG_PHYTUNE 0x0c + #define REG_PHYCTL_A33 0x10 + #define REG_PHY_OTGCTL 0x20 +-#define REG_PMU_UNK1 0x10 ++ ++#define REG_HCI_PHY_CTL 0x10 + + /* Common Control Bits for Both PHYs */ + #define PHY_PLL_BW 0x03 +@@ -64,6 +68,7 @@ + /* A83T specific control bits for PHY0 */ + #define PHY_CTL_VBUSVLDEXT BIT(5) + #define PHY_CTL_SIDDQ BIT(3) ++#define PHY_CTL_H3_SIDDQ BIT(1) + + /* A83T specific control bits for PHY2 HSIC */ + #define SUNXI_EHCI_HS_FORCE BIT(20) +@@ -88,48 +93,19 @@ + int num_phys; + enum sun4i_usb_phy_type type; + u32 disc_thresh; ++ u32 hci_phy_ctl_clear; + u8 phyctl_offset; + bool dedicated_clocks; +- bool enable_pmu_unk1; + bool phy0_dual_route; + int missing_phys; + }; + +-struct sun4i_usb_phy_info { +- const char *gpio_vbus; +- const char *gpio_vbus_det; +- const char *gpio_id_det; +-} phy_info[] = { +- { +- .gpio_vbus = CONFIG_USB0_VBUS_PIN, +- .gpio_vbus_det = CONFIG_USB0_VBUS_DET, +- .gpio_id_det = CONFIG_USB0_ID_DET, +- }, +- { +- .gpio_vbus = CONFIG_USB1_VBUS_PIN, +- .gpio_vbus_det = NULL, +- .gpio_id_det = NULL, +- }, +- { +- .gpio_vbus = CONFIG_USB2_VBUS_PIN, +- .gpio_vbus_det = NULL, +- .gpio_id_det = NULL, +- }, +- { +- .gpio_vbus = CONFIG_USB3_VBUS_PIN, +- .gpio_vbus_det = NULL, +- .gpio_id_det = NULL, +- }, +-}; +- + struct sun4i_usb_phy_plat { + void __iomem *pmu; + int power_on_count; +- int gpio_vbus; +- int gpio_vbus_det; +- int gpio_id_det; + struct clk clocks; + struct reset_ctl resets; ++ struct udevice *vbus; + int id; + }; + +@@ -137,6 +113,9 @@ + void __iomem *base; + const struct sun4i_usb_phy_cfg *cfg; + struct sun4i_usb_phy_plat *usb_phy; ++ struct gpio_desc id_det_gpio; ++ struct gpio_desc vbus_det_gpio; ++ struct udevice *vbus_power_supply; + }; + + static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY; +@@ -227,8 +206,8 @@ + if (usb_phy->power_on_count != 1) + return 0; + +- if (usb_phy->gpio_vbus >= 0) +- gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP); ++ if (usb_phy->vbus) ++ return regulator_set_enable(usb_phy->vbus, true); + + return 0; + } +@@ -242,8 +221,8 @@ + if (usb_phy->power_on_count != 0) + return 0; + +- if (usb_phy->gpio_vbus >= 0) +- gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE); ++ if (usb_phy->vbus) ++ return regulator_set_enable(usb_phy->vbus, false); + + return 0; + } +@@ -284,6 +263,12 @@ + return ret; + } + ++ if (usb_phy->pmu && data->cfg->hci_phy_ctl_clear) { ++ val = readl(usb_phy->pmu + REG_HCI_PHY_CTL); ++ val &= ~data->cfg->hci_phy_ctl_clear; ++ writel(val, usb_phy->pmu + REG_HCI_PHY_CTL); ++ } ++ + if (data->cfg->type == sun8i_a83t_phy || + data->cfg->type == sun50i_h6_phy) { + if (phy->id == 0) { +@@ -293,11 +278,6 @@ + writel(val, data->base + data->cfg->phyctl_offset); + } + } else { +- if (usb_phy->pmu && data->cfg->enable_pmu_unk1) { +- val = readl(usb_phy->pmu + REG_PMU_UNK1); +- writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1); +- } +- + if (usb_phy->id == 0) + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, + PHY_RES45_CAL_DATA, +@@ -390,23 +370,21 @@ + int sun4i_usb_phy_vbus_detect(struct phy *phy) + { + struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); +- struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; +- int err, retries = 3; ++ int err = 1, retries = 3; + +- debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det); +- +- if (usb_phy->gpio_vbus_det < 0) +- return usb_phy->gpio_vbus_det; +- +- err = gpio_get_value(usb_phy->gpio_vbus_det); +- /* +- * Vbus may have been provided by the board and just been turned of +- * some milliseconds ago on reset, what we're measuring then is a +- * residual charge on Vbus, sleep a bit and try again. +- */ +- while (err > 0 && retries--) { +- mdelay(100); +- err = gpio_get_value(usb_phy->gpio_vbus_det); ++ if (dm_gpio_is_valid(&data->vbus_det_gpio)) { ++ err = dm_gpio_get_value(&data->vbus_det_gpio); ++ /* ++ * Vbus may have been provided by the board and just turned off ++ * some milliseconds ago on reset. What we're measuring then is ++ * a residual charge on Vbus. Sleep a bit and try again. ++ */ ++ while (err > 0 && retries--) { ++ mdelay(100); ++ err = dm_gpio_get_value(&data->vbus_det_gpio); ++ } ++ } else if (data->vbus_power_supply) { ++ err = regulator_get_enable(data->vbus_power_supply); + } + + return err; +@@ -415,14 +393,11 @@ + int sun4i_usb_phy_id_detect(struct phy *phy) + { + struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); +- struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + +- debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det); ++ if (!dm_gpio_is_valid(&data->id_det_gpio)) ++ return -EOPNOTSUPP; + +- if (usb_phy->gpio_id_det < 0) +- return usb_phy->gpio_id_det; +- +- return gpio_get_value(usb_phy->gpio_id_det); ++ return dm_gpio_get_value(&data->id_det_gpio); + } + + void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled) +@@ -452,44 +427,30 @@ + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + ++ gpio_request_by_name(dev, "usb0_id_det-gpios", 0, &data->id_det_gpio, ++ GPIOD_IS_IN | GPIOD_PULL_UP); ++ ++ gpio_request_by_name(dev, "usb0_vbus_det-gpios", 0, &data->vbus_det_gpio, ++ GPIOD_IS_IN); ++ ++ device_get_supply_regulator(dev, "usb0_vbus_power-supply", ++ &data->vbus_power_supply); ++ + data->usb_phy = plat; + for (i = 0; i < data->cfg->num_phys; i++) { + struct sun4i_usb_phy_plat *phy = &plat[i]; +- struct sun4i_usb_phy_info *info = &phy_info[i]; +- char name[16]; ++ char name[20]; + + if (data->cfg->missing_phys & BIT(i)) + continue; + +- phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus); +- if (phy->gpio_vbus >= 0) { +- ret = gpio_request(phy->gpio_vbus, "usb_vbus"); +- if (ret) ++ snprintf(name, sizeof(name), "usb%d_vbus-supply", i); ++ ret = device_get_supply_regulator(dev, name, &phy->vbus); ++ if (phy->vbus) { ++ ret = regulator_set_enable(phy->vbus, false); ++ /* Fixed regulators cannot be disabled. */ ++ if (ret && ret != -ENOSYS) + return ret; +- ret = gpio_direction_output(phy->gpio_vbus, 0); +- if (ret) +- return ret; +- } +- +- phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det); +- if (phy->gpio_vbus_det >= 0) { +- ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det"); +- if (ret) +- return ret; +- ret = gpio_direction_input(phy->gpio_vbus_det); +- if (ret) +- return ret; +- } +- +- phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det); +- if (phy->gpio_id_det >= 0) { +- ret = gpio_request(phy->gpio_id_det, "usb_id_det"); +- if (ret) +- return ret; +- ret = gpio_direction_input(phy->gpio_id_det); +- if (ret) +- return ret; +- sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP); + } + + if (data->cfg->dedicated_clocks) +@@ -530,7 +491,6 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { +@@ -539,7 +499,6 @@ + .disc_thresh = 2, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { +@@ -548,7 +507,6 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = true, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { +@@ -557,7 +515,6 @@ + .disc_thresh = 2, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { +@@ -566,7 +523,6 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = true, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { +@@ -575,7 +531,6 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = false, + }; + + static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { +@@ -591,7 +546,7 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = true, ++ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, + .phy0_dual_route = true, + }; + +@@ -601,7 +556,7 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = true, ++ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, + .phy0_dual_route = true, + }; + +@@ -611,7 +566,16 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = true, ++ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, ++ .phy0_dual_route = true, ++}; ++ ++static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = { ++ .num_phys = 2, ++ .type = sun50i_h6_phy, ++ .phyctl_offset = REG_PHYCTL_A33, ++ .dedicated_clocks = true, ++ .hci_phy_ctl_clear = PHY_CTL_SIDDQ, + .phy0_dual_route = true, + }; + +@@ -621,7 +585,7 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = true, ++ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, + .phy0_dual_route = true, + }; + +@@ -631,7 +595,6 @@ + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +- .enable_pmu_unk1 = true, + .phy0_dual_route = true, + .missing_phys = BIT(1) | BIT(2), + }; +@@ -647,8 +610,9 @@ + { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg }, + { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg }, + { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg }, +- { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg}, +- { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg}, ++ { .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg }, ++ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg }, ++ { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg }, + { } + }; + +diff -ruN u-boot-2021.10/drivers/phy/marvell/comphy_core.h u-boot/drivers/phy/marvell/comphy_core.h +--- u-boot-2021.10/drivers/phy/marvell/comphy_core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/phy/marvell/comphy_core.h 2021-11-01 17:10:14.399585012 +0100 +@@ -141,4 +141,3 @@ + void comphy_pcie_unit_general_config(u32 pex_index); + + #endif /* _COMPHY_CORE_H_ */ +- +diff -ruN u-boot-2021.10/drivers/phy/marvell/Kconfig u-boot/drivers/phy/marvell/Kconfig +--- u-boot-2021.10/drivers/phy/marvell/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/phy/marvell/Kconfig 2021-11-01 17:10:14.399585012 +0100 +@@ -1,6 +1,5 @@ + config MVEBU_COMPHY_SUPPORT + bool "ComPhy SerDes driver" +- default n + help + Choose this option to add support + for Comphy driver. +diff -ruN u-boot-2021.10/drivers/phy/marvell/utmi_phy.h u-boot/drivers/phy/marvell/utmi_phy.h +--- u-boot-2021.10/drivers/phy/marvell/utmi_phy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/phy/marvell/utmi_phy.h 2021-11-01 17:10:14.402918162 +0100 +@@ -98,4 +98,3 @@ + (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET) + + #endif /* _UTMI_PHY_H_ */ +- +diff -ruN u-boot-2021.10/drivers/pinctrl/intel/pinctrl_apl.c u-boot/drivers/pinctrl/intel/pinctrl_apl.c +--- u-boot-2021.10/drivers/pinctrl/intel/pinctrl_apl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/intel/pinctrl_apl.c 2021-11-01 17:10:14.406251313 +0100 +@@ -155,7 +155,7 @@ + return intel_pinctrl_of_to_plat(dev, comm, 2); + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id apl_gpio_ids[] = { + { .compatible = "intel,apl-pinctrl"}, + { } +@@ -168,7 +168,7 @@ + .of_match = of_match_ptr(apl_gpio_ids), + .probe = intel_pinctrl_probe, + .ops = &intel_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .of_to_plat = apl_pinctrl_of_to_plat, +diff -ruN u-boot-2021.10/drivers/pinctrl/Kconfig u-boot/drivers/pinctrl/Kconfig +--- u-boot-2021.10/drivers/pinctrl/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/Kconfig 2021-11-01 17:10:14.402918162 +0100 +@@ -312,6 +312,7 @@ + source "drivers/pinctrl/nxp/Kconfig" + source "drivers/pinctrl/renesas/Kconfig" + source "drivers/pinctrl/rockchip/Kconfig" ++source "drivers/pinctrl/sunxi/Kconfig" + source "drivers/pinctrl/uniphier/Kconfig" + + endmenu +diff -ruN u-boot-2021.10/drivers/pinctrl/Makefile u-boot/drivers/pinctrl/Makefile +--- u-boot-2021.10/drivers/pinctrl/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/Makefile 2021-11-01 17:10:14.402918162 +0100 +@@ -13,7 +13,7 @@ + obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ + obj-$(CONFIG_ARCH_RMOBILE) += renesas/ + obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o +- ++obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ + obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ + obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o + obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ +diff -ruN u-boot-2021.10/drivers/pinctrl/mediatek/pinctrl-mt7622.c u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c +--- u-boot-2021.10/drivers/pinctrl/mediatek/pinctrl-mt7622.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/mediatek/pinctrl-mt7622.c 2021-11-01 17:10:14.406251313 +0100 +@@ -750,5 +750,3 @@ + .probe = mtk_pinctrl_mt7622_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), + }; +- +- +diff -ruN u-boot-2021.10/drivers/pinctrl/meson/pinctrl-meson-axg.c u-boot/drivers/pinctrl/meson/pinctrl-meson-axg.c +--- u-boot-2021.10/drivers/pinctrl/meson/pinctrl-meson-axg.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/meson/pinctrl-meson-axg.c 2021-11-01 17:10:14.406251313 +0100 +@@ -908,7 +908,7 @@ + }; + + static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { +- /* name first last reg offset */ ++ /* name first last reg offset */ + BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 0x2, 0), + BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 0x0, 0), + BANK_PMX("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0xb, 0), +diff -ruN u-boot-2021.10/drivers/pinctrl/meson/pinctrl-meson-g12a.c u-boot/drivers/pinctrl/meson/pinctrl-meson-g12a.c +--- u-boot-2021.10/drivers/pinctrl/meson/pinctrl-meson-g12a.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/meson/pinctrl-meson-g12a.c 2021-11-01 17:10:14.406251313 +0100 +@@ -1220,7 +1220,7 @@ + }; + + static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { +- /* name first last reg offset */ ++ /* name first last reg offset */ + BANK_PMX("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 0x6, 0), + BANK_PMX("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 0xb, 0), + BANK_PMX("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0x0, 0), +diff -ruN u-boot-2021.10/drivers/pinctrl/nxp/pinctrl-mxs.c u-boot/drivers/pinctrl/nxp/pinctrl-mxs.c +--- u-boot-2021.10/drivers/pinctrl/nxp/pinctrl-mxs.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/nxp/pinctrl-mxs.c 2021-11-01 17:10:14.409584464 +0100 +@@ -186,7 +186,7 @@ + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(mxs_pinctrl_match), + .probe = mxs_pinctrl_probe, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .priv_auto = sizeof(struct mxs_pinctrl_priv), +diff -ruN u-boot-2021.10/drivers/pinctrl/pinctrl-qe-io.c u-boot/drivers/pinctrl/pinctrl-qe-io.c +--- u-boot-2021.10/drivers/pinctrl/pinctrl-qe-io.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/pinctrl-qe-io.c 2021-11-01 17:10:14.409584464 +0100 +@@ -248,7 +248,7 @@ + .of_to_plat = qe_io_of_to_plat, + .plat_auto = sizeof(struct qe_io_plat), + .ops = &par_io_pinctrl_ops, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .flags = DM_FLAG_PRE_RELOC, + #endif + }; +diff -ruN u-boot-2021.10/drivers/pinctrl/pinctrl-single.c u-boot/drivers/pinctrl/pinctrl-single.c +--- u-boot-2021.10/drivers/pinctrl/pinctrl-single.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/pinctrl-single.c 2021-11-01 17:10:14.409584464 +0100 +@@ -8,6 +8,7 @@ + #include <dm.h> + #include <dm/device_compat.h> + #include <dm/devres.h> ++#include <dm/of_access.h> + #include <dm/pinctrl.h> + #include <linux/libfdt.h> + #include <linux/list.h> +@@ -45,10 +46,26 @@ + }; + + /** ++ * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun ++ * @offset: offset base of pins ++ * @npins: number pins with the same mux value of gpio function ++ * @gpiofunc: mux value of gpio function ++ * @node: list node ++ */ ++struct single_gpiofunc_range { ++ u32 offset; ++ u32 npins; ++ u32 gpiofunc; ++ struct list_head node; ++}; ++ ++/** + * struct single_priv - private data + * @bits_per_pin: number of bits per pin + * @npins: number of selectable pins + * @pin_name: temporary buffer to store the pin name ++ * @functions: list pin functions ++ * @gpiofuncs: list gpio functions + */ + struct single_priv { + #if (IS_ENABLED(CONFIG_SANDBOX)) +@@ -58,6 +75,7 @@ + unsigned int npins; + char pin_name[PINNAME_SIZE]; + struct list_head functions; ++ struct list_head gpiofuncs; + }; + + /** +@@ -232,6 +250,39 @@ + return 0; + } + ++static int single_request(struct udevice *dev, int pin, int flags) ++{ ++ struct single_priv *priv = dev_get_priv(dev); ++ struct single_pdata *pdata = dev_get_plat(dev); ++ struct single_gpiofunc_range *frange = NULL; ++ struct list_head *pos, *tmp; ++ phys_addr_t reg; ++ int mux_bytes = 0; ++ u32 data; ++ ++ /* If function mask is null, needn't enable it. */ ++ if (!pdata->mask) ++ return -ENOTSUPP; ++ ++ list_for_each_safe(pos, tmp, &priv->gpiofuncs) { ++ frange = list_entry(pos, struct single_gpiofunc_range, node); ++ if ((pin >= frange->offset + frange->npins) || ++ pin < frange->offset) ++ continue; ++ ++ mux_bytes = pdata->width / BITS_PER_BYTE; ++ reg = pdata->base + pin * mux_bytes; ++ ++ data = single_read(dev, reg); ++ data &= ~pdata->mask; ++ data |= frange->gpiofunc; ++ single_write(dev, data, reg); ++ break; ++ } ++ ++ return 0; ++} ++ + static struct single_func *single_allocate_function(struct udevice *dev, + unsigned int group_pins) + { +@@ -454,6 +505,36 @@ + return priv->npins; + } + ++static int single_add_gpio_func(struct udevice *dev) ++{ ++ struct single_priv *priv = dev_get_priv(dev); ++ const char *propname = "pinctrl-single,gpio-range"; ++ const char *cellname = "#pinctrl-single,gpio-range-cells"; ++ struct single_gpiofunc_range *range; ++ struct ofnode_phandle_args gpiospec; ++ int ret, i; ++ ++ for (i = 0; ; i++) { ++ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), propname, ++ cellname, 0, i, &gpiospec); ++ /* Do not treat it as error. Only treat it as end condition. */ ++ if (ret) { ++ ret = 0; ++ break; ++ } ++ range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); ++ if (!range) { ++ ret = -ENOMEM; ++ break; ++ } ++ range->offset = gpiospec.args[0]; ++ range->npins = gpiospec.args[1]; ++ range->gpiofunc = gpiospec.args[2]; ++ list_add_tail(&range->node, &priv->gpiofuncs); ++ } ++ return ret; ++} ++ + static int single_probe(struct udevice *dev) + { + struct single_pdata *pdata = dev_get_plat(dev); +@@ -461,6 +542,7 @@ + u32 size; + + INIT_LIST_HEAD(&priv->functions); ++ INIT_LIST_HEAD(&priv->gpiofuncs); + + size = pdata->offset + pdata->width / BITS_PER_BYTE; + #if (CONFIG_IS_ENABLED(SANDBOX)) +@@ -483,6 +565,9 @@ + priv->npins *= (pdata->width / priv->bits_per_pin); + } + ++ if (single_add_gpio_func(dev)) ++ dev_dbg(dev, "gpio functions are not added\n"); ++ + dev_dbg(dev, "%d pins\n", priv->npins); + return 0; + } +@@ -535,6 +620,7 @@ + .get_pin_name = single_get_pin_name, + .set_state = single_set_state, + .get_pin_muxing = single_get_pin_muxing, ++ .request = single_request, + }; + + static const struct udevice_id single_pinctrl_match[] = { +diff -ruN u-boot-2021.10/drivers/pinctrl/pinctrl-uclass.c u-boot/drivers/pinctrl/pinctrl-uclass.c +--- u-boot-2021.10/drivers/pinctrl/pinctrl-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/pinctrl-uclass.c 2021-11-01 17:10:14.412917616 +0100 +@@ -421,7 +421,7 @@ + + UCLASS_DRIVER(pinctrl) = { + .id = UCLASS_PINCTRL, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = pinctrl_post_bind, + #endif + .flags = DM_UC_FLAG_SEQ_ALIAS, +diff -ruN u-boot-2021.10/drivers/pinctrl/renesas/pfc-r8a77970.c u-boot/drivers/pinctrl/renesas/pfc-r8a77970.c +--- u-boot-2021.10/drivers/pinctrl/renesas/pfc-r8a77970.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/renesas/pfc-r8a77970.c 2021-11-01 17:10:14.419583917 +0100 +@@ -161,7 +161,7 @@ + #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +diff -ruN u-boot-2021.10/drivers/pinctrl/renesas/pfc-r8a77980.c u-boot/drivers/pinctrl/renesas/pfc-r8a77980.c +--- u-boot-2021.10/drivers/pinctrl/renesas/pfc-r8a77980.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/renesas/pfc-r8a77980.c 2021-11-01 17:10:14.419583917 +0100 +@@ -88,7 +88,7 @@ + #define GPSR1_0 F_(IRQ0, IP2_27_24) + + /* GPSR2 */ +-#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) ++#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) + #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) + #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) + #define GPSR2_26 F_(SDA3, IP10_7_4) +@@ -253,11 +253,11 @@ + #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-px30.c u-boot/drivers/pinctrl/rockchip/pinctrl-px30.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-px30.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-px30.c 2021-11-01 17:10:14.419583917 +0100 +@@ -363,7 +363,7 @@ + .of_match = px30_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3036.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3036.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3036.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3036.c 2021-11-01 17:10:14.419583917 +0100 +@@ -103,7 +103,7 @@ + .of_match = rk3036_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3128.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3128.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3128.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3128.c 2021-11-01 17:10:14.419583917 +0100 +@@ -205,7 +205,7 @@ + .of_match = rk3128_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3188.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3188.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3188.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3188.c 2021-11-01 17:10:14.419583917 +0100 +@@ -126,7 +126,7 @@ + .of_match = rk3188_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk322x.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk322x.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk322x.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk322x.c 2021-11-01 17:10:14.419583917 +0100 +@@ -292,7 +292,7 @@ + .of_match = rk3228_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3288.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3288.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3288.c 2021-11-01 17:10:14.419583917 +0100 +@@ -248,7 +248,7 @@ + .of_match = rk3288_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3308.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3308.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3308.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3308.c 2021-11-01 17:10:14.419583917 +0100 +@@ -459,7 +459,7 @@ + .of_match = rk3308_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3328.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3328.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c 2021-11-01 17:10:14.419583917 +0100 +@@ -323,7 +323,7 @@ + .of_match = rk3328_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3368.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3368.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3368.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3368.c 2021-11-01 17:10:14.419583917 +0100 +@@ -177,7 +177,7 @@ + .of_match = rk3368_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3399.c u-boot/drivers/pinctrl/rockchip/pinctrl-rk3399.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rk3399.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rk3399.c 2021-11-01 17:10:14.419583917 +0100 +@@ -317,7 +317,7 @@ + .of_match = rk3399_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rv1108.c u-boot/drivers/pinctrl/rockchip/pinctrl-rv1108.c +--- u-boot-2021.10/drivers/pinctrl/rockchip/pinctrl-rv1108.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pinctrl/rockchip/pinctrl-rv1108.c 2021-11-01 17:10:14.422917069 +0100 +@@ -291,7 +291,7 @@ + .of_match = rv1108_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, + #endif + .probe = rockchip_pinctrl_probe, +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/Kconfig u-boot/drivers/pinctrl/sunxi/Kconfig +--- u-boot-2021.10/drivers/pinctrl/sunxi/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/Kconfig 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,121 @@ ++if ARCH_SUNXI || TARGET_SUNXI ++ ++config PINCTRL_SUNXI ++ bool ++ ++config PINCTRL_SUN4I_A10 ++ bool "Support for the Allwinner A10 PIO" ++ default MACH_SUN4I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN5I_A13 ++ bool "Support for the Allwinner A10s/A13 PIO" ++ default MACH_SUN5I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN6I_A31 ++ bool "Support for the Allwinner A31 PIO" ++ default MACH_SUN6I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN6I_A31_R ++ bool "Support for the Allwinner A31 R-PIO" ++ default MACH_SUN6I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN7I_A20 ++ bool "Support for the Allwinner A20/R40 PIO" ++ default MACH_SUN7I || MACH_SUN8I_R40 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_A23 ++ bool "Support for the Allwinner A23 PIO" ++ default MACH_SUN8I_A23 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_A23_R ++ bool "Support for the Allwinner A23/A33 R-PIO" ++ default MACH_SUN8I_A23 || MACH_SUN8I_A33 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_A33 ++ bool "Support for the Allwinner A33 PIO" ++ default MACH_SUN8I_A33 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_A83T ++ bool "Support for the Allwinner A83T PIO" ++ default MACH_SUN8I_A83T ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_A83T_R ++ bool "Support for the Allwinner A83T R-PIO" ++ default MACH_SUN8I_A83T ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_H3 ++ bool "Support for the Allwinner H3 PIO" ++ default MACH_SUN8I_H3 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_H3_R ++ bool "Support for the Allwinner H3/H5 R-PIO" ++ default MACH_SUN8I_H3 || MACH_SUN50I_H5 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN8I_V3S ++ bool "Support for the Allwinner V3s PIO" ++ default MACH_SUN8I_V3S ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN9I_A80 ++ bool "Support for the Allwinner A80 PIO" ++ default MACH_SUN9I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN9I_A80_R ++ bool "Support for the Allwinner A80 R-PIO" ++ default MACH_SUN9I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN20I_D1 ++ bool "Support for the Allwinner D1 PIO" ++ default MACH_SUN20I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_A64 ++ bool "Support for the Allwinner A64 PIO" ++ default MACH_SUN50I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_A64_R ++ bool "Support for the Allwinner A64 R-PIO" ++ default MACH_SUN50I ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_H5 ++ bool "Support for the Allwinner H5 PIO" ++ default MACH_SUN50I_H5 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_H6 ++ bool "Support for the Allwinner H6 PIO" ++ default MACH_SUN50I_H6 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_H6_R ++ bool "Support for the Allwinner H6 R-PIO" ++ default MACH_SUN50I_H6 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_H616 ++ bool "Support for the Allwinner H616 PIO" ++ default MACH_SUN50I_H616 ++ select PINCTRL_SUNXI ++ ++config PINCTRL_SUN50I_H616_R ++ bool "Support for the Allwinner H616 R-PIO" ++ default MACH_SUN50I_H616 ++ select PINCTRL_SUNXI ++ ++endif +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/Makefile u-boot/drivers/pinctrl/sunxi/Makefile +--- u-boot-2021.10/drivers/pinctrl/sunxi/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/Makefile 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,27 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj-y += pinctrl-sunxi.o ++ ++obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o ++obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o ++obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o ++obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o ++obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o ++obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o ++obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o ++obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o ++obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o ++obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o ++obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o ++obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o ++obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o ++obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o ++obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o ++obj-$(CONFIG_PINCTRL_SUN20I_D1) += pinctrl-sun20i-d1.o ++obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o ++obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o ++obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o ++obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o ++obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o ++obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o ++obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = { ++ { "emac", 8 }, /* PE0-PE15 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 4 }, /* PB10-PB11 */ ++ { "i2c2", 4 }, /* PB0-PB1 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC2-PC7 */ ++ { "spi0", 2 }, /* PC2-PC7 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 6 }, /* PB8-PB9 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 7 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun20i_d1_pinctrl_desc = { ++ .functions = sun20i_d1_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 7, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = { ++ { "emac", 2 }, /* PA0-PA17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PB0-PB1 */ ++ { "i2c1", 2 }, /* PB18-PB19 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++#if IS_ENABLED(CONFIG_MMC1_PINS_PH) ++ { "mmc1", 5 }, /* PH22-PH27 */ ++#else ++ { "mmc1", 4 }, /* PG0-PG5 */ ++#endif ++ { "mmc2", 3 }, /* PC6-PC15 */ ++ { "mmc3", 2 }, /* PI4-PI9 */ ++ { "spi0", 3 }, /* PC0-PC2, PC23 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 4 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PB22-PB23 */ ++#endif ++}; ++ ++const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_desc = { ++ .functions = sun4i_a10_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun4i_a10_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 9, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = { ++ { "emac", 4 }, /* PD8-PD23 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH0-PH1 */ ++ { "i2c1", 2 }, /* PH2-PH3 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC1-PC16 */ ++ { "pwm", 2 }, /* PD22 */ ++ { "spi0", 4 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 4 }, /* PB8-PB9 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_a64_pinctrl_desc = { ++ .functions = sun50i_a64_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_a64_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 2 }, /* PL8-PL9 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_desc = { ++ .functions = sun50i_a64_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_a64_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 1, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = { ++ { "emac", 2 }, /* PD0-PD17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PA11-PA12 */ ++ { "i2c1", 2 }, /* PA18-PA19 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC1-PC16 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PA4-PA5 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PA0-PA1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_desc = { ++ .functions = sun50i_h5_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_h5_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 7, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,26 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = { ++ { "emac0", 2 }, /* PI0-PI16 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC0-PC16 */ ++ { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PH0-PH1 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_h616_pinctrl_desc = { ++ .functions = sun50i_h616_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_h616_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 9, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 3 }, /* PL0-PL1 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_desc = { ++ .functions = sun50i_h616_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_h616_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 1, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = { ++ { "emac", 5 }, /* PD0-PD20 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PD25-PD26 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC1-PC14 */ ++ { "spi0", 4 }, /* PC0-PC7 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PH0-PH1 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_h6_pinctrl_desc = { ++ .functions = sun50i_h6_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_h6_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 3 }, /* PL0-PL1 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_desc = { ++ .functions = sun50i_h6_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun50i_h6_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 2, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,28 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = { ++ { "emac", 2 }, /* PA0-PA17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PB0-PB1 */ ++ { "i2c1", 2 }, /* PB15-PB16 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG3-PG8 */ ++ { "mmc2", 3 }, /* PC6-PC15 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 4 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PB19-PB20 */ ++#endif ++ { "uart1", 4 }, /* PG3-PG4 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_desc = { ++ .functions = sun5i_a13_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun5i_a13_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 7, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,28 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = { ++ { "gmac", 2 }, /* PA0-PA27 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH14-PH15 */ ++ { "i2c1", 2 }, /* PH16-PH17 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC6-PC15, PC24 */ ++ { "mmc3", 4 }, /* PC6-PC15, PC24 */ ++ { "spi0", 3 }, /* PC0-PC2, PC27 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PH20-PH21 */ ++#endif ++}; ++ ++const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_desc = { ++ .functions = sun6i_a31_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun6i_a31_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 2 }, /* PL0-PL1 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_desc = { ++ .functions = sun6i_a31_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun6i_a31_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 2, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = { ++ { "emac", 2 }, /* PA0-PA17 */ ++ { "gmac", 5 }, /* PA0-PA17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PB0-PB1 */ ++ { "i2c1", 2 }, /* PB18-PB19 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++#if IS_ENABLED(CONFIG_MMC1_PINS_PH) ++ { "mmc1", 5 }, /* PH22-PH27 */ ++#else ++ { "mmc1", 4 }, /* PG0-PG5 */ ++#endif ++ { "mmc2", 3 }, /* PC5-PC15, PC24 */ ++ { "spi0", 3 }, /* PC0-PC2, PC23 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 4 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PB22-PB23 */ ++#endif ++}; ++ ++const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_desc = { ++ .functions = sun7i_a20_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun7i_a20_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 9, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,26 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH2-PH3 */ ++ { "i2c1", 2 }, /* PH4-PH5 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC5-PC16 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_desc = { ++ .functions = sun8i_a23_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_a23_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 3 }, /* PL0-PL1 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_desc = { ++ .functions = sun8i_a23_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_a23_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 1, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,28 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH2-PH3 */ ++ { "i2c1", 2 }, /* PH4-PH5 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC5-PC16 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 3 }, /* PB0-PB1 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_desc = { ++ .functions = sun8i_a33_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_a33_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = { ++ { "gmac", 4 }, /* PD2-PD23 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH0-PH1 */ ++ { "i2c1", 2 }, /* PH2-PH3 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC5-PC16 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PB9-PB10 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_desc = { ++ .functions = sun8i_a83t_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_a83t_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 2 }, /* PL8-PL9 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_desc = { ++ .functions = sun8i_a83t_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_a83t_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 1, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = { ++ { "emac", 2 }, /* PD0-PD17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PA11-PA12 */ ++ { "i2c1", 3 }, /* PA18-PA19 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC5-PC16 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PA4-PA5 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PA0-PA1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_desc = { ++ .functions = sun8i_h3_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_h3_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 7, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c", 2 }, /* PL0-PL1 */ ++ { "s_uart", 2 }, /* PL2-PL3 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_desc = { ++ .functions = sun8i_h3_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_h3_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 1, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = { ++ { "emac", 4 }, /* PD0-PD17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PB6-PB7 */ ++ { "i2c1", 2 }, /* PB8-PB9 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 2 }, /* PC0-PC10 */ ++ { "spi0", 3 }, /* PC0-PC3 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 3 }, /* PF2-PF4 */ ++#else ++ { "uart0", 3 }, /* PB8-PB9 */ ++#endif ++ { "uart1", 2 }, /* PG6-PG7 */ ++ { "uart2", 2 }, /* PB0-PB1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_desc = { ++ .functions = sun8i_v3s_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun8i_v3s_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 7, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = { ++ { "gmac", 2 }, /* PA0-PA17 */ ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "i2c0", 2 }, /* PH0-PH1 */ ++ { "i2c1", 2 }, /* PH2-PH3 */ ++ { "mmc0", 2 }, /* PF0-PF5 */ ++ { "mmc1", 2 }, /* PG0-PG5 */ ++ { "mmc2", 3 }, /* PC6-PC16 */ ++ { "spi0", 3 }, /* PC0-PC2, PC19 */ ++#if IS_ENABLED(CONFIG_UART0_PORT_F) ++ { "uart0", 4 }, /* PF2-PF4 */ ++#else ++ { "uart0", 2 }, /* PH12-PH13 */ ++#endif ++}; ++ ++const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_desc = { ++ .functions = sun9i_a80_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun9i_a80_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_A, ++ .num_banks = 8, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c u-boot/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "pinctrl-sunxi.h" ++ ++static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = { ++ { "gpio_in", 0 }, ++ { "gpio_out", 1 }, ++ { "s_i2c0", 2 }, /* PN0-PN1 */ ++ { "s_i2c1", 3 }, /* PM8-PM9 */ ++ { "s_uart", 3 }, /* PL0-PL1 */ ++}; ++ ++const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_desc = { ++ .functions = sun9i_a80_r_pinctrl_functions, ++ .num_functions = ARRAY_SIZE(sun9i_a80_r_pinctrl_functions), ++ .first_bank = SUNXI_GPIO_L, ++ .num_banks = 3, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sunxi.c u-boot/drivers/pinctrl/sunxi/pinctrl-sunxi.c +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sunxi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sunxi.c 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,368 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include <dm.h> ++#include <dm/device-internal.h> ++#include <dm/lists.h> ++#include <dm/pinctrl.h> ++#include <malloc.h> ++ ++#include "pinctrl-sunxi.h" ++ ++extern U_BOOT_DRIVER(gpio_sunxi); ++ ++struct sunxi_pinctrl_plat { ++ struct sunxi_gpio __iomem *base; ++}; ++ ++static int sunxi_pinctrl_get_pins_count(struct udevice *dev) ++{ ++ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev); ++ ++ return desc->num_banks * SUNXI_GPIOS_PER_BANK; ++} ++ ++static const char *sunxi_pinctrl_get_pin_name(struct udevice *dev, ++ unsigned pin_selector) ++{ ++ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev); ++ static char pin_name[5]; ++ ++ snprintf(pin_name, sizeof(pin_name), "P%c%d", ++ pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A', ++ pin_selector % SUNXI_GPIOS_PER_BANK); ++ ++ return pin_name; ++} ++ ++static int sunxi_pinctrl_get_functions_count(struct udevice *dev) ++{ ++ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev); ++ ++ return desc->num_functions; ++} ++ ++static const char *sunxi_pinctrl_get_function_name(struct udevice *dev, ++ unsigned func_selector) ++{ ++ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev); ++ ++ return desc->functions[func_selector].name; ++} ++ ++static int sunxi_pinctrl_pinmux_set(struct udevice *dev, unsigned pin_selector, ++ unsigned func_selector) ++{ ++ const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev); ++ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); ++ int bank = pin_selector / SUNXI_GPIOS_PER_BANK; ++ int pin = pin_selector % SUNXI_GPIOS_PER_BANK; ++ ++ debug("set mux: %-4s => %s (%d)\n", ++ sunxi_pinctrl_get_pin_name(dev, pin_selector), ++ sunxi_pinctrl_get_function_name(dev, func_selector), ++ desc->functions[func_selector].mux); ++ ++ sunxi_gpio_set_cfgbank(plat->base + bank, pin, ++ desc->functions[func_selector].mux); ++ ++ return 0; ++} ++ ++static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = { ++ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, ++ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 2 }, ++ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, ++ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 10 }, ++}; ++ ++static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat, ++ unsigned bank, unsigned pin, ++ unsigned bias) ++{ ++ struct sunxi_gpio *regs = &plat->base[bank]; ++ ++ sunxi_gpio_set_pull_bank(regs, pin, bias); ++ ++ return 0; ++} ++ ++static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat, ++ unsigned bank, unsigned pin, ++ unsigned drive) ++{ ++ struct sunxi_gpio *regs = &plat->base[bank]; ++ ++ if (drive < 10 || drive > 40) ++ return -EINVAL; ++ ++ /* Convert mA to the register value, rounding down. */ ++ sunxi_gpio_set_drv_bank(regs, pin, drive / 10 - 1); ++ ++ return 0; ++} ++ ++static int sunxi_pinctrl_pinconf_set(struct udevice *dev, unsigned pin_selector, ++ unsigned param, unsigned val) ++{ ++ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); ++ int bank = pin_selector / SUNXI_GPIOS_PER_BANK; ++ int pin = pin_selector % SUNXI_GPIOS_PER_BANK; ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ case PIN_CONFIG_BIAS_PULL_UP: ++ return sunxi_pinctrl_pinconf_set_pull(plat, bank, pin, val); ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ return sunxi_pinctrl_pinconf_set_drive(plat, bank, pin, val); ++ } ++ ++ return -EINVAL; ++} ++ ++static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, ++ unsigned pin_selector, ++ char *buf, int size) ++{ ++ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); ++ int bank = pin_selector / SUNXI_GPIOS_PER_BANK; ++ int pin = pin_selector % SUNXI_GPIOS_PER_BANK; ++ int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin); ++ ++ switch (mux) { ++ case SUNXI_GPIO_INPUT: ++ strlcpy(buf, "gpio in", size); ++ break; ++ case SUNXI_GPIO_OUTPUT: ++ strlcpy(buf, "gpio out", size); ++ break; ++ case SUNXI_GPIO_DISABLE: ++ strlcpy(buf, "disabled", size); ++ break; ++ default: ++ snprintf(buf, size, "function %d", mux); ++ break; ++ } ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops sunxi_pinctrl_ops = { ++ .get_pins_count = sunxi_pinctrl_get_pins_count, ++ .get_pin_name = sunxi_pinctrl_get_pin_name, ++ .get_functions_count = sunxi_pinctrl_get_functions_count, ++ .get_function_name = sunxi_pinctrl_get_function_name, ++ .pinmux_set = sunxi_pinctrl_pinmux_set, ++ .pinconf_num_params = ARRAY_SIZE(sunxi_pinctrl_pinconf_params), ++ .pinconf_params = sunxi_pinctrl_pinconf_params, ++ .pinconf_set = sunxi_pinctrl_pinconf_set, ++ .set_state = pinctrl_generic_set_state, ++ .get_pin_muxing = sunxi_pinctrl_get_pin_muxing, ++}; ++ ++static int sunxi_pinctrl_bind(struct udevice *dev) ++{ ++ struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); ++ struct sunxi_pinctrl_desc *desc; ++ struct sunxi_gpio_plat *gpio_plat; ++ struct udevice *gpio_dev; ++ int i, ret; ++ ++ desc = (void *)dev_get_driver_data(dev); ++ if (!desc) ++ return -EINVAL; ++ dev_set_priv(dev, desc); ++ ++ plat->base = dev_read_addr_ptr(dev); ++ ++ ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name, ++ dev_ofnode(dev), &gpio_dev); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < desc->num_banks; ++i) { ++ gpio_plat = malloc(sizeof(*gpio_plat)); ++ if (!gpio_plat) ++ return -ENOMEM; ++ ++ gpio_plat->regs = plat->base + i; ++ gpio_plat->bank_name[0] = 'P'; ++ gpio_plat->bank_name[1] = 'A' + desc->first_bank + i; ++ gpio_plat->bank_name[2] = '\0'; ++ ++ ret = device_bind(gpio_dev, DM_DRIVER_REF(gpio_sunxi), ++ gpio_plat->bank_name, gpio_plat, ++ ofnode_null(), NULL); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct udevice_id sunxi_pinctrl_ids[] = { ++#if IS_ENABLED(CONFIG_PINCTRL_SUN4I_A10) ++ { ++ .compatible = "allwinner,sun4i-a10-pinctrl", ++ .data = (ulong)&sun4i_a10_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN5I_A13) ++ { ++ .compatible = "allwinner,sun5i-a10s-pinctrl", ++ .data = (ulong)&sun5i_a13_pinctrl_desc, ++ }, ++ { ++ .compatible = "allwinner,sun5i-a13-pinctrl", ++ .data = (ulong)&sun5i_a13_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN6I_A31) ++ { ++ .compatible = "allwinner,sun6i-a31-pinctrl", ++ .data = (ulong)&sun6i_a31_pinctrl_desc, ++ }, ++ { ++ .compatible = "allwinner,sun6i-a31s-pinctrl", ++ .data = (ulong)&sun6i_a31_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN6I_A31_R) ++ { ++ .compatible = "allwinner,sun6i-a31-r-pinctrl", ++ .data = (ulong)&sun6i_a31_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN7I_A20) ++ { ++ .compatible = "allwinner,sun7i-a20-pinctrl", ++ .data = (ulong)&sun7i_a20_pinctrl_desc, ++ }, ++ { ++ .compatible = "allwinner,sun8i-r40-pinctrl", ++ .data = (ulong)&sun7i_a20_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_A23) ++ { ++ .compatible = "allwinner,sun8i-a23-pinctrl", ++ .data = (ulong)&sun8i_a23_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_A23_R) ++ { ++ .compatible = "allwinner,sun8i-a23-r-pinctrl", ++ .data = (ulong)&sun8i_a23_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_A33) ++ { ++ .compatible = "allwinner,sun8i-a33-pinctrl", ++ .data = (ulong)&sun8i_a33_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_A83T) ++ { ++ .compatible = "allwinner,sun8i-a83t-pinctrl", ++ .data = (ulong)&sun8i_a83t_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_A83T_R) ++ { ++ .compatible = "allwinner,sun8i-a83t-r-pinctrl", ++ .data = (ulong)&sun8i_a83t_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_H3) ++ { ++ .compatible = "allwinner,sun8i-h3-pinctrl", ++ .data = (ulong)&sun8i_h3_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_H3_R) ++ { ++ .compatible = "allwinner,sun8i-h3-r-pinctrl", ++ .data = (ulong)&sun8i_h3_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN8I_V3S) ++ { ++ .compatible = "allwinner,sun8i-v3-pinctrl", ++ .data = (ulong)&sun8i_v3s_pinctrl_desc, ++ }, ++ { ++ .compatible = "allwinner,sun8i-v3s-pinctrl", ++ .data = (ulong)&sun8i_v3s_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN9I_A80) ++ { ++ .compatible = "allwinner,sun9i-a80-pinctrl", ++ .data = (ulong)&sun9i_a80_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN9I_A80_R) ++ { ++ .compatible = "allwinner,sun9i-a80-r-pinctrl", ++ .data = (ulong)&sun9i_a80_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN20I_D1) ++ { ++ .compatible = "allwinner,sun20i-d1-pinctrl", ++ .data = (ulong)&sun20i_d1_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_A64) ++ { ++ .compatible = "allwinner,sun50i-a64-pinctrl", ++ .data = (ulong)&sun50i_a64_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_A64_R) ++ { ++ .compatible = "allwinner,sun50i-a64-r-pinctrl", ++ .data = (ulong)&sun50i_a64_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_H5) ++ { ++ .compatible = "allwinner,sun50i-h5-pinctrl", ++ .data = (ulong)&sun50i_h5_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_H6) ++ { ++ .compatible = "allwinner,sun50i-h6-pinctrl", ++ .data = (ulong)&sun50i_h6_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_H6_R) ++ { ++ .compatible = "allwinner,sun50i-h6-r-pinctrl", ++ .data = (ulong)&sun50i_h6_r_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_H616) ++ { ++ .compatible = "allwinner,sun50i-h616-pinctrl", ++ .data = (ulong)&sun50i_h616_pinctrl_desc, ++ }, ++#endif ++#if IS_ENABLED(CONFIG_PINCTRL_SUN50I_H616_R) ++ { ++ .compatible = "allwinner,sun50i-h616-r-pinctrl", ++ .data = (ulong)&sun50i_h616_r_pinctrl_desc, ++ }, ++#endif ++ { } ++}; ++ ++U_BOOT_DRIVER(sunxi_pinctrl) = { ++ .name = "sunxi-pinctrl", ++ .id = UCLASS_PINCTRL, ++ .of_match = sunxi_pinctrl_ids, ++ .bind = sunxi_pinctrl_bind, ++ .plat_auto = sizeof(struct sunxi_pinctrl_plat), ++ .ops = &sunxi_pinctrl_ops, ++}; +diff -ruN u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sunxi.h u-boot/drivers/pinctrl/sunxi/pinctrl-sunxi.h +--- u-boot-2021.10/drivers/pinctrl/sunxi/pinctrl-sunxi.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/pinctrl/sunxi/pinctrl-sunxi.h 2021-11-01 17:10:14.422917069 +0100 +@@ -0,0 +1,44 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++//#include <asm/gpio.h> ++#include <common.h> ++#include "../../../arch/arm/include/asm/arch-sunxi/gpio.h" ++ ++/* "gpio_out" including the null terminator */ ++#define FUNCTION_NAME_MAX 9 ++ ++struct sunxi_pinctrl_function { ++ const char name[FUNCTION_NAME_MAX]; ++ u8 mux; ++}; ++ ++struct sunxi_pinctrl_desc { ++ const struct sunxi_pinctrl_function *functions; ++ u8 num_functions; ++ u8 first_bank; ++ u8 num_banks; ++}; ++ ++extern const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun20i_d1_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_a64_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_h6_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_h616_pinctrl_desc; ++extern const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_desc; +diff -ruN u-boot-2021.10/drivers/power/acpi_pmc/Makefile u-boot/drivers/power/acpi_pmc/Makefile +--- u-boot-2021.10/drivers/power/acpi_pmc/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/acpi_pmc/Makefile 2021-11-01 17:10:14.422917069 +0100 +@@ -2,5 +2,5 @@ + # + # Copyright 2019 Google LLC + +-obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o ++obj-y += acpi-pmc-uclass.o + obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o +diff -ruN u-boot-2021.10/drivers/power/axp152.c u-boot/drivers/power/axp152.c +--- u-boot-2021.10/drivers/power/axp152.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp152.c 2021-11-01 17:10:14.422917069 +0100 +@@ -79,6 +79,7 @@ + return 0; + } + ++#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP152_SHUTDOWN, AXP152_POWEROFF); +@@ -89,3 +90,4 @@ + /* not reached */ + return 0; + } ++#endif +diff -ruN u-boot-2021.10/drivers/power/axp209.c u-boot/drivers/power/axp209.c +--- u-boot-2021.10/drivers/power/axp209.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp209.c 2021-11-01 17:10:14.422917069 +0100 +@@ -230,6 +230,7 @@ + return 0; + } + ++#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP209_SHUTDOWN, AXP209_POWEROFF); +@@ -240,3 +241,4 @@ + /* not reached */ + return 0; + } ++#endif +diff -ruN u-boot-2021.10/drivers/power/axp221.c u-boot/drivers/power/axp221.c +--- u-boot-2021.10/drivers/power/axp221.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp221.c 2021-11-01 17:10:14.422917069 +0100 +@@ -264,6 +264,7 @@ + return 0; + } + ++#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP221_SHUTDOWN, AXP221_SHUTDOWN_POWEROFF); +@@ -274,3 +275,4 @@ + /* not reached */ + return 0; + } ++#endif +diff -ruN u-boot-2021.10/drivers/power/axp305.c u-boot/drivers/power/axp305.c +--- u-boot-2021.10/drivers/power/axp305.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp305.c 2021-11-01 17:10:14.422917069 +0100 +@@ -69,7 +69,7 @@ + return ret; + } + +-#ifndef CONFIG_PSCI_RESET ++#if !CONFIG_IS_ENABLED(ARM_PSCI_FW) && !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP305_SHUTDOWN, AXP305_POWEROFF); +diff -ruN u-boot-2021.10/drivers/power/axp809.c u-boot/drivers/power/axp809.c +--- u-boot-2021.10/drivers/power/axp809.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp809.c 2021-11-01 17:10:14.422917069 +0100 +@@ -13,7 +13,6 @@ + #include <common.h> + #include <command.h> + #include <errno.h> +-#include <asm/arch/gpio.h> + #include <asm/arch/pmic_bus.h> + #include <axp_pmic.h> + +@@ -220,6 +219,7 @@ + return pmic_bus_init(); + } + ++#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF); +@@ -230,3 +230,4 @@ + /* not reached */ + return 0; + } ++#endif +diff -ruN u-boot-2021.10/drivers/power/axp818.c u-boot/drivers/power/axp818.c +--- u-boot-2021.10/drivers/power/axp818.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/axp818.c 2021-11-01 17:10:14.422917069 +0100 +@@ -13,7 +13,6 @@ + #include <common.h> + #include <command.h> + #include <errno.h> +-#include <asm/arch/gpio.h> + #include <asm/arch/pmic_bus.h> + #include <axp_pmic.h> + +@@ -256,6 +255,7 @@ + return 0; + } + ++#if !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF) + int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) + { + pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF); +@@ -266,3 +266,4 @@ + /* not reached */ + return 0; + } ++#endif +diff -ruN u-boot-2021.10/drivers/power/domain/power-domain-uclass.c u-boot/drivers/power/domain/power-domain-uclass.c +--- u-boot-2021.10/drivers/power/domain/power-domain-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/domain/power-domain-uclass.c 2021-11-01 17:10:14.426250220 +0100 +@@ -112,7 +112,7 @@ + return ops->off(power_domain); + } + +-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int dev_power_domain_ctrl(struct udevice *dev, bool on) + { + struct power_domain pd; +@@ -162,7 +162,7 @@ + { + return dev_power_domain_ctrl(dev, false); + } +-#endif ++#endif /* OF_REAL */ + + UCLASS_DRIVER(power_domain) = { + .id = UCLASS_POWER_DOMAIN, +diff -ruN u-boot-2021.10/drivers/power/Kconfig u-boot/drivers/power/Kconfig +--- u-boot-2021.10/drivers/power/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/Kconfig 2021-11-01 17:10:14.422917069 +0100 +@@ -1,4 +1,46 @@ +-menu "Power" ++menuconfig POWER ++ bool "Power" ++ default y ++ help ++ Enable support for power control in U-Boot. This includes support ++ for PMICs (Power-management Integrated Circuits) and some of the ++ features provided by PMICs. In particular, voltage regulators can ++ be used to enable/disable power and vary its voltage. That can be ++ useful in U-Boot to turn on boot peripherals and adjust CPU voltage ++ so that the clock speed can be increased. This enables the drivers ++ in drivers/power, drivers/power/pmic and drivers/power/regulator ++ as part of a build. ++ ++if POWER ++ ++config POWER_LEGACY ++ bool "Legacy power support" ++ help ++ Note: This is a legacy option. Use DM_PMIC instead. ++ ++ Enable support for power control in U-Boot. This includes support ++ for PMICs (Power-management Integrated Circuits) and some of the ++ features provided by PMICs. In particular, voltage regulators can ++ be used to enable/disable power and vary its voltage. That can be ++ useful in U-Boot to turn on boot peripherals and adjust CPU voltage ++ so that the clock speed can be increased. This enables the drivers ++ in drivers/power, drivers/power/pmic and drivers/power/regulator ++ as part of a build. ++ ++config SPL_POWER_LEGACY ++ bool "Legacy power support in SPL" ++ default y if POWER_LEGACY ++ help ++ Note: This is a legacy option. Use SPL_DM_PMIC instead. ++ ++ Enable support for power control in SPL. This includes support ++ for PMICs (Power-management Integrated Circuits) and some of the ++ features provided by PMICs. In particular, voltage regulators can ++ be used to enable/disable power and vary its voltage. That can be ++ useful in SPL to turn on boot peripherals and adjust CPU voltage ++ so that the clock speed can be increased. This enables the drivers ++ in drivers/power, drivers/power/pmic and drivers/power/regulator ++ as part of a build. + + source "drivers/power/acpi_pmc/Kconfig" + +@@ -248,7 +290,6 @@ + config AXP_ALDO3_INRUSH_QUIRK + bool "axp pmic (a)ldo3 inrush quirk" + depends on AXP209_POWER +- default n + ---help--- + The reference design denotes a value of 4.7 uF for the output capacitor + of LDO3. Some boards have too high capacitance causing an inrush current +@@ -357,7 +398,6 @@ + config AXP_SW_ON + bool "axp pmic sw on" + depends on AXP809_POWER || AXP818_POWER +- default n + ---help--- + Enable to turn on axp pmic sw. + +@@ -385,4 +425,25 @@ + This adds poweroff driver for mt6323 + this pmic is used on mt7623 / Bananapi R2 + +-endmenu ++config POWER_I2C ++ bool "I2C-based power control for legacy power" ++ depends on POWER_LEGACY ++ help ++ Enable this to use the I2C driver designed for the legacy PMIC ++ interface. ++ ++ Not to be used for new designs and existing ones should be moved to ++ the new PMIC interface based on driver model. ++ ++config SPL_POWER_I2C ++ bool "I2C-based power control for legacy power" ++ depends on SPL_POWER_LEGACY ++ default y if POWER_I2C ++ help ++ Enable this to use the I2C driver designed for the legacy PMIC ++ interface. ++ ++ Not to be used for new designs and existing ones should be moved to ++ the new PMIC interface based on driver model. ++ ++endif +diff -ruN u-boot-2021.10/drivers/power/Makefile u-boot/drivers/power/Makefile +--- u-boot-2021.10/drivers/power/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/Makefile 2021-11-01 17:10:14.422917069 +0100 +@@ -3,6 +3,14 @@ + # Copyright (c) 2009 Wind River Systems, Inc. + # Tom Rix <Tom.Rix at windriver.com> + ++obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ ++obj-y += battery/ ++obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ ++obj-y += fuel_gauge/ ++obj-y += mfd/ ++obj-y += pmic/ ++obj-y += regulator/ ++ + obj-$(CONFIG_AXP152_POWER) += axp152.o + obj-$(CONFIG_AXP209_POWER) += axp209.o + obj-$(CONFIG_AXP221_POWER) += axp221.o +@@ -16,9 +24,9 @@ + obj-$(CONFIG_TWL4030_POWER) += twl4030.o + obj-$(CONFIG_TWL6030_POWER) += twl6030.o + obj-$(CONFIG_PALMAS_POWER) += palmas.o +-obj-$(CONFIG_POWER) += power_core.o ++obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o + obj-$(CONFIG_DIALOG_POWER) += power_dialog.o + obj-$(CONFIG_POWER_FSL) += power_fsl.o +-obj-$(CONFIG_POWER_I2C) += power_i2c.o ++obj-$(CONFIG_$(SPL_TPL_)POWER_I2C) += power_i2c.o + obj-$(CONFIG_POWER_SPI) += power_spi.o + obj-$(CONFIG_POWER_MT6323) += mt6323.o +diff -ruN u-boot-2021.10/drivers/power/pmic/axp.c u-boot/drivers/power/pmic/axp.c +--- u-boot-2021.10/drivers/power/pmic/axp.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/power/pmic/axp.c 2021-11-01 17:10:14.426250220 +0100 +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <axp_pmic.h> ++#include <dm.h> ++#include <dm/lists.h> ++#include <i2c.h> ++#include <power/pmic.h> ++#include <sysreset.h> ++ ++#if CONFIG_IS_ENABLED(SYSRESET) ++static int axp_sysreset_request(struct udevice *dev, enum sysreset_t type) ++{ ++ int ret; ++ ++ if (type != SYSRESET_POWER_OFF) ++ return -EPROTONOSUPPORT; ++ ++ ret = pmic_clrsetbits(dev->parent, AXP152_SHUTDOWN, 0, AXP152_POWEROFF); ++ if (ret < 0) ++ return ret; ++ ++ return -EINPROGRESS; ++} ++ ++static struct sysreset_ops axp_sysreset_ops = { ++ .request = axp_sysreset_request, ++}; ++ ++U_BOOT_DRIVER(axp_sysreset) = { ++ .name = "axp_sysreset", ++ .id = UCLASS_SYSRESET, ++ .ops = &axp_sysreset_ops, ++}; ++#endif ++ ++static int axp_pmic_reg_count(struct udevice *dev) ++{ ++ /* TODO: Get the specific value from driver data. */ ++ return 0x100; ++} ++ ++static struct dm_pmic_ops axp_pmic_ops = { ++ .reg_count = axp_pmic_reg_count, ++ .read = dm_i2c_read, ++ .write = dm_i2c_write, ++}; ++ ++static const struct pmic_child_info axp_pmic_child_info[] = { ++ { "drivevbus", "axp_drivevbus" }, ++ { } ++}; ++ ++static int axp_pmic_bind(struct udevice *dev) ++{ ++ ofnode regulators_node; ++ int ret; ++ ++ ret = dm_scan_fdt_dev(dev); ++ if (ret) ++ return ret; ++ ++ regulators_node = dev_read_subnode(dev, "regulators"); ++ if (!ofnode_valid(regulators_node)) ++ return -ENXIO; ++ ++ pmic_bind_children(dev, regulators_node, axp_pmic_child_info); ++ ++ if (CONFIG_IS_ENABLED(SYSRESET)) { ++ ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset", ++ dev_ofnode(dev), NULL); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct udevice_id axp_pmic_ids[] = { ++ { .compatible = "x-powers,axp152" }, ++ { .compatible = "x-powers,axp202" }, ++ { .compatible = "x-powers,axp209" }, ++ { .compatible = "x-powers,axp221" }, ++ { .compatible = "x-powers,axp223" }, ++ { .compatible = "x-powers,axp803" }, ++ { .compatible = "x-powers,axp806" }, ++ { .compatible = "x-powers,axp809" }, ++ { .compatible = "x-powers,axp813" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(axp_pmic) = { ++ .name = "axp_pmic", ++ .id = UCLASS_PMIC, ++ .of_match = axp_pmic_ids, ++ .bind = axp_pmic_bind, ++ .ops = &axp_pmic_ops, ++}; +diff -ruN u-boot-2021.10/drivers/power/pmic/Kconfig u-boot/drivers/power/pmic/Kconfig +--- u-boot-2021.10/drivers/power/pmic/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/pmic/Kconfig 2021-11-01 17:10:14.426250220 +0100 +@@ -10,9 +10,23 @@ + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' + ++if DM_PMIC ++ ++config SPL_DM_PMIC ++ bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" ++ depends on SPL_DM ++ default y ++ ---help--- ++ This config enables the driver-model PMIC support in SPL. ++ UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. ++ For the multi-function PMIC devices, this can be used as parent I/O ++ device for each IC's interface. Then, each children uses its parent ++ for read/write. For detailed description, please refer to the files: ++ - 'drivers/power/pmic/pmic-uclass.c' ++ - 'include/power/pmic.h' ++ + config PMIC_CHILDREN + bool "Allow child devices for PMICs" +- depends on DM_PMIC + default y + ---help--- + This allows PMICs to support child devices (such as regulators) in +@@ -22,7 +36,7 @@ + + config SPL_PMIC_CHILDREN + bool "Allow child devices for PMICs in SPL" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + default y + ---help--- + This allows PMICs to support child devices (such as regulators) in +@@ -33,7 +47,6 @@ + + config PMIC_AB8500 + bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU" +- depends on DM_PMIC + select REGMAP + select SYSCON + help +@@ -43,23 +56,38 @@ + + config PMIC_ACT8846 + bool "Enable support for the active-semi 8846 PMIC" +- depends on DM_PMIC && DM_I2C ++ depends on DM_I2C + ---help--- + This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout + regulators (LDOs). It also provides some GPIO, reset and battery + functions. It uses an I2C interface and is designed for use with + tablets and smartphones. + ++config PMIC_AXP ++ bool "Enable Driver Model for X-Powers AXP PMICs" ++ depends on DM_I2C ++ select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF ++ imply CMD_POWEROFF if SYSRESET ++ help ++ This config enables driver-model PMIC uclass features for ++ X-Powers AXP152, AXP2xx, and AXP8xx PMICs. ++ ++config SPL_PMIC_AXP ++ bool "Enable Driver Model for X-Powers AXP PMICs in SPL" ++ depends on SPL_DM_I2C && SPL_DM_PMIC ++ help ++ This config enables driver-model PMIC uclass features in the SPL for ++ X-Powers AXP152, AXP2xx, and AXP8xx PMICs. ++ + config DM_PMIC_DA9063 + bool "Enable Driver Model for the Dialog DA9063 PMIC" +- depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC DA9063. The driver implements read/write operations. + + config SPL_DM_PMIC_DA9063 + bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL" +- depends on DM_PMIC && SPL ++ depends on SPL_DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC DA9063. The driver implements read/write operations. +@@ -74,14 +102,13 @@ + + config DM_PMIC_BD71837 + bool "Enable Driver Model for PMIC BD71837" +- depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC BD71837. The driver implements read/write operations. + + config SPL_DM_PMIC_BD71837 + bool "Enable Driver Model for PMIC BD71837 in SPL stage" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + This config enables implementation of driver-model pmic uclass + features for PMIC BD71837. The driver implements read/write +@@ -89,7 +116,7 @@ + + config DM_PMIC_FAN53555 + bool "Enable support for OnSemi FAN53555" +- depends on DM_PMIC && DM_REGULATOR && DM_I2C ++ depends on DM_REGULATOR && DM_I2C + select DM_REGULATOR_FAN53555 + help + This config enables implementation of driver-model PMIC +@@ -103,14 +130,13 @@ + + config DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416" +- depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC MP5416. The driver implements read/write operations. + + config SPL_DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416 in SPL stage" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + This config enables implementation of driver-model pmic uclass + features for PMIC MP5416. The driver implements read/write +@@ -118,56 +144,50 @@ + + config DM_PMIC_PCA9450 + bool "Enable Driver Model for PMIC PCA9450" +- depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC PCA9450. The driver implements read/write operations. + + config SPL_DM_PMIC_PCA9450 + bool "Enable Driver Model for PMIC PCA9450" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC PCA9450 in SPL. The driver implements read/write operations. + + config DM_PMIC_PFUZE100 + bool "Enable Driver Model for PMIC PFUZE100" +- depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100. The driver implements read/write operations. + + config SPL_DM_PMIC_PFUZE100 + bool "Enable Driver Model for PMIC PFUZE100 in SPL" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100 in SPL. The driver implements read/write operations. + + config DM_PMIC_MAX77686 + bool "Enable Driver Model for PMIC MAX77686" +- depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77686. The driver implements read/write operations. + + config DM_PMIC_MAX8998 + bool "Enable Driver Model for PMIC MAX8998" +- depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8998. The driver implements read/write operations. + + config DM_PMIC_MC34708 + bool "Enable Driver Model for PMIC MC34708" +- depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC MC34708. The driver implements read/write operations. + + config PMIC_MAX8997 + bool "Enable Driver Model for PMIC MAX8997" +- depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8997. The driver implements read/write operations. +@@ -182,7 +202,6 @@ + + config PMIC_PM8916 + bool "Enable Driver Model for Qualcomm PM8916 PMIC" +- depends on DM_PMIC + ---help--- + The PM8916 is a PMIC connected to one (or several) processors + with SPMI bus. It has 2 slaves with several peripherals: +@@ -198,6 +217,14 @@ + + config PMIC_RK8XX + bool "Enable support for Rockchip PMIC RK8XX" ++ ---help--- ++ The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, ++ an RTC and two low Rds (resistance (drain to source)) switches. It is ++ accessed via an I2C interface. The device is used with Rockchip SoCs. ++ This driver implements register read/write operations. ++ ++config SPL_PMIC_RK8XX ++ bool "Enable support for Rockchip PMIC RK8XX" + depends on DM_PMIC + ---help--- + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, +@@ -207,7 +234,6 @@ + + config PMIC_S2MPS11 + bool "Enable Driver Model for PMIC Samsung S2MPS11" +- depends on DM_PMIC + ---help--- + The Samsung S2MPS11 PMIC provides: + - 38 adjustable LDO regulators +@@ -221,7 +247,6 @@ + + config DM_PMIC_SANDBOX + bool "Enable Driver Model for emulated Sandbox PMIC" +- depends on DM_PMIC + ---help--- + Enable the driver for Sandbox PMIC emulation. The emulated PMIC device + depends on two drivers: +@@ -246,7 +271,6 @@ + + config PMIC_S5M8767 + bool "Enable Driver Model for the Samsung S5M8767 PMIC" +- depends on DM_PMIC + ---help--- + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use + as a SoC power controller. It also provides 32KHz clock outputs. This +@@ -255,7 +279,6 @@ + + config PMIC_RN5T567 + bool "Enable driver for Ricoh RN5T567 PMIC" +- depends on DM_PMIC + ---help--- + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides +@@ -263,7 +286,6 @@ + + config PMIC_TPS65090 + bool "Enable driver for Texas Instruments TPS65090 PMIC" +- depends on DM_PMIC + ---help--- + The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access +@@ -272,21 +294,18 @@ + + config PMIC_PALMAS + bool "Enable driver for Texas Instruments PALMAS PMIC" +- depends on DM_PMIC + ---help--- + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children. + + config PMIC_LP873X + bool "Enable driver for Texas Instruments LP873X PMIC" +- depends on DM_PMIC + ---help--- + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children. + + config PMIC_LP87565 + bool "Enable driver for Texas Instruments LP87565 PMIC" +- depends on DM_PMIC + ---help--- + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children. +@@ -300,7 +319,6 @@ + + config DM_PMIC_TPS65910 + bool "Enable driver for Texas Instruments TPS65910 PMIC" +- depends on DM_PMIC + ---help--- + The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost + DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO +@@ -308,7 +326,7 @@ + + config PMIC_STPMIC1 + bool "Enable support for STMicroelectronics STPMIC1 PMIC" +- depends on DM_PMIC && DM_I2C ++ depends on DM_I2C + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW + ---help--- + The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. +@@ -317,28 +335,29 @@ + + config SPL_PMIC_PALMAS + bool "Enable driver for Texas Instruments PALMAS PMIC" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children in SPL. + + config SPL_PMIC_LP873X + bool "Enable driver for Texas Instruments LP873X PMIC" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children in SPL. + + config SPL_PMIC_LP87565 + bool "Enable driver for Texas Instruments LP87565 PMIC" +- depends on DM_PMIC ++ depends on SPL_DM_PMIC + help + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children in SPL. + + config PMIC_TPS65941 + bool "Enable driver for Texas Instruments TPS65941 PMIC" +- depends on DM_PMIC + help + The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. ++ ++endif +diff -ruN u-boot-2021.10/drivers/power/pmic/Makefile u-boot/drivers/power/pmic/Makefile +--- u-boot-2021.10/drivers/power/pmic/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/pmic/Makefile 2021-11-01 17:10:14.426250220 +0100 +@@ -3,7 +3,7 @@ + # Copyright (C) 2012 Samsung Electronics + # Lukasz Majewski <l.majewski@samsung.com> + +-obj-$(CONFIG_DM_PMIC) += pmic-uclass.o ++obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o + obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o + obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o + obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o +@@ -18,9 +18,10 @@ + obj-$(CONFIG_PMIC_AB8500) += ab8500.o + obj-$(CONFIG_PMIC_ACT8846) += act8846.o + obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o ++obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o + obj-$(CONFIG_PMIC_MAX8997) += max8997.o + obj-$(CONFIG_PMIC_PM8916) += pm8916.o +-obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o ++obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o + obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o + obj-$(CONFIG_PMIC_TPS65090) += tps65090.o + obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o +diff -ruN u-boot-2021.10/drivers/power/pmic/pmic_tps65910.c u-boot/drivers/power/pmic/pmic_tps65910.c +--- u-boot-2021.10/drivers/power/pmic/pmic_tps65910.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/pmic/pmic_tps65910.c 2021-11-01 17:10:14.426250220 +0100 +@@ -51,7 +51,7 @@ + + /* + * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C +- * interface. ++ * interface. + * @return: 0 on success, not 0 on failure + */ + int tps65910_set_i2c_control(void) +diff -ruN u-boot-2021.10/drivers/power/regulator/axp_regulator.c u-boot/drivers/power/regulator/axp_regulator.c +--- u-boot-2021.10/drivers/power/regulator/axp_regulator.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/power/regulator/axp_regulator.c 2021-11-01 17:10:14.429583371 +0100 +@@ -0,0 +1,58 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <dm.h> ++#include <errno.h> ++#include <power/pmic.h> ++#include <power/regulator.h> ++ ++#define AXP_VBUS_IPSOUT 0x30 ++#define AXP_VBUS_IPSOUT_DRIVEBUS BIT(2) ++#define AXP_MISC_CTRL 0x8f ++#define AXP_MISC_CTRL_N_VBUSEN_FUNC BIT(4) ++ ++static int axp_drivevbus_get_enable(struct udevice *dev) ++{ ++ int ret; ++ ++ ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT); ++ if (ret < 0) ++ return ret; ++ ++ return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS); ++} ++ ++static int axp_drivevbus_set_enable(struct udevice *dev, bool enable) ++{ ++ return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT, ++ AXP_VBUS_IPSOUT_DRIVEBUS, ++ enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0); ++} ++ ++static const struct dm_regulator_ops axp_drivevbus_ops = { ++ .get_enable = axp_drivevbus_get_enable, ++ .set_enable = axp_drivevbus_set_enable, ++}; ++ ++static int axp_drivevbus_probe(struct udevice *dev) ++{ ++ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev); ++ int ret; ++ ++ uc_plat->type = REGULATOR_TYPE_FIXED; ++ ++ if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) { ++ ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL, ++ AXP_MISC_CTRL_N_VBUSEN_FUNC, 0); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++U_BOOT_DRIVER(axp_drivevbus) = { ++ .name = "axp_drivevbus", ++ .id = UCLASS_REGULATOR, ++ .probe = axp_drivevbus_probe, ++ .ops = &axp_drivevbus_ops, ++}; +diff -ruN u-boot-2021.10/drivers/power/regulator/axp_usb_power.c u-boot/drivers/power/regulator/axp_usb_power.c +--- u-boot-2021.10/drivers/power/regulator/axp_usb_power.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/power/regulator/axp_usb_power.c 2021-11-01 17:10:14.429583371 +0100 +@@ -0,0 +1,49 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <dm/device.h> ++#include <errno.h> ++#include <power/pmic.h> ++#include <power/regulator.h> ++ ++#define AXP_POWER_STATUS 0x00 ++#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) ++ ++static int axp_usb_power_get_enable(struct udevice *dev) ++{ ++ int ret; ++ ++ ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS); ++ if (ret < 0) ++ return ret; ++ ++ return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT); ++} ++ ++static const struct dm_regulator_ops axp_usb_power_ops = { ++ .get_enable = axp_usb_power_get_enable, ++}; ++ ++static int axp_usb_power_probe(struct udevice *dev) ++{ ++ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev); ++ ++ uc_plat->type = REGULATOR_TYPE_FIXED; ++ ++ return 0; ++} ++ ++static const struct udevice_id axp_usb_power_ids[] = { ++ { .compatible = "x-powers,axp202-usb-power-supply" }, ++ { .compatible = "x-powers,axp221-usb-power-supply" }, ++ { .compatible = "x-powers,axp223-usb-power-supply" }, ++ { .compatible = "x-powers,axp813-usb-power-supply" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(axp_usb_power) = { ++ .name = "axp_usb_power", ++ .id = UCLASS_REGULATOR, ++ .of_match = axp_usb_power_ids, ++ .probe = axp_usb_power_probe, ++ .ops = &axp_usb_power_ops, ++}; +diff -ruN u-boot-2021.10/drivers/power/regulator/Kconfig u-boot/drivers/power/regulator/Kconfig +--- u-boot-2021.10/drivers/power/regulator/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/regulator/Kconfig 2021-11-01 17:10:14.429583371 +0100 +@@ -43,6 +43,27 @@ + but does not yet support change voltages. Currently this must be + done using direct register writes to the PMIC. + ++config REGULATOR_AXP ++ bool "Enable driver for X-Powers AXP PMIC regulators" ++ depends on DM_REGULATOR && PMIC_AXP ++ help ++ Enable support for the regulators (DCDCs, LDOs) in the ++ X-Powers AXP152, AXP2xx, and AXP8xx PMICs. ++ ++config SPL_REGULATOR_AXP ++ bool "Enable driver for X-Powers AXP PMIC regulators in SPL" ++ depends on SPL_DM_REGULATOR && SPL_PMIC_AXP ++ help ++ Enable support in SPL for the regulators (DCDCs, LDOs) in the ++ X-Powers AXP152, AXP2xx, and AXP8xx PMICs. ++ ++config REGULATOR_AXP_USB_POWER ++ bool "Enable driver for X-Powers AXP PMIC USB power supply" ++ depends on DM_REGULATOR && PMIC_AXP ++ help ++ Enable support for reading the USB power supply status from ++ X-Powers AXP2xx and AXP8xx PMICs. ++ + config DM_REGULATOR_BD71837 + bool "Enable Driver Model for ROHM BD71837/BD71847 regulators" + depends on DM_REGULATOR && DM_PMIC_BD71837 +diff -ruN u-boot-2021.10/drivers/power/regulator/Makefile u-boot/drivers/power/regulator/Makefile +--- u-boot-2021.10/drivers/power/regulator/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/power/regulator/Makefile 2021-11-01 17:10:14.429583371 +0100 +@@ -7,6 +7,8 @@ + obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o + obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o + obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o ++obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o ++obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o + obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o + obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o + obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o +@@ -16,7 +18,7 @@ + obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o + obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o + obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o +-obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o ++obj-$(CONFIG_$(SPL_TPL_)REGULATOR_RK8XX) += rk8xx.o + obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o + obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o + obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o +diff -ruN u-boot-2021.10/drivers/pwm/pwm-meson.c u-boot/drivers/pwm/pwm-meson.c +--- u-boot-2021.10/drivers/pwm/pwm-meson.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pwm/pwm-meson.c 2021-11-01 17:10:14.429583371 +0100 +@@ -401,7 +401,7 @@ + .set_invert = meson_pwm_set_invert, + }; + +-#define XTAL -1 ++#define XTAL -1 + + /* Local clock ids aliases to avoid define conflicts */ + #define GXBB_CLKID_HDMI_PLL 2 +diff -ruN u-boot-2021.10/drivers/pwm/sunxi_pwm.c u-boot/drivers/pwm/sunxi_pwm.c +--- u-boot-2021.10/drivers/pwm/sunxi_pwm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/pwm/sunxi_pwm.c 2021-11-01 17:10:14.432916521 +0100 +@@ -13,7 +13,6 @@ + #include <asm/global_data.h> + #include <asm/io.h> + #include <asm/arch/pwm.h> +-#include <asm/arch/gpio.h> + #include <power/regulator.h> + + DECLARE_GLOBAL_DATA_PTR; +@@ -45,14 +44,6 @@ + 1, /* 1111 */ + }; + +-static int sunxi_pwm_config_pinmux(void) +-{ +-#ifdef CONFIG_MACH_SUN50I +- sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM); +-#endif +- return 0; +-} +- + static int sunxi_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) + { +@@ -137,8 +128,6 @@ + return 0; + } + +- sunxi_pwm_config_pinmux(); +- + if (priv->invert) + v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA; + else +diff -ruN u-boot-2021.10/drivers/qe/uec.c u-boot/drivers/qe/uec.c +--- u-boot-2021.10/drivers/qe/uec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/qe/uec.c 2021-11-01 17:10:14.432916521 +0100 +@@ -1407,7 +1407,7 @@ + + if (!mdiodev) + return -ENOMEM; +- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); ++ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = uec_miiphy_read; + mdiodev->write = uec_miiphy_write; + +diff -ruN u-boot-2021.10/drivers/ram/aspeed/Kconfig u-boot/drivers/ram/aspeed/Kconfig +--- u-boot-2021.10/drivers/ram/aspeed/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/aspeed/Kconfig 2021-11-01 17:10:14.432916521 +0100 +@@ -3,7 +3,6 @@ + config ASPEED_DDR4_DUALX8 + bool "Enable Dual X8 DDR4 die" + depends on DM && OF_CONTROL && ARCH_ASPEED +- default n + help + Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram + controller needs to know if the memory chip mounted on the board is dual +@@ -42,14 +41,12 @@ + + config ASPEED_BYPASS_SELFTEST + bool "bypass self test during DRAM initialization" +- default n + help + Say Y here to bypass DRAM self test to speed up the boot time + + config ASPEED_ECC + bool "aspeed SDRAM error correcting code" + depends on DM && OF_CONTROL && ARCH_ASPEED +- default n + help + enable SDRAM ECC function + +diff -ruN u-boot-2021.10/drivers/ram/k3-ddrss/k3-ddrss.c u-boot/drivers/ram/k3-ddrss/k3-ddrss.c +--- u-boot-2021.10/drivers/ram/k3-ddrss/k3-ddrss.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/k3-ddrss/k3-ddrss.c 2021-11-01 17:10:14.446249125 +0100 +@@ -27,8 +27,8 @@ + #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 + #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 + +-#define DDRSS_V2A_R1_MAT_REG 0x0020 +-#define DDRSS_ECC_CTRL_REG 0x0120 ++#define DDRSS_V2A_R1_MAT_REG 0x0020 ++#define DDRSS_ECC_CTRL_REG 0x0120 + + struct k3_ddrss_desc { + struct udevice *dev; +diff -ruN u-boot-2021.10/drivers/ram/octeon/Kconfig u-boot/drivers/ram/octeon/Kconfig +--- u-boot-2021.10/drivers/ram/octeon/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/octeon/Kconfig 2021-11-01 17:10:14.449582277 +0100 +@@ -1,7 +1,6 @@ + config RAM_OCTEON + bool "Ram drivers for Octeon SoCs" + depends on RAM && ARCH_OCTEON +- default n + help + This enables support for RAM drivers for Octeon SoCs. + +@@ -9,7 +8,6 @@ + + config RAM_OCTEON_DDR4 + bool "Octeon III DDR4 RAM support" +- default n + help + This enables support for DDR4 RAM suppoort for Octeon III. This does + not include support for Octeon CN70XX. +diff -ruN u-boot-2021.10/drivers/ram/rockchip/dmc-rk3368.c u-boot/drivers/ram/rockchip/dmc-rk3368.c +--- u-boot-2021.10/drivers/ram/rockchip/dmc-rk3368.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/dmc-rk3368.c 2021-11-01 17:10:14.452915428 +0100 +@@ -883,13 +883,13 @@ + { + int ret = 0; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rk3368_sdram_params *plat = dev_get_plat(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rk3368_sdram_params *plat = dev_get_plat(dev); + +- ret = regmap_init_mem(dev_ofnode(dev), &plat->map); +- if (ret) +- return ret; +-#endif ++ ret = regmap_init_mem(dev_ofnode(dev), &plat->map); ++ if (ret) ++ return ret; ++ } + + return ret; + } +diff -ruN u-boot-2021.10/drivers/ram/rockchip/sdram_rk3188.c u-boot/drivers/ram/rockchip/sdram_rk3188.c +--- u-boot-2021.10/drivers/ram/rockchip/sdram_rk3188.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/sdram_rk3188.c 2021-11-01 17:10:14.452915428 +0100 +@@ -816,10 +816,12 @@ + + static int rk3188_dmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_sdram_params *params = dev_get_plat(dev); + int ret; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + /* rk3188 supports only one-channel */ + params->num_channels = 1; + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", +@@ -846,7 +848,6 @@ + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +-#endif + + return 0; + } +diff -ruN u-boot-2021.10/drivers/ram/rockchip/sdram_rk322x.c u-boot/drivers/ram/rockchip/sdram_rk322x.c +--- u-boot-2021.10/drivers/ram/rockchip/sdram_rk322x.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/sdram_rk322x.c 2021-11-01 17:10:14.452915428 +0100 +@@ -716,12 +716,14 @@ + + static int rk322x_dmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk322x_sdram_params *params = dev_get_plat(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + int ret; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + params->num_channels = 1; + + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", +@@ -748,7 +750,6 @@ + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +-#endif + + return 0; + } +@@ -852,4 +853,3 @@ + .plat_auto = sizeof(struct rk322x_sdram_params), + #endif + }; +- +diff -ruN u-boot-2021.10/drivers/ram/rockchip/sdram_rk3288.c u-boot/drivers/ram/rockchip/sdram_rk3288.c +--- u-boot-2021.10/drivers/ram/rockchip/sdram_rk3288.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/sdram_rk3288.c 2021-11-01 17:10:14.452915428 +0100 +@@ -973,10 +973,12 @@ + + static int rk3288_dmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3288_sdram_params *params = dev_get_plat(dev); + int ret; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + /* Rk3288 supports dual-channel, set default channel num to 2 */ + params->num_channels = 2; + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", +@@ -1008,7 +1010,6 @@ + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +-#endif + + return 0; + } +diff -ruN u-boot-2021.10/drivers/ram/rockchip/sdram_rk3328.c u-boot/drivers/ram/rockchip/sdram_rk3328.c +--- u-boot-2021.10/drivers/ram/rockchip/sdram_rk3328.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/sdram_rk3328.c 2021-11-01 17:10:14.452915428 +0100 +@@ -517,7 +517,7 @@ + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct rk3328_sdram_params *params = &plat->sdram_params; + #else + struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; +@@ -549,7 +549,7 @@ + + static int rk3328_dmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + +diff -ruN u-boot-2021.10/drivers/ram/rockchip/sdram_rk3399.c u-boot/drivers/ram/rockchip/sdram_rk3399.c +--- u-boot-2021.10/drivers/ram/rockchip/sdram_rk3399.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/rockchip/sdram_rk3399.c 2021-11-01 17:10:14.452915428 +0100 +@@ -3013,10 +3013,12 @@ + + static int rk3399_dmc_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + ++ if (!CONFIG_IS_ENABLED(OF_REAL)) ++ return 0; ++ + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); +@@ -3029,7 +3031,6 @@ + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); + +-#endif + return 0; + } + +@@ -3068,7 +3069,7 @@ + struct dram_info *priv = dev_get_priv(dev); + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct rk3399_sdram_params *params = &plat->sdram_params; + #else + struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; +@@ -3106,7 +3107,7 @@ + priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); + + #if CONFIG_IS_ENABLED(OF_PLATDATA) +- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk); ++ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk); + #else + ret = clk_get_by_index(dev, 0, &priv->ddr_clk); + #endif +diff -ruN u-boot-2021.10/drivers/ram/stm32mp1/Kconfig u-boot/drivers/ram/stm32mp1/Kconfig +--- u-boot-2021.10/drivers/ram/stm32mp1/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/stm32mp1/Kconfig 2021-11-01 17:10:14.452915428 +0100 +@@ -23,7 +23,6 @@ + config STM32MP1_DDR_INTERACTIVE_FORCE + bool "STM32MP1 DDR driver : force interactive mode" + depends on STM32MP1_DDR_INTERACTIVE +- default n + help + force interactive mode in STM32MP1 DDR controller driver + skip the polling of character 'd' in console +diff -ruN u-boot-2021.10/drivers/ram/stm32_sdram.c u-boot/drivers/ram/stm32_sdram.c +--- u-boot-2021.10/drivers/ram/stm32_sdram.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/ram/stm32_sdram.c 2021-11-01 17:10:14.452915428 +0100 +@@ -286,7 +286,7 @@ + } else { + dev_dbg(dev, "cannot find st,mem_remap property\n"); + } +- ++ + swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); + if (swp_fmc != NOT_FOUND) { + /* set fmc swapping selection */ +diff -ruN u-boot-2021.10/drivers/reboot-mode/Kconfig u-boot/drivers/reboot-mode/Kconfig +--- u-boot-2021.10/drivers/reboot-mode/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reboot-mode/Kconfig 2021-11-01 17:10:14.456248579 +0100 +@@ -9,7 +9,6 @@ + config DM_REBOOT_MODE + bool "Enable reboot mode using Driver Model" + depends on DM +- default n + help + Enable support for reboot mode control. This will allow users to + adjust the boot process based on reboot mode parameter +@@ -18,7 +17,6 @@ + config DM_REBOOT_MODE_GPIO + bool "Use GPIOs as reboot mode backend" + depends on DM_REBOOT_MODE +- default n + help + Use GPIOs to control the reboot mode. This will allow users to boot + a device in a specific mode by using a GPIO that can be controlled +@@ -27,7 +25,6 @@ + config DM_REBOOT_MODE_RTC + bool "Use RTC as reboot mode backend" + depends on DM_REBOOT_MODE +- default n + help + Use RTC non volatile memory to control the reboot mode. This will allow users to boot + a device in a specific mode by using a register(s) that can be controlled +diff -ruN u-boot-2021.10/drivers/reboot-mode/reboot-mode-uclass.c u-boot/drivers/reboot-mode/reboot-mode-uclass.c +--- u-boot-2021.10/drivers/reboot-mode/reboot-mode-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reboot-mode/reboot-mode-uclass.c 2021-11-01 17:10:14.456248579 +0100 +@@ -10,8 +10,6 @@ + #include <exports.h> + #include <reboot-mode/reboot-mode.h> + +-DECLARE_GLOBAL_DATA_PTR; +- + int dm_reboot_mode_update(struct udevice *dev) + { + struct reboot_mode_ops *ops = reboot_mode_get_ops(dev); +@@ -66,25 +64,20 @@ + return -EINVAL; + + #if CONFIG_IS_ENABLED(OF_CONTROL) +- const int node = dev_of_offset(dev); + const char *mode_prefix = "mode-"; + const int mode_prefix_len = strlen(mode_prefix); +- int property; ++ struct ofprop property; + const u32 *propvalue; + const char *propname; + +- plat_data->env_variable = fdt_getprop(gd->fdt_blob, +- node, +- "u-boot,env-variable", +- NULL); ++ plat_data->env_variable = dev_read_string(dev, "u-boot,env-variable"); + if (!plat_data->env_variable) + plat_data->env_variable = "reboot-mode"; + + plat_data->count = 0; + +- fdt_for_each_property_offset(property, gd->fdt_blob, node) { +- propvalue = fdt_getprop_by_offset(gd->fdt_blob, +- property, &propname, NULL); ++ dev_for_each_property(property, dev) { ++ propvalue = dev_read_prop_by_prop(&property, &propname, NULL); + if (!propvalue) { + dev_err(dev, "Could not get the value for property %s\n", + propname); +@@ -100,9 +93,8 @@ + + struct reboot_mode_mode *next = plat_data->modes; + +- fdt_for_each_property_offset(property, gd->fdt_blob, node) { +- propvalue = fdt_getprop_by_offset(gd->fdt_blob, +- property, &propname, NULL); ++ dev_for_each_property(property, dev) { ++ propvalue = dev_read_prop_by_prop(&property, &propname, NULL); + if (!propvalue) { + dev_err(dev, "Could not get the value for property %s\n", + propname); +diff -ruN u-boot-2021.10/drivers/remoteproc/rproc-uclass.c u-boot/drivers/remoteproc/rproc-uclass.c +--- u-boot-2021.10/drivers/remoteproc/rproc-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/remoteproc/rproc-uclass.c 2021-11-01 17:10:14.456248579 +0100 +@@ -9,19 +9,15 @@ + #define pr_fmt(fmt) "%s: " fmt, __func__ + #include <common.h> + #include <errno.h> +-#include <fdtdec.h> + #include <log.h> + #include <malloc.h> + #include <remoteproc.h> +-#include <asm/global_data.h> + #include <asm/io.h> + #include <dm/device-internal.h> + #include <dm.h> + #include <dm/uclass.h> + #include <dm/uclass-internal.h> + +-DECLARE_GLOBAL_DATA_PTR; +- + /** + * for_each_remoteproc_device() - iterate through the list of rproc devices + * @fn: check function to call per match, if this function returns fail, +@@ -121,21 +117,13 @@ + + if (!dev_get_plat(dev)) { + #if CONFIG_IS_ENABLED(OF_CONTROL) +- int node = dev_of_offset(dev); +- const void *blob = gd->fdt_blob; + bool tmp; +- if (!blob) { +- debug("'%s' no dt?\n", dev->name); +- return -EINVAL; +- } + debug("'%s': using fdt\n", dev->name); +- uc_pdata->name = fdt_getprop(blob, node, +- "remoteproc-name", NULL); ++ uc_pdata->name = dev_read_string(dev, "remoteproc-name"); + + /* Default is internal memory mapped */ + uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED; +- tmp = fdtdec_get_bool(blob, node, +- "remoteproc-internal-memory-mapped"); ++ tmp = dev_read_bool(dev, "remoteproc-internal-memory-mapped"); + if (tmp) + uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED; + #else +diff -ruN u-boot-2021.10/drivers/reset/Kconfig u-boot/drivers/reset/Kconfig +--- u-boot-2021.10/drivers/reset/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reset/Kconfig 2021-11-01 17:10:14.456248579 +0100 +@@ -137,7 +137,7 @@ + + config RESET_SUNXI + bool "RESET support for Allwinner SoCs" +- depends on DM_RESET && ARCH_SUNXI ++ depends on DM_RESET && (ARCH_SUNXI || TARGET_SUNXI) + default y + help + This enables support for common reset driver for +diff -ruN u-boot-2021.10/drivers/reset/reset-meson.c u-boot/drivers/reset/reset-meson.c +--- u-boot-2021.10/drivers/reset/reset-meson.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reset/reset-meson.c 2021-11-01 17:10:14.456248579 +0100 +@@ -70,16 +70,16 @@ + .rst_deassert = meson_reset_deassert, + }; + +-static const struct udevice_id meson_reset_ids[] = { +- { .compatible = "amlogic,meson-gxbb-reset" }, ++static const struct udevice_id meson_reset_ids[] = { ++ { .compatible = "amlogic,meson-gxbb-reset" }, + { .compatible = "amlogic,meson-axg-reset" }, +- { } +-}; ++ { } ++}; + + static int meson_reset_probe(struct udevice *dev) + { + struct meson_reset_priv *priv = dev_get_priv(dev); +- ++ + return regmap_init_mem(dev_ofnode(dev), &priv->regmap); + } + +diff -ruN u-boot-2021.10/drivers/reset/reset-raspberrypi.c u-boot/drivers/reset/reset-raspberrypi.c +--- u-boot-2021.10/drivers/reset/reset-raspberrypi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reset/reset-raspberrypi.c 2021-11-01 17:10:14.456248579 +0100 +@@ -57,4 +57,3 @@ + .of_match = raspberrypi_reset_ids, + .ops = &raspberrypi_reset_ops, + }; +- +diff -ruN u-boot-2021.10/drivers/reset/reset-sunxi.c u-boot/drivers/reset/reset-sunxi.c +--- u-boot-2021.10/drivers/reset/reset-sunxi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/reset/reset-sunxi.c 2021-11-01 17:10:14.459581730 +0100 +@@ -11,11 +11,11 @@ + #include <malloc.h> + #include <reset-uclass.h> + #include <asm/io.h> ++#include <clk/sunxi.h> + #include <dm/device-internal.h> + #include <dm/lists.h> + #include <linux/bitops.h> + #include <linux/log2.h> +-#include <asm/arch/ccu.h> + + struct sunxi_reset_priv { + void *base; +diff -ruN u-boot-2021.10/drivers/rng/Kconfig u-boot/drivers/rng/Kconfig +--- u-boot-2021.10/drivers/rng/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rng/Kconfig 2021-11-01 17:10:14.459581730 +0100 +@@ -34,14 +34,12 @@ + config RNG_STM32MP1 + bool "Enable random number generator for STM32MP1" + depends on ARCH_STM32MP +- default n + help + Enable STM32MP1 rng driver. + + config RNG_ROCKCHIP + bool "Enable random number generator for rockchip crypto rng" + depends on ARCH_ROCKCHIP && DM_RNG +- default n + help + Enable random number generator for rockchip.This driver is + support rng module of crypto v1 and crypto v2. +@@ -49,7 +47,6 @@ + config RNG_IPROC200 + bool "Broadcom iProc RNG200 random number generator" + depends on DM_RNG +- default n + help + Enable random number generator for RPI4. + endif +diff -ruN u-boot-2021.10/drivers/rtc/ds1307.c u-boot/drivers/rtc/ds1307.c +--- u-boot-2021.10/drivers/rtc/ds1307.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rtc/ds1307.c 2021-11-01 17:10:14.459581730 +0100 +@@ -43,11 +43,21 @@ + + #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ + ++/* DS1307-specific bits */ + #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ + #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ + #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ + #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ + ++/* DS1337-specific bits */ ++#define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */ ++#define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */ ++#define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */ ++ ++/* DS1340-specific bits */ ++#define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */ ++#define DS1340_CTL_BIT_OUT 0x80 /* Output Control */ ++ + /* MCP7941X-specific bits */ + #define MCP7941X_BIT_ST 0x80 + #define MCP7941X_BIT_VBATEN 0x08 +@@ -261,9 +271,25 @@ + buf[RTC_SEC_REG_ADDR]); + return -1; + } +- } +- +- if (type == m41t11) { ++ } else if (type == ds_1337) { ++ if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) { ++ printf("### Warning: RTC oscillator has stopped\n"); ++ /* clear the not oscillator enable (~EOSC) flag */ ++ buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC; ++ dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, ++ buf[RTC_CTL_REG_ADDR]); ++ return -1; ++ } ++ } else if (type == ds_1340) { ++ if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) { ++ printf("### Warning: RTC oscillator has stopped\n"); ++ /* clear the not oscillator enable (~EOSC) flag */ ++ buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC; ++ dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, ++ buf[RTC_SEC_REG_ADDR]); ++ return -1; ++ } ++ } else if (type == m41t11) { + /* clock halted? turn it on, so clock can tick. */ + if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) { + buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH; +@@ -273,9 +299,7 @@ + buf[RTC_SEC_REG_ADDR]); + goto read_rtc; + } +- } +- +- if (type == mcp794xx) { ++ } else if (type == mcp794xx) { + /* make sure that the backup battery is enabled */ + if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) { + dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, +@@ -314,18 +338,37 @@ + static int ds1307_rtc_reset(struct udevice *dev) + { + int ret; ++ enum ds_type type = dev_get_driver_data(dev); + +- /* clear Clock Halt */ ++ /* ++ * reset clock/oscillator in the seconds register: ++ * on DS1307 bit 7 enables Clock Halt (CH), ++ * on DS1340 bit 7 disables the oscillator (not EOSC) ++ * on MCP794xx bit 7 enables Start Oscillator (ST) ++ */ + ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00); + if (ret < 0) + return ret; +- ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, +- RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | +- RTC_CTL_BIT_RS0); +- if (ret < 0) +- return ret; + +- return 0; ++ if (type == ds_1307) { ++ /* Write control register in order to enable square-wave ++ * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0). ++ */ ++ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, ++ RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | ++ RTC_CTL_BIT_RS0); ++ } else if (type == ds_1337) { ++ /* Write control register in order to enable oscillator output ++ * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1). ++ */ ++ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, ++ DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1); ++ } else if (type == ds_1340 || type == mcp794xx || type == m41t11) { ++ /* Reset clock calibration, frequency test and output level. */ ++ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00); ++ } ++ ++ return ret; + } + + static int ds1307_probe(struct udevice *dev) +diff -ruN u-boot-2021.10/drivers/rtc/emul_rtc.c u-boot/drivers/rtc/emul_rtc.c +--- u-boot-2021.10/drivers/rtc/emul_rtc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rtc/emul_rtc.c 2021-11-01 17:10:14.459581730 +0100 +@@ -9,8 +9,8 @@ + #include <div64.h> + #include <dm.h> + #include <env.h> +-#include <generated/timestamp_autogenerated.h> + #include <rtc.h> ++#include <timestamp.h> + + /** + * struct emul_rtc - private data for emulated RTC driver +diff -ruN u-boot-2021.10/drivers/rtc/Kconfig u-boot/drivers/rtc/Kconfig +--- u-boot-2021.10/drivers/rtc/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rtc/Kconfig 2021-11-01 17:10:14.459581730 +0100 +@@ -136,6 +136,7 @@ + + config RTC_RX8025 + bool "Enable RX8025 driver" ++ depends on DM_RTC + help + Support for Epson RX8025 Real Time Clock devices. + +diff -ruN u-boot-2021.10/drivers/rtc/rtc-uclass.c u-boot/drivers/rtc/rtc-uclass.c +--- u-boot-2021.10/drivers/rtc/rtc-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rtc/rtc-uclass.c 2021-11-01 17:10:14.462914881 +0100 +@@ -177,7 +177,7 @@ + .name = "rtc", + .id = UCLASS_RTC, + .flags = DM_UC_FLAG_SEQ_ALIAS, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + }; +diff -ruN u-boot-2021.10/drivers/rtc/rx8025.c u-boot/drivers/rtc/rx8025.c +--- u-boot-2021.10/drivers/rtc/rx8025.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/rtc/rx8025.c 2021-11-01 17:10:14.462914881 +0100 +@@ -24,22 +24,11 @@ + #endif + /*---------------------------------------------------------------------*/ + +-#ifndef CONFIG_SYS_I2C_RTC_ADDR +-# define CONFIG_SYS_I2C_RTC_ADDR 0x32 +-#endif +- +-#ifdef CONFIG_DM_RTC +-#define DEV_TYPE struct udevice +-#else +-/* Local udevice */ +-struct ludevice { +- u8 chip; ++enum rx_model { ++ model_rx_8025, ++ model_rx_8035, + }; + +-#define DEV_TYPE struct ludevice +- +-#endif +- + /* + * RTC register addresses + */ +@@ -50,6 +39,7 @@ + #define RTC_DATE_REG_ADDR 0x04 + #define RTC_MON_REG_ADDR 0x05 + #define RTC_YR_REG_ADDR 0x06 ++#define RTC_OFFSET_REG_ADDR 0x07 + + #define RTC_CTL1_REG_ADDR 0x0e + #define RTC_CTL2_REG_ADDR 0x0f +@@ -74,39 +64,36 @@ + * address in a first cycle that is terminated by + * a STOP condition. The chips needs a 'restart' + * sequence (start sequence without a prior stop). +- * This driver has been written for a 4xx board. +- * U-Boot's 4xx i2c driver is currently not capable +- * to generate such cycles to some work arounds +- * are used. + */ + +-/* static uchar rtc_read (uchar reg); */ +-#ifdef CONFIG_DM_RTC +-/* +- * on mpc85xx based board with DM and offset len 1 +- * accessing rtc works fine. May we can drop this ? +- */ + #define rtc_read(reg) buf[(reg) & 0xf] +-#else +-#define rtc_read(reg) buf[((reg) + 1) & 0xf] +-#endif + +-static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val); ++static int rtc_write(struct udevice *dev, uchar reg, uchar val); ++ ++static int rx8025_is_osc_stopped(enum rx_model model, int ctrl2) ++{ ++ int xstp = ctrl2 & RTC_CTL2_BIT_XST; ++ /* XSTP bit has different polarity on RX-8025 vs RX-8035. ++ * RX-8025: 0 == oscillator stopped ++ * RX-8035: 1 == oscillator stopped ++ */ ++ ++ if (model == model_rx_8025) ++ xstp = !xstp; ++ ++ return xstp; ++} + + /* + * Get the current time from the RTC + */ +-static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) ++static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp) + { + int rel = 0; + uchar sec, min, hour, mday, wday, mon, year, ctl2; + uchar buf[16]; + +-#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +-#else +- if (i2c_read(dev->chip, 0, 0, buf, 16)) { +-#endif + printf("Error reading from RTC\n"); + return -EIO; + } +@@ -134,8 +121,7 @@ + printf("RTC: voltage drop detected\n"); + rel = -1; + } +- +- if (!(ctl2 & RTC_CTL2_BIT_XST)) { ++ if (rx8025_is_osc_stopped(dev->driver_data, ctl2)) { + printf("RTC: oscillator stop detected\n"); + rel = -1; + } +@@ -165,8 +151,21 @@ + /* + * Set the RTC + */ +-static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) ++static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp) + { ++ /* To work around the read/write cycle issue mentioned ++ * at the top of this file, write all the time registers ++ * in one I2C transaction ++ */ ++ u8 write_op[8]; ++ ++ /* 2412 flag must be set before doing a RTC write, ++ * otherwise the seconds and minute register ++ * will be cleared when the flag is set ++ */ ++ if (rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412)) ++ return -EIO; ++ + DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +@@ -174,50 +173,38 @@ + if (tmp->tm_year < 1970 || tmp->tm_year > 2069) + printf("WARNING: year should be between 1970 and 2069!\n"); + +- if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100))) +- return -EIO; +- +- if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon))) +- return -EIO; +- +- if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday))) +- return -EIO; +- +- if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday))) +- return -EIO; ++ write_op[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec); ++ write_op[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min); ++ write_op[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour); ++ write_op[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday); ++ write_op[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday); ++ write_op[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon); ++ write_op[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100); ++ write_op[RTC_OFFSET_REG_ADDR] = 0; + +- if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour))) +- return -EIO; +- +- if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min))) +- return -EIO; +- +- if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec))) +- return -EIO; +- +- return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); ++ return dm_i2c_write(dev, 0, &write_op[0], 8); + } + + /* + * Reset the RTC + */ +-static int rx8025_rtc_reset(DEV_TYPE *dev) ++static int rx8025_rtc_reset(struct udevice *dev) + { + uchar buf[16]; + uchar ctl2; + +-#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +-#else +- if (i2c_read(dev->chip, 0, 0, buf, 16)) { +-#endif + printf("Error reading from RTC\n"); + return -EIO; + } + + ctl2 = rtc_read(RTC_CTL2_REG_ADDR); + ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); +- ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; ++ ++ if (dev->driver_data == model_rx_8035) ++ ctl2 &= ~(RTC_CTL2_BIT_XST); ++ else ++ ctl2 |= RTC_CTL2_BIT_XST; + + return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2); + } +@@ -225,17 +212,16 @@ + /* + * Helper functions + */ +-static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) ++static int rtc_write(struct udevice *dev, uchar reg, uchar val) + { +- uchar buf[2]; +- buf[0] = reg << 4; +- buf[1] = val; +- +-#ifdef CONFIG_DM_RTC +- if (dm_i2c_write(dev, 0, buf, 2)) { +-#else +- if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) { +-#endif ++ /* The RX8025/RX8035 uses the top 4 bits of the ++ * 'offset' byte as the start register address, ++ * and the bottom 4 bits as a 'transfer' mode setting ++ * (only applicable for reads) ++ */ ++ u8 offset = (reg << 4); ++ ++ if (dm_i2c_reg_write(dev, offset, val)) { + printf("Error writing to RTC\n"); + return -EIO; + } +@@ -243,7 +229,6 @@ + return 0; + } + +-#ifdef CONFIG_DM_RTC + static int rx8025_probe(struct udevice *dev) + { + uchar buf[16]; +@@ -265,42 +250,15 @@ + }; + + static const struct udevice_id rx8025_rtc_ids[] = { +- { .compatible = "epson,rx8025" }, ++ { .compatible = "epson,rx8025", .data = model_rx_8025 }, ++ { .compatible = "epson,rx8035", .data = model_rx_8035 }, + { } + }; + +-U_BOOT_DRIVER(rx8010sj_rtc) = { ++U_BOOT_DRIVER(rx8025_rtc) = { + .name = "rx8025_rtc", + .id = UCLASS_RTC, + .probe = rx8025_probe, + .of_match = rx8025_rtc_ids, + .ops = &rx8025_rtc_ops, + }; +-#else +-int rtc_get(struct rtc_time *tm) +-{ +- struct ludevice dev = { +- .chip = CONFIG_SYS_I2C_RTC_ADDR, +- }; +- +- return rx8025_rtc_get(&dev, tm); +-} +- +-int rtc_set(struct rtc_time *tm) +-{ +- struct ludevice dev = { +- .chip = CONFIG_SYS_I2C_RTC_ADDR, +- }; +- +- return rx8025_rtc_set(&dev, tm); +-} +- +-void rtc_reset(void) +-{ +- struct ludevice dev = { +- .chip = CONFIG_SYS_I2C_RTC_ADDR, +- }; +- +- rx8025_rtc_reset(&dev); +-} +-#endif +diff -ruN u-boot-2021.10/drivers/scsi/Makefile u-boot/drivers/scsi/Makefile +--- u-boot-2021.10/drivers/scsi/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/scsi/Makefile 2021-11-01 17:10:14.462914881 +0100 +@@ -9,7 +9,7 @@ + endif + + ifdef CONFIG_SPL_BUILD +-ifdef CONFIG_SPL_SATA_SUPPORT ++ifdef CONFIG_SPL_SATA + obj-$(CONFIG_DM_SCSI) += scsi-uclass.o + obj-$(CONFIG_SCSI) += scsi.o + endif +diff -ruN u-boot-2021.10/drivers/serial/Kconfig u-boot/drivers/serial/Kconfig +--- u-boot-2021.10/drivers/serial/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/Kconfig 2021-11-01 17:10:14.462914881 +0100 +@@ -2,7 +2,18 @@ + # Serial device configuration + # + +-menu "Serial drivers" ++menuconfig SERIAL ++ bool "Serial" ++ default y ++ help ++ Enable support for serial drivers. This allows use of a serial UART ++ for displaying messages while U-Boot is running. It also brings in ++ printf() and panic() functions. This should normally be enabled ++ unless there are space reasons not to. If you just need to disable ++ the console you can adjust the stdout environment variable or use ++ SILENT_CONSOLE. ++ ++if SERIAL + + config BAUDRATE + int "Default baudrate" +@@ -137,7 +148,6 @@ + config SERIAL_PROBE_ALL + bool "Probe all available serial devices" + depends on DM_SERIAL +- default n + help + The serial subsystem only probes for a single serial device, + but does not probe for other remaining serial devices. +@@ -270,6 +280,14 @@ + U-Boot when running on top of EFI (Extensive Firmware Interface). + This is a type of BIOS used by PCs. + ++config DEBUG_SBI_CONSOLE ++ bool "SBI" ++ depends on SBI_V01 ++ help ++ Select this to enable a debug console which calls back to SBI to ++ output to the console. This can be useful for early debugging of ++ U-Boot when running on top of SBI (Supervisor Binary Interface). ++ + config DEBUG_UART_S5P + bool "Samsung S5P" + depends on ARCH_EXYNOS || ARCH_S5PC1XX +@@ -432,6 +450,7 @@ + config DEBUG_UART_BASE + hex "Base address of UART" + depends on DEBUG_UART ++ default 0 if DEBUG_SBI_CONSOLE + default 0 if DEBUG_UART_SANDBOX + help + This is the base address of your UART for memory-mapped UARTs. +@@ -442,6 +461,7 @@ + config DEBUG_UART_CLOCK + int "UART input clock" + depends on DEBUG_UART ++ default 0 if DEBUG_SBI_CONSOLE + default 0 if DEBUG_UART_SANDBOX + default 0 if DEBUG_MVEBU_A3700_UART + help +@@ -621,7 +641,6 @@ + + config MVEBU_A3700_UART + bool "UART support for Armada 3700" +- default n + help + Choose this option to add support for UART driver on the Marvell + Armada 3700 SoC. The base address is configured via DT. +@@ -636,8 +655,7 @@ + + config MXC_UART + bool "IMX serial port support" +- depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ +- || MX5 || MX6 || MX7 || IMX8M ++ depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M + help + If you have a machine based on a Motorola IMX CPU you + can enable its onboard serial port by enabling this option. +@@ -939,4 +957,4 @@ + depends on MPC8XX_CONS + default 0 + +-endmenu ++endif +diff -ruN u-boot-2021.10/drivers/serial/Makefile u-boot/drivers/serial/Makefile +--- u-boot-2021.10/drivers/serial/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/Makefile 2021-11-01 17:10:14.462914881 +0100 +@@ -36,6 +36,7 @@ + obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o + obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o + obj-$(CONFIG_CORTINA_UART) += serial_cortina.o ++obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o + obj-$(CONFIG_EFI_APP) += serial_efi.o + obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o + obj-$(CONFIG_MCFUART) += serial_mcf.o +diff -ruN u-boot-2021.10/drivers/serial/ns16550.c u-boot/drivers/serial/ns16550.c +--- u-boot-2021.10/drivers/serial/ns16550.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/ns16550.c 2021-11-01 17:10:14.462914881 +0100 +@@ -41,7 +41,7 @@ + #endif + #endif /* !CONFIG_DM_SERIAL */ + +-#if defined(CONFIG_SOC_KEYSTONE) ++#if defined(CONFIG_ARCH_KEYSTONE) + #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 + #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) + #undef UART_MCRVAL +@@ -267,7 +267,7 @@ + /* /16 is proper to hit 115200 with 48MHz */ + serial_out(0, &com_port->mdr1); + #endif +-#if defined(CONFIG_SOC_KEYSTONE) ++#if defined(CONFIG_ARCH_KEYSTONE) + serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); + #endif + } +@@ -533,7 +533,7 @@ + }; + #endif + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + int ns16550_serial_of_to_plat(struct udevice *dev) + { + struct ns16550_plat *plat = dev_get_plat(dev); +@@ -588,7 +588,7 @@ + .getinfo = ns16550_serial_getinfo, + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /* + * Please consider existing compatible strings before adding a new + * one to keep this table compact. Or you may add a generic "ns16550" +@@ -602,7 +602,7 @@ + { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + {} + }; +-#endif /* OF_CONTROL && !OF_PLATDATA */ ++#endif /* OF_REAL */ + + #if CONFIG_IS_ENABLED(SERIAL_PRESENT) + +@@ -611,7 +611,7 @@ + U_BOOT_DRIVER(ns16550_serial) = { + .name = "ns16550_serial", + .id = UCLASS_SERIAL, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = ns16550_serial_ids, + .of_to_plat = ns16550_serial_of_to_plat, + .plat_auto = sizeof(struct ns16550_plat), +diff -ruN u-boot-2021.10/drivers/serial/sandbox.c u-boot/drivers/serial/sandbox.c +--- u-boot-2021.10/drivers/serial/sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/sandbox.c 2021-11-01 17:10:14.462914881 +0100 +@@ -237,7 +237,7 @@ + .flags = DM_FLAG_PRE_RELOC, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct sandbox_serial_plat platdata_non_fdt = { + .colour = -1, + }; +diff -ruN u-boot-2021.10/drivers/serial/serial_msm.c u-boot/drivers/serial/serial_msm.c +--- u-boot-2021.10/drivers/serial/serial_msm.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial_msm.c 2021-11-01 17:10:14.466248032 +0100 +@@ -233,7 +233,7 @@ + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + +- priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ++ priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE); + + return 0; +diff -ruN u-boot-2021.10/drivers/serial/serial_mt7620.c u-boot/drivers/serial/serial_mt7620.c +--- u-boot-2021.10/drivers/serial/serial_mt7620.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial_mt7620.c 2021-11-01 17:10:14.466248032 +0100 +@@ -145,7 +145,7 @@ + return 0; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int mt7620_serial_of_to_plat(struct udevice *dev) + { + struct mt7620_serial_plat *plat = dev_get_plat(dev); +@@ -200,7 +200,7 @@ + U_BOOT_DRIVER(serial_mt7620) = { + .name = "serial_mt7620", + .id = UCLASS_SERIAL, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = mt7620_serial_ids, + .of_to_plat = mt7620_serial_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/serial/serial_omap.c u-boot/drivers/serial/serial_omap.c +--- u-boot-2021.10/drivers/serial/serial_omap.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial_omap.c 2021-11-01 17:10:14.466248032 +0100 +@@ -98,7 +98,7 @@ + + #if CONFIG_IS_ENABLED(DM_SERIAL) + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int omap_serial_of_to_plat(struct udevice *dev) + { + struct ns16550_plat *plat = dev_get_plat(dev); +@@ -149,13 +149,13 @@ + { .compatible = "ti,am654-uart", }, + {} + }; +-#endif /* OF_CONTROL && !OF_PLATDATA */ ++#endif /* OF_REAL */ + + #if CONFIG_IS_ENABLED(SERIAL_PRESENT) + U_BOOT_DRIVER(omap_serial) = { + .name = "omap_serial", + .id = UCLASS_SERIAL, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = omap_serial_ids, + .of_to_plat = omap_serial_of_to_plat, + .plat_auto = sizeof(struct ns16550_plat), +diff -ruN u-boot-2021.10/drivers/serial/serial_sbi.c u-boot/drivers/serial/serial_sbi.c +--- u-boot-2021.10/drivers/serial/serial_sbi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/serial/serial_sbi.c 2021-11-01 17:10:14.466248032 +0100 +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <debug_uart.h> ++#include <asm/sbi.h> ++ ++static inline void _debug_uart_init(void) ++{ ++} ++ ++static inline void _debug_uart_putc(int c) ++{ ++ if (CONFIG_IS_ENABLED(RISCV_SMODE)) ++ sbi_console_putchar(c); ++} ++ ++DEBUG_UART_FUNCS +diff -ruN u-boot-2021.10/drivers/serial/serial_sti_asc.c u-boot/drivers/serial/serial_sti_asc.c +--- u-boot-2021.10/drivers/serial/serial_sti_asc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial_sti_asc.c 2021-11-01 17:10:14.466248032 +0100 +@@ -209,4 +209,3 @@ + .probe = sti_asc_serial_probe, + .priv_auto = sizeof(struct sti_asc_serial), + }; +- +diff -ruN u-boot-2021.10/drivers/serial/serial-uclass.c u-boot/drivers/serial/serial-uclass.c +--- u-boot-2021.10/drivers/serial/serial-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial-uclass.c 2021-11-01 17:10:14.462914881 +0100 +@@ -27,10 +27,6 @@ + */ + static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; + +-#if !CONFIG_VAL(SYS_MALLOC_F_LEN) +-#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work" +-#endif +- + #if CONFIG_IS_ENABLED(SERIAL_PRESENT) + static int serial_check_stdout(const void *blob, struct udevice **devp) + { +diff -ruN u-boot-2021.10/drivers/serial/serial_xen.c u-boot/drivers/serial/serial_xen.c +--- u-boot-2021.10/drivers/serial/serial_xen.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/serial/serial_xen.c 2021-11-01 17:10:14.466248032 +0100 +@@ -180,4 +180,3 @@ + .flags = DM_FLAG_PRE_RELOC, + #endif + }; +- +diff -ruN u-boot-2021.10/drivers/spi/altera_spi.c u-boot/drivers/spi/altera_spi.c +--- u-boot-2021.10/drivers/spi/altera_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/altera_spi.c 2021-11-01 17:10:14.472914334 +0100 +@@ -19,9 +19,7 @@ + #define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) + #define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) + +-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL +-#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff +-#endif ++#define ALTERA_SPI_IDLE_VAL 0xff + + struct altera_spi_regs { + u32 rxdata; +@@ -119,7 +117,7 @@ + if (txp) + data = *txp++; + else +- data = CONFIG_ALTERA_SPI_IDLE_VAL; ++ data = ALTERA_SPI_IDLE_VAL; + + debug("%s: tx:%x ", __func__, data); + writel(data, ®s->txdata); +diff -ruN u-boot-2021.10/drivers/spi/atcspi200_spi.c u-boot/drivers/spi/atcspi200_spi.c +--- u-boot-2021.10/drivers/spi/atcspi200_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/atcspi200_spi.c 2021-11-01 17:10:14.472914334 +0100 +@@ -81,7 +81,7 @@ + unsigned int freq; + ulong clock; + unsigned int mode; +- u8 num_cs; ++ u8 num_cs; + unsigned int mtiming; + size_t cmd_len; + u8 cmd_buf[16]; +diff -ruN u-boot-2021.10/drivers/spi/cf_spi.c u-boot/drivers/spi/cf_spi.c +--- u-boot-2021.10/drivers/spi/cf_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/cf_spi.c 2021-11-01 17:10:14.472914334 +0100 +@@ -384,7 +384,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int coldfire_dspi_of_to_plat(struct udevice *bus) + { + fdt_addr_t addr; +@@ -450,7 +450,7 @@ + U_BOOT_DRIVER(coldfire_spi) = { + .name = "spi_coldfire", + .id = UCLASS_SPI, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = coldfire_spi_ids, + .of_to_plat = coldfire_dspi_of_to_plat, + .plat_auto = sizeof(struct coldfire_spi_plat), +diff -ruN u-boot-2021.10/drivers/spi/davinci_spi.c u-boot/drivers/spi/davinci_spi.c +--- u-boot-2021.10/drivers/spi/davinci_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/davinci_spi.c 2021-11-01 17:10:14.472914334 +0100 +@@ -391,7 +391,7 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int davinci_ofdata_to_platadata(struct udevice *bus) + { + struct davinci_spi_plat *plat = dev_get_plat(bus); +@@ -418,7 +418,7 @@ + U_BOOT_DRIVER(davinci_spi) = { + .name = "davinci_spi", + .id = UCLASS_SPI, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = davinci_spi_ids, + .of_to_plat = davinci_ofdata_to_platadata, + .plat_auto = sizeof(struct davinci_spi_plat), +diff -ruN u-boot-2021.10/drivers/spi/fsl_espi.c u-boot/drivers/spi/fsl_espi.c +--- u-boot-2021.10/drivers/spi/fsl_espi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/fsl_espi.c 2021-11-01 17:10:14.472914334 +0100 +@@ -541,7 +541,7 @@ + .set_mode = fsl_espi_set_mode, + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int fsl_espi_of_to_plat(struct udevice *bus) + { + fdt_addr_t addr; +@@ -572,7 +572,7 @@ + U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = fsl_espi_ids, + .of_to_plat = fsl_espi_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/spi/ich.c u-boot/drivers/spi/ich.c +--- u-boot-2021.10/drivers/spi/ich.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/ich.c 2021-11-01 17:10:14.476247485 +0100 +@@ -604,7 +604,7 @@ + return ret; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /** + * ich_spi_get_basics() - Get basic information about the ICH device + * +@@ -672,7 +672,7 @@ + uint *map_sizep, uint *offsetp) + { + pci_dev_t spi_bdf; +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + if (device_is_on_pci_bus(bus)) { + struct pci_child_plat *pplat; + +@@ -940,7 +940,7 @@ + { + struct ich_spi_plat *plat = dev_get_plat(dev); + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + struct ich_spi_priv *priv = dev_get_priv(dev); + int ret; + +diff -ruN u-boot-2021.10/drivers/spi/Kconfig u-boot/drivers/spi/Kconfig +--- u-boot-2021.10/drivers/spi/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/Kconfig 2021-11-01 17:10:14.472914334 +0100 +@@ -376,7 +376,7 @@ + + config SPI_SUNXI + bool "Allwinner SoC SPI controllers" +- default ARCH_SUNXI ++ default (ARCH_SUNXI || TARGET_SUNXI) + help + Enable the Allwinner SoC SPi controller driver. + +diff -ruN u-boot-2021.10/drivers/spi/mxc_spi.c u-boot/drivers/spi/mxc_spi.c +--- u-boot-2021.10/drivers/spi/mxc_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/mxc_spi.c 2021-11-01 17:10:14.476247485 +0100 +@@ -23,7 +23,7 @@ + DECLARE_GLOBAL_DATA_PTR; + + /* MX35 and older is CSPI */ +-#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35) ++#if defined(CONFIG_MX31) + #define MXC_CSPI + struct cspi_regs { + u32 rxdata; +@@ -48,17 +48,10 @@ + #define MXC_CSPICTRL_RXOVF BIT(6) + #define MXC_CSPIPERIOD_32KHZ BIT(15) + #define MAX_SPI_BYTES 4 +-#if defined(CONFIG_MX25) || defined(CONFIG_MX35) +-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +-#define MXC_CSPICTRL_TC BIT(7) +-#define MXC_CSPICTRL_MAXBITS 0xfff +-#else /* MX31 */ + #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) + #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) + #define MXC_CSPICTRL_TC BIT(8) + #define MXC_CSPICTRL_MAXBITS 0x1f +-#endif + + #else /* MX51 and newer is ECSPI */ + #define MXC_ECSPI +@@ -211,9 +204,6 @@ + MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | + MXC_CSPICTRL_DATARATE(div) | + MXC_CSPICTRL_EN | +-#ifdef CONFIG_MX35 +- MXC_CSPICTRL_SSCTL | +-#endif + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) +diff -ruN u-boot-2021.10/drivers/spi/mxs_spi.c u-boot/drivers/spi/mxs_spi.c +--- u-boot-2021.10/drivers/spi/mxs_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/mxs_spi.c 2021-11-01 17:10:14.476247485 +0100 +@@ -440,7 +440,7 @@ + */ + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int mxs_of_to_plat(struct udevice *bus) + { + struct mxs_spi_plat *plat = dev_get_plat(bus); +@@ -483,7 +483,7 @@ + U_BOOT_DRIVER(fsl_imx23_spi) = { + .name = "fsl_imx23_spi", + .id = UCLASS_SPI, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = mxs_spi_ids, + .of_to_plat = mxs_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/spi/omap3_spi.c u-boot/drivers/spi/omap3_spi.c +--- u-boot-2021.10/drivers/spi/omap3_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/omap3_spi.c 2021-11-01 17:10:14.476247485 +0100 +@@ -481,7 +481,7 @@ + */ + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static struct omap2_mcspi_platform_config omap2_pdata = { + .regs_offset = 0, + }; +@@ -516,7 +516,7 @@ + .name = "omap3_spi", + .id = UCLASS_SPI, + .flags = DM_FLAG_PRE_RELOC, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = omap3_spi_ids, + .of_to_plat = omap3_spi_of_to_plat, + .plat_auto = sizeof(struct omap3_spi_plat), +diff -ruN u-boot-2021.10/drivers/spi/pl022_spi.c u-boot/drivers/spi/pl022_spi.c +--- u-boot-2021.10/drivers/spi/pl022_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/pl022_spi.c 2021-11-01 17:10:14.476247485 +0100 +@@ -286,7 +286,7 @@ + .cs_info = pl022_cs_info, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int pl022_spi_of_to_plat(struct udevice *bus) + { + struct pl022_spi_pdata *plat = dev_get_plat(bus); +@@ -315,7 +315,7 @@ + U_BOOT_DRIVER(pl022_spi) = { + .name = "pl022_spi", + .id = UCLASS_SPI, +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .of_match = pl022_spi_ids, + .of_to_plat = pl022_spi_of_to_plat, + #endif +diff -ruN u-boot-2021.10/drivers/spi/rk_spi.c u-boot/drivers/spi/rk_spi.c +--- u-boot-2021.10/drivers/spi/rk_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/rk_spi.c 2021-11-01 17:10:14.476247485 +0100 +@@ -183,7 +183,7 @@ + + plat->base = dtplat->reg[0]; + plat->frequency = 20000000; +- ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); ++ ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; + +@@ -193,32 +193,32 @@ + + static int rockchip_spi_of_to_plat(struct udevice *bus) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_spi_plat *plat = dev_get_plat(bus); + struct rockchip_spi_priv *priv = dev_get_priv(bus); + int ret; + +- plat->base = dev_read_addr(bus); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ plat->base = dev_read_addr(bus); + +- ret = clk_get_by_index(bus, 0, &priv->clk); +- if (ret < 0) { +- debug("%s: Could not get clock for %s: %d\n", __func__, +- bus->name, ret); +- return ret; ++ ret = clk_get_by_index(bus, 0, &priv->clk); ++ if (ret < 0) { ++ debug("%s: Could not get clock for %s: %d\n", __func__, ++ bus->name, ret); ++ return ret; ++ } ++ ++ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", ++ 50000000); ++ plat->deactivate_delay_us = ++ dev_read_u32_default(bus, "spi-deactivate-delay", 0); ++ plat->activate_delay_us = ++ dev_read_u32_default(bus, "spi-activate-delay", 0); ++ ++ debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", ++ __func__, (uint)plat->base, plat->frequency, ++ plat->deactivate_delay_us); + } + +- plat->frequency = +- dev_read_u32_default(bus, "spi-max-frequency", 50000000); +- plat->deactivate_delay_us = +- dev_read_u32_default(bus, "spi-deactivate-delay", 0); +- plat->activate_delay_us = +- dev_read_u32_default(bus, "spi-activate-delay", 0); +- +- debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", +- __func__, (uint)plat->base, plat->frequency, +- plat->deactivate_delay_us); +-#endif +- + return 0; + } + +diff -ruN u-boot-2021.10/drivers/spi/spi-sunxi.c u-boot/drivers/spi/spi-sunxi.c +--- u-boot-2021.10/drivers/spi/spi-sunxi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/spi-sunxi.c 2021-11-01 17:10:14.479580636 +0100 +@@ -30,9 +30,9 @@ + #include <asm/global_data.h> + #include <dm/device_compat.h> + #include <linux/bitops.h> ++#include <linux/log2.h> + + #include <asm/bitops.h> +-#include <asm/gpio.h> + #include <asm/io.h> + + #include <linux/iopoll.h> +@@ -78,7 +78,7 @@ + #define SUN4I_SPI_DEFAULT_RATE 1000000 + #define SUN4I_SPI_TIMEOUT_US 1000000 + +-#define SPI_REG(priv, reg) ((priv)->base + \ ++#define SPI_REG(priv, reg) (void *)((priv)->base + \ + (priv)->variant->regs[reg]) + #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit]) + #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \ +@@ -180,86 +180,6 @@ + writel(reg, SPI_REG(priv, SPI_TCR)); + } + +-static int sun4i_spi_parse_pins(struct udevice *dev) +-{ +- const void *fdt = gd->fdt_blob; +- const char *pin_name; +- const fdt32_t *list; +- u32 phandle; +- int drive, pull = 0, pin, i; +- int offset; +- int size; +- +- list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); +- if (!list) { +- printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n"); +- return -EINVAL; +- } +- +- while (size) { +- phandle = fdt32_to_cpu(*list++); +- size -= sizeof(*list); +- +- offset = fdt_node_offset_by_phandle(fdt, phandle); +- if (offset < 0) +- return offset; +- +- drive = fdt_getprop_u32_default_node(fdt, offset, 0, +- "drive-strength", 0); +- if (drive) { +- if (drive <= 10) +- drive = 0; +- else if (drive <= 20) +- drive = 1; +- else if (drive <= 30) +- drive = 2; +- else +- drive = 3; +- } else { +- drive = fdt_getprop_u32_default_node(fdt, offset, 0, +- "allwinner,drive", +- 0); +- drive = min(drive, 3); +- } +- +- if (fdt_get_property(fdt, offset, "bias-disable", NULL)) +- pull = 0; +- else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) +- pull = 1; +- else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) +- pull = 2; +- else +- pull = fdt_getprop_u32_default_node(fdt, offset, 0, +- "allwinner,pull", +- 0); +- pull = min(pull, 2); +- +- for (i = 0; ; i++) { +- pin_name = fdt_stringlist_get(fdt, offset, +- "pins", i, NULL); +- if (!pin_name) { +- pin_name = fdt_stringlist_get(fdt, offset, +- "allwinner,pins", +- i, NULL); +- if (!pin_name) +- break; +- } +- +- pin = name_to_gpio(pin_name); +- if (pin < 0) +- break; +- +- if (IS_ENABLED(CONFIG_MACH_SUN50I)) +- sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0); +- else +- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); +- sunxi_gpio_set_drv(pin, drive); +- sunxi_gpio_set_pull(pin, pull); +- } +- } +- return 0; +-} +- + static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) + { + struct sun4i_spi_priv *priv = dev_get_priv(dev); +@@ -443,7 +363,7 @@ + reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + } else { +- div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); ++ div = ilog2(SUN4I_SPI_MAX_RATE) - ilog2(speed); + reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR1(div); + } +@@ -506,8 +426,6 @@ + return ret; + } + +- sun4i_spi_parse_pins(bus); +- + priv->variant = plat->variant; + priv->base = plat->base; + priv->freq = plat->max_hz; +@@ -623,6 +541,10 @@ + .compatible = "allwinner,sun8i-h3-spi", + .data = (ulong)&sun8i_h3_spi_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-r329-spi", ++ .data = (ulong)&sun8i_h3_spi_variant, ++ }, + { /* sentinel */ } + }; + +diff -ruN u-boot-2021.10/drivers/spi/spi-uclass.c u-boot/drivers/spi/spi-uclass.c +--- u-boot-2021.10/drivers/spi/spi-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/spi/spi-uclass.c 2021-11-01 17:10:14.479580636 +0100 +@@ -162,7 +162,7 @@ + return ret; + } + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static int spi_child_post_bind(struct udevice *dev) + { + struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); +@@ -176,11 +176,11 @@ + + static int spi_post_probe(struct udevice *bus) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct dm_spi_bus *spi = dev_get_uclass_priv(bus); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct dm_spi_bus *spi = dev_get_uclass_priv(bus); + +- spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); +-#endif ++ spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); ++ } + #if defined(CONFIG_NEEDS_MANUAL_RELOC) + struct dm_spi_ops *ops = spi_get_ops(bus); + static int reloc_done; +@@ -531,7 +531,7 @@ + .id = UCLASS_SPI, + .name = "spi", + .flags = DM_UC_FLAG_SEQ_ALIAS, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + .post_probe = spi_post_probe, +@@ -539,7 +539,7 @@ + .per_device_auto = sizeof(struct dm_spi_bus), + .per_child_auto = sizeof(struct spi_slave), + .per_child_plat_auto = sizeof(struct dm_spi_slave_plat), +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .child_post_bind = spi_child_post_bind, + #endif + }; +diff -ruN u-boot-2021.10/drivers/sysreset/Kconfig u-boot/drivers/sysreset/Kconfig +--- u-boot-2021.10/drivers/sysreset/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/Kconfig 2021-11-01 17:10:14.482913787 +0100 +@@ -85,6 +85,18 @@ + Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware + must be running on your system. + ++config SYSRESET_SBI ++ bool "Enable support for SBI System Reset" ++ depends on RISCV_SMODE && SBI_V02 ++ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF ++ help ++ Enable system reset and poweroff via the SBI system reset extension. ++ The extension was introduced in version 0.3 of the SBI specification. ++ ++ If the SBI implementation provides the extension, is board specific. ++ The RISC-V platform specification mandates the extension for rich ++ operating system platforms. ++ + config SYSRESET_SOCFPGA + bool "Enable support for Intel SOCFPGA family" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) +@@ -106,8 +118,6 @@ + This enables the system reset driver support over TI System Control + Interface available on some new TI's SoCs. + +-endif +- + config SYSRESET_SYSCON + bool "Enable support for mfd syscon reboot driver" + select REGMAP +@@ -121,12 +131,21 @@ + help + Reboot support for generic watchdog reset. + ++config SYSRESET_WATCHDOG_AUTO ++ bool "Automatically register first watchdog with sysreset" ++ depends on SYSRESET_WATCHDOG ++ help ++ If enabled, the first watchdog (as selected by the watchdog uclass) ++ will automatically be registered with the watchdog reboot driver. ++ + config SYSRESET_RESETCTL + bool "Enable support for reset controller reboot driver" + select DM_RESET + help + Reboot support using generic reset controller. + ++endif ++ + config SYSRESET_X86 + bool "Enable support for x86 processor reboot driver" + depends on X86 +diff -ruN u-boot-2021.10/drivers/sysreset/Makefile u-boot/drivers/sysreset/Makefile +--- u-boot-2021.10/drivers/sysreset/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/Makefile 2021-11-01 17:10:14.482913787 +0100 +@@ -13,6 +13,7 @@ + obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o + obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o + obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o ++obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o + obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o + obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o + obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o +diff -ruN u-boot-2021.10/drivers/sysreset/sysreset_resetctl.c u-boot/drivers/sysreset/sysreset_resetctl.c +--- u-boot-2021.10/drivers/sysreset/sysreset_resetctl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/sysreset_resetctl.c 2021-11-01 17:10:14.482913787 +0100 +@@ -26,7 +26,7 @@ + .request = resetctl_reboot_request, + }; + +-int resetctl_reboot_probe(struct udevice *dev) ++static int resetctl_reboot_probe(struct udevice *dev) + { + struct resetctl_reboot_priv *priv = dev_get_priv(dev); + +diff -ruN u-boot-2021.10/drivers/sysreset/sysreset_sandbox.c u-boot/drivers/sysreset/sysreset_sandbox.c +--- u-boot-2021.10/drivers/sysreset/sysreset_sandbox.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/sysreset_sandbox.c 2021-11-01 17:10:14.482913787 +0100 +@@ -133,7 +133,7 @@ + .ops = &sandbox_warm_sysreset_ops, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + /* This is here in case we don't have a device tree */ + U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = { + .name = "sysreset_sandbox", +diff -ruN u-boot-2021.10/drivers/sysreset/sysreset_sbi.c u-boot/drivers/sysreset/sysreset_sbi.c +--- u-boot-2021.10/drivers/sysreset/sysreset_sbi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/sysreset/sysreset_sbi.c 2021-11-01 17:10:14.482913787 +0100 +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2021, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <errno.h> ++#include <log.h> ++#include <sysreset.h> ++#include <asm/sbi.h> ++ ++static enum sbi_srst_reset_type reset_type_map[SYSRESET_COUNT] = { ++ [SYSRESET_WARM] = SBI_SRST_RESET_TYPE_WARM_REBOOT, ++ [SYSRESET_COLD] = SBI_SRST_RESET_TYPE_COLD_REBOOT, ++ [SYSRESET_POWER] = SBI_SRST_RESET_TYPE_COLD_REBOOT, ++ [SYSRESET_POWER_OFF] = SBI_SRST_RESET_TYPE_SHUTDOWN, ++}; ++ ++static int sbi_sysreset_request(struct udevice *dev, enum sysreset_t type) ++{ ++ enum sbi_srst_reset_type reset_type; ++ ++ reset_type = reset_type_map[type]; ++ sbi_srst_reset(reset_type, SBI_SRST_RESET_REASON_NONE); ++ ++ return -EINPROGRESS; ++} ++ ++static int sbi_sysreset_probe(struct udevice *dev) ++{ ++ long have_reset; ++ ++ have_reset = sbi_probe_extension(SBI_EXT_SRST); ++ if (have_reset) ++ return 0; ++ ++ log_warning("SBI has no system reset extension\n"); ++ return -ENOENT; ++} ++ ++static struct sysreset_ops sbi_sysreset_ops = { ++ .request = sbi_sysreset_request, ++}; ++ ++U_BOOT_DRIVER(sbi_sysreset) = { ++ .name = "sbi-sysreset", ++ .id = UCLASS_SYSRESET, ++ .ops = &sbi_sysreset_ops, ++ .probe = sbi_sysreset_probe, ++}; +diff -ruN u-boot-2021.10/drivers/sysreset/sysreset_syscon.c u-boot/drivers/sysreset/sysreset_syscon.c +--- u-boot-2021.10/drivers/sysreset/sysreset_syscon.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/sysreset_syscon.c 2021-11-01 17:10:14.482913787 +0100 +@@ -39,7 +39,7 @@ + .request = syscon_reboot_request, + }; + +-int syscon_reboot_probe(struct udevice *dev) ++static int syscon_reboot_probe(struct udevice *dev) + { + struct syscon_reboot_priv *priv = dev_get_priv(dev); + int err; +diff -ruN u-boot-2021.10/drivers/sysreset/sysreset_watchdog.c u-boot/drivers/sysreset/sysreset_watchdog.c +--- u-boot-2021.10/drivers/sysreset/sysreset_watchdog.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/sysreset/sysreset_watchdog.c 2021-11-01 17:10:14.482913787 +0100 +@@ -5,20 +5,22 @@ + + #include <common.h> + #include <dm.h> ++#include <dm/device-internal.h> + #include <errno.h> ++#include <malloc.h> + #include <sysreset.h> + #include <wdt.h> + +-struct wdt_reboot_priv { ++struct wdt_reboot_plat { + struct udevice *wdt; + }; + + static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type) + { +- struct wdt_reboot_priv *priv = dev_get_priv(dev); ++ struct wdt_reboot_plat *plat = dev_get_plat(dev); + int ret; + +- ret = wdt_expire_now(priv->wdt, 0); ++ ret = wdt_expire_now(plat->wdt, 0); + if (ret) + return ret; + +@@ -29,13 +31,13 @@ + .request = wdt_reboot_request, + }; + +-int wdt_reboot_probe(struct udevice *dev) ++static int wdt_reboot_of_to_plat(struct udevice *dev) + { +- struct wdt_reboot_priv *priv = dev_get_priv(dev); ++ struct wdt_reboot_plat *plat = dev_get_plat(dev); + int err; + + err = uclass_get_device_by_phandle(UCLASS_WDT, dev, +- "wdt", &priv->wdt); ++ "wdt", &plat->wdt); + if (err) { + pr_err("unable to find wdt device\n"); + return err; +@@ -53,7 +55,29 @@ + .name = "wdt_reboot", + .id = UCLASS_SYSRESET, + .of_match = wdt_reboot_ids, ++ .of_to_plat = wdt_reboot_of_to_plat, ++ .plat_auto = sizeof(struct wdt_reboot_plat), + .ops = &wdt_reboot_ops, +- .priv_auto = sizeof(struct wdt_reboot_priv), +- .probe = wdt_reboot_probe, + }; ++ ++#if IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO) ++int sysreset_register_wdt(struct udevice *dev) ++{ ++ struct wdt_reboot_plat *plat = malloc(sizeof(*plat)); ++ int ret; ++ ++ if (!plat) ++ return -ENOMEM; ++ ++ plat->wdt = dev; ++ ++ ret = device_bind(dev, DM_DRIVER_GET(wdt_reboot), ++ dev->name, plat, ofnode_null(), NULL); ++ if (ret) { ++ free(plat); ++ return ret; ++ } ++ ++ return 0; ++} ++#endif +diff -ruN u-boot-2021.10/drivers/thermal/imx_tmu.c u-boot/drivers/thermal/imx_tmu.c +--- u-boot-2021.10/drivers/thermal/imx_tmu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/thermal/imx_tmu.c 2021-11-01 17:10:14.486246938 +0100 +@@ -22,8 +22,8 @@ + DECLARE_GLOBAL_DATA_PTR; + + #define SITES_MAX 16 +-#define FLAGS_VER2 0x1 +-#define FLAGS_VER3 0x2 ++#define FLAGS_VER2 0x1 ++#define FLAGS_VER3 0x2 + + #define TMR_DISABLE 0x0 + #define TMR_ME 0x80000000 +diff -ruN u-boot-2021.10/drivers/timer/atmel_pit_timer.c u-boot/drivers/timer/atmel_pit_timer.c +--- u-boot-2021.10/drivers/timer/atmel_pit_timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/timer/atmel_pit_timer.c 2021-11-01 17:10:14.486246938 +0100 +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright (C) 2017 Microchip Corporation +- * Wenyou.Yang <wenyou.yang@microchip.com> ++ * Wenyou.Yang <wenyou.yang@microchip.com> + */ + + #include <common.h> +diff -ruN u-boot-2021.10/drivers/timer/rockchip_timer.c u-boot/drivers/timer/rockchip_timer.c +--- u-boot-2021.10/drivers/timer/rockchip_timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/timer/rockchip_timer.c 2021-11-01 17:10:14.486246938 +0100 +@@ -55,8 +55,7 @@ + /* The timer is available */ + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- } else if (ret == -EAGAIN) { ++ } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) { + /* We have been called so early that the DM is not ready,... */ + ofnode node = offset_to_ofnode(-1); + struct rk_timer *timer = NULL; +@@ -79,7 +78,6 @@ + debug("%s: could not read clock-frequency\n", __func__); + return 0; + } +-#endif + } else { + return 0; + } +@@ -100,13 +98,13 @@ + + static int rockchip_clk_of_to_plat(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct rockchip_timer_priv *priv = dev_get_priv(dev); ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct rockchip_timer_priv *priv = dev_get_priv(dev); + +- priv->timer = dev_read_addr_ptr(dev); +- if (!priv->timer) +- return -ENOENT; +-#endif ++ priv->timer = dev_read_addr_ptr(dev); ++ if (!priv->timer) ++ return -ENOENT; ++ } + + return 0; + } +diff -ruN u-boot-2021.10/drivers/timer/stm32_timer.c u-boot/drivers/timer/stm32_timer.c +--- u-boot-2021.10/drivers/timer/stm32_timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/timer/stm32_timer.c 2021-11-01 17:10:14.486246938 +0100 +@@ -135,4 +135,3 @@ + .probe = stm32_timer_probe, + .ops = &stm32_timer_ops, + }; +- +diff -ruN u-boot-2021.10/drivers/timer/timer-uclass.c u-boot/drivers/timer/timer-uclass.c +--- u-boot-2021.10/drivers/timer/timer-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/timer/timer-uclass.c 2021-11-01 17:10:14.486246938 +0100 +@@ -50,27 +50,29 @@ + + static int timer_pre_probe(struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); +- struct clk timer_clk; +- int err; +- ulong ret; ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); ++ struct clk timer_clk; ++ int err; ++ ulong ret; + +- /* It is possible that a timer device has a null ofnode */ +- if (!dev_has_ofnode(dev)) +- return 0; ++ /* ++ * It is possible that a timer device has a null ofnode ++ */ ++ if (!dev_has_ofnode(dev)) ++ return 0; + +- err = clk_get_by_index(dev, 0, &timer_clk); +- if (!err) { +- ret = clk_get_rate(&timer_clk); +- if (IS_ERR_VALUE(ret)) +- return ret; +- uc_priv->clock_rate = ret; +- } else { +- uc_priv->clock_rate = +- dev_read_u32_default(dev, "clock-frequency", 0); ++ err = clk_get_by_index(dev, 0, &timer_clk); ++ if (!err) { ++ ret = clk_get_rate(&timer_clk); ++ if (IS_ERR_VALUE(ret)) ++ return ret; ++ uc_priv->clock_rate = ret; ++ } else { ++ uc_priv->clock_rate = ++ dev_read_u32_default(dev, "clock-frequency", 0); ++ } + } +-#endif + + return 0; + } +@@ -136,23 +138,23 @@ + if (gd->dm_root == NULL) + return -EAGAIN; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) +- /* Check for a chosen timer to be used for tick */ +- node = ofnode_get_chosen_node("tick-timer"); +- +- if (ofnode_valid(node) && +- uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { +- /* +- * If the timer is not marked to be bound before +- * relocation, bind it anyway. +- */ +- if (!lists_bind_fdt(dm_root(), node, &dev, false)) { +- ret = device_probe(dev); +- if (ret) +- return ret; ++ if (CONFIG_IS_ENABLED(OF_REAL)) { ++ /* Check for a chosen timer to be used for tick */ ++ node = ofnode_get_chosen_node("tick-timer"); ++ ++ if (ofnode_valid(node) && ++ uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { ++ /* ++ * If the timer is not marked to be bound before ++ * relocation, bind it anyway. ++ */ ++ if (!lists_bind_fdt(dm_root(), node, &dev, false)) { ++ ret = device_probe(dev); ++ if (ret) ++ return ret; ++ } + } + } +-#endif + + if (!dev) { + /* Fall back to the first available timer */ +diff -ruN u-boot-2021.10/drivers/timer/tsc_timer.c u-boot/drivers/timer/tsc_timer.c +--- u-boot-2021.10/drivers/timer/tsc_timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/timer/tsc_timer.c 2021-11-01 17:10:14.486246938 +0100 +@@ -479,7 +479,7 @@ + .get_count = tsc_timer_get_count, + }; + +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + static const struct udevice_id tsc_timer_ids[] = { + { .compatible = "x86,tsc-timer", }, + { } +diff -ruN u-boot-2021.10/drivers/tpm/tpm2_tis_spi.c u-boot/drivers/tpm/tpm2_tis_spi.c +--- u-boot-2021.10/drivers/tpm/tpm2_tis_spi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/tpm/tpm2_tis_spi.c 2021-11-01 17:10:14.489580089 +0100 +@@ -589,18 +589,25 @@ + if (CONFIG_IS_ENABLED(DM_GPIO)) { + struct gpio_desc reset_gpio; + +- ret = gpio_request_by_name(dev, "gpio-reset", 0, ++ ret = gpio_request_by_name(dev, "reset-gpios", 0, + &reset_gpio, GPIOD_IS_OUT); + if (ret) { +- log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n", +- __func__); +- } else { +- dm_gpio_set_value(&reset_gpio, 1); +- mdelay(1); +- dm_gpio_set_value(&reset_gpio, 0); ++ /* legacy reset */ ++ ret = gpio_request_by_name(dev, "gpio-reset", 0, ++ &reset_gpio, GPIOD_IS_OUT); ++ if (ret) { ++ log(LOGC_NONE, LOGL_NOTICE, ++ "%s: missing reset GPIO\n", __func__); ++ goto init; ++ } ++ log(LOGC_NONE, LOGL_NOTICE, ++ "%s: gpio-reset is deprecated\n", __func__); + } ++ dm_gpio_set_value(&reset_gpio, 1); ++ mdelay(1); ++ dm_gpio_set_value(&reset_gpio, 0); + } +- ++init: + /* Ensure a minimum amount of time elapsed since reset of the TPM */ + mdelay(drv_data->time_before_first_cmd_ms); + +diff -ruN u-boot-2021.10/drivers/tpm/tpm-uclass.c u-boot/drivers/tpm/tpm-uclass.c +--- u-boot-2021.10/drivers/tpm/tpm-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/tpm/tpm-uclass.c 2021-11-01 17:10:14.486246938 +0100 +@@ -140,7 +140,7 @@ + .id = UCLASS_TPM, + .name = "tpm", + .flags = DM_UC_FLAG_SEQ_ALIAS, +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + .post_bind = dm_scan_fdt_dev, + #endif + .per_device_auto = sizeof(struct tpm_chip_priv), +diff -ruN u-boot-2021.10/drivers/usb/dwc3/core.h u-boot/drivers/usb/dwc3/core.h +--- u-boot-2021.10/drivers/usb/dwc3/core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/dwc3/core.h 2021-11-01 17:10:14.492913240 +0100 +@@ -691,8 +691,8 @@ + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that + * there's now way for software to detect this in runtime. + * @is_utmi_l1_suspend: the core asserts output signal +- * 0 - utmi_sleep_n +- * 1 - utmi_l1_suspend_n ++ * 0 - utmi_sleep_n ++ * 1 - utmi_l1_suspend_n + * @is_selfpowered: true when we are selfpowered + * @is_fpga: true when we are using the FPGA board + * @needs_fifo_resize: not all users might want fifo resizing, flag it +@@ -713,10 +713,10 @@ + * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy + * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk + * @tx_de_emphasis: Tx de-emphasis value +- * 0 - -6dB de-emphasis +- * 1 - -3.5dB de-emphasis +- * 2 - No de-emphasis +- * 3 - Reserved ++ * 0 - -6dB de-emphasis ++ * 1 - -3.5dB de-emphasis ++ * 2 - No de-emphasis ++ * 3 - Reserved + * @index: index of _this_ controller + * @list: to maintain the list of dwc3 controllers + */ +diff -ruN u-boot-2021.10/drivers/usb/dwc3/dwc3-meson-gxl.c u-boot/drivers/usb/dwc3/dwc3-meson-gxl.c +--- u-boot-2021.10/drivers/usb/dwc3/dwc3-meson-gxl.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/dwc3/dwc3-meson-gxl.c 2021-11-01 17:10:14.492913240 +0100 +@@ -170,7 +170,7 @@ + static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv) + { + int ret; +- ++ + ret = dwc3_meson_gxl_usb2_init(priv); + if (ret) + return ret; +@@ -409,6 +409,7 @@ + } + + static const struct udevice_id dwc3_meson_gxl_ids[] = { ++ { .compatible = "amlogic,meson-axg-usb-ctrl" }, + { .compatible = "amlogic,meson-gxl-usb-ctrl" }, + { .compatible = "amlogic,meson-gxm-usb-ctrl" }, + { } +diff -ruN u-boot-2021.10/drivers/usb/dwc3/gadget.c u-boot/drivers/usb/dwc3/gadget.c +--- u-boot-2021.10/drivers/usb/dwc3/gadget.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/dwc3/gadget.c 2021-11-01 17:10:14.492913240 +0100 +@@ -2209,7 +2209,7 @@ + * BESL value in the LPM token is less than or equal to LPM + * NYET threshold. + */ +- if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum) ++ if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum) + WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); + + if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) +diff -ruN u-boot-2021.10/drivers/usb/eth/r8152.c u-boot/drivers/usb/eth/r8152.c +--- u-boot-2021.10/drivers/usb/eth/r8152.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/eth/r8152.c 2021-11-01 17:10:14.496246391 +0100 +@@ -1894,4 +1894,3 @@ + + U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); + #endif /* CONFIG_DM_ETH */ +- +diff -ruN u-boot-2021.10/drivers/usb/gadget/at91_udc.h u-boot/drivers/usb/gadget/at91_udc.h +--- u-boot-2021.10/drivers/usb/gadget/at91_udc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/gadget/at91_udc.h 2021-11-01 17:10:14.496246391 +0100 +@@ -35,7 +35,7 @@ + + #define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ + #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ +-#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ ++#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ + #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ + #define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */ + #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ +@@ -164,4 +164,3 @@ + #define DBG(stuff...) debug("udc: " stuff) + + #endif +- +diff -ruN u-boot-2021.10/drivers/usb/gadget/f_rockusb.c u-boot/drivers/usb/gadget/f_rockusb.c +--- u-boot-2021.10/drivers/usb/gadget/f_rockusb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/gadget/f_rockusb.c 2021-11-01 17:10:14.499579542 +0100 +@@ -17,7 +17,6 @@ + #include <linux/usb/gadget.h> + #include <linux/usb/composite.h> + #include <linux/compiler.h> +-#include <version.h> + #include <g_dnl.h> + #include <asm/arch-rockchip/f_rockusb.h> + +diff -ruN u-boot-2021.10/drivers/usb/gadget/Kconfig u-boot/drivers/usb/gadget/Kconfig +--- u-boot-2021.10/drivers/usb/gadget/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/gadget/Kconfig 2021-11-01 17:10:14.496246391 +0100 +@@ -40,7 +40,7 @@ + + config USB_GADGET_MANUFACTURER + string "Vendor name of the USB device" +- default "Allwinner Technology" if ARCH_SUNXI ++ default "Allwinner Technology" if (ARCH_SUNXI || TARGET_SUNXI) + default "Rockchip" if ARCH_ROCKCHIP + default "U-Boot" + help +@@ -49,7 +49,7 @@ + + config USB_GADGET_VENDOR_NUM + hex "Vendor ID of the USB device" +- default 0x1f3a if ARCH_SUNXI ++ default 0x1f3a if (ARCH_SUNXI || TARGET_SUNXI) + default 0x2207 if ARCH_ROCKCHIP + default 0x0 + help +@@ -59,7 +59,7 @@ + + config USB_GADGET_PRODUCT_NUM + hex "Product ID of the USB device" +- default 0x1010 if ARCH_SUNXI ++ default 0x1010 if (ARCH_SUNXI || TARGET_SUNXI) + default 0x310a if ROCKCHIP_RK3036 + default 0x310c if ROCKCHIP_RK3128 + default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 +@@ -187,7 +187,6 @@ + config USB_ETHER + bool "USB Ethernet Gadget" + depends on NET +- default y if ARCH_SUNXI && USB_MUSB_GADGET + help + Creates an Ethernet network device through a USB peripheral + controller. This will create a network interface on both the device +diff -ruN u-boot-2021.10/drivers/usb/gadget/pxa27x_udc.c u-boot/drivers/usb/gadget/pxa27x_udc.c +--- u-boot-2021.10/drivers/usb/gadget/pxa27x_udc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/gadget/pxa27x_udc.c 2021-11-01 17:10:14.502912693 +0100 +@@ -472,7 +472,7 @@ + * so using '|=' isn't safe as it may ack an interrupt. + */ + #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +-#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) ++#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) + + static inline void udc_set_mask_UDCCR(int mask) + { +diff -ruN u-boot-2021.10/drivers/usb/host/dwc2.c u-boot/drivers/usb/host/dwc2.c +--- u-boot-2021.10/drivers/usb/host/dwc2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/dwc2.c 2021-11-01 17:10:14.502912693 +0100 +@@ -86,14 +86,14 @@ + { + uint32_t phyclk; + +-#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) ++#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) + phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ + #else + /* High speed PHY running at full speed or high speed */ + phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; + #endif + +-#ifdef CONFIG_DWC2_ULPI_FS_LS ++#ifdef DWC2_ULPI_FS_LS + uint32_t hwcfg2 = readl(®s->ghwcfg2); + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; +@@ -257,28 +257,28 @@ + + /* Initialize Host Configuration Register */ + init_fslspclksel(regs); +-#ifdef CONFIG_DWC2_DFLT_SPEED_FULL ++#ifdef DWC2_DFLT_SPEED_FULL + setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); + #endif + + /* Configure data FIFO sizes */ +-#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO ++#ifdef DWC2_ENABLE_DYNAMIC_FIFO + if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { + /* Rx FIFO */ +- writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); ++ writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); + + /* Non-periodic Tx FIFO */ +- nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << ++ nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << + DWC2_FIFOSIZE_DEPTH_OFFSET; +- nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << ++ nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE << + DWC2_FIFOSIZE_STARTADDR_OFFSET; + writel(nptxfifosize, ®s->gnptxfsiz); + + /* Periodic Tx FIFO */ +- ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << ++ ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE << + DWC2_FIFOSIZE_DEPTH_OFFSET; +- ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + +- CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << ++ ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE + ++ DWC2_HOST_NPERIO_TX_FIFO_SIZE) << + DWC2_FIFOSIZE_STARTADDR_OFFSET; + writel(ptxfifosize, ®s->hptxfsiz); + } +@@ -340,7 +340,7 @@ + struct dwc2_core_regs *regs = priv->regs; + uint32_t ahbcfg = 0; + uint32_t usbcfg = 0; +- uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; ++ uint8_t brst_sz = DWC2_DMA_BURST_SIZE; + + /* Common Initialization */ + usbcfg = readl(®s->gusbcfg); +@@ -357,7 +357,7 @@ + } + + /* Set external TS Dline pulsing */ +-#ifdef CONFIG_DWC2_TS_DLINE ++#ifdef DWC2_TS_DLINE + usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; + #else + usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; +@@ -371,8 +371,8 @@ + * This programming sequence needs to happen in FS mode before + * any other programming occurs + */ +-#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ +- (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) ++#if defined(DWC2_DFLT_SPEED_FULL) && \ ++ (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) + /* If FS mode with FS PHY */ + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); + +@@ -387,7 +387,7 @@ + if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) + init_fslspclksel(regs); + +-#ifdef CONFIG_DWC2_I2C_ENABLE ++#ifdef DWC2_I2C_ENABLE + /* Program GUSBCFG.OtgUtmifsSel to I2C */ + setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); + +@@ -407,16 +407,16 @@ + * immediately after setting phyif. + */ + usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); +- usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; ++ usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; + + if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ +-#ifdef CONFIG_DWC2_PHY_ULPI_DDR ++#ifdef DWC2_PHY_ULPI_DDR + usbcfg |= DWC2_GUSBCFG_DDRSEL; + #else + usbcfg &= ~DWC2_GUSBCFG_DDRSEL; + #endif + } else { /* UTMI+ interface */ +-#if (CONFIG_DWC2_UTMI_WIDTH == 16) ++#if (DWC2_UTMI_WIDTH == 16) + usbcfg |= DWC2_GUSBCFG_PHYIF; + #endif + } +@@ -429,7 +429,7 @@ + + usbcfg = readl(®s->gusbcfg); + usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); +-#ifdef CONFIG_DWC2_ULPI_FS_LS ++#ifdef DWC2_ULPI_FS_LS + uint32_t hwcfg2 = readl(®s->ghwcfg2); + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; +@@ -456,14 +456,14 @@ + brst_sz >>= 1; + } + +-#ifdef CONFIG_DWC2_DMA_ENABLE ++#ifdef DWC2_DMA_ENABLE + ahbcfg |= DWC2_GAHBCFG_DMAENABLE; + #endif + break; + + case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: + ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; +-#ifdef CONFIG_DWC2_DMA_ENABLE ++#ifdef DWC2_DMA_ENABLE + ahbcfg |= DWC2_GAHBCFG_DMAENABLE; + #endif + break; +@@ -476,7 +476,7 @@ + + if (!priv->hnp_srp_disable) + usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; +-#ifdef CONFIG_DWC2_IC_USB_CAP ++#ifdef DWC2_IC_USB_CAP + usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; + #endif + +@@ -939,9 +939,9 @@ + debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, + in, len); + +- max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; +- if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) +- max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; ++ max_xfer_len = DWC2_MAX_PACKET_COUNT * max; ++ if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE) ++ max_xfer_len = DWC2_MAX_TRANSFER_SIZE; + if (max_xfer_len > DWC2_DATA_BUF_SIZE) + max_xfer_len = DWC2_DATA_BUF_SIZE; + +@@ -1198,7 +1198,7 @@ + return -ENODEV; + } + +-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS ++#ifdef DWC2_PHY_ULPI_EXT_VBUS + priv->ext_vbus = 1; + #else + priv->ext_vbus = 0; +diff -ruN u-boot-2021.10/drivers/usb/host/dwc2.h u-boot/drivers/usb/host/dwc2.h +--- u-boot-2021.10/drivers/usb/host/dwc2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/dwc2.h 2021-11-01 17:10:14.502912693 +0100 +@@ -759,32 +759,32 @@ + #define RH_B_PPCM 0xffff0000 /* port power control mask */ + + /* Default driver configuration */ +-#define CONFIG_DWC2_DMA_ENABLE +-#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +-#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +-#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +-#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) +-#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +-#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +-#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 +-#define CONFIG_DWC2_MAX_PACKET_COUNT 511 ++#define DWC2_DMA_ENABLE ++#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ ++#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ ++#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ ++#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ ++#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) ++#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ ++#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ ++#define DWC2_MAX_TRANSFER_SIZE 65535 ++#define DWC2_MAX_PACKET_COUNT 511 + + #define DWC2_PHY_TYPE_FS 0 + #define DWC2_PHY_TYPE_UTMI 1 + #define DWC2_PHY_TYPE_ULPI 2 +-#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +-#ifndef CONFIG_DWC2_UTMI_WIDTH +-#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ ++#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ ++#ifndef DWC2_UTMI_WIDTH ++#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ + #endif + +-#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +-#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +-#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ +-#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +-#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ +-#undef CONFIG_DWC2_THR_CTL /* Threshold control */ +-#define CONFIG_DWC2_TX_THR_LENGTH 64 +-#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ ++#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ ++#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ ++#undef DWC2_I2C_ENABLE /* Enable I2C */ ++#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ ++#undef DWC2_TS_DLINE /* External DLine pulsing */ ++#undef DWC2_THR_CTL /* Threshold control */ ++#define DWC2_TX_THR_LENGTH 64 ++#undef DWC2_IC_USB_CAP /* IC Cap */ + + #endif /* __DWC2_H__ */ +diff -ruN u-boot-2021.10/drivers/usb/host/ehci-mxc.c u-boot/drivers/usb/host/ehci-mxc.c +--- u-boot-2021.10/drivers/usb/host/ehci-mxc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/ehci-mxc.c 2021-11-01 17:10:14.506245844 +0100 +@@ -67,56 +67,7 @@ + unsigned int v; + + v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); +-#if defined(CONFIG_MX25) +- switch (port) { +- case 0: /* OTG port */ +- v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | +- MX25_OTG_OCPOL_BIT); +- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; +- +- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) +- v |= MX25_OTG_PM_BIT; +- +- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) +- v |= MX25_OTG_PP_BIT; +- +- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) +- v |= MX25_OTG_OCPOL_BIT; +- +- break; +- case 1: /* H1 port */ +- v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | +- MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | +- MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | +- MX25_H1_IPPUE_UP_BIT); +- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; +- +- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) +- v |= MX25_H1_PM_BIT; +- +- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) +- v |= MX25_H1_PP_BIT; +- +- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) +- v |= MX25_H1_OCPOL_BIT; +- +- if (!(flags & MXC_EHCI_TTL_ENABLED)) +- v |= MX25_H1_TLL_BIT; +- +- if (flags & MXC_EHCI_INTERNAL_PHY) +- v |= MX25_H1_USBTE_BIT; +- +- if (flags & MXC_EHCI_IPPUE_DOWN) +- v |= MX25_H1_IPPUE_DOWN_BIT; +- +- if (flags & MXC_EHCI_IPPUE_UP) +- v |= MX25_H1_IPPUE_UP_BIT; +- +- break; +- default: +- return -EINVAL; +- } +-#elif defined(CONFIG_MX31) ++#if defined(CONFIG_MX31) + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); +@@ -151,55 +102,6 @@ + default: + return -EINVAL; + } +-#elif defined(CONFIG_MX35) +- switch (port) { +- case 0: /* OTG port */ +- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | +- MX35_OTG_OCPOL_BIT); +- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; +- +- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) +- v |= MX35_OTG_PM_BIT; +- +- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) +- v |= MX35_OTG_PP_BIT; +- +- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) +- v |= MX35_OTG_OCPOL_BIT; +- +- break; +- case 1: /* H1 port */ +- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | +- MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | +- MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | +- MX35_H1_IPPUE_UP_BIT); +- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; +- +- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) +- v |= MX35_H1_PM_BIT; +- +- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) +- v |= MX35_H1_PP_BIT; +- +- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) +- v |= MX35_H1_OCPOL_BIT; +- +- if (!(flags & MXC_EHCI_TTL_ENABLED)) +- v |= MX35_H1_TLL_BIT; +- +- if (flags & MXC_EHCI_INTERNAL_PHY) +- v |= MX35_H1_USBTE_BIT; +- +- if (flags & MXC_EHCI_IPPUE_DOWN) +- v |= MX35_H1_IPPUE_DOWN_BIT; +- +- if (flags & MXC_EHCI_IPPUE_UP) +- v |= MX35_H1_IPPUE_UP_BIT; +- +- break; +- default: +- return -EINVAL; +- } + #else + #error MXC EHCI USB driver not supported on this platform + #endif +@@ -230,10 +132,6 @@ + setbits_le32(&ehci->usbmode, CM_HOST); + __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); +-#ifdef CONFIG_MX35 +- /* Workaround for ENGcm11601 */ +- __raw_writel(0, &ehci->sbuscfg); +-#endif + + udelay(10000); + +diff -ruN u-boot-2021.10/drivers/usb/host/ehci-omap.c u-boot/drivers/usb/host/ehci-omap.c +--- u-boot-2021.10/drivers/usb/host/ehci-omap.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/ehci-omap.c 2021-11-01 17:10:14.506245844 +0100 +@@ -183,17 +183,8 @@ + * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 + * See there for additional Copyrights. + */ +-#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL) +- +-int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, +- struct ehci_hccr **hccr, struct ehci_hcor **hcor) +-{ +- *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); +- *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); +-#else + int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata) + { +-#endif + int ret; + unsigned int i, reg = 0, rev = 0; + +@@ -304,8 +295,6 @@ + return 0; + } + +-#if CONFIG_IS_ENABLED(DM_USB) +- + static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, +@@ -409,5 +398,3 @@ + .ops = &ehci_usb_ops, + .flags = DM_FLAG_ALLOC_PRIV_DMA, + }; +- +-#endif +diff -ruN u-boot-2021.10/drivers/usb/host/Kconfig u-boot/drivers/usb/host/Kconfig +--- u-boot-2021.10/drivers/usb/host/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/Kconfig 2021-11-01 17:10:14.502912693 +0100 +@@ -57,6 +57,16 @@ + family SoCs. This is a driver for the dwc3 to provide the glue logic + to configure the controller. + ++config USB_XHCI_OMAP ++ bool "Support for TI OMAP family xHCI USB controller" ++ depends on ARCH_OMAP2PLUS ++ help ++ Enables support for the on-chip xHCI controller found on some TI SoC ++ families. Note that some families have multiple contollers while ++ others only have something such as DesignWare-based controllers. ++ Consult the SoC documentation to determine if this option applies ++ to your hardware. ++ + config USB_XHCI_PCI + bool "Support for PCI-based xHCI USB controller" + depends on DM_USB +@@ -146,7 +156,6 @@ + config USB_EHCI_MX5 + bool "Support for i.MX5 on-chip EHCI USB controller" + depends on ARCH_MX5 +- default n + help + Enables support for the on-chip EHCI controller on i.MX5 SoCs. + +@@ -174,6 +183,40 @@ + Enables support for the on-chip EHCI controller on OMAP3 and later + SoCs. + ++if USB_EHCI_OMAP ++ ++config HAS_OMAP_EHCI_PHY1_RESET_GPIO ++ bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles" ++ help ++ Enable this to be able to configure the GPIO number used to hold the ++ PHY in RESET for enough time until the PHY is settled and ready. ++ ++config OMAP_EHCI_PHY1_RESET_GPIO ++ int "GPIO number to hold PHY #1 in RESET" ++ depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO ++ ++config HAS_OMAP_EHCI_PHY2_RESET_GPIO ++ bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles" ++ help ++ Enable this to be able to configure the GPIO number used to hold the ++ PHY in RESET for enough time until the PHY is settled and ready. ++ ++config OMAP_EHCI_PHY2_RESET_GPIO ++ int "GPIO number to hold PHY #2 in RESET" ++ depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO ++ ++config HAS_OMAP_EHCI_PHY3_RESET_GPIO ++ bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles" ++ help ++ Enable this to be able to configure the GPIO number used to hold the ++ PHY in RESET for enough time until the PHY is settled and ready. ++ ++config OMAP_EHCI_PHY3_RESET_GPIO ++ int "GPIO number to hold PHY #3 in RESET" ++ depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO ++ ++endif ++ + config USB_EHCI_VF + bool "Support for Vybrid on-chip EHCI USB controller" + depends on ARCH_VF610 +@@ -195,7 +238,6 @@ + depends on DM_USB + select USB_ULPI_VIEWPORT + select MSM8916_USB_PHY +- default n + ---help--- + Enables support for the on-chip EHCI controller on Qualcomm + Snapdragon SoCs. +@@ -221,14 +263,11 @@ + config USB_EHCI_GENERIC + bool "Support for generic EHCI USB controller" + depends on DM_USB +- default ARCH_SUNXI +- default n + ---help--- + Enables support for generic EHCI controller. + + config USB_EHCI_FSL + bool "Support for FSL on-chip EHCI USB controller" +- default n + select CONFIG_EHCI_HCD_INIT_AFTER_RESET + ---help--- + Enables support for the on-chip EHCI controller on FSL chips. +@@ -258,7 +297,6 @@ + + config USB_OHCI_GENERIC + bool "Support for generic OHCI USB controller" +- default ARCH_SUNXI + ---help--- + Enables support for generic OHCI controller. + +diff -ruN u-boot-2021.10/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h u-boot/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +--- u-boot-2021.10/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h 2021-11-01 17:10:14.509578995 +0100 +@@ -40,7 +40,7 @@ + * + * To generate the content of the array below, use ie. the following command: + * $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \ +- * sed "s@\(.\{47\}\) @\1\n@g" ++ * sed "s@\(.\{47\}\) @\1\n@g" + * + * [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git + */ +diff -ruN u-boot-2021.10/drivers/usb/musb/musb_core.h u-boot/drivers/usb/musb/musb_core.h +--- u-boot-2021.10/drivers/usb/musb/musb_core.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb/musb_core.h 2021-11-01 17:10:14.512912146 +0100 +@@ -207,14 +207,14 @@ + /* TxType/RxType */ + #define MUSB_TYPE_SPEED 0xc0 + #define MUSB_TYPE_SPEED_SHIFT 6 +-#define MUSB_TYPE_SPEED_HIGH 1 +-#define MUSB_TYPE_SPEED_FULL 2 ++#define MUSB_TYPE_SPEED_HIGH 1 ++#define MUSB_TYPE_SPEED_FULL 2 + #define MUSB_TYPE_SPEED_LOW 3 + #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ + #define MUSB_TYPE_PROTO_SHIFT 4 + #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ +-#define MUSB_TYPE_PROTO_BULK 2 +-#define MUSB_TYPE_PROTO_INTR 3 ++#define MUSB_TYPE_PROTO_BULK 2 ++#define MUSB_TYPE_PROTO_INTR 3 + + /* CONFIGDATA */ + #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +@@ -304,7 +304,7 @@ + * values are not supported + */ + struct musb_epinfo { +- u8 epnum; /* endpoint number */ ++ u8 epnum; /* endpoint number */ + u8 epdir; /* endpoint direction */ + u16 epsize; /* endpoint FIFO size */ + }; +diff -ruN u-boot-2021.10/drivers/usb/musb/musb_hcd.c u-boot/drivers/usb/musb/musb_hcd.c +--- u-boot-2021.10/drivers/usb/musb/musb_hcd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb/musb_hcd.c 2021-11-01 17:10:14.516245298 +0100 +@@ -14,7 +14,7 @@ + #include "musb_hcd.h" + + /* MSC control transfers */ +-#define USB_MSC_BBB_RESET 0xFF ++#define USB_MSC_BBB_RESET 0xFF + #define USB_MSC_BBB_GET_MAX_LUN 0xFE + + /* Endpoint configuration information */ +@@ -327,7 +327,7 @@ + + /* Set TXPKTRDY bit */ + csr = readw(&musbr->txcsr); +- ++ + csr |= MUSB_CSR0_TXPKTRDY; + csr |= MUSB_CSR0_H_DIS_PING; + writew(csr, &musbr->txcsr); +diff -ruN u-boot-2021.10/drivers/usb/musb-new/Kconfig u-boot/drivers/usb/musb-new/Kconfig +--- u-boot-2021.10/drivers/usb/musb-new/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/Kconfig 2021-11-01 17:10:14.509578995 +0100 +@@ -34,7 +34,6 @@ + bool "Enable TI OTG USB controller" + depends on AM33XX + select USB_MUSB_DSPS +- default n + help + Say y here to enable support for the dual role high + speed USB controller based on the Mentor Graphics +@@ -53,7 +52,6 @@ + config USB_MUSB_MT85XX + bool "Enable Mediatek MT85XX DRC USB controller" + depends on ARCH_MEDIATEK +- default n + help + Say y to enable Mediatek MT85XX USB DRC controller support + if it is available on your Mediatek MUSB IP based platform. +@@ -69,7 +67,7 @@ + + config USB_MUSB_SUNXI + bool "Enable sunxi OTG / DRC USB controller" +- depends on ARCH_SUNXI ++ depends on (ARCH_SUNXI || TARGET_SUNXI) + default y + ---help--- + Say y here to enable support for the sunxi OTG / DRC USB controller +diff -ruN u-boot-2021.10/drivers/usb/musb-new/musb_gadget.c u-boot/drivers/usb/musb-new/musb_gadget.c +--- u-boot-2021.10/drivers/usb/musb-new/musb_gadget.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/musb_gadget.c 2021-11-01 17:10:14.512912146 +0100 +@@ -995,8 +995,8 @@ + && (musb_ep->dma->actual_len + == musb_ep->packet_sz)) { + /* In double buffer case, continue to unload fifo if +- * there is Rx packet in FIFO. +- **/ ++ * there is Rx packet in FIFO. ++ **/ + csr = musb_readw(epio, MUSB_RXCSR); + if ((csr & MUSB_RXCSR_RXPKTRDY) && + hw_ep->rx_double_buffered) +diff -ruN u-boot-2021.10/drivers/usb/musb-new/musb_io.h u-boot/drivers/usb/musb-new/musb_io.h +--- u-boot-2021.10/drivers/usb/musb-new/musb_io.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/musb_io.h 2021-11-01 17:10:14.512912146 +0100 +@@ -23,7 +23,7 @@ + #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \ + && !defined(CONFIG_PPC32) \ + && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \ +- && !defined(CONFIG_M68K) ++ && !defined(CONFIG_M68K) && !defined(CONFIG_RISCV) + static inline void readsl(const void __iomem *addr, void *buf, int len) + { insl((unsigned long)addr, buf, len); } + static inline void readsw(const void __iomem *addr, void *buf, int len) +diff -ruN u-boot-2021.10/drivers/usb/musb-new/musb_regs.h u-boot/drivers/usb/musb-new/musb_regs.h +--- u-boot-2021.10/drivers/usb/musb-new/musb_regs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/musb_regs.h 2021-11-01 17:10:14.512912146 +0100 +@@ -190,7 +190,7 @@ + + + /* SUNXI has different reg addresses, but identical r/w functions */ +-#ifndef CONFIG_ARCH_SUNXI ++#ifndef CONFIG_ARCH_SUNXI + + /* + * Common USB registers +diff -ruN u-boot-2021.10/drivers/usb/musb-new/musb_uboot.c u-boot/drivers/usb/musb-new/musb_uboot.c +--- u-boot-2021.10/drivers/usb/musb-new/musb_uboot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/musb_uboot.c 2021-11-01 17:10:14.512912146 +0100 +@@ -159,7 +159,7 @@ + static int _musb_destroy_int_queue(struct musb_host_data *host, + struct usb_device *dev, struct int_queue *queue) + { +- int index = usb_pipein(queue->urb.pipe) * 16 + ++ int index = usb_pipein(queue->urb.pipe) * 16 + + usb_pipeendpoint(queue->urb.pipe); + + if (queue->urb.status == -EINPROGRESS) +diff -ruN u-boot-2021.10/drivers/usb/musb-new/sunxi.c u-boot/drivers/usb/musb-new/sunxi.c +--- u-boot-2021.10/drivers/usb/musb-new/sunxi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/musb-new/sunxi.c 2021-11-01 17:10:14.512912146 +0100 +@@ -23,10 +23,8 @@ + #include <malloc.h> + #include <phy-sun4i-usb.h> + #include <reset.h> +-#include <asm/arch/cpu.h> +-#include <asm/arch/clock.h> +-#include <asm/arch/gpio.h> +-#include <asm-generic/gpio.h> ++//#include <asm/arch/cpu.h> ++//#include <asm/arch/clock.h> + #include <dm/device_compat.h> + #include <dm/lists.h> + #include <dm/root.h> +@@ -176,6 +174,7 @@ + + static void USBC_ConfigFIFO_Base(void) + { ++#if 0 + u32 reg_value; + + /* config usb fifo, 8kb mode */ +@@ -183,6 +182,7 @@ + reg_value &= ~(0x03 << 0); + reg_value |= BIT(0); + writel(reg_value, SUNXI_SRAMC_BASE + 0x04); ++#endif + } + + /****************************************************************************** +diff -ruN u-boot-2021.10/drivers/usb/phy/Kconfig u-boot/drivers/usb/phy/Kconfig +--- u-boot-2021.10/drivers/usb/phy/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/phy/Kconfig 2021-11-01 17:10:14.516245298 +0100 +@@ -8,8 +8,5 @@ + config TWL4030_USB + bool "TWL4030 PHY" + +-config OMAP_USB_PHY +- bool "OMAP PHY" +- + config ROCKCHIP_USB2_PHY + bool "Rockchip USB2 PHY" +diff -ruN u-boot-2021.10/drivers/usb/phy/Makefile u-boot/drivers/usb/phy/Makefile +--- u-boot-2021.10/drivers/usb/phy/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/phy/Makefile 2021-11-01 17:10:14.516245298 +0100 +@@ -4,5 +4,4 @@ + # Tom Rix <Tom.Rix@windriver.com> + + obj-$(CONFIG_TWL4030_USB) += twl4030.o +-obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o + obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o +diff -ruN u-boot-2021.10/drivers/usb/phy/omap_usb_phy.c u-boot/drivers/usb/phy/omap_usb_phy.c +--- u-boot-2021.10/drivers/usb/phy/omap_usb_phy.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/usb/phy/omap_usb_phy.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,267 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * OMAP USB PHY Support +- * +- * (C) Copyright 2013 +- * Texas Instruments, <www.ti.com> +- * +- * Author: Dan Murphy <dmurphy@ti.com> +- */ +- +-#include <common.h> +-#include <usb.h> +-#include <dm/device_compat.h> +-#include <linux/delay.h> +-#include <linux/errno.h> +-#include <asm/omap_common.h> +-#include <asm/arch/cpu.h> +-#include <asm/arch/sys_proto.h> +- +-#include <linux/compat.h> +-#include <linux/usb/dwc3.h> +-#include <linux/usb/xhci-omap.h> +- +-#include <usb/xhci.h> +- +-#ifdef CONFIG_OMAP_USB3PHY1_HOST +-struct usb3_dpll_params { +- u16 m; +- u8 n; +- u8 freq:3; +- u8 sd; +- u32 mf; +-}; +- +-struct usb3_dpll_map { +- unsigned long rate; +- struct usb3_dpll_params params; +- struct usb3_dpll_map *dpll_map; +-}; +- +-static struct usb3_dpll_map dpll_map_usb[] = { +- {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ +- {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ +- {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ +- {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ +- {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ +- {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ +- { }, /* Terminator */ +-}; +- +-static struct usb3_dpll_params *omap_usb3_get_dpll_params(void) +-{ +- unsigned long rate; +- struct usb3_dpll_map *dpll_map = dpll_map_usb; +- +- rate = get_sys_clk_freq(); +- +- for (; dpll_map->rate; dpll_map++) { +- if (rate == dpll_map->rate) +- return &dpll_map->params; +- } +- +- dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); +- +- return NULL; +-} +- +-static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) +-{ +- u32 val; +- +- writel(SET_PLL_GO, &phy_regs->pll_go); +- do { +- val = readl(&phy_regs->pll_status); +- if (val & PLL_LOCK) +- break; +- } while (1); +-} +- +-static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) +-{ +- struct usb3_dpll_params *dpll_params; +- u32 val; +- +- dpll_params = omap_usb3_get_dpll_params(); +- if (!dpll_params) +- return; +- +- val = readl(&phy_regs->pll_config_1); +- val &= ~PLL_REGN_MASK; +- val |= dpll_params->n << PLL_REGN_SHIFT; +- writel(val, &phy_regs->pll_config_1); +- +- val = readl(&phy_regs->pll_config_2); +- val &= ~PLL_SELFREQDCO_MASK; +- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; +- writel(val, &phy_regs->pll_config_2); +- +- val = readl(&phy_regs->pll_config_1); +- val &= ~PLL_REGM_MASK; +- val |= dpll_params->m << PLL_REGM_SHIFT; +- writel(val, &phy_regs->pll_config_1); +- +- val = readl(&phy_regs->pll_config_4); +- val &= ~PLL_REGM_F_MASK; +- val |= dpll_params->mf << PLL_REGM_F_SHIFT; +- writel(val, &phy_regs->pll_config_4); +- +- val = readl(&phy_regs->pll_config_3); +- val &= ~PLL_SD_MASK; +- val |= dpll_params->sd << PLL_SD_SHIFT; +- writel(val, &phy_regs->pll_config_3); +- +- omap_usb_dpll_relock(phy_regs); +-} +- +-static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) +-{ +- u32 rate = get_sys_clk_freq()/1000000; +- u32 val; +- +- val = readl((*ctrl)->control_phy_power_usb); +- val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); +- val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); +- val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; +- +- writel(val, (*ctrl)->control_phy_power_usb); +-} +- +-void usb_phy_power(int on) +-{ +- u32 val; +- +- val = readl((*ctrl)->control_phy_power_usb); +- if (on) { +- val &= ~USB3_PWRCTL_CLK_CMD_MASK; +- val |= USB3_PHY_TX_RX_POWERON; +- } else { +- val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); +- } +- +- writel(val, (*ctrl)->control_phy_power_usb); +-} +- +-void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) +-{ +- omap_usb_dpll_lock(phy_regs); +- usb3_phy_partial_powerup(phy_regs); +- /* +- * Give enough time for the PHY to partially power-up before +- * powering it up completely. delay value suggested by the HW +- * team. +- */ +- mdelay(100); +-} +- +-static void omap_enable_usb3_phy(struct omap_xhci *omap) +-{ +- u32 val; +- +- val = (USBOTGSS_DMADISABLE | +- USBOTGSS_STANDBYMODE_SMRT_WKUP | +- USBOTGSS_IDLEMODE_NOIDLE); +- writel(val, &omap->otg_wrapper->sysconfig); +- +- /* Clear the utmi OTG status */ +- val = readl(&omap->otg_wrapper->utmi_otg_status); +- writel(val, &omap->otg_wrapper->utmi_otg_status); +- +- /* Enable interrupts */ +- writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); +- val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | +- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | +- USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | +- USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | +- USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | +- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | +- USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | +- USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | +- USBOTGSS_IRQ_SET_1_OEVT_EN); +- writel(val, &omap->otg_wrapper->irqenable_set_1); +- +- /* Clear the IRQ status */ +- val = readl(&omap->otg_wrapper->irqstatus_1); +- writel(val, &omap->otg_wrapper->irqstatus_1); +- val = readl(&omap->otg_wrapper->irqstatus_0); +- writel(val, &omap->otg_wrapper->irqstatus_0); +-}; +-#endif /* CONFIG_OMAP_USB3PHY1_HOST */ +- +-#ifdef CONFIG_OMAP_USB2PHY2_HOST +-static void omap_enable_usb2_phy2(struct omap_xhci *omap) +-{ +- u32 reg, val; +- +- val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); +- writel(val, (*ctrl)->control_srcomp_north_side); +- +- setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, +- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); +- +- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, +- (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K | +- OTG_SS_CLKCTRL_MODULEMODE_HW)); +- +- /* This is an undocumented Reserved register */ +- reg = 0x4a0086c0; +- val = readl(reg); +- val |= 0x100; +- setbits_le32(reg, val); +-} +- +-void usb_phy_power(int on) +-{ +- return; +-} +-#endif /* CONFIG_OMAP_USB2PHY2_HOST */ +- +-#ifdef CONFIG_AM437X_USB2PHY2_HOST +-static void am437x_enable_usb2_phy2(struct omap_xhci *omap) +-{ +- const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN | +- USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); +- +- writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL); +- writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL); +- +- writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL); +- writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL); +-} +- +-void usb_phy_power(int on) +-{ +- u32 val; +- +- /* USB1_CTRL */ +- val = readl(USB1_CTRL); +- if (on) { +- /* +- * these bits are re-used on AM437x to power up/down the USB +- * CM and OTG PHYs, if we don't toggle them, USB will not be +- * functional on newer silicon revisions +- */ +- val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); +- } else { +- val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; +- } +- +- writel(val, USB1_CTRL); +-} +-#endif /* CONFIG_AM437X_USB2PHY2_HOST */ +- +-void omap_enable_phy(struct omap_xhci *omap) +-{ +-#ifdef CONFIG_OMAP_USB2PHY2_HOST +- omap_enable_usb2_phy2(omap); +-#endif +- +-#ifdef CONFIG_AM437X_USB2PHY2_HOST +- am437x_enable_usb2_phy2(omap); +-#endif +- +-#ifdef CONFIG_OMAP_USB3PHY1_HOST +- omap_enable_usb3_phy(omap); +- omap_usb3_phy_init(omap->usb3_phy); +-#endif +-} +diff -ruN u-boot-2021.10/drivers/video/anx9804.c u-boot/drivers/video/anx9804.c +--- u-boot-2021.10/drivers/video/anx9804.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/anx9804.c 2021-11-01 17:10:14.516245298 +0100 +@@ -21,18 +21,23 @@ + * This function will init an anx9804 parallel lcd to dp bridge chip + * using the passed in parameters. + * +- * @i2c_bus: Number of the i2c bus to which the anx9804 is connected. ++ * @i2c_bus: Device of the i2c bus to which the anx9804 is connected. + * @lanes: Number of displayport lanes to use + * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G + * @bpp: Bits per pixel, must be 18 or 24 + */ +-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) ++void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) + { +- unsigned int orig_i2c_bus = i2c_get_bus_num(); +- u8 c, colordepth; +- int i; ++ struct udevice *chip0, *chip1; ++ int c, colordepth, i, ret; + +- i2c_set_bus_num(i2c_bus); ++ ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0); ++ if (ret) ++ return; ++ ++ ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1); ++ if (ret) ++ return; + + if (bpp == 18) + colordepth = 0x00; /* 6 bit */ +@@ -40,24 +45,23 @@ + colordepth = 0x10; /* 8 bit */ + + /* Reset */ +- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1); ++ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1); + mdelay(100); +- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0); ++ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0); + + /* Write 0 to the powerdown reg (powerup everything) */ +- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0); ++ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0); + +- c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG); ++ c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG); + if (c != 0x98) { + printf("Error anx9804 chipid mismatch\n"); +- i2c_set_bus_num(orig_i2c_bus); + return; + } + + for (i = 0; i < 100; i++) { +- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); +- i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c); +- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); ++ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG); ++ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c); ++ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG); + if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0) + break; + +@@ -66,51 +70,51 @@ + if (i == 100) + printf("Error anx9804 clock is not stable\n"); + +- i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth); +- ++ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth); ++ + /* Set a bunch of analog related register values */ +- i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); +- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); +- i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); +- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); +- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0); +- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99); +- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b); +- i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30); +- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06); ++ dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07); ++ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19); ++ dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9); ++ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); ++ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0); ++ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99); ++ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b); ++ dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30); ++ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06); + + /* Force HPD */ +- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, +- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); ++ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG, ++ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); + + /* Power up and configure lanes */ +- i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); +- i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00); +- i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00); +- i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00); +- i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00); ++ dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); ++ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00); ++ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00); ++ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00); ++ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00); + + /* Reset AUX CH */ +- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, +- ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX); +- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, +- ANX9804_RST_CTRL2_AC_MODE); ++ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ++ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX); ++ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ++ ANX9804_RST_CTRL2_AC_MODE); + + /* Powerdown audio and some other unused bits */ +- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); +- i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00); +- i2c_reg_write(0x38, 0xa7, 0x00); ++ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); ++ dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00); ++ dm_i2c_reg_write(chip0, 0xa7, 0x00); + + /* Set data-rate / lanes */ +- i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate); +- i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); ++ dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate); ++ dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes); + +- /* Link training */ +- i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG, +- ANX9804_LINK_TRAINING_CTRL_EN); ++ /* Link training */ ++ dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG, ++ ANX9804_LINK_TRAINING_CTRL_EN); + mdelay(5); + for (i = 0; i < 100; i++) { +- c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG); ++ c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG); + if ((c & 0x01) == 0) + break; + +@@ -118,17 +122,14 @@ + } + if(i == 100) { + printf("Error anx9804 link training timeout\n"); +- i2c_set_bus_num(orig_i2c_bus); + return; + } + + /* Enable */ +- i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG, +- ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); ++ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG, ++ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); + /* Force stream valid */ +- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, +- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL | +- ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL); +- +- i2c_set_bus_num(orig_i2c_bus); ++ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG, ++ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL | ++ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL); + } +diff -ruN u-boot-2021.10/drivers/video/anx9804.h u-boot/drivers/video/anx9804.h +--- u-boot-2021.10/drivers/video/anx9804.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/anx9804.h 2021-11-01 17:10:14.516245298 +0100 +@@ -16,9 +16,10 @@ + #define ANX9804_DATA_RATE_2700M 0x0a + + #ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 +-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp); ++void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp); + #else +-static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, ++static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, + int bpp) {} + #endif ++ + #endif +diff -ruN u-boot-2021.10/drivers/video/ati_ids.h u-boot/drivers/video/ati_ids.h +--- u-boot-2021.10/drivers/video/ati_ids.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/ati_ids.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,211 +0,0 @@ +-/* +- * ATI PCI IDs from XFree86, kept here to make sync'ing with +- * XFree much simpler. Currently, this list is only used by +- * radeonfb +- */ +- +-#define PCI_CHIP_RV380_3150 0x3150 +-#define PCI_CHIP_RV380_3151 0x3151 +-#define PCI_CHIP_RV380_3152 0x3152 +-#define PCI_CHIP_RV380_3153 0x3153 +-#define PCI_CHIP_RV380_3154 0x3154 +-#define PCI_CHIP_RV380_3156 0x3156 +-#define PCI_CHIP_RV380_3E50 0x3E50 +-#define PCI_CHIP_RV380_3E51 0x3E51 +-#define PCI_CHIP_RV380_3E52 0x3E52 +-#define PCI_CHIP_RV380_3E53 0x3E53 +-#define PCI_CHIP_RV380_3E54 0x3E54 +-#define PCI_CHIP_RV380_3E56 0x3E56 +-#define PCI_CHIP_RS100_4136 0x4136 +-#define PCI_CHIP_RS200_4137 0x4137 +-#define PCI_CHIP_R300_AD 0x4144 +-#define PCI_CHIP_R300_AE 0x4145 +-#define PCI_CHIP_R300_AF 0x4146 +-#define PCI_CHIP_R300_AG 0x4147 +-#define PCI_CHIP_R350_AH 0x4148 +-#define PCI_CHIP_R350_AI 0x4149 +-#define PCI_CHIP_R350_AJ 0x414A +-#define PCI_CHIP_R350_AK 0x414B +-#define PCI_CHIP_RV350_AP 0x4150 +-#define PCI_CHIP_RV350_AQ 0x4151 +-#define PCI_CHIP_RV360_AR 0x4152 +-#define PCI_CHIP_RV350_AS 0x4153 +-#define PCI_CHIP_RV350_AT 0x4154 +-#define PCI_CHIP_RV350_AV 0x4156 +-#define PCI_CHIP_MACH32 0x4158 +-#define PCI_CHIP_RS250_4237 0x4237 +-#define PCI_CHIP_R200_BB 0x4242 +-#define PCI_CHIP_R200_BC 0x4243 +-#define PCI_CHIP_RS100_4336 0x4336 +-#define PCI_CHIP_RS200_4337 0x4337 +-#define PCI_CHIP_MACH64CT 0x4354 +-#define PCI_CHIP_MACH64CX 0x4358 +-#define PCI_CHIP_RS250_4437 0x4437 +-#define PCI_CHIP_MACH64ET 0x4554 +-#define PCI_CHIP_MACH64GB 0x4742 +-#define PCI_CHIP_MACH64GD 0x4744 +-#define PCI_CHIP_MACH64GI 0x4749 +-#define PCI_CHIP_MACH64GL 0x474C +-#define PCI_CHIP_MACH64GM 0x474D +-#define PCI_CHIP_MACH64GN 0x474E +-#define PCI_CHIP_MACH64GO 0x474F +-#define PCI_CHIP_MACH64GP 0x4750 +-#define PCI_CHIP_MACH64GQ 0x4751 +-#define PCI_CHIP_MACH64GR 0x4752 +-#define PCI_CHIP_MACH64GS 0x4753 +-#define PCI_CHIP_MACH64GT 0x4754 +-#define PCI_CHIP_MACH64GU 0x4755 +-#define PCI_CHIP_MACH64GV 0x4756 +-#define PCI_CHIP_MACH64GW 0x4757 +-#define PCI_CHIP_MACH64GX 0x4758 +-#define PCI_CHIP_MACH64GY 0x4759 +-#define PCI_CHIP_MACH64GZ 0x475A +-#define PCI_CHIP_RV250_Id 0x4964 +-#define PCI_CHIP_RV250_Ie 0x4965 +-#define PCI_CHIP_RV250_If 0x4966 +-#define PCI_CHIP_RV250_Ig 0x4967 +-#define PCI_CHIP_R420_JH 0x4A48 +-#define PCI_CHIP_R420_JI 0x4A49 +-#define PCI_CHIP_R420_JJ 0x4A4A +-#define PCI_CHIP_R420_JK 0x4A4B +-#define PCI_CHIP_R420_JL 0x4A4C +-#define PCI_CHIP_R420_JM 0x4A4D +-#define PCI_CHIP_R420_JN 0x4A4E +-#define PCI_CHIP_R420_JP 0x4A50 +-#define PCI_CHIP_MACH64LB 0x4C42 +-#define PCI_CHIP_MACH64LD 0x4C44 +-#define PCI_CHIP_RAGE128LE 0x4C45 +-#define PCI_CHIP_RAGE128LF 0x4C46 +-#define PCI_CHIP_MACH64LG 0x4C47 +-#define PCI_CHIP_MACH64LI 0x4C49 +-#define PCI_CHIP_MACH64LM 0x4C4D +-#define PCI_CHIP_MACH64LN 0x4C4E +-#define PCI_CHIP_MACH64LP 0x4C50 +-#define PCI_CHIP_MACH64LQ 0x4C51 +-#define PCI_CHIP_MACH64LR 0x4C52 +-#define PCI_CHIP_MACH64LS 0x4C53 +-#define PCI_CHIP_MACH64LT 0x4C54 +-#define PCI_CHIP_RADEON_LW 0x4C57 +-#define PCI_CHIP_RADEON_LX 0x4C58 +-#define PCI_CHIP_RADEON_LY 0x4C59 +-#define PCI_CHIP_RADEON_LZ 0x4C5A +-#define PCI_CHIP_RV250_Ld 0x4C64 +-#define PCI_CHIP_RV250_Le 0x4C65 +-#define PCI_CHIP_RV250_Lf 0x4C66 +-#define PCI_CHIP_RV250_Lg 0x4C67 +-#define PCI_CHIP_RV250_Ln 0x4C6E +-#define PCI_CHIP_RAGE128MF 0x4D46 +-#define PCI_CHIP_RAGE128ML 0x4D4C +-#define PCI_CHIP_R300_ND 0x4E44 +-#define PCI_CHIP_R300_NE 0x4E45 +-#define PCI_CHIP_R300_NF 0x4E46 +-#define PCI_CHIP_R300_NG 0x4E47 +-#define PCI_CHIP_R350_NH 0x4E48 +-#define PCI_CHIP_R350_NI 0x4E49 +-#define PCI_CHIP_R360_NJ 0x4E4A +-#define PCI_CHIP_R350_NK 0x4E4B +-#define PCI_CHIP_RV350_NP 0x4E50 +-#define PCI_CHIP_RV350_NQ 0x4E51 +-#define PCI_CHIP_RV350_NR 0x4E52 +-#define PCI_CHIP_RV350_NS 0x4E53 +-#define PCI_CHIP_RV350_NT 0x4E54 +-#define PCI_CHIP_RV350_NV 0x4E56 +-#define PCI_CHIP_RAGE128PA 0x5041 +-#define PCI_CHIP_RAGE128PB 0x5042 +-#define PCI_CHIP_RAGE128PC 0x5043 +-#define PCI_CHIP_RAGE128PD 0x5044 +-#define PCI_CHIP_RAGE128PE 0x5045 +-#define PCI_CHIP_RAGE128PF 0x5046 +-#define PCI_CHIP_RAGE128PG 0x5047 +-#define PCI_CHIP_RAGE128PH 0x5048 +-#define PCI_CHIP_RAGE128PI 0x5049 +-#define PCI_CHIP_RAGE128PJ 0x504A +-#define PCI_CHIP_RAGE128PK 0x504B +-#define PCI_CHIP_RAGE128PL 0x504C +-#define PCI_CHIP_RAGE128PM 0x504D +-#define PCI_CHIP_RAGE128PN 0x504E +-#define PCI_CHIP_RAGE128PO 0x504F +-#define PCI_CHIP_RAGE128PP 0x5050 +-#define PCI_CHIP_RAGE128PQ 0x5051 +-#define PCI_CHIP_RAGE128PR 0x5052 +-#define PCI_CHIP_RAGE128PS 0x5053 +-#define PCI_CHIP_RAGE128PT 0x5054 +-#define PCI_CHIP_RAGE128PU 0x5055 +-#define PCI_CHIP_RAGE128PV 0x5056 +-#define PCI_CHIP_RAGE128PW 0x5057 +-#define PCI_CHIP_RAGE128PX 0x5058 +-#define PCI_CHIP_RADEON_QD 0x5144 +-#define PCI_CHIP_RADEON_QE 0x5145 +-#define PCI_CHIP_RADEON_QF 0x5146 +-#define PCI_CHIP_RADEON_QG 0x5147 +-#define PCI_CHIP_R200_QH 0x5148 +-#define PCI_CHIP_R200_QI 0x5149 +-#define PCI_CHIP_R200_QJ 0x514A +-#define PCI_CHIP_R200_QK 0x514B +-#define PCI_CHIP_R200_QL 0x514C +-#define PCI_CHIP_R200_QM 0x514D +-#define PCI_CHIP_R200_QN 0x514E +-#define PCI_CHIP_R200_QO 0x514F +-#define PCI_CHIP_RV200_QW 0x5157 +-#define PCI_CHIP_RV200_QX 0x5158 +-#define PCI_CHIP_RV100_QY 0x5159 +-#define PCI_CHIP_RV100_QZ 0x515A +-#define PCI_CHIP_RN50 0x515E +-#define PCI_CHIP_RAGE128RE 0x5245 +-#define PCI_CHIP_RAGE128RF 0x5246 +-#define PCI_CHIP_RAGE128RG 0x5247 +-#define PCI_CHIP_RAGE128RK 0x524B +-#define PCI_CHIP_RAGE128RL 0x524C +-#define PCI_CHIP_RAGE128SE 0x5345 +-#define PCI_CHIP_RAGE128SF 0x5346 +-#define PCI_CHIP_RAGE128SG 0x5347 +-#define PCI_CHIP_RAGE128SH 0x5348 +-#define PCI_CHIP_RAGE128SK 0x534B +-#define PCI_CHIP_RAGE128SL 0x534C +-#define PCI_CHIP_RAGE128SM 0x534D +-#define PCI_CHIP_RAGE128SN 0x534E +-#define PCI_CHIP_RAGE128TF 0x5446 +-#define PCI_CHIP_RAGE128TL 0x544C +-#define PCI_CHIP_RAGE128TR 0x5452 +-#define PCI_CHIP_RAGE128TS 0x5453 +-#define PCI_CHIP_RAGE128TT 0x5454 +-#define PCI_CHIP_RAGE128TU 0x5455 +-#define PCI_CHIP_RV370_5460 0x5460 +-#define PCI_CHIP_RV370_5461 0x5461 +-#define PCI_CHIP_RV370_5462 0x5462 +-#define PCI_CHIP_RV370_5463 0x5463 +-#define PCI_CHIP_RV370_5464 0x5464 +-#define PCI_CHIP_RV370_5465 0x5465 +-#define PCI_CHIP_RV370_5466 0x5466 +-#define PCI_CHIP_RV370_5467 0x5467 +-#define PCI_CHIP_R423_UH 0x5548 +-#define PCI_CHIP_R423_UI 0x5549 +-#define PCI_CHIP_R423_UJ 0x554A +-#define PCI_CHIP_R423_UK 0x554B +-#define PCI_CHIP_R423_UQ 0x5551 +-#define PCI_CHIP_R423_UR 0x5552 +-#define PCI_CHIP_R423_UT 0x5554 +-#define PCI_CHIP_MACH64VT 0x5654 +-#define PCI_CHIP_MACH64VU 0x5655 +-#define PCI_CHIP_MACH64VV 0x5656 +-#define PCI_CHIP_RS300_5834 0x5834 +-#define PCI_CHIP_RS300_5835 0x5835 +-#define PCI_CHIP_RS300_5836 0x5836 +-#define PCI_CHIP_RS300_5837 0x5837 +-#define PCI_CHIP_RV370_5B60 0x5B60 +-#define PCI_CHIP_RV370_5B61 0x5B61 +-#define PCI_CHIP_RV370_5B62 0x5B62 +-#define PCI_CHIP_RV370_5B63 0x5B63 +-#define PCI_CHIP_RV370_5B64 0x5B64 +-#define PCI_CHIP_RV370_5B65 0x5B65 +-#define PCI_CHIP_RV370_5B66 0x5B66 +-#define PCI_CHIP_RV370_5B67 0x5B67 +-#define PCI_CHIP_RV280_5960 0x5960 +-#define PCI_CHIP_RV280_5961 0x5961 +-#define PCI_CHIP_RV280_5962 0x5962 +-#define PCI_CHIP_RV280_5964 0x5964 +-#define PCI_CHIP_RV280_5C61 0x5C61 +-#define PCI_CHIP_RV280_5C63 0x5C63 +-#define PCI_CHIP_R423_5D57 0x5D57 +-#define PCI_CHIP_RS350_7834 0x7834 +-#define PCI_CHIP_RS350_7835 0x7835 +diff -ruN u-boot-2021.10/drivers/video/ati_radeon_fb.c u-boot/drivers/video/ati_radeon_fb.c +--- u-boot-2021.10/drivers/video/ati_radeon_fb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/ati_radeon_fb.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,761 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * ATI Radeon Video card Framebuffer driver. +- * +- * Copyright 2007 Freescale Semiconductor, Inc. +- * Zhang Wei <wei.zhang@freescale.com> +- * Jason Jin <jason.jin@freescale.com> +- * +- * Some codes of this file is partly ported from Linux kernel +- * ATI video framebuffer driver. +- * +- * Now the driver is tested on below ATI chips: +- * 9200 +- * X300 +- * X700 +- */ +- +-#include <common.h> +-#include <linux/delay.h> +- +-#include <command.h> +-#include <bios_emul.h> +-#include <env.h> +-#include <pci.h> +-#include <asm/processor.h> +-#include <linux/errno.h> +-#include <asm/io.h> +-#include <malloc.h> +-#include <video_fb.h> +-#include "videomodes.h" +- +-#include <radeon.h> +-#include "ati_ids.h" +-#include "ati_radeon_fb.h" +- +-#undef DEBUG +- +-#ifdef DEBUG +-#define DPRINT(x...) printf(x) +-#else +-#define DPRINT(x...) do{}while(0) +-#endif +- +-#define MAX_MAPPED_VRAM (2048*2048*4) +-#define MIN_MAPPED_VRAM (1024*768*1) +- +-#define RADEON_BUFFER_ALIGN 0x00000fff +-#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ +- & ~RADEON_BUFFER_ALIGN) - 1) +-#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ +- ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) +- +-#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ +- (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) +-#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ +- (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) +-#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ +- ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) +-#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ +- ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) +- +-/*#define PCI_VENDOR_ID_ATI*/ +-#define PCI_CHIP_RV280_5960 0x5960 +-#define PCI_CHIP_RV280_5961 0x5961 +-#define PCI_CHIP_RV280_5962 0x5962 +-#define PCI_CHIP_RV280_5964 0x5964 +-#define PCI_CHIP_RV280_5C63 0x5C63 +-#define PCI_CHIP_RV370_5B60 0x5B60 +-#define PCI_CHIP_RV380_5657 0x5657 +-#define PCI_CHIP_R420_554d 0x554d +- +-static struct pci_device_id ati_radeon_pci_ids[] = { +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, +- {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, +- {0, 0} +-}; +- +-static u16 ati_radeon_id_family_table[][2] = { +- {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, +- {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, +- {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, +- {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, +- {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, +- {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, +- {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, +- {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, +- {0, 0} +-}; +- +-u16 get_radeon_id_family(u16 device) +-{ +- int i; +- for (i=0; ati_radeon_id_family_table[0][i]; i+=2) +- if (ati_radeon_id_family_table[0][i] == device) +- return ati_radeon_id_family_table[0][i + 1]; +- return 0; +-} +- +-struct radeonfb_info *rinfo; +- +-static void radeon_identify_vram(struct radeonfb_info *rinfo) +-{ +- u32 tmp; +- +- /* framebuffer size */ +- if ((rinfo->family == CHIP_FAMILY_RS100) || +- (rinfo->family == CHIP_FAMILY_RS200) || +- (rinfo->family == CHIP_FAMILY_RS300)) { +- u32 tom = INREG(NB_TOM); +- tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); +- +- radeon_fifo_wait(6); +- OUTREG(MC_FB_LOCATION, tom); +- OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); +- OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); +- OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); +- +- /* This is supposed to fix the crtc2 noise problem. */ +- OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); +- +- if ((rinfo->family == CHIP_FAMILY_RS100) || +- (rinfo->family == CHIP_FAMILY_RS200)) { +- /* This is to workaround the asic bug for RMX, some versions +- of BIOS dosen't have this register initialized correctly. +- */ +- OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, +- ~CRTC_H_CUTOFF_ACTIVE_EN); +- } +- } else { +- tmp = INREG(CONFIG_MEMSIZE); +- } +- +- /* mem size is bits [28:0], mask off the rest */ +- rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; +- +- /* +- * Hack to get around some busted production M6's +- * reporting no ram +- */ +- if (rinfo->video_ram == 0) { +- switch (rinfo->pdev.device) { +- case PCI_CHIP_RADEON_LY: +- case PCI_CHIP_RADEON_LZ: +- rinfo->video_ram = 8192 * 1024; +- break; +- default: +- break; +- } +- } +- +- /* +- * Now try to identify VRAM type +- */ +- if ((rinfo->family >= CHIP_FAMILY_R300) || +- (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) +- rinfo->vram_ddr = 1; +- else +- rinfo->vram_ddr = 0; +- +- tmp = INREG(MEM_CNTL); +- if (IS_R300_VARIANT(rinfo)) { +- tmp &= R300_MEM_NUM_CHANNELS_MASK; +- switch (tmp) { +- case 0: rinfo->vram_width = 64; break; +- case 1: rinfo->vram_width = 128; break; +- case 2: rinfo->vram_width = 256; break; +- default: rinfo->vram_width = 128; break; +- } +- } else if ((rinfo->family == CHIP_FAMILY_RV100) || +- (rinfo->family == CHIP_FAMILY_RS100) || +- (rinfo->family == CHIP_FAMILY_RS200)){ +- if (tmp & RV100_MEM_HALF_MODE) +- rinfo->vram_width = 32; +- else +- rinfo->vram_width = 64; +- } else { +- if (tmp & MEM_NUM_CHANNELS_MASK) +- rinfo->vram_width = 128; +- else +- rinfo->vram_width = 64; +- } +- +- /* This may not be correct, as some cards can have half of channel disabled +- * ToDo: identify these cases +- */ +- +- DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", +- rinfo->video_ram / 1024, +- rinfo->vram_ddr ? "DDR" : "SDRAM", +- rinfo->vram_width); +- +-} +- +-static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +-{ +- int i; +- +- radeon_fifo_wait(20); +- +-#if 0 +- /* Workaround from XFree */ +- if (rinfo->is_mobility) { +- /* A temporal workaround for the occational blanking on certain laptop +- * panels. This appears to related to the PLL divider registers +- * (fail to lock?). It occurs even when all dividers are the same +- * with their old settings. In this case we really don't need to +- * fiddle with PLL registers. By doing this we can avoid the blanking +- * problem with some panels. +- */ +- if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && +- (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & +- (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { +- /* We still have to force a switch to selected PPLL div thanks to +- * an XFree86 driver bug which will switch it away in some cases +- * even when using UseFDev */ +- OUTREGP(CLOCK_CNTL_INDEX, +- mode->clk_cntl_index & PPLL_DIV_SEL_MASK, +- ~PPLL_DIV_SEL_MASK); +- radeon_pll_errata_after_index(rinfo); +- radeon_pll_errata_after_data(rinfo); +- return; +- } +- } +-#endif +- if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; +- +- /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ +- OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); +- +- /* Reset PPLL & enable atomic update */ +- OUTPLLP(PPLL_CNTL, +- PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, +- ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); +- +- /* Switch to selected PPLL divider */ +- OUTREGP(CLOCK_CNTL_INDEX, +- mode->clk_cntl_index & PPLL_DIV_SEL_MASK, +- ~PPLL_DIV_SEL_MASK); +- +- /* Set PPLL ref. div */ +- if (rinfo->family == CHIP_FAMILY_R300 || +- rinfo->family == CHIP_FAMILY_RS300 || +- rinfo->family == CHIP_FAMILY_R350 || +- rinfo->family == CHIP_FAMILY_RV350) { +- if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { +- /* When restoring console mode, use saved PPLL_REF_DIV +- * setting. +- */ +- OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); +- } else { +- /* R300 uses ref_div_acc field as real ref divider */ +- OUTPLLP(PPLL_REF_DIV, +- (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), +- ~R300_PPLL_REF_DIV_ACC_MASK); +- } +- } else +- OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); +- +- /* Set PPLL divider 3 & post divider*/ +- OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); +- OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); +- +- /* Write update */ +- while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) +- ; +- OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); +- +- /* Wait read update complete */ +- /* FIXME: Certain revisions of R300 can't recover here. Not sure of +- the cause yet, but this workaround will mask the problem for now. +- Other chips usually will pass at the very first test, so the +- workaround shouldn't have any effect on them. */ +- for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) +- ; +- +- OUTPLL(HTOTAL_CNTL, 0); +- +- /* Clear reset & atomic update */ +- OUTPLLP(PPLL_CNTL, 0, +- ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); +- +- /* We may want some locking ... oh well */ +- udelay(5000); +- +- /* Switch back VCLK source to PPLL */ +- OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +-} +- +-typedef struct { +- u16 reg; +- u32 val; +-} reg_val; +- +-#if 0 /* unused ? -> scheduled for removal */ +-/* these common regs are cleared before mode setting so they do not +- * interfere with anything +- */ +-static reg_val common_regs[] = { +- { OVR_CLR, 0 }, +- { OVR_WID_LEFT_RIGHT, 0 }, +- { OVR_WID_TOP_BOTTOM, 0 }, +- { OV0_SCALE_CNTL, 0 }, +- { SUBPIC_CNTL, 0 }, +- { VIPH_CONTROL, 0 }, +- { I2C_CNTL_1, 0 }, +- { GEN_INT_CNTL, 0 }, +- { CAP0_TRIG_CNTL, 0 }, +- { CAP1_TRIG_CNTL, 0 }, +-}; +-#endif /* 0 */ +- +-void radeon_setmode(void) +-{ +- struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); +- +- mode->crtc_gen_cntl = 0x03000200; +- mode->crtc_ext_cntl = 0x00008048; +- mode->dac_cntl = 0xff002100; +- mode->crtc_h_total_disp = 0x4f0063; +- mode->crtc_h_sync_strt_wid = 0x8c02a2; +- mode->crtc_v_total_disp = 0x01df020c; +- mode->crtc_v_sync_strt_wid = 0x8201ea; +- mode->crtc_pitch = 0x00500050; +- +- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); +- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, +- ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); +- OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); +- OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); +- OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); +- OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); +- OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); +- OUTREG(CRTC_OFFSET, 0); +- OUTREG(CRTC_OFFSET_CNTL, 0); +- OUTREG(CRTC_PITCH, mode->crtc_pitch); +- +- mode->clk_cntl_index = 0x300; +- mode->ppll_ref_div = 0xc; +- mode->ppll_div_3 = 0x00030059; +- +- radeon_write_pll_regs(rinfo, mode); +-} +- +-static void set_pal(void) +-{ +- int idx, val = 0; +- +- for (idx = 0; idx < 256; idx++) { +- OUTREG8(PALETTE_INDEX, idx); +- OUTREG(PALETTE_DATA, val); +- val += 0x00010101; +- } +-} +- +-void radeon_setmode_9200(int vesa_idx, int bpp) +-{ +- struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); +- +- mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; +- mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; +- mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; +- mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; +- +- switch (bpp) { +- case 24: +- mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ +-#if defined(__BIG_ENDIAN) +- mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; +- mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; +-#endif +- break; +- case 16: +- mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ +-#if defined(__BIG_ENDIAN) +- mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; +- mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; +-#endif +- break; +- default: +- mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ +- mode->surface_cntl = 0x00000000; +- break; +- } +- +- switch (vesa_idx) { +- case RES_MODE_1280x1024: +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); +-#if defined(CONFIG_RADEON_VREFRESH_75HZ) +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); +- mode->ppll_div_3 = 0x00010078; +-#else /* default @ 60 Hz */ +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); +- mode->ppll_div_3 = 0x00010060; +-#endif +- /* +- * for this mode pitch expands to the same value for 32, 16 and 8 bpp, +- * so we set it here once only. +- */ +- mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); +- switch (bpp) { +- case 24: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); +- break; +- case 16: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); +- break; +- default: /* 8 bpp */ +- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); +- break; +- } +- break; +- case RES_MODE_1024x768: +-#if defined(CONFIG_RADEON_VREFRESH_75HZ) +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); +- mode->ppll_div_3 = 0x0002008c; +-#else /* @ 60 Hz */ +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; +- mode->ppll_div_3 = 0x00020074; +-#endif +- /* also same pitch value for 32, 16 and 8 bpp */ +- mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); +- switch (bpp) { +- case 24: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); +- break; +- case 16: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); +- break; +- default: /* 8 bpp */ +- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); +- break; +- } +- break; +- case RES_MODE_800x600: +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); +-#if defined(CONFIG_RADEON_VREFRESH_75HZ) +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); +- mode->ppll_div_3 = 0x000300b0; +-#else /* @ 60 Hz */ +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); +- mode->ppll_div_3 = 0x0003008e; +-#endif +- switch (bpp) { +- case 24: +- mode->crtc_pitch = RADEON_CRT_PITCH(832,32); +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); +- break; +- case 16: +- mode->crtc_pitch = RADEON_CRT_PITCH(896,16); +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); +- break; +- default: /* 8 bpp */ +- mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); +- mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); +- break; +- } +- break; +- default: /* RES_MODE_640x480 */ +-#if defined(CONFIG_RADEON_VREFRESH_75HZ) +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; +- mode->ppll_div_3 = 0x00030070; +-#else /* @ 60 Hz */ +- mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); +- mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; +- mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); +- mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; +- mode->ppll_div_3 = 0x00030059; +-#endif +- /* also same pitch value for 32, 16 and 8 bpp */ +- mode->crtc_pitch = RADEON_CRT_PITCH(640,32); +- switch (bpp) { +- case 24: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); +- break; +- case 16: +- mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); +- mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); +- break; +- default: /* 8 bpp */ +- mode->crtc_offset_cntl = 0x00000000; +- break; +- } +- break; +- } +- +- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); +- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, +- (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); +- OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); +- OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); +- OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); +- OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); +- OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); +- OUTREG(CRTC_OFFSET, 0); +- OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); +- OUTREG(CRTC_PITCH, mode->crtc_pitch); +- OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); +- +- mode->clk_cntl_index = 0x300; +- mode->ppll_ref_div = 0xc; +- +- radeon_write_pll_regs(rinfo, mode); +- +- OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, +- ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); +- OUTREG(SURFACE0_INFO, mode->surf_info[0]); +- OUTREG(SURFACE0_LOWER_BOUND, 0); +- OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); +- OUTREG(SURFACE_CNTL, mode->surface_cntl); +- +- if (bpp > 8) +- set_pal(); +- +- free(mode); +-} +- +-#include "../bios_emulator/include/biosemu.h" +- +-int radeon_probe(struct radeonfb_info *rinfo) +-{ +- pci_dev_t pdev; +- u16 did; +- +- pdev = pci_find_devices(ati_radeon_pci_ids, 0); +- +- if (pdev != -1) { +- pci_read_config_word(pdev, PCI_DEVICE_ID, &did); +- printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", +- PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, +- (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); +- +- strcpy(rinfo->name, "ATI Radeon"); +- rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; +- rinfo->pdev.device = did; +- rinfo->family = get_radeon_id_family(rinfo->pdev.device); +- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, +- &rinfo->fb_base_bus); +- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, +- &rinfo->mmio_base_bus); +- rinfo->fb_base_bus &= 0xfffff000; +- rinfo->mmio_base_bus &= ~0x04; +- +- rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, +- PCI_REGION_MEM, 0, MAP_NOCACHE); +- DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", +- rinfo->mmio_base, rinfo->mmio_base_bus); +- rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; +- DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); +- /* PostBIOS with x86 emulater */ +- if (!BootVideoCardBIOS(pdev, NULL, 0)) +- return -1; +- +- /* +- * Check for errata +- * (These will be added in the future for the chipfamily +- * R300, RV200, RS200, RV100, RS100.) +- */ +- +- /* Get VRAM size and type */ +- radeon_identify_vram(rinfo); +- +- rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, +- rinfo->video_ram); +- rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, +- PCI_REGION_MEM, 0, MAP_NOCACHE); +- DPRINT("Radeon: framebuffer base address 0x%08x, " +- "bus address 0x%08x\n" +- "MMIO base address 0x%08x, bus address 0x%08x, " +- "framebuffer local base 0x%08x.\n ", +- (u32)rinfo->fb_base, rinfo->fb_base_bus, +- (u32)rinfo->mmio_base, rinfo->mmio_base_bus, +- rinfo->fb_local_base); +- return 0; +- } +- return -1; +-} +- +-/* +- * The Graphic Device +- */ +-GraphicDevice ctfb; +- +-#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +-#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +-#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +-#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ +- +-void *video_hw_init(void) +-{ +- GraphicDevice *pGD = (GraphicDevice *) & ctfb; +- u32 *vm; +- char *penv; +- unsigned long t1, hsynch, vsynch; +- int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; +- struct ctfb_res_modes *res_mode; +- struct ctfb_res_modes var_mode; +- +- rinfo = malloc(sizeof(struct radeonfb_info)); +- +- printf("Video: "); +- if(radeon_probe(rinfo)) { +- printf("No radeon video card found!\n"); +- return NULL; +- } +- +- tmp = 0; +- +- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; +- /* get video mode via environment */ +- penv = env_get("videomode"); +- if (penv) { +- /* deceide if it is a string */ +- if (penv[0] <= '9') { +- videomode = (int)hextoul(penv, NULL); +- tmp = 1; +- } +- } else { +- tmp = 1; +- } +- if (tmp) { +- /* parameter are vesa modes */ +- /* search params */ +- for (i = 0; i < VESA_MODES_COUNT; i++) { +- if (vesa_modes[i].vesanr == videomode) +- break; +- } +- if (i == VESA_MODES_COUNT) { +- printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); +- i = 0; +- } +- res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; +- bits_per_pixel = vesa_modes[i].bits_per_pixel; +- vesa_idx = vesa_modes[i].resindex; +- } else { +- res_mode = (struct ctfb_res_modes *) &var_mode; +- bits_per_pixel = video_get_params (res_mode, penv); +- } +- +- /* calculate hsynch and vsynch freq (info only) */ +- t1 = (res_mode->left_margin + res_mode->xres + +- res_mode->right_margin + res_mode->hsync_len) / 8; +- t1 *= 8; +- t1 *= res_mode->pixclock; +- t1 /= 1000; +- hsynch = 1000000000L / t1; +- t1 *= (res_mode->upper_margin + res_mode->yres + +- res_mode->lower_margin + res_mode->vsync_len); +- t1 /= 1000; +- vsynch = 1000000000L / t1; +- +- /* fill in Graphic device struct */ +- sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, +- res_mode->yres, bits_per_pixel, (hsynch / 1000), +- (vsynch / 1000)); +- printf ("%s\n", pGD->modeIdent); +- pGD->winSizeX = res_mode->xres; +- pGD->winSizeY = res_mode->yres; +- pGD->plnSizeX = res_mode->xres; +- pGD->plnSizeY = res_mode->yres; +- +- switch (bits_per_pixel) { +- case 24: +- pGD->gdfBytesPP = 4; +- pGD->gdfIndex = GDF_32BIT_X888RGB; +- if (res_mode->xres == 800) { +- pGD->winSizeX = 832; +- pGD->plnSizeX = 832; +- } +- break; +- case 16: +- pGD->gdfBytesPP = 2; +- pGD->gdfIndex = GDF_16BIT_565RGB; +- if (res_mode->xres == 800) { +- pGD->winSizeX = 896; +- pGD->plnSizeX = 896; +- } +- break; +- default: +- if (res_mode->xres == 800) { +- pGD->winSizeX = 1024; +- pGD->plnSizeX = 1024; +- } +- pGD->gdfBytesPP = 1; +- pGD->gdfIndex = GDF__8BIT_INDEX; +- break; +- } +- +- pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; +- pGD->pciBase = (unsigned int)rinfo->fb_base; +- pGD->frameAdrs = (unsigned int)rinfo->fb_base; +- pGD->memSize = 64 * 1024 * 1024; +- +- /* Cursor Start Address */ +- pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + +- (unsigned int)rinfo->fb_base; +- if ((pGD->dprBase & 0x0fff) != 0) { +- /* allign it */ +- pGD->dprBase &= 0xfffff000; +- pGD->dprBase += 0x00001000; +- } +- DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, +- PATTERN_ADR); +- pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ +- pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ +- /* set up Hardware */ +- +- /* Clear video memory (only visible screen area) */ +- i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; +- vm = (unsigned int *) pGD->pciBase; +- while (i--) +- *vm++ = 0; +- /*SetDrawingEngine (bits_per_pixel);*/ +- +- if (rinfo->family == CHIP_FAMILY_RV280) +- radeon_setmode_9200(vesa_idx, bits_per_pixel); +- else +- radeon_setmode(); +- +- return ((void *) pGD); +-} +- +-void video_set_lut (unsigned int index, /* color number */ +- unsigned char r, /* red */ +- unsigned char g, /* green */ +- unsigned char b /* blue */ +- ) +-{ +- OUTREG(PALETTE_INDEX, index); +- OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); +-} +diff -ruN u-boot-2021.10/drivers/video/ati_radeon_fb.h u-boot/drivers/video/ati_radeon_fb.h +--- u-boot-2021.10/drivers/video/ati_radeon_fb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/ati_radeon_fb.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,282 +0,0 @@ +-#ifndef __ATI_RADEON_FB_H +-#define __ATI_RADEON_FB_H +- +-/*************************************************************** +- * Most of the definitions here are adapted right from XFree86 * +- ***************************************************************/ +- +-/* +- * Chip families. Must fit in the low 16 bits of a long word +- */ +-enum radeon_family { +- CHIP_FAMILY_UNKNOW, +- CHIP_FAMILY_LEGACY, +- CHIP_FAMILY_RADEON, +- CHIP_FAMILY_RV100, +- CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ +- CHIP_FAMILY_RV200, +- CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), +- RS250 (IGP 7000) */ +- CHIP_FAMILY_R200, +- CHIP_FAMILY_RV250, +- CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ +- CHIP_FAMILY_RV280, +- CHIP_FAMILY_R300, +- CHIP_FAMILY_R350, +- CHIP_FAMILY_RV350, +- CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ +- CHIP_FAMILY_R420, /* R420/R423/M18 */ +- CHIP_FAMILY_LAST, +-}; +- +-#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ +- ((rinfo)->family == CHIP_FAMILY_RV200) || \ +- ((rinfo)->family == CHIP_FAMILY_RS100) || \ +- ((rinfo)->family == CHIP_FAMILY_RS200) || \ +- ((rinfo)->family == CHIP_FAMILY_RV250) || \ +- ((rinfo)->family == CHIP_FAMILY_RV280) || \ +- ((rinfo)->family == CHIP_FAMILY_RS300)) +- +-#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ +- ((rinfo)->family == CHIP_FAMILY_RV350) || \ +- ((rinfo)->family == CHIP_FAMILY_R350) || \ +- ((rinfo)->family == CHIP_FAMILY_RV380) || \ +- ((rinfo)->family == CHIP_FAMILY_R420)) +- +-struct radeonfb_info { +- char name[20]; +- +- struct pci_device_id pdev; +- u16 family; +- +- u32 fb_base_bus; +- u32 mmio_base_bus; +- +- void *mmio_base; +- void *fb_base; +- +- u32 video_ram; +- u32 mapped_vram; +- int vram_width; +- int vram_ddr; +- +- u32 fb_local_base; +-}; +- +-#define INREG8(addr) readb((rinfo->mmio_base)+addr) +-#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) +-#define INREG16(addr) readw((rinfo->mmio_base)+addr) +-#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) +-#define INREG(addr) readl((rinfo->mmio_base)+addr) +-#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) +- +-static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, +- u32 val, u32 mask) +-{ +- unsigned int tmp; +- +- tmp = INREG(addr); +- tmp &= (mask); +- tmp |= (val); +- OUTREG(addr, tmp); +-} +- +-#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) +- +-/* +- * 2D Engine helper routines +- */ +-static inline void radeon_engine_flush (struct radeonfb_info *rinfo) +-{ +- int i; +- +- /* initiate flush */ +- OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, +- ~RB2D_DC_FLUSH_ALL); +- +- for (i=0; i < 2000000; i++) { +- if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) +- return; +- udelay(1); +- } +- printf("radeonfb: Flush Timeout !\n"); +-} +- +-static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +-{ +- int i; +- +- for (i=0; i<2000000; i++) { +- if ((INREG(RBBM_STATUS) & 0x7f) >= entries) +- return; +- udelay(1); +- } +- printf("radeonfb: FIFO Timeout !\n"); +-} +- +-static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) +-{ +- int i; +- +- /* ensure FIFO is empty before waiting for idle */ +- _radeon_fifo_wait (rinfo, 64); +- +- for (i=0; i<2000000; i++) { +- if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { +- radeon_engine_flush (rinfo); +- return; +- } +- udelay(1); +- } +- printf("radeonfb: Idle Timeout !\n"); +-} +- +-#define radeon_engine_idle() _radeon_engine_idle(rinfo) +-#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) +-#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) +- +-/* +- * This structure contains the various registers manipulated by this +- * driver for setting or restoring a mode. It's mostly copied from +- * XFree's RADEONSaveRec structure. A few chip settings might still be +- * tweaked without beeing reflected or saved in these registers though +- */ +-struct radeon_regs { +- /* Common registers */ +- u32 ovr_clr; +- u32 ovr_wid_left_right; +- u32 ovr_wid_top_bottom; +- u32 ov0_scale_cntl; +- u32 mpp_tb_config; +- u32 mpp_gp_config; +- u32 subpic_cntl; +- u32 viph_control; +- u32 i2c_cntl_1; +- u32 gen_int_cntl; +- u32 cap0_trig_cntl; +- u32 cap1_trig_cntl; +- u32 bus_cntl; +- u32 surface_cntl; +- u32 bios_5_scratch; +- +- /* Other registers to save for VT switches or driver load/unload */ +- u32 dp_datatype; +- u32 rbbm_soft_reset; +- u32 clock_cntl_index; +- u32 amcgpio_en_reg; +- u32 amcgpio_mask; +- +- /* Surface/tiling registers */ +- u32 surf_lower_bound[8]; +- u32 surf_upper_bound[8]; +- u32 surf_info[8]; +- +- /* CRTC registers */ +- u32 crtc_gen_cntl; +- u32 crtc_ext_cntl; +- u32 dac_cntl; +- u32 crtc_h_total_disp; +- u32 crtc_h_sync_strt_wid; +- u32 crtc_v_total_disp; +- u32 crtc_v_sync_strt_wid; +- u32 crtc_offset; +- u32 crtc_offset_cntl; +- u32 crtc_pitch; +- u32 disp_merge_cntl; +- u32 grph_buffer_cntl; +- u32 crtc_more_cntl; +- +- /* CRTC2 registers */ +- u32 crtc2_gen_cntl; +- u32 dac2_cntl; +- u32 disp_output_cntl; +- u32 disp_hw_debug; +- u32 disp2_merge_cntl; +- u32 grph2_buffer_cntl; +- u32 crtc2_h_total_disp; +- u32 crtc2_h_sync_strt_wid; +- u32 crtc2_v_total_disp; +- u32 crtc2_v_sync_strt_wid; +- u32 crtc2_offset; +- u32 crtc2_offset_cntl; +- u32 crtc2_pitch; +- +- /* Flat panel regs */ +- u32 fp_crtc_h_total_disp; +- u32 fp_crtc_v_total_disp; +- u32 fp_gen_cntl; +- u32 fp2_gen_cntl; +- u32 fp_h_sync_strt_wid; +- u32 fp2_h_sync_strt_wid; +- u32 fp_horz_stretch; +- u32 fp_panel_cntl; +- u32 fp_v_sync_strt_wid; +- u32 fp2_v_sync_strt_wid; +- u32 fp_vert_stretch; +- u32 lvds_gen_cntl; +- u32 lvds_pll_cntl; +- u32 tmds_crc; +- u32 tmds_transmitter_cntl; +- +- /* Computed values for PLL */ +- u32 dot_clock_freq; +- int feedback_div; +- int post_div; +- +- /* PLL registers */ +- u32 ppll_div_3; +- u32 ppll_ref_div; +- u32 vclk_ecp_cntl; +- u32 clk_cntl_index; +- +- /* Computed values for PLL2 */ +- u32 dot_clock_freq_2; +- int feedback_div_2; +- int post_div_2; +- +- /* PLL2 registers */ +- u32 p2pll_ref_div; +- u32 p2pll_div_0; +- u32 htotal_cntl2; +- +- /* Palette */ +- int palette_valid; +-}; +- +-static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) +-{ +- u32 data; +- +- OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); +- /* radeon_pll_errata_after_index(rinfo); */ +- data = INREG(CLOCK_CNTL_DATA); +- /* radeon_pll_errata_after_data(rinfo); */ +- return data; +-} +- +-static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, +- u32 val) +-{ +- +- OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); +- /* radeon_pll_errata_after_index(rinfo); */ +- OUTREG(CLOCK_CNTL_DATA, val); +- /* radeon_pll_errata_after_data(rinfo); */ +-} +- +-static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, +- u32 val, u32 mask) +-{ +- unsigned int tmp; +- +- tmp = __INPLL(rinfo, index); +- tmp &= (mask); +- tmp |= (val); +- __OUTPLL(rinfo, index, tmp); +-} +- +-#define INPLL(addr) __INPLL(rinfo, addr) +-#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) +-#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) +- +-#endif +diff -ruN u-boot-2021.10/drivers/video/bus_vcxk.c u-boot/drivers/video/bus_vcxk.c +--- u-boot-2021.10/drivers/video/bus_vcxk.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/bus_vcxk.c 2021-11-01 17:10:14.516245298 +0100 +@@ -63,8 +63,8 @@ + + #ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED + #define VCXK_BWS(x, data) vcxk_bws[x] = data; +- #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask; +- #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask; ++ #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask; ++ #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask; + #define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data; + #else + u_char double_bws[16384]; +@@ -83,7 +83,7 @@ + #endif + + #define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2] +-#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2] ++#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2] + #define VC2K_Bright vcxk_bws[0x8000] + #define VC8K_BrightH vcxk_bws[0xC000] + #define VC8K_BrightL vcxk_bws[0xC001] +@@ -263,7 +263,7 @@ + * set the display brightness + * PARAMETER + * side 1 set front side brightness +- * 2 set back side brightness ++ * 2 set back side brightness + * 3 set brightness for both sides + * brightness 0..1000 + *** +@@ -276,7 +276,7 @@ + VC4K16_Bright1 = brightness + 23; + if ((side == 0) || (side & 0x2)) + VC4K16_Bright2 = brightness + 23; +- } else { ++ } else { + VC2K_Bright = (brightness >> 4) + 2; + VC8K_BrightH = (brightness + 23) >> 8; + VC8K_BrightL = (brightness + 23) & 0xFF; +diff -ruN u-boot-2021.10/drivers/video/cfb_console.c u-boot/drivers/video/cfb_console.c +--- u-boot-2021.10/drivers/video/cfb_console.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/cfb_console.c 2021-11-01 17:10:14.516245298 +0100 +@@ -71,10 +71,11 @@ + #include <fdtdec.h> + #include <gzip.h> + #include <log.h> +-#include <version.h> ++#include <version_string.h> + #include <malloc.h> + #include <video.h> + #include <asm/global_data.h> ++#include <dm/ofnode.h> + #include <linux/compiler.h> + + #if defined(CONFIG_VIDEO_MXS) +@@ -108,7 +109,6 @@ + * Console device + */ + +-#include <version.h> + #include <linux/types.h> + #include <stdio_dev.h> + #include <video_font.h> +@@ -2138,8 +2138,7 @@ + #if defined(CONFIG_VGA_AS_SINGLE_DEVICE) + have_keyboard = false; + #elif defined(CONFIG_OF_CONTROL) +- have_keyboard = !fdtdec_get_config_bool(gd->fdt_blob, +- "u-boot,no-keyboard"); ++ have_keyboard = !ofnode_conf_read_bool("u-boot,no-keyboard"); + #else + have_keyboard = true; + #endif +diff -ruN u-boot-2021.10/drivers/video/exynos/exynos_mipi_dsi.c u-boot/drivers/video/exynos/exynos_mipi_dsi.c +--- u-boot-2021.10/drivers/video/exynos/exynos_mipi_dsi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/exynos/exynos_mipi_dsi.c 2021-11-01 17:10:14.519578448 +0100 +@@ -288,8 +288,8 @@ + dt->rx_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-rx-timeout", 0); + +- lcd_dt->name = fdtdec_get_config_string(blob, +- "samsung,dsim-device-name"); ++ lcd_dt->name = fdt_getprop(blob, node, "samsung,dsim-device-name", ++ NULL); + + lcd_dt->id = fdtdec_get_int(blob, node, + "samsung,dsim-device-id", 0); +diff -ruN u-boot-2021.10/drivers/video/hitachi_tx18d42vm_lcd.c u-boot/drivers/video/hitachi_tx18d42vm_lcd.c +--- u-boot-2021.10/drivers/video/hitachi_tx18d42vm_lcd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/hitachi_tx18d42vm_lcd.c 2021-11-01 17:10:14.522911599 +0100 +@@ -49,9 +49,9 @@ + }; + int i, cs, clk, mosi, ret = 0; + +- cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); +- clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK); +- mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI); ++ cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); ++ clk = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK); ++ mosi = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI); + + if (cs == -1 || clk == -1 || mosi == 1) { + printf("Error tx18d42vm spi gpio config is invalid\n"); +diff -ruN u-boot-2021.10/drivers/video/Kconfig u-boot/drivers/video/Kconfig +--- u-boot-2021.10/drivers/video/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/Kconfig 2021-11-01 17:10:14.516245298 +0100 +@@ -259,7 +259,6 @@ + + config VIDEO_VESA + bool "Enable VESA video driver support" +- default n + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use +@@ -406,7 +405,6 @@ + + config VIDEO_LCD_ANX9804 + bool "ANX9804 bridge chip" +- default n + ---help--- + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP +@@ -416,7 +414,6 @@ + bool "OTM8009A DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI +- default n + help + Say Y here if you want to enable support for Orise Technology + otm8009a 480x800 dsi 2dl panel. +@@ -425,14 +422,12 @@ + bool "RM68200 DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI +- default n + help + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. + + config VIDEO_LCD_SSD2828 + bool "SSD2828 bridge chip" +- default n + ---help--- + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI +@@ -457,20 +452,18 @@ + default "" + ---help--- + The reset pin of SSD2828 chip. This takes a string in the format +- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. ++ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + + config VIDEO_LCD_TDO_TL070WSH30 + bool "TDO TL070WSH30 DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI +- default n + help + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. + + config VIDEO_LCD_HITACHI_TX18D42VM + bool "Hitachi tx18d42vm LVDS LCD panel support" +- default n + ---help--- + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is +@@ -484,7 +477,7 @@ + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format +- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. ++ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + + config VIDEO_LCD_SPI_SCLK + string "SPI SCLK pin for LCD related config job" +@@ -494,7 +487,7 @@ + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format +- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. ++ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + + config VIDEO_LCD_SPI_MOSI + string "SPI MOSI pin for LCD related config job" +@@ -504,7 +497,7 @@ + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format +- understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. ++ understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + + config VIDEO_LCD_SPI_MISO + string "SPI MISO pin for LCD related config job (optional)" +@@ -516,14 +509,13 @@ + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The +- option takes a string in the format understood by 'name_to_gpio' ++ option takes a string in the format understood by 'sunxi_name_to_gpio' + function, e.g. PH1 for pin 1 of port H. + + source "drivers/video/meson/Kconfig" + + config VIDEO_MVEBU + bool "Armada XP LCD controller" +- default n + ---help--- + Support for the LCD controller integrated in the Marvell + Armada XP SoC. +@@ -536,14 +528,12 @@ + + config I2C_EDID + bool "Enable EDID library" +- default n + help + This enables library for accessing EDID data from an LCD panel. + + config DISPLAY + bool "Enable Display support" + depends on DM +- default n + select I2C_EDID + help + This supports drivers that provide a display, such as eDP (Embedded +@@ -554,7 +544,6 @@ + config NXP_TDA19988 + bool "Enable NXP TDA19988 support" + depends on DISPLAY +- default n + help + This enables support for the NXP TDA19988 HDMI encoder. This encoder + will convert RGB data streams into HDMI-encoded signals. +@@ -868,7 +857,6 @@ + config OSD + bool "Enable OSD support" + depends on DM +- default n + help + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on +@@ -1008,7 +996,6 @@ + + config VIDEO_VCXK + bool "Enable VCXK video controller driver support" +- default n + help + This enables VCXK driver which can be used with VC2K, VC4K + and VC8K devices on various boards from BuS Elektronik GmbH. +diff -ruN u-boot-2021.10/drivers/video/Makefile u-boot/drivers/video/Makefile +--- u-boot-2021.10/drivers/video/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/Makefile 2021-11-01 17:10:14.516245298 +0100 +@@ -25,7 +25,6 @@ + obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ + obj-y += ti/ + +-obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o + obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o + obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o + obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o +diff -ruN u-boot-2021.10/drivers/video/mxsfb.c u-boot/drivers/video/mxsfb.c +--- u-boot-2021.10/drivers/video/mxsfb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/mxsfb.c 2021-11-01 17:10:14.526244750 +0100 +@@ -54,7 +54,7 @@ + * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel: + * setenv videomode + * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851, +- * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 ++ * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 + */ + + static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, +diff -ruN u-boot-2021.10/drivers/video/pxa_lcd.c u-boot/drivers/video/pxa_lcd.c +--- u-boot-2021.10/drivers/video/pxa_lcd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/pxa_lcd.c 2021-11-01 17:10:14.529577902 +0100 +@@ -199,72 +199,6 @@ + + /*----------------------------------------------------------------------*/ + +-#ifdef CONFIG_ACX517AKN +- +-# define LCD_BPP LCD_COLOR8 +- +-/* you have to set lccr0 and lccr3 (including pcd) */ +-# define REG_LCCR0 0x003008f9 +-# define REG_LCCR3 0x03700006 +- +-vidinfo_t panel_info = { +- .vl_col = 320, +- .vl_row = 320, +- .vl_width = 320, +- .vl_height = 320, +- .vl_clkp = CONFIG_SYS_HIGH, +- .vl_oep = CONFIG_SYS_LOW, +- .vl_hsp = CONFIG_SYS_LOW, +- .vl_vsp = CONFIG_SYS_LOW, +- .vl_dp = CONFIG_SYS_HIGH, +- .vl_bpix = LCD_BPP, +- .vl_lbw = 0, +- .vl_splt = 1, +- .vl_clor = 1, +- .vl_tft = 1, +- .vl_hpw = 0x04, +- .vl_blw = 0x1c, +- .vl_elw = 0x08, +- .vl_vpw = 0x01, +- .vl_bfw = 0x07, +- .vl_efw = 0x08, +-}; +-#endif /* CONFIG_ACX517AKN */ +- +-#ifdef CONFIG_ACX544AKN +- +-# define LCD_BPP LCD_COLOR16 +- +-/* you have to set lccr0 and lccr3 (including pcd) */ +-# define REG_LCCR0 0x003008f9 +-# define REG_LCCR3 0x04700007 /* 16bpp */ +- +-vidinfo_t panel_info = { +- .vl_col = 320, +- .vl_row = 320, +- .vl_width = 320, +- .vl_height = 320, +- .vl_clkp = CONFIG_SYS_LOW, +- .vl_oep = CONFIG_SYS_LOW, +- .vl_hsp = CONFIG_SYS_LOW, +- .vl_vsp = CONFIG_SYS_LOW, +- .vl_dp = CONFIG_SYS_LOW, +- .vl_bpix = LCD_BPP, +- .vl_lbw = 0, +- .vl_splt = 0, +- .vl_clor = 1, +- .vl_tft = 1, +- .vl_hpw = 0x05, +- .vl_blw = 0x13, +- .vl_elw = 0x08, +- .vl_vpw = 0x02, +- .vl_bfw = 0x07, +- .vl_efw = 0x05, +-}; +-#endif /* CONFIG_ACX544AKN */ +- +-/*----------------------------------------------------------------------*/ +- + #ifdef CONFIG_LQ038J7DH53 + + # define LCD_BPP LCD_COLOR8 +@@ -295,7 +229,7 @@ + .vl_bfw = 0x04, + .vl_efw = 0x01, + }; +-#endif /* CONFIG_ACX517AKN */ ++#endif /* CONFIG_LQ038J7DH53 */ + + /*----------------------------------------------------------------------*/ + +diff -ruN u-boot-2021.10/drivers/video/rockchip/rk_mipi.c u-boot/drivers/video/rockchip/rk_mipi.c +--- u-boot-2021.10/drivers/video/rockchip/rk_mipi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/rockchip/rk_mipi.c 2021-11-01 17:10:14.529577902 +0100 +@@ -328,4 +328,3 @@ + + return 0; + } +- +diff -ruN u-boot-2021.10/drivers/video/stb_truetype.h u-boot/drivers/video/stb_truetype.h +--- u-boot-2021.10/drivers/video/stb_truetype.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/stb_truetype.h 2021-11-01 17:10:14.532911053 +0100 +@@ -497,7 +497,6 @@ + // It's inefficient; you might want to c&p it and optimize it. + + +- + ////////////////////////////////////////////////////////////////////////////// + // + // NEW TEXTURE BAKING API +diff -ruN u-boot-2021.10/drivers/video/sunxi/sunxi_display.c u-boot/drivers/video/sunxi/sunxi_display.c +--- u-boot-2021.10/drivers/video/sunxi/sunxi_display.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/sunxi/sunxi_display.c 2021-11-01 17:10:14.532911053 +0100 +@@ -17,7 +17,6 @@ + + #include <asm/arch/clock.h> + #include <asm/arch/display.h> +-#include <asm/arch/gpio.h> + #include <asm/arch/lcdc.h> + #include <asm/arch/pwm.h> + #include <asm/arch/tve.h> +@@ -872,11 +871,11 @@ + static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) + { + struct ssd2828_config cfg = { +- .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), +- .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), +- .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), +- .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), +- .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), ++ .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), ++ .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), ++ .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), ++ .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), ++ .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), + .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000, + .ssd2828_color_depth = 24, + #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 +@@ -902,6 +901,42 @@ + } + #endif /* CONFIG_VIDEO_LCD_SSD2828 */ + ++#ifdef CONFIG_VIDEO_LCD_PANEL_I2C ++static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) ++{ ++ const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME; ++ struct udevice *i2c_bus; ++ int ret; ++ ++ ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus); ++ if (ret) ++ return; ++ ++ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { ++ /* ++ * The anx9804 needs 1.8V from eldo3, we do this here ++ * and not via CONFIG_AXP_ELDO3_VOLT from board_init() ++ * to avoid turning this on when using hdmi output. ++ */ ++ axp_set_eldo(3, 1800); ++ anx9804_init(i2c_bus, 4, ++ ANX9804_DATA_RATE_1620M, ++ sunxi_display->depth); ++ } ++ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) { ++ struct udevice *chip; ++ ++ ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip); ++ if (ret) ++ return; ++ ++ dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */ ++ } ++} ++#else ++static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {} ++#endif ++ + static void sunxi_engines_init(void) + { + sunxi_composer_init(); +@@ -936,27 +971,12 @@ + break; + case sunxi_monitor_lcd: + sunxi_lcdc_panel_enable(); +- if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { +- /* +- * The anx9804 needs 1.8V from eldo3, we do this here +- * and not via CONFIG_AXP_ELDO3_VOLT from board_init() +- * to avoid turning this on when using hdmi output. +- */ +- axp_set_eldo(3, 1800); +- anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4, +- ANX9804_DATA_RATE_1620M, +- sunxi_display->depth); +- } + if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) { + mdelay(50); /* Wait for lcd controller power on */ + hitachi_tx18d42vm_init(); + } +- if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) { +- unsigned int orig_i2c_bus = i2c_get_bus_num(); +- i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS); +- i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */ +- i2c_set_bus_num(orig_i2c_bus); +- } ++ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C)) ++ sunxi_panel_i2c_init(sunxi_display); + sunxi_composer_mode_set(mode, address, monitor); + sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false); + sunxi_composer_enable(); +diff -ruN u-boot-2021.10/drivers/video/sunxi/sunxi_lcd.c u-boot/drivers/video/sunxi/sunxi_lcd.c +--- u-boot-2021.10/drivers/video/sunxi/sunxi_lcd.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/sunxi/sunxi_lcd.c 2021-11-01 17:10:14.532911053 +0100 +@@ -15,7 +15,6 @@ + #include <asm/io.h> + #include <asm/arch/clock.h> + #include <asm/arch/lcdc.h> +-#include <asm/arch/gpio.h> + #include <asm/global_data.h> + #include <asm/gpio.h> + +diff -ruN u-boot-2021.10/drivers/video/tdo-tl070wsh30.c u-boot/drivers/video/tdo-tl070wsh30.c +--- u-boot-2021.10/drivers/video/tdo-tl070wsh30.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/video/tdo-tl070wsh30.c 2021-11-01 17:10:14.532911053 +0100 +@@ -118,7 +118,7 @@ + + /* reset panel */ + dm_gpio_set_value(&priv->reset, true); +- ++ + mdelay(10); + + dm_gpio_set_value(&priv->reset, false); +diff -ruN u-boot-2021.10/drivers/w1/Kconfig u-boot/drivers/w1/Kconfig +--- u-boot-2021.10/drivers/w1/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/w1/Kconfig 2021-11-01 17:10:14.536244203 +0100 +@@ -6,7 +6,6 @@ + + config W1 + bool "Enable 1-wire controllers support" +- default no + depends on DM + help + Support for the Dallas 1-Wire bus. +@@ -15,15 +14,13 @@ + + config W1_GPIO + bool "Enable 1-wire GPIO bitbanging" +- default no + depends on DM_GPIO + help + Emulate a 1-wire bus using a GPIO. + + config W1_MXC + bool "Enable 1-wire controller on i.MX processors" +- default no +- depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 ++ depends on ARCH_MX31 || ARCH_MX5 + help + Support the one wire controller found in some members of the NXP + i.MX SoC family. +diff -ruN u-boot-2021.10/drivers/watchdog/gpio_wdt.c u-boot/drivers/watchdog/gpio_wdt.c +--- u-boot-2021.10/drivers/watchdog/gpio_wdt.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/watchdog/gpio_wdt.c 2021-11-01 17:10:14.539577354 +0100 +@@ -0,0 +1,68 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include <dm.h> ++#include <dm/device_compat.h> ++#include <wdt.h> ++#include <asm/gpio.h> ++ ++struct gpio_wdt_priv { ++ struct gpio_desc gpio; ++ bool always_running; ++ int state; ++}; ++ ++static int gpio_wdt_reset(struct udevice *dev) ++{ ++ struct gpio_wdt_priv *priv = dev_get_priv(dev); ++ ++ priv->state = !priv->state; ++ ++ return dm_gpio_set_value(&priv->gpio, priv->state); ++} ++ ++static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags) ++{ ++ struct gpio_wdt_priv *priv = dev_get_priv(dev); ++ ++ if (priv->always_running) ++ return 0; ++ ++ return -ENOSYS; ++} ++ ++static int dm_probe(struct udevice *dev) ++{ ++ struct gpio_wdt_priv *priv = dev_get_priv(dev); ++ int ret; ++ ++ priv->always_running = dev_read_bool(dev, "always-running"); ++ ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT); ++ if (ret < 0) { ++ dev_err(dev, "Request for wdt gpio failed: %d\n", ret); ++ return ret; ++ } ++ ++ if (priv->always_running) ++ ret = gpio_wdt_reset(dev); ++ ++ return ret; ++} ++ ++static const struct wdt_ops gpio_wdt_ops = { ++ .start = gpio_wdt_start, ++ .reset = gpio_wdt_reset, ++}; ++ ++static const struct udevice_id gpio_wdt_ids[] = { ++ { .compatible = "linux,wdt-gpio" }, ++ {} ++}; ++ ++U_BOOT_DRIVER(wdt_gpio) = { ++ .name = "wdt_gpio", ++ .id = UCLASS_WDT, ++ .of_match = gpio_wdt_ids, ++ .ops = &gpio_wdt_ops, ++ .probe = dm_probe, ++ .priv_auto = sizeof(struct gpio_wdt_priv), ++}; +diff -ruN u-boot-2021.10/drivers/watchdog/Kconfig u-boot/drivers/watchdog/Kconfig +--- u-boot-2021.10/drivers/watchdog/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/Kconfig 2021-11-01 17:10:14.536244203 +0100 +@@ -24,9 +24,10 @@ + + config WATCHDOG_TIMEOUT_MSECS + int "Watchdog timeout in msec" +- default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 ++ default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX7 || ARCH_VF610 + default 30000 if ARCH_SOCFPGA ++ default 16000 if (ARCH_SUNXI || TARGET_SUNXI) + default 60000 + help + Watchdog timeout in msec +@@ -147,6 +148,15 @@ + This driver support all CPU ISAs supported by Cortina + Access CAxxxx SoCs. + ++config WDT_GPIO ++ bool "External gpio watchdog support" ++ depends on WDT ++ depends on DM_GPIO ++ help ++ Support for external watchdog fed by toggling a gpio. See ++ doc/device-tree-bindings/watchdog/gpio-wdt.txt for ++ information on how to describe the watchdog in device tree. ++ + config WDT_MPC8xx + bool "MPC8xx watchdog timer support" + depends on WDT && MPC8xx +@@ -209,6 +219,26 @@ + Say Y here if you want to include support for the K3 watchdog + timer (RTI module) available in the K3 generation of processors. + ++if WDT_K3_RTI ++ ++config WDT_K3_RTI_LOAD_FW ++ bool "Load watchdog firmware" ++ depends on REMOTEPROC ++ help ++ Automatically load the specified firmware image into the MCU R5F ++ core 0. On the AM65x, this firmware is supposed to handle the expiry ++ of the watchdog timer, typically by resetting the system. ++ ++config WDT_K3_RTI_FW_FILE ++ string "Watchdog firmware image file" ++ default "k3-rti-wdt.fw" ++ depends on WDT_K3_RTI_LOAD_FW ++ help ++ Firmware image to be embedded into U-Boot and loaded on watchdog ++ start. ++ ++endif ++ + config WDT_SANDBOX + bool "Enable Watchdog Timer support for Sandbox" + depends on SANDBOX && WDT +@@ -241,6 +271,13 @@ + Enable the STM32 watchdog (IWDG) driver. Enable support to + configure STM32's on-SoC watchdog. + ++config WDT_SUNXI ++ bool "Allwinner sunxi watchdog timer support" ++ depends on WDT && (ARCH_SUNXI || TARGET_SUNXI) ++ default y ++ help ++ Enable support for the watchdog timer in Allwinner sunxi SoCs. ++ + config XILINX_TB_WATCHDOG + bool "Xilinx Axi watchdog timer support" + depends on WDT +diff -ruN u-boot-2021.10/drivers/watchdog/Makefile u-boot/drivers/watchdog/Makefile +--- u-boot-2021.10/drivers/watchdog/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/Makefile 2021-11-01 17:10:14.536244203 +0100 +@@ -25,6 +25,7 @@ + obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o + obj-$(CONFIG_WDT_ORION) += orion_wdt.o + obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o ++obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o + obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o + obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o + obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o +@@ -35,5 +36,6 @@ + obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o + obj-$(CONFIG_WDT_SP805) += sp805_wdt.o + obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o ++obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o + obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o + obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o +diff -ruN u-boot-2021.10/drivers/watchdog/orion_wdt.c u-boot/drivers/watchdog/orion_wdt.c +--- u-boot-2021.10/drivers/watchdog/orion_wdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/orion_wdt.c 2021-11-01 17:10:14.539577354 +0100 +@@ -4,8 +4,8 @@ + * Watchdog driver for Orion/Kirkwood processors + * + * Authors: Tomas Hlavacek <tmshlvck@gmail.com> +- * Sylver Bruneau <sylver.bruneau@googlemail.com> +- * Marek Behun <marek.behun@nic.cz> ++ * Sylver Bruneau <sylver.bruneau@googlemail.com> ++ * Marek Behun <marek.behun@nic.cz> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any +diff -ruN u-boot-2021.10/drivers/watchdog/rti_wdt.c u-boot/drivers/watchdog/rti_wdt.c +--- u-boot-2021.10/drivers/watchdog/rti_wdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/rti_wdt.c 2021-11-01 17:10:14.539577354 +0100 +@@ -11,9 +11,11 @@ + #include <common.h> + #include <clk.h> + #include <dm.h> ++#include <dm/device_compat.h> + #include <power-domain.h> + #include <wdt.h> + #include <asm/io.h> ++#include <remoteproc.h> + + /* Timer register set definition */ + #define RTIDWDCTRL 0x90 +@@ -42,6 +44,88 @@ + unsigned int clk_khz; + }; + ++#ifdef CONFIG_WDT_K3_RTI_LOAD_FW ++#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware" ++ ++static int rti_wdt_load_fw(struct udevice *dev) ++{ ++ struct udevice *rproc_dev; ++ int primary_core, ret; ++ u32 cluster_mode; ++ ofnode node; ++ u64 rti_wdt_fw; ++ u32 rti_wdt_fw_size; ++ ++ node = ofnode_path(RTI_WDT_FIT_PATH); ++ if (!ofnode_valid(node)) ++ goto fit_error; ++ ++ ret = ofnode_read_u64(node, "load", &rti_wdt_fw); ++ if (ret) ++ goto fit_error; ++ ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size); ++ if (ret) ++ goto fit_error; ++ ++ node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss"); ++ if (!ofnode_valid(node)) ++ goto dt_error; ++ ++ ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode); ++ if (ret) ++ cluster_mode = 1; ++ ++ node = ofnode_by_compatible(node, "ti,am654-r5f"); ++ if (!ofnode_valid(node)) ++ goto dt_error; ++ ++ ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev); ++ if (ret) ++ return ret; ++ ++ primary_core = dev_seq(rproc_dev); ++ ++ ret = rproc_dev_init(primary_core); ++ if (ret) ++ goto fw_error; ++ ++ if (cluster_mode == 1) { ++ ret = rproc_dev_init(primary_core + 1); ++ if (ret) ++ goto fw_error; ++ } ++ ++ ret = rproc_load(primary_core, (ulong)rti_wdt_fw, ++ rti_wdt_fw_size); ++ if (ret) ++ goto fw_error; ++ ++ ret = rproc_start(primary_core); ++ if (ret) ++ goto fw_error; ++ ++ return 0; ++ ++fit_error: ++ dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH); ++ return -ENOENT; ++ ++dt_error: ++ dev_err(dev, "No compatible firmware target processor found\n"); ++ return -ENODEV; ++ ++fw_error: ++ dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n", ++ primary_core); ++ return ret; ++} ++#else ++static inline int rti_wdt_load_fw(struct udevice *dev) ++{ ++ return 0; ++} ++#endif ++ + static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) + { + struct rti_wdt_priv *priv = dev_get_priv(dev); +@@ -51,6 +135,10 @@ + if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) + return -EBUSY; + ++ ret = rti_wdt_load_fw(dev); ++ if (ret < 0) ++ return ret; ++ + timer_margin = timeout_ms * priv->clk_khz / 1000; + timer_margin >>= WDT_PRELOAD_SHIFT; + if (timer_margin > WDT_PRELOAD_MAX) +diff -ruN u-boot-2021.10/drivers/watchdog/sunxi_wdt.c u-boot/drivers/watchdog/sunxi_wdt.c +--- u-boot-2021.10/drivers/watchdog/sunxi_wdt.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/drivers/watchdog/sunxi_wdt.c 2021-11-01 17:10:14.539577354 +0100 +@@ -0,0 +1,188 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Derived from linux/drivers/watchdog/sunxi_wdt.c: ++ * Copyright (C) 2013 Carlo Caione ++ * Copyright (C) 2012 Henrik Nordstrom ++ */ ++ ++#include <dm.h> ++#include <wdt.h> ++#include <asm/io.h> ++#include <linux/delay.h> ++ ++#define MSEC_PER_SEC 1000 ++ ++#define WDT_MAX_TIMEOUT 16 ++#define WDT_TIMEOUT_MASK 0xf ++ ++#define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1)) ++ ++#define WDT_MODE_EN BIT(0) ++ ++struct sunxi_wdt_reg { ++ u8 wdt_ctrl; ++ u8 wdt_cfg; ++ u8 wdt_mode; ++ u8 wdt_timeout_shift; ++ u8 wdt_reset_mask; ++ u8 wdt_reset_val; ++ u32 wdt_key_val; ++}; ++ ++struct sunxi_wdt_priv { ++ void __iomem *base; ++ const struct sunxi_wdt_reg *regs; ++}; ++ ++/* Map of timeout in seconds to register value */ ++static const u8 wdt_timeout_map[1 + WDT_MAX_TIMEOUT] = { ++ [0] = 0x0, ++ [1] = 0x1, ++ [2] = 0x2, ++ [3] = 0x3, ++ [4] = 0x4, ++ [5] = 0x5, ++ [6] = 0x6, ++ [7] = 0x7, ++ [8] = 0x7, ++ [9] = 0x8, ++ [10] = 0x8, ++ [11] = 0x9, ++ [12] = 0x9, ++ [13] = 0xa, ++ [14] = 0xa, ++ [15] = 0xb, ++ [16] = 0xb, ++}; ++ ++static int sunxi_wdt_reset(struct udevice *dev) ++{ ++ struct sunxi_wdt_priv *priv = dev_get_priv(dev); ++ const struct sunxi_wdt_reg *regs = priv->regs; ++ void __iomem *base = priv->base; ++ ++ writel(WDT_CTRL_RELOAD, base + regs->wdt_ctrl); ++ ++ return 0; ++} ++ ++static int sunxi_wdt_start(struct udevice *dev, u64 timeout, ulong flags) ++{ ++ struct sunxi_wdt_priv *priv = dev_get_priv(dev); ++ const struct sunxi_wdt_reg *regs = priv->regs; ++ void __iomem *base = priv->base; ++ u32 val; ++ ++ timeout /= MSEC_PER_SEC; ++ if (timeout > WDT_MAX_TIMEOUT) ++ timeout = WDT_MAX_TIMEOUT; ++ ++ /* Set system reset function */ ++ val = readl(base + regs->wdt_cfg); ++ val &= ~regs->wdt_reset_mask; ++ val |= regs->wdt_reset_val; ++ val |= regs->wdt_key_val; ++ writel(val, base + regs->wdt_cfg); ++ ++ /* Set timeout and enable watchdog */ ++ val = readl(base + regs->wdt_mode); ++ val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); ++ val |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; ++ val |= WDT_MODE_EN; ++ val |= regs->wdt_key_val; ++ writel(val, base + regs->wdt_mode); ++ ++ return sunxi_wdt_reset(dev); ++} ++ ++static int sunxi_wdt_stop(struct udevice *dev) ++{ ++ struct sunxi_wdt_priv *priv = dev_get_priv(dev); ++ const struct sunxi_wdt_reg *regs = priv->regs; ++ void __iomem *base = priv->base; ++ ++ writel(regs->wdt_key_val, base + regs->wdt_mode); ++ ++ return 0; ++} ++ ++static int sunxi_wdt_expire_now(struct udevice *dev, ulong flags) ++{ ++ int ret; ++ ++ ret = sunxi_wdt_start(dev, 0, flags); ++ if (ret) ++ return ret; ++ ++ mdelay(500); ++ ++ return 0; ++} ++ ++static const struct wdt_ops sunxi_wdt_ops = { ++ .reset = sunxi_wdt_reset, ++ .start = sunxi_wdt_start, ++ .stop = sunxi_wdt_stop, ++ .expire_now = sunxi_wdt_expire_now, ++}; ++ ++static const struct sunxi_wdt_reg sun4i_wdt_reg = { ++ .wdt_ctrl = 0x00, ++ .wdt_cfg = 0x04, ++ .wdt_mode = 0x04, ++ .wdt_timeout_shift = 3, ++ .wdt_reset_mask = 0x2, ++ .wdt_reset_val = 0x2, ++}; ++ ++static const struct sunxi_wdt_reg sun6i_wdt_reg = { ++ .wdt_ctrl = 0x10, ++ .wdt_cfg = 0x14, ++ .wdt_mode = 0x18, ++ .wdt_timeout_shift = 4, ++ .wdt_reset_mask = 0x3, ++ .wdt_reset_val = 0x1, ++}; ++ ++static const struct sunxi_wdt_reg sun20i_wdt_reg = { ++ .wdt_ctrl = 0x10, ++ .wdt_cfg = 0x14, ++ .wdt_mode = 0x18, ++ .wdt_timeout_shift = 4, ++ .wdt_reset_mask = 0x03, ++ .wdt_reset_val = 0x01, ++ .wdt_key_val = 0x16aa0000, ++}; ++ ++static const struct udevice_id sunxi_wdt_ids[] = { ++ { .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg }, ++ { .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg }, ++ { .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg }, ++ { /* sentinel */ } ++}; ++ ++static int sunxi_wdt_probe(struct udevice *dev) ++{ ++ struct sunxi_wdt_priv *priv = dev_get_priv(dev); ++ ++ priv->base = dev_remap_addr(dev); ++ if (!priv->base) ++ return -EINVAL; ++ ++ priv->regs = (void *)dev_get_driver_data(dev); ++ if (!priv->regs) ++ return -EINVAL; ++ ++ sunxi_wdt_stop(dev); ++ ++ return 0; ++} ++ ++U_BOOT_DRIVER(sunxi_wdt) = { ++ .name = "sunxi_wdt", ++ .id = UCLASS_WDT, ++ .of_match = sunxi_wdt_ids, ++ .probe = sunxi_wdt_probe, ++ .priv_auto = sizeof(struct sunxi_wdt_priv), ++ .ops = &sunxi_wdt_ops, ++}; +diff -ruN u-boot-2021.10/drivers/watchdog/wdt-uclass.c u-boot/drivers/watchdog/wdt-uclass.c +--- u-boot-2021.10/drivers/watchdog/wdt-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/wdt-uclass.c 2021-11-01 17:10:14.539577354 +0100 +@@ -10,6 +10,7 @@ + #include <errno.h> + #include <hang.h> + #include <log.h> ++#include <sysreset.h> + #include <time.h> + #include <wdt.h> + #include <asm/global_data.h> +@@ -20,53 +21,71 @@ + + #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) + +-/* +- * Reset every 1000ms, or however often is required as indicated by a +- * hw_margin_ms property. +- */ +-static ulong reset_period = 1000; ++struct wdt_priv { ++ /* Timeout, in seconds, to configure this device to. */ ++ u32 timeout; ++ /* ++ * Time, in milliseconds, between calling the device's ->reset() ++ * method from watchdog_reset(). ++ */ ++ ulong reset_period; ++ /* ++ * Next time (as returned by get_timer(0)) to call ++ * ->reset(). ++ */ ++ ulong next_reset; ++ /* Whether watchdog_start() has been called on the device. */ ++ bool running; ++}; + +-int initr_watchdog(void) ++static void init_watchdog_dev(struct udevice *dev) + { +- u32 timeout = WATCHDOG_TIMEOUT_SECS; ++ struct wdt_priv *priv; + int ret; + +- /* +- * Init watchdog: This will call the probe function of the +- * watchdog driver, enabling the use of the device +- */ +- if (uclass_get_device_by_seq(UCLASS_WDT, 0, +- (struct udevice **)&gd->watchdog_dev)) { +- debug("WDT: Not found by seq!\n"); +- if (uclass_get_device(UCLASS_WDT, 0, +- (struct udevice **)&gd->watchdog_dev)) { +- printf("WDT: Not found!\n"); +- return 0; +- } +- } ++ priv = dev_get_uclass_priv(dev); + +- if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { +- timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec", +- WATCHDOG_TIMEOUT_SECS); +- reset_period = dev_read_u32_default(gd->watchdog_dev, +- "hw_margin_ms", +- 4 * reset_period) / 4; +- } ++ ret = sysreset_register_wdt(dev); ++ if (ret) ++ printf("WDT: Failed to register sysreset\n"); + + if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) { +- printf("WDT: Not starting\n"); +- return 0; ++ printf("WDT: Not starting %s\n", dev->name); ++ return; + } + +- ret = wdt_start(gd->watchdog_dev, timeout * 1000, 0); ++ ret = wdt_start(dev, priv->timeout * 1000, 0); + if (ret != 0) { +- printf("WDT: Failed to start\n"); ++ printf("WDT: Failed to start %s\n", dev->name); ++ return; ++ } ++ ++ printf("WDT: Started %s with%s servicing (%ds timeout)\n", dev->name, ++ IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", priv->timeout); ++} ++ ++int initr_watchdog(void) ++{ ++ struct udevice *dev; ++ struct uclass *uc; ++ int ret; ++ ++ ret = uclass_get(UCLASS_WDT, &uc); ++ if (ret) { ++ log_debug("Error getting UCLASS_WDT: %d\n", ret); + return 0; + } + +- printf("WDT: Started with%s servicing (%ds timeout)\n", +- IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout); ++ uclass_foreach_dev(dev, uc) { ++ ret = device_probe(dev); ++ if (ret) { ++ log_debug("Error probing %s: %d\n", dev->name, ret); ++ continue; ++ } ++ init_watchdog_dev(dev); ++ } + ++ gd->flags |= GD_FLG_WDT_READY; + return 0; + } + +@@ -79,8 +98,11 @@ + return -ENOSYS; + + ret = ops->start(dev, timeout_ms, flags); +- if (ret == 0) +- gd->flags |= GD_FLG_WDT_READY; ++ if (ret == 0) { ++ struct wdt_priv *priv = dev_get_uclass_priv(dev); ++ ++ priv->running = true; ++ } + + return ret; + } +@@ -94,8 +116,36 @@ + return -ENOSYS; + + ret = ops->stop(dev); +- if (ret == 0) +- gd->flags &= ~GD_FLG_WDT_READY; ++ if (ret == 0) { ++ struct wdt_priv *priv = dev_get_uclass_priv(dev); ++ ++ priv->running = false; ++ } ++ ++ return ret; ++} ++ ++int wdt_stop_all(void) ++{ ++ struct wdt_priv *priv; ++ struct udevice *dev; ++ struct uclass *uc; ++ int ret, err; ++ ++ ret = uclass_get(UCLASS_WDT, &uc); ++ if (ret) ++ return ret; ++ ++ uclass_foreach_dev(dev, uc) { ++ if (!device_active(dev)) ++ continue; ++ priv = dev_get_uclass_priv(dev); ++ if (!priv->running) ++ continue; ++ err = wdt_stop(dev); ++ if (!ret) ++ ret = err; ++ } + + return ret; + } +@@ -120,10 +170,8 @@ + if (ops->expire_now) { + return ops->expire_now(dev, flags); + } else { +- if (!ops->start) +- return -ENOSYS; ++ ret = wdt_start(dev, 1, flags); + +- ret = ops->start(dev, 1, flags); + if (ret < 0) + return ret; + +@@ -141,18 +189,36 @@ + */ + void watchdog_reset(void) + { +- static ulong next_reset; ++ struct wdt_priv *priv; ++ struct udevice *dev; ++ struct uclass *uc; + ulong now; + + /* Exit if GD is not ready or watchdog is not initialized yet */ + if (!gd || !(gd->flags & GD_FLG_WDT_READY)) + return; + +- /* Do not reset the watchdog too often */ +- now = get_timer(0); +- if (time_after_eq(now, next_reset)) { +- next_reset = now + reset_period; +- wdt_reset(gd->watchdog_dev); ++ if (uclass_get(UCLASS_WDT, &uc)) ++ return; ++ ++ /* ++ * All devices bound to the wdt uclass should have been probed ++ * in initr_watchdog(). But just in case something went wrong, ++ * check device_active() before accessing the uclass private ++ * data. ++ */ ++ uclass_foreach_dev(dev, uc) { ++ if (!device_active(dev)) ++ continue; ++ priv = dev_get_uclass_priv(dev); ++ if (!priv->running) ++ continue; ++ /* Do not reset the watchdog too often */ ++ now = get_timer(0); ++ if (time_after_eq(now, priv->next_reset)) { ++ priv->next_reset = now + priv->reset_period; ++ wdt_reset(dev); ++ } + } + } + #endif +@@ -179,9 +245,38 @@ + return 0; + } + ++static int wdt_pre_probe(struct udevice *dev) ++{ ++ u32 timeout = WATCHDOG_TIMEOUT_SECS; ++ /* ++ * Reset every 1000ms, or however often is required as ++ * indicated by a hw_margin_ms property. ++ */ ++ ulong reset_period = 1000; ++ struct wdt_priv *priv; ++ ++ if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ++ timeout = dev_read_u32_default(dev, "timeout-sec", timeout); ++ reset_period = dev_read_u32_default(dev, "hw_margin_ms", ++ 4 * reset_period) / 4; ++ } ++ priv = dev_get_uclass_priv(dev); ++ priv->timeout = timeout; ++ priv->reset_period = reset_period; ++ /* ++ * Pretend this device was last reset "long" ago so the first ++ * watchdog_reset will actually call its ->reset method. ++ */ ++ priv->next_reset = get_timer(0); ++ ++ return 0; ++} ++ + UCLASS_DRIVER(wdt) = { +- .id = UCLASS_WDT, +- .name = "watchdog", +- .flags = DM_UC_FLAG_SEQ_ALIAS, +- .post_bind = wdt_post_bind, ++ .id = UCLASS_WDT, ++ .name = "watchdog", ++ .flags = DM_UC_FLAG_SEQ_ALIAS, ++ .post_bind = wdt_post_bind, ++ .pre_probe = wdt_pre_probe, ++ .per_device_auto = sizeof(struct wdt_priv), + }; +diff -ruN u-boot-2021.10/drivers/watchdog/xilinx_wwdt.c u-boot/drivers/watchdog/xilinx_wwdt.c +--- u-boot-2021.10/drivers/watchdog/xilinx_wwdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/watchdog/xilinx_wwdt.c 2021-11-01 17:10:14.539577354 +0100 +@@ -3,7 +3,7 @@ + * Xilinx window watchdog timer driver. + * + * Author(s): Michal Simek <michal.simek@xilinx.com> +- * Ashok Reddy Soma <ashokred@xilinx.com> ++ * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> + * + * Copyright (c) 2020, Xilinx Inc. + */ +@@ -23,13 +23,22 @@ + /* Generic Control/Status Register Masks */ + #define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */ + +-/* Register offsets for the Wdt device */ +-#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */ +-#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */ +-#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */ +-#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */ +-#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */ +-#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */ ++/* Register offsets for the WWDT device */ ++#define XWT_WWDT_MWR_OFFSET 0x00 ++#define XWT_WWDT_ESR_OFFSET 0x04 ++#define XWT_WWDT_FCR_OFFSET 0x08 ++#define XWT_WWDT_FWR_OFFSET 0x0c ++#define XWT_WWDT_SWR_OFFSET 0x10 ++#define XWT_WWDT_CNT_MIN 1 ++#define XWT_WWDT_CNT_MAX 0xffffffff ++ ++/* Master Write Control Register Masks */ ++#define XWT_WWDT_MWR_MASK BIT(0) ++ ++/* Enable and Status Register Masks */ ++#define XWT_WWDT_ESR_WINT_MASK BIT(16) ++#define XWT_WWDT_ESR_WSW_MASK BIT(8) ++#define XWT_WWDT_ESR_WEN_MASK BIT(0) + + struct xlnx_wwdt_priv { + bool enable_once; +@@ -43,16 +52,23 @@ + + static int xlnx_wwdt_reset(struct udevice *dev) + { ++ u32 esr; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + +- regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK); ++ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); ++ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); ++ esr |= XWT_WWDT_ESR_WINT_MASK; ++ esr &= ~XWT_WWDT_ESR_WSW_MASK; ++ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); ++ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); ++ esr |= XWT_WWDT_ESR_WSW_MASK; ++ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); + + return 0; + } + + static int xlnx_wwdt_stop(struct udevice *dev) + { +- u32 csr; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + if (wdt->enable_once) { +@@ -60,10 +76,9 @@ + return -EBUSY; + } + +- /* Disable the generic watchdog timer */ +- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); +- csr &= ~(XWT_WWCSR_GWEN_MASK); +- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); ++ /* Disable the window watchdog timer */ ++ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); ++ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); + + clk_disable(&wdt->clk); + +@@ -72,11 +87,11 @@ + return 0; + } + +-static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) ++static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) + { + int ret; +- u32 csr; +- u64 count; ++ u32 esr; ++ u64 count, timeout; + unsigned long clock_f; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + +@@ -88,40 +103,52 @@ + + dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f); + ++ /* Convert timeout from msec to sec */ ++ timeout = timeout_ms / 1000; ++ + /* Calculate timeout count */ + count = timeout * clock_f; + ++ /* Count should be at least 1 */ ++ if (count < XWT_WWDT_CNT_MIN) { ++ debug("%s: watchdog won't fire with 0 ticks\n", __func__); ++ count = XWT_WWDT_CNT_MIN; ++ } ++ ++ /* Limit the count to maximum possible value */ ++ if (count > XWT_WWDT_CNT_MAX) { ++ debug("%s: maximum watchdog timeout exceeded\n", __func__); ++ count = XWT_WWDT_CNT_MAX; ++ } ++ + ret = clk_enable(&wdt->clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + +- /* +- * Timeout count is half as there are two windows +- * first window overflow is ignored (interrupt), +- * reset is only generated at second window overflow +- */ +- count = count >> 1; +- +- /* Disable the generic watchdog timer */ +- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); +- csr &= ~(XWT_WWCSR_GWEN_MASK); +- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); +- +- /* Set compare and offset registers for generic watchdog timeout */ +- regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count); +- regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0); +- regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count); +- +- /* Enable the generic watchdog timer */ +- regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); +- csr |= (XWT_WWCSR_GWEN_MASK); +- regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); ++ /* Disable the window watchdog timer */ ++ regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); ++ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); ++ ++ /* Set first window and second window registers with timeout */ ++ regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */ ++ regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count); ++ regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0); ++ ++ /* Enable the window watchdog timer */ ++ regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); ++ esr |= XWT_WWDT_ESR_WEN_MASK; ++ regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); + + return 0; + } + ++static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags) ++{ ++ return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags); ++} ++ + static int xlnx_wwdt_probe(struct udevice *dev) + { + int ret; +@@ -160,6 +187,7 @@ + .start = xlnx_wwdt_start, + .reset = xlnx_wwdt_reset, + .stop = xlnx_wwdt_stop, ++ .expire_now = xlnx_wwdt_expire_now, + }; + + static const struct udevice_id xlnx_wwdt_ids[] = { +diff -ruN u-boot-2021.10/drivers/xen/events.c u-boot/drivers/xen/events.c +--- u-boot-2021.10/drivers/xen/events.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/xen/events.c 2021-11-01 17:10:14.539577354 +0100 +@@ -196,4 +196,3 @@ + /* Dealloc all events */ + unbind_all_ports(); + } +- +diff -ruN u-boot-2021.10/drivers/xen/gnttab.c u-boot/drivers/xen/gnttab.c +--- u-boot-2021.10/drivers/xen/gnttab.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/drivers/xen/gnttab.c 2021-11-01 17:10:14.539577354 +0100 +@@ -215,4 +215,3 @@ + setup.dom = DOMID_SELF; + setup.nr_frames = 0; + } +- +diff -ruN u-boot-2021.10/dts/Kconfig u-boot/dts/Kconfig +--- u-boot-2021.10/dts/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/dts/Kconfig 2021-11-01 17:10:14.539577354 +0100 +@@ -44,10 +44,19 @@ + bool "Run-time configuration via Device Tree" + select DTC + select OF_LIBFDT if !OF_PLATDATA ++ select OF_REAL if !OF_PLATDATA + help + This feature provides for run-time configuration of U-Boot + via a flattened device tree. + ++config OF_REAL ++ bool ++ help ++ Indicates that a real devicetree is available which can be accessed ++ at runtime. This means that dev_read_...() functions can be used to ++ read data from the devicetree for each device. This is true if ++ OF_CONTROL is enabled in U-Boot proper. ++ + config OF_BOARD_FIXUP + bool "Board-specific manipulation of Device Tree" + help +@@ -62,6 +71,7 @@ + bool "Enable run-time configuration via Device Tree in SPL" + depends on SPL && OF_CONTROL + select SPL_OF_LIBFDT if !SPL_OF_PLATDATA ++ select SPL_OF_REAL if !SPL_OF_PLATDATA + help + Some boards use device tree in U-Boot but only have 4KB of SRAM + which is not enough to support device tree. Disable this option to +@@ -71,6 +81,7 @@ + bool "Enable run-time configuration via Device Tree in TPL" + depends on TPL && OF_CONTROL + select TPL_OF_LIBFDT if !TPL_OF_PLATDATA ++ select TPL_OF_REAL if !TPL_OF_PLATDATA + help + Some boards use device tree in U-Boot but only have 4KB of SRAM + which is not enough to support device tree. Enable this option to +@@ -236,7 +247,7 @@ + + + config SPL_MULTI_DTB_FIT +- depends on SPL_LOAD_FIT && SPL_OF_CONTROL && !SPL_OF_PLATDATA ++ depends on SPL_LOAD_FIT && SPL_OF_REAL + bool "Support embedding several DTBs in a FIT image for the SPL" + help + This option provides the SPL with the ability to select its own +@@ -374,6 +385,14 @@ + compatible string, then adding platform data and U_BOOT_DRVINFO + declarations for each node. See of-plat.txt for more information. + ++config SPL_OF_REAL ++ bool ++ help ++ Indicates that a real devicetree is available which can be accessed ++ at runtime. This means that dev_read_...() functions can be used to ++ read data from the devicetree for each device. This is true if ++ SPL_OF_CONTROL is enabled and not SPL_OF_PLATDATA ++ + if SPL_OF_PLATDATA + + config SPL_OF_PLATDATA_PARENT +@@ -421,6 +440,14 @@ + + endif + ++config TPL_OF_REAL ++ bool ++ help ++ Indicates that a real devicetree is available which can be accessed ++ at runtime. This means that dev_read_...() functions can be used to ++ read data from the devicetree for each device. This is true if ++ TPL_OF_CONTROL is enabled and not TPL_OF_PLATDATA ++ + config TPL_OF_PLATDATA + bool "Generate platform data for use in TPL" + depends on TPL_OF_CONTROL +diff -ruN u-boot-2021.10/env/eeprom.c u-boot/env/eeprom.c +--- u-boot-2021.10/env/eeprom.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/env/eeprom.c 2021-11-01 17:10:14.539577354 +0100 +@@ -76,7 +76,7 @@ + if (gd->env_valid == ENV_REDUND) + off = CONFIG_ENV_OFFSET_REDUND; + #endif +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + off + index + offsetof(env_t, data), &c, 1); + + return c; +@@ -100,11 +100,11 @@ + + for (i = 0; i < 2; i++) { + /* read CRC */ +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + off_env[i] + offsetof(env_t, crc), + (uchar *)&crc[i], sizeof(ulong)); + /* read FLAGS */ +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + off_env[i] + offsetof(env_t, flags), + (uchar *)&flags[i], sizeof(uchar)); + +@@ -114,7 +114,7 @@ + while (len > 0) { + int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; + +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, + rdbuf, n); + + crc_tmp = crc32(crc_tmp, rdbuf, n); +@@ -156,7 +156,7 @@ + eeprom_init(-1); /* prepare for EEPROM read/write */ + + /* read old CRC */ +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_ENV_OFFSET + offsetof(env_t, crc), + (uchar *)&crc, sizeof(ulong)); + +@@ -166,7 +166,7 @@ + while (len > 0) { + int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; + +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_ENV_OFFSET + off, rdbuf, n); + new = crc32(new, rdbuf, n); + len -= n; +@@ -186,7 +186,7 @@ + off = CONFIG_ENV_OFFSET_REDUND; + #endif + +- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + off, (uchar *)buf_env, CONFIG_ENV_SIZE); + + return env_import(buf_env, 1, H_EXTERNAL); +@@ -215,12 +215,12 @@ + env_new.flags = ENV_REDUND_ACTIVE; + #endif + +- rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, ++ rc = eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, + off, (uchar *)&env_new, CONFIG_ENV_SIZE); + + #ifdef CONFIG_ENV_OFFSET_REDUND + if (rc == 0) { +- eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, ++ eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, + off_red + offsetof(env_t, flags), + (uchar *)&flag_obsolete, 1); + +diff -ruN u-boot-2021.10/env/Kconfig u-boot/env/Kconfig +--- u-boot-2021.10/env/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/env/Kconfig 2021-11-01 17:10:14.539577354 +0100 +@@ -44,10 +44,6 @@ + still be one byte because the extra address bits are hidden + in the chip address. + +- - CONFIG_ENV_EEPROM_IS_ON_I2C +- define this, if you have I2C and SPI activated, and your +- EEPROM, which holds the environment, is on the I2C bus. +- + - CONFIG_I2C_ENV_EEPROM_BUS + if you have an Environment on an EEPROM reached over + I2C muxes, you can define here, how to reach this +@@ -689,7 +685,6 @@ + + config ENV_APPEND + bool "Always append the environment with new data" +- default n + help + If defined, the environment hash table is only ever appended with new + data, but the existing hash table can never be dropped and reloaded +@@ -698,7 +693,6 @@ + + config ENV_WRITEABLE_LIST + bool "Permit write access only to listed variables" +- default n + help + If defined, only environment variables which explicitly set the 'w' + writeable flag can be written and modified at runtime. No variables +@@ -706,7 +700,6 @@ + + config ENV_ACCESS_IGNORE_FORCE + bool "Block forced environment operations" +- default n + help + If defined, don't allow the -f switch to env set override variable + access flags. +diff -ruN u-boot-2021.10/env/mmc.c u-boot/env/mmc.c +--- u-boot-2021.10/env/mmc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/env/mmc.c 2021-11-01 17:10:14.542910506 +0100 +@@ -19,6 +19,7 @@ + #include <part.h> + #include <search.h> + #include <errno.h> ++#include <dm/ofnode.h> + + #define __STR(X) #X + #define STR(X) __STR(X) +@@ -73,7 +74,7 @@ + int err; + + /* look for the partition in mmc CONFIG_SYS_MMC_ENV_DEV */ +- str = fdtdec_get_config_string(gd->fdt_blob, dt_prop.partition); ++ str = ofnode_conf_read_str(dt_prop.partition); + if (str) { + /* try to place the environment at end of the partition */ + err = mmc_offset_try_partition(str, copy, &val); +@@ -90,7 +91,7 @@ + propname = dt_prop.offset_redund; + } + #endif +- return fdtdec_get_config_int(gd->fdt_blob, propname, defvalue); ++ return ofnode_conf_read_int(propname, defvalue); + } + #else + static inline s64 mmc_offset(int copy) +diff -ruN u-boot-2021.10/fs/btrfs/btrfs.c u-boot/fs/btrfs/btrfs.c +--- u-boot-2021.10/fs/btrfs/btrfs.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/btrfs/btrfs.c 2021-11-01 17:10:14.542910506 +0100 +@@ -23,7 +23,7 @@ + struct btrfs_key key; + static const char* dir_item_str[] = { + [BTRFS_FT_REG_FILE] = " ", +- [BTRFS_FT_DIR] = "DIR", ++ [BTRFS_FT_DIR] = "DIR", + [BTRFS_FT_CHRDEV] = "CHR", + [BTRFS_FT_BLKDEV] = "BLK", + [BTRFS_FT_FIFO] = "FIF", +diff -ruN u-boot-2021.10/fs/btrfs/disk-io.c u-boot/fs/btrfs/disk-io.c +--- u-boot-2021.10/fs/btrfs/disk-io.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/btrfs/disk-io.c 2021-11-01 17:10:14.546243657 +0100 +@@ -918,7 +918,11 @@ + + ret = btrfs_scan_one_device(desc, part, fs_devices, &total_devs); + if (ret) { +- fprintf(stderr, "No valid Btrfs found\n"); ++ /* ++ * Avoid showing this when probing for a possible Btrfs ++ * ++ * fprintf(stderr, "No valid Btrfs found\n"); ++ */ + return ret; + } + return 0; +@@ -1007,7 +1011,7 @@ + disk_super = fs_info->super_copy; + ret = btrfs_read_dev_super(desc, part, disk_super); + if (ret) { +- printk("No valid btrfs found\n"); ++ debug("No valid btrfs found\n"); + goto out_devices; + } + +diff -ruN u-boot-2021.10/fs/btrfs/kernel-shared/btrfs_tree.h u-boot/fs/btrfs/kernel-shared/btrfs_tree.h +--- u-boot-2021.10/fs/btrfs/kernel-shared/btrfs_tree.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/btrfs/kernel-shared/btrfs_tree.h 2021-11-01 17:10:14.546243657 +0100 +@@ -334,7 +334,6 @@ + #define BTRFS_STRING_ITEM_KEY 253 + + +- + /* 32 bytes in various csum fields */ + #define BTRFS_CSUM_SIZE 32 + +diff -ruN u-boot-2021.10/fs/jffs2/summary.h u-boot/fs/jffs2/summary.h +--- u-boot-2021.10/fs/jffs2/summary.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/jffs2/summary.h 2021-11-01 17:10:14.549576807 +0100 +@@ -39,7 +39,7 @@ + __u32 inode; /* inode number */ + __u32 version; /* inode version */ + __u32 offset; /* offset on jeb */ +- __u32 totlen; /* record length */ ++ __u32 totlen; /* record length */ + } __attribute__((packed)); + + struct jffs2_sum_dirent_flash +@@ -49,7 +49,7 @@ + __u32 offset; /* offset on jeb */ + __u32 pino; /* parent inode */ + __u32 version; /* dirent version */ +- __u32 ino; /* == zero for unlink */ ++ __u32 ino; /* == zero for unlink */ + uint8_t nsize; /* dirent name size */ + uint8_t type; /* dirent type */ + uint8_t name[0]; /* dirent name */ +@@ -94,7 +94,7 @@ + __u32 inode; /* inode number */ + __u32 version; /* inode version */ + __u32 offset; /* offset on jeb */ +- __u32 totlen; /* record length */ ++ __u32 totlen; /* record length */ + } __attribute__((packed)); + + struct jffs2_sum_dirent_mem +@@ -105,7 +105,7 @@ + __u32 offset; /* ofset on jeb */ + __u32 pino; /* parent inode */ + __u32 version; /* dirent version */ +- __u32 ino; /* == zero for unlink */ ++ __u32 ino; /* == zero for unlink */ + uint8_t nsize; /* dirent name size */ + uint8_t type; /* dirent type */ + uint8_t name[0]; /* dirent name */ +@@ -155,7 +155,7 @@ + struct jffs2_sum_marker + { + __u32 offset; /* offset of the summary node in the jeb */ +- __u32 magic; /* == JFFS2_SUM_MAGIC */ ++ __u32 magic; /* == JFFS2_SUM_MAGIC */ + }; + + #define JFFS2_SUMMARY_FRAME_SIZE (sizeof(struct jffs2_raw_summary) + sizeof(struct jffs2_sum_marker)) +diff -ruN u-boot-2021.10/fs/squashfs/sqfs.c u-boot/fs/squashfs/sqfs.c +--- u-boot-2021.10/fs/squashfs/sqfs.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/squashfs/sqfs.c 2021-11-01 17:10:14.552909959 +0100 +@@ -1090,7 +1090,7 @@ + + /* Make sure it has a valid SquashFS magic number*/ + if (get_unaligned_le32(&sblk->s_magic) != SQFS_MAGIC_NUMBER) { +- printf("Bad magic number for SquashFS image.\n"); ++ debug("Bad magic number for SquashFS image.\n"); + ret = -EINVAL; + goto error; + } +diff -ruN u-boot-2021.10/fs/ubifs/ubifs.h u-boot/fs/ubifs/ubifs.h +--- u-boot-2021.10/fs/ubifs/ubifs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/ubifs/ubifs.h 2021-11-01 17:10:14.556243110 +0100 +@@ -252,10 +252,10 @@ + }; + + struct super_operations { +- struct inode *(*alloc_inode)(struct super_block *sb); ++ struct inode *(*alloc_inode)(struct super_block *sb); + void (*destroy_inode)(struct inode *); + +- void (*dirty_inode) (struct inode *, int flags); ++ void (*dirty_inode) (struct inode *, int flags); + int (*write_inode) (struct inode *, struct writeback_control *wbc); + int (*drop_inode) (struct inode *); + void (*evict_inode) (struct inode *); +@@ -326,7 +326,7 @@ + char s_id[32]; /* Informational name */ + u8 s_uuid[16]; /* UUID */ + +- void *s_fs_info; /* Filesystem private info */ ++ void *s_fs_info; /* Filesystem private info */ + unsigned int s_max_links; + #ifndef __UBOOT__ + fmode_t s_mode; +@@ -431,7 +431,7 @@ + #define f_dentry f_path.dentry + #define f_vfsmnt f_path.mnt + const struct file_operations *f_op; +- unsigned int f_flags; ++ unsigned int f_flags; + loff_t f_pos; + unsigned int f_uid, f_gid; + +@@ -466,7 +466,7 @@ + #if BITS_PER_LONG==32 + #define MAX_LFS_FILESIZE (((u64)PAGE_CACHE_SIZE << (BITS_PER_LONG-1))-1) + #elif BITS_PER_LONG==64 +-#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL ++#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL + #endif + + /* +diff -ruN u-boot-2021.10/fs/yaffs2/yaffs_uboot_glue.c u-boot/fs/yaffs2/yaffs_uboot_glue.c +--- u-boot-2021.10/fs/yaffs2/yaffs_uboot_glue.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/fs/yaffs2/yaffs_uboot_glue.c 2021-11-01 17:10:14.559576261 +0100 +@@ -35,6 +35,7 @@ + #else + #include "malloc.h" + #endif ++#include <linux/mtd/rawnand.h> + + unsigned yaffs_trace_mask = 0x0; /* Disable logging */ + static int yaffs_errno; +diff -ruN u-boot-2021.10/.git/config u-boot/.git/config +diff -ruN u-boot-2021.10/.git/description u-boot/.git/description +diff -ruN u-boot-2021.10/.git/HEAD u-boot/.git/HEAD +diff -ruN u-boot-2021.10/.git/hooks/applypatch-msg.sample u-boot/.git/hooks/applypatch-msg.sample +diff -ruN u-boot-2021.10/.git/hooks/commit-msg.sample u-boot/.git/hooks/commit-msg.sample +diff -ruN u-boot-2021.10/.git/hooks/fsmonitor-watchman.sample u-boot/.git/hooks/fsmonitor-watchman.sample +diff -ruN u-boot-2021.10/.git/hooks/post-update.sample u-boot/.git/hooks/post-update.sample +diff -ruN u-boot-2021.10/.git/hooks/pre-applypatch.sample u-boot/.git/hooks/pre-applypatch.sample +diff -ruN u-boot-2021.10/.git/hooks/pre-commit.sample u-boot/.git/hooks/pre-commit.sample +diff -ruN u-boot-2021.10/.git/hooks/prepare-commit-msg.sample u-boot/.git/hooks/prepare-commit-msg.sample +diff -ruN u-boot-2021.10/.git/hooks/pre-push.sample u-boot/.git/hooks/pre-push.sample +diff -ruN u-boot-2021.10/.git/hooks/pre-rebase.sample u-boot/.git/hooks/pre-rebase.sample +diff -ruN u-boot-2021.10/.git/hooks/pre-receive.sample u-boot/.git/hooks/pre-receive.sample +diff -ruN u-boot-2021.10/.git/hooks/update.sample u-boot/.git/hooks/update.sample +Binary files u-boot-2021.10/.git/index and u-boot/.git/index differ +diff -ruN u-boot-2021.10/.git/info/exclude u-boot/.git/info/exclude +diff -ruN u-boot-2021.10/.git/logs/HEAD u-boot/.git/logs/HEAD +diff -ruN u-boot-2021.10/.git/logs/refs/heads/d1-wip u-boot/.git/logs/refs/heads/d1-wip +diff -ruN u-boot-2021.10/.git/logs/refs/remotes/origin/HEAD u-boot/.git/logs/refs/remotes/origin/HEAD +Binary files u-boot-2021.10/.git/objects/pack/pack-6c3f1253c7d4e1d4d771e179081a47164c6a3219.idx and u-boot/.git/objects/pack/pack-6c3f1253c7d4e1d4d771e179081a47164c6a3219.idx differ +Binary files u-boot-2021.10/.git/objects/pack/pack-6c3f1253c7d4e1d4d771e179081a47164c6a3219.pack and u-boot/.git/objects/pack/pack-6c3f1253c7d4e1d4d771e179081a47164c6a3219.pack differ +diff -ruN u-boot-2021.10/.git/packed-refs u-boot/.git/packed-refs +diff -ruN u-boot-2021.10/.git/refs/heads/d1-wip u-boot/.git/refs/heads/d1-wip +diff -ruN u-boot-2021.10/.git/refs/remotes/origin/HEAD u-boot/.git/refs/remotes/origin/HEAD +diff -ruN u-boot-2021.10/.gitlab-ci.yml u-boot/.gitlab-ci.yml +--- u-boot-2021.10/.gitlab-ci.yml 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/.gitlab-ci.yml 2021-11-01 17:10:13.536298895 +0100 +@@ -2,7 +2,7 @@ + + # Grab our configured image. The source for this is found at: + # https://source.denx.de/u-boot/gitlab-ci-runner +-image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021 ++image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 + + # We run some tests in different order, to catch some failures quicker. + stages: +@@ -23,7 +23,7 @@ + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + fi +- - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then ++ - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + fi +@@ -40,6 +40,18 @@ + - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi + - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi + - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi ++ # create sdcard / spi-nor images for sifive unleashed using genimage ++ - if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then ++ mkdir -p root; ++ cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .; ++ cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .; ++ rm -rf tmp; ++ genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg; ++ cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/; ++ rm -rf tmp; ++ genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg; ++ cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/; ++ fi + - virtualenv -p /usr/bin/python3 /tmp/venv + - . /tmp/venv/bin/activate + - pip install -r test/py/requirements.txt +@@ -204,6 +216,12 @@ + TEST_PY_BD: "sandbox_flattree" + <<: *buildman_and_testpy_dfn + ++vexpress_ca9x4 test.py: ++ variables: ++ TEST_PY_BD: "vexpress_ca9x4" ++ TEST_PY_ID: "--id qemu" ++ <<: *buildman_and_testpy_dfn ++ + integratorcp_cm926ejs test.py: + variables: + TEST_PY_BD: "integratorcp_cm926ejs" +@@ -317,6 +335,18 @@ + TEST_PY_ID: "--id tulip_qemu" + <<: *buildman_and_testpy_dfn + ++sifive_unleashed_sdcard test.py: ++ variables: ++ TEST_PY_BD: "sifive_unleashed" ++ TEST_PY_ID: "--id sdcard_qemu" ++ <<: *buildman_and_testpy_dfn ++ ++sifive_unleashed_spi-nor test.py: ++ variables: ++ TEST_PY_BD: "sifive_unleashed" ++ TEST_PY_ID: "--id spi-nor_qemu" ++ <<: *buildman_and_testpy_dfn ++ + xilinx_zynq_virt test.py: + variables: + TEST_PY_BD: "xilinx_zynq_virt" +diff -ruN u-boot-2021.10/include/asm-generic/global_data.h u-boot/include/asm-generic/global_data.h +--- u-boot-2021.10/include/asm-generic/global_data.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/asm-generic/global_data.h 2021-11-01 17:10:14.566242563 +0100 +@@ -277,7 +277,7 @@ + */ + void *trace_buff; + #endif +-#if defined(CONFIG_SYS_I2C_LEGACY) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + /** + * @cur_i2c_bus: currently used I2C bus + */ +@@ -447,12 +447,6 @@ + */ + fdt_addr_t translation_offset; + #endif +-#if CONFIG_IS_ENABLED(WDT) +- /** +- * @watchdog_dev: watchdog device +- */ +- struct udevice *watchdog_dev; +-#endif + #ifdef CONFIG_GENERATE_ACPI_TABLE + /** + * @acpi_ctx: ACPI context pointer +diff -ruN u-boot-2021.10/include/asm-generic/gpio.h u-boot/include/asm-generic/gpio.h +--- u-boot-2021.10/include/asm-generic/gpio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/asm-generic/gpio.h 2021-11-01 17:10:14.566242563 +0100 +@@ -222,6 +222,14 @@ + struct fdtdec_phandle_args; + + /** ++ * gpio_flags_xlate() - convert DT flags to internal flags ++ * ++ * This routine converts the GPIO_* flags from the generic DT binding to the ++ * GPIOD_* flags used internally. It can be called from driver xlate functions. ++ */ ++unsigned long gpio_flags_xlate(uint32_t arg); ++ ++/** + * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate + * + * This routine sets the offset field to args[0] and the flags field to +@@ -608,6 +616,11 @@ + */ + int dm_gpio_request(struct gpio_desc *desc, const char *label); + ++struct phandle_2_arg; ++int gpio_request_by_phandle(struct udevice *dev, ++ const struct phandle_2_arg *cells, ++ struct gpio_desc *desc, int flags); ++ + /** + * gpio_get_list_count() - Returns the number of GPIOs in a list + * +diff -ruN u-boot-2021.10/include/atsha204a-i2c.h u-boot/include/atsha204a-i2c.h +--- u-boot-2021.10/include/atsha204a-i2c.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/atsha204a-i2c.h 2021-11-01 17:10:14.566242563 +0100 +@@ -2,8 +2,8 @@ + * I2C Driver for Atmel ATSHA204 over I2C + * + * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com +- * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com +- * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz ++ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com ++ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as +diff -ruN u-boot-2021.10/include/axp152.h u-boot/include/axp152.h +--- u-boot-2021.10/include/axp152.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp152.h 2021-11-01 17:10:14.566242563 +0100 +@@ -13,14 +13,3 @@ + }; + + #define AXP152_POWEROFF (1 << 7) +- +-/* For axp_gpio.c */ +-#define AXP_GPIO0_CTRL 0x90 +-#define AXP_GPIO1_CTRL 0x91 +-#define AXP_GPIO2_CTRL 0x92 +-#define AXP_GPIO3_CTRL 0x93 +-#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +-#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +-#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +-#define AXP_GPIO_STATE 0x97 +-#define AXP_GPIO_STATE_OFFSET 0 +diff -ruN u-boot-2021.10/include/axp209.h u-boot/include/axp209.h +--- u-boot-2021.10/include/axp209.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp209.h 2021-11-01 17:10:14.566242563 +0100 +@@ -72,15 +72,3 @@ + #define AXP209_IRQ5_PEK_DOWN BIT(5) + + #define AXP209_POWEROFF BIT(7) +- +-/* For axp_gpio.c */ +-#define AXP_POWER_STATUS 0x00 +-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) +-#define AXP_GPIO0_CTRL 0x90 +-#define AXP_GPIO1_CTRL 0x92 +-#define AXP_GPIO2_CTRL 0x93 +-#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +-#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +-#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +-#define AXP_GPIO_STATE 0x94 +-#define AXP_GPIO_STATE_OFFSET 4 +diff -ruN u-boot-2021.10/include/axp221.h u-boot/include/axp221.h +--- u-boot-2021.10/include/axp221.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp221.h 2021-11-01 17:10:14.566242563 +0100 +@@ -48,18 +48,3 @@ + + /* Page 1 addresses */ + #define AXP221_SID 0x20 +- +-/* For axp_gpio.c */ +-#define AXP_POWER_STATUS 0x00 +-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +-#define AXP_VBUS_IPSOUT 0x30 +-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +-#define AXP_MISC_CTRL 0x8f +-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +-#define AXP_GPIO0_CTRL 0x90 +-#define AXP_GPIO1_CTRL 0x92 +-#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +-#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +-#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +-#define AXP_GPIO_STATE 0x94 +-#define AXP_GPIO_STATE_OFFSET 0 +diff -ruN u-boot-2021.10/include/axp809.h u-boot/include/axp809.h +--- u-boot-2021.10/include/axp809.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp809.h 2021-11-01 17:10:14.566242563 +0100 +@@ -42,18 +42,3 @@ + #define AXP809_ALDO3_CTRL 0x2a + #define AXP809_SHUTDOWN 0x32 + #define AXP809_SHUTDOWN_POWEROFF (1 << 7) +- +-/* For axp_gpio.c */ +-#define AXP_POWER_STATUS 0x00 +-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +-#define AXP_VBUS_IPSOUT 0x30 +-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +-#define AXP_MISC_CTRL 0x8f +-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +-#define AXP_GPIO0_CTRL 0x90 +-#define AXP_GPIO1_CTRL 0x92 +-#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +-#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +-#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +-#define AXP_GPIO_STATE 0x94 +-#define AXP_GPIO_STATE_OFFSET 0 +diff -ruN u-boot-2021.10/include/axp818.h u-boot/include/axp818.h +--- u-boot-2021.10/include/axp818.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp818.h 2021-11-01 17:10:14.566242563 +0100 +@@ -56,18 +56,3 @@ + + #define AXP818_SHUTDOWN 0x32 + #define AXP818_SHUTDOWN_POWEROFF (1 << 7) +- +-/* For axp_gpio.c */ +-#define AXP_POWER_STATUS 0x00 +-#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +-#define AXP_VBUS_IPSOUT 0x30 +-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +-#define AXP_MISC_CTRL 0x8f +-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +-#define AXP_GPIO0_CTRL 0x90 +-#define AXP_GPIO1_CTRL 0x92 +-#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +-#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +-#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +-#define AXP_GPIO_STATE 0x94 +-#define AXP_GPIO_STATE_OFFSET 0 +diff -ruN u-boot-2021.10/include/axp_pmic.h u-boot/include/axp_pmic.h +--- u-boot-2021.10/include/axp_pmic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/axp_pmic.h 2021-11-01 17:10:14.566242563 +0100 +@@ -5,25 +5,26 @@ + * X-Powers AX Power Management IC support header + */ + #ifndef _AXP_PMIC_H_ ++#define _AXP_PMIC_H_ ++ ++#include <stdbool.h> + +-#ifdef CONFIG_AXP152_POWER + #include <axp152.h> +-#endif +-#ifdef CONFIG_AXP209_POWER + #include <axp209.h> +-#endif +-#ifdef CONFIG_AXP221_POWER + #include <axp221.h> +-#endif +-#ifdef CONFIG_AXP305_POWER + #include <axp305.h> +-#endif +-#ifdef CONFIG_AXP809_POWER + #include <axp809.h> +-#endif +-#ifdef CONFIG_AXP818_POWER + #include <axp818.h> +-#endif ++ ++#define AXP_PMIC_MODE_REG 0x3e ++#define AXP_PMIC_MODE_I2C 0x00 ++#define AXP_PMIC_MODE_P2WI 0x3e ++#define AXP_PMIC_MODE_RSB 0x7c ++ ++#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3 ++#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d ++#define AXP_PMIC_SEC_DEVICE_ADDR 0x745 ++#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a + + int axp_set_dcdc1(unsigned int mvolt); + int axp_set_dcdc2(unsigned int mvolt); +diff -ruN u-boot-2021.10/include/clk/sunxi.h u-boot/include/clk/sunxi.h +--- u-boot-2021.10/include/clk/sunxi.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/clk/sunxi.h 2021-11-01 17:10:14.569575714 +0100 +@@ -0,0 +1,98 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018 Amarula Solutions. ++ * Author: Jagan Teki <jagan@amarulasolutions.com> ++ */ ++ ++#ifndef _CLK_SUNXI_H ++#define _CLK_SUNXI_H ++ ++#include <linux/bitops.h> ++ ++/** ++ * enum ccu_flags - ccu clock/reset flags ++ * ++ * @CCU_CLK_F_IS_VALID: is given clock gate is valid? ++ * @CCU_RST_F_IS_VALID: is given reset control is valid? ++ */ ++enum ccu_flags { ++ CCU_CLK_F_IS_VALID = BIT(0), ++ CCU_RST_F_IS_VALID = BIT(1), ++}; ++ ++/** ++ * struct ccu_clk_gate - ccu clock gate ++ * @off: gate offset ++ * @bit: gate bit ++ * @flags: ccu clock gate flags ++ */ ++struct ccu_clk_gate { ++ u16 off; ++ u32 bit; ++ enum ccu_flags flags; ++}; ++ ++#define GATE(_off, _bit) { \ ++ .off = _off, \ ++ .bit = _bit, \ ++ .flags = CCU_CLK_F_IS_VALID, \ ++} ++ ++/** ++ * struct ccu_reset - ccu reset ++ * @off: reset offset ++ * @bit: reset bit ++ * @flags: ccu reset control flags ++ */ ++struct ccu_reset { ++ u16 off; ++ u32 bit; ++ enum ccu_flags flags; ++}; ++ ++#define RESET(_off, _bit) { \ ++ .off = _off, \ ++ .bit = _bit, \ ++ .flags = CCU_RST_F_IS_VALID, \ ++} ++ ++/** ++ * struct ccu_desc - clock control unit descriptor ++ * ++ * @gates: clock gates ++ * @resets: reset unit ++ */ ++struct ccu_desc { ++ const struct ccu_clk_gate *gates; ++ const struct ccu_reset *resets; ++}; ++ ++/** ++ * struct ccu_priv - sunxi clock control unit ++ * ++ * @base: base address ++ * @desc: ccu descriptor ++ */ ++struct ccu_priv { ++ void *base; ++ const struct ccu_desc *desc; ++}; ++ ++/** ++ * sunxi_clk_probe - common sunxi clock probe ++ * @dev: clock device ++ */ ++int sunxi_clk_probe(struct udevice *dev); ++ ++extern struct clk_ops sunxi_clk_ops; ++ ++/** ++ * sunxi_reset_bind() - reset binding ++ * ++ * @dev: reset device ++ * @count: reset count ++ * @return 0 success, or error value ++ */ ++int sunxi_reset_bind(struct udevice *dev, ulong count); ++ ++#endif /* _CLK_SUNXI_H */ +diff -ruN u-boot-2021.10/include/clk.h u-boot/include/clk.h +--- u-boot-2021.10/include/clk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/clk.h 2021-11-01 17:10:14.569575714 +0100 +@@ -89,11 +89,36 @@ + + #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) + struct phandle_1_arg; +-int clk_get_by_driver_info(struct udevice *dev, +- struct phandle_1_arg *cells, struct clk *clk); ++/** ++ * clk_get_by_phandle() - Get a clock by its phandle information (of-platadata) ++ * ++ * This function is used when of-platdata is enabled. ++ * ++ * This looks up a clock using the phandle info. With dtoc, each phandle in the ++ * 'clocks' property is transformed into an idx representing the device. For ++ * example: ++ * ++ * clocks = <&dpll_mpu_ck 23>; ++ * ++ * might result in: ++ * ++ * .clocks = {1, {23}},}, ++ * ++ * indicating that the clock is udevice idx 1 in dt-plat.c with an argument of ++ * 23. This function can return a valid clock given the above information. In ++ * this example it would return a clock containing the 'dpll_mpu_ck' device and ++ * the clock ID 23. ++ * ++ * @dev: Device containing the phandle ++ * @cells: Phandle info ++ * @clock: A pointer to a clock struct to initialise ++ * @return 0 if OK, or a negative error code. ++ */ ++int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, ++ struct clk *clk); + + /** +- * clk_get_by_index - Get/request a clock by integer index. ++ * clk_get_by_index() - Get/request a clock by integer index. + * + * This looks up and requests a clock. The index is relative to the client + * device; each device is assumed to have n clocks associated with it somehow, +@@ -300,9 +325,7 @@ + CLK_DEFAULTS_POST_FORCE, + }; + +-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ +- CONFIG_IS_ENABLED(CLK) +- ++#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(CLK) + /** + * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}' + * properties to configure clocks +diff -ruN u-boot-2021.10/include/clock_legacy.h u-boot/include/clock_legacy.h +--- u-boot-2021.10/include/clock_legacy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/clock_legacy.h 2021-11-01 17:10:14.569575714 +0100 +@@ -11,4 +11,15 @@ + unsigned long get_bus_freq(unsigned long dummy); + int get_serial_clock(void); + ++/* ++ * If we have CONFIG_DYNAMIC_DDR_CLK_FREQ then there will be an ++ * implentation of get_board_ddr_clk() somewhere. Otherwise we have ++ * a static value to use now. ++ */ ++#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ ++unsigned long get_board_ddr_clk(void); ++#else ++#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ ++#endif ++ + #endif +diff -ruN u-boot-2021.10/include/config_distro_bootcmd.h u-boot/include/config_distro_bootcmd.h +--- u-boot-2021.10/include/config_distro_bootcmd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/config_distro_bootcmd.h 2021-11-01 17:10:14.572908865 +0100 +@@ -226,6 +226,7 @@ + "fi\0" \ + \ + "scsi_boot=" \ ++ BOOTENV_RUN_PCI_ENUM \ + BOOTENV_RUN_SCSI_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(scsi) + #define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV +diff -ruN u-boot-2021.10/include/config_fallbacks.h u-boot/include/config_fallbacks.h +--- u-boot-2021.10/include/config_fallbacks.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/config_fallbacks.h 2021-11-01 17:10:14.572908865 +0100 +@@ -46,10 +46,4 @@ + #define CONFIG_SYS_MAXARGS 16 + #endif + +-#if CONFIG_IS_ENABLED(DM_I2C) +-# ifdef CONFIG_SYS_I2C_LEGACY +-# error "Cannot define CONFIG_SYS_I2C_LEGACY when CONFIG_DM_I2C is used" +-# endif +-#endif +- + #endif /* __CONFIG_FALLBACKS_H */ +diff -ruN u-boot-2021.10/include/configs/10m50_devboard.h u-boot/include/configs/10m50_devboard.h +--- u-boot-2021.10/include/configs/10m50_devboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/10m50_devboard.h 2021-11-01 17:10:14.572908865 +0100 +@@ -47,7 +47,6 @@ + #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +-#define CONFIG_SYS_MALLOC_LEN 0x20000 + + /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above +@@ -57,10 +56,5 @@ + * (which is common practice). + */ + +-/* +- * MISC +- */ +-#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/3c120_devboard.h u-boot/include/configs/3c120_devboard.h +--- u-boot-2021.10/include/configs/3c120_devboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/3c120_devboard.h 2021-11-01 17:10:14.572908865 +0100 +@@ -47,7 +47,6 @@ + #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +-#define CONFIG_SYS_MALLOC_LEN 0x20000 + + /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above +@@ -57,10 +56,5 @@ + * (which is common practice). + */ + +-/* +- * MISC +- */ +-#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/adp-ae3xx.h u-boot/include/configs/adp-ae3xx.h +--- u-boot-2021.10/include/configs/adp-ae3xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/adp-ae3xx.h 2021-11-01 17:10:14.572908865 +0100 +@@ -15,8 +15,6 @@ + */ + #define CONFIG_USE_INTERRUPT + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_SKIP_TRUNOFF_WATCHDOG + + #define CONFIG_ARCH_MAP_SYSMEM +@@ -86,7 +84,6 @@ + * Size of malloc() pool + */ + /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +-#define CONFIG_SYS_MALLOC_LEN (512 << 10) + + /* + * Physical Memory Map +@@ -105,14 +102,6 @@ + GENERATED_GBL_DATA_SIZE) + + /* +- * Load address and memory test area should agree with +- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x300000 +- +-/* memtest works on 63 MB in DRAM */ +- +-/* + * Static memory controller configuration + */ + #define CONFIG_FTSMC020 +diff -ruN u-boot-2021.10/include/configs/adp-ag101p.h u-boot/include/configs/adp-ag101p.h +--- u-boot-2021.10/include/configs/adp-ag101p.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/adp-ag101p.h 2021-11-01 17:10:14.572908865 +0100 +@@ -15,8 +15,6 @@ + */ + #define CONFIG_USE_INTERRUPT + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_ARCH_MAP_SYSMEM + + #define CONFIG_BOOTP_SERVERIP +@@ -85,12 +83,6 @@ + */ + + /* +- * Size of malloc() pool +- */ +-/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +-#define CONFIG_SYS_MALLOC_LEN (512 << 10) +- +-/* + * AHB Controller configuration + */ + #define CONFIG_FTAHBC020S +@@ -217,14 +209,6 @@ + #endif /* CONFIG_MEM_REMAP */ + + /* +- * Load address and memory test area should agree with +- * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x300000 +- +-/* memtest works on 63 MB in DRAM */ +- +-/* + * Static memory controller configuration + */ + #define CONFIG_FTSMC020 +diff -ruN u-boot-2021.10/include/configs/am335x_evm.h u-boot/include/configs/am335x_evm.h +--- u-boot-2021.10/include/configs/am335x_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am335x_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -25,8 +25,6 @@ + + #define CONFIG_SYS_BOOTM_LEN SZ_16M + +-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM +- + /* Clock Defines */ + #define V_OSCK 24000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) +@@ -168,10 +166,6 @@ + #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ + #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + /* PMIC support */ + #define CONFIG_POWER_TPS65217 + #define CONFIG_POWER_TPS65910 +@@ -186,14 +180,7 @@ + + #ifdef CONFIG_MTD_RAW_NAND + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -204,9 +191,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 + /* NAND: SPL related configs */ + #ifdef CONFIG_SPL_OS_BOOT + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +@@ -267,8 +251,6 @@ + /* SPL related */ + #elif defined(CONFIG_EMMC_BOOT) + #define CONFIG_SYS_MMC_MAX_DEVICE 2 +-#elif defined(CONFIG_ENV_IS_IN_NAND) +-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #endif + + /* Network. */ +diff -ruN u-boot-2021.10/include/configs/am335x_guardian.h u-boot/include/configs/am335x_guardian.h +--- u-boot-2021.10/include/configs/am335x_guardian.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am335x_guardian.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,8 +22,6 @@ + #define V_OSCK 24000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + #ifndef CONFIG_SPL_BUILD + + #define MEM_LAYOUT_ENV_SETTINGS \ +@@ -108,14 +106,6 @@ + #define CONFIG_SYS_BOOTCOUNT_LE + + #ifdef CONFIG_MTD_RAW_NAND +- +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +-#define CONFIG_SYS_NAND_OOBSIZE 256 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +- + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ +@@ -140,12 +130,8 @@ + } + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 26 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW + #define MTDIDS_DEFAULT "nand0=nand.0" + +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +- + #endif /* CONFIG_MTD_RAW_NAND */ + + #define CONFIG_AM335X_USB0 +diff -ruN u-boot-2021.10/include/configs/am335x_igep003x.h u-boot/include/configs/am335x_igep003x.h +--- u-boot-2021.10/include/configs/am335x_igep003x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am335x_igep003x.h 2021-11-01 17:10:14.576242016 +0100 +@@ -103,16 +103,8 @@ + /* Ethernet support */ + + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION 1 + + /* NAND config */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -123,6 +115,5 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + + #endif /* ! __CONFIG_IGEP003X_H */ +diff -ruN u-boot-2021.10/include/configs/am335x_shc.h u-boot/include/configs/am335x_shc.h +--- u-boot-2021.10/include/configs/am335x_shc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am335x_shc.h 2021-11-01 17:10:14.576242016 +0100 +@@ -223,10 +223,4 @@ + #endif + + #define CONFIG_NET_RETRY_COUNT 10 +- +-/* I2C configuration */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +-#define CONFIG_SYS_I2C_SPEED 400000 +-#define CONFIG_SYS_I2C_SLAVE 1 + #endif /* ! __CONFIG_AM335X_SHC_H */ +diff -ruN u-boot-2021.10/include/configs/am335x_sl50.h u-boot/include/configs/am335x_sl50.h +--- u-boot-2021.10/include/configs/am335x_sl50.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am335x_sl50.h 2021-11-01 17:10:14.576242016 +0100 +@@ -16,8 +16,6 @@ + + #define CONFIG_SYS_BOOTM_LEN (16 << 20) + +-/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ +- + /* Clock Defines */ + #define V_OSCK 24000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) +@@ -55,10 +53,6 @@ + #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ + #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + /* PMIC support */ + #define CONFIG_POWER_TPS65217 + #define CONFIG_POWER_TPS65910 +diff -ruN u-boot-2021.10/include/configs/am3517_evm.h u-boot/include/configs/am3517_evm.h +--- u-boot-2021.10/include/configs/am3517_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am3517_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -14,34 +14,11 @@ + + #include <configs/ti_omap3_common.h> + +-#define CONFIG_REVISION_TAG +- +-/* Hardware drivers */ +- +-/* +- * USB configuration +- * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard +- * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. +- */ +-#ifdef CONFIG_SPL_BUILD +-#undef CONFIG_USB_EHCI_OMAP +-#else +-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 +-#endif +- +-/* I2C */ +- + /* Ethernet */ + #define CONFIG_NET_RETRY_COUNT 10 + + /* Board NAND Info. */ + #ifdef CONFIG_MTD_RAW_NAND +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ + 11, 12, 13, 14, 16, 17, 18, 19, 20, \ + 21, 22, 23, 24, 25, 26, 27, 28, 30, \ +@@ -51,11 +28,9 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 13 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + #define CONFIG_SYS_NAND_MAX_ECCPOS 56 + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 + /* NAND block size is 128 KiB. Synchronize these values with + * corresponding Device Tree entries in Linux: +diff -ruN u-boot-2021.10/include/configs/am43xx_evm.h u-boot/include/configs/am43xx_evm.h +--- u-boot-2021.10/include/configs/am43xx_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am43xx_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -21,15 +21,8 @@ + #endif + + /* I2C Configuration */ +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* Power */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C +-#endif + #define CONFIG_POWER_TPS65218 + #define CONFIG_POWER_TPS62362 + +@@ -42,14 +35,6 @@ + #define CONFIG_SYS_PL310_BASE 0x48242000 + + /* +- * Since SPL did pll and ddr initialization for us, +- * we don't need to do it twice. +- */ +-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- +-/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. +@@ -69,12 +54,9 @@ + + #if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) + #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 +-#define CONFIG_USB_XHCI_OMAP +- +-#define CONFIG_AM437X_USB2PHY2_HOST + #endif + +-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER) ++#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_GADGET) + #undef CONFIG_USB_DWC3_PHY_OMAP + #undef CONFIG_USB_DWC3_OMAP + #undef CONFIG_USB_DWC3 +@@ -175,16 +157,7 @@ + /* NAND support */ + #ifdef CONFIG_MTD_RAW_NAND + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +-#define CONFIG_SYS_NAND_OOBSIZE 224 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ +@@ -209,7 +182,6 @@ + } + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 26 +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 + /* NAND: SPL related configs */ + /* NAND: SPL falcon mode configs */ + #ifdef CONFIG_SPL_OS_BOOT +diff -ruN u-boot-2021.10/include/configs/am57xx_evm.h u-boot/include/configs/am57xx_evm.h +--- u-boot-2021.10/include/configs/am57xx_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am57xx_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,10 +22,6 @@ + #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ + #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ + +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + #define CONFIG_SYS_OMAP_ABE_SYSCK + + #ifndef CONFIG_SPL_BUILD +@@ -52,11 +48,6 @@ + #define CONFIG_NET_RETRY_COUNT 10 + #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ + +-/* USB xHCI HOST */ +-#define CONFIG_USB_XHCI_OMAP +- +-#define CONFIG_OMAP_USB3PHY1_HOST +- + /* SATA */ + #define CONFIG_SCSI_AHCI_PLAT + #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +diff -ruN u-boot-2021.10/include/configs/am64x_evm.h u-boot/include/configs/am64x_evm.h +--- u-boot-2021.10/include/configs/am64x_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am64x_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,10 +22,6 @@ + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" + #endif + +-#ifndef CONFIG_CPU_V7R +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- + #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + #if defined(CONFIG_TARGET_AM642_A53_EVM) + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ +diff -ruN u-boot-2021.10/include/configs/am65x_evm.h u-boot/include/configs/am65x_evm.h +--- u-boot-2021.10/include/configs/am65x_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/am65x_evm.h 2021-11-01 17:10:14.576242016 +0100 +@@ -49,10 +49,6 @@ + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" + #endif + +-#ifndef CONFIG_CPU_V7R +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- + #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + + #define CONFIG_SYS_BOOTM_LEN SZ_64M +diff -ruN u-boot-2021.10/include/configs/amcore.h u-boot/include/configs/amcore.h +--- u-boot-2021.10/include/configs/amcore.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/amcore.h 2021-11-01 17:10:14.576242016 +0100 +@@ -13,7 +13,6 @@ + #define CONFIG_MCFTMR + #define CONFIG_MCFUART + #define CONFIG_SYS_UART_PORT 0 +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + #define CONFIG_BOOTCOMMAND "bootm ffc20000" + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -28,10 +27,6 @@ + "erase 0xfff00000 0xffffffff; " \ + "cp.b 0x20000 0xfff00000 ${filesize}\0" + +-/* undef to save memory */ +- +-#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ +- + #define CONFIG_SYS_HZ 1000 + + #define CONFIG_SYS_CLK 45000000 +@@ -58,7 +53,6 @@ + /* reserve 128-4KB */ + #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) + #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) + + #define LDS_BOARD_TEXT \ +@@ -75,7 +69,6 @@ + * This is a single unified instruction/data cache. + * sdram - single region - no masks + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +@@ -99,4 +92,3 @@ + #define CONFIG_SYS_CS1_CTRL 0x0100 + + #endif /* __AMCORE_CONFIG_H */ +- +diff -ruN u-boot-2021.10/include/configs/ap121.h u-boot/include/configs/ap121.h +--- u-boot-2021.10/include/configs/ap121.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ap121.h 2021-11-01 17:10:14.576242016 +0100 +@@ -12,20 +12,15 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x40000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 + + #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {9600, 19200, 38400, 57600, 115200} +- + #define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f650000" +diff -ruN u-boot-2021.10/include/configs/ap143.h u-boot/include/configs/ap143.h +--- u-boot-2021.10/include/configs/ap143.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ap143.h 2021-11-01 17:10:14.576242016 +0100 +@@ -12,11 +12,9 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x40000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 + + #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +@@ -27,8 +25,6 @@ + * Serial Port + */ + #define CONFIG_SYS_NS16550_CLK 25000000 +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {9600, 19200, 38400, 57600, 115200} + + #define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ +diff -ruN u-boot-2021.10/include/configs/ap152.h u-boot/include/configs/ap152.h +--- u-boot-2021.10/include/configs/ap152.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ap152.h 2021-11-01 17:10:14.576242016 +0100 +@@ -12,11 +12,9 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x40000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 + + #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +@@ -27,8 +25,6 @@ + * Serial Port + */ + #define CONFIG_SYS_NS16550_CLK 25000000 +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {9600, 19200, 38400, 57600, 115200} + + #define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ +diff -ruN u-boot-2021.10/include/configs/apalis_imx6.h u-boot/include/configs/apalis_imx6.h +--- u-boot-2021.10/include/configs/apalis_imx6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/apalis_imx6.h 2021-11-01 17:10:14.576242016 +0100 +@@ -14,8 +14,6 @@ + + #undef CONFIG_DISPLAY_BOARDINFO + +-#define CONFIG_MACH_TYPE 4886 +- + #include <asm/arch/imx-regs.h> + #include <asm/mach-imx/gpio.h> + +@@ -23,25 +21,8 @@ + #include "imx6_spl.h" + #endif + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SERIAL_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#define CONFIG_SYS_MXC_I2C3_SPEED 400000 +- + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_FSL_USDHC_NUM 3 +@@ -80,8 +61,6 @@ + #undef CONFIG_SERVERIP + #define CONFIG_SERVERIP 192.168.10.1 + +-#define CONFIG_LOADADDR 0x12000000 +- + #ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ +@@ -162,7 +141,7 @@ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" + + /* Miscellaneous configurable options */ +@@ -171,8 +150,6 @@ + #undef CONFIG_SYS_MAXARGS + #define CONFIG_SYS_MAXARGS 48 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical Memory Map */ + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +diff -ruN u-boot-2021.10/include/configs/apalis-imx8.h u-boot/include/configs/apalis-imx8.h +--- u-boot-2021.10/include/configs/apalis-imx8.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/apalis-imx8.h 2021-11-01 17:10:14.576242016 +0100 +@@ -18,8 +18,6 @@ + #define USDHC2_BASE_ADDR 0x5b020000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + /* Networking */ + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 +@@ -70,9 +68,6 @@ + "${blkcnt}; fi\0" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -83,9 +78,6 @@ + + #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/apalis-imx8x.h u-boot/include/configs/apalis-imx8x.h +--- u-boot-2021.10/include/configs/apalis-imx8x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/apalis-imx8x.h 2021-11-01 17:10:14.576242016 +0100 +@@ -17,8 +17,6 @@ + #define USDHC2_BASE_ADDR 0x5b020000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 + #define CONFIG_SERVERIP 192.168.10.1 +@@ -97,9 +95,6 @@ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x89000000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -112,9 +107,6 @@ + + #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/apalis_t30.h u-boot/include/configs/apalis_t30.h +--- u-boot-2021.10/include/configs/apalis_t30.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/apalis_t30.h 2021-11-01 17:10:14.576242016 +0100 +@@ -23,8 +23,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTA + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 +- + /* PCI networking support */ + #define CONFIG_E1000_NO_NVM + +diff -ruN u-boot-2021.10/include/configs/aristainetos2.h u-boot/include/configs/aristainetos2.h +--- u-boot-2021.10/include/configs/aristainetos2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/aristainetos2.h 2021-11-01 17:10:14.576242016 +0100 +@@ -28,7 +28,6 @@ + + #include "mx6_common.h" + +-#define CONFIG_MACH_TYPE 4501 + #define CONFIG_MMCROOT "/dev/mmcblk0p1" + + /* MMC Configs */ +@@ -93,13 +92,13 @@ + #endif + + #if (CONFIG_SYS_BOARD_VERSION == 5) +-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ ++#define EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; sleep 1;" \ + "led led_red off; sleep 1;" \ + "done\0" + #elif (CONFIG_SYS_BOARD_VERSION == 6) +-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ ++#define EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; led led_red2 on; sleep 1;" \ + "led led_red off; led led_red2 off;; sleep 1;" \ +@@ -414,7 +413,7 @@ + "run main_rescue_boot;" \ + "fi; \0"\ + HAB_EXTRA_SETTINGS \ +- CONFIG_EXTRA_ENV_BOARD_SETTINGS ++ EXTRA_ENV_BOARD_SETTINGS + + #define CONFIG_ARP_TIMEOUT 200UL + +diff -ruN u-boot-2021.10/include/configs/armadillo-800eva.h u-boot/include/configs/armadillo-800eva.h +--- u-boot-2021.10/include/configs/armadillo-800eva.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/armadillo-800eva.h 2021-11-01 17:10:14.576242016 +0100 +@@ -44,12 +44,9 @@ + + #define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) + #define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ +- 64 * 1024 * 1024) + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 + #define CONFIG_SYS_MONITOR_LEN (256 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + + /* FLASH */ +diff -ruN u-boot-2021.10/include/configs/aspeed-common.h u-boot/include/configs/aspeed-common.h +--- u-boot-2021.10/include/configs/aspeed-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/aspeed-common.h 2021-11-01 17:10:14.576242016 +0100 +@@ -13,9 +13,6 @@ + #include <asm/arch/platform.h> + + /* Misc CPU related */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG + + #define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE + +@@ -32,8 +29,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN (32 << 20) +- + /* + * NS16550 Configuration + */ +diff -ruN u-boot-2021.10/include/configs/aspenite.h u-boot/include/configs/aspenite.h +--- u-boot-2021.10/include/configs/aspenite.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/aspenite.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,32 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2010 +- * Marvell Semiconductor <www.marvell.com> +- * Written-by: Prafulla Wadaskar <prafulla@marvell.com> +- * Contributor: Mahavir Jain <mjain@marvell.com> +- */ +- +-#ifndef __CONFIG_ASPENITE_H +-#define __CONFIG_ASPENITE_H +- +-/* +- * High Level Configuration Options +- */ +-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ +-#define CONFIG_ARMADA100 1 /* SOC Family Name */ +-#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +- +-/* +- * There is no internal RAM in ARMADA100, using DRAM +- * TBD: dcache to be used for this +- */ +-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) +- +-#include "mv-common.h" +- +-/* +- * Environment variables configurations +- */ +- +-#endif /* __CONFIG_ASPENITE_H */ +diff -ruN u-boot-2021.10/include/configs/astro_mcf5373l.h u-boot/include/configs/astro_mcf5373l.h +--- u-boot-2021.10/include/configs/astro_mcf5373l.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/astro_mcf5373l.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,17 +22,17 @@ + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +-#define CONFIG_ASTRO_V532 1 ++#define ASTRO_V532 1 + +-#if CONFIG_ASTRO_V532 ++#if ASTRO_V532 + #define ASTRO_ID 0xF8 +-#elif CONFIG_ASTRO_V512 ++#elif ASTRO_V512 + #define ASTRO_ID 0xFA +-#elif CONFIG_ASTRO_TWIN7S2 ++#elif ASTRO_TWIN7S2 + #define ASTRO_ID 0xF9 +-#elif CONFIG_ASTRO_V912 ++#elif ASTRO_V912 + #define ASTRO_ID 0xFC +-#elif CONFIG_ASTRO_COFDMDUOS2 ++#elif ASTRO_COFDMDUOS2 + #define ASTRO_ID 0xFB + #else + #error No card type defined! +@@ -58,11 +58,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + + /* +@@ -149,7 +144,7 @@ + #ifdef CONFIG_MONITOR_IS_IN_RAM + #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ + #else +-#if CONFIG_ASTRO_V532 ++#if ASTRO_V532 + #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +@@ -159,9 +154,6 @@ + #endif + #endif + +-/* default RAM address for user programs */ +-#define CONFIG_SYS_LOAD_ADDR 0x20000 +- + #define CONFIG_FPGA_COUNT 1 + #define CONFIG_SYS_FPGA_PROG_FEEDBACK + #define CONFIG_SYS_FPGA_WAIT 1000 +@@ -240,8 +232,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) + + #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +-/* Reserve 128 kB for malloc() */ +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) + + /* + * For booting Linux, the board info and command line data +@@ -272,7 +262,6 @@ + #endif + + /* Cache Configuration */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/at91sam9260ek.h u-boot/include/configs/at91sam9260ek.h +--- u-boot-2021.10/include/configs/at91sam9260ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9260ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -35,10 +35,6 @@ + #endif + + /* Misc CPU related */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT + + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +@@ -68,24 +64,6 @@ + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-/* +- * The (arm)linux board id set by generic code depending on configured board +- * (see boards.cfg for different boards) +- */ +-#ifdef CONFIG_AT91SAM9G20 +- /* the sam9g20 variants have two different board ids */ +-# ifdef CONFIG_AT91SAM9G20EK_2MMC +- /* we may be setup for the 2MMC variant of at91sam9g20ek */ +-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC +-# else +- /* or the normal at91sam9g20ek */ +-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK +-# endif +-#else +- /* otherwise default to good old at91sam9260ek */ +-# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK +-#endif +- + /* NAND flash */ + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -106,8 +84,6 @@ + #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + + /* bootstrap + u-boot + env + linux in dataflash on CS0 */ +@@ -134,9 +110,4 @@ + "fatload mmc 0:1 0x22000000 uImage; bootm" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/at91sam9261ek.h u-boot/include/configs/at91sam9261ek.h +--- u-boot-2021.10/include/configs/at91sam9261ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9261ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,12 +22,6 @@ + + #include <asm/hardware.h> + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_ATMEL_LEGACY + + /* +@@ -93,8 +87,6 @@ + #endif + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + + /* bootstrap + u-boot + env + linux in dataflash on CS0 */ +@@ -115,9 +107,4 @@ + #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/at91sam9263ek.h u-boot/include/configs/at91sam9263ek.h +--- u-boot-2021.10/include/configs/at91sam9263ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9263ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -22,12 +22,7 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 +-#define CONFIG_INITRD_TAG 1 +- + #ifndef CONFIG_SYS_USE_BOOT_NORFLASH +-#define CONFIG_SKIP_LOWLEVEL_INIT + #else + #define CONFIG_SYS_USE_NORFLASH + #endif +@@ -91,7 +86,7 @@ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ +- AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ ++ AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + + /* PCK/2 = MCK Master Clock from PLLA */ +@@ -101,7 +96,7 @@ + + /* PCK/2 = MCK Master Clock from PLLA */ + #define CONFIG_SYS_MCKR2_VAL \ +- (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ ++ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + + /* define PDC[31:16] as DATA[31:16] */ +@@ -209,8 +204,6 @@ + #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_SYS_USE_DATAFLASH + + /* bootstrap + u-boot + env + linux in dataflash on CS0 */ +@@ -224,9 +217,4 @@ + #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/at91sam9m10g45ek.h u-boot/include/configs/at91sam9m10g45ek.h +--- u-boot-2021.10/include/configs/at91sam9m10g45ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9m10g45ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -18,11 +18,6 @@ + + #define CONFIG_AT91SAM9M10G45EK + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +@@ -67,8 +62,6 @@ + #define CONFIG_RESET_PHY_R + #define CONFIG_AT91_WANTS_COMMON_PHY + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_NAND_BOOT + /* bootstrap + u-boot + env in nandflash */ + +@@ -83,11 +76,6 @@ + "bootz 0x72000000 - 0x71000000" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + /* Defines for SPL */ + #define CONFIG_SPL_MAX_SIZE 0x010000 + #define CONFIG_SPL_STACK 0x310000 +@@ -105,17 +93,10 @@ + + #elif CONFIG_NAND_BOOT + #define CONFIG_SPL_NAND_SOFTECC +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +diff -ruN u-boot-2021.10/include/configs/at91sam9n12ek.h u-boot/include/configs/at91sam9n12ek.h +--- u-boot-2021.10/include/configs/at91sam9n12ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9n12ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -14,10 +14,6 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ + + /* Misc CPU related */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT + + /* LCD */ + #define LCD_BPP LCD_COLOR16 +@@ -61,9 +57,6 @@ + "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ + "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" + +-/* Ethernet */ +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* USB host */ + #ifdef CONFIG_CMD_USB + #define CONFIG_USB_ATMEL +@@ -102,11 +95,6 @@ + + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +- + /* SPL */ + #define CONFIG_SPL_MAX_SIZE 0x6000 + #define CONFIG_SPL_STACK 0x308000 +@@ -126,12 +114,5 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + #endif +diff -ruN u-boot-2021.10/include/configs/at91sam9rlek.h u-boot/include/configs/at91sam9rlek.h +--- u-boot-2021.10/include/configs/at91sam9rlek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9rlek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -16,12 +16,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 +-#define CONFIG_INITRD_TAG 1 +- + #define CONFIG_ATMEL_LEGACY + + /* +@@ -62,10 +56,6 @@ + + /* Ethernet - not present */ + +-/* USB - not supported */ +- +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_SYS_USE_DATAFLASH + + /* bootstrap + u-boot + env + linux in dataflash on CS0 */ +@@ -87,10 +77,4 @@ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" + #endif +- +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/at91sam9x5ek.h u-boot/include/configs/at91sam9x5ek.h +--- u-boot-2021.10/include/configs/at91sam9x5ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91sam9x5ek.h 2021-11-01 17:10:14.576242016 +0100 +@@ -12,11 +12,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +@@ -65,8 +60,6 @@ + #endif + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_NAND_BOOT + /* bootstrap + u-boot + env + linux in nandflash */ + #define CONFIG_BOOTCOMMAND "nand read " \ +@@ -85,11 +78,6 @@ + "bootm 0x22000000" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) +- + /* SPL */ + #define CONFIG_SPL_MAX_SIZE 0x6000 + #define CONFIG_SPL_STACK 0x308000 +@@ -109,12 +97,5 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + #endif +diff -ruN u-boot-2021.10/include/configs/at91-sama5_common.h u-boot/include/configs/at91-sama5_common.h +--- u-boot-2021.10/include/configs/at91-sama5_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/at91-sama5_common.h 2021-11-01 17:10:14.576242016 +0100 +@@ -15,10 +15,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- + /* + * BOOTP options + */ +@@ -54,7 +50,4 @@ + + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +- + #endif +diff -ruN u-boot-2021.10/include/configs/ax25-ae350.h u-boot/include/configs/ax25-ae350.h +--- u-boot-2021.10/include/configs/ax25-ae350.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ax25-ae350.h 2021-11-01 17:10:14.576242016 +0100 +@@ -12,7 +12,7 @@ + #define CONFIG_SPL_BSS_START_ADDR 0x04000000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 + +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" + #endif + #endif +@@ -47,12 +47,6 @@ + */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-/* +- * Size of malloc() pool +- * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough +- */ +-#define CONFIG_SYS_MALLOC_LEN (512 << 10) +- + /* DT blob (fdt) address */ + #define CONFIG_SYS_FDT_BASE 0x800f0000 + +@@ -79,20 +73,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ + GENERATED_GBL_DATA_SIZE) + +-/* +- * Load address and memory test area should agree with +- * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ +- +-/* +- * memtest works on 512 MB in DRAM +- */ +- +-/* +- * FLASH and environment organization +- */ +- + /* use CFI framework */ + + #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +diff -ruN u-boot-2021.10/include/configs/axs10x.h u-boot/include/configs/axs10x.h +--- u-boot-2021.10/include/configs/axs10x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/axs10x.h 2021-11-01 17:10:14.576242016 +0100 +@@ -27,9 +27,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + #define CONFIG_SYS_BOOTM_LEN SZ_128M +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + + /* + * UART configuration +@@ -63,7 +61,6 @@ + * Environment configuration + */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + /* + * Console configuration +diff -ruN u-boot-2021.10/include/configs/baltos.h u-boot/include/configs/baltos.h +--- u-boot-2021.10/include/configs/baltos.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/baltos.h 2021-11-01 17:10:14.576242016 +0100 +@@ -19,8 +19,6 @@ + #include <linux/sizes.h> + #include <configs/ti_am335x_common.h> + +-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM +- + /* Clock Defines */ + #define V_OSCK 24000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) +@@ -204,10 +202,6 @@ + #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ + #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + /* PMIC support */ + #define CONFIG_POWER_TPS65910 + +@@ -215,13 +209,6 @@ + #ifndef CONFIG_NOR_BOOT + + #ifdef CONFIG_MTD_RAW_NAND +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -232,8 +219,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + #endif + #endif +diff -ruN u-boot-2021.10/include/configs/bcm7260.h u-boot/include/configs/bcm7260.h +--- u-boot-2021.10/include/configs/bcm7260.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bcm7260.h 2021-11-01 17:10:14.576242016 +0100 +@@ -15,8 +15,6 @@ + #define CONFIG_SYS_TEXT_BASE 0x10100000 + #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 + +-#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ +- + #include "bcmstb.h" + + #define BCMSTB_TIMER_LOW 0xf0412008 +diff -ruN u-boot-2021.10/include/configs/bcm7445.h u-boot/include/configs/bcm7445.h +--- u-boot-2021.10/include/configs/bcm7445.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bcm7445.h 2021-11-01 17:10:14.576242016 +0100 +@@ -15,8 +15,6 @@ + #define CONFIG_SYS_TEXT_BASE 0x80100000 + #define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 + +-#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ +- + #include "bcmstb.h" + + #define BCMSTB_TIMER_LOW 0xf0412008 +diff -ruN u-boot-2021.10/include/configs/bcm_ns3.h u-boot/include/configs/bcm_ns3.h +--- u-boot-2021.10/include/configs/bcm_ns3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bcm_ns3.h 2021-11-01 17:10:14.576242016 +0100 +@@ -16,7 +16,6 @@ + #define PHYS_SDRAM_1 V2M_BASE + + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000) + + /* + * Initial SP before reloaction is placed at end of first DRAM bank, +@@ -26,7 +25,6 @@ + */ + #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) + /* 12MB Malloc size */ +-#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M) + + /* console configuration */ + #define CONFIG_SYS_NS16550_CLK 25000000 +diff -ruN u-boot-2021.10/include/configs/bcmstb.h u-boot/include/configs/bcmstb.h +--- u-boot-2021.10/include/configs/bcmstb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bcmstb.h 2021-11-01 17:10:14.576242016 +0100 +@@ -10,7 +10,6 @@ + #ifndef __BCMSTB_H + #define __BCMSTB_H + +-#include "version.h" + #include <linux/sizes.h> + + #ifndef __ASSEMBLY__ +@@ -36,7 +35,6 @@ + /* + * CPU configuration. + */ +-#define CONFIG_SKIP_LOWLEVEL_INIT + + /* + * Memory configuration. +@@ -88,7 +86,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 + + /* + * CONFIG_SYS_LOAD_ADDR - 1 MiB. +@@ -121,7 +118,6 @@ + /* + * Informational display configuration. + */ +-#define CONFIG_REVISION_TAG + + /* + * Command configuration. +diff -ruN u-boot-2021.10/include/configs/beaver.h u-boot/include/configs/beaver.h +--- u-boot-2021.10/include/configs/beaver.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/beaver.h 2021-11-01 17:10:14.576242016 +0100 +@@ -20,8 +20,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTA + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER +- + /* SPI */ + #define CONFIG_TEGRA_SLINK_CTRLS 6 + #define CONFIG_SPI_FLASH_SIZE (4 << 20) +diff -ruN u-boot-2021.10/include/configs/bg0900.h u-boot/include/configs/bg0900.h +--- u-boot-2021.10/include/configs/bg0900.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bg0900.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,41 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2013 Marek Vasut <marex@denx.de> +- */ +-#ifndef __CONFIGS_BG0900_H__ +-#define __CONFIGS_BG0900_H__ +- +-/* Memory configuration */ +-#define PHYS_SDRAM_1 0x40000000 /* Base address */ +-#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +- +-/* Environment */ +- +-/* FEC Ethernet on SoC */ +-#ifdef CONFIG_CMD_NET +-#define CONFIG_FEC_MXC +-#endif +- +-/* Boot Linux */ +-#define CONFIG_BOOTFILE "uImage" +-#define CONFIG_BOOTCOMMAND "bootm" +-#define CONFIG_LOADADDR 0x42000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- +-/* Extra Environment */ +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "update_spi_firmware_filename=u-boot.sb\0" \ +- "update_spi_firmware_maxsz=0x80000\0" \ +- "update_spi_firmware=" /* Update the SPI flash firmware */ \ +- "if sf probe 2:0 ; then " \ +- "if tftp ${update_spi_firmware_filename} ; then " \ +- "sf erase 0x0 +${filesize} ; " \ +- "sf write ${loadaddr} 0x0 ${filesize} ; " \ +- "fi ; " \ +- "fi\0" +- +-/* The rest of the configuration is shared */ +-#include <configs/mxs.h> +- +-#endif /* __CONFIGS_BG0900_H__ */ +diff -ruN u-boot-2021.10/include/configs/bk4r1.h u-boot/include/configs/bk4r1.h +--- u-boot-2021.10/include/configs/bk4r1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bk4r1.h 2021-11-01 17:10:14.576242016 +0100 +@@ -60,16 +60,7 @@ + #include <asm/arch/imx-regs.h> + #include <linux/sizes.h> + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- +-/* Enable passing of ATAGs */ +-#define CONFIG_CMDLINE_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) +- + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define IMX_FEC1_BASE ENET1_BASE_ADDR +@@ -81,8 +72,6 @@ + #define CONFIG_SYS_FSL_QSPI_LE + #endif + +-#define CONFIG_LOADADDR 0x82000000 +- + /* We boot from the gfxRAM area of the OCRAM. */ + #define CONFIG_BOARD_SIZE_LIMIT 520192 + +@@ -230,10 +219,6 @@ + "source to NAND\0" \ + "active_workset=1\0" + +-/* Miscellaneous configurable options */ +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical memory map */ + #define PHYS_SDRAM (0x80000000) + #define PHYS_SDRAM_SIZE (SZ_512M) +diff -ruN u-boot-2021.10/include/configs/bmips_bcm3380.h u-boot/include/configs/bmips_bcm3380.h +--- u-boot-2021.10/include/configs/bmips_bcm3380.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm3380.h 2021-11-01 17:10:14.576242016 +0100 +@@ -15,10 +15,8 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6318.h u-boot/include/configs/bmips_bcm6318.h +--- u-boot-2021.10/include/configs/bmips_bcm6318.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6318.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm63268.h u-boot/include/configs/bmips_bcm63268.h +--- u-boot-2021.10/include/configs/bmips_bcm63268.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm63268.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6328.h u-boot/include/configs/bmips_bcm6328.h +--- u-boot-2021.10/include/configs/bmips_bcm6328.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6328.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6338.h u-boot/include/configs/bmips_bcm6338.h +--- u-boot-2021.10/include/configs/bmips_bcm6338.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6338.h 2021-11-01 17:10:14.579575167 +0100 +@@ -15,10 +15,8 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6348.h u-boot/include/configs/bmips_bcm6348.h +--- u-boot-2021.10/include/configs/bmips_bcm6348.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6348.h 2021-11-01 17:10:14.579575167 +0100 +@@ -22,10 +22,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6358.h u-boot/include/configs/bmips_bcm6358.h +--- u-boot-2021.10/include/configs/bmips_bcm6358.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6358.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6362.h u-boot/include/configs/bmips_bcm6362.h +--- u-boot-2021.10/include/configs/bmips_bcm6362.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6362.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6368.h u-boot/include/configs/bmips_bcm6368.h +--- u-boot-2021.10/include/configs/bmips_bcm6368.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6368.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,10 +24,8 @@ + #endif /* CONFIG_USB_OHCI_HCD */ + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_bcm6838.h u-boot/include/configs/bmips_bcm6838.h +--- u-boot-2021.10/include/configs/bmips_bcm6838.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_bcm6838.h 2021-11-01 17:10:14.579575167 +0100 +@@ -15,10 +15,8 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + + /* U-Boot */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M + + #if defined(CONFIG_BMIPS_BOOT_RAM) +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K + #endif + +diff -ruN u-boot-2021.10/include/configs/bmips_common.h u-boot/include/configs/bmips_common.h +--- u-boot-2021.10/include/configs/bmips_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bmips_common.h 2021-11-01 17:10:14.579575167 +0100 +@@ -18,7 +18,6 @@ + + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 24 +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + #define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K + #define CONFIG_SYS_CBSIZE SZ_512 + +diff -ruN u-boot-2021.10/include/configs/boston.h u-boot/include/configs/boston.h +--- u-boot-2021.10/include/configs/boston.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/boston.h 2021-11-01 17:10:14.579575167 +0100 +@@ -33,10 +33,6 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) +- +-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) +- + /* + * Console + */ +diff -ruN u-boot-2021.10/include/configs/broadcom_bcm963158.h u-boot/include/configs/broadcom_bcm963158.h +--- u-boot-2021.10/include/configs/broadcom_bcm963158.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/broadcom_bcm963158.h 2021-11-01 17:10:14.579575167 +0100 +@@ -14,7 +14,6 @@ + 230400, 500000, 1500000 } + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 24 +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + #define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) + + /* +@@ -26,17 +25,12 @@ + + /* U-Boot */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +- +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* CONFIG_MTD_RAW_NAND */ + + /* + * bcm963158 + */ +- +diff -ruN u-boot-2021.10/include/configs/broadcom_bcm968360bg.h u-boot/include/configs/broadcom_bcm968360bg.h +--- u-boot-2021.10/include/configs/broadcom_bcm968360bg.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/broadcom_bcm968360bg.h 2021-11-01 17:10:14.579575167 +0100 +@@ -14,7 +14,6 @@ + 230400, 500000, 1500000 } + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 24 +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + + /* + * 6858 +@@ -25,14 +24,10 @@ + + /* U-Boot */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +- +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* CONFIG_MTD_RAW_NAND */ + + /* +diff -ruN u-boot-2021.10/include/configs/broadcom_bcm968380gerg.h u-boot/include/configs/broadcom_bcm968380gerg.h +--- u-boot-2021.10/include/configs/broadcom_bcm968380gerg.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/broadcom_bcm968380gerg.h 2021-11-01 17:10:14.579575167 +0100 +@@ -9,5 +9,4 @@ + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* CONFIG_MTD_RAW_NAND */ +diff -ruN u-boot-2021.10/include/configs/broadcom_bcm968580xref.h u-boot/include/configs/broadcom_bcm968580xref.h +--- u-boot-2021.10/include/configs/broadcom_bcm968580xref.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/broadcom_bcm968580xref.h 2021-11-01 17:10:14.579575167 +0100 +@@ -14,7 +14,6 @@ + 230400, 500000, 1500000 } + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 24 +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + + /* + * 6858 +@@ -25,17 +24,12 @@ + + /* U-Boot */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +- +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* CONFIG_MTD_RAW_NAND */ + + /* + * 968580xref + */ +- +diff -ruN u-boot-2021.10/include/configs/brppt1.h u-boot/include/configs/brppt1.h +--- u-boot-2021.10/include/configs/brppt1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/brppt1.h 2021-11-01 17:10:14.579575167 +0100 +@@ -16,7 +16,6 @@ + #include <linux/stringify.h> + /* ------------------------------------------------------------------------- */ + /* memory */ +-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + #define CONFIG_SYS_BOOTM_LEN SZ_32M + + /* Clock Defines */ +@@ -25,13 +24,6 @@ + + #define CONFIG_POWER_TPS65217 + +-/* Support both device trees and ATAGs. */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-/*#define CONFIG_MACH_TYPE 3589*/ +-#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ +- + /* + * When we have NAND flash we expect to be making use of mtdparts, + * both for ease of use in U-Boot and for passing information on to +@@ -54,7 +46,6 @@ + + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* CONFIG_MTD_RAW_NAND */ + + #ifdef CONFIG_MTD_RAW_NAND +@@ -153,14 +144,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x8000000 + /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +diff -ruN u-boot-2021.10/include/configs/brppt2.h u-boot/include/configs/brppt2.h +--- u-boot-2021.10/include/configs/brppt2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/brppt2.h 2021-11-01 17:10:14.579575167 +0100 +@@ -20,20 +20,12 @@ + #define CONFIG_BOARD_POSTCLK_INIT + #define CONFIG_MXC_GPT_HCLK + +-#define CONFIG_LOADADDR 0x10700000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* MMC */ + #define CONFIG_FSL_USDHC + + /* Boot */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_MACH_TYPE 0xFFFFFFFF + + /* misc */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + + /* Environment */ + +diff -ruN u-boot-2021.10/include/configs/brsmarc1.h u-boot/include/configs/brsmarc1.h +--- u-boot-2021.10/include/configs/brsmarc1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/brsmarc1.h 2021-11-01 17:10:14.579575167 +0100 +@@ -18,15 +18,12 @@ + /* ------------------------------------------------------------------------- */ + + /* memory */ +-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + + /* Clock Defines */ + #define V_OSCK 26000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) + +-#define CONFIG_MACH_TYPE 3589 +- + #ifndef CONFIG_SPL_BUILD + + /* Default environment */ +@@ -61,11 +58,6 @@ + " bootm ${loadaddr} - ${dtbaddr}\0" + #endif /* !CONFIG_SPL_BUILD*/ + +-/* Support both device trees and ATAGs. */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + /* SPI Flash */ + + /* Environment */ +diff -ruN u-boot-2021.10/include/configs/brxre1.h u-boot/include/configs/brxre1.h +--- u-boot-2021.10/include/configs/brxre1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/brxre1.h 2021-11-01 17:10:14.579575167 +0100 +@@ -18,14 +18,11 @@ + #define LCD_BPP LCD_COLOR32 + + /* memory */ +-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + + /* Clock Defines */ + #define V_OSCK 26000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) + +-#define CONFIG_MACH_TYPE 3589 +- + #ifndef CONFIG_SPL_BUILD + + /* Default environment */ +@@ -58,11 +55,6 @@ + + #define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" + +-/* Support both device trees and ATAGs. */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + /* Environment */ + + #endif /* __CONFIG_BRXRE1_H__ */ +diff -ruN u-boot-2021.10/include/configs/bur_am335x_common.h u-boot/include/configs/bur_am335x_common.h +--- u-boot-2021.10/include/configs/bur_am335x_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/bur_am335x_common.h 2021-11-01 17:10:14.579575167 +0100 +@@ -19,8 +19,6 @@ + #define CONFIG_SYS_NS16550_CLK (48000000) + #define CONFIG_SYS_NS16550_COM1 0x44e09000 + +-#define CONFIG_SYS_I2C_LEGACY +- + #endif /* CONFIG_DM */ + + #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +@@ -47,14 +45,6 @@ + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif /* !CONFIG_SPL_BUILD, ... */ +-/* +- * Our DDR memory always starts at 0x80000000 and U-Boot shall have +- * relocated itself to higher in memory by the time this value is used. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x80000000 + /* + * ---------------------------------------------------------------------------- + * DDR information. We say (for simplicity) that we have 1 bank, +diff -ruN u-boot-2021.10/include/configs/capricorn-common.h u-boot/include/configs/capricorn-common.h +--- u-boot-2021.10/include/configs/capricorn-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/capricorn-common.h 2021-11-01 17:10:14.579575167 +0100 +@@ -51,7 +51,6 @@ + + /* I2C Configuration */ + #ifndef CONFIG_SPL_BUILD +-#define CONFIG_SYS_I2C_SPEED 400000 + /* EEPROM */ + #define EEPROM_I2C_BUS 0 /* I2C0 */ + #define EEPROM_I2C_ADDR 0x50 +@@ -128,17 +127,12 @@ + "reset;" + + /* Default location for tftp and bootm */ +-#define CONFIG_LOADADDR 0x80280000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + /* On CCP board, USDHC1 is for eMMC */ + #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/cardhu.h u-boot/include/configs/cardhu.h +--- u-boot-2021.10/include/configs/cardhu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cardhu.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,8 +24,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTA + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU +- + /* SPI */ + #define CONFIG_TEGRA_SLINK_CTRLS 6 + #define CONFIG_SPI_FLASH_SIZE (4 << 20) +diff -ruN u-boot-2021.10/include/configs/cgtqmx8.h u-boot/include/configs/cgtqmx8.h +--- u-boot-2021.10/include/configs/cgtqmx8.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cgtqmx8.h 2021-11-01 17:10:14.579575167 +0100 +@@ -50,8 +50,6 @@ + + #define CONFIG_ENV_OVERWRITE + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + /* Boot M4 */ + #define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ +@@ -147,9 +145,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -158,18 +153,12 @@ + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + #define CONFIG_SYS_FSL_USDHC_NUM 3 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 + #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ + #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +-/* Serial */ +-#define CONFIG_BAUDRATE 115200 +- + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +diff -ruN u-boot-2021.10/include/configs/chiliboard.h u-boot/include/configs/chiliboard.h +--- u-boot-2021.10/include/configs/chiliboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/chiliboard.h 2021-11-01 17:10:14.579575167 +0100 +@@ -123,14 +123,7 @@ + #define CONFIG_SYS_BOOTCOUNT_BE + + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -141,9 +134,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 + /* NAND: SPL related configs */ + + /* USB configuration */ +diff -ruN u-boot-2021.10/include/configs/ci20.h u-boot/include/configs/ci20.h +--- u-boot-2021.10/include/configs/ci20.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ci20.h 2021-11-01 17:10:14.579575167 +0100 +@@ -9,8 +9,6 @@ + #ifndef __CONFIG_CI20_H__ + #define __CONFIG_CI20_H__ + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* Ingenic JZ4780 clock configuration. */ + #define CONFIG_SYS_HZ 1000 + #define CONFIG_SYS_MHZ 1200 +@@ -18,13 +16,10 @@ + + /* Memory configuration */ + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +diff -ruN u-boot-2021.10/include/configs/cl-som-imx7.h u-boot/include/configs/cl-som-imx7.h +--- u-boot-2021.10/include/configs/cl-som-imx7.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cl-som-imx7.h 2021-11-01 17:10:14.579575167 +0100 +@@ -12,9 +12,6 @@ + + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + /* Network */ + #define CONFIG_FEC_MXC + #define CONFIG_FEC_XCV_TYPE RGMII +@@ -25,22 +22,9 @@ + #define IMX_FEC_BASE ENET_IPS_BASE_ADDR + + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE3000 + #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#define SYS_I2C_BUS_SOM 0 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM +- + #define CONFIG_PCA953X + #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 + #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +@@ -108,7 +92,6 @@ + "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ + "echo USB boot attempt ...; run usbbootscript; " + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/cm_fx6.h u-boot/include/configs/cm_fx6.h +--- u-boot-2021.10/include/configs/cm_fx6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cm_fx6.h 2021-11-01 17:10:14.579575167 +0100 +@@ -14,7 +14,6 @@ + + /* Machine config */ + #define CONFIG_SYS_LITTLE_ENDIAN +-#define CONFIG_MACH_TYPE 4273 + + /* MMC */ + #define CONFIG_SYS_FSL_USDHC_NUM 3 +@@ -33,7 +32,6 @@ + + /* Serial console */ + #define CONFIG_MXC_UART_BASE UART4_BASE +-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + + /* Environment */ + +@@ -43,9 +41,9 @@ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "ramdisk_addr_r=0x13000000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=undefined\0" \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ +@@ -144,9 +142,7 @@ + /* NAND */ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + /* APBH DMA is required for NAND support */ + #endif + +@@ -165,19 +161,6 @@ + #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + +-/* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#define CONFIG_SYS_MXC_I2C3_SPEED 400000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_I2C_EEPROM_BUS 2 +- + /* SATA */ + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_LBA48 +@@ -186,10 +169,8 @@ + + /* Boot */ + #define CONFIG_SYS_BOOTMAPSZ (8 << 20) +-#define CONFIG_SERIAL_TAG + + /* misc */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + + /* SPL */ + #include "imx6_spl.h" +@@ -201,10 +182,5 @@ + #define CONFIG_VIDEO_BMP_LOGO + + /* EEPROM */ +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +-#define CONFIG_SYS_EEPROM_SIZE 256 + + #endif /* __CONFIG_CM_FX6_H */ +diff -ruN u-boot-2021.10/include/configs/cm_t335.h u-boot/include/configs/cm_t335.h +--- u-boot-2021.10/include/configs/cm_t335.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cm_t335.h 2021-11-01 17:10:14.579575167 +0100 +@@ -10,15 +10,11 @@ + #ifndef __CONFIG_CM_T335_H + #define __CONFIG_CM_T335_H + +-#define CONFIG_CM_T335 +- + #include <configs/ti_am335x_common.h> + + #undef CONFIG_MAX_RAM_BANK_SIZE + #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ + +-#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 +- + /* Clock Defines */ + #define V_OSCK 25000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) +@@ -83,22 +79,12 @@ + #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ + + /* I2C Configuration */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_I2C_EEPROM_BUS 0 + + /* SPL */ + + /* Network. */ + + /* NAND support */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -112,11 +98,7 @@ + + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +-#undef CONFIG_SYS_NAND_U_BOOT_OFFS +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +- + #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #ifdef CONFIG_SPL_OS_BOOT + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 + #endif +@@ -128,11 +110,6 @@ + /* Status LED polarity is inversed, so init it in the "off" state */ + + /* EEPROM */ +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +-#define CONFIG_SYS_EEPROM_SIZE 256 + + #ifndef CONFIG_SPL_BUILD + /* +@@ -145,4 +122,3 @@ + #endif /* CONFIG_SPL_BUILD */ + + #endif /* __CONFIG_CM_T335_H */ +- +diff -ruN u-boot-2021.10/include/configs/cm_t43.h u-boot/include/configs/cm_t43.h +--- u-boot-2021.10/include/configs/cm_t43.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cm_t43.h 2021-11-01 17:10:14.579575167 +0100 +@@ -8,7 +8,6 @@ + #ifndef __CONFIG_CM_T43_H + #define __CONFIG_CM_T43_H + +-#define CONFIG_CM_T43 + #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ + #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +@@ -23,17 +22,8 @@ + #endif + + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -45,13 +35,7 @@ + /* CPSW Ethernet support */ + #define CONFIG_SYS_RX_ETH_BUFFER 64 + +-/* USB support */ +-#define CONFIG_USB_XHCI_OMAP +-#define CONFIG_AM437X_USB2PHY2_HOST +- + /* Power */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_TPS65218 + + /* Enabling L2 Cache */ +@@ -62,9 +46,6 @@ + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#if !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_HSMMC2_8BIT + +@@ -114,10 +95,5 @@ + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) + + /* EEPROM */ +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +-#define CONFIG_SYS_EEPROM_SIZE 256 + + #endif /* __CONFIG_CM_T43_H */ +diff -ruN u-boot-2021.10/include/configs/cobra5272.h u-boot/include/configs/cobra5272.h +--- u-boot-2021.10/include/configs/cobra5272.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/cobra5272.h 2021-11-01 17:10:14.579575167 +0100 +@@ -135,9 +135,6 @@ + + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address +-from which user programs will be started */ +- + /*---*/ + + /* +@@ -217,7 +214,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -237,7 +233,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/colibri_imx6.h u-boot/include/configs/colibri_imx6.h +--- u-boot-2021.10/include/configs/colibri_imx6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_imx6.h 2021-11-01 17:10:14.579575167 +0100 +@@ -21,25 +21,8 @@ + #include "imx6_spl.h" + #endif + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SERIAL_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#define CONFIG_SYS_MXC_I2C3_SPEED 400000 +- + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_FSL_USDHC_NUM 2 +@@ -68,8 +51,6 @@ + #undef CONFIG_SERVERIP + #define CONFIG_SERVERIP 192.168.10.1 + +-#define CONFIG_LOADADDR 0x12000000 +- + #ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ +@@ -142,7 +123,7 @@ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "vidargs=fbmem=8M\0" + + /* Miscellaneous configurable options */ +@@ -151,8 +132,6 @@ + #undef CONFIG_SYS_MAXARGS + #define CONFIG_SYS_MAXARGS 48 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical Memory Map */ + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +diff -ruN u-boot-2021.10/include/configs/colibri-imx6ull.h u-boot/include/configs/colibri-imx6ull.h +--- u-boot-2021.10/include/configs/colibri-imx6ull.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri-imx6ull.h 2021-11-01 17:10:14.579575167 +0100 +@@ -15,9 +15,6 @@ + + #define PHYS_SDRAM_SIZE SZ_512M + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + /* ENET1 */ + #define IMX_FEC_BASE ENET2_BASE_ADDR + +@@ -25,9 +22,6 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_FSL_USDHC_NUM 1 + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 + #define CONFIG_SERVERIP 192.168.10.1 +@@ -106,11 +100,10 @@ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "vidargs=video=mxsfb:640x480M-16@60" + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Physical Memory Map */ + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +@@ -128,7 +121,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ + #define CONFIG_SYS_NAND_BASE -1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* USB Configs */ + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +diff -ruN u-boot-2021.10/include/configs/colibri_imx7.h u-boot/include/configs/colibri_imx7.h +--- u-boot-2021.10/include/configs/colibri_imx7.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_imx7.h 2021-11-01 17:10:14.579575167 +0100 +@@ -13,9 +13,6 @@ + + #include "mx7_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + /* MMC Config*/ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND +@@ -24,10 +21,6 @@ + #define CONFIG_SYS_FSL_USDHC_NUM 2 + #endif + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 + #define CONFIG_SERVERIP 192.168.10.1 +@@ -171,13 +164,12 @@ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "updlevel=2\0" + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -196,8 +188,6 @@ + /* NAND stuff */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES + #endif + +diff -ruN u-boot-2021.10/include/configs/colibri-imx8x.h u-boot/include/configs/colibri-imx8x.h +--- u-boot-2021.10/include/configs/colibri-imx8x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri-imx8x.h 2021-11-01 17:10:14.579575167 +0100 +@@ -19,8 +19,6 @@ + #define USDHC2_BASE_ADDR 0x5b020000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 + #define CONFIG_SERVERIP 192.168.10.1 +@@ -102,9 +100,6 @@ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -117,9 +112,6 @@ + + #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/colibri_pxa270.h u-boot/include/configs/colibri_pxa270.h +--- u-boot-2021.10/include/configs/colibri_pxa270.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_pxa270.h 2021-11-01 17:10:14.579575167 +0100 +@@ -19,7 +19,6 @@ + /* + * Environment settings + */ +-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + #define CONFIG_BOOTCOMMAND \ + "if fatload mmc 0 0xa0000000 uImage; then " \ + "bootm 0xa0000000; " \ +@@ -29,8 +28,6 @@ + "fi; " \ + "bootm 0xc0000;" + #define CONFIG_TIMESTAMP +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS + + /* + * Serial Console Configuration +@@ -41,11 +38,10 @@ + */ + + /* I2C support */ +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + #define CONFIG_SYS_I2C_PXA + #define CONFIG_PXA_STD_I2C + #define CONFIG_PXA_PWR_I2C +-#define CONFIG_SYS_I2C_SPEED 100000 + #endif + + /* LCD support */ +@@ -83,7 +79,6 @@ + #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ + #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 + +diff -ruN u-boot-2021.10/include/configs/colibri_t20.h u-boot/include/configs/colibri_t20.h +--- u-boot-2021.10/include/configs/colibri_t20.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_t20.h 2021-11-01 17:10:14.579575167 +0100 +@@ -15,8 +15,6 @@ + #define CONFIG_TEGRA_UARTA_SDIO1 + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 +- + /* LCD support */ + #define CONFIG_LCD_LOGO + +diff -ruN u-boot-2021.10/include/configs/colibri_t30.h u-boot/include/configs/colibri_t30.h +--- u-boot-2021.10/include/configs/colibri_t30.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_t30.h 2021-11-01 17:10:14.579575167 +0100 +@@ -24,8 +24,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTA + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 +- + /* Increase console I/O buffer size */ + #undef CONFIG_SYS_CBSIZE + #define CONFIG_SYS_CBSIZE 1024 +diff -ruN u-boot-2021.10/include/configs/colibri_vf.h u-boot/include/configs/colibri_vf.h +--- u-boot-2021.10/include/configs/colibri_vf.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/colibri_vf.h 2021-11-01 17:10:14.579575167 +0100 +@@ -16,8 +16,6 @@ + + #define CONFIG_SYS_FSL_CLK + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #ifdef CONFIG_VIDEO_FSL_DCU_FB + #define CONFIG_VIDEO_LOGO + #define CONFIG_VIDEO_BMP_LOGO +@@ -27,18 +25,13 @@ + #define DCU_LAYER_MAX_NUM 64 + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) +- + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define CONFIG_IPADDR 192.168.10.2 + #define CONFIG_NETMASK 255.255.255.0 + #define CONFIG_SERVERIP 192.168.10.1 + +-#define CONFIG_LOADADDR 0x80008000 + #define CONFIG_FDTADDR 0x84000000 + + /* We boot from the gfxRAM area of the OCRAM. */ +@@ -117,7 +110,6 @@ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical memory map */ +diff -ruN u-boot-2021.10/include/configs/comtrend_ar5315u.h u-boot/include/configs/comtrend_ar5315u.h +--- u-boot-2021.10/include/configs/comtrend_ar5315u.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/comtrend_ar5315u.h 2021-11-01 17:10:14.579575167 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6318.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/comtrend_ar5387un.h u-boot/include/configs/comtrend_ar5387un.h +--- u-boot-2021.10/include/configs/comtrend_ar5387un.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/comtrend_ar5387un.h 2021-11-01 17:10:14.579575167 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6328.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/comtrend_ct5361.h u-boot/include/configs/comtrend_ct5361.h +--- u-boot-2021.10/include/configs/comtrend_ct5361.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/comtrend_ct5361.h 2021-11-01 17:10:14.579575167 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6348.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/comtrend_vr3032u.h u-boot/include/configs/comtrend_vr3032u.h +--- u-boot-2021.10/include/configs/comtrend_vr3032u.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/comtrend_vr3032u.h 2021-11-01 17:10:14.579575167 +0100 +@@ -11,5 +11,4 @@ + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* CONFIG_MTD_RAW_NAND */ +diff -ruN u-boot-2021.10/include/configs/comtrend_wap5813n.h u-boot/include/configs/comtrend_wap5813n.h +--- u-boot-2021.10/include/configs/comtrend_wap5813n.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/comtrend_wap5813n.h 2021-11-01 17:10:14.579575167 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6368.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/controlcenterdc.h u-boot/include/configs/controlcenterdc.h +--- u-boot-2021.10/include/configs/controlcenterdc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/controlcenterdc.h 2021-11-01 17:10:14.579575167 +0100 +@@ -12,16 +12,12 @@ + */ + #define CONFIG_CUSTOMER_BOARD_SUPPORT + +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +- + /* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ + +-#define CONFIG_LOADADDR 1000000 +- + /* + * SATA/SCSI/AHCI configuration + */ +@@ -85,7 +81,7 @@ + + #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD + /* SPL related MMC defines */ +-#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_MMC + #ifdef CONFIG_SPL_BUILD + #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ + #endif +@@ -134,7 +130,7 @@ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " fi; sleep 0.12; done\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ +@@ -142,7 +138,7 @@ + "tftpboot ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +-#define CONFIG_MMCBOOTCOMMAND \ ++#define MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ +diff -ruN u-boot-2021.10/include/configs/corenet_ds.h u-boot/include/configs/corenet_ds.h +--- u-boot-2021.10/include/configs/corenet_ds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/corenet_ds.h 2021-11-01 17:10:14.579575167 +0100 +@@ -25,16 +25,6 @@ + #else + #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE + #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +-#if defined(CONFIG_TARGET_P3041DS) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg +-#elif defined(CONFIG_TARGET_P4080DS) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg +-#elif defined(CONFIG_TARGET_P5020DS) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg +-#elif defined(CONFIG_TARGET_P5040DS) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg +-#endif + #endif + #endif + +@@ -73,9 +63,7 @@ + #define CONFIG_BACKSIDE_L2_CACHE + #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E + #define CONFIG_BTB /* toggle branch predition */ +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -101,11 +89,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + + /* + * DDR Setup +@@ -117,8 +102,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +-#define CONFIG_DDR_SPD +- + #define CONFIG_SYS_SPD_BUS_NUM 1 + #define SPD_EEPROM_ADDRESS1 0x51 + #define SPD_EEPROM_ADDRESS2 0x52 +@@ -165,7 +148,7 @@ + #define PIXIS_LBMAP_ALTBANK 0x40 + + #define CONFIG_SYS_FLASH_QUIET_TEST +-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ ++#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + + #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ + #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +@@ -189,7 +172,6 @@ + + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + + /* NAND flash config */ + #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +@@ -250,7 +232,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + + /* Serial Port - controlled on board with jumper J8 + * open - index 2 +@@ -269,19 +250,6 @@ + #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_FSL + + /* + * RapidIO +@@ -413,7 +381,7 @@ + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) + #elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) ++#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024)) + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * Slave has no ucode locally, it can fetch this from remote. When implementing +@@ -488,7 +456,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -498,10 +465,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -509,9 +472,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #ifdef CONFIG_TARGET_P4080DS + #define __USB_PHY_TYPE ulpi + #else +@@ -539,14 +499,14 @@ + "fdtfile=p4080ds/p4080ds.dtb\0" \ + "bdev=sda3\0" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -555,7 +515,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -563,7 +523,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT ++#define CONFIG_BOOTCOMMAND HDBOOT + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/corvus.h u-boot/include/configs/corvus.h +--- u-boot-2021.10/include/configs/corvus.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/corvus.h 2021-11-01 17:10:14.579575167 +0100 +@@ -29,11 +29,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +- + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ +@@ -83,20 +78,12 @@ + /* DFU class support */ + #define DFU_MANIFEST_POLL_TIMEOUT 25000 + +-#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 +- + /* bootstrap + u-boot + env in nandflash */ + + #define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ + "bootm 0x70000000" + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ +- SZ_4M, 0x1000) +- + /* Defines for SPL */ + #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) + #define CONFIG_SPL_STACK (SZ_16K) +@@ -106,20 +93,12 @@ + + #define CONFIG_SPL_NAND_RAW_ONLY + #define CONFIG_SPL_NAND_SOFTECC +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +diff -ruN u-boot-2021.10/include/configs/da850evm.h u-boot/include/configs/da850evm.h +--- u-boot-2021.10/include/configs/da850evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/da850evm.h 2021-11-01 17:10:14.579575167 +0100 +@@ -22,7 +22,6 @@ + #define CONFIG_SYS_OSCIN_FREQ 24000000 + #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE + #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + + #ifdef CONFIG_MTD_NOR_FLASH + #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +@@ -31,7 +30,6 @@ + /* + * Memory Info + */ +-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ + #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ + #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ + #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +@@ -123,9 +121,6 @@ + #undef CONFIG_SYS_NAND_HW_ECC + #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ + #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 + #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +@@ -139,12 +134,8 @@ + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ + 59, 60, 61, 62, 63 } +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 10 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SPL_NAND_LOAD + + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_NAND_SELF_INIT +@@ -173,16 +164,12 @@ + #define CONFIG_BOOTFILE "uImage" /* Boot file name */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + + /* + * Linux Information + */ + #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + #define CONFIG_HWCONFIG /* enable hwconfig */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SETUP_MEMORY_TAGS + + #define CONFIG_BOOTCOMMAND \ + "run envboot; " \ +diff -ruN u-boot-2021.10/include/configs/dalmore.h u-boot/include/configs/dalmore.h +--- u-boot-2021.10/include/configs/dalmore.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dalmore.h 2021-11-01 17:10:14.582908318 +0100 +@@ -17,8 +17,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTD + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE +- + /* Environment in eMMC, at the end of 2nd "boot sector" */ + + /* SPI */ +diff -ruN u-boot-2021.10/include/configs/dart_6ul.h u-boot/include/configs/dart_6ul.h +--- u-boot-2021.10/include/configs/dart_6ul.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dart_6ul.h 2021-11-01 17:10:14.582908318 +0100 +@@ -29,9 +29,6 @@ + #endif + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + /* Environment settings */ + + /* Environment in SD */ +@@ -47,15 +44,9 @@ + #define CONFIG_SUPPORT_EMMC_BOOT + + /* I2C configs */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/db-88f6720.h u-boot/include/configs/db-88f6720.h +--- u-boot-2021.10/include/configs/db-88f6720.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/db-88f6720.h 2021-11-01 17:10:14.582908318 +0100 +@@ -17,11 +17,7 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* USB/EHCI configuration */ + #define CONFIG_EHCI_IS_TDI +diff -ruN u-boot-2021.10/include/configs/db-88f6820-amc.h u-boot/include/configs/db-88f6820-amc.h +--- u-boot-2021.10/include/configs/db-88f6820-amc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/db-88f6820-amc.h 2021-11-01 17:10:14.582908318 +0100 +@@ -23,7 +23,6 @@ + #endif + + /* NAND */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* Keep device tree and initrd in lower memory so the kernel can access them */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/db-88f6820-gp.h u-boot/include/configs/db-88f6820-gp.h +--- u-boot-2021.10/include/configs/db-88f6820-gp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/db-88f6820-gp.h 2021-11-01 17:10:14.582908318 +0100 +@@ -11,11 +11,7 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* + * SATA/SCSI/AHCI configuration +diff -ruN u-boot-2021.10/include/configs/db-mv784mp-gp.h u-boot/include/configs/db-mv784mp-gp.h +--- u-boot-2021.10/include/configs/db-mv784mp-gp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/db-mv784mp-gp.h 2021-11-01 17:10:14.582908318 +0100 +@@ -18,11 +18,7 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* USB/EHCI configuration */ + #define CONFIG_EHCI_IS_TDI +@@ -42,7 +38,6 @@ + #endif + + /* NAND */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* + * mv-common.h should be defined after CMD configs since it used them +diff -ruN u-boot-2021.10/include/configs/db-xc3-24g4xg.h u-boot/include/configs/db-xc3-24g4xg.h +--- u-boot-2021.10/include/configs/db-xc3-24g4xg.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/db-xc3-24g4xg.h 2021-11-01 17:10:14.582908318 +0100 +@@ -18,7 +18,6 @@ + /* Environment in SPI NOR flash */ + + /* NAND */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* Keep device tree and initrd in lower memory so the kernel can access them */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/devkit3250.h u-boot/include/configs/devkit3250.h +--- u-boot-2021.10/include/configs/devkit3250.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/devkit3250.h 2021-11-01 17:10:14.582908318 +0100 +@@ -12,36 +12,18 @@ + #include <linux/sizes.h> + #include <asm/arch/cpu.h> + +-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 +- +-#if !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- + /* + * Memory configurations + */ +-#define CONFIG_SYS_MALLOC_LEN SZ_1M + #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE + #define CONFIG_SYS_SDRAM_SIZE SZ_64M + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) +- + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - GENERATED_GBL_DATA_SIZE) + + /* + * DMA + */ +-#if !defined(CONFIG_SPL_BUILD) +-#define CONFIG_DMA_LPC32XX +-#endif +- +-/* +- * I2C +- */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* + * GPIO +@@ -82,9 +64,6 @@ + #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 + #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 + +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE +- + /* + * USB + */ +@@ -125,14 +104,7 @@ + * U-Boot Commands + */ + +-/* +- * Boot Linux +- */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +- + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR 0x80008000 + + /* + * SPL specific defines +@@ -155,7 +127,6 @@ + #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE + + /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 + + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +diff -ruN u-boot-2021.10/include/configs/devkit8000.h u-boot/include/configs/devkit8000.h +--- u-boot-2021.10/include/configs/devkit8000.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/devkit8000.h 2021-11-01 17:10:14.582908318 +0100 +@@ -15,7 +15,6 @@ + #define __CONFIG_H + + /* High Level Configuration Options */ +-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 + + /* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM +@@ -34,12 +33,6 @@ + + #include <configs/ti_omap3_common.h> + +-#define CONFIG_REVISION_TAG 1 +- +-/* Size of malloc() pool */ +-#undef CONFIG_SYS_MALLOC_LEN +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +- + /* Hardware drivers */ + /* DM9000 */ + #define CONFIG_NET_RETRY_COUNT 20 +@@ -140,20 +133,12 @@ + /* Defines for SPL */ + + /* NAND boot config */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 + + /* SPL OS boot options */ +diff -ruN u-boot-2021.10/include/configs/dh_imx6.h u-boot/include/configs/dh_imx6.h +--- u-boot-2021.10/include/configs/dh_imx6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dh_imx6.h 2021-11-01 17:10:14.582908318 +0100 +@@ -27,14 +27,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) +- + /* Bootcounter */ + #define CONFIG_SYS_BOOTCOUNT_BE + +@@ -81,9 +73,6 @@ + #define CONFIG_HW_WATCHDOG + #endif + +-#define CONFIG_LOADADDR 0x12000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #ifndef CONFIG_SPL_BUILD + #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ +diff -ruN u-boot-2021.10/include/configs/display5.h u-boot/include/configs/display5.h +--- u-boot-2021.10/include/configs/display5.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/display5.h 2021-11-01 17:10:14.582908318 +0100 +@@ -47,14 +47,6 @@ + + #include "imx6_spl.h" + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +- + #define CONFIG_MXC_UART_BASE UART5_BASE + + /* I2C Configs */ +diff -ruN u-boot-2021.10/include/configs/dns325.h u-boot/include/configs/dns325.h +--- u-boot-2021.10/include/configs/dns325.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dns325.h 2021-11-01 17:10:14.582908318 +0100 +@@ -13,16 +13,10 @@ + #define _CONFIG_DNS325_H + + /* +- * Machine number definition +- */ +-#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 +- +-/* + * High Level Configuration Options (easy to change) + */ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/dockstar.h u-boot/include/configs/dockstar.h +--- u-boot-2021.10/include/configs/dockstar.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dockstar.h 2021-11-01 17:10:14.582908318 +0100 +@@ -16,7 +16,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + /* + * mv-common.h should be defined after CMD configs since it used them +diff -ruN u-boot-2021.10/include/configs/dra7xx_evm.h u-boot/include/configs/dra7xx_evm.h +--- u-boot-2021.10/include/configs/dra7xx_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dra7xx_evm.h 2021-11-01 17:10:14.582908318 +0100 +@@ -31,10 +31,6 @@ + #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ + #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ + +-#define CONFIG_ENV_EEPROM_IS_ON_I2C +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + #define CONFIG_SYS_OMAP_ABE_SYSCK + + #ifndef CONFIG_SPL_BUILD +@@ -78,27 +74,13 @@ + + /* SPI SPL */ + +-/* USB xHCI HOST */ +-#define CONFIG_USB_XHCI_OMAP +- +-#define CONFIG_OMAP_USB2PHY2_HOST +- + /* SATA */ + #define CONFIG_SCSI_AHCI_PLAT + + /* NAND support */ + #ifdef CONFIG_MTD_RAW_NAND + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -108,7 +90,6 @@ + 50, 51, 52, 53, 54, 55, 56, 57, } + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 + /* NAND: SPL related configs */ + /* NAND: SPL falcon mode configs */ + #ifdef CONFIG_SPL_OS_BOOT +diff -ruN u-boot-2021.10/include/configs/draco.h u-boot/include/configs/draco.h +--- u-boot-2021.10/include/configs/draco.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/draco.h 2021-11-01 17:10:14.582908318 +0100 +@@ -12,8 +12,6 @@ + #ifndef __CONFIG_DRACO_H + #define __CONFIG_DRACO_H + +-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO +- + #include "siemens-am33x-common.h" + + #define DDR_PLL_FREQ 303 +@@ -29,13 +27,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define EEPROM_ADDR_DDR3 0x90 +-#define EEPROM_ADDR_CHIP 0x120 +- + #define CONFIG_FACTORYSET + + /* Define own nand partitions */ +diff -ruN u-boot-2021.10/include/configs/dragonboard410c.h u-boot/include/configs/dragonboard410c.h +--- u-boot-2021.10/include/configs/dragonboard410c.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dragonboard410c.h 2021-11-01 17:10:14.582908318 +0100 +@@ -20,7 +20,6 @@ + #define PHYS_SDRAM_1_SIZE SZ_1G + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + /* UART */ +@@ -82,9 +81,6 @@ + "pxefile_addr_r=0x90100000\0"\ + BOOTENV + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +- + /* Monitor Command Prompt */ + #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + #define CONFIG_SYS_MAXARGS 64 /* max command args */ +diff -ruN u-boot-2021.10/include/configs/dragonboard820c.h u-boot/include/configs/dragonboard820c.h +--- u-boot-2021.10/include/configs/dragonboard820c.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dragonboard820c.h 2021-11-01 17:10:14.582908318 +0100 +@@ -21,7 +21,6 @@ + + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + /* Generic Timer Definitions */ +@@ -50,9 +49,6 @@ + "pxefile_addr_r=0x90100000\0"\ + BOOTENV + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +- + /* Monitor Command Prompt */ + #define CONFIG_SYS_CBSIZE 512 + #define CONFIG_SYS_MAXARGS 64 +diff -ruN u-boot-2021.10/include/configs/dreamplug.h u-boot/include/configs/dreamplug.h +--- u-boot-2021.10/include/configs/dreamplug.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/dreamplug.h 2021-11-01 17:10:14.582908318 +0100 +@@ -15,7 +15,6 @@ + * High Level Configuration Options (easy to change) + */ + #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +-#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG + + #include "mv-plug-common.h" + +diff -ruN u-boot-2021.10/include/configs/ds109.h u-boot/include/configs/ds109.h +--- u-boot-2021.10/include/configs/ds109.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ds109.h 2021-11-01 17:10:14.582908318 +0100 +@@ -11,9 +11,6 @@ + #ifndef _CONFIG_DS109_H + #define _CONFIG_DS109_H + +-/* Provide the MACH_TYPE value that the vendor kernel requires. */ +-#define CONFIG_MACH_TYPE 527 +- + /* + * High Level Configuration Options (easy to change) + */ +diff -ruN u-boot-2021.10/include/configs/ds414.h u-boot/include/configs/ds414.h +--- u-boot-2021.10/include/configs/ds414.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ds414.h 2021-11-01 17:10:14.582908318 +0100 +@@ -6,9 +6,6 @@ + #ifndef _CONFIG_SYNOLOGY_DS414_H + #define _CONFIG_SYNOLOGY_DS414_H + +-/* Vendor kernel expects this MACH_TYPE */ +-#define CONFIG_MACH_TYPE 3036 +- + /* + * High Level Configuration Options (easy to change) + */ +@@ -20,11 +17,7 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* PCIe support */ + #ifndef CONFIG_SPL_BUILD +@@ -67,11 +60,7 @@ + #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) + #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +-/* DS414 bus width is 32bits */ +-#define CONFIG_DDR_32BIT +- + /* Default Environment */ +-#define CONFIG_LOADADDR 0x80000 + #define CONFIG_BOOTCOMMAND \ + "sf probe; " \ + "sf read ${loadaddr} 0xd0000 0x2d0000; " \ +diff -ruN u-boot-2021.10/include/configs/durian.h u-boot/include/configs/durian.h +--- u-boot-2021.10/include/configs/durian.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/durian.h 2021-11-01 17:10:14.582908318 +0100 +@@ -13,11 +13,6 @@ + #define PHYS_SDRAM_1_SIZE 0x7B000000 + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) +- +-/* Size of Malloc Pool */ +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +- + #define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) + + /* PCI CONFIG */ +diff -ruN u-boot-2021.10/include/configs/ea-lpc3250devkitv2.h u-boot/include/configs/ea-lpc3250devkitv2.h +--- u-boot-2021.10/include/configs/ea-lpc3250devkitv2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ea-lpc3250devkitv2.h 2021-11-01 17:10:14.582908318 +0100 +@@ -13,20 +13,16 @@ + /* + * SoC and board defines + */ +-#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */ + + /* + * RAM + */ +-#define CONFIG_SYS_MALLOC_LEN SZ_4M + #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE + + /* + * cmd + */ +-#define CONFIG_SYS_LOAD_ADDR 0x80100000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + + /* +diff -ruN u-boot-2021.10/include/configs/eb_cpu5282.h u-boot/include/configs/eb_cpu5282.h +--- u-boot-2021.10/include/configs/eb_cpu5282.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/eb_cpu5282.h 2021-11-01 17:10:14.582908318 +0100 +@@ -47,8 +47,6 @@ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR 0x20000 +- + /*#define CONFIG_SYS_DRAM_TEST 1 */ + #undef CONFIG_SYS_DRAM_TEST + +@@ -104,7 +102,6 @@ + #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -135,7 +132,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +@@ -194,15 +190,8 @@ + * I2C + */ + +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +- +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +-#define CONFIG_SYS_FSL_I2C_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0 +- + #ifdef CONFIG_CMD_DATE + #define CONFIG_RTC_DS1338 + #define CONFIG_I2C_RTC_ADDR 0x68 +diff -ruN u-boot-2021.10/include/configs/edison.h u-boot/include/configs/edison.h +--- u-boot-2021.10/include/configs/edison.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/edison.h 2021-11-01 17:10:14.582908318 +0100 +@@ -15,7 +15,6 @@ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + + /* Memory */ +-#define CONFIG_SYS_LOAD_ADDR 0x100000 + #define CONFIG_PHYSMEM + + #define CONFIG_SYS_STACK_SIZE (32 * 1024) +diff -ruN u-boot-2021.10/include/configs/edminiv2.h u-boot/include/configs/edminiv2.h +--- u-boot-2021.10/include/configs/edminiv2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/edminiv2.h 2021-11-01 17:10:14.582908318 +0100 +@@ -94,15 +94,6 @@ + + /* auto boot */ + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ +- + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + + /* +@@ -153,11 +144,7 @@ + * I2C related stuff + */ + #ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + #endif + + /* +@@ -165,15 +152,9 @@ + */ + + /* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ +- +-/* + * Other required minimal configurations + */ + +-#define CONFIG_SYS_LOAD_ADDR 0x00800000 + #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 + + /* Enable command line editing */ +diff -ruN u-boot-2021.10/include/configs/el6x_common.h u-boot/include/configs/el6x_common.h +--- u-boot-2021.10/include/configs/el6x_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/el6x_common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -14,9 +14,6 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + #ifdef CONFIG_SPL + #include "imx6_spl.h" + #endif +@@ -25,17 +22,7 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_FSL_USDHC_NUM 2 + +-/* I2C config */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +@@ -55,9 +42,9 @@ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + BOOTENV + + #define BOOT_TARGET_DEVICES(func) \ +diff -ruN u-boot-2021.10/include/configs/embestmx6boards.h u-boot/include/configs/embestmx6boards.h +--- u-boot-2021.10/include/configs/embestmx6boards.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/embestmx6boards.h 2021-11-01 17:10:14.582908318 +0100 +@@ -17,17 +17,6 @@ + + #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* USB Configs */ + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ + #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +diff -ruN u-boot-2021.10/include/configs/emsdp.h u-boot/include/configs/emsdp.h +--- u-boot-2021.10/include/configs/emsdp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/emsdp.h 2021-11-01 17:10:14.582908318 +0100 +@@ -15,14 +15,10 @@ + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) + +-#define CONFIG_SYS_MALLOC_LEN SZ_64K +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +- + /* + * Environment + */ + #define CONFIG_BOOTFILE "app.bin" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade_image=u-boot.bin\0" \ +@@ -33,4 +29,3 @@ + "emsdp rom lock\0" + + #endif /* _CONFIG_EMSDP_H_ */ +- +diff -ruN u-boot-2021.10/include/configs/etamin.h u-boot/include/configs/etamin.h +--- u-boot-2021.10/include/configs/etamin.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/etamin.h 2021-11-01 17:10:14.582908318 +0100 +@@ -14,19 +14,10 @@ + + #include "siemens-am33x-common.h" + /* NAND specific changes for etamin due to different page size */ +-#undef CONFIG_SYS_NAND_PAGE_SIZE +-#undef CONFIG_SYS_NAND_OOBSIZE +-#undef CONFIG_SYS_NAND_BLOCK_SIZE + #undef CONFIG_SYS_NAND_ECCPOS +-#undef CONFIG_SYS_NAND_U_BOOT_OFFS + #undef CONFIG_SYS_ENV_SECT_SIZE +-#undef CONFIG_NAND_OMAP_ECCSCHEME +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW + + #define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +-#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +-#define CONFIG_SYS_NAND_OOBSIZE 224 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE) + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ +@@ -55,17 +46,12 @@ + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 26 + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +- +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 +- + #undef CONFIG_SYS_MAX_NAND_DEVICE + #define CONFIG_SYS_MAX_NAND_DEVICE 3 + #define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE2} + +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define DDR_PLL_FREQ 303 + + /* FWD Button = 27 +@@ -86,10 +72,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + #define EEPROM_ADDR_DDR3 0x90 + #define EEPROM_ADDR_CHIP 0x120 + +@@ -110,7 +92,6 @@ + #define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) + + +- + #undef COMMON_ENV_DFU_ARGS + #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs};" \ +diff -ruN u-boot-2021.10/include/configs/ethernut5.h u-boot/include/configs/ethernut5.h +--- u-boot-2021.10/include/configs/ethernut5.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ethernut5.h 2021-11-01 17:10:14.582908318 +0100 +@@ -14,10 +14,6 @@ + /* The first stage boot loader expects u-boot running at this address. */ + + /* The first stage boot loader takes care of low level initialization. */ +-#define CONFIG_SKIP_LOWLEVEL_INIT +- +-/* Set our official architecture number. */ +-#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 + + /* CPU information */ + +@@ -34,9 +30,6 @@ + /* 128MB SDRAM in 1 bank */ + #define CONFIG_SYS_SDRAM_BASE 0x20000000 + #define CONFIG_SYS_SDRAM_SIZE (128 << 20) +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + + /* 512kB on-chip NOR flash */ + # define CONFIG_SYS_MAX_FLASH_BANKS 1 +@@ -97,11 +90,6 @@ + /* I2C */ + #define CONFIG_SYS_MAX_I2C_BUS 1 + +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +-#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +-#define CONFIG_SYS_I2C_SOFT_SLAVE 0 +- + #define I2C_SOFT_DECLARATIONS + + #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 +@@ -131,9 +119,6 @@ + /* File systems */ + + /* Boot command */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG + #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ + "sf read 0x22000000 0xc6000 0x294000; " \ + "bootm 0x22000000" +diff -ruN u-boot-2021.10/include/configs/evb_ast2500.h u-boot/include/configs/evb_ast2500.h +--- u-boot-2021.10/include/configs/evb_ast2500.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/evb_ast2500.h 2021-11-01 17:10:14.582908318 +0100 +@@ -13,7 +13,4 @@ + + #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +-/* Memory Info */ +-#define CONFIG_SYS_LOAD_ADDR 0x83000000 +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/evb_ast2600.h u-boot/include/configs/evb_ast2600.h +--- u-boot-2021.10/include/configs/evb_ast2600.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/evb_ast2600.h 2021-11-01 17:10:14.582908318 +0100 +@@ -10,7 +10,4 @@ + + #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +-/* Memory Info */ +-#define CONFIG_SYS_LOAD_ADDR 0x83000000 +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/exynos4-common.h u-boot/include/configs/exynos4-common.h +--- u-boot-2021.10/include/configs/exynos4-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos4-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -14,8 +14,6 @@ + + #define CONFIG_BOARD_COMMON + +-#define CONFIG_REVISION_TAG +- + /* SD/MMC configuration */ + #define CONFIG_MMC_DEFAULT_DEV 0 + +@@ -32,7 +30,7 @@ + #define CONFIG_USB_GADGET_DWC2_OTG_PHY + + /* Common environment variables */ +-#define CONFIG_EXTRA_ENV_ITB \ ++#define ENV_ITB \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ +diff -ruN u-boot-2021.10/include/configs/exynos5250-common.h u-boot/include/configs/exynos5250-common.h +--- u-boot-2021.10/include/configs/exynos5250-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos5250-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -13,8 +13,6 @@ + + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + +-#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 +- + #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + + #define CONFIG_IRAM_STACK 0x02050000 +diff -ruN u-boot-2021.10/include/configs/exynos5420-common.h u-boot/include/configs/exynos5420-common.h +--- u-boot-2021.10/include/configs/exynos5420-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos5420-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -12,9 +12,6 @@ + + #define CONFIG_EXYNOS5_DT + +-/* Provide the MACH_TYPE value that the vendor kernel requires. */ +-#define CONFIG_MACH_TYPE 8002 +- + #define CONFIG_VAR_SIZE_SPL + + #define CONFIG_IRAM_TOP 0x02074000 +diff -ruN u-boot-2021.10/include/configs/exynos5-common.h u-boot/include/configs/exynos5-common.h +--- u-boot-2021.10/include/configs/exynos5-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos5-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -45,12 +45,6 @@ + /* MMC SPL */ + #define COPY_BL2_FNPTR_ADDR 0x02020030 + +-/* specific .lds file */ +- +-/* Boot Argument Buffer Size */ +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +- + #define CONFIG_RD_LVL + + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +@@ -96,11 +90,6 @@ + #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 + #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +-/* I2C */ +-#define CONFIG_SYS_I2C_S3C24X0 +-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 +- + /* SPI */ + + /* Ethernet Controllor Driver */ +diff -ruN u-boot-2021.10/include/configs/exynos7420-common.h u-boot/include/configs/exynos7420-common.h +--- u-boot-2021.10/include/configs/exynos7420-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos7420-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -16,9 +16,6 @@ + #include <asm/arch/cpu.h> /* get chip and board defs */ + #include <linux/sizes.h> + +-/* Size of malloc() pool before and after relocation */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) +- + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ +@@ -42,8 +39,6 @@ + + /* select serial console configuration */ + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +- + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE + #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +diff -ruN u-boot-2021.10/include/configs/exynos-common.h u-boot/include/configs/exynos-common.h +--- u-boot-2021.10/include/configs/exynos-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/exynos-common.h 2021-11-01 17:10:14.582908318 +0100 +@@ -16,21 +16,12 @@ + #include <linux/sizes.h> + #include <linux/stringify.h> + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* Keep L2 Cache Disabled */ + + /* input clock of PLL: 24MHz input clock */ + #define CONFIG_SYS_CLK_FREQ 24000000 + #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ + +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +- +-/* Size of malloc() pool before and after relocation */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) +- + /* select serial console configuration */ + + /* PWM */ +diff -ruN u-boot-2021.10/include/configs/falcon.h u-boot/include/configs/falcon.h +--- u-boot-2021.10/include/configs/falcon.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/falcon.h 2021-11-01 17:10:14.582908318 +0100 +@@ -11,14 +11,13 @@ + + #include "rcar-gen3-common.h" + +-/* Generic Interrupt Controller Definitions */ +-#ifdef CONFIG_GICV2 +-#undef CONFIG_GICV2 ++/* ++ * Generic Interrupt Controller Definitions. Undefine v2 locations and define ++ * v3 locations. ++ */ + #undef GICD_BASE + #undef GICC_BASE + #undef GICR_BASE +-#endif +-#define CONFIG_GICV3 + #define GICD_BASE 0xF1000000 + #define GICR_BASE 0xF1060000 + +diff -ruN u-boot-2021.10/include/configs/flea3.h u-boot/include/configs/flea3.h +--- u-boot-2021.10/include/configs/flea3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/flea3.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,178 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de> +- * +- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. +- * +- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +- * +- * Configuration for the flea3 board. +- */ +- +-#ifndef __CONFIG_H +-#define __CONFIG_H +- +-#include <asm/arch/imx-regs.h> +- +- /* High Level Configuration Options */ +-#define CONFIG_MX35 +- +-#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 +- +-/* Set TEXT at the beginning of the NOR flash */ +- +-/* This is required to setup the ESDC controller */ +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_REVISION_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +- +-/* +- * Hardware drivers +- */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ +-#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe +- +-/* +- * UART (console) +- */ +-#define CONFIG_MXC_UART_BASE UART3_BASE +- +-/* +- * Command definition +- */ +- +-#define CONFIG_NET_RETRY_COUNT 100 +- +- +-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ +- +-/* +- * Ethernet on SOC (FEC) +- */ +-#define CONFIG_FEC_MXC +-#define IMX_FEC_BASE FEC_BASE_ADDR +-#define CONFIG_FEC_MXC_PHYADDR 0x1 +- +-#define CONFIG_ARP_TIMEOUT 200UL +- +-/* +- * Miscellaneous configurable options +- */ +- +-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +-/* Print Buffer Size */ +-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- +-/* +- * Physical Memory Map +- */ +-#define PHYS_SDRAM_1 CSD0_BASE_ADDR +-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +- +-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR +-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) +-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) +-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ +- GENERATED_GBL_DATA_SIZE) +-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +- CONFIG_SYS_GBL_DATA_OFFSET) +- +-/* +- * MTD Command for mtdparts +- */ +- +-/* +- * FLASH and environment organization +- */ +-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +-/* Monitor at beginning of flash */ +-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +- +-/* Address and size of Redundant Environment Sector */ +- +-/* +- * CFI FLASH driver setup +- */ +- +-/* A non-standard buffered write algorithm */ +- +-/* +- * NAND FLASH driver setup +- */ +-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) +-#define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) +-#define CONFIG_MXC_NAND_HWECC +-#define CONFIG_SYS_NAND_LARGEPAGE +- +-/* +- * Default environment and default scripts +- * to update uboot and load kernel +- */ +- +-#define CONFIG_HOSTNAME "flea3" +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "netdev=eth0\0" \ +- "nfsargs=setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=${serverip}:${rootpath}\0" \ +- "ramargs=setenv bootargs root=/dev/ram rw\0" \ +- "addip_sta=setenv bootargs ${bootargs} " \ +- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ +- ":${hostname}:${netdev}:off panic=1\0" \ +- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ +- "addip=if test -n ${ipdyn};then run addip_dyn;" \ +- "else run addip_sta;fi\0" \ +- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ +- "addtty=setenv bootargs ${bootargs}" \ +- " console=ttymxc2,${baudrate}\0" \ +- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ +- "loadaddr=80800000\0" \ +- "kernel_addr_r=80800000\0" \ +- "hostname=" CONFIG_HOSTNAME "\0" \ +- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ +- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ +- "flash_self=run ramargs addip addtty addmtd addmisc;" \ +- "bootm ${kernel_addr} ${ramdisk_addr}\0" \ +- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ +- "bootm ${kernel_addr}\0" \ +- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ +- "run nfsargs addip addtty addmtd addmisc;" \ +- "bootm ${kernel_addr_r}\0" \ +- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ +- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ +- "net_self=if run net_self_load;then " \ +- "run ramargs addip addtty addmtd addmisc;" \ +- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ +- "else echo Images not loades;fi\0" \ +- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ +- "load=tftp ${loadaddr} ${u-boot}\0" \ +- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ +- "update=protect off ${uboot_addr} +80000;" \ +- "erase ${uboot_addr} +80000;" \ +- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ +- "upd=if run load;then echo Updating u-boot;if run update;" \ +- "then echo U-Boot updated;" \ +- "else echo Error updating u-boot !;" \ +- "echo Board without bootloader !!;" \ +- "fi;" \ +- "else echo U-Boot not downloaded..exiting;fi\0" \ +- "bootcmd=run net_nfs\0" +- +-#endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/gardena-smart-gateway-at91sam.h u-boot/include/configs/gardena-smart-gateway-at91sam.h +--- u-boot-2021.10/include/configs/gardena-smart-gateway-at91sam.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/gardena-smart-gateway-at91sam.h 2021-11-01 17:10:14.582908318 +0100 +@@ -17,11 +17,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +- + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +@@ -32,8 +27,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +- + /* NAND flash */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +@@ -45,8 +38,6 @@ + #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 + #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SPL */ + #define CONFIG_SPL_MAX_SIZE 0x7000 + #define CONFIG_SPL_STACK 0x308000 +@@ -64,18 +55,10 @@ + #define CONFIG_SYS_MCKR_CSS 0x1302 + + #define CONFIG_SPL_NAND_RAW_ONLY +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +- + #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS + #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +diff -ruN u-boot-2021.10/include/configs/gardena-smart-gateway-mt7688.h u-boot/include/configs/gardena-smart-gateway-mt7688.h +--- u-boot-2021.10/include/configs/gardena-smart-gateway-mt7688.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/gardena-smart-gateway-mt7688.h 2021-11-01 17:10:14.582908318 +0100 +@@ -12,14 +12,9 @@ + /* RAM */ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +- + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + + /* SPL */ +-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SPL_BSS_START_ADDR 0x80010000 +@@ -31,7 +26,7 @@ + #define CONFIG_SYS_UBOOT_BASE 0 + + /* Serial SPL */ +-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) ++#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) + #define CONFIG_SYS_NS16550_MEM32 + #define CONFIG_SYS_NS16550_CLK 40000000 + #define CONFIG_SYS_NS16550_REG_SIZE -4 +@@ -46,7 +41,6 @@ + + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 64 +-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + #define CONFIG_SYS_CBSIZE 512 + +diff -ruN u-boot-2021.10/include/configs/gazerbeam.h u-boot/include/configs/gazerbeam.h +--- u-boot-2021.10/include/configs/gazerbeam.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/gazerbeam.h 2021-11-01 17:10:14.582908318 +0100 +@@ -27,7 +27,6 @@ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + + /* + * Initial RAM Base Address Setup +@@ -60,7 +59,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +@@ -84,8 +82,6 @@ + #define CONFIG_HAS_ETH0 + #define CONFIG_HAS_ETH1 + +-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ +- + /* TODO: Turn into string option and migrate to Kconfig */ + #define CONFIG_HOSTNAME "gazerbeam" + #define CONFIG_ROOTPATH "/opt/nfsroot" +@@ -105,7 +101,7 @@ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -114,13 +110,13 @@ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +-#define CONFIG_MMCBOOTCOMMAND \ ++#define MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/ge_b1x5v2.h u-boot/include/configs/ge_b1x5v2.h +--- u-boot-2021.10/include/configs/ge_b1x5v2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ge_b1x5v2.h 2021-11-01 17:10:14.586241469 +0100 +@@ -15,9 +15,6 @@ + #include "imx6_spl.h" + #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* PWM */ + #define CONFIG_IMX6_PWM_PER_CLK 66000000 + +diff -ruN u-boot-2021.10/include/configs/ge_bx50v3.h u-boot/include/configs/ge_bx50v3.h +--- u-boot-2021.10/include/configs/ge_bx50v3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ge_bx50v3.h 2021-11-01 17:10:14.586241469 +0100 +@@ -19,12 +19,6 @@ + #include "mx6_common.h" + #include <linux/sizes.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* SATA Configs */ + #ifdef CONFIG_CMD_SATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 +@@ -33,10 +27,6 @@ + #define CONFIG_LBA48 + #endif + +-/* Serial Flash */ +- +-#define CONFIG_LOADADDR 0x12000000 +- + #ifdef CONFIG_CMD_NFS + #define NETWORKBOOT \ + "setnetworkboot=" \ +@@ -53,7 +43,7 @@ + "nfs ${loadaddr} /srv/nfs/fitImage; " \ + "bootm ${loadaddr}\0" \ + +-#define CONFIG_NETWORKBOOTCOMMAND \ ++#define NETWORKBOOTCOMMAND \ + "run networkboot; " \ + + #else +@@ -108,21 +98,16 @@ + "run doboot; " \ + "run failbootcmd\0" \ + +-#define CONFIG_MMCBOOTCOMMAND \ ++#define MMCBOOTCOMMAND \ + "run doquiet; " \ + "run tryboot; " \ + + #ifdef CONFIG_CMD_NFS +-#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND NETWORKBOOTCOMMAND + #else +-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND + #endif + +- +-/* Miscellaneous configurable options */ +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical Memory Map */ + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +diff -ruN u-boot-2021.10/include/configs/goflexhome.h u-boot/include/configs/goflexhome.h +--- u-boot-2021.10/include/configs/goflexhome.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/goflexhome.h 2021-11-01 17:10:14.586241469 +0100 +@@ -19,7 +19,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + /* + * Default GPIO configuration and LED status +diff -ruN u-boot-2021.10/include/configs/grpeach.h u-boot/include/configs/grpeach.h +--- u-boot-2021.10/include/configs/grpeach.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/grpeach.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,18 +13,13 @@ + + /* Miscellaneous */ + #define CONFIG_SYS_PBSIZE 256 +-#define CONFIG_CMDLINE_TAG + + /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ + #define CONFIG_SYS_SDRAM_BASE 0x20000000 + #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) +-#define CONFIG_SYS_LOAD_ADDR \ +- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) + +-/* Malloc */ +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) + + /* Network interface */ +diff -ruN u-boot-2021.10/include/configs/gw_ventana.h u-boot/include/configs/gw_ventana.h +--- u-boot-2021.10/include/configs/gw_ventana.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/gw_ventana.h 2021-11-01 17:10:14.586241469 +0100 +@@ -8,7 +8,6 @@ + + /* SPL */ + /* Location in NAND to read U-Boot from */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) + + /* Falcon Mode */ + #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 +@@ -24,14 +23,6 @@ + #include "imx6_spl.h" /* common IMX6 SPL configuration */ + #include "mx6_common.h" + +-#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ +- +-/* Serial ATAG */ +-#define CONFIG_SERIAL_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* Serial */ + #define CONFIG_MXC_UART_BASE UART2_BASE + +@@ -42,12 +33,6 @@ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) + + /* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_I2C_GSC 0 + #define CONFIG_I2C_EDID + +@@ -74,8 +59,6 @@ + /* + * PMIC + */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #define CONFIG_POWER_LTC3676 +diff -ruN u-boot-2021.10/include/configs/harmony.h u-boot/include/configs/harmony.h +--- u-boot-2021.10/include/configs/harmony.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/harmony.h 2021-11-01 17:10:14.586241469 +0100 +@@ -23,8 +23,6 @@ + #define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE + #endif + +-#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY +- + /* NAND support */ + #define CONFIG_TEGRA_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +diff -ruN u-boot-2021.10/include/configs/highbank.h u-boot/include/configs/highbank.h +--- u-boot-2021.10/include/configs/highbank.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/highbank.h 2021-11-01 17:10:14.586241469 +0100 +@@ -12,11 +12,6 @@ + #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) + #define CONFIG_SYS_TIMER_COUNTS_DOWN + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +- + #define CONFIG_PL011_CLOCK 150000000 + + #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ +@@ -36,7 +31,6 @@ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR 0x800000 + #define CONFIG_SYS_64BIT_LBA + + /* Environment data setup +@@ -46,7 +40,6 @@ + + #define CONFIG_SYS_SDRAM_BASE 0x00000000 + #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x20000000\0" \ +diff -ruN u-boot-2021.10/include/configs/hikey960.h u-boot/include/configs/hikey960.h +--- u-boot-2021.10/include/configs/hikey960.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/hikey960.h 2021-11-01 17:10:14.586241469 +0100 +@@ -24,8 +24,6 @@ + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) +- + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 19000000 + +@@ -33,9 +31,6 @@ + #define GICD_BASE 0xe82b1000 + #define GICC_BASE 0xe82b2000 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + #include <config_distro_bootcmd.h> +diff -ruN u-boot-2021.10/include/configs/hikey.h u-boot/include/configs/hikey.h +--- u-boot-2021.10/include/configs/hikey.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/hikey.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,7 +13,6 @@ + + #include <linux/sizes.h> + +-#define CONFIG_POWER + #define CONFIG_POWER_HI6553 + + #define CONFIG_REMAKE_ELF +@@ -35,8 +34,6 @@ + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) +- + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 19000000 + +@@ -44,13 +41,6 @@ + #define GICD_BASE 0xf6801000 + #define GICC_BASE 0xf6802000 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +- +-#ifdef CONFIG_USB_DWC2 +-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +-#endif +- + #define CONFIG_HIKEY_GPIO + + /* BOOTP options */ +diff -ruN u-boot-2021.10/include/configs/hsdk-4xd.h u-boot/include/configs/hsdk-4xd.h +--- u-boot-2021.10/include/configs/hsdk-4xd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/hsdk-4xd.h 2021-11-01 17:10:14.586241469 +0100 +@@ -29,9 +29,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + #define CONFIG_SYS_BOOTM_LEN SZ_128M +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + + /* + * UART configuration +@@ -107,7 +105,6 @@ + * Environment configuration + */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + /* Cli configuration */ + #define CONFIG_SYS_CBSIZE SZ_2K +diff -ruN u-boot-2021.10/include/configs/hsdk.h u-boot/include/configs/hsdk.h +--- u-boot-2021.10/include/configs/hsdk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/hsdk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -28,9 +28,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + #define CONFIG_SYS_BOOTM_LEN SZ_128M +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + + /* + * UART configuration +@@ -106,7 +104,6 @@ + * Environment configuration + */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + /* Cli configuration */ + #define CONFIG_SYS_CBSIZE SZ_2K +diff -ruN u-boot-2021.10/include/configs/huawei_hg556a.h u-boot/include/configs/huawei_hg556a.h +--- u-boot-2021.10/include/configs/huawei_hg556a.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/huawei_hg556a.h 2021-11-01 17:10:14.586241469 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6358.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/ib62x0.h u-boot/include/configs/ib62x0.h +--- u-boot-2021.10/include/configs/ib62x0.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ib62x0.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,7 +13,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/iconnect.h u-boot/include/configs/iconnect.h +--- u-boot-2021.10/include/configs/iconnect.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/iconnect.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,12 +13,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +- +-/* +- * Machine type +- */ +-#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/ids8313.h u-boot/include/configs/ids8313.h +--- u-boot-2021.10/include/configs/ids8313.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ids8313.h 2021-11-01 17:10:14.586241469 +0100 +@@ -129,10 +129,6 @@ + */ + #define CONFIG_SYS_NAND_BASE 0xE1000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 +-#define CONFIG_NAND_FSL_ELBC +-#define CONFIG_SYS_NAND_PAGE_SIZE (2048) +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) + #define NAND_CACHE_PAGES 64 + + +@@ -163,11 +159,6 @@ + /* + * I2C setup + */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 + #define CONFIG_SYS_I2C_RTC_ADDR 0x51 + + /* +@@ -217,7 +208,6 @@ + */ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) + + /* + * Environment Configuration +@@ -229,7 +219,6 @@ + #define CONFIG_BOOTFILE "ids8313/uImage" + #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" + #define CONFIG_FDTFILE "ids8313/ids8313.dtb" +-#define CONFIG_LOADADDR 0x400000 + #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" + + /* Initial Memory map for Linux*/ +@@ -241,7 +230,6 @@ + #define CONFIG_SYS_CBSIZE 1024 + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR 0x100000 + #define CONFIG_LOADS_ECHO + #define CONFIG_TIMESTAMP + #define CONFIG_BOOTCOMMAND "run boot_cramfs" +@@ -284,7 +272,7 @@ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setipargs;run addmtd;" \ + "tftp ${loadaddr} ${bootfile};" \ +diff -ruN u-boot-2021.10/include/configs/imgtec_xilfpga.h u-boot/include/configs/imgtec_xilfpga.h +--- u-boot-2021.10/include/configs/imgtec_xilfpga.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imgtec_xilfpga.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,7 +11,6 @@ + #define __XILFPGA_CONFIG_H + + /* BootROM + MIG is pretty smart. DDR and Cache initialized */ +-#define CONFIG_SKIP_LOWLEVEL_INIT + + /*-------------------------------------------- + * CPU configuration +@@ -29,9 +28,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) + +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ + + /*---------------------------------------------------------------------- + * Commands +diff -ruN u-boot-2021.10/include/configs/imx27lite-common.h u-boot/include/configs/imx27lite-common.h +--- u-boot-2021.10/include/configs/imx27lite-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx27lite-common.h 2021-11-01 17:10:14.586241469 +0100 +@@ -15,10 +15,6 @@ + #define CONFIG_MX27 + #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ + +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 +-#define CONFIG_INITRD_TAG 1 +- + /* + * Lowlevel configuration + */ +@@ -67,8 +63,6 @@ + /* + * Memory Info + */ +-/* malloc() len */ +-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) + /* memtest start address */ + #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ + #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +@@ -120,9 +114,6 @@ + /* Boot Argument Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ +diff -ruN u-boot-2021.10/include/configs/imx6dl-mamoj.h u-boot/include/configs/imx6dl-mamoj.h +--- u-boot-2021.10/include/configs/imx6dl-mamoj.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx6dl-mamoj.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,9 +13,6 @@ + #include <linux/sizes.h> + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) +- + /* Total Size of Environment Sector */ + + /* Environment */ +@@ -65,7 +62,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/imx6-engicam.h u-boot/include/configs/imx6-engicam.h +--- u-boot-2021.10/include/configs/imx6-engicam.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx6-engicam.h 2021-11-01 17:10:14.586241469 +0100 +@@ -13,9 +13,6 @@ + #include <linux/stringify.h> + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + /* Total Size of Environment Sector */ + + /* Environment */ +@@ -30,7 +27,7 @@ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=uImage\0" \ + "fit_image=fit.itb\0" \ + "fdt_high=0xffffffff\0" \ +@@ -103,13 +100,12 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + #ifdef CONFIG_MX6UL + # define DRAM_OFFSET(x) 0x87##x + # define FDT_ADDR __stringify(DRAM_OFFSET(800000)) +-#else ++#else + # define DRAM_OFFSET(x) 0x1##x + # define FDT_ADDR __stringify(DRAM_OFFSET(8000000)) + #endif +@@ -141,10 +137,7 @@ + #ifdef CONFIG_NAND_MXS + # define CONFIG_SYS_MAX_NAND_DEVICE 1 + # define CONFIG_SYS_NAND_BASE 0x40000000 +-# define CONFIG_SYS_NAND_5_ADDR_CYCLE +-# define CONFIG_SYS_NAND_ONFI_DETECTION + # define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +-# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + + /* MTD device */ + #endif +@@ -174,7 +167,7 @@ + # ifdef CONFIG_ENV_IS_IN_NAND + # define CONFIG_SPL_NAND_SUPPORT + # else +-# define CONFIG_SPL_MMC_SUPPORT ++# define CONFIG_SPL_MMC + # endif + + # include "imx6_spl.h" +diff -ruN u-boot-2021.10/include/configs/imx6_logic.h u-boot/include/configs/imx6_logic.h +--- u-boot-2021.10/include/configs/imx6_logic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx6_logic.h 2021-11-01 17:10:14.586241469 +0100 +@@ -17,9 +17,6 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_FSL_USDHC_NUM 2 +@@ -36,7 +33,7 @@ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x14000000\0" \ + "ramdisk_addr_r=0x14080000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_file=rootfs.cpio.uboot\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ +@@ -132,10 +129,7 @@ + /* NAND stuff */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 + + /* MTD device */ +diff -ruN u-boot-2021.10/include/configs/imx6_spl.h u-boot/include/configs/imx6_spl.h +--- u-boot-2021.10/include/configs/imx6_spl.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx6_spl.h 2021-11-01 17:10:14.586241469 +0100 +@@ -54,12 +54,12 @@ + #endif + + /* MMC support */ +-#if defined(CONFIG_SPL_MMC_SUPPORT) ++#if defined(CONFIG_SPL_MMC) + #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ + #endif + + /* SATA support */ +-#if defined(CONFIG_SPL_SATA_SUPPORT) ++#if defined(CONFIG_SPL_SATA) + #define CONFIG_SPL_SATA_BOOT_DEVICE 0 + #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 + #endif +diff -ruN u-boot-2021.10/include/configs/imx7-cm.h u-boot/include/configs/imx7-cm.h +--- u-boot-2021.10/include/configs/imx7-cm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx7-cm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -12,9 +12,6 @@ + + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + #define CONFIG_ETHPRIME "FEC" + + #undef CONFIG_SYS_AUTOLOAD +@@ -23,9 +20,9 @@ + + /* + * Use: +- * boot-mode=mix +- * boot-mode=sd +- * boot-mode=net ++ * boot-mode=mix ++ * boot-mode=sd ++ * boot-mode=net + */ + #define MY_CONFIG_BOOT_MODE "boot-mode=sd\0" + +@@ -75,7 +72,6 @@ + + #define CONFIG_BOOTCOMMAND "run boot${boot-mode}" + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/imx7_spl.h u-boot/include/configs/imx7_spl.h +--- u-boot-2021.10/include/configs/imx7_spl.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx7_spl.h 2021-11-01 17:10:14.586241469 +0100 +@@ -31,7 +31,7 @@ + #define CONFIG_SPL_PAD_TO 0x11000 + + /* MMC support */ +-#if defined(CONFIG_SPL_MMC_SUPPORT) ++#if defined(CONFIG_SPL_MMC) + #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ + #endif + +diff -ruN u-boot-2021.10/include/configs/imx8mm_beacon.h u-boot/include/configs/imx8mm_beacon.h +--- u-boot-2021.10/include/configs/imx8mm_beacon.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mm_beacon.h 2021-11-01 17:10:14.586241469 +0100 +@@ -93,9 +93,6 @@ + "fi;" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +@@ -104,9 +101,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +@@ -128,9 +122,6 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* I2C */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* FEC*/ + #define CONFIG_ETHPRIME "FEC" + #define CONFIG_FEC_XCV_TYPE RGMII +diff -ruN u-boot-2021.10/include/configs/imx8mm-cl-iot-gate.h u-boot/include/configs/imx8mm-cl-iot-gate.h +--- u-boot-2021.10/include/configs/imx8mm-cl-iot-gate.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mm-cl-iot-gate.h 2021-11-01 17:10:14.586241469 +0100 +@@ -140,9 +140,6 @@ + #endif + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -153,9 +150,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +@@ -178,8 +172,6 @@ + + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_ETHPRIME "FEC" + + #define CONFIG_FEC_XCV_TYPE RGMII +diff -ruN u-boot-2021.10/include/configs/imx8mm_evk.h u-boot/include/configs/imx8mm_evk.h +--- u-boot-2021.10/include/configs/imx8mm_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mm_evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -44,8 +44,8 @@ + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ +@@ -57,9 +57,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +@@ -70,9 +67,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +@@ -94,8 +88,6 @@ + + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_ETHPRIME "FEC" + + #define CONFIG_FEC_XCV_TYPE RGMII +diff -ruN u-boot-2021.10/include/configs/imx8mm_icore_mx8mm.h u-boot/include/configs/imx8mm_icore_mx8mm.h +--- u-boot-2021.10/include/configs/imx8mm_icore_mx8mm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mm_icore_mx8mm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -56,8 +56,6 @@ + BOOTENV + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +@@ -66,8 +64,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + /* SDRAM configuration */ +@@ -94,7 +90,4 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* I2C */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #endif /* __IMX8MM_ICORE_MX8MM_H */ +diff -ruN u-boot-2021.10/include/configs/imx8mm_venice.h u-boot/include/configs/imx8mm_venice.h +--- u-boot-2021.10/include/configs/imx8mm_venice.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mm_venice.h 2021-11-01 17:10:14.586241469 +0100 +@@ -37,8 +37,6 @@ + "scriptaddr=0x46000000\0" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Enable Distro Boot */ + #ifndef CONFIG_SPL_BUILD +@@ -87,8 +85,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + /* SDRAM configuration */ +@@ -112,9 +108,6 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* I2C */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* FEC */ + #define CONFIG_ETHPRIME "eth0" + #define CONFIG_FEC_XCV_TYPE RGMII +diff -ruN u-boot-2021.10/include/configs/imx8mn_beacon.h u-boot/include/configs/imx8mn_beacon.h +--- u-boot-2021.10/include/configs/imx8mn_beacon.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mn_beacon.h 2021-11-01 17:10:14.586241469 +0100 +@@ -108,9 +108,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +@@ -121,9 +118,6 @@ + + #define CONFIG_ENV_OVERWRITE + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) +diff -ruN u-boot-2021.10/include/configs/imx8mn_evk.h u-boot/include/configs/imx8mn_evk.h +--- u-boot-2021.10/include/configs/imx8mn_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mn_evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -44,8 +44,8 @@ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fit=no\0" \ +@@ -56,9 +56,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +@@ -69,9 +66,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +@@ -93,6 +87,4 @@ + + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #endif +diff -ruN u-boot-2021.10/include/configs/imx8mp_evk.h u-boot/include/configs/imx8mp_evk.h +--- u-boot-2021.10/include/configs/imx8mp_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mp_evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -30,15 +30,9 @@ + #define CONFIG_SPL_ABORT_ON_RAW_IMAGE + + #undef CONFIG_DM_MMC +-#undef CONFIG_DM_PMIC +-#undef CONFIG_DM_PMIC_PFUZE100 + +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PCA9450 + +-#define CONFIG_SYS_I2C_LEGACY +- + #endif + + #if defined(CONFIG_CMD_NET) +@@ -68,8 +62,8 @@ + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ +@@ -81,9 +75,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -94,9 +85,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M +- + /* Totally 6GB DDR */ + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 +@@ -120,6 +108,4 @@ + + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #endif +diff -ruN u-boot-2021.10/include/configs/imx8mq_cm.h u-boot/include/configs/imx8mq_cm.h +--- u-boot-2021.10/include/configs/imx8mq_cm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mq_cm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -65,9 +65,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -78,9 +75,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ +diff -ruN u-boot-2021.10/include/configs/imx8mq_evk.h u-boot/include/configs/imx8mq_evk.h +--- u-boot-2021.10/include/configs/imx8mq_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mq_evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -28,7 +28,7 @@ + #define CONFIG_SPL_LIBCOMMON_SUPPORT + #define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_SPL_GPIO +-#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_MMC + #define CONFIG_SPL_BSS_START_ADDR 0x00180000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ + #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +@@ -41,18 +41,7 @@ + #define CONFIG_SPL_ABORT_ON_RAW_IMAGE + + #undef CONFIG_DM_MMC +-#undef CONFIG_DM_PMIC +-#undef CONFIG_DM_PMIC_PFUZE100 + +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +- +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #endif +@@ -99,9 +88,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -112,9 +98,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ +@@ -139,13 +122,6 @@ + + #define CONFIG_MXC_GPIO + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_OF_SYSTEM_SETUP + +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_DM_PMIC +-#endif +- + #endif +diff -ruN u-boot-2021.10/include/configs/imx8mq_phanbell.h u-boot/include/configs/imx8mq_phanbell.h +--- u-boot-2021.10/include/configs/imx8mq_phanbell.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8mq_phanbell.h 2021-11-01 17:10:14.586241469 +0100 +@@ -25,7 +25,7 @@ + #define CONFIG_SPL_LIBCOMMON_SUPPORT + #define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_SPL_GPIO +-#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_MMC + #define CONFIG_SPL_BSS_START_ADDR 0x00180000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ + #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +@@ -38,18 +38,6 @@ + #define CONFIG_SPL_ABORT_ON_RAW_IMAGE + + #undef CONFIG_DM_MMC +-#undef CONFIG_DM_PMIC +-#undef CONFIG_DM_PMIC_PFUZE100 +- +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +- +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #endif + + #define CONFIG_REMAKE_ELF +@@ -142,9 +130,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -155,9 +140,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +@@ -184,13 +166,6 @@ + + #define CONFIG_MXC_GPIO + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_OF_SYSTEM_SETUP + +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_DM_PMIC +-#endif +- + #endif +diff -ruN u-boot-2021.10/include/configs/imx8qm_mek.h u-boot/include/configs/imx8qm_mek.h +--- u-boot-2021.10/include/configs/imx8qm_mek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8qm_mek.h 2021-11-01 17:10:14.586241469 +0100 +@@ -42,8 +42,6 @@ + #define USDHC2_BASE_ADDR 0x5B020000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + #ifdef CONFIG_AHAB_BOOT + #define AHAB_ENV "sec_boot=yes\0" + #else +@@ -145,9 +143,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -159,9 +154,6 @@ + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + #define CONFIG_SYS_FSL_USDHC_NUM 2 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/imx8qm_rom7720.h u-boot/include/configs/imx8qm_rom7720.h +--- u-boot-2021.10/include/configs/imx8qm_rom7720.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8qm_rom7720.h 2021-11-01 17:10:14.586241469 +0100 +@@ -24,7 +24,6 @@ + + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* FUSE command */ + + /* Boot M4 */ +@@ -122,9 +121,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -146,9 +142,6 @@ + #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + #define CONFIG_SYS_FSL_USDHC_NUM 3 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/imx8qxp_mek.h u-boot/include/configs/imx8qxp_mek.h +--- u-boot-2021.10/include/configs/imx8qxp_mek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8qxp_mek.h 2021-11-01 17:10:14.586241469 +0100 +@@ -41,8 +41,6 @@ + #define USDHC1_BASE_ADDR 0x5B010000 + #define USDHC2_BASE_ADDR 0x5B020000 + +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- + #ifdef CONFIG_AHAB_BOOT + #define AHAB_ENV "sec_boot=yes\0" + #else +@@ -144,9 +142,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80280000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +@@ -158,9 +153,6 @@ + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + #define CONFIG_SYS_FSL_USDHC_NUM 2 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM_1 0x80000000 + #define PHYS_SDRAM_2 0x880000000 +diff -ruN u-boot-2021.10/include/configs/imx8ulp_evk.h u-boot/include/configs/imx8ulp_evk.h +--- u-boot-2021.10/include/configs/imx8ulp_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imx8ulp_evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -33,8 +33,6 @@ + + #endif + +-#define CONFIG_SERIAL_TAG +- + #define CONFIG_REMAKE_ELF + + #define CONFIG_BOARD_EARLY_INIT_F +@@ -63,8 +61,8 @@ + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttyLP1,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ +@@ -76,9 +74,6 @@ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x80480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -88,9 +83,6 @@ + #define CONFIG_ENV_OVERWRITE + #define CONFIG_MMCROOT "/dev/mmcblk2p2" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M) +- + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define PHYS_SDRAM 0x80000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +diff -ruN u-boot-2021.10/include/configs/imxrt1020-evk.h u-boot/include/configs/imxrt1020-evk.h +--- u-boot-2021.10/include/configs/imxrt1020-evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imxrt1020-evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,13 +11,6 @@ + + #define CONFIG_SYS_INIT_SP_ADDR 0x20240000 + +-#ifdef CONFIG_SUPPORT_SPL +-#define CONFIG_SYS_LOAD_ADDR 0x20209000 +-#else +-#define CONFIG_SYS_LOAD_ADDR 0x80000000 +-#define CONFIG_LOADADDR 0x80000000 +-#endif +- + #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 + #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +@@ -31,7 +24,6 @@ + /* + * Configuration of the external SDRAM memory + */ +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + /* For SPL */ + #ifdef CONFIG_SUPPORT_SPL +diff -ruN u-boot-2021.10/include/configs/imxrt1050-evk.h u-boot/include/configs/imxrt1050-evk.h +--- u-boot-2021.10/include/configs/imxrt1050-evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/imxrt1050-evk.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,13 +11,6 @@ + + #define CONFIG_SYS_INIT_SP_ADDR 0x20280000 + +-#ifdef CONFIG_SUPPORT_SPL +-#define CONFIG_SYS_LOAD_ADDR 0x20209000 +-#else +-#define CONFIG_SYS_LOAD_ADDR 0x80000000 +-#define CONFIG_LOADADDR 0x80000000 +-#endif +- + #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 + #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +@@ -42,7 +35,6 @@ + /* + * Configuration of the external SDRAM memory + */ +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + /* For SPL */ + #ifdef CONFIG_SUPPORT_SPL +diff -ruN u-boot-2021.10/include/configs/integrator-common.h u-boot/include/configs/integrator-common.h +--- u-boot-2021.10/include/configs/integrator-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/integrator-common.h 2021-11-01 17:10:14.586241469 +0100 +@@ -7,11 +7,6 @@ + */ + + #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS + + /* + * There are various dependencies on the core module (CM) fitted +@@ -48,7 +43,6 @@ + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + */ +-/* #define CONFIG_SKIP_LOWLEVEL_INIT */ + + /* + * The ARM boot monitor does not relocate U-Boot. +diff -ruN u-boot-2021.10/include/configs/iot2050.h u-boot/include/configs/iot2050.h +--- u-boot-2021.10/include/configs/iot2050.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/configs/iot2050.h 2021-11-01 17:10:14.586241469 +0100 +@@ -0,0 +1,62 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Configuration header file for IOT2050 ++ * Copyright (c) Siemens AG, 2018-2021 ++ * ++ * Authors: ++ * Le Jin <le.jin@siemens.com> ++ * Jan Kiszka <jan.kiszka@siemens.com> ++ */ ++ ++#ifndef __CONFIG_IOT2050_H ++#define __CONFIG_IOT2050_H ++ ++#include <linux/sizes.h> ++ ++/* SPL Loader Configuration */ ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ ++ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) ++ ++#define CONFIG_SKIP_LOWLEVEL_INIT ++ ++#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE ++ ++#define CONFIG_SYS_BOOTM_LEN SZ_64M ++ ++/* U-Boot general configuration */ ++#define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ ++ "usb_pgood_delay=900\0" ++ ++#ifndef CONFIG_SPL_BUILD ++ ++#if CONFIG_IS_ENABLED(CMD_USB) ++# define BOOT_TARGET_USB(func) \ ++ func(USB, usb, 0) \ ++ func(USB, usb, 1) \ ++ func(USB, usb, 2) ++#else ++# define BOOT_TARGET_USB(func) ++#endif ++ ++/* ++ * This defines all MMC devices, even if the basic variant has no mmc1. ++ * The non-supported device will be removed from the boot targets during ++ * runtime, when that board was detected. ++ */ ++#define BOOT_TARGET_DEVICES(func) \ ++ func(MMC, mmc, 1) \ ++ func(MMC, mmc, 0) \ ++ BOOT_TARGET_USB(func) ++ ++#include <config_distro_bootcmd.h> ++ ++#endif ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ DEFAULT_LINUX_BOOT_ENV \ ++ BOOTENV \ ++ EXTRA_ENV_IOT2050_BOARD_SETTINGS ++ ++#include <configs/ti_armv7_common.h> ++ ++#endif /* __CONFIG_IOT2050_H */ +diff -ruN u-boot-2021.10/include/configs/iot_devkit.h u-boot/include/configs/iot_devkit.h +--- u-boot-2021.10/include/configs/iot_devkit.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/iot_devkit.h 2021-11-01 17:10:14.586241469 +0100 +@@ -57,9 +57,7 @@ + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +-#define CONFIG_SYS_MALLOC_LEN SZ_64K + #define CONFIG_SYS_BOOTM_LEN SZ_128K +-#define CONFIG_SYS_LOAD_ADDR SRAM_BASE + + #define ROM_BASE CONFIG_SYS_MONITOR_BASE + #define ROM_SIZE SZ_256K +@@ -75,6 +73,5 @@ + * Environment + */ + #define CONFIG_BOOTFILE "app.bin" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #endif /* _CONFIG_IOT_DEVKIT_H_ */ +diff -ruN u-boot-2021.10/include/configs/jethub.h u-boot/include/configs/jethub.h +--- u-boot-2021.10/include/configs/jethub.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/configs/jethub.h 2021-11-01 17:10:14.586241469 +0100 +@@ -0,0 +1,40 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Configuration for JetHome devices ++ * Copyright (C) 2021 Vyacheslav Bocharov ++ * Author: Vyacheslav Bocharov <adeep@lexina.in> ++ */ ++ ++#ifndef __JETHUB_CONFIG_H ++#define __JETHUB_CONFIG_H ++ ++#if defined(CONFIG_MESON_AXG) ++#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ ++ "bootcmd_rescue=" \ ++ "if gpio input 10; then " \ ++ "run bootcmd_usb0;" \ ++ "fi;\0" ++#else ++#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ ++ "bootcmd_rescue=" \ ++ "if test \"${userbutton}\" = \"true\"; then " \ ++ "run bootcmd_mmc0; " \ ++ "fi;\0" ++#endif ++ ++#define BOOTENV_DEV_NAME_RESCUE(devtypeu, devtypel, instance) \ ++ "rescue " ++ ++#ifndef BOOT_TARGET_DEVICES ++#define BOOT_TARGET_DEVICES(func) \ ++ func(RESCUE, rescue, na) \ ++ func(MMC, mmc, 1) \ ++ func(MMC, mmc, 0) \ ++ BOOT_TARGET_DEVICES_USB(func) \ ++ func(PXE, pxe, na) \ ++ func(DHCP, dhcp, na) ++#endif ++ ++#include <configs/meson64.h> ++ ++#endif /* __JETHUB_CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/k2e_evm.h u-boot/include/configs/k2e_evm.h +--- u-boot-2021.10/include/configs/k2e_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/k2e_evm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,9 +11,6 @@ + + #include <environment/ti/spi.h> + +-/* Platform type */ +-#define CONFIG_SOC_K2E +- + #ifdef CONFIG_TI_SECURE_DEVICE + #define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ +@@ -23,7 +20,7 @@ + #endif + + /* U-Boot general configuration */ +-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ ++#define ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ +@@ -47,6 +44,4 @@ + #define CONFIG_KSNET_CPSW_NUM_PORTS 9 + #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + +-#define CONFIG_DDR_SPD +- + #endif /* __CONFIG_K2E_EVM_H */ +diff -ruN u-boot-2021.10/include/configs/k2g_evm.h u-boot/include/configs/k2g_evm.h +--- u-boot-2021.10/include/configs/k2g_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/k2g_evm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -12,11 +12,8 @@ + #include <environment/ti/mmc.h> + #include <environment/ti/spi.h> + +-/* Platform type */ +-#define CONFIG_SOC_K2G +- + /* U-Boot general configuration */ +-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ ++#define ENV_KS2_BOARD_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_PMMC_BOOT_ENV \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ +diff -ruN u-boot-2021.10/include/configs/k2hk_evm.h u-boot/include/configs/k2hk_evm.h +--- u-boot-2021.10/include/configs/k2hk_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/k2hk_evm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,9 +11,6 @@ + + #include <environment/ti/spi.h> + +-/* Platform type */ +-#define CONFIG_SOC_K2HK +- + #ifdef CONFIG_TI_SECURE_DEVICE + #define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ +@@ -23,7 +20,7 @@ + #endif + + /* U-Boot general configuration */ +-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ ++#define ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ +@@ -46,6 +43,4 @@ + #define CONFIG_KSNET_NETCP_V1_0 + #define CONFIG_KSNET_CPSW_NUM_PORTS 5 + +-#define CONFIG_DDR_SPD +- + #endif /* __CONFIG_K2HK_EVM_H */ +diff -ruN u-boot-2021.10/include/configs/k2l_evm.h u-boot/include/configs/k2l_evm.h +--- u-boot-2021.10/include/configs/k2l_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/k2l_evm.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,9 +11,6 @@ + + #include <environment/ti/spi.h> + +-/* Platform type */ +-#define CONFIG_SOC_K2L +- + #ifdef CONFIG_TI_SECURE_DEVICE + #define DEFAULT_SEC_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ +@@ -23,7 +20,7 @@ + #endif + + /* U-Boot general configuration */ +-#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ ++#define ENV_KS2_BOARD_SETTINGS \ + DEFAULT_FW_INITRAMFS_BOOT_ENV \ + DEFAULT_SEC_BOOT_ENV \ + "boot=ubi\0" \ +diff -ruN u-boot-2021.10/include/configs/km/km_arm.h u-boot/include/configs/km/km_arm.h +--- u-boot-2021.10/include/configs/km/km_arm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km_arm.h 2021-11-01 17:10:14.589574620 +0100 +@@ -25,23 +25,16 @@ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ + +-#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD +- + #define CONFIG_NAND_ECC_BCH + + /* include common defines/options for all Keymile boards */ + #include "keymile-common.h" + +-/* Reserve 4 MB for malloc */ +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +- + /* Increase max size of compressed kernel */ + #define CONFIG_SYS_BOOTM_LEN (32 << 20) + + #include "asm/arch/config.h" + +-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +- + /* architecture specific default bootargs */ + #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ + "bootcountaddr=${bootcountaddr} ${mtdparts}" \ +@@ -59,17 +52,6 @@ + "appended one; fi\0" \ + "" + +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +- +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ +- + /* + * NAND Flash configuration + */ +@@ -90,8 +72,6 @@ + * I2C related stuff + */ + #undef CONFIG_I2C_MVTWSI +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ + #define CONFIG_SYS_I2C_INIT_BOARD + + #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ +@@ -125,16 +105,8 @@ + #define I2C_DELAY udelay(1) + #define I2C_SOFT_DECLARATIONS + +-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +- + /* EEprom support 24C128, 24C256 valid for environment eeprom */ + #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * Environment variables configurations +@@ -142,8 +114,6 @@ + #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR + #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ + #else +-#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +-#define CONFIG_ENV_EEPROM_IS_ON_I2C + #define CONFIG_SYS_EEPROM_WREN + #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ + #endif +@@ -165,9 +135,9 @@ + "newenv=setenv addr 0x100000 && " \ + "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ + "mw.b ${addr} 0 4 && " \ +- "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ ++ "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ + " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ +- "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ ++ "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ + " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" + #endif + +diff -ruN u-boot-2021.10/include/configs/km/km-mpc8309.h u-boot/include/configs/km/km-mpc8309.h +--- u-boot-2021.10/include/configs/km/km-mpc8309.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km-mpc8309.h 2021-11-01 17:10:14.586241469 +0100 +@@ -8,7 +8,6 @@ + /* + * System Clock Setup + */ +-#define CONFIG_83XX_CLKIN 66000000 + #define CONFIG_SYS_CLK_FREQ 66000000 + #define CONFIG_83XX_PCICLK 66000000 + +@@ -123,7 +122,6 @@ + #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + + /* EEprom support */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + + /* ethernet port connected to piggy (UEC2) */ + #define CONFIG_HAS_ETH1 +diff -ruN u-boot-2021.10/include/configs/km/km-mpc832x.h u-boot/include/configs/km/km-mpc832x.h +--- u-boot-2021.10/include/configs/km/km-mpc832x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km-mpc832x.h 2021-11-01 17:10:14.586241469 +0100 +@@ -6,7 +6,6 @@ + /* + * System Clock Setup + */ +-#define CONFIG_83XX_CLKIN 66000000 + #define CONFIG_SYS_CLK_FREQ 66000000 + #define CONFIG_83XX_PCICLK 66000000 + +@@ -73,4 +72,3 @@ + + /* EEprom support */ + #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +- +diff -ruN u-boot-2021.10/include/configs/km/km-mpc8360.h u-boot/include/configs/km/km-mpc8360.h +--- u-boot-2021.10/include/configs/km/km-mpc8360.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km-mpc8360.h 2021-11-01 17:10:14.586241469 +0100 +@@ -67,7 +67,6 @@ + #define CONFIG_SYS_DDR_TIMING_3 0x00000000 + + /* EEprom support */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * PAXE on the local bus CS3 +diff -ruN u-boot-2021.10/include/configs/km/km-mpc83xx.h u-boot/include/configs/km/km-mpc83xx.h +--- u-boot-2021.10/include/configs/km/km-mpc83xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km-mpc83xx.h 2021-11-01 17:10:14.586241469 +0100 +@@ -18,7 +18,6 @@ + /* + * Manually set up DDR parameters + */ +-#define CONFIG_DDR_II + #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + + /* +@@ -62,17 +61,8 @@ + #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY + #define CONFIG_SYS_NUM_I2C_BUSES 4 + #define CONFIG_SYS_I2C_MAX_HOPS 1 +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 200000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ +diff -ruN u-boot-2021.10/include/configs/km/km-powerpc.h u-boot/include/configs/km/km-powerpc.h +--- u-boot-2021.10/include/configs/km/km-powerpc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/km-powerpc.h 2021-11-01 17:10:14.586241469 +0100 +@@ -11,13 +11,6 @@ + + /* EEprom support 24C08, 24C16, 24C64 */ + #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +- +-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +- +-/* Reserve 4 MB for malloc */ +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + /* Increase max size of compressed kernel */ + #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +diff -ruN u-boot-2021.10/include/configs/km/pg-wcom-ls102xa.h u-boot/include/configs/km/pg-wcom-ls102xa.h +--- u-boot-2021.10/include/configs/km/pg-wcom-ls102xa.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/km/pg-wcom-ls102xa.h 2021-11-01 17:10:14.589574620 +0100 +@@ -8,16 +8,9 @@ + + #define CONFIG_SYS_FSL_CLK + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* include common defines/options for all Keymile boards */ + #include "keymile-common.h" + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) +- + #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +@@ -26,12 +19,6 @@ + CONFIG_KM_RESERVED_PRAM) >> 10) + + #define CONFIG_SYS_CLK_FREQ 66666666 +-/* +- * Take into account default implementation where DDR_FDBK_MULTI is consider as +- * configured for DDR_PLL = 2*MEM_PLL_RAT. +- * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. +- */ +-#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) + + #define PHYS_SDRAM 0x80000000 + #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +@@ -42,8 +29,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +-#define CONFIG_DDR_SPD +- + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define SPD_EEPROM_ADDRESS 0x54 + +@@ -109,7 +94,6 @@ + #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + + /* NAND Flash Definitions */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0x68000000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +@@ -130,8 +114,6 @@ + | CSOR_NAND_TRHZ_40 \ + | CSOR_NAND_BCTLD) + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ +@@ -156,7 +138,6 @@ + + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + + /* QRIO FPGA Definitions */ + #define CONFIG_SYS_QRIO_BASE 0x70000000 +@@ -191,9 +172,7 @@ + /* + * I2C + */ +-#define CONFIG_SYS_I2C_LEGACY + #define CONFIG_SYS_I2C_INIT_BOARD +-#define CONFIG_SYS_I2C_SPEED 100000 + + #define CONFIG_I2C_MULTI_BUS + #define CONFIG_SYS_I2C_MAX_HOPS 1 +@@ -224,8 +203,6 @@ + * Miscellaneous configurable options + */ + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_LS102XA_STREAM_ID + + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/kmcent2.h u-boot/include/configs/kmcent2.h +--- u-boot-2021.10/include/configs/kmcent2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kmcent2.h 2021-11-01 17:10:14.589574620 +0100 +@@ -177,21 +177,14 @@ + #define CONFIG_VERY_BIG_RAM + #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +-#define CONFIG_DDR_CLK_FREQ 66666666 + + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +-#define CONFIG_DDR_SPD +- + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define SPD_EEPROM_ADDRESS 0x54 + #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + /****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- +@@ -263,7 +256,6 @@ + #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + + /* NAND Flash on IFC CS1*/ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0xfa000000 + #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +@@ -285,8 +277,6 @@ + CSOR_NAND_TRHZ_40 | /**/ \ + CSOR_NAND_BCTLD) /**/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ +@@ -366,8 +356,6 @@ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ + +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +- + /* + * Serial Port - controlled on board with jumper J8 + * open - index 2 +diff -ruN u-boot-2021.10/include/configs/kmcoge5ne.h u-boot/include/configs/kmcoge5ne.h +--- u-boot-2021.10/include/configs/kmcoge5ne.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kmcoge5ne.h 2021-11-01 17:10:14.589574620 +0100 +@@ -27,7 +27,6 @@ + /* + * System Clock Setup + */ +-#define CONFIG_83XX_CLKIN 66000000 + #define CONFIG_SYS_CLK_FREQ 66000000 + #define CONFIG_83XX_PCICLK 66000000 + +diff -ruN u-boot-2021.10/include/configs/kontron_sl28.h u-boot/include/configs/kontron_sl28.h +--- u-boot-2021.10/include/configs/kontron_sl28.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kontron_sl28.h 2021-11-01 17:10:14.589574620 +0100 +@@ -16,8 +16,6 @@ + #endif + + /* DDR */ +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + + #define CONFIG_VERY_BIG_RAM +@@ -42,18 +40,13 @@ + /* generic timer */ + #define COUNTER_FREQUENCY 25000000 + +-/* size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +- + /* early heap for SPL DM */ + #define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE + + /* serial port */ + #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + + /* ethernet */ +@@ -71,7 +64,6 @@ + + /* environment */ + /* see include/configs/ti_armv7_common.h */ +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + #define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ +diff -ruN u-boot-2021.10/include/configs/kp_imx53.h u-boot/include/configs/kp_imx53.h +--- u-boot-2021.10/include/configs/kp_imx53.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kp_imx53.h 2021-11-01 17:10:14.589574620 +0100 +@@ -12,20 +12,11 @@ + + #define CONFIG_SYS_FSL_CLK + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + /* USB Configs */ + #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + #define CONFIG_MXC_USB_FLAGS 0 + +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_EEPROM_BUS_NUM 1 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- + /* Command definition */ +-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1,115200\0" \ +@@ -77,7 +68,6 @@ + + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Physical Memory Map */ + #define PHYS_SDRAM_1 CSD0_BASE_ADDR +diff -ruN u-boot-2021.10/include/configs/kp_imx6q_tpc.h u-boot/include/configs/kp_imx6q_tpc.h +--- u-boot-2021.10/include/configs/kp_imx6q_tpc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kp_imx6q_tpc.h 2021-11-01 17:10:14.589574620 +0100 +@@ -16,13 +16,6 @@ + #include "imx6_spl.h" /* common IMX6 SPL configuration */ + + /* Miscellaneous configurable options */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + + /* FEC ethernet */ + #define CONFIG_ARP_TIMEOUT 200UL +@@ -37,11 +30,6 @@ + #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ + #endif + +-/* Watchdog */ +- +-#define CONFIG_LOADADDR 0x12000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #ifndef CONFIG_SPL_BUILD + #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ +diff -ruN u-boot-2021.10/include/configs/kzm9g.h u-boot/include/configs/kzm9g.h +--- u-boot-2021.10/include/configs/kzm9g.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/kzm9g.h 2021-11-01 17:10:14.589574620 +0100 +@@ -8,14 +8,9 @@ + #define __KZM9G_H + + #define CONFIG_SH73A0 +-#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G + + #include <asm/arch/rmobile.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + /* MEMORY */ + #define KZM_SDRAM_BASE (0x40000000) + #define PHYS_SDRAM KZM_SDRAM_BASE +@@ -46,10 +41,8 @@ + #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) + #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) + #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) + + #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + + #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 +@@ -82,23 +75,4 @@ + + #define CONFIG_NFS_TIMEOUT 10000UL + +-/* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SH +-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 +-#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 +-#define CONFIG_SYS_I2C_SH_SPEED0 100000 +-#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 +-#define CONFIG_SYS_I2C_SH_SPEED1 100000 +-#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 +-#define CONFIG_SYS_I2C_SH_SPEED2 100000 +-#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 +-#define CONFIG_SYS_I2C_SH_SPEED3 100000 +-#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 +-#define CONFIG_SYS_I2C_SH_SPEED4 100000 +-#define CONFIG_SH_I2C_8BIT +-#define CONFIG_SH_I2C_DATA_HIGH 4 +-#define CONFIG_SH_I2C_DATA_LOW 5 +-#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ +- + #endif /* __KZM9G_H */ +diff -ruN u-boot-2021.10/include/configs/lacie_kw.h u-boot/include/configs/lacie_kw.h +--- u-boot-2021.10/include/configs/lacie_kw.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lacie_kw.h 2021-11-01 17:10:14.589574620 +0100 +@@ -7,27 +7,6 @@ + #define _CONFIG_LACIE_KW_H + + /* +- * Machine number definition +- */ +-#if defined(CONFIG_INETSPACE_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 +-#elif defined(CONFIG_NETSPACE_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +-#elif defined(CONFIG_NETSPACE_LITE_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 +-#elif defined(CONFIG_NETSPACE_MINI_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 +-#elif defined(CONFIG_NETSPACE_MAX_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +-#elif defined(CONFIG_D2NET_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 +-#elif defined(CONFIG_NET2BIG_V2) +-#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 +-#else +-#error "Unknown board" +-#endif +- +-/* + * High Level Configuration Options (easy to change) + */ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +@@ -37,7 +16,6 @@ + #else + #define CONFIG_KW88F6281 + #endif +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + /* + * SDRAM configuration +@@ -99,9 +77,6 @@ + */ + #ifdef CONFIG_CMD_I2C + /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ + #if defined(CONFIG_NET2BIG_V2) + #define CONFIG_SYS_I2C_G762_ADDR 0x3e + #endif +diff -ruN u-boot-2021.10/include/configs/legoev3.h u-boot/include/configs/legoev3.h +--- u-boot-2021.10/include/configs/legoev3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/legoev3.h 2021-11-01 17:10:14.589574620 +0100 +@@ -22,12 +22,10 @@ + #define CONFIG_SYS_OSCIN_FREQ 24000000 + #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE + #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +-#define CONFIG_SKIP_LOWLEVEL_INIT + + /* + * Memory Info + */ +-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ + #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ + #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ + #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +@@ -47,7 +45,6 @@ + /* + * I2C Configuration + */ +-#define CONFIG_SYS_I2C_LEGACY + #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 + #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +@@ -57,15 +54,12 @@ + #define CONFIG_BOOTFILE "uImage" /* Boot file name */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + + /* + * Linux Information + */ + #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + #define CONFIG_HWCONFIG /* enable hwconfig */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS + #define CONFIG_SETUP_INITRD_TAG + #define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ +diff -ruN u-boot-2021.10/include/configs/linkit-smart-7688.h u-boot/include/configs/linkit-smart-7688.h +--- u-boot-2021.10/include/configs/linkit-smart-7688.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/linkit-smart-7688.h 2021-11-01 17:10:14.589574620 +0100 +@@ -12,14 +12,9 @@ + /* RAM */ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +- + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + + /* SPL */ +-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SPL_BSS_START_ADDR 0x80010000 +@@ -31,7 +26,7 @@ + #define CONFIG_SYS_UBOOT_BASE 0 + + /* Serial SPL */ +-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) ++#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) + #define CONFIG_SYS_NS16550_MEM32 + #define CONFIG_SYS_NS16550_CLK 40000000 + #define CONFIG_SYS_NS16550_REG_SIZE -4 +@@ -47,7 +42,6 @@ + + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 64 +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + #define CONFIG_SYS_CBSIZE 512 + +diff -ruN u-boot-2021.10/include/configs/liteboard.h u-boot/include/configs/liteboard.h +--- u-boot-2021.10/include/configs/liteboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/liteboard.h 2021-11-01 17:10:14.589574620 +0100 +@@ -16,9 +16,6 @@ + /* SPL options */ + #include "imx6_spl.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ +@@ -104,8 +101,6 @@ + "else run netboot; fi" + + /* Miscellaneous configurable options */ +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/ls1012a_common.h u-boot/include/configs/ls1012a_common.h +--- u-boot-2021.10/include/configs/ls1012a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1012a_common.h 2021-11-01 17:10:14.589574620 +0100 +@@ -6,22 +6,17 @@ + #ifndef __LS1012A_COMMON_H + #define __LS1012A_COMMON_H + +-#define CONFIG_GICV2 +- + #include <asm/arch/config.h> + #include <asm/arch/stream_id_lsch2.h> + #include <linux/sizes.h> + + #define CONFIG_SYS_CLK_FREQ 125000000 + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #ifdef CONFIG_TFABOOT + #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + #else + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + #endif +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +@@ -34,9 +29,6 @@ + /* CSU */ + #define CONFIG_LAYERSCAPE_NS_ACCESS + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M) +- + /* PFE */ + #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 + #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 +@@ -55,12 +47,6 @@ + CONFIG_SYS_SCSI_MAX_LUN) + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + + /* GPIO */ + #ifdef CONFIG_DM_GPIO +@@ -73,8 +59,6 @@ + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + #define CONFIG_SYS_HZ 1000 + + #define CONFIG_HWCONFIG +diff -ruN u-boot-2021.10/include/configs/ls1012aqds.h u-boot/include/configs/ls1012aqds.h +--- u-boot-2021.10/include/configs/ls1012aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1012aqds.h 2021-11-01 17:10:14.589574620 +0100 +@@ -54,13 +54,8 @@ + #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + + /* Voltage monitor on channel 2*/ +diff -ruN u-boot-2021.10/include/configs/ls1021aiot.h u-boot/include/configs/ls1021aiot.h +--- u-boot-2021.10/include/configs/ls1021aiot.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1021aiot.h 2021-11-01 17:10:14.589574620 +0100 +@@ -11,16 +11,10 @@ + + #define CONFIG_SYS_FSL_CLK + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) +- + #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + /* + * DDR: 800 MHz ( 1600 MT/s data rate ) +@@ -53,21 +47,13 @@ + #define SDRAM_CFG2_FRC_SR 0x80000000 + #define SDRAM_CFG_BI 0x00000001 + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI \ +- board/freescale/ls1021aiot/ls102xa_pbi.cfg +-#endif +- + #ifdef CONFIG_SD_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg + #define CONFIG_SPL_LIBCOMMON_SUPPORT + #define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_SPL_ENV_SUPPORT +-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + #define CONFIG_SPL_I2C + #define CONFIG_SPL_WATCHDOG +-#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_MMC + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 + + #define CONFIG_SPL_MAX_SIZE 0x1a000 +@@ -98,23 +84,9 @@ + * I2C + */ + +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +- + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * MMC +@@ -175,8 +147,6 @@ + #define CONFIG_PCI_SCAN_SHOW + #endif + +-#define CONFIG_CMDLINE_TAG +- + #define CONFIG_PEN_ADDR_BIG_ENDIAN + #define CONFIG_LAYERSCAPE_NS_ACCESS + #define CONFIG_SMP_PEN_ADDR 0x01ee0200 +@@ -196,8 +166,6 @@ + */ + #define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_LS102XA_STREAM_ID + + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/ls1021aqds.h u-boot/include/configs/ls1021aqds.h +--- u-boot-2021.10/include/configs/ls1021aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1021aqds.h 2021-11-01 17:10:14.589574620 +0100 +@@ -11,45 +11,23 @@ + + #define CONFIG_SYS_FSL_CLK + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_DEEP_SLEEP + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) +- + #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #define CONFIG_QIXIS_I2C_ACCESS + #else + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +-#endif +- +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg + #endif + + #ifdef CONFIG_SD_BOOT +-#ifdef CONFIG_SD_BOOT_QSPI +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +-#endif +- + #define CONFIG_SPL_MAX_SIZE 0x1a000 + #define CONFIG_SPL_STACK 0x1001d000 + #define CONFIG_SPL_PAD_TO 0x1c000 +@@ -63,15 +41,11 @@ + #endif + + #ifdef CONFIG_NAND_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +- + #define CONFIG_SPL_MAX_SIZE 0x1a000 + #define CONFIG_SPL_STACK 0x1001d000 + #define CONFIG_SPL_PAD_TO 0x1c000 + + #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 + #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +@@ -82,7 +56,6 @@ + #define CONFIG_SYS_MONITOR_LEN 0x80000 + #endif + +-#define CONFIG_DDR_SPD + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SPD_BUS_NUM 0 + +@@ -95,9 +68,7 @@ + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -153,7 +124,6 @@ + /* + * NAND Flash Definitions + */ +-#define CONFIG_NAND_FSL_IFC + + #define CONFIG_SYS_NAND_BASE 0x7e800000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +@@ -173,8 +143,6 @@ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -190,8 +158,6 @@ + + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +- +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + #endif + + /* +@@ -330,16 +296,6 @@ + /* + * I2C + */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + + /* GPIO */ + #ifdef CONFIG_DM_GPIO +@@ -349,13 +305,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* + * I2C bus multiplexer +@@ -429,8 +380,6 @@ + #define CONFIG_PCI_SCAN_SHOW + #endif + +-#define CONFIG_CMDLINE_TAG +- + #define CONFIG_PEN_ADDR_BIG_ENDIAN + #define CONFIG_LAYERSCAPE_NS_ACCESS + #define CONFIG_SMP_PEN_ADDR 0x01ee0200 +@@ -461,8 +410,6 @@ + */ + #define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_LS102XA_STREAM_ID + + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/ls1021atsn.h u-boot/include/configs/ls1021atsn.h +--- u-boot-2021.10/include/configs/ls1021atsn.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1021atsn.h 2021-11-01 17:10:14.589574620 +0100 +@@ -1,5 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0 +- * Copyright 2016-2019 NXP Semiconductors ++ * Copyright 2016-2019 NXP + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> + */ + +@@ -12,9 +12,6 @@ + + #define CONFIG_DEEP_SLEEP + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) +- + #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +@@ -22,7 +19,6 @@ + #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + #define DDR_SDRAM_CFG 0x470c0008 + #define DDR_CS0_BNDS 0x008000bf +@@ -51,15 +47,7 @@ + #define SDRAM_CFG2_FRC_SR 0x80000000 + #define SDRAM_CFG_BI 0x00000001 + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI \ +- "board/freescale/ls1021atsn/ls102xa_pbi.cfg" +-#endif +- + #ifdef CONFIG_SD_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW \ +- "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" +- + #ifdef CONFIG_NXP_ESBC + #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) + #endif /* ifdef CONFIG_NXP_ESBC */ +@@ -104,23 +92,10 @@ + #define CONFIG_SYS_NS16550_CLK get_serial_clock() + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* QSPI */ + #define FSL_QSPI_FLASH_SIZE (1 << 24) +@@ -220,8 +195,6 @@ + #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_LS102XA_STREAM_ID + + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/ls1021atwr.h u-boot/include/configs/ls1021atwr.h +--- u-boot-2021.10/include/configs/ls1021atwr.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1021atwr.h 2021-11-01 17:10:14.589574620 +0100 +@@ -11,19 +11,12 @@ + + #define CONFIG_SYS_FSL_CLK + +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_DEEP_SLEEP + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) +- + #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + #define DDR_SDRAM_CFG 0x470c0008 + #define DDR_CS0_BNDS 0x008000bf +@@ -52,19 +45,7 @@ + #define SDRAM_CFG2_FRC_SR 0x80000000 + #define SDRAM_CFG_BI 0x00000001 + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +-#endif +- + #ifdef CONFIG_SD_BOOT +-#ifdef CONFIG_SD_BOOT_QSPI +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +-#endif +- + #ifdef CONFIG_NXP_ESBC + /* + * HDR would be appended at end of image and copied to DDR along +@@ -208,16 +189,6 @@ + /* + * I2C + */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + + /* GPIO */ + #ifdef CONFIG_DM_GPIO +@@ -227,13 +198,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 1 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* + * MMC +@@ -267,8 +233,6 @@ + #define CONFIG_PCI_SCAN_SHOW + #endif + +-#define CONFIG_CMDLINE_TAG +- + #define CONFIG_PEN_ADDR_BIG_ENDIAN + #define CONFIG_LAYERSCAPE_NS_ACCESS + #define CONFIG_SMP_PEN_ADDR 0x01ee0200 +@@ -431,8 +395,6 @@ + */ + #define CONFIG_SYS_BOOTMAPSZ (256 << 20) + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_LS102XA_STREAM_ID + + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/ls1028a_common.h u-boot/include/configs/ls1028a_common.h +--- u-boot-2021.10/include/configs/ls1028a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1028a_common.h 2021-11-01 17:10:14.589574620 +0100 +@@ -16,8 +16,6 @@ + /* Link Definitions */ + #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_VERY_BIG_RAM + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL + #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +@@ -33,9 +31,6 @@ + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +- + /* GPIO */ + #ifdef CONFIG_DM_GPIO + #ifndef CONFIG_MPC8XXX_GPIO +@@ -44,19 +39,13 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#endif + + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + /* Physical Memory Map */ + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +@@ -103,13 +92,8 @@ + #define I2C_MUX_CH_DEFAULT 0x8 + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* DisplayPort */ + #define DP_PWD_EN_DEFAULT_MASK 0x8 +diff -ruN u-boot-2021.10/include/configs/ls1028aqds.h u-boot/include/configs/ls1028aqds.h +--- u-boot-2021.10/include/configs/ls1028aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1028aqds.h 2021-11-01 17:10:14.589574620 +0100 +@@ -9,7 +9,6 @@ + #include "ls1028a_common.h" + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + + /* DDR */ +diff -ruN u-boot-2021.10/include/configs/ls1028ardb.h u-boot/include/configs/ls1028ardb.h +--- u-boot-2021.10/include/configs/ls1028ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1028ardb.h 2021-11-01 17:10:14.589574620 +0100 +@@ -9,7 +9,6 @@ + #include "ls1028a_common.h" + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + + #define CONFIG_SYS_RTC_BUS_NUM 0 +diff -ruN u-boot-2021.10/include/configs/ls1043a_common.h u-boot/include/configs/ls1043a_common.h +--- u-boot-2021.10/include/configs/ls1043a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1043a_common.h 2021-11-01 17:10:14.589574620 +0100 +@@ -27,7 +27,6 @@ + #endif + + #define CONFIG_REMAKE_ELF +-#define CONFIG_GICV2 + + #include <asm/arch/stream_id_lsch2.h> + #include <asm/arch/config.h> +@@ -39,8 +38,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + #endif + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_VERY_BIG_RAM + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +@@ -52,16 +49,11 @@ + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +- + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + /* SD boot SPL */ + #ifdef CONFIG_SD_BOOT + +@@ -149,16 +141,6 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + + /* PCIe */ + #ifndef SPL_NO_PCIE +@@ -192,10 +174,7 @@ + + + #else +-#ifdef CONFIG_NAND_BOOT +-/* Store Fman ucode at offeset 0x900000(72 blocks). */ +-#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) +-#elif defined(CONFIG_SD_BOOT) ++#if defined(CONFIG_SD_BOOT) + /* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2040 blocks), Env is stored after the image, and the env size is +@@ -217,7 +196,6 @@ + #endif + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + #define CONFIG_HWCONFIG + #define HWCONFIG_BUFFER_SIZE 128 +@@ -236,7 +214,7 @@ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ +- "fdt_addr=0x64f00000\0" \ ++ "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ +diff -ruN u-boot-2021.10/include/configs/ls1043aqds.h u-boot/include/configs/ls1043aqds.h +--- u-boot-2021.10/include/configs/ls1043aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1043aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,13 +10,9 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +- +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_LAYERSCAPE_NS_ACCESS + +@@ -24,13 +20,10 @@ + /* Physical Memory Map */ + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +-#define CONFIG_DDR_SPD + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SPD_BUS_NUM 0 + +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -53,23 +46,6 @@ + #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB + #endif + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +-#endif +- +-#ifdef CONFIG_NAND_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +-#endif +- +-#ifdef CONFIG_SD_BOOT +-#ifdef CONFIG_SD_BOOT_QSPI +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +-#endif +-#endif +- + /* LPUART */ + #ifdef CONFIG_LPUART + #define CONFIG_LPUART_32B_REG +@@ -79,13 +55,8 @@ + #define CONFIG_SCSI_AHCI_PLAT + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #define CONFIG_SYS_SATA AHCI_BASE_ADDR + +@@ -140,7 +111,6 @@ + /* + * NAND Flash Definitions + */ +-#define CONFIG_NAND_FSL_IFC + + #define CONFIG_SYS_NAND_BASE 0x7e800000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +@@ -160,8 +130,6 @@ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -178,20 +146,16 @@ + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE +- +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + #endif + + #ifdef CONFIG_NAND_BOOT + #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO + #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) + #endif + + #if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) + #define CONFIG_QIXIS_I2C_ACCESS +-#define CONFIG_SYS_I2C_EARLY_INIT + #endif + + /* +@@ -395,8 +359,6 @@ + * Environment + */ + +-#define CONFIG_CMDLINE_TAG +- + #include <asm/fsl_secure_boot.h> + + #endif /* __LS1043AQDS_H__ */ +diff -ruN u-boot-2021.10/include/configs/ls1043ardb.h u-boot/include/configs/ls1043ardb.h +--- u-boot-2021.10/include/configs/ls1043ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1043ardb.h 2021-11-01 17:10:14.592907771 +0100 +@@ -9,7 +9,6 @@ + #include "ls1043a_common.h" + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + #define CONFIG_LAYERSCAPE_NS_ACCESS + +@@ -21,20 +20,10 @@ + + #ifndef CONFIG_SPL + #define CONFIG_SYS_DDR_RAW_TIMING +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +-#endif +- +-#ifdef CONFIG_NAND_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +-#endif +- + #ifdef CONFIG_SD_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg + #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 + #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 + #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 +@@ -83,9 +72,6 @@ + /* + * NAND Flash Definitions + */ +-#ifndef SPL_NO_IFC +-#define CONFIG_NAND_FSL_IFC +-#endif + + #define CONFIG_SYS_NAND_BASE 0x7e800000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +@@ -104,8 +90,6 @@ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -123,11 +107,8 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + #ifdef CONFIG_NAND_BOOT + #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO + #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) + #endif + +@@ -228,13 +209,8 @@ + + /* EEPROM */ + #ifndef SPL_NO_EEPROM +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + #endif + + /* +diff -ruN u-boot-2021.10/include/configs/ls1046a_common.h u-boot/include/configs/ls1046a_common.h +--- u-boot-2021.10/include/configs/ls1046a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1046a_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -27,7 +27,6 @@ + #endif + + #define CONFIG_REMAKE_ELF +-#define CONFIG_GICV2 + + #include <asm/arch/config.h> + #include <asm/arch/stream_id_lsch2.h> +@@ -39,8 +38,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + #endif + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_VERY_BIG_RAM + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +@@ -52,16 +49,11 @@ + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +- + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + /* SD boot SPL */ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ +@@ -108,7 +100,6 @@ + #define CONFIG_SPL_ENV_SUPPORT + #define CONFIG_SPL_WATCHDOG + #define CONFIG_SPL_I2C +-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + + #define CONFIG_SPL_NAND_SUPPORT + #define CONFIG_SPL_DRIVERS_MISC +@@ -133,16 +124,6 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + + /* PCIe */ + #define CONFIG_PCIE1 /* PCIE controller 1 */ +@@ -185,7 +166,7 @@ + #elif defined(CONFIG_QSPI_BOOT) + #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 + #elif defined(CONFIG_NAND_BOOT) +-#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) ++#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024)) + #else + #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 + #endif +@@ -195,7 +176,6 @@ + #endif + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + #define CONFIG_HWCONFIG + #define HWCONFIG_BUFFER_SIZE 128 +diff -ruN u-boot-2021.10/include/configs/ls1046afrwy.h u-boot/include/configs/ls1046afrwy.h +--- u-boot-2021.10/include/configs/ls1046afrwy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1046afrwy.h 2021-11-01 17:10:14.592907771 +0100 +@@ -9,7 +9,6 @@ + #include "ls1046a_common.h" + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + #define CONFIG_LAYERSCAPE_NS_ACCESS + +@@ -23,7 +22,6 @@ + /* + * NAND Flash Definitions + */ +-#define CONFIG_NAND_FSL_IFC + + #define CONFIG_SYS_NAND_BASE 0x7e800000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +@@ -42,8 +40,6 @@ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -61,8 +57,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + /* IFC Timing Params */ + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT + #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +@@ -74,13 +68,8 @@ + #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + #define I2C_RETIMER_ADDR 0x18 + + /* I2C bus multiplexer */ +diff -ruN u-boot-2021.10/include/configs/ls1046aqds.h u-boot/include/configs/ls1046aqds.h +--- u-boot-2021.10/include/configs/ls1046aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1046aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,13 +10,9 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +- +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_LAYERSCAPE_NS_ACCESS + +@@ -24,13 +20,10 @@ + /* Physical Memory Map */ + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +-#define CONFIG_DDR_SPD + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SPD_BUS_NUM 0 + +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -55,26 +48,6 @@ + #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB + #endif + +-#ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI \ +- board/freescale/ls1046aqds/ls1046aqds_pbi.cfg +-#endif +- +-#ifdef CONFIG_NAND_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg +-#endif +- +-#ifdef CONFIG_SD_BOOT +-#ifdef CONFIG_SD_BOOT_QSPI +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg +-#endif +-#endif +- + /* IFC */ + #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + #define CONFIG_FSL_IFC +@@ -103,13 +76,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* + * IFC Definitions +@@ -158,7 +126,6 @@ + /* + * NAND Flash Definitions + */ +-#define CONFIG_NAND_FSL_IFC + + #define CONFIG_SYS_NAND_BASE 0x7e800000 + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +@@ -178,8 +145,6 @@ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -196,20 +161,16 @@ + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE +- +-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) + #endif + + #ifdef CONFIG_NAND_BOOT + #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO + #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) + #endif + + #if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) + #define CONFIG_QIXIS_I2C_ACCESS +-#define CONFIG_SYS_I2C_EARLY_INIT + #endif + + /* +@@ -410,8 +371,6 @@ + * Environment + */ + +-#define CONFIG_CMDLINE_TAG +- + #undef CONFIG_BOOTCOMMAND + #ifdef CONFIG_TFABOOT + #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ +diff -ruN u-boot-2021.10/include/configs/ls1046ardb.h u-boot/include/configs/ls1046ardb.h +--- u-boot-2021.10/include/configs/ls1046ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1046ardb.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,7 +10,6 @@ + #include "ls1046a_common.h" + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + #define CONFIG_LAYERSCAPE_NS_ACCESS + +@@ -18,27 +17,12 @@ + /* Physical Memory Map */ + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +-#define CONFIG_DDR_SPD + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SPD_BUS_NUM 0 + +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +-#ifdef CONFIG_SD_BOOT +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg +-#ifdef CONFIG_EMMC_BOOT +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg +-#endif +-#elif defined(CONFIG_QSPI_BOOT) +-#define CONFIG_SYS_FSL_PBL_RCW \ +- board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg +-#define CONFIG_SYS_FSL_PBL_PBI \ +- board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg ++#if defined(CONFIG_QSPI_BOOT) + #define CONFIG_SYS_UBOOT_BASE 0x40100000 + #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 + #endif +@@ -49,7 +33,6 @@ + /* + * NAND Flash Definitions + */ +-#define CONFIG_NAND_FSL_IFC + #endif + + #define CONFIG_SYS_NAND_BASE 0x7e800000 +@@ -69,8 +52,6 @@ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ +@@ -88,8 +69,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + /* + * CPLD + */ +@@ -135,20 +114,11 @@ + #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + #define I2C_RETIMER_ADDR 0x18 + + /* PMIC */ +-#define CONFIG_POWER +-#ifdef CONFIG_POWER +-#define CONFIG_POWER_I2C +-#endif + + /* + * Environment +diff -ruN u-boot-2021.10/include/configs/ls1088a_common.h u-boot/include/configs/ls1088a_common.h +--- u-boot-2021.10/include/configs/ls1088a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1088a_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -37,8 +37,6 @@ + /* Link Definitions */ + #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_VERY_BIG_RAM + #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL + #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +@@ -50,9 +48,6 @@ + */ + #define CPU_RELEASE_ADDR secondary_boot_addr + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +- + /* GPIO */ + #ifdef CONFIG_DM_GPIO + #ifndef CONFIG_MPC8XXX_GPIO +@@ -61,9 +56,6 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#endif + + + /* Serial Port */ +@@ -71,8 +63,6 @@ + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) + /* IFC */ + #define CONFIG_FSL_IFC +@@ -147,7 +137,6 @@ + #endif + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + /* SATA */ + #ifdef CONFIG_SCSI +diff -ruN u-boot-2021.10/include/configs/ls1088aqds.h u-boot/include/configs/ls1088aqds.h +--- u-boot-2021.10/include/configs/ls1088aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1088aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,7 +11,6 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #ifdef CONFIG_TFABOOT +@@ -23,14 +22,9 @@ + #define SYS_NO_FLASH + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #else + #define CONFIG_QIXIS_I2C_ACCESS +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_EARLY_INIT +-#endif + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + #endif + + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) +@@ -38,9 +32,6 @@ + + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +-#define CONFIG_DDR_SPD +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SPD_BUS_NUM 0 +@@ -104,7 +95,6 @@ + #endif + #endif + +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +@@ -123,8 +113,6 @@ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -143,8 +131,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + #define CONFIG_FSL_QIXIS + #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + #define QIXIS_LBMAP_SWITCH 6 +@@ -335,13 +321,8 @@ + #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #ifdef CONFIG_FSL_DSPI + #define CONFIG_SPI_FLASH_STMICRO +diff -ruN u-boot-2021.10/include/configs/ls1088ardb.h u-boot/include/configs/ls1088ardb.h +--- u-boot-2021.10/include/configs/ls1088ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls1088ardb.h 2021-11-01 17:10:14.592907771 +0100 +@@ -17,18 +17,12 @@ + #endif + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-#define CONFIG_DDR_SPD + #ifdef CONFIG_EMU + #define CONFIG_SYS_FSL_DDR_EMU +-#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +-#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 + #else +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + #define SPD_EEPROM_ADDRESS 0x51 +@@ -77,10 +71,6 @@ + #endif + #endif + +-#ifndef SPL_NO_IFC +-#define CONFIG_NAND_FSL_IFC +-#endif +- + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +@@ -99,8 +89,6 @@ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -119,8 +107,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + #ifndef SPL_NO_QIXIS + #define CONFIG_FSL_QIXIS + #endif +@@ -241,13 +227,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #ifdef CONFIG_SPL_BUILD + #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +diff -ruN u-boot-2021.10/include/configs/ls2080a_common.h u-boot/include/configs/ls2080a_common.h +--- u-boot-2021.10/include/configs/ls2080a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls2080a_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -8,7 +8,6 @@ + #define __LS2_COMMON_H + + #define CONFIG_REMAKE_ELF +-#define CONFIG_GICV3 + + #include <asm/arch/stream_id_lsch3.h> + #include <asm/arch/config.h> +@@ -24,8 +23,6 @@ + + /* Link Definitions */ + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #ifndef CONFIG_SYS_FSL_DDR4 + #define CONFIG_SYS_DDR_RAW_TIMING + #endif +@@ -63,9 +60,6 @@ + */ + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +- + /* GPIO */ + #ifdef CONFIG_DM_GPIO + #ifndef CONFIG_MPC8XXX_GPIO +@@ -74,17 +68,12 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#endif + + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE 1 + #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + /* IFC */ + #define CONFIG_FSL_IFC + +@@ -157,7 +146,6 @@ + #endif + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + /* Physical Memory Map */ + /* fixme: these need to be checked against the board */ +diff -ruN u-boot-2021.10/include/configs/ls2080aqds.h u-boot/include/configs/ls2080aqds.h +--- u-boot-2021.10/include/configs/ls2080aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls2080aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,25 +11,17 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #ifdef CONFIG_FSL_QSPI + #define CONFIG_QIXIS_I2C_ACCESS +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_EARLY_INIT +-#endif + #define CONFIG_SYS_I2C_IFDR_DIV 0x7e + #endif + + #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +-#define CONFIG_DDR_SPD +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #define SPD_EEPROM_ADDRESS1 0x51 + #define SPD_EEPROM_ADDRESS2 0x52 +@@ -108,7 +100,6 @@ + CONFIG_SYS_FLASH_BASE + 0x40000000} + #endif + +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +@@ -127,8 +118,6 @@ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -147,8 +136,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +- + #define CONFIG_FSL_QIXIS /* use common QIXIS code */ + #define QIXIS_LBMAP_SWITCH 0x06 + #define QIXIS_LBMAP_MASK 0x0f +@@ -221,7 +208,6 @@ + #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + + #define CONFIG_SPL_PAD_TO 0x20000 +-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) + #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) + #endif + #else +@@ -304,13 +290,8 @@ + #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #define CONFIG_FSL_MEMAC + +diff -ruN u-boot-2021.10/include/configs/ls2080ardb.h u-boot/include/configs/ls2080ardb.h +--- u-boot-2021.10/include/configs/ls2080ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ls2080ardb.h 2021-11-01 17:10:14.592907771 +0100 +@@ -13,9 +13,6 @@ + #ifdef CONFIG_TARGET_LS2081ARDB + #define CONFIG_QIXIS_I2C_ACCESS + #endif +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_EARLY_INIT +-#endif + #endif + + #define I2C_MUX_CH_VOL_MONITOR 0xa +@@ -39,12 +36,8 @@ + #endif + + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ 133333333 + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +-#define CONFIG_DDR_SPD +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #define SPD_EEPROM_ADDRESS1 0x51 + #define SPD_EEPROM_ADDRESS2 0x52 +@@ -115,7 +108,6 @@ + CONFIG_SYS_FLASH_BASE + 0x40000000} + #endif + +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +@@ -134,8 +126,6 @@ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ + FTIM0_NAND_TWP(0x30) | \ +@@ -154,7 +144,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + #define CONFIG_FSL_QIXIS /* use common QIXIS code */ + #define QIXIS_LBMAP_SWITCH 0x06 + #define QIXIS_LBMAP_MASK 0x0f +@@ -213,7 +202,6 @@ + #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + + #define CONFIG_SPL_PAD_TO 0x80000 +-#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) + #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) + #else + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +@@ -286,13 +274,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #define CONFIG_FSL_MEMAC + +diff -ruN u-boot-2021.10/include/configs/lsxl.h u-boot/include/configs/lsxl.h +--- u-boot-2021.10/include/configs/lsxl.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lsxl.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,10 +12,8 @@ + */ + #if defined(CONFIG_LSCHLV2) + #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +-#define CONFIG_MACH_TYPE 3006 + #elif defined(CONFIG_LSXHL) + #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +-#define CONFIG_MACH_TYPE 2663 + #else + #error "unknown board" + #endif +@@ -26,8 +24,6 @@ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ + +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +- + #define CONFIG_KIRKWOOD_GPIO + + #include "mv-common.h" +@@ -45,7 +41,6 @@ + /* + * Default environment variables + */ +-#define CONFIG_LOADADDR 0x00800000 + + #if defined(CONFIG_LSXHL) + #define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" +diff -ruN u-boot-2021.10/include/configs/lx2160a_common.h u-boot/include/configs/lx2160a_common.h +--- u-boot-2021.10/include/configs/lx2160a_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lx2160a_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,15 +12,12 @@ + + #define CONFIG_REMAKE_ELF + #define CONFIG_FSL_LAYERSCAPE +-#define CONFIG_GICV3 + #define CONFIG_FSL_TZPC_BP147 + #define CONFIG_FSL_MEMAC + + #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_FLASH_BASE 0x20000000 + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* DDR */ + #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ + #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +@@ -30,9 +27,6 @@ + #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL + #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 + #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL +-#define CONFIG_DDR_SPD +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #define SPD_EEPROM_ADDRESS1 0x51 +@@ -49,7 +43,6 @@ + #define CONFIG_SYS_MONITOR_LEN (936 * 1024) + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + + /* SMP Definitinos */ + #define CPU_RELEASE_ADDR secondary_boot_addr +@@ -62,9 +55,6 @@ + + #define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +- + /* Serial Port */ + #define CONFIG_PL01X_SERIAL + #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +@@ -77,7 +67,6 @@ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3 } +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + /* MC firmware */ + #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +@@ -110,13 +99,8 @@ + #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* Qixis */ + #define CONFIG_FSL_QIXIS +@@ -157,11 +141,9 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + + #define CONFIG_HWCONFIG +diff -ruN u-boot-2021.10/include/configs/lx2160aqds.h u-boot/include/configs/lx2160aqds.h +--- u-boot-2021.10/include/configs/lx2160aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lx2160aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -34,13 +34,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/lx2160ardb.h u-boot/include/configs/lx2160ardb.h +--- u-boot-2021.10/include/configs/lx2160ardb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lx2160ardb.h 2021-11-01 17:10:14.592907771 +0100 +@@ -30,13 +30,8 @@ + #define I2C_EMC2305_PWM 0x80 + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/lx2162aqds.h u-boot/include/configs/lx2162aqds.h +--- u-boot-2021.10/include/configs/lx2162aqds.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/lx2162aqds.h 2021-11-01 17:10:14.592907771 +0100 +@@ -38,13 +38,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/M5208EVBE.h u-boot/include/configs/M5208EVBE.h +--- u-boot-2021.10/include/configs/M5208EVBE.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5208EVBE.h 2021-11-01 17:10:14.572908865 +0100 +@@ -40,11 +40,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + + #define CONFIG_UDP_CHECKSUM +@@ -71,8 +66,6 @@ + + #define CONFIG_PRAM 512 /* 512 KB */ + +-#define CONFIG_SYS_LOAD_ADDR 0x40010000 +- + #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ + #define CONFIG_SYS_PLL_ODR 0x36 + #define CONFIG_SYS_PLL_FDR 0x7D +@@ -108,7 +101,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + /* + * For booting Linux, the board info and command line data +@@ -138,7 +130,6 @@ + env/embedded.o(.text*); + + /* Cache Configuration */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5235EVB.h u-boot/include/configs/M5235EVB.h +--- u-boot-2021.10/include/configs/M5235EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5235EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -49,11 +49,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_i2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) + #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +@@ -83,8 +78,6 @@ + + #define CONFIG_PRAM 512 /* 512 KB */ + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) +- + #define CONFIG_SYS_CLK 75000000 + #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 + +@@ -116,7 +109,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + /* + * For booting Linux, the board info and command line data +@@ -154,7 +146,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5249EVB.h u-boot/include/configs/M5249EVB.h +--- u-boot-2021.10/include/configs/M5249EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5249EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -31,8 +31,6 @@ + */ + #undef CONFIG_BOOTP_BOOTFILESIZE + +-#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +- + /* + * Clock configuration: enable only one of the following options + */ +@@ -78,7 +76,6 @@ + #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -104,7 +101,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5253DEMO.h u-boot/include/configs/M5253DEMO.h +--- u-boot-2021.10/include/configs/M5253DEMO.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5253DEMO.h 2021-11-01 17:10:14.572908865 +0100 +@@ -70,18 +70,11 @@ + #define CONFIG_HOSTNAME "M5253DEMO" + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) + #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) + #define CONFIG_SYS_I2C_PINMUX_SET (0) + +-#define CONFIG_SYS_LOAD_ADDR 0x00100000 +- + #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ + #define CONFIG_SYS_FAST_CLK + #ifdef CONFIG_SYS_FAST_CLK +@@ -124,7 +117,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN 0x40000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) + + /* +@@ -160,7 +152,6 @@ + #endif + + /* Cache Configuration */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5272C3.h u-boot/include/configs/M5272C3.h +--- u-boot-2021.10/include/configs/M5272C3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5272C3.h 2021-11-01 17:10:14.572908865 +0100 +@@ -75,7 +75,6 @@ + "save\0" \ + "" + +-#define CONFIG_SYS_LOAD_ADDR 0x20000 + #define CONFIG_SYS_CLK 66000000 + + /* +@@ -111,7 +110,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -134,7 +132,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5275EVB.h u-boot/include/configs/M5275EVB.h +--- u-boot-2021.10/include/configs/M5275EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5275EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -59,18 +59,11 @@ + #endif + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) + #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) + #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) + +-#define CONFIG_SYS_LOAD_ADDR 0x800000 +- + #define CONFIG_BOOTCOMMAND "bootm ffe40000" + + #ifdef CONFIG_MCFFEC +@@ -124,7 +117,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -147,7 +139,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5282EVB.h u-boot/include/configs/M5282EVB.h +--- u-boot-2021.10/include/configs/M5282EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5282EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -72,8 +72,6 @@ + "save\0" \ + "" + +-#define CONFIG_SYS_LOAD_ADDR 0x20000 +- + #define CONFIG_SYS_CLK 64000000 + + /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ +@@ -116,7 +114,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN 0x20000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 + + /* +@@ -142,7 +139,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M53017EVB.h u-boot/include/configs/M53017EVB.h +--- u-boot-2021.10/include/configs/M53017EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M53017EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -55,11 +55,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + + #define CONFIG_UDP_CHECKSUM +@@ -86,8 +81,6 @@ + + #define CONFIG_PRAM 512 /* 512 KB */ + +-#define CONFIG_SYS_LOAD_ADDR 0x40010000 +- + #define CONFIG_SYS_CLK 80000000 + #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +@@ -124,7 +117,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + /* + * For booting Linux, the board info and command line data +@@ -158,7 +150,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5329EVB.h u-boot/include/configs/M5329EVB.h +--- u-boot-2021.10/include/configs/M5329EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5329EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -49,11 +49,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + + #define CONFIG_UDP_CHECKSUM +@@ -80,8 +75,6 @@ + + #define CONFIG_PRAM 512 /* 512 KB */ + +-#define CONFIG_SYS_LOAD_ADDR 0x40010000 +- + #define CONFIG_SYS_CLK 80000000 + #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +@@ -120,7 +113,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + /* + * For booting Linux, the board info and command line data +@@ -165,7 +157,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/M5373EVB.h u-boot/include/configs/M5373EVB.h +--- u-boot-2021.10/include/configs/M5373EVB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/M5373EVB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -51,11 +51,6 @@ + #define CONFIG_MCFTMR + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 80000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 + #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + + #define CONFIG_UDP_CHECKSUM +@@ -82,8 +77,6 @@ + + #define CONFIG_PRAM 512 /* 512 KB */ + +-#define CONFIG_SYS_LOAD_ADDR 0x40010000 +- + #define CONFIG_SYS_CLK 80000000 + #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +@@ -122,7 +115,6 @@ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + /* + * For booting Linux, the board info and command line data +@@ -167,7 +159,6 @@ + /*----------------------------------------------------------------------- + * Cache Configuration + */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +diff -ruN u-boot-2021.10/include/configs/m53menlo.h u-boot/include/configs/m53menlo.h +--- u-boot-2021.10/include/configs/m53menlo.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/m53menlo.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,7 +11,6 @@ + + #include <asm/arch/imx-regs.h> + +-#define CONFIG_REVISION_TAG + #define CONFIG_SYS_FSL_CLK + + #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +@@ -24,7 +23,6 @@ + #define PHYS_SDRAM_2 CSD1_BASE_ADDR + #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) + #define PHYS_SDRAM_SIZE (gd->ram_size) +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + + #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) + #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +@@ -84,17 +82,7 @@ + #define CONFIG_ETHPRIME "FEC0" + #endif + +-/* +- * I2C +- */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +-#endif + + /* + * RTC +@@ -141,14 +129,8 @@ + /* + * Boot Linux + */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SETUP_MEMORY_TAGS + #define CONFIG_BOOTFILE "boot/fitImage" +-#define CONFIG_LOADADDR 0x70800000 + #define CONFIG_BOOTCOMMAND "run mmc_mmc" +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* + * NAND SPL +@@ -157,12 +139,7 @@ + #define CONFIG_SPL_PAD_TO 0x8000 + #define CONFIG_SPL_STACK 0x70004000 + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 + #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + + /* + * Extra Environments +diff -ruN u-boot-2021.10/include/configs/malta.h u-boot/include/configs/malta.h +--- u-boot-2021.10/include/configs/malta.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/malta.h 2021-11-01 17:10:14.592907771 +0100 +@@ -38,9 +38,6 @@ + + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) +- +-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + +diff -ruN u-boot-2021.10/include/configs/maxbcm.h u-boot/include/configs/maxbcm.h +--- u-boot-2021.10/include/configs/maxbcm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/maxbcm.h 2021-11-01 17:10:14.592907771 +0100 +@@ -6,6 +6,8 @@ + #ifndef _CONFIG_DB_MV7846MP_GP_H + #define _CONFIG_DB_MV7846MP_GP_H + ++#include <linux/sizes.h> ++ + /* + * High Level Configuration Options (easy to change) + */ +@@ -17,11 +19,7 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* SPI NOR flash default params, used by sf commands */ + +@@ -65,7 +63,7 @@ + /* SPL related SPI defines */ + + /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +-#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ ++#define CONFIG_SYS_SDRAM_SIZE SZ_1G + #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ + + #endif /* _CONFIG_DB_MV7846MP_GP_H */ +diff -ruN u-boot-2021.10/include/configs/mccmon6.h u-boot/include/configs/mccmon6.h +--- u-boot-2021.10/include/configs/mccmon6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mccmon6.h 2021-11-01 17:10:14.592907771 +0100 +@@ -25,9 +25,6 @@ + #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) + #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configuration */ +diff -ruN u-boot-2021.10/include/configs/MCR3000.h u-boot/include/configs/MCR3000.h +--- u-boot-2021.10/include/configs/MCR3000.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MCR3000.h 2021-11-01 17:10:14.572908865 +0100 +@@ -60,8 +60,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR 0x200000 +- + #define CONFIG_SYS_HZ 1000 + + /* Definitions for initial stack pointer and data area (in DPRAM) */ +@@ -86,7 +84,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (8 << 20) + #define CONFIG_SYS_MONITOR_LEN (320 << 10) + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) + + /* Environment Configuration */ + +@@ -98,7 +95,6 @@ + + /* NAND configuration part */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_BASE 0x0C000000 + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/meerkat96.h u-boot/include/configs/meerkat96.h +--- u-boot-2021.10/include/configs/meerkat96.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/meerkat96.h 2021-11-01 17:10:14.592907771 +0100 +@@ -14,10 +14,6 @@ + + #define PHYS_SDRAM_SIZE SZ_512M + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/meesc.h u-boot/include/configs/meesc.h +--- u-boot-2021.10/include/configs/meesc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/meesc.h 2021-11-01 17:10:14.592907771 +0100 +@@ -32,12 +32,6 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ + + /* Misc CPU related */ +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SERIAL_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ + + /* + * Hardware drivers +@@ -58,8 +52,6 @@ + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) +- + /* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above +@@ -100,10 +92,4 @@ + + #define CONFIG_SYS_CBSIZE 512 + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ +- 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/meson64_android.h u-boot/include/configs/meson64_android.h +--- u-boot-2021.10/include/configs/meson64_android.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/meson64_android.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,8 +11,6 @@ + + #include <linux/sizes.h> + +-#define CONFIG_SYS_MALLOC_LEN SZ_128M +- + #ifndef BOOT_PARTITION + #define BOOT_PARTITION "boot" + #endif +diff -ruN u-boot-2021.10/include/configs/meson64.h u-boot/include/configs/meson64.h +--- u-boot-2021.10/include/configs/meson64.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/meson64.h 2021-11-01 17:10:14.592907771 +0100 +@@ -32,14 +32,10 @@ + #define CONFIG_CPU_ARMV8 + #define CONFIG_REMAKE_ELF + #define CONFIG_SYS_MAXARGS 32 +-#ifndef CONFIG_SYS_MALLOC_LEN +-#define CONFIG_SYS_MALLOC_LEN (32 << 20) +-#endif + #define CONFIG_SYS_CBSIZE 1024 + + #define CONFIG_SYS_SDRAM_BASE 0 + #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ + + /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ +@@ -66,6 +62,12 @@ + #define BOOT_TARGET_NVME(func) + #endif + ++#ifdef CONFIG_CMD_SCSI ++ #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) ++#else ++ #define BOOT_TARGET_SCSI(func) ++#endif ++ + #ifndef BOOT_TARGET_DEVICES + #define BOOT_TARGET_DEVICES(func) \ + func(ROMUSB, romusb, na) \ +@@ -74,6 +76,7 @@ + func(MMC, mmc, 2) \ + BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_NVME(func) \ ++ BOOT_TARGET_SCSI(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + #endif +diff -ruN u-boot-2021.10/include/configs/microblaze-generic.h u-boot/include/configs/microblaze-generic.h +--- u-boot-2021.10/include/configs/microblaze-generic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/microblaze-generic.h 2021-11-01 17:10:14.592907771 +0100 +@@ -24,8 +24,6 @@ + /* setting reset address */ + /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ + +-#define CONFIG_SYS_MALLOC_LEN 0xC0000 +- + /* Stack location before relocation */ + #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_F_LEN) +@@ -55,8 +53,6 @@ + #define CONFIG_SYS_CBSIZE 512 + /* max number of command args */ + #define CONFIG_SYS_MAXARGS 15 +-/* default load address */ +-#define CONFIG_SYS_LOAD_ADDR 0 + + #define CONFIG_HOSTNAME "microblaze-generic" + +diff -ruN u-boot-2021.10/include/configs/microchip_mpfs_icicle.h u-boot/include/configs/microchip_mpfs_icicle.h +--- u-boot-2021.10/include/configs/microchip_mpfs_icicle.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/microchip_mpfs_icicle.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,10 +12,6 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +- +-#define CONFIG_SYS_MALLOC_LEN SZ_8M +- + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +diff -ruN u-boot-2021.10/include/configs/MPC8349EMDS.h u-boot/include/configs/MPC8349EMDS.h +--- u-boot-2021.10/include/configs/MPC8349EMDS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC8349EMDS.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,369 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2006-2010 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- */ +- +-/* +- * mpc8349emds board configuration file +- * +- */ +- +-#ifndef __CONFIG_H +-#define __CONFIG_H +- +-/* +- * High Level Configuration Options +- */ +-#define CONFIG_E300 1 /* E300 Family */ +- +-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +- +-/* +- * DDR Setup +- */ +-#define CONFIG_DDR_ECC /* support DDR ECC function */ +-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +- +-/* +- * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver +- * unselect it to use old spd_sdram.c +- */ +-#define CONFIG_SYS_SPD_BUS_NUM 0 +-#define SPD_EEPROM_ADDRESS1 0x52 +-#define SPD_EEPROM_ADDRESS2 0x51 +-#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +- +-/* +- * 32-bit data path mode. +- * +- * Please note that using this mode for devices with the real density of 64-bit +- * effectively reduces the amount of available memory due to the effect of +- * wrapping around while translating address to row/columns, for example in the +- * 256MB module the upper 128MB get aliased with contents of the lower +- * 128MB); normally this define should be used for devices with real 32-bit +- * data path. +- */ +-#undef CONFIG_DDR_32BIT +- +-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ +- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +-#undef CONFIG_DDR_2T_TIMING +- +-/* +- * DDRCDR - DDR Control Driver Register +- */ +-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 +- +-#if defined(CONFIG_SPD_EEPROM) +-/* +- * Determine DDR configuration from I2C interface. +- */ +-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +-#else +-/* +- * Manually set up DDR parameters +- */ +-#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +-#if defined(CONFIG_DDR_II) +-#define CONFIG_SYS_DDRCDR 0x80080001 +-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +-#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +-#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +-#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +-#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +-#define CONFIG_SYS_DDR_MODE 0x47d00432 +-#define CONFIG_SYS_DDR_MODE2 0x8000c000 +-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +-#else +-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ +- | CSCONFIG_ROW_BIT_13 \ +- | CSCONFIG_COL_BIT_10) +-#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ +- +-#if defined(CONFIG_DDR_32BIT) +-/* set burst length to 8 for 32-bit data path */ +- /* DLL,normal,seq,4/2.5, 8 burst len */ +-#define CONFIG_SYS_DDR_MODE 0x00000023 +-#else +-/* the default burst length is 4 - for 64-bit data path */ +- /* DLL,normal,seq,4/2.5, 4 burst len */ +-#define CONFIG_SYS_DDR_MODE 0x00000022 +-#endif +-#endif +-#endif +- +-/* +- * SDRAM on the Local Bus +- */ +-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +- +-/* +- * FLASH on the Local Bus +- */ +-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ +- +- +-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ +- +-#undef CONFIG_SYS_FLASH_CHECKSUM +-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +- +-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +- +-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +-#define CONFIG_SYS_RAMBOOT +-#else +-#undef CONFIG_SYS_RAMBOOT +-#endif +- +-/* +- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg +- */ +-#define CONFIG_SYS_BCSR 0xE2400000 +- /* Access window base at BCSR base */ +- +- +-#define CONFIG_SYS_INIT_RAM_LOCK 1 +-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ +- +-#define CONFIG_SYS_GBL_DATA_OFFSET \ +- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +- +-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +- +-/* +- * Serial Port +- */ +-#define CONFIG_SYS_NS16550_SERIAL +-#define CONFIG_SYS_NS16550_REG_SIZE 1 +-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +- +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +- +-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +- +-/* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +- +-/* SPI */ +-#undef CONFIG_SOFT_SPI /* SPI bit-banged */ +- +-/* GPIOs. Used as SPI chip selects */ +-#define CONFIG_SYS_GPIO1_PRELIM +-#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +-#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ +- +-/* TSEC */ +-#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +-#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) +- +-/* USB */ +-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ +- +-/* +- * General PCI +- * Addresses are mapped 1-1. +- */ +-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +- +-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ +- +-#if defined(CONFIG_PCI) +- +-#define CONFIG_83XX_PCI_STREAMING +- +- +-#if !defined(CONFIG_PCI_PNP) +- #define PCI_ENET0_IOADDR 0xFIXME +- #define PCI_ENET0_MEMADDR 0xFIXME +- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +-#endif +- +-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +- +-#endif /* CONFIG_PCI */ +- +-/* +- * TSEC configuration +- */ +- +-#if defined(CONFIG_TSEC_ENET) +- +-#define CONFIG_GMII 1 /* MII PHY management */ +-#define CONFIG_TSEC1 1 +-#define CONFIG_TSEC1_NAME "TSEC0" +-#define CONFIG_TSEC2 1 +-#define CONFIG_TSEC2_NAME "TSEC1" +-#define TSEC1_PHY_ADDR 0 +-#define TSEC2_PHY_ADDR 1 +-#define TSEC1_PHYIDX 0 +-#define TSEC2_PHYIDX 0 +-#define TSEC1_FLAGS TSEC_GIGABIT +-#define TSEC2_FLAGS TSEC_GIGABIT +- +-/* Options are: TSEC[0-1] */ +-#define CONFIG_ETHPRIME "TSEC0" +- +-#endif /* CONFIG_TSEC_ENET */ +- +-/* +- * Configure on-board RTC +- */ +-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +- +-/* +- * Environment +- */ +-#ifndef CONFIG_SYS_RAMBOOT +-/* Address and size of Redundant Environment Sector */ +-#endif +- +-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +- +-/* +- * BOOTP options +- */ +-#define CONFIG_BOOTP_BOOTFILESIZE +- +-#undef CONFIG_WATCHDOG /* watchdog disabled */ +- +-/* +- * Miscellaneous configurable options +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +- +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 256 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +- /* Initial Memory map for Linux*/ +-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +- +-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ +- +-/* +- * System performance +- */ +-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ +- +-/* System IO Config */ +-#define CONFIG_SYS_SICRH 0 +-#define CONFIG_SYS_SICRL SICRL_LDP_A +- +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +-#endif +- +-/* +- * Environment Configuration +- */ +- +-#if defined(CONFIG_TSEC_ENET) +-#define CONFIG_HAS_ETH1 +-#define CONFIG_HAS_ETH0 +-#endif +- +-#define CONFIG_HOSTNAME "mpc8349emds" +-#define CONFIG_ROOTPATH "/nfsroot/rootfs" +-#define CONFIG_BOOTFILE "uImage" +- +-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ +- +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "netdev=eth0\0" \ +- "hostname=mpc8349emds\0" \ +- "nfsargs=setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=${serverip}:${rootpath}\0" \ +- "ramargs=setenv bootargs root=/dev/ram rw\0" \ +- "addip=setenv bootargs ${bootargs} " \ +- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ +- ":${hostname}:${netdev}:off panic=1\0" \ +- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ +- "flash_nfs=run nfsargs addip addtty;" \ +- "bootm ${kernel_addr}\0" \ +- "flash_self=run ramargs addip addtty;" \ +- "bootm ${kernel_addr} ${ramdisk_addr}\0" \ +- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ +- "bootm\0" \ +- "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ +- "update=protect off fe000000 fe03ffff; " \ +- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ +- "upd=run load update\0" \ +- "fdtaddr=780000\0" \ +- "fdtfile=mpc834x_mds.dtb\0" \ +- "" +- +-#define CONFIG_NFSBOOTCOMMAND \ +- "setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=$serverip:$rootpath " \ +- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ +- "$netdev:off " \ +- "console=$consoledev,$baudrate $othbootargs;" \ +- "tftp $loadaddr $bootfile;" \ +- "tftp $fdtaddr $fdtfile;" \ +- "bootm $loadaddr - $fdtaddr" +- +-#define CONFIG_RAMBOOTCOMMAND \ +- "setenv bootargs root=/dev/ram rw " \ +- "console=$consoledev,$baudrate $othbootargs;" \ +- "tftp $ramdiskaddr $ramdiskfile;" \ +- "tftp $loadaddr $bootfile;" \ +- "tftp $fdtaddr $fdtfile;" \ +- "bootm $loadaddr $ramdiskaddr $fdtaddr" +- +-#define CONFIG_BOOTCOMMAND "run flash_self" +- +-#endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/MPC8349EMDS_SDRAM.h u-boot/include/configs/MPC8349EMDS_SDRAM.h +--- u-boot-2021.10/include/configs/MPC8349EMDS_SDRAM.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC8349EMDS_SDRAM.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,426 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2006-2010 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- */ +- +-/* +- * mpc8349emds board configuration file +- * +- */ +- +-#ifndef __CONFIG_H +-#define __CONFIG_H +- +-/* +- * High Level Configuration Options +- */ +-#define CONFIG_E300 1 /* E300 Family */ +- +-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +- +-/* +- * DDR Setup +- */ +-#define CONFIG_DDR_ECC /* support DDR ECC function */ +-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +- +-/* +- * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver +- * unselect it to use old spd_sdram.c +- */ +-#define CONFIG_SYS_SPD_BUS_NUM 0 +-#define SPD_EEPROM_ADDRESS1 0x52 +-#define SPD_EEPROM_ADDRESS2 0x51 +-#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +- +-/* +- * 32-bit data path mode. +- * +- * Please note that using this mode for devices with the real density of 64-bit +- * effectively reduces the amount of available memory due to the effect of +- * wrapping around while translating address to row/columns, for example in the +- * 256MB module the upper 128MB get aliased with contents of the lower +- * 128MB); normally this define should be used for devices with real 32-bit +- * data path. +- */ +-#undef CONFIG_DDR_32BIT +- +-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ +- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +-#undef CONFIG_DDR_2T_TIMING +- +-/* +- * DDRCDR - DDR Control Driver Register +- */ +-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 +- +-#if defined(CONFIG_SPD_EEPROM) +-/* +- * Determine DDR configuration from I2C interface. +- */ +-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +-#else +-/* +- * Manually set up DDR parameters +- */ +-#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +-#if defined(CONFIG_DDR_II) +-#define CONFIG_SYS_DDRCDR 0x80080001 +-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +-#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +-#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +-#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +-#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +-#define CONFIG_SYS_DDR_MODE 0x47d00432 +-#define CONFIG_SYS_DDR_MODE2 0x8000c000 +-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +-#else +-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ +- | CSCONFIG_ROW_BIT_13 \ +- | CSCONFIG_COL_BIT_10) +-#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ +- +-#if defined(CONFIG_DDR_32BIT) +-/* set burst length to 8 for 32-bit data path */ +- /* DLL,normal,seq,4/2.5, 8 burst len */ +-#define CONFIG_SYS_DDR_MODE 0x00000023 +-#else +-/* the default burst length is 4 - for 64-bit data path */ +- /* DLL,normal,seq,4/2.5, 4 burst len */ +-#define CONFIG_SYS_DDR_MODE 0x00000022 +-#endif +-#endif +-#endif +- +-/* +- * SDRAM on the Local Bus +- */ +-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +- +-/* +- * FLASH on the Local Bus +- */ +-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ +- +-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ +- +-#undef CONFIG_SYS_FLASH_CHECKSUM +-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +- +-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +- +-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +-#define CONFIG_SYS_RAMBOOT +-#else +-#undef CONFIG_SYS_RAMBOOT +-#endif +- +-/* +- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg +- */ +-#define CONFIG_SYS_BCSR 0xE2400000 +- /* Access window base at BCSR base */ +-#define CONFIG_SYS_INIT_RAM_LOCK 1 +-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ +- +-#define CONFIG_SYS_GBL_DATA_OFFSET \ +- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +- +-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +- +-/* +- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. +- */ +- +-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +-/* +- * Base Register 2 and Option Register 2 configure SDRAM. +- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. +- * +- * For BR2, need: +- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 +- * port-size = 32-bits = BR2[19:20] = 11 +- * no parity checking = BR2[21:22] = 00 +- * SDRAM for MSEL = BR2[24:26] = 011 +- * Valid = BR[31] = 1 +- * +- * 0 4 8 12 16 20 24 28 +- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 +- */ +- +-/* +- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. +- * +- * For OR2, need: +- * 64MB mask for AM, OR2[0:7] = 1111 1100 +- * XAM, OR2[17:18] = 11 +- * 9 columns OR2[19-21] = 010 +- * 13 rows OR2[23-25] = 100 +- * EAD set for extra time OR[31] = 1 +- * +- * 0 4 8 12 16 20 24 28 +- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 +- */ +- +- +- /* LB sdram refresh timer, about 6us */ +-#define CONFIG_SYS_LBC_LSRT 0x32000000 +- /* LB refresh timer prescal, 266MHz/32 */ +-#define CONFIG_SYS_LBC_MRTPR 0x20000000 +- +-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ +- | LSDMR_BSMA1516 \ +- | LSDMR_RFCR8 \ +- | LSDMR_PRETOACT6 \ +- | LSDMR_ACTTORW3 \ +- | LSDMR_BL8 \ +- | LSDMR_WRC3 \ +- | LSDMR_CL3) +- +-/* +- * SDRAM Controller configuration sequence. +- */ +-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) +- +-/* +- * Serial Port +- */ +-#define CONFIG_SYS_NS16550_SERIAL +-#define CONFIG_SYS_NS16550_REG_SIZE 1 +-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +- +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +- +-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +- +-/* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +- +-/* SPI */ +-#undef CONFIG_SOFT_SPI /* SPI bit-banged */ +- +-/* GPIOs. Used as SPI chip selects */ +-#define CONFIG_SYS_GPIO1_PRELIM +-#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +-#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ +- +-/* TSEC */ +-#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +-#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) +- +-/* USB */ +-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ +- +-/* +- * General PCI +- * Addresses are mapped 1-1. +- */ +-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +- +-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ +- +-#if defined(CONFIG_PCI) +- +-#define CONFIG_83XX_PCI_STREAMING +- +- +-#if !defined(CONFIG_PCI_PNP) +- #define PCI_ENET0_IOADDR 0xFIXME +- #define PCI_ENET0_MEMADDR 0xFIXME +- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +-#endif +- +-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +- +-#endif /* CONFIG_PCI */ +- +-/* +- * TSEC configuration +- */ +- +-#if defined(CONFIG_TSEC_ENET) +- +-#define CONFIG_GMII 1 /* MII PHY management */ +-#define CONFIG_TSEC1 1 +-#define CONFIG_TSEC1_NAME "TSEC0" +-#define CONFIG_TSEC2 1 +-#define CONFIG_TSEC2_NAME "TSEC1" +-#define TSEC1_PHY_ADDR 0 +-#define TSEC2_PHY_ADDR 1 +-#define TSEC1_PHYIDX 0 +-#define TSEC2_PHYIDX 0 +-#define TSEC1_FLAGS TSEC_GIGABIT +-#define TSEC2_FLAGS TSEC_GIGABIT +- +-/* Options are: TSEC[0-1] */ +-#define CONFIG_ETHPRIME "TSEC0" +- +-#endif /* CONFIG_TSEC_ENET */ +- +-/* +- * Configure on-board RTC +- */ +-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +- +-/* +- * Environment +- */ +-#ifndef CONFIG_SYS_RAMBOOT +-/* Address and size of Redundant Environment Sector */ +-#endif +- +-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +- +-/* +- * BOOTP options +- */ +-#define CONFIG_BOOTP_BOOTFILESIZE +- +-#undef CONFIG_WATCHDOG /* watchdog disabled */ +- +-/* +- * Miscellaneous configurable options +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +- +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 256 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +- /* Initial Memory map for Linux*/ +-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +- +-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ +- +-/* +- * System performance +- */ +-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ +- +-/* System IO Config */ +-#define CONFIG_SYS_SICRH 0 +-#define CONFIG_SYS_SICRL SICRL_LDP_A +- +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +-#endif +- +-/* +- * Environment Configuration +- */ +- +-#if defined(CONFIG_TSEC_ENET) +-#define CONFIG_HAS_ETH1 +-#define CONFIG_HAS_ETH0 +-#endif +- +-#define CONFIG_HOSTNAME "mpc8349emds" +-#define CONFIG_ROOTPATH "/nfsroot/rootfs" +-#define CONFIG_BOOTFILE "uImage" +- +-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ +- +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "netdev=eth0\0" \ +- "hostname=mpc8349emds\0" \ +- "nfsargs=setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=${serverip}:${rootpath}\0" \ +- "ramargs=setenv bootargs root=/dev/ram rw\0" \ +- "addip=setenv bootargs ${bootargs} " \ +- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ +- ":${hostname}:${netdev}:off panic=1\0" \ +- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ +- "flash_nfs=run nfsargs addip addtty;" \ +- "bootm ${kernel_addr}\0" \ +- "flash_self=run ramargs addip addtty;" \ +- "bootm ${kernel_addr} ${ramdisk_addr}\0" \ +- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ +- "bootm\0" \ +- "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ +- "update=protect off fe000000 fe03ffff; " \ +- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ +- "upd=run load update\0" \ +- "fdtaddr=780000\0" \ +- "fdtfile=mpc834x_mds.dtb\0" \ +- "" +- +-#define CONFIG_NFSBOOTCOMMAND \ +- "setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=$serverip:$rootpath " \ +- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ +- "$netdev:off " \ +- "console=$consoledev,$baudrate $othbootargs;" \ +- "tftp $loadaddr $bootfile;" \ +- "tftp $fdtaddr $fdtfile;" \ +- "bootm $loadaddr - $fdtaddr" +- +-#define CONFIG_RAMBOOTCOMMAND \ +- "setenv bootargs root=/dev/ram rw " \ +- "console=$consoledev,$baudrate $othbootargs;" \ +- "tftp $ramdiskaddr $ramdiskfile;" \ +- "tftp $loadaddr $bootfile;" \ +- "tftp $fdtaddr $fdtfile;" \ +- "bootm $loadaddr $ramdiskaddr $fdtaddr" +- +-#define CONFIG_BOOTCOMMAND "run flash_self" +- +-#endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/MPC837XERDB.h u-boot/include/configs/MPC837XERDB.h +--- u-boot-2021.10/include/configs/MPC837XERDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC837XERDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -66,9 +66,6 @@ + + #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) + +-#undef CONFIG_DDR_ECC /* support DDR ECC function */ +-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +- + #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + + /* +@@ -113,17 +110,9 @@ + | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x06090100 */ + +-#if defined(CONFIG_DDR_2T_TIMING) +-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ +- | SDRAM_CFG_SDRAM_TYPE_DDR2 \ +- | SDRAM_CFG_32_BE \ +- | SDRAM_CFG_2T_EN) +- /* 0x43088000 */ +-#else + #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2) + /* 0x43000000 */ +-#endif + #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ + #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0442 << SDRAM_MODE_SD_SHIFT)) +@@ -147,7 +136,6 @@ + #endif + + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + + /* + * Initial RAM Base Address Setup +@@ -203,11 +191,6 @@ + #define CONFIG_FSL_SERDES2 0xe3100 + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } + + /* +@@ -329,7 +312,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -339,10 +321,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -361,9 +339,6 @@ + #define CONFIG_UBOOTPATH "u-boot.bin" + #define CONFIG_FDTFILE "mpc8379_rdb.dtb" + +- /* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 800000 +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ +@@ -390,7 +365,7 @@ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ +@@ -398,7 +373,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +diff -ruN u-boot-2021.10/include/configs/MPC8540ADS.h u-boot/include/configs/MPC8540ADS.h +--- u-boot-2021.10/include/configs/MPC8540ADS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC8540ADS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -61,7 +61,6 @@ + + /* DDR Setup */ + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +-#define CONFIG_DDR_SPD + + #define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +@@ -189,7 +188,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL +@@ -205,11 +203,6 @@ + /* + * I2C + */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + + /* RapidIO MMU */ +@@ -286,7 +279,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -296,10 +288,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -321,8 +309,6 @@ + #define CONFIG_GATEWAYIP 192.168.1.1 + #define CONFIG_NETMASK 255.255.255.0 + +-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ +@@ -331,7 +317,7 @@ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -340,7 +326,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -348,6 +334,6 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/MPC8548CDS.h u-boot/include/configs/MPC8548CDS.h +--- u-boot-2021.10/include/configs/MPC8548CDS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC8548CDS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -45,10 +45,7 @@ + + /* DDR Setup */ + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +-#define CONFIG_DDR_SPD + +-#define CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + #define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +@@ -278,7 +275,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL +@@ -295,23 +291,13 @@ + * I2C + */ + #if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + #else + #define CONFIG_SYS_SPD_BUS_NUM 0 +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 + #endif +-#define CONFIG_SYS_I2C_FSL + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_CCID +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * General PCI +@@ -420,7 +406,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -430,10 +415,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -455,8 +436,6 @@ + #define CONFIG_GATEWAYIP 192.168.1.1 + #define CONFIG_NETMASK 255.255.255.0 + +-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=off\0" \ + "netdev=eth0\0" \ +@@ -478,7 +457,7 @@ + "fdtaddr=1e00000\0" \ + "fdtfile=mpc8548cds.dtb\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -487,7 +466,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -495,6 +474,6 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/MPC8560ADS.h u-boot/include/configs/MPC8560ADS.h +--- u-boot-2021.10/include/configs/MPC8560ADS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/MPC8560ADS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -28,7 +28,6 @@ + */ + + #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ + #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + + /* +@@ -62,7 +61,6 @@ + + /* DDR Setup */ + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +-#define CONFIG_DDR_SPD + + #define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +@@ -190,7 +188,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + + /* Serial Port */ + #define CONFIG_CONS_ON_SCC /* define if console on SCC */ +@@ -202,11 +199,6 @@ + /* + * I2C + */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + + /* RapidIO MMU */ +@@ -258,50 +250,6 @@ + + #endif /* CONFIG_TSEC_ENET */ + +-#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ +- +-#undef CONFIG_ETHER_NONE /* define if ether on something else */ +-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ +- +-#if (CONFIG_ETHER_INDEX == 2) +- /* +- * - Rx-CLK is CLK13 +- * - Tx-CLK is CLK14 +- * - Select bus for bd/buffers +- * - Full duplex +- */ +- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +- #define CONFIG_SYS_CPMFCR_RAMTYPE 0 +- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) +- #define FETH2_RST 0x01 +-#elif (CONFIG_ETHER_INDEX == 3) +- /* need more definitions here for FE3 */ +- #define FETH3_RST 0x80 +-#endif /* CONFIG_ETHER_INDEX */ +- +-/* +- * GPIO pins used for bit-banged MII communications +- */ +-#define MDIO_PORT 2 /* Port C */ +-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ +- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +-#define MDC_DECLARE MDIO_DECLARE +- +-#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +-#define MDIO_READ ((iop->pdat & 0x00400000) != 0) +- +-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ +- else iop->pdat &= ~0x00400000 +- +-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ +- else iop->pdat &= ~0x00200000 +- +-#define MIIDELAY udelay(1) +- +-#endif +- + /* + * Environment + */ +@@ -319,7 +267,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ + + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +@@ -331,14 +278,10 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) ++#if defined(CONFIG_TSEC_ENET) + #define CONFIG_HAS_ETH0 + #define CONFIG_HAS_ETH1 + #define CONFIG_HAS_ETH2 +@@ -355,8 +298,6 @@ + #define CONFIG_GATEWAYIP 192.168.1.1 + #define CONFIG_NETMASK 255.255.255.0 + +-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyCPM\0" \ +@@ -365,7 +306,7 @@ + "fdtaddr=400000\0" \ + "fdtfile=mpc8560ads.dtb\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -374,7 +315,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -382,6 +323,6 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/mt7620.h u-boot/include/configs/mt7620.h +--- u-boot-2021.10/include/configs/mt7620.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt7620.h 2021-11-01 17:10:14.592907771 +0100 +@@ -13,11 +13,9 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x100000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 +-#define CONFIG_SYS_LOAD_ADDR 0x80010000 + + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +@@ -26,13 +24,7 @@ + #define CONFIG_SYS_MAXARGS 16 + #define CONFIG_SYS_CBSIZE 1024 + +-/* Serial common */ +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +- + /* SPL */ +-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SPL_BSS_START_ADDR 0x80010000 +diff -ruN u-boot-2021.10/include/configs/mt7622.h u-boot/include/configs/mt7622.h +--- u-boot-2021.10/include/configs/mt7622.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt7622.h 2021-11-01 17:10:14.592907771 +0100 +@@ -16,8 +16,6 @@ + #define CONFIG_SYS_CBSIZE SZ_1K + #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_4M + #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + + /* Uboot definition */ +@@ -27,10 +25,6 @@ + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) +-/* UBoot -> Kernel */ +-#define CONFIG_LOADADDR 0x4007ff28 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* DRAM */ + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + +diff -ruN u-boot-2021.10/include/configs/mt7623.h u-boot/include/configs/mt7623.h +--- u-boot-2021.10/include/configs/mt7623.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt7623.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,9 +12,6 @@ + #include <linux/sizes.h> + + /* Miscellaneous configurable options */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_CMDLINE_TAG + + #define CONFIG_SYS_MAXARGS 8 + #define CONFIG_SYS_BOOTM_LEN SZ_64M +@@ -22,8 +19,6 @@ + #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_4M + #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + + /* Environment */ +@@ -32,10 +27,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +-/* UBoot -> Kernel */ +-#define CONFIG_LOADADDR 0x84000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* MMC */ + #define MMC_SUPPORTS_TUNING + +diff -ruN u-boot-2021.10/include/configs/mt7628.h u-boot/include/configs/mt7628.h +--- u-boot-2021.10/include/configs/mt7628.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt7628.h 2021-11-01 17:10:14.592907771 +0100 +@@ -13,11 +13,9 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x100000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 +-#define CONFIG_SYS_LOAD_ADDR 0x80010000 + + #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 + +@@ -27,7 +25,7 @@ + #define CONFIG_SYS_CBSIZE 1024 + + /* Serial SPL */ +-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) ++#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) + #define CONFIG_SYS_NS16550_MEM32 + #define CONFIG_SYS_NS16550_CLK 40000000 + #define CONFIG_SYS_NS16550_REG_SIZE -4 +@@ -39,9 +37,6 @@ + 230400, 460800, 921600 } + + /* SPL */ +-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SPL_BSS_START_ADDR 0x80010000 +diff -ruN u-boot-2021.10/include/configs/mt7629.h u-boot/include/configs/mt7629.h +--- u-boot-2021.10/include/configs/mt7629.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt7629.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,9 +12,6 @@ + #include <linux/sizes.h> + + /* Miscellaneous configurable options */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_CMDLINE_TAG + + #define CONFIG_SYS_MAXARGS 8 + #define CONFIG_SYS_BOOTM_LEN SZ_64M +@@ -22,8 +19,6 @@ + #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_4M + #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + + /* Environment */ +@@ -43,8 +38,6 @@ + + /* UBoot -> Kernel */ + #define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 +-#define CONFIG_LOADADDR 0x42007f1c +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* DRAM */ + #define CONFIG_SYS_SDRAM_BASE 0x40000000 +diff -ruN u-boot-2021.10/include/configs/mt8183.h u-boot/include/configs/mt8183.h +--- u-boot-2021.10/include/configs/mt8183.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt8183.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,9 +11,6 @@ + + #include <linux/sizes.h> + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_MALLOC_LEN SZ_4M +- + #define CONFIG_CPU_ARMV8 + #define COUNTER_FREQUENCY 13000000 + +diff -ruN u-boot-2021.10/include/configs/mt8512.h u-boot/include/configs/mt8512.h +--- u-boot-2021.10/include/configs/mt8512.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt8512.h 2021-11-01 17:10:14.592907771 +0100 +@@ -17,10 +17,6 @@ + + #define COUNTER_FREQUENCY 13000000 + +-#define CONFIG_SYS_LOAD_ADDR 0x41000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +- +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + /* Uboot definition */ +diff -ruN u-boot-2021.10/include/configs/mt8516.h u-boot/include/configs/mt8516.h +--- u-boot-2021.10/include/configs/mt8516.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt8516.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,9 +11,6 @@ + + #include <linux/sizes.h> + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_MALLOC_LEN SZ_4M +- + #define CONFIG_CPU_ARMV8 + #define COUNTER_FREQUENCY 13000000 + +diff -ruN u-boot-2021.10/include/configs/mt8518.h u-boot/include/configs/mt8518.h +--- u-boot-2021.10/include/configs/mt8518.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mt8518.h 2021-11-01 17:10:14.592907771 +0100 +@@ -21,10 +21,6 @@ + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +-#define CONFIG_SYS_LOAD_ADDR 0x41000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +- +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + /* Uboot definition */ +diff -ruN u-boot-2021.10/include/configs/mv-common.h u-boot/include/configs/mv-common.h +--- u-boot-2021.10/include/configs/mv-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mv-common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -50,26 +50,11 @@ + + /* auto boot */ + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ +- + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + + /* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ +- +-/* + * Other required minimal configurations + */ +-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +diff -ruN u-boot-2021.10/include/configs/mvebu_armada-37xx.h u-boot/include/configs/mvebu_armada-37xx.h +--- u-boot-2021.10/include/configs/mvebu_armada-37xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mvebu_armada-37xx.h 2021-11-01 17:10:14.592907771 +0100 +@@ -25,26 +25,11 @@ + 4000000, 4500000, 5000000, 5500000, \ + 6000000 } + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ +- + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + + /* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ +- +-/* + * Other required minimal configurations + */ +-#define CONFIG_SYS_LOAD_ADDR 0x06000000 /* default load adr */ + #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +@@ -55,7 +40,6 @@ + * I2C + */ + #define CONFIG_I2C_MV +-#define CONFIG_SYS_I2C_SLAVE 0x0 + + /* + * Environment +diff -ruN u-boot-2021.10/include/configs/mvebu_armada-8k.h u-boot/include/configs/mvebu_armada-8k.h +--- u-boot-2021.10/include/configs/mvebu_armada-8k.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mvebu_armada-8k.h 2021-11-01 17:10:14.592907771 +0100 +@@ -19,26 +19,11 @@ + #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ +- + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + + /* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ +- +-/* + * Other required minimal configurations + */ +-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +@@ -48,8 +33,6 @@ + /* When runtime detection fails this is the default */ + + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* + * Ethernet Driver configuration +diff -ruN u-boot-2021.10/include/configs/mv-plug-common.h u-boot/include/configs/mv-plug-common.h +--- u-boot-2021.10/include/configs/mv-plug-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mv-plug-common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,7 +11,6 @@ + * High Level Configuration Options (easy to change) + */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + /* + * mv-common.h should be defined after CMD configs since it used them +diff -ruN u-boot-2021.10/include/configs/mx23evk.h u-boot/include/configs/mx23evk.h +--- u-boot-2021.10/include/configs/mx23evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx23evk.h 2021-11-01 17:10:14.592907771 +0100 +@@ -8,9 +8,6 @@ + #ifndef __CONFIGS_MX23EVK_H__ + #define __CONFIGS_MX23EVK_H__ + +-/* System configurations */ +-#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK +- + /* U-Boot Commands */ + + /* Memory configuration */ +@@ -36,8 +33,6 @@ + + /* Boot Linux */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR 0x42000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Extra Environments */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/mx23_olinuxino.h u-boot/include/configs/mx23_olinuxino.h +--- u-boot-2021.10/include/configs/mx23_olinuxino.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx23_olinuxino.h 2021-11-01 17:10:14.592907771 +0100 +@@ -5,9 +5,6 @@ + #ifndef __CONFIGS_MX23_OLINUXINO_H__ + #define __CONFIGS_MX23_OLINUXINO_H__ + +-/* System configurations */ +-#define CONFIG_MACH_TYPE 4105 +- + /* U-Boot Commands */ + + /* Memory configuration */ +@@ -27,8 +24,6 @@ + + /* Booting Linux */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR 0x42000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Extra Environment */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/mx28evk.h u-boot/include/configs/mx28evk.h +--- u-boot-2021.10/include/configs/mx28evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx28evk.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,9 +10,6 @@ + #ifndef __CONFIGS_MX28EVK_H__ + #define __CONFIGS_MX28EVK_H__ + +-/* System configurations */ +-#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK +- + /* Memory configuration */ + #define PHYS_SDRAM_1 0x40000000 /* Base address */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ +@@ -50,8 +47,6 @@ + + /* Boot Linux */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR 0x42000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Extra Environment */ + #define CONFIG_EXTRA_ENV_SETTINGS \ +diff -ruN u-boot-2021.10/include/configs/mx51evk.h u-boot/include/configs/mx51evk.h +--- u-boot-2021.10/include/configs/mx51evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx51evk.h 2021-11-01 17:10:14.592907771 +0100 +@@ -16,17 +16,6 @@ + + #include <asm/arch/imx-regs.h> + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +- + /* + * Hardware drivers + */ +@@ -35,7 +24,6 @@ + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* PMIC Controller */ +-#define CONFIG_POWER + #define CONFIG_POWER_SPI + #define CONFIG_POWER_FSL + #define CONFIG_FSL_PMIC_BUS 0 +@@ -61,8 +49,6 @@ + + #define CONFIG_ETHPRIME "FEC0" + +-#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ +@@ -140,8 +126,6 @@ + * Miscellaneous configurable options + */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /*----------------------------------------------------------------------- + * Physical Memory Map + */ +diff -ruN u-boot-2021.10/include/configs/mx53cx9020.h u-boot/include/configs/mx53cx9020.h +--- u-boot-2021.10/include/configs/mx53cx9020.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx53cx9020.h 2021-11-01 17:10:14.592907771 +0100 +@@ -14,17 +14,8 @@ + + #include <asm/arch/imx-regs.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + #define CONFIG_SYS_FSL_CLK + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- +-#define CONFIG_REVISION_TAG +- + #define CONFIG_MXC_UART_BASE UART2_BASE + + #define CONFIG_FPGA_COUNT 1 +@@ -43,8 +34,6 @@ + + /* Command definition */ + +-#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ +@@ -72,8 +61,6 @@ + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical Memory Map */ + #define PHYS_SDRAM_1 CSD0_BASE_ADDR + #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +diff -ruN u-boot-2021.10/include/configs/mx53loco.h u-boot/include/configs/mx53loco.h +--- u-boot-2021.10/include/configs/mx53loco.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx53loco.h 2021-11-01 17:10:14.592907771 +0100 +@@ -9,21 +9,10 @@ + #ifndef __CONFIG_H + #define __CONFIG_H + +-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO +- + #include <asm/arch/imx-regs.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + #define CONFIG_SYS_FSL_CLK + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +- +-#define CONFIG_REVISION_TAG +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ +@@ -35,16 +24,7 @@ + #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + #define CONFIG_MXC_USB_FLAGS 0 + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +- + /* PMIC Controller */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_DIALOG_POWER + #define CONFIG_POWER_FSL + #define CONFIG_POWER_FSL_MC13892 +@@ -56,8 +36,6 @@ + + #define CONFIG_ETHPRIME "FEC0" + +-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ +@@ -132,8 +110,6 @@ + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical Memory Map */ + #define PHYS_SDRAM_1 CSD0_BASE_ADDR + #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +diff -ruN u-boot-2021.10/include/configs/mx53ppd.h u-boot/include/configs/mx53ppd.h +--- u-boot-2021.10/include/configs/mx53ppd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx53ppd.h 2021-11-01 17:10:14.592907771 +0100 +@@ -11,17 +11,8 @@ + + #include <asm/arch/imx-regs.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + #define CONFIG_SYS_FSL_CLK + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +- +-#define CONFIG_REVISION_TAG +- + /* USB Configs */ + #define CONFIG_USB_HOST_ETHER + #define CONFIG_USB_ETHER_ASIX +@@ -33,8 +24,6 @@ + + /* Command definition */ + +-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ +- + #define PPD_CONFIG_NFS \ + "nfsserver=192.168.252.95\0" \ + "gatewayip=192.168.252.95\0" \ +@@ -102,11 +91,11 @@ + "video-mode=" \ + "lcd:800x480-24@60,monitor=lcd\0" \ + +-#define CONFIG_MMCBOOTCOMMAND \ ++#define MMCBOOTCOMMAND \ + "run doquiet; " \ + "run tryboot; " \ + +-#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND + + #define CONFIG_ARP_TIMEOUT 200UL + +@@ -116,8 +105,6 @@ + #define CONFIG_SYS_MAXARGS 48 /* max number of command args */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/mx6_common.h u-boot/include/configs/mx6_common.h +--- u-boot-2021.10/include/configs/mx6_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -33,22 +33,6 @@ + + #define CONFIG_SYS_FSL_CLK + +-/* ATAGs */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* Boot options */ +-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ +- defined(CONFIG_MX6SX) || \ +- defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) +-#define CONFIG_LOADADDR 0x82000000 +-#else +-#define CONFIG_LOADADDR 0x12000000 +-#endif +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 512 + #define CONFIG_SYS_MAXARGS 32 +diff -ruN u-boot-2021.10/include/configs/mx6cuboxi.h u-boot/include/configs/mx6cuboxi.h +--- u-boot-2021.10/include/configs/mx6cuboxi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6cuboxi.h 2021-11-01 17:10:14.592907771 +0100 +@@ -13,8 +13,6 @@ + + #include "imx6_spl.h" + +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +@@ -46,9 +44,9 @@ + "fdtfile=undefined\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "initrd_high=0xffffffff\0" \ +diff -ruN u-boot-2021.10/include/configs/mx6memcal.h u-boot/include/configs/mx6memcal.h +--- u-boot-2021.10/include/configs/mx6memcal.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6memcal.h 2021-11-01 17:10:14.592907771 +0100 +@@ -13,8 +13,6 @@ + #include "mx6_common.h" + #include "imx6_spl.h" + +-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +- + #ifdef CONFIG_SERIAL_CONSOLE_UART1 + #if defined(CONFIG_MX6SL) + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +diff -ruN u-boot-2021.10/include/configs/mx6sabreauto.h u-boot/include/configs/mx6sabreauto.h +--- u-boot-2021.10/include/configs/mx6sabreauto.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sabreauto.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,7 +12,6 @@ + #include "imx6_spl.h" + #endif + +-#define CONFIG_MACH_TYPE 3529 + #define CONFIG_MXC_UART_BASE UART4_BASE + #define CONSOLE_DEV "ttymxc3" + +@@ -50,25 +49,13 @@ + + #define CONFIG_SYS_FSL_USDHC_NUM 2 + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* NAND stuff */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +diff -ruN u-boot-2021.10/include/configs/mx6sabre_common.h u-boot/include/configs/mx6sabre_common.h +--- u-boot-2021.10/include/configs/mx6sabre_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sabre_common.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,9 +12,6 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +@@ -52,7 +49,7 @@ + "dfu_alt_info=spl raw 0x400\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ +diff -ruN u-boot-2021.10/include/configs/mx6sabresd.h u-boot/include/configs/mx6sabresd.h +--- u-boot-2021.10/include/configs/mx6sabresd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sabresd.h 2021-11-01 17:10:14.592907771 +0100 +@@ -12,7 +12,6 @@ + #include "imx6_spl.h" + #endif + +-#define CONFIG_MACH_TYPE 3980 + #define CONFIG_MXC_UART_BASE UART1_BASE + #define CONSOLE_DEV "ttymxc0" + +@@ -37,17 +36,7 @@ + #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) + #endif + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +diff -ruN u-boot-2021.10/include/configs/mx6slevk.h u-boot/include/configs/mx6slevk.h +--- u-boot-2021.10/include/configs/mx6slevk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6slevk.h 2021-11-01 17:10:14.592907771 +0100 +@@ -14,23 +14,11 @@ + #include "imx6_spl.h" + #endif + +-#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ +diff -ruN u-boot-2021.10/include/configs/mx6sllevk.h u-boot/include/configs/mx6sllevk.h +--- u-boot-2021.10/include/configs/mx6sllevk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sllevk.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,20 +10,8 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + +-/* I2C Configs */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ + "script=boot.scr\0" \ +diff -ruN u-boot-2021.10/include/configs/mx6sxsabreauto.h u-boot/include/configs/mx6sxsabreauto.h +--- u-boot-2021.10/include/configs/mx6sxsabreauto.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sxsabreauto.h 2021-11-01 17:10:14.592907771 +0100 +@@ -10,9 +10,6 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -106,18 +103,9 @@ + /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* NAND stuff */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + +diff -ruN u-boot-2021.10/include/configs/mx6sxsabresd.h u-boot/include/configs/mx6sxsabresd.h +--- u-boot-2021.10/include/configs/mx6sxsabresd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6sxsabresd.h 2021-11-01 17:10:14.596240922 +0100 +@@ -16,9 +16,6 @@ + #include "imx6_spl.h" + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + #ifdef CONFIG_IMX_BOOTAUX +@@ -140,13 +137,6 @@ + /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* Network */ + #define CONFIG_FEC_MXC + +diff -ruN u-boot-2021.10/include/configs/mx6ul_14x14_evk.h u-boot/include/configs/mx6ul_14x14_evk.h +--- u-boot-2021.10/include/configs/mx6ul_14x14_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6ul_14x14_evk.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,9 +18,6 @@ + /* SPL options */ + #include "imx6_spl.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ +@@ -36,14 +33,6 @@ + + #endif + +-/* I2C configs */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif +- + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -56,7 +45,7 @@ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ +@@ -135,7 +124,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/mx6ullevk.h u-boot/include/configs/mx6ullevk.h +--- u-boot-2021.10/include/configs/mx6ullevk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx6ullevk.h 2021-11-01 17:10:14.596240922 +0100 +@@ -16,9 +16,6 @@ + + #define PHYS_SDRAM_SIZE SZ_512M + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ +@@ -33,14 +30,6 @@ + #endif + #endif + +-/* I2C configs */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif +- + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -132,7 +121,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/mx7_common.h u-boot/include/configs/mx7_common.h +--- u-boot-2021.10/include/configs/mx7_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx7_common.h 2021-11-01 17:10:14.596240922 +0100 +@@ -28,8 +28,6 @@ + /* Enable iomux-lpsr support */ + #define CONFIG_IOMUX_LPSR + +-#define CONFIG_LOADADDR 0x80800000 +- + /* Miscellaneous configurable options */ + #define CONFIG_SYS_CBSIZE 512 + #define CONFIG_SYS_MAXARGS 32 +@@ -49,10 +47,5 @@ + * launched by OPTEE, because of that we shall skip all the low level + * initialization since it was already done by ATF or OPTEE + */ +-#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) +-#ifndef CONFIG_OPTEE +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +-#endif + + #endif +diff -ruN u-boot-2021.10/include/configs/mx7dsabresd.h u-boot/include/configs/mx7dsabresd.h +--- u-boot-2021.10/include/configs/mx7dsabresd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx7dsabresd.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,16 +14,9 @@ + + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + /* MMC Config*/ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + #ifdef CONFIG_IMX_BOOTAUX +@@ -79,11 +72,11 @@ + "fdtfile=imx7d-sdb.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x83100000\0" \ + "ramdiskaddr=0x83100000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + BOOTENV + +@@ -94,7 +87,6 @@ + + #include <config_distro_bootcmd.h> + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -119,8 +111,6 @@ + /* NAND stuff */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + #endif +diff -ruN u-boot-2021.10/include/configs/mx7ulp_com.h u-boot/include/configs/mx7ulp_com.h +--- u-boot-2021.10/include/configs/mx7ulp_com.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx7ulp_com.h 2021-11-01 17:10:14.596240922 +0100 +@@ -32,13 +32,6 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ + +-#define CONFIG_INITRD_TAG +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) +- + /* UART */ + #define LPUART_BASE LPUART4_RBASE + +@@ -47,8 +40,6 @@ + #define PHYS_SDRAM 0x60000000 + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +-#define CONFIG_LOADADDR 0x60800000 +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "console=ttyLP0\0" \ +@@ -74,8 +65,6 @@ + "run mmcboot; " \ + "fi; " \ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +diff -ruN u-boot-2021.10/include/configs/mx7ulp_evk.h u-boot/include/configs/mx7ulp_evk.h +--- u-boot-2021.10/include/configs/mx7ulp_evk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mx7ulp_evk.h 2021-11-01 17:10:14.596240922 +0100 +@@ -22,19 +22,9 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +-#define CONFIG_INITRD_TAG +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-/*#define CONFIG_REVISION_TAG*/ +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) +- + /* UART */ + #define LPUART_BASE LPUART4_RBASE + +-#define CONFIG_SYS_CACHELINE_SIZE 64 +- + /* Miscellaneous configurable options */ + #define CONFIG_SYS_PROMPT "=> " + #define CONFIG_SYS_CBSIZE 512 +@@ -47,8 +37,6 @@ + #define PHYS_SDRAM_SIZE SZ_1G + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +-#define CONFIG_LOADADDR 0x60800000 +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ +@@ -125,7 +113,6 @@ + "fi" + + #define CONFIG_SYS_HZ 1000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +diff -ruN u-boot-2021.10/include/configs/mxs.h u-boot/include/configs/mxs.h +--- u-boot-2021.10/include/configs/mxs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mxs.h 2021-11-01 17:10:14.596240922 +0100 +@@ -50,7 +50,6 @@ + #endif + + /* Memory sizes */ +-#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ + + /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ + #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +@@ -85,10 +84,6 @@ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ + +-/* Booting Linux */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +- + /* + * Drivers + */ +@@ -119,7 +114,6 @@ + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x60000000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + #endif + + /* OCOTP */ +diff -ruN u-boot-2021.10/include/configs/mys_6ulx.h u-boot/include/configs/mys_6ulx.h +--- u-boot-2021.10/include/configs/mys_6ulx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/mys_6ulx.h 2021-11-01 17:10:14.596240922 +0100 +@@ -15,16 +15,12 @@ + + #define CONFIG_SYS_FSL_USDHC_NUM 1 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + /* Console configs */ + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/nas220.h u-boot/include/configs/nas220.h +--- u-boot-2021.10/include/configs/nas220.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nas220.h 2021-11-01 17:10:14.596240922 +0100 +@@ -12,16 +12,10 @@ + #define _CONFIG_NAS220_H + + /* +- * Machine type ID +- */ +-#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS +- +-/* + * High Level Configuration Options (easy to change) + */ + #define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ + #define CONFIG_KW88F6192 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + /* power-on led, regulator, sata0, sata1 */ + #define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) +@@ -87,4 +81,3 @@ + #define CONFIG_KIRKWOOD_GPIO + + #endif /* _CONFIG_NAS220_H */ +- +diff -ruN u-boot-2021.10/include/configs/netgear_cg3100d.h u-boot/include/configs/netgear_cg3100d.h +--- u-boot-2021.10/include/configs/netgear_cg3100d.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/netgear_cg3100d.h 2021-11-01 17:10:14.596240922 +0100 +@@ -5,4 +5,3 @@ + + #include <configs/bmips_common.h> + #include <configs/bmips_bcm3380.h> +- +diff -ruN u-boot-2021.10/include/configs/netgear_dgnd3700v2.h u-boot/include/configs/netgear_dgnd3700v2.h +--- u-boot-2021.10/include/configs/netgear_dgnd3700v2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/netgear_dgnd3700v2.h 2021-11-01 17:10:14.596240922 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6362.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/nitrogen6x.h u-boot/include/configs/nitrogen6x.h +--- u-boot-2021.10/include/configs/nitrogen6x.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nitrogen6x.h 2021-11-01 17:10:14.596240922 +0100 +@@ -11,22 +11,11 @@ + + #include "mx6_common.h" + +-#define CONFIG_MACH_TYPE 3769 +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +- + #define CONFIG_USBD_HS + + #define CONFIG_MXC_UART_BASE UART2_BASE + + /* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_I2C_EDID + + /* MMC Configs */ +@@ -90,14 +79,6 @@ + #define DISTRO_BOOT_DEV_DHCP(func) + #endif + +- +-#if defined(CONFIG_SABRELITE) +-#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" +-#else +-/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ +-#define FDTFILE +-#endif +- + #define BOOT_TARGET_DEVICES(func) \ + DISTRO_BOOT_DEV_MMC(func) \ + DISTRO_BOOT_DEV_SATA(func) \ +@@ -113,10 +94,10 @@ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ +- FDTFILE \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "ip_dyn=yes\0" \ +diff -ruN u-boot-2021.10/include/configs/nokia_rx51.h u-boot/include/configs/nokia_rx51.h +--- u-boot-2021.10/include/configs/nokia_rx51.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nokia_rx51.h 2021-11-01 17:10:14.596240922 +0100 +@@ -23,8 +23,6 @@ + */ + #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ + +-#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 +- + #include <asm/arch/cpu.h> /* get chip and board defs */ + #include <asm/arch/omap.h> + #include <asm/arch/mem.h> +@@ -34,19 +32,7 @@ + #define V_OSCK 26000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK >> 1) + +-#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ +- +-#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ +-#define CONFIG_INITRD_TAG /* enable passing initrd */ +-#define CONFIG_REVISION_TAG /* enable passing revision tag*/ +-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ +- +-/* +- * Size of malloc() pool +- */ + #define CONFIG_UBI_SIZE (512 << 10) +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ +- (128 << 10)) + + /* + * Hardware drivers +@@ -188,9 +174,6 @@ + "run attachboot;" \ + "echo" + +-/* default load address */ +-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) +- + /* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). +diff -ruN u-boot-2021.10/include/configs/novena.h u-boot/include/configs/novena.h +--- u-boot-2021.10/include/configs/novena.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/novena.h 2021-11-01 17:10:14.596240922 +0100 +@@ -41,8 +41,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +- + /* SPL */ + #include "imx6_spl.h" /* common IMX6 SPL configuration */ + +@@ -52,20 +50,10 @@ + #endif + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + #define CONFIG_I2C_MULTI_BUS +-#define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_SPD_BUS_NUM 0 + + /* I2C EEPROM */ +-#ifdef CONFIG_CMD_EEPROM +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +-#define CONFIG_SYS_I2C_EEPROM_BUS 2 +-#endif + + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +@@ -80,8 +68,6 @@ + #endif + + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +@@ -115,10 +101,10 @@ + "bootdev=/dev/mmcblk0p1\0" \ + "rootdev=/dev/mmcblk0p2\0" \ + "netdev=eth0\0" \ +- "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ +- "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ +- "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ +- "ramdisk_addr_r=0x28000000\0" \ ++ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ ++ "pxefile_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ ++ "scriptaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ ++ "ramdisk_addr_r=0x28000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdtfile=imx6q-novena.dtb\0" \ + "stdout=serial,vidconsole\0" \ +diff -ruN u-boot-2021.10/include/configs/npi_imx6ull.h u-boot/include/configs/npi_imx6ull.h +--- u-boot-2021.10/include/configs/npi_imx6ull.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/npi_imx6ull.h 2021-11-01 17:10:14.596240922 +0100 +@@ -15,9 +15,6 @@ + + #define CONFIG_SYS_FSL_USDHC_NUM 1 + +-/* Size of malloc() poll */ +-#define CONFIG_SYS_MALLOC_LEN SZ_2M +- + /* Console configs */ + #define CONFIG_MXC_UART_BASE UART1_BASE + +@@ -26,7 +23,6 @@ + + #define CONFIG_NETMASK 255.255.255.0 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/nsa310s.h u-boot/include/configs/nsa310s.h +--- u-boot-2021.10/include/configs/nsa310s.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nsa310s.h 2021-11-01 17:10:14.596240922 +0100 +@@ -13,7 +13,6 @@ + #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6192 1 /* SOC Name */ + #define CONFIG_KW88F6702 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/nsim.h u-boot/include/configs/nsim.h +--- u-boot-2021.10/include/configs/nsim.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nsim.h 2021-11-01 17:10:14.596240922 +0100 +@@ -20,15 +20,12 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + #define CONFIG_SYS_BOOTM_LEN SZ_32M +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + + /* + * Environment configuration + */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + /* + * Console configuration +diff -ruN u-boot-2021.10/include/configs/nyan-big.h u-boot/include/configs/nyan-big.h +--- u-boot-2021.10/include/configs/nyan-big.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/nyan-big.h 2021-11-01 17:10:14.596240922 +0100 +@@ -26,9 +26,6 @@ + /* SPI */ + #define CONFIG_SPI_FLASH_SIZE (4 << 20) + +-#undef CONFIG_LOADADDR +-#define CONFIG_LOADADDR 0x82408000 +- + #include "tegra-common-usb-gadget.h" + #include "tegra-common-post.h" + +diff -ruN u-boot-2021.10/include/configs/o4-imx6ull-nano.h u-boot/include/configs/o4-imx6ull-nano.h +--- u-boot-2021.10/include/configs/o4-imx6ull-nano.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/o4-imx6ull-nano.h 2021-11-01 17:10:14.596240922 +0100 +@@ -6,7 +6,6 @@ + + #include "mx6_common.h" + +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +diff -ruN u-boot-2021.10/include/configs/octeon_common.h u-boot/include/configs/octeon_common.h +--- u-boot-2021.10/include/configs/octeon_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/octeon_common.h 2021-11-01 17:10:14.596240922 +0100 +@@ -8,19 +8,15 @@ + #define __OCTEON_COMMON_H__ + + #if defined(CONFIG_RAM_OCTEON) +-#define CONFIG_SYS_MALLOC_LEN (16 << 20) + #define CONFIG_SYS_INIT_SP_OFFSET 0x20100000 + #else + /* No DDR init -> run in L2 cache with limited resources */ +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 + #endif + + #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) +- + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + + #endif /* __OCTEON_COMMON_H__ */ +diff -ruN u-boot-2021.10/include/configs/octeontx2_common.h u-boot/include/configs/octeontx2_common.h +--- u-boot-2021.10/include/configs/octeontx2_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/octeontx2_common.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,11 +18,6 @@ + /** Stack starting address */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + +-/** Heap size for U-Boot */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +- + #define CONFIG_LAST_STAGE_INIT + + /* Allow environment variable to be overwritten */ +diff -ruN u-boot-2021.10/include/configs/octeontx_common.h u-boot/include/configs/octeontx_common.h +--- u-boot-2021.10/include/configs/octeontx_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/octeontx_common.h 2021-11-01 17:10:14.596240922 +0100 +@@ -44,9 +44,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + + /** Heap size for U-Boot */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + + /* Allow environment variable to be overwritten */ + #define CONFIG_ENV_OVERWRITE +@@ -98,7 +95,6 @@ + #if defined(CONFIG_NAND_OCTEONTX) + /*#define CONFIG_MTD_CONCAT */ + #define CONFIG_SYS_MAX_NAND_DEVICE 8 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + #endif /* __OCTEONTX_COMMON_H__ */ +diff -ruN u-boot-2021.10/include/configs/odroid.h u-boot/include/configs/odroid.h +--- u-boot-2021.10/include/configs/odroid.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/odroid.h 2021-11-01 17:10:14.596240922 +0100 +@@ -19,8 +19,6 @@ + #define CONFIG_SYS_PL310_BASE 0x10502000 + #endif + +-#define CONFIG_MACH_TYPE 4289 +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +@@ -28,9 +26,6 @@ + #define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) + #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE + +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +- + #include <linux/sizes.h> + + #define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" +@@ -174,6 +169,4 @@ + */ + #define CONFIG_MISC_COMMON + +-#undef CONFIG_REVISION_TAG +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/odroid_xu3.h u-boot/include/configs/odroid_xu3.h +--- u-boot-2021.10/include/configs/odroid_xu3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/odroid_xu3.h 2021-11-01 17:10:14.596240922 +0100 +@@ -75,7 +75,6 @@ + + /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ + #define CONFIG_ODROID_REV_AIN 9 +-#define CONFIG_REVISION_TAG + + /* + * Need to override existing one (smdk5420) with odroid so set_board_info will +diff -ruN u-boot-2021.10/include/configs/omap3_beagle.h u-boot/include/configs/omap3_beagle.h +--- u-boot-2021.10/include/configs/omap3_beagle.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap3_beagle.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,27 +18,14 @@ + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + /* NAND */ + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_FLASH_BASE NAND_BASE + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K + /* NAND: SPL falcon mode configs */ + #if defined(CONFIG_SPL_OS_BOOT) +@@ -46,9 +33,6 @@ + #endif /* CONFIG_SPL_OS_BOOT */ + #endif /* CONFIG_MTD_RAW_NAND */ + +-/* USB EHCI */ +-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 +- + /* Enable Multi Bus support for I2C */ + #define CONFIG_I2C_MULTI_BUS + +@@ -211,7 +195,7 @@ + "${defargs} " \ + "${optargs} " \ + "root=${ramroot} ramdisk_size=${ramdisk_size} " \ +- "rootfstype=${ramrootfstype}\0" \ ++ "rootfstype=${ramrootfstype}\0" \ + "ramboot=run mmcbootenv; " \ + "if run loadimage && run loaddtb && run loadramdisk; then " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \ +diff -ruN u-boot-2021.10/include/configs/omap3_evm.h u-boot/include/configs/omap3_evm.h +--- u-boot-2021.10/include/configs/omap3_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap3_evm.h 2021-11-01 17:10:14.596240922 +0100 +@@ -23,26 +23,14 @@ + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + /* NAND */ + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_FLASH_BASE NAND_BASE + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K + /* NAND: SPL falcon mode configs */ + #if defined(CONFIG_SPL_OS_BOOT) +diff -ruN u-boot-2021.10/include/configs/omap3_igep00x0.h u-boot/include/configs/omap3_igep00x0.h +--- u-boot-2021.10/include/configs/omap3_igep00x0.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap3_igep00x0.h 2021-11-01 17:10:14.596240922 +0100 +@@ -16,8 +16,6 @@ + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +-#define CONFIG_REVISION_TAG 1 +- + /* TPS65950 */ + #define PBIASLITEVMODE1 (1 << 8) + +@@ -77,12 +75,6 @@ + #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) + + /* NAND config */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -92,6 +84,5 @@ + 50, 51, 52, 53, 54, 55, 56, 57, } + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + + #endif /* __IGEP00X0_H */ +diff -ruN u-boot-2021.10/include/configs/omap3_logic.h u-boot/include/configs/omap3_logic.h +--- u-boot-2021.10/include/configs/omap3_logic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap3_logic.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,39 +14,10 @@ + + #include <configs/ti_omap3_common.h> + +-/* +- * We are only ever GP parts and will utilize all of the "downloaded image" +- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in +- * order to allow for BCH8 to fit in. +- */ +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* Hardware drivers */ +- +-/* I2C */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +- +-#ifdef CONFIG_SPL_BUILD +-#undef CONFIG_USB_EHCI_OMAP +-#endif +-#ifdef CONFIG_USB_EHCI_OMAP +-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 +-#endif +- + /* Board NAND Info. */ + #ifdef CONFIG_MTD_RAW_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ +@@ -56,7 +27,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 13 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + #define CONFIG_SYS_NAND_MAX_ECCPOS 56 + #endif +diff -ruN u-boot-2021.10/include/configs/omap4_panda.h u-boot/include/configs/omap4_panda.h +--- u-boot-2021.10/include/configs/omap4_panda.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap4_panda.h 2021-11-01 17:10:14.596240922 +0100 +@@ -11,22 +11,6 @@ + #ifndef __CONFIG_PANDA_H + #define __CONFIG_PANDA_H + +-/* +- * High Level Configuration Options +- */ +- +-/* USB UHH support options */ +-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 +-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 +- +-/* USB Networking options */ +- +-#define CONFIG_UBOOT_ENABLE_PADS_ALL +- + #include <configs/ti_omap4_common.h> + +-/* GPIO */ +- +-/* ENV related config options */ +- + #endif /* __CONFIG_PANDA_H */ +diff -ruN u-boot-2021.10/include/configs/omap4_sdp4430.h u-boot/include/configs/omap4_sdp4430.h +--- u-boot-2021.10/include/configs/omap4_sdp4430.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap4_sdp4430.h 2021-11-01 17:10:14.596240922 +0100 +@@ -15,7 +15,6 @@ + /* + * High Level Configuration Options + */ +-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP + + #include <configs/ti_omap4_common.h> + +diff -ruN u-boot-2021.10/include/configs/omap5_uevm.h u-boot/include/configs/omap5_uevm.h +--- u-boot-2021.10/include/configs/omap5_uevm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omap5_uevm.h 2021-11-01 17:10:14.596240922 +0100 +@@ -43,9 +43,6 @@ + /* USB UHH support options */ + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 +-#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 +- + /* Enabled commands */ + + /* USB Networking options */ +diff -ruN u-boot-2021.10/include/configs/omapl138_lcdk.h u-boot/include/configs/omapl138_lcdk.h +--- u-boot-2021.10/include/configs/omapl138_lcdk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/omapl138_lcdk.h 2021-11-01 17:10:14.596240922 +0100 +@@ -17,18 +17,15 @@ + /* + * SoC Configuration + */ +-#define CONFIG_MACH_OMAPL138_LCDK + #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) + #define CONFIG_SYS_OSCIN_FREQ 24000000 + #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE + #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) + #define CONFIG_SYS_HZ 1000 +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + + /* + * Memory Info + */ +-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ + #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ + #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ + #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +@@ -125,9 +122,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ + #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST + #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) + #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K + #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +@@ -140,12 +134,8 @@ + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 10 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SPL_NAND_LOAD + #endif + + /* +@@ -161,7 +151,6 @@ + #define CONFIG_BOOTFILE "zImage" /* Boot file name */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) + + /* + * USB Configs +@@ -173,9 +162,6 @@ + * Linux Information + */ + #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SETUP_MEMORY_TAGS + #define CONFIG_BOOTCOMMAND \ + "run envboot; " \ + "run mmcboot; " +diff -ruN u-boot-2021.10/include/configs/openpiton-riscv64.h u-boot/include/configs/openpiton-riscv64.h +--- u-boot-2021.10/include/configs/openpiton-riscv64.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/openpiton-riscv64.h 2021-11-01 17:10:14.596240922 +0100 +@@ -16,8 +16,6 @@ + /* Environment options */ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) +-#define CONFIG_SYS_LOAD_ADDR 0x87000000 +-#define CONFIG_SYS_MALLOC_LEN SZ_256M + #define CONFIG_SYS_BOOTM_LEN SZ_256M + + #ifdef CONFIG_SPL +diff -ruN u-boot-2021.10/include/configs/openrd.h u-boot/include/configs/openrd.h +--- u-boot-2021.10/include/configs/openrd.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/openrd.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,7 +18,6 @@ + */ + #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/opos6uldev.h u-boot/include/configs/opos6uldev.h +--- u-boot-2021.10/include/configs/opos6uldev.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/opos6uldev.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,9 +18,6 @@ + #endif + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 << 20) +- + /* Miscellaneous configurable options */ + #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR + +@@ -78,7 +75,7 @@ + "mmcrootfstype=ext4 rootwait\0" \ + "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ + "splashpos=0,0\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ +diff -ruN u-boot-2021.10/include/configs/origen.h u-boot/include/configs/origen.h +--- u-boot-2021.10/include/configs/origen.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/origen.h 2021-11-01 17:10:14.596240922 +0100 +@@ -19,11 +19,6 @@ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +- +-#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN +- + #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 +diff -ruN u-boot-2021.10/include/configs/owl-common.h u-boot/include/configs/owl-common.h +--- u-boot-2021.10/include/configs/owl-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/owl-common.h 2021-11-01 17:10:14.596240922 +0100 +@@ -16,10 +16,7 @@ + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY (24000000) /* 24MHz */ + +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- + /* Some commands use this as the default load address */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) + + /* + * This is the initial SP which is used only briefly for relocating the u-boot +diff -ruN u-boot-2021.10/include/configs/P1010RDB.h u-boot/include/configs/P1010RDB.h +--- u-boot-2021.10/include/configs/P1010RDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/P1010RDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -14,7 +14,6 @@ + #include <linux/stringify.h> + + #include <asm/config_mpc85xx.h> +-#define CONFIG_NAND_FSL_IFC + + #ifdef CONFIG_SDCARD + #define CONFIG_SPL_FLUSH_IMAGE +@@ -153,7 +152,6 @@ + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + #endif + +-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ + #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ + + #define CONFIG_HWCONFIG +@@ -168,7 +166,6 @@ + + /* DDR Setup */ + #define CONFIG_SYS_DDR_RAW_TIMING +-#define CONFIG_DDR_SPD + #define CONFIG_SYS_SPD_BUS_NUM 1 + #define SPD_EEPROM_ADDRESS 0x52 + +@@ -311,10 +308,8 @@ + | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ + | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ + | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ +-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + + #elif defined(CONFIG_TARGET_P1010RDB_PB) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ +@@ -322,7 +317,6 @@ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + #endif + + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +@@ -443,7 +437,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + + /* + * Config the L2 Cache as L2 SRAM +@@ -497,38 +490,19 @@ + #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + #define I2C_PCA9557_ADDR1 0x18 + #define I2C_PCA9557_ADDR2 0x19 + #define I2C_PCA9557_BUS_NUM 0 +-#define CONFIG_SYS_I2C_FSL + + /* I2C EEPROM */ + #if defined(CONFIG_TARGET_P1010RDB_PB) +-#define CONFIG_ID_EEPROM + #ifdef CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #endif +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 + #define CONFIG_SYS_EEPROM_BUS_NUM 0 + #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ + #endif + /* enable read and write access to EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* RTC */ + #define CONFIG_RTC_PT7C4338 +@@ -632,7 +606,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -642,10 +615,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -660,9 +629,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "netdev=eth0\0" \ +@@ -715,7 +681,7 @@ + "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" + #endif + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -723,7 +689,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND ++#define CONFIG_BOOTCOMMAND RAMBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/p1_p2_rdb_pc.h u-boot/include/configs/p1_p2_rdb_pc.h +--- u-boot-2021.10/include/configs/p1_p2_rdb_pc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/p1_p2_rdb_pc.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,7 +14,6 @@ + + #if defined(CONFIG_TARGET_P1020RDB_PC) + #define CONFIG_BOARDNAME "P1020RDB-PC" +-#define CONFIG_NAND_FSL_ELBC + #define CONFIG_VSC7385_ENET + #define CONFIG_SLIC + #define __SW_BOOT_MASK 0x03 +@@ -41,7 +40,6 @@ + */ + #if defined(CONFIG_TARGET_P1020RDB_PD) + #define CONFIG_BOARDNAME "P1020RDB-PD" +-#define CONFIG_NAND_FSL_ELBC + #define CONFIG_VSC7385_ENET + #define CONFIG_SLIC + #define __SW_BOOT_MASK 0x03 +@@ -58,7 +56,6 @@ + + #if defined(CONFIG_TARGET_P2020RDB) + #define CONFIG_BOARDNAME "P2020RDB-PC" +-#define CONFIG_NAND_FSL_ELBC + #define CONFIG_VSC7385_ENET + #define __SW_BOOT_MASK 0x03 + #define __SW_BOOT_NOR 0xc8 +@@ -85,9 +82,7 @@ + #ifdef CONFIG_SPL_BUILD + #define CONFIG_SPL_COMMON_INIT_DDR + #endif +-#endif +- +-#ifdef CONFIG_SPIFLASH ++#elif defined(CONFIG_SPIFLASH) + #define CONFIG_SPL_SPI_FLASH_MINIMAL + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +@@ -101,9 +96,7 @@ + #ifdef CONFIG_SPL_BUILD + #define CONFIG_SPL_COMMON_INIT_DDR + #endif +-#endif +- +-#ifdef CONFIG_MTD_RAW_NAND ++#elif defined(CONFIG_MTD_RAW_NAND) + #ifdef CONFIG_TPL_BUILD + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_NAND_INIT +@@ -157,7 +150,6 @@ + #else + #define CONFIG_SYS_CLK_FREQ 66666666 + #endif +-#define CONFIG_DDR_CLK_FREQ 66666666 + + #define CONFIG_HWCONFIG + /* +@@ -179,7 +171,6 @@ + + /* DDR Setup */ + #define CONFIG_SYS_DDR_RAW_TIMING +-#define CONFIG_DDR_SPD + #define CONFIG_SYS_SPD_BUS_NUM 1 + #define SPD_EEPROM_ADDRESS 0x52 + +@@ -292,11 +283,6 @@ + + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#if defined(CONFIG_TARGET_P1020RDB_PD) +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#else +-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +-#endif + + #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ +@@ -346,7 +332,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + + #define CONFIG_SYS_CPLD_BASE 0xffa00000 + #ifdef CONFIG_PHYS_64BIT +@@ -464,36 +449,20 @@ + + /* I2C */ + #if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 + #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 + #endif + +-#define CONFIG_SYS_I2C_FSL +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 + #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ + + /* + * I2C2 EEPROM + */ +-#undef CONFIG_ID_EEPROM + + #define CONFIG_RTC_PT7C4338 + #define CONFIG_SYS_I2C_RTC_ADDR 0x68 + #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + + /* enable read and write access to EEPROM */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + #if defined(CONFIG_PCI) + /* +@@ -607,7 +576,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -617,10 +585,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -629,9 +593,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #ifdef __SW_BOOT_NOR + #define __NOR_RST_CMD \ + norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ +@@ -691,7 +652,7 @@ + __stringify(__NAND_RST_CMD)"\0" \ + __stringify(__PCIE_RST_CMD)"\0" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -700,7 +661,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ +@@ -733,7 +694,7 @@ + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ + "bootm $norbootaddr - $norfdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs " \ + "ramdisk_size=$ramdisk_size;" \ +@@ -742,6 +703,6 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT ++#define CONFIG_BOOTCOMMAND HDBOOT + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/P2041RDB.h u-boot/include/configs/P2041RDB.h +--- u-boot-2021.10/include/configs/P2041RDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/P2041RDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -14,8 +14,6 @@ + #ifdef CONFIG_RAMBOOT_PBL + #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE + #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg + #endif + + #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +@@ -88,11 +86,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * DDR Setup +@@ -104,8 +99,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +-#define CONFIG_DDR_SPD +- + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define SPD_EEPROM_ADDRESS 0x52 + #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +@@ -166,7 +159,6 @@ + #define CONFIG_SYS_RAMBOOT + #endif + +-#define CONFIG_NAND_FSL_ELBC + /* Nand Flash */ + #ifdef CONFIG_NAND_FSL_ELBC + #define CONFIG_SYS_NAND_BASE 0xffa00000 +@@ -178,7 +170,6 @@ + + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + + /* NAND flash config */ + #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +@@ -240,7 +231,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + + /* Serial Port - controlled on board with jumper J8 + * open - index 2 +@@ -259,19 +249,6 @@ + #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +-#define CONFIG_SYS_I2C_FSL + + + /* +@@ -400,7 +377,7 @@ + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) + #elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) ++#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024)) + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * Slave has no ucode locally, it can fetch this from remote. When implementing +@@ -478,7 +455,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -488,10 +464,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -499,9 +471,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH u-boot.bin + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #define __USB_PHY_TYPE utmi + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -525,14 +494,14 @@ + "fdtfile=p2041rdb/p2041rdb.dtb\0" \ + "bdev=sda3\0" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -541,7 +510,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -549,7 +518,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT ++#define CONFIG_BOOTCOMMAND HDBOOT + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/P3041DS.h u-boot/include/configs/P3041DS.h +--- u-boot-2021.10/include/configs/P3041DS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/P3041DS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -9,7 +9,6 @@ + */ + #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +-#define CONFIG_NAND_FSL_ELBC + #define CONFIG_FSL_SATA_V2 + #define CONFIG_PCIE3 + #define CONFIG_PCIE4 +diff -ruN u-boot-2021.10/include/configs/P5040DS.h u-boot/include/configs/P5040DS.h +--- u-boot-2021.10/include/configs/P5040DS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/P5040DS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -9,7 +9,6 @@ + */ + #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +-#define CONFIG_NAND_FSL_ELBC + #define CONFIG_PCIE3 + #define CONFIG_FSL_SATA_V2 + #define CONFIG_SYS_FSL_RAID_ENGINE +diff -ruN u-boot-2021.10/include/configs/paz00.h u-boot/include/configs/paz00.h +--- u-boot-2021.10/include/configs/paz00.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/paz00.h 2021-11-01 17:10:14.596240922 +0100 +@@ -19,8 +19,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTA + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 +- + /* Environment in eMMC, at the end of 2nd "boot sector" */ + + #include "tegra-common-post.h" +diff -ruN u-boot-2021.10/include/configs/pcl063.h u-boot/include/configs/pcl063.h +--- u-boot-2021.10/include/configs/pcl063.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pcl063.h 2021-11-01 17:10:14.596240922 +0100 +@@ -24,9 +24,6 @@ + + #define CONFIG_SYS_FSL_USDHC_NUM 1 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + /* Console configs */ + #define CONFIG_MXC_UART_BASE UART1_BASE + +@@ -36,7 +33,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/pcl063_ull.h u-boot/include/configs/pcl063_ull.h +--- u-boot-2021.10/include/configs/pcl063_ull.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pcl063_ull.h 2021-11-01 17:10:14.596240922 +0100 +@@ -18,9 +18,6 @@ + + #define CONFIG_SYS_FSL_USDHC_NUM 2 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + /* Environment settings */ + + /* Environment in SD */ +@@ -36,14 +33,9 @@ + #define CONFIG_SUPPORT_EMMC_BOOT + + /* I2C configs */ +-#ifdef CONFIG_CMD_I2C +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +-#endif + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/pcm052.h u-boot/include/configs/pcm052.h +--- u-boot-2021.10/include/configs/pcm052.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pcm052.h 2021-11-01 17:10:14.596240922 +0100 +@@ -12,21 +12,10 @@ + #include <linux/sizes.h> + #include <linux/stringify.h> + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- +-/* Enable passing of ATAGs */ +-#define CONFIG_CMDLINE_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) +- + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + +-#define CONFIG_LOADADDR 0x82000000 +- + /* We boot from the gfxRAM area of the OCRAM. */ + #define CONFIG_BOARD_SIZE_LIMIT 520192 + +@@ -139,8 +128,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Physical memory map */ + #define PHYS_SDRAM (0x80000000) + #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) +diff -ruN u-boot-2021.10/include/configs/pcm058.h u-boot/include/configs/pcm058.h +--- u-boot-2021.10/include/configs/pcm058.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pcm058.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,12 +14,8 @@ + + #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) +- + /* Enable NAND support */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + /* Physical Memory Map */ + #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +diff -ruN u-boot-2021.10/include/configs/pdu001.h u-boot/include/configs/pdu001.h +--- u-boot-2021.10/include/configs/pdu001.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pdu001.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,9 +14,6 @@ + + /* Using 32K of volatile storage for environment */ + +-#define MACH_TYPE_PDU001 5075 +-#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 +- + /* Clock Defines */ + #define V_OSCK 24000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK) +diff -ruN u-boot-2021.10/include/configs/phycore_am335x_r2.h u-boot/include/configs/phycore_am335x_r2.h +--- u-boot-2021.10/include/configs/phycore_am335x_r2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/phycore_am335x_r2.h 2021-11-01 17:10:14.596240922 +0100 +@@ -14,8 +14,6 @@ + + #include <configs/ti_am335x_common.h> + +-#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X +- + #ifdef CONFIG_MTD_RAW_NAND + #define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ +@@ -87,14 +85,7 @@ + + #ifdef CONFIG_MTD_RAW_NAND + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -105,8 +96,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + + /* NAND: SPL related configs */ + #ifdef CONFIG_SPL_OS_BOOT +@@ -118,8 +107,6 @@ + + #ifdef CONFIG_SPI_BOOT + #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +-#elif defined(CONFIG_ENV_IS_IN_NAND) +-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #endif + + #endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ +diff -ruN u-boot-2021.10/include/configs/phycore_imx8mm.h u-boot/include/configs/phycore_imx8mm.h +--- u-boot-2021.10/include/configs/phycore_imx8mm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/phycore_imx8mm.h 2021-11-01 17:10:14.596240922 +0100 +@@ -82,8 +82,6 @@ + "fi;" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +@@ -94,8 +92,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + #define PHYS_SDRAM SZ_1G +@@ -117,9 +113,6 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* I2C */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* ENET1 */ + #define CONFIG_ETHPRIME "FEC" + #define CONFIG_FEC_XCV_TYPE RGMII +diff -ruN u-boot-2021.10/include/configs/phycore_imx8mp.h u-boot/include/configs/phycore_imx8mp.h +--- u-boot-2021.10/include/configs/phycore_imx8mp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/phycore_imx8mp.h 2021-11-01 17:10:14.596240922 +0100 +@@ -29,12 +29,8 @@ + + #define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PCA9450 + +-#define CONFIG_SYS_I2C_LEGACY +- + #endif + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -84,8 +80,6 @@ + "fi;" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +@@ -96,8 +90,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + #define PHYS_SDRAM 0x40000000 +@@ -117,7 +109,4 @@ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* I2C */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #endif /* __PHYCORE_IMX8MP_H */ +diff -ruN u-boot-2021.10/include/configs/pic32mzdask.h u-boot/include/configs/pic32mzdask.h +--- u-boot-2021.10/include/configs/pic32mzdask.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pic32mzdask.h 2021-11-01 17:10:14.596240922 +0100 +@@ -28,13 +28,11 @@ + + /* SDRAM Configuration (for final code, data, stack, heap) */ + #define CONFIG_SYS_SDRAM_BASE 0x88000000 +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + #define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_MONITOR_LEN (192 << 10) + +-#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ + #define CONFIG_SYS_ENV_ADDR 0x88300000 + #define CONFIG_SYS_FDT_ADDR 0x89d00000 + +diff -ruN u-boot-2021.10/include/configs/pico-imx6.h u-boot/include/configs/pico-imx6.h +--- u-boot-2021.10/include/configs/pico-imx6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pico-imx6.h 2021-11-01 17:10:14.596240922 +0100 +@@ -24,9 +24,6 @@ + #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configuration */ +@@ -94,11 +91,11 @@ + "run base_boot;" \ + "fi; \0" \ + "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + BOOTENV + + #define BOOT_TARGET_DEVICES(func) \ +diff -ruN u-boot-2021.10/include/configs/pico-imx6ul.h u-boot/include/configs/pico-imx6ul.h +--- u-boot-2021.10/include/configs/pico-imx6ul.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pico-imx6ul.h 2021-11-01 17:10:14.596240922 +0100 +@@ -33,9 +33,6 @@ + #define CONFIG_FEC_MXC_PHYADDR 0x1 + #define CONFIG_FEC_XCV_TYPE RMII + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ +- + #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR + + /* MMC Configs */ +@@ -82,11 +79,11 @@ + BOOTMENU_ENV \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "mmcautodetect=yes\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "findfdt=" \ +@@ -111,7 +108,6 @@ + #include <config_distro_bootcmd.h> + #include <linux/stringify.h> + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -126,10 +122,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* environment organization */ + /* Environment starts at 768k = 768 * 1024 = 786432 */ + /* +diff -ruN u-boot-2021.10/include/configs/pico-imx7d.h u-boot/include/configs/pico-imx7d.h +--- u-boot-2021.10/include/configs/pico-imx7d.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pico-imx7d.h 2021-11-01 17:10:14.596240922 +0100 +@@ -24,9 +24,6 @@ + #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR + + /* MMC Config */ +@@ -74,7 +71,7 @@ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "console=ttymxc4\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ +@@ -82,11 +79,11 @@ + "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "findfdt=" \ + "if test $fdtfile = ask ; then " \ +@@ -110,7 +107,6 @@ + #include <config_distro_bootcmd.h> + #include <linux/stringify.h> + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -125,18 +121,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 +-#define CONFIG_SYS_I2C_MXC_I2C2 +-#define CONFIG_SYS_I2C_MXC_I2C3 +-#define CONFIG_SYS_I2C_MXC_I2C4 +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE3000 + #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + +diff -ruN u-boot-2021.10/include/configs/pico-imx8mq.h u-boot/include/configs/pico-imx8mq.h +--- u-boot-2021.10/include/configs/pico-imx8mq.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pico-imx8mq.h 2021-11-01 17:10:14.596240922 +0100 +@@ -25,7 +25,7 @@ + #define CONFIG_SPL_LIBCOMMON_SUPPORT + #define CONFIG_SPL_LIBGENERIC_SUPPORT + #define CONFIG_SPL_GPIO +-#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_MMC + #define CONFIG_SPL_BSS_START_ADDR 0x00180000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ + #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +@@ -38,17 +38,6 @@ + #define CONFIG_SPL_ABORT_ON_RAW_IMAGE + + #undef CONFIG_DM_MMC +-#undef CONFIG_DM_PMIC +- +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +- +-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +- +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #endif + + #define CONFIG_REMAKE_ELF +@@ -121,9 +110,6 @@ + "else booti ${loadaddr} - ${fdt_addr}; fi" + + /* Link Definitions */ +-#define CONFIG_LOADADDR 0x40480000 +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +@@ -134,9 +120,6 @@ + + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ +@@ -163,15 +146,8 @@ + + #define CONFIG_MXC_GPIO + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + #define CONFIG_OF_SYSTEM_SETUP + +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_DM_PMIC +-#endif +- + #define CONFIG_SYS_BOOTM_LEN SZ_128M + + #endif +diff -ruN u-boot-2021.10/include/configs/pm9261.h u-boot/include/configs/pm9261.h +--- u-boot-2021.10/include/configs/pm9261.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pm9261.h 2021-11-01 17:10:14.599574073 +0100 +@@ -25,10 +25,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ + #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 + +-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" +- +-#define CONFIG_MACH_TYPE MACH_TYPE_PM9261 +- + /* clocks */ + /* CKGR_MOR - enable main osc. */ + #define CONFIG_SYS_MOR_VAL \ +@@ -128,12 +124,6 @@ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 +-#define CONFIG_INITRD_TAG 1 +- +-#undef CONFIG_SKIP_LOWLEVEL_INIT +- + /* + * Hardware drivers + */ +@@ -182,8 +172,6 @@ + #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 +- + #undef CONFIG_SYS_USE_DATAFLASH_CS0 + #undef CONFIG_SYS_USE_NANDFLASH + #define CONFIG_SYS_USE_FLASH 1 +@@ -233,12 +221,6 @@ + #error "Undefined memory device" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN \ +- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +- + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ + GENERATED_GBL_DATA_SIZE) +diff -ruN u-boot-2021.10/include/configs/pm9263.h u-boot/include/configs/pm9263.h +--- u-boot-2021.10/include/configs/pm9263.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pm9263.h 2021-11-01 17:10:14.599574073 +0100 +@@ -25,10 +25,6 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ + +-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" +- +-#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 +- + /* clocks */ + #define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | \ +@@ -140,11 +136,6 @@ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) + +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 +-#define CONFIG_INITRD_TAG 1 +- +-#undef CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_USER_LOWLEVEL_INIT 1 + + /* +@@ -213,8 +204,6 @@ + #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #define CONFIG_SYS_USE_FLASH 1 + #undef CONFIG_SYS_USE_DATAFLASH + #undef CONFIG_SYS_USE_NANDFLASH +@@ -266,11 +255,6 @@ + #error "Undefined memory device" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +- + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ + GENERATED_GBL_DATA_SIZE) +diff -ruN u-boot-2021.10/include/configs/pm9g45.h u-boot/include/configs/pm9g45.h +--- u-boot-2021.10/include/configs/pm9g45.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pm9g45.h 2021-11-01 17:10:14.599574073 +0100 +@@ -19,11 +19,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +@@ -57,8 +52,6 @@ + #define CONFIG_RESET_PHY_R + #define CONFIG_AT91_WANTS_COMMON_PHY + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_NAND_BOOT + /* bootstrap + u-boot + env in nandflash */ + +@@ -73,12 +66,6 @@ + "bootz 0x72000000 - 0x71000000" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ +- 128 * 1024, 0x1000) +- + /* Defines for SPL */ + #define CONFIG_SPL_MAX_SIZE 0x010000 + #define CONFIG_SPL_STACK 0x310000 +@@ -96,17 +83,10 @@ + + #elif CONFIG_NAND_BOOT + #define CONFIG_SPL_NAND_SOFTECC +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +diff -ruN u-boot-2021.10/include/configs/pogo_e02.h u-boot/include/configs/pogo_e02.h +--- u-boot-2021.10/include/configs/pogo_e02.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pogo_e02.h 2021-11-01 17:10:14.599574073 +0100 +@@ -13,16 +13,10 @@ + #define _CONFIG_POGO_E02_H + + /* +- * Machine type definition and ID +- */ +-#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 +- +-/* + * High Level Configuration Options (easy to change) + */ + #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ + #define CONFIG_KW88F6281 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + + #include "mv-common.h" + +diff -ruN u-boot-2021.10/include/configs/poplar.h u-boot/include/configs/poplar.h +--- u-boot-2021.10/include/configs/poplar.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/poplar.h 2021-11-01 17:10:14.599574073 +0100 +@@ -18,8 +18,6 @@ + /* SYS */ + #define CONFIG_SYS_BOOTM_LEN SZ_64M + #define CONFIG_SYS_INIT_SP_ADDR 0x200000 +-#define CONFIG_SYS_LOAD_ADDR 0x800000 +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + + /* ATF bl33.bin load address (must match) */ + +diff -ruN u-boot-2021.10/include/configs/presidio_asic.h u-boot/include/configs/presidio_asic.h +--- u-boot-2021.10/include/configs/presidio_asic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/presidio_asic.h 2021-11-01 17:10:14.599574073 +0100 +@@ -23,13 +23,9 @@ + /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE + * does not yet support DT. Thus define it here. + */ +-#define CONFIG_GICV2 + #define GICD_BASE 0xf7011000 + #define GICC_BASE 0xf7012000 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) +- + #define CONFIG_SYS_TIMER_BASE 0xf4321000 + + /* Use external clock source */ +@@ -48,7 +44,6 @@ + #define CONFIG_BOOTP_BOOTFILESIZE + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) + #define CONFIG_LAST_STAGE_INIT + + /* SDRAM Bank #1 */ +@@ -82,9 +77,7 @@ + + /* nand driver parameters */ + #ifdef CONFIG_TARGET_PRESIDIO_ASIC +- #define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +- #define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #endif +diff -ruN u-boot-2021.10/include/configs/puma_rk3399.h u-boot/include/configs/puma_rk3399.h +--- u-boot-2021.10/include/configs/puma_rk3399.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/puma_rk3399.h 2021-11-01 17:10:14.599574073 +0100 +@@ -10,6 +10,4 @@ + + #define SDRAM_BANK_SIZE (2UL << 30) + +-#define CONFIG_SERIAL_TAG +- + #endif +diff -ruN u-boot-2021.10/include/configs/px30_common.h u-boot/include/configs/px30_common.h +--- u-boot-2021.10/include/configs/px30_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/px30_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,7 +9,6 @@ + #include "rockchip-common.h" + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_SYS_NS16550_MEM32 + +@@ -20,7 +19,6 @@ + #define CONFIG_IRAM_BASE 0xff020000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 +-#define CONFIG_SYS_LOAD_ADDR 0x00800800 + #define CONFIG_SPL_STACK 0x00400000 + #define CONFIG_SPL_MAX_SIZE 0x20000 + #define CONFIG_SPL_BSS_START_ADDR 0x4000000 +diff -ruN u-boot-2021.10/include/configs/pxa-common.h u-boot/include/configs/pxa-common.h +--- u-boot-2021.10/include/configs/pxa-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pxa-common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,13 +9,6 @@ + #define __CONFIG_PXA_COMMON_H__ + + /* +- * KGDB +- */ +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 +-#endif +- +-/* + * OHCI USB + */ + #ifdef CONFIG_CMD_USB +diff -ruN u-boot-2021.10/include/configs/pxm2.h u-boot/include/configs/pxm2.h +--- u-boot-2021.10/include/configs/pxm2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/pxm2.h 2021-11-01 17:10:14.599574073 +0100 +@@ -13,8 +13,6 @@ + #ifndef __CONFIG_PXM2_H + #define __CONFIG_PXM2_H + +-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 +- + #include "siemens-am33x-common.h" + + #define DDR_IOCTRL_VAL 0x18b +@@ -32,10 +30,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 400000 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +- + #define CONFIG_FACTORYSET + + #ifndef CONFIG_SPL_BUILD +diff -ruN u-boot-2021.10/include/configs/qemu-arm.h u-boot/include/configs/qemu-arm.h +--- u-boot-2021.10/include/configs/qemu-arm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/qemu-arm.h 2021-11-01 17:10:14.599574073 +0100 +@@ -14,8 +14,6 @@ + + /* The DTB generated by QEMU is placed at start of RAM, stay away from there */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +-#define CONFIG_SYS_MALLOC_LEN SZ_16M + + #define CONFIG_SYS_BOOTM_LEN SZ_64M + +diff -ruN u-boot-2021.10/include/configs/qemu-ppce500.h u-boot/include/configs/qemu-ppce500.h +--- u-boot-2021.10/include/configs/qemu-ppce500.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/qemu-ppce500.h 2021-11-01 17:10:14.599574073 +0100 +@@ -69,7 +69,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (512 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + #define CONFIG_LBA48 + +@@ -85,7 +84,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -102,9 +100,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #define CONFIG_BOOTCOMMAND \ + "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0" + +diff -ruN u-boot-2021.10/include/configs/qemu-riscv.h u-boot/include/configs/qemu-riscv.h +--- u-boot-2021.10/include/configs/qemu-riscv.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/qemu-riscv.h 2021-11-01 17:10:14.599574073 +0100 +@@ -21,10 +21,6 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +- +-#define CONFIG_SYS_MALLOC_LEN SZ_8M +- + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +diff -ruN u-boot-2021.10/include/configs/r2dplus.h u-boot/include/configs/r2dplus.h +--- u-boot-2021.10/include/configs/r2dplus.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/r2dplus.h 2021-11-01 17:10:14.599574073 +0100 +@@ -15,12 +15,9 @@ + + #define CONFIG_SYS_PBSIZE 256 + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) + /* Address of u-boot image in Flash */ + #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) + #define CONFIG_SYS_MONITOR_LEN (256 * 1024) +-/* Size of DRAM reserved for malloc() use */ +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + + /* +diff -ruN u-boot-2021.10/include/configs/rastaban.h u-boot/include/configs/rastaban.h +--- u-boot-2021.10/include/configs/rastaban.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rastaban.h 2021-11-01 17:10:14.599574073 +0100 +@@ -34,10 +34,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + #define EEPROM_ADDR_DDR3 0x90 + #define EEPROM_ADDR_CHIP 0x120 + +diff -ruN u-boot-2021.10/include/configs/rcar-gen2-common.h u-boot/include/configs/rcar-gen2-common.h +--- u-boot-2021.10/include/configs/rcar-gen2-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rcar-gen2-common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -10,10 +10,6 @@ + + #include <asm/arch/rmobile.h> + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + #ifdef CONFIG_SPL + #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" + #endif +@@ -28,12 +24,9 @@ + + #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) + #define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +-#define CONFIG_SYS_LOAD_ADDR 0x50000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 + #define CONFIG_SYS_MONITOR_LEN (256 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + /* ENV setting */ + +diff -ruN u-boot-2021.10/include/configs/rcar-gen3-common.h u-boot/include/configs/rcar-gen3-common.h +--- u-boot-2021.10/include/configs/rcar-gen3-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rcar-gen3-common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -21,12 +21,7 @@ + + /* boot option */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + /* Generic Interrupt Controller Definitions */ +-#define CONFIG_GICV2 + #define GICD_BASE 0xF1010000 + #define GICC_BASE 0xF1020000 + +@@ -45,14 +40,11 @@ + #define DRAM_RSV_SIZE 0x08000000 + #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) + #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +-#define CONFIG_SYS_LOAD_ADDR 0x58000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + #define CONFIG_VERY_BIG_RAM + #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 + #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + #define CONFIG_SYS_BOOTM_LEN (64 << 20) + + /* The HF/QSPI layout permits up to 1 MiB large bootloader blob */ +diff -ruN u-boot-2021.10/include/configs/rk3036_common.h u-boot/include/configs/rk3036_common.h +--- u-boot-2021.10/include/configs/rk3036_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3036_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,7 +9,6 @@ + #include "rockchip-common.h" + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 + #define COUNTER_FREQUENCY 24000000 +@@ -17,7 +16,6 @@ + #define CONFIG_SYS_HZ_CLOCK 24000000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +-#define CONFIG_SYS_LOAD_ADDR 0x60800800 + #define CONFIG_SPL_STACK 0x10081fff + + #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +diff -ruN u-boot-2021.10/include/configs/rk3128_common.h u-boot/include/configs/rk3128_common.h +--- u-boot-2021.10/include/configs/rk3128_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3128_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -10,7 +10,6 @@ + + #define CONFIG_SYS_MAXARGS 16 + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 + #define COUNTER_FREQUENCY 24000000 +@@ -20,7 +19,6 @@ + #define CONFIG_IRAM_BASE 0x10080000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +-#define CONFIG_SYS_LOAD_ADDR 0x60800800 + + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +diff -ruN u-boot-2021.10/include/configs/rk3188_common.h u-boot/include/configs/rk3188_common.h +--- u-boot-2021.10/include/configs/rk3188_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3188_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -6,19 +6,15 @@ + #ifndef __CONFIG_RK3188_COMMON_H + #define __CONFIG_RK3188_COMMON_H + +-#define CONFIG_SYS_CACHELINE_SIZE 64 +- + #include <asm/arch-rockchip/hardware.h> + #include "rockchip-common.h" + +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + #define CONFIG_SYS_CBSIZE 1024 + + #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM + /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ + #endif + #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +-#define CONFIG_SYS_LOAD_ADDR 0x60800800 + + #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) + #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" +diff -ruN u-boot-2021.10/include/configs/rk322x_common.h u-boot/include/configs/rk322x_common.h +--- u-boot-2021.10/include/configs/rk322x_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk322x_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -8,7 +8,6 @@ + #include <asm/arch-rockchip/hardware.h> + #include "rockchip-common.h" + +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_CBSIZE 1024 + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +@@ -18,7 +17,6 @@ + #define CONFIG_SYS_HZ_CLOCK 24000000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +-#define CONFIG_SYS_LOAD_ADDR 0x61800800 + #define CONFIG_SPL_MAX_SIZE 0x100000 + + #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) +diff -ruN u-boot-2021.10/include/configs/rk3288_common.h u-boot/include/configs/rk3288_common.h +--- u-boot-2021.10/include/configs/rk3288_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3288_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -11,7 +11,6 @@ + + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ + +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + #define CONFIG_SYS_CBSIZE 1024 + + #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 +@@ -23,7 +22,6 @@ + /* Bootrom will load u-boot binary to 0x0 once return from SPL */ + #endif + #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +-#define CONFIG_SYS_LOAD_ADDR 0x00800800 + #define CONFIG_SPL_STACK 0xff718000 + + #define CONFIG_IRAM_BASE 0xff700000 +diff -ruN u-boot-2021.10/include/configs/rk3308_common.h u-boot/include/configs/rk3308_common.h +--- u-boot-2021.10/include/configs/rk3308_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3308_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,12 +9,6 @@ + #include "rockchip-common.h" + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) + #define CONFIG_SPL_MAX_SIZE 0x20000 + #define CONFIG_SPL_BSS_START_ADDR 0x00400000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +@@ -25,7 +19,6 @@ + #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 + #define CONFIG_IRAM_BASE 0xfff80000 + #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 +-#define CONFIG_SYS_LOAD_ADDR 0x00C00800 + #define CONFIG_SPL_STACK 0x00400000 + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +diff -ruN u-boot-2021.10/include/configs/rk3328_common.h u-boot/include/configs/rk3328_common.h +--- u-boot-2021.10/include/configs/rk3328_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3328_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -14,10 +14,8 @@ + #define COUNTER_FREQUENCY 24000000 + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +-#define CONFIG_SYS_LOAD_ADDR 0x00800800 + #define CONFIG_SPL_STACK 0x00400000 + #define CONFIG_SPL_MAX_SIZE 0x40000 + #define CONFIG_SPL_BSS_START_ADDR 0x2000000 +diff -ruN u-boot-2021.10/include/configs/rk3368_common.h u-boot/include/configs/rk3368_common.h +--- u-boot-2021.10/include/configs/rk3368_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3368_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -8,15 +8,12 @@ + + #include "rockchip-common.h" + +-#define CONFIG_SYS_CACHELINE_SIZE 64 +- + #include <asm/arch-rockchip/hardware.h> + #include <linux/sizes.h> + + #define CONFIG_SYS_SDRAM_BASE 0 + #define SDRAM_MAX_SIZE 0xff000000 + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 + #define COUNTER_FREQUENCY 24000000 +@@ -24,7 +21,6 @@ + #define CONFIG_IRAM_BASE 0xff8c0000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +-#define CONFIG_SYS_LOAD_ADDR 0x00800800 + + #define CONFIG_SPL_MAX_SIZE 0x40000 + #define CONFIG_SPL_BSS_START_ADDR 0x400000 +diff -ruN u-boot-2021.10/include/configs/rk3399_common.h u-boot/include/configs/rk3399_common.h +--- u-boot-2021.10/include/configs/rk3399_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3399_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,7 +9,6 @@ + #include "rockchip-common.h" + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define COUNTER_FREQUENCY 24000000 + #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 +@@ -17,7 +16,6 @@ + #define CONFIG_IRAM_BASE 0xff8c0000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +-#define CONFIG_SYS_LOAD_ADDR 0x00800800 + + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) + #define CONFIG_SPL_STACK 0x00400000 +diff -ruN u-boot-2021.10/include/configs/rk3568_common.h u-boot/include/configs/rk3568_common.h +--- u-boot-2021.10/include/configs/rk3568_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rk3568_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -9,7 +9,6 @@ + #include "rockchip-common.h" + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define COUNTER_FREQUENCY 24000000 + #define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 +@@ -17,7 +16,6 @@ + #define CONFIG_IRAM_BASE 0xfdcc0000 + + #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 +-#define CONFIG_SYS_LOAD_ADDR 0x00c00800 + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + + #define CONFIG_SYS_SDRAM_BASE 0 +diff -ruN u-boot-2021.10/include/configs/rpi.h u-boot/include/configs/rpi.h +--- u-boot-2021.10/include/configs/rpi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rpi.h 2021-11-01 17:10:14.599574073 +0100 +@@ -13,10 +13,6 @@ + #include <asm/arch/base.h> + #endif + +-#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- + /* Architecture, CPU, etc.*/ + + /* Use SoC timer for AArch32, but architected timer for AArch64 */ +@@ -26,21 +22,6 @@ + (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) + #endif + +-/* +- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, +- * so 2708 has historically been used rather than a dedicated 2835 ID. +- * +- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation +- * chose to use someone else's previously registered machine ID (3139, MX51_GGC) +- * rather than obtaining a valid ID:-/ +- * +- * For the bcm2837, hopefully a machine type is not needed, since everything +- * is DT. +- */ +-#ifdef CONFIG_BCM2835 +-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 +-#endif +- + /* Memory layout */ + #define CONFIG_SYS_SDRAM_BASE 0x00000000 + #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +@@ -54,8 +35,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +-#define CONFIG_SYS_MALLOC_LEN SZ_4M +-#define CONFIG_LOADADDR 0x00200000 + + #ifdef CONFIG_ARM64 + #define CONFIG_SYS_BOOTM_LEN SZ_64M +@@ -88,15 +67,9 @@ + #define CONFIG_SYS_CBSIZE 1024 + + /* Environment */ +-#define CONFIG_SYS_LOAD_ADDR 0x1000000 + + /* Shell */ + +-/* ATAGs support for bootm/bootz */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +- + /* Environment */ + #define ENV_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ +diff -ruN u-boot-2021.10/include/configs/rut.h u-boot/include/configs/rut.h +--- u-boot-2021.10/include/configs/rut.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rut.h 2021-11-01 17:10:14.599574073 +0100 +@@ -13,8 +13,6 @@ + #ifndef __CONFIG_RUT_H + #define __CONFIG_RUT_H + +-#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT +- + #include "siemens-am33x-common.h" + + #define RUT_IOCTRL_VAL 0x18b +@@ -23,14 +21,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ +- + #define CONFIG_FACTORYSET + + /* Watchdog */ +diff -ruN u-boot-2021.10/include/configs/rv1108_common.h u-boot/include/configs/rv1108_common.h +--- u-boot-2021.10/include/configs/rv1108_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/rv1108_common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -11,7 +11,6 @@ + #define CONFIG_IRAM_BASE 0x10080000 + + #define CONFIG_SYS_CBSIZE 1024 +-#define CONFIG_SKIP_LOWLEVEL_INIT + + #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) + /* TIMER1,initialized by ddr initialize code */ +@@ -20,7 +19,6 @@ + + #define CONFIG_SYS_SDRAM_BASE 0x60000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) + + /* rockchip ohci host driver */ + #define CONFIG_USB_OHCI_NEW +diff -ruN u-boot-2021.10/include/configs/s5p4418_nanopi2.h u-boot/include/configs/s5p4418_nanopi2.h +--- u-boot-2021.10/include/configs/s5p4418_nanopi2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/s5p4418_nanopi2.h 2021-11-01 17:10:14.599574073 +0100 +@@ -60,12 +60,9 @@ + */ + #define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) + +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- + #define BMP_LOAD_ADDR 0x78000000 + + /* kernel load address */ +-#define CONFIG_SYS_LOAD_ADDR 0x71080000 + #define INITRD_START 0x79000000 + #define KERNEL_DTB_ADDR 0x7A000000 + +@@ -116,7 +113,6 @@ + (void *)PHY_BASEADDR_UART1, \ + (void *)PHY_BASEADDR_UART2, \ + (void *)PHY_BASEADDR_UART3} +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + /*----------------------------------------------------------------------- + * PLL +diff -ruN u-boot-2021.10/include/configs/s5pc210_universal.h u-boot/include/configs/s5pc210_universal.h +--- u-boot-2021.10/include/configs/s5pc210_universal.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/s5pc210_universal.h 2021-11-01 17:10:14.599574073 +0100 +@@ -31,9 +31,6 @@ + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 + +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) +- + /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ + + #define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT +@@ -44,16 +41,6 @@ + ",100M(swap)"\ + ",-(UMS)\0" + +-#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" +-#define CONFIG_BOOTBLOCK "10" +-#define CONFIG_UBIBLOCK "9" +- +-#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " +-#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ +- "${mtdparts}" +- +-#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + "updateb=" \ + "onenand erase 0x0 0x100000;" \ +@@ -71,18 +58,20 @@ + "lpj=lpj=3981312\0" \ + "ubifsboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \ +- CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ +- CONFIG_ENV_COMMON_BOOT "; run bootk\0" \ ++ "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ ++ "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ ++ "${lcdinfo} ${console} ${meminfo}; run bootk\0" \ + "tftpboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ +- CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ +- CONFIG_ENV_COMMON_BOOT \ ++ "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ ++ "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ ++ "${lcdinfo} ${console} ${meminfo}" \ + "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \ + "nfsboot=" \ + "set bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ +- "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ ++ "${netmask}:generic:usb0:off ${console} ${meminfo}" \ + "; run bootk\0" \ + "ramfsboot=" \ + "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ +@@ -102,8 +91,8 @@ + "mbrparts=" MBRPARTS_DEFAULT \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ +- "bootblock=" CONFIG_BOOTBLOCK "\0" \ +- "ubiblock=" CONFIG_UBIBLOCK" \0" \ ++ "bootblock=10\0" \ ++ "ubiblock=9\0" \ + "ubi=enabled\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ + "mmcdev=0\0" \ +diff -ruN u-boot-2021.10/include/configs/s5p_goni.h u-boot/include/configs/s5p_goni.h +--- u-boot-2021.10/include/configs/s5p_goni.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/s5p_goni.h 2021-11-01 17:10:14.599574073 +0100 +@@ -26,14 +26,6 @@ + + /* Text Base */ + +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_INITRD_TAG +- +-/* Size of malloc() pool before and after relocation */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) +- + /* MMC */ + #define SDHCI_MAX_HOSTS 4 + +@@ -138,8 +130,6 @@ + "dfu_alt_info=" CONFIG_DFU_ALT "\0" + + #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) + + /* Goni has 3 banks of DRAM, but swap the bank */ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +diff -ruN u-boot-2021.10/include/configs/sagem_f@st1704.h u-boot/include/configs/sagem_f@st1704.h +--- u-boot-2021.10/include/configs/sagem_f@st1704.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sagem_f@st1704.h 2021-11-01 17:10:14.599574073 +0100 +@@ -5,4 +5,3 @@ + + #include <configs/bmips_common.h> + #include <configs/bmips_bcm6338.h> +- +diff -ruN u-boot-2021.10/include/configs/sam9x60ek.h u-boot/include/configs/sam9x60ek.h +--- u-boot-2021.10/include/configs/sam9x60ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sam9x60ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -14,11 +14,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #define CONFIG_USART_BASE ATMEL_BASE_DBGU + #define CONFIG_USART_ID 0 /* ignored in arm */ + +@@ -51,11 +46,8 @@ + #define CONFIG_SYS_NAND_MASK_CLE BIT(22) + #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 + #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #ifdef CONFIG_SD_BOOT + /* bootstrap + u-boot + env + linux in sd card */ + #define CONFIG_BOOTCOMMAND \ +@@ -78,9 +70,4 @@ + "bootz 0x22000000 - 0x21000000" + #endif + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/sama5d27_som1_ek.h u-boot/include/configs/sama5d27_som1_ek.h +--- u-boot-2021.10/include/configs/sama5d27_som1_ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d27_som1_ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -14,26 +14,20 @@ + #undef CONFIG_SYS_AT91_MAIN_CLOCK + #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +-/* SDRAM */ +-#define CONFIG_SYS_SDRAM_BASE 0x20000000 +-#define CONFIG_SYS_SDRAM_SIZE 0x8000000 +- + #ifdef CONFIG_SPL_BUILD + #define CONFIG_SYS_INIT_SP_ADDR 0x218000 + #else + #define CONFIG_SYS_INIT_SP_ADDR \ +- (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) ++ (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + #undef CONFIG_BOOTCOMMAND + #ifdef CONFIG_SD_BOOT + /* bootstrap + u-boot + env in sd card */ +-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \ ++#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 " \ + CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ +- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ +- "bootz 0x22000000 - 0x21000000" ++ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ ++ "bootz 0x23000000 - 0x22000000" + #endif + + /* SPL */ +diff -ruN u-boot-2021.10/include/configs/sama5d27_wlsom1_ek.h u-boot/include/configs/sama5d27_wlsom1_ek.h +--- u-boot-2021.10/include/configs/sama5d27_wlsom1_ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d27_wlsom1_ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -26,8 +26,6 @@ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SPL */ + #define CONFIG_SPL_TEXT_BASE 0x200000 + #define CONFIG_SPL_MAX_SIZE 0x10000 +diff -ruN u-boot-2021.10/include/configs/sama5d2_icp.h u-boot/include/configs/sama5d2_icp.h +--- u-boot-2021.10/include/configs/sama5d2_icp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d2_icp.h 2021-11-01 17:10:14.599574073 +0100 +@@ -27,8 +27,6 @@ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* NAND flash */ + + /* SPI flash */ +diff -ruN u-boot-2021.10/include/configs/sama5d2_ptc_ek.h u-boot/include/configs/sama5d2_ptc_ek.h +--- u-boot-2021.10/include/configs/sama5d2_ptc_ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d2_ptc_ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -22,8 +22,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* NAND Flash */ + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -32,7 +30,6 @@ + #define CONFIG_SYS_NAND_MASK_ALE BIT(21) + /* our CLE is AD22 */ + #define CONFIG_SYS_NAND_MASK_CLE BIT(22) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/sama5d2_xplained.h u-boot/include/configs/sama5d2_xplained.h +--- u-boot-2021.10/include/configs/sama5d2_xplained.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d2_xplained.h 2021-11-01 17:10:14.599574073 +0100 +@@ -11,19 +11,13 @@ + + #include "at91-sama5_common.h" + +-/* SDRAM */ +-#define CONFIG_SYS_SDRAM_BASE 0x20000000 +-#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +- + #ifdef CONFIG_SPL_BUILD + #define CONFIG_SYS_INIT_SP_ADDR 0x218000 + #else + #define CONFIG_SYS_INIT_SP_ADDR \ +- (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) ++ (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SerialFlash */ + + #ifdef CONFIG_SD_BOOT +@@ -31,18 +25,18 @@ + /* bootstrap + u-boot + env in sd card */ + #undef CONFIG_BOOTCOMMAND + +-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \ +- "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ +- "bootz 0x22000000 - 0x21000000" ++#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 at91-sama5d2_xplained.dtb; " \ ++ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ ++ "bootz 0x23000000 - 0x22000000" + + #elif CONFIG_SPI_BOOT + + /* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */ + #undef CONFIG_BOOTCOMMAND + +-#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \ +- "ext4load mmc 0:1 0x22000000 /boot/zImage; " \ +- "bootz 0x22000000 - 0x21000000" ++#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; " \ ++ "ext4load mmc 0:1 0x23000000 /boot/zImage; " \ ++ "bootz 0x23000000 - 0x22000000" + + #endif + +@@ -51,9 +45,9 @@ + #undef CONFIG_BOOTCOMMAND + #define CONFIG_ENV_SPI_BUS 1 + #define CONFIG_BOOTCOMMAND "sf probe 1:0; " \ +- "sf read 0x21000000 0x180000 0x80000; " \ +- "sf read 0x22000000 0x200000 0x600000; "\ +- "bootz 0x22000000 - 0x21000000" ++ "sf read 0x22000000 0x180000 0x80000; " \ ++ "sf read 0x23000000 0x200000 0x600000; "\ ++ "bootz 0x23000000 - 0x22000000" + + #endif + +diff -ruN u-boot-2021.10/include/configs/sama5d3xek.h u-boot/include/configs/sama5d3xek.h +--- u-boot-2021.10/include/configs/sama5d3xek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d3xek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -56,7 +56,6 @@ + #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) + /* our CLE is AD22 */ + #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + /* USB */ +@@ -69,8 +68,6 @@ + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SPL */ + #define CONFIG_SPL_MAX_SIZE 0x18000 + #define CONFIG_SPL_BSS_START_ADDR 0x20000000 +@@ -83,12 +80,5 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + #endif +diff -ruN u-boot-2021.10/include/configs/sama5d3_xplained.h u-boot/include/configs/sama5d3_xplained.h +--- u-boot-2021.10/include/configs/sama5d3_xplained.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d3_xplained.h 2021-11-01 17:10:14.599574073 +0100 +@@ -42,7 +42,6 @@ + #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) + /* our CLE is AD22 */ + #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + /* USB */ +@@ -56,8 +55,6 @@ + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SPL */ + #define CONFIG_SPL_MAX_SIZE 0x18000 + #define CONFIG_SPL_BSS_START_ADDR 0x20000000 +@@ -71,13 +68,6 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + /* Falcon boot support on raw MMC */ + #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ +diff -ruN u-boot-2021.10/include/configs/sama5d4ek.h u-boot/include/configs/sama5d4ek.h +--- u-boot-2021.10/include/configs/sama5d4ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d4ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -22,8 +22,6 @@ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* NAND flash */ + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -32,7 +30,6 @@ + #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) + /* our CLE is AD22 */ + #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + /* SPL */ +@@ -47,12 +44,5 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 224 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + #endif +diff -ruN u-boot-2021.10/include/configs/sama5d4_xplained.h u-boot/include/configs/sama5d4_xplained.h +--- u-boot-2021.10/include/configs/sama5d4_xplained.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama5d4_xplained.h 2021-11-01 17:10:14.599574073 +0100 +@@ -22,8 +22,6 @@ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* NAND flash */ + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -32,7 +30,6 @@ + #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) + /* our CLE is AD22 */ + #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + /* SPL */ +@@ -47,12 +44,5 @@ + #ifdef CONFIG_SD_BOOT + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_OOBSIZE 224 +-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + + #endif +diff -ruN u-boot-2021.10/include/configs/sama7g5ek.h u-boot/include/configs/sama7g5ek.h +--- u-boot-2021.10/include/configs/sama7g5ek.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sama7g5ek.h 2021-11-01 17:10:14.599574073 +0100 +@@ -24,9 +24,7 @@ + GENERATED_GBL_DATA_SIZE) + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x62000000 /* load address */ +- +-#undef CONFIG_BOOTCOMMAND ++#ifndef CONFIG_BOOTCOMMAND + #ifdef CONFIG_SD_BOOT + /* u-boot env in sd/mmc card */ + +@@ -34,10 +32,11 @@ + #define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \ + "bootz 0x62000000 - 0x61000000" ++#else ++#define CONFIG_BOOTCOMMAND "Place your bootcommand here" + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) ++#endif + + #define CONFIG_ARP_TIMEOUT 200 + #define CONFIG_NET_RETRY_COUNT 50 +diff -ruN u-boot-2021.10/include/configs/sandbox.h u-boot/include/configs/sandbox.h +--- u-boot-2021.10/include/configs/sandbox.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sandbox.h 2021-11-01 17:10:14.599574073 +0100 +@@ -24,11 +24,7 @@ + + #define CONFIG_HOST_MAX_DEVICES 4 + +-/* +- * Size of malloc() pool, before and after relocation +- */ + #define CONFIG_MALLOC_F_ADDR 0x0010000 +-#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ + + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +@@ -38,8 +34,6 @@ + + #define CONFIG_I2C_EDID + +-/* Memory things - we don't really want a memory test */ +-#define CONFIG_SYS_LOAD_ADDR 0x00000000 + #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 + + #define CONFIG_PHYSMEM +diff -ruN u-boot-2021.10/include/configs/SBx81LIFKW.h u-boot/include/configs/SBx81LIFKW.h +--- u-boot-2021.10/include/configs/SBx81LIFKW.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/SBx81LIFKW.h 2021-11-01 17:10:14.572908865 +0100 +@@ -11,7 +11,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg + + /* additions for new ARM relocation support */ +@@ -38,15 +37,6 @@ + * for your console driver. + */ + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ +- + #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" + #define MTDPARTS_MTDOOPS "errlog" + #define CONFIG_DOS_PARTITION +@@ -60,13 +50,7 @@ + */ + + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ + #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + + /* size in bytes reserved for initial data */ +@@ -89,6 +73,4 @@ + #define CONFIG_PHY_BASE_ADR 0x01 + #endif /* CONFIG_CMD_NET */ + +-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ +- + #endif /* _CONFIG_SBX81LIFKW_H */ +diff -ruN u-boot-2021.10/include/configs/SBx81LIFXCAT.h u-boot/include/configs/SBx81LIFXCAT.h +--- u-boot-2021.10/include/configs/SBx81LIFXCAT.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/SBx81LIFXCAT.h 2021-11-01 17:10:14.572908865 +0100 +@@ -11,7 +11,6 @@ + */ + #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ + #define CONFIG_KW88F6281 1 /* SOC Name */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg + + /* additions for new ARM relocation support */ +@@ -38,15 +37,6 @@ + * for your console driver. + */ + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ +- + #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" + #define MTDPARTS_MTDOOPS "errlog" + #define CONFIG_DOS_PARTITION +@@ -60,7 +50,6 @@ + */ + + #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + + /* + * For booting Linux, the board info and command line data +@@ -89,6 +78,4 @@ + #define CONFIG_PHY_BASE_ADR 0x01 + #endif /* CONFIG_CMD_NET */ + +-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ +- + #endif /* _CONFIG_SBX81LIFXCAT_H */ +diff -ruN u-boot-2021.10/include/configs/seaboard.h u-boot/include/configs/seaboard.h +--- u-boot-2021.10/include/configs/seaboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/seaboard.h 2021-11-01 17:10:14.599574073 +0100 +@@ -24,8 +24,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTD + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD +- + /* Environment in eMMC, at the end of 2nd "boot sector" */ + + /* NAND support */ +diff -ruN u-boot-2021.10/include/configs/sfr_nb4_ser.h u-boot/include/configs/sfr_nb4_ser.h +--- u-boot-2021.10/include/configs/sfr_nb4_ser.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sfr_nb4_ser.h 2021-11-01 17:10:14.599574073 +0100 +@@ -7,4 +7,3 @@ + #include <configs/bmips_bcm6358.h> + + #define CONFIG_REMAKE_ELF +- +diff -ruN u-boot-2021.10/include/configs/siemens-am33x-common.h u-boot/include/configs/siemens-am33x-common.h +--- u-boot-2021.10/include/configs/siemens-am33x-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/siemens-am33x-common.h 2021-11-01 17:10:14.599574073 +0100 +@@ -18,15 +18,6 @@ + #define CONFIG_DMA_COHERENT + #define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +-#ifdef CONFIG_SIEMENS_MACH_TYPE +-#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE +-#endif +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + /* commands to include */ + + #ifndef CONFIG_SPL_BUILD +@@ -53,8 +44,6 @@ + * start addr of ram disk + */ + +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +- + /* Physical Memory Map */ + #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ + +@@ -73,7 +62,6 @@ + + + /* I2C Configuration */ +-#define CONFIG_SYS_I2C_LEGACY + + /* Defines for SPL */ + #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ +@@ -84,14 +72,6 @@ + + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -102,7 +82,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + + #define CONFIG_SYS_NAND_ECCSTEPS 4 + #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ +@@ -110,8 +89,6 @@ + + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +- + /* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's +@@ -125,9 +102,6 @@ + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #ifndef CONFIG_SPL_BUILD + /* +diff -ruN u-boot-2021.10/include/configs/sifive-unleashed.h u-boot/include/configs/sifive-unleashed.h +--- u-boot-2021.10/include/configs/sifive-unleashed.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sifive-unleashed.h 2021-11-01 17:10:14.599574073 +0100 +@@ -28,10 +28,6 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +- +-#define CONFIG_SYS_MALLOC_LEN SZ_8M +- + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 +diff -ruN u-boot-2021.10/include/configs/sifive-unmatched.h u-boot/include/configs/sifive-unmatched.h +--- u-boot-2021.10/include/configs/sifive-unmatched.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sifive-unmatched.h 2021-11-01 17:10:14.599574073 +0100 +@@ -28,18 +28,12 @@ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +- +-#define CONFIG_SYS_MALLOC_LEN SZ_8M +- + #define CONFIG_SYS_BOOTM_LEN SZ_64M + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + + #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ + +-#define CONFIG_SYS_CACHELINE_SIZE 64 +- + #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 + + /* Environment options */ +@@ -85,9 +79,5 @@ + #endif /* CONFIG_SPL_BUILD */ + + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 +- +-#define CONFIG_ID_EEPROM + + #endif /* __SIFIVE_UNMATCHED_H */ +diff -ruN u-boot-2021.10/include/configs/sipeed-maix.h u-boot/include/configs/sipeed-maix.h +--- u-boot-2021.10/include/configs/sipeed-maix.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sipeed-maix.h 2021-11-01 17:10:14.602907224 +0100 +@@ -8,11 +8,8 @@ + + #include <linux/sizes.h> + +-#define CONFIG_SYS_LOAD_ADDR 0x80000000 + /* Start just below the second bank so we don't clobber it during reloc */ + #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF +-#define CONFIG_SYS_MALLOC_LEN SZ_128K +-#define CONFIG_SYS_CACHELINE_SIZE 64 + + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_SDRAM_SIZE SZ_8M +diff -ruN u-boot-2021.10/include/configs/smartweb.h u-boot/include/configs/smartweb.h +--- u-boot-2021.10/include/configs/smartweb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/smartweb.h 2021-11-01 17:10:14.602907224 +0100 +@@ -40,16 +40,11 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ + + /* misc settings */ +-#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ +-#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ +-#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ + + /* We set the max number of command args high to avoid HUSH bugs. */ + #define CONFIG_SYS_MAXARGS 32 + + /* setting board specific options */ +-#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB + #define CONFIG_SYS_AUTOLOAD "yes" + #define CONFIG_RESET_TO_RETRY + +@@ -69,10 +64,6 @@ + * till the beginning of the U-Boot position in RAM. + */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN \ +- ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) +- + /* NAND flash settings */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +@@ -101,7 +92,7 @@ + + /* BOOTP and DHCP options */ + #define CONFIG_BOOTP_BOOTFILESIZE +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv autoload yes; setenv autoboot yes; " \ + "setenv bootargs ${basicargs} ${mtdparts} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ +@@ -130,12 +121,6 @@ + #define CONFIG_SYS_CBSIZE 512 + + /* +- * RAM Memory address where to put the +- * Linux Kernel befor starting. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 +- +-/* + * The NAND Flash partitions: + */ + #define CONFIG_ENV_RANGE (SZ_512K) +@@ -177,21 +162,13 @@ + #define CONFIG_SYS_USE_NANDFLASH 1 + #define CONFIG_SPL_NAND_RAW_ONLY + #define CONFIG_SPL_NAND_SOFTECC +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + + #define CONFIG_SYS_NAND_SIZE (SZ_256M) +-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +diff -ruN u-boot-2021.10/include/configs/smdkc100.h u-boot/include/configs/smdkc100.h +--- u-boot-2021.10/include/configs/smdkc100.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/smdkc100.h 2021-11-01 17:10:14.602907224 +0100 +@@ -29,16 +29,6 @@ + + /* Text Base */ + +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +- +-/* +- * Size of malloc() pool +- * 1MB = 0x100000, 0x100000 = 1024 * 1024 +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +- + /* + * select serial console configuration + */ +@@ -105,8 +95,6 @@ + * Miscellaneous configurable options + */ + #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + + /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +diff -ruN u-boot-2021.10/include/configs/smdkv310.h u-boot/include/configs/smdkv310.h +--- u-boot-2021.10/include/configs/smdkv310.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/smdkv310.h 2021-11-01 17:10:14.602907224 +0100 +@@ -12,14 +12,10 @@ + + #undef CONFIG_BOARD_COMMON + #undef CONFIG_USB_GADGET_DWC2_OTG_PHY +-#undef CONFIG_REVISION_TAG + + /* High Level Configuration Options */ + #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ + +-/* Mach Type */ +-#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 +- + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + /* Handling Sleep Mode*/ +@@ -28,14 +24,10 @@ + #define S5P_CHECK_LPA 0xABAD0000 + + /* MMC SPL */ +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define COPY_BL2_FNPTR_ADDR 0x00002488 + + #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" + +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +- + /* SMDKV310 has 4 bank of DRAM */ + #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +diff -ruN u-boot-2021.10/include/configs/smegw01.h u-boot/include/configs/smegw01.h +--- u-boot-2021.10/include/configs/smegw01.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/smegw01.h 2021-11-01 17:10:14.602907224 +0100 +@@ -14,9 +14,6 @@ + + #define PHYS_SDRAM_SIZE SZ_512M + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) +- + /* MMC Config*/ + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +@@ -45,7 +42,6 @@ + "run mmcboot; " \ + "fi; " \ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/snapper9260.h u-boot/include/configs/snapper9260.h +--- u-boot-2021.10/include/configs/snapper9260.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/snapper9260.h 2021-11-01 17:10:14.602907224 +0100 +@@ -20,11 +20,6 @@ + + /* CPU */ + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* SDRAM */ + #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 + #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ +@@ -73,10 +68,6 @@ + #endif + + /* I2C - Bit-bashed */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +-#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F + #define CONFIG_SOFT_I2C_READ_REPEATED_START + #define I2C_INIT do { \ + at91_set_gpio_output(AT91_PIN_PA23, 1); \ +@@ -100,7 +91,6 @@ + #define I2C_DELAY udelay(2) + + /* Boot options */ +-#define CONFIG_SYS_LOAD_ADDR 0x23000000 + + #define CONFIG_BOOTP_BOOTFILESIZE + +@@ -108,7 +98,4 @@ + + /* Console settings */ + +-/* U-Boot memory settings */ +-#define CONFIG_SYS_MALLOC_LEN (1 << 20) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/snapper9g45.h u-boot/include/configs/snapper9g45.h +--- u-boot-2021.10/include/configs/snapper9g45.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/snapper9g45.h 2021-11-01 17:10:14.602907224 +0100 +@@ -19,10 +19,6 @@ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + + /* CPU */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + + /* SDRAM */ + #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +@@ -64,7 +60,6 @@ + /* UARTs/Serial console */ + + /* Boot options */ +-#define CONFIG_SYS_LOAD_ADDR 0x23000000 + + #define CONFIG_BOOTP_BOOTFILESIZE + +@@ -92,7 +87,4 @@ + + /* Console settings */ + +-/* U-Boot memory settings */ +-#define CONFIG_SYS_MALLOC_LEN (1 << 20) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/sniper.h u-boot/include/configs/sniper.h +--- u-boot-2021.10/include/configs/sniper.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sniper.h 2021-11-01 17:10:14.602907224 +0100 +@@ -12,16 +12,6 @@ + #include <asm/arch/omap.h> + + /* +- * CPU +- */ +- +-#define CONFIG_ARM_ARCH_CP15_ERRATA +- +-/* +- * Board +- */ +- +-/* + * Clocks + */ + +@@ -47,13 +37,10 @@ + #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) +- + /* + * I2C + */ + +-#define CONFIG_SYS_I2C_LEGACY + #define CONFIG_I2C_MULTI_BUS + + /* +@@ -112,21 +99,9 @@ + "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" + + /* +- * ATAGs +- */ +- +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +-#define CONFIG_SERIAL_TAG +- +-/* + * Boot + */ + +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + #define CONFIG_BOOTCOMMAND \ + "setenv boot_mmc_part ${kernel_mmc_part}; " \ + "if test reboot-${reboot-mode} = reboot-r; then " \ +diff -ruN u-boot-2021.10/include/configs/socfpga_arria10_socdk.h u-boot/include/configs/socfpga_arria10_socdk.h +--- u-boot-2021.10/include/configs/socfpga_arria10_socdk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_arria10_socdk.h 2021-11-01 17:10:14.602907224 +0100 +@@ -8,10 +8,6 @@ + + #include <asm/arch/base_addr_a10.h> + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* + * U-Boot general configurations + */ +diff -ruN u-boot-2021.10/include/configs/socfpga_arria5_secu1.h u-boot/include/configs/socfpga_arria5_secu1.h +--- u-boot-2021.10/include/configs/socfpga_arria5_secu1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_arria5_secu1.h 2021-11-01 17:10:14.602907224 +0100 +@@ -43,7 +43,6 @@ + "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \ + "saveenv && saveenv && boot;" + +-#define CONFIG_CMDLINE_TAG + #define CONFIG_SYS_BOOTM_LEN (64 << 20) + + /* Environment settings */ +@@ -57,9 +56,6 @@ + #define CONFIG_BOOT_RETRY_TIME 45 + #define CONFIG_RESET_TO_RETRY + +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR +- + /* + * FPGA Remote Update related environment + * +@@ -115,11 +111,6 @@ + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +-#ifdef CONFIG_SPL_NAND_SUPPORT +-#undef CONFIG_SYS_NAND_U_BOOT_OFFS +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +-#endif +- + #undef CONFIG_WATCHDOG_TIMEOUT_MSECS + #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +diff -ruN u-boot-2021.10/include/configs/socfpga_arria5_socdk.h u-boot/include/configs/socfpga_arria5_socdk.h +--- u-boot-2021.10/include/configs/socfpga_arria5_socdk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_arria5_socdk.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_common.h u-boot/include/configs/socfpga_common.h +--- u-boot-2021.10/include/configs/socfpga_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_common.h 2021-11-01 17:10:14.602907224 +0100 +@@ -18,7 +18,6 @@ + * Memory configurations + */ + #define PHYS_SDRAM_1 0x0 +-#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) + #if defined(CONFIG_TARGET_SOCFPGA_GEN5) + #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 + #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +@@ -124,9 +123,7 @@ + * NAND Support + */ + #ifdef CONFIG_NAND_DENALI +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS + #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS + #endif +@@ -186,7 +183,7 @@ + #endif + + /* SPL SDMMC boot support */ +-#ifdef CONFIG_SPL_MMC_SUPPORT ++#ifdef CONFIG_SPL_MMC + #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #endif +@@ -199,13 +196,6 @@ + /* SPL QSPI boot support */ + + /* SPL NAND boot support */ +-#ifdef CONFIG_SPL_NAND_SUPPORT +-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +-#endif +-#endif + + /* Extra Environment */ + #ifndef CONFIG_SPL_BUILD +diff -ruN u-boot-2021.10/include/configs/socfpga_cyclone5_socdk.h u-boot/include/configs/socfpga_cyclone5_socdk.h +--- u-boot-2021.10/include/configs/socfpga_cyclone5_socdk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_cyclone5_socdk.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_dbm_soc1.h u-boot/include/configs/socfpga_dbm_soc1.h +--- u-boot-2021.10/include/configs/socfpga_dbm_soc1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_dbm_soc1.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,8 +13,6 @@ + /* Booting Linux */ + #define CONFIG_BOOTFILE "fitImage" + #define CONFIG_BOOTCOMMAND "run mmc_mmc" +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Environment is in MMC */ + +diff -ruN u-boot-2021.10/include/configs/socfpga_de0_nano_soc.h u-boot/include/configs/socfpga_de0_nano_soc.h +--- u-boot-2021.10/include/configs/socfpga_de0_nano_soc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_de0_nano_soc.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_de10_nano.h u-boot/include/configs/socfpga_de10_nano.h +--- u-boot-2021.10/include/configs/socfpga_de10_nano.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_de10_nano.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_de1_soc.h u-boot/include/configs/socfpga_de1_soc.h +--- u-boot-2021.10/include/configs/socfpga_de1_soc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_de1_soc.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_is1.h u-boot/include/configs/socfpga_is1.h +--- u-boot-2021.10/include/configs/socfpga_is1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_is1.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,8 +13,6 @@ + + /* Booting Linux */ + #define CONFIG_BOOTFILE "zImage" +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Ethernet on SoC (EMAC) */ + #if defined(CONFIG_CMD_NET) +diff -ruN u-boot-2021.10/include/configs/socfpga_mcvevk.h u-boot/include/configs/socfpga_mcvevk.h +--- u-boot-2021.10/include/configs/socfpga_mcvevk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_mcvevk.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,8 +13,6 @@ + /* Booting Linux */ + #define CONFIG_BOOTFILE "fitImage" + #define CONFIG_BOOTCOMMAND "run mmc_mmc" +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Environment is in MMC */ + +diff -ruN u-boot-2021.10/include/configs/socfpga_soc64_common.h u-boot/include/configs/socfpga_soc64_common.h +--- u-boot-2021.10/include/configs/socfpga_soc64_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_soc64_common.h 2021-11-01 17:10:14.602907224 +0100 +@@ -15,8 +15,6 @@ + * U-Boot general configurations + */ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +-#define CONFIG_LOADADDR 0x2000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_REMAKE_ELF + /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ + #define CPU_RELEASE_ADDR 0xFFD12210 +@@ -47,7 +45,6 @@ + + 0x100000) + #endif + #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + + /* + * U-Boot environment configurations +@@ -116,11 +113,6 @@ + "socfpga_legacy_reset_compat=1\0" + + /* +- * Generic Interrupt Controller Definitions +- */ +-#define CONFIG_GICV2 +- +-/* + * External memory configurations + */ + #define PHYS_SDRAM_1 0x0 +diff -ruN u-boot-2021.10/include/configs/socfpga_sockit.h u-boot/include/configs/socfpga_sockit.h +--- u-boot-2021.10/include/configs/socfpga_sockit.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_sockit.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_socrates.h u-boot/include/configs/socfpga_socrates.h +--- u-boot-2021.10/include/configs/socfpga_socrates.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_socrates.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> + +diff -ruN u-boot-2021.10/include/configs/socfpga_sr1500.h u-boot/include/configs/socfpga_sr1500.h +--- u-boot-2021.10/include/configs/socfpga_sr1500.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_sr1500.h 2021-11-01 17:10:14.602907224 +0100 +@@ -10,10 +10,6 @@ + /* Memory configurations */ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ + +-/* Booting Linux */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Ethernet on SoC (EMAC) */ + #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII + /* The PHY is autodetected, so no MII PHY address is needed here */ +diff -ruN u-boot-2021.10/include/configs/socfpga_vining_fpga.h u-boot/include/configs/socfpga_vining_fpga.h +--- u-boot-2021.10/include/configs/socfpga_vining_fpga.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socfpga_vining_fpga.h 2021-11-01 17:10:14.602907224 +0100 +@@ -14,8 +14,6 @@ + #define CONFIG_BOOTFILE "fitImage" + #define CONFIG_BOOTCOMMAND "run selboot" + #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ +-#define CONFIG_LOADADDR 0x01000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Extra Environment */ + #define CONFIG_HOSTNAME "socfpga_vining_fpga" +diff -ruN u-boot-2021.10/include/configs/socrates.h u-boot/include/configs/socrates.h +--- u-boot-2021.10/include/configs/socrates.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/socrates.h 2021-11-01 17:10:14.602907224 +0100 +@@ -57,9 +57,7 @@ + + /* DDR Setup */ + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +-#define CONFIG_DDR_SPD + +-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + #define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +@@ -72,7 +70,6 @@ + /* I2C addresses of SPD EEPROMs */ + #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ + +-#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ + + /* Hardcoded values, to use instead of SPD */ + #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +@@ -126,14 +123,13 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ + + /* FPGA and NAND */ + #define CONFIG_SYS_FPGA_BASE 0xc0000000 + #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ + #define CONFIG_SYS_HMI_BASE 0xc0010000 + #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +-#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ ++#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ + + #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -146,8 +142,6 @@ + + #define CONFIG_SYS_SPD_BUS_NUM 0 + +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +- + /* + * General PCI + * Memory space is mapped 1-1. +@@ -201,7 +195,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -210,11 +203,6 @@ + */ + #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +-#endif +- +-#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ +@@ -254,17 +242,17 @@ + "era fe000000 fe1dffff;" \ + "cp.b 100000 fe000000 ${filesize};" \ + "setenv filesize;saveenv\0" \ +- "update_fdt=tftp 100000 ${fdt_file};" \ ++ "update_fdt=tftp 100000 ${fdt_file};" \ + "era fe1e0000 fe1fffff;" \ + "cp.b 100000 fe1e0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ +- "update_initrd=tftp 100000 ${initrd_file};" \ ++ "update_initrd=tftp 100000 ${initrd_file};" \ + "era fe200000 fe9fffff;" \ + "cp.b 100000 fe200000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "clean_data=era fea00000 fff5ffff\0" \ +- "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ +- "load_usb=usb start;" \ ++ "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ ++ "load_usb=usb start;" \ + "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ + "boot_usb=run load_usb usbargs addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr};" \ +diff -ruN u-boot-2021.10/include/configs/somlabs_visionsom_6ull.h u-boot/include/configs/somlabs_visionsom_6ull.h +--- u-boot-2021.10/include/configs/somlabs_visionsom_6ull.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/somlabs_visionsom_6ull.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,9 +16,6 @@ + /* SPL options */ + #include "imx6_spl.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* MMC Configs */ +@@ -71,7 +68,6 @@ + + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/stemmy.h u-boot/include/configs/stemmy.h +--- u-boot-2021.10/include/configs/stemmy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stemmy.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,17 +13,37 @@ + * low-level initialization and rely on configuration provided by the Samsung + * bootloader. New images are loaded at the same address for compatibility. + */ +-#define CONFIG_SKIP_LOWLEVEL_INIT + #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +- +-#define CONFIG_SYS_MALLOC_LEN SZ_2M + + /* FIXME: This should be loaded from device tree... */ + #define CONFIG_SYS_L2_PL310 + #define CONFIG_SYS_PL310_BASE 0xa0412000 + +-/* Generate initrd atag for downstream kernel (others are copied in stemmy.c) */ +-#define CONFIG_INITRD_TAG ++/* Linux does not boot if FDT / initrd is loaded to end of RAM */ ++#define BOOT_ENV \ ++ "fdt_high=0x6000000\0" \ ++ "initrd_high=0x6000000\0" ++ ++#define CONSOLE_ENV \ ++ "stdin=serial\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#define FASTBOOT_ENV \ ++ "fastboot_partition_alias_boot=Kernel\0" \ ++ "fastboot_partition_alias_recovery=Kernel2\0" \ ++ "fastboot_partition_alias_system=SYSTEM\0" \ ++ "fastboot_partition_alias_cache=CACHEFS\0" \ ++ "fastboot_partition_alias_hidden=HIDDEN\0" \ ++ "fastboot_partition_alias_userdata=DATAFS\0" ++ ++#define BOOTCMD_ENV \ ++ "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ BOOT_ENV \ ++ CONSOLE_ENV \ ++ FASTBOOT_ENV \ ++ BOOTCMD_ENV + + #endif +diff -ruN u-boot-2021.10/include/configs/stih410-b2260.h u-boot/include/configs/stih410-b2260.h +--- u-boot-2021.10/include/configs/stih410-b2260.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stih410-b2260.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,7 +13,6 @@ + #define PHYS_SDRAM_1 0x40000000 + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define PHYS_SDRAM_1_SIZE 0x3E000000 +-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ + + #define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ + +@@ -25,7 +24,6 @@ + */ + #define CONFIG_SYS_BOOTMAPSZ SZ_256M + +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + #define CONFIG_SYS_BOOTM_LEN SZ_16M + + #define BOOT_TARGET_DEVICES(func) \ +@@ -45,10 +43,6 @@ + + /* Extra Commands */ + +-#define CONFIG_SETUP_MEMORY_TAGS +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN 0x1800000 + #define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN - \ +@@ -59,8 +53,6 @@ + + #define CONFIG_SYS_MAX_FLASH_BANKS 1 + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* USB Configs */ + #define CONFIG_USB_OHCI_NEW + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +diff -ruN u-boot-2021.10/include/configs/stm32f429-discovery.h u-boot/include/configs/stm32f429-discovery.h +--- u-boot-2021.10/include/configs/stm32f429-discovery.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32f429-discovery.h 2021-11-01 17:10:14.602907224 +0100 +@@ -14,8 +14,6 @@ + /* + * Configuration of the external SDRAM memory + */ +-#define CONFIG_SYS_LOAD_ADDR 0x90400000 +-#define CONFIG_LOADADDR 0x90400000 + + #define CONFIG_SYS_MAX_FLASH_SECT 12 + #define CONFIG_SYS_MAX_FLASH_BANKS 2 +@@ -27,15 +25,8 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_CBSIZE 1024 + +-#define CONFIG_SYS_MALLOC_LEN (2 << 20) +- + #define CONFIG_BOOTCOMMAND \ + "run bootcmd_romfs" + +diff -ruN u-boot-2021.10/include/configs/stm32f429-evaluation.h u-boot/include/configs/stm32f429-evaluation.h +--- u-boot-2021.10/include/configs/stm32f429-evaluation.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32f429-evaluation.h 2021-11-01 17:10:14.602907224 +0100 +@@ -19,8 +19,6 @@ + /* + * Configuration of the external SDRAM memory + */ +-#define CONFIG_SYS_LOAD_ADDR 0x00400000 +-#define CONFIG_LOADADDR 0x00400000 + + #define CONFIG_SYS_MAX_FLASH_SECT 12 + #define CONFIG_SYS_MAX_FLASH_BANKS 2 +@@ -29,15 +27,8 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_CBSIZE 1024 + +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +diff -ruN u-boot-2021.10/include/configs/stm32f469-discovery.h u-boot/include/configs/stm32f469-discovery.h +--- u-boot-2021.10/include/configs/stm32f469-discovery.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32f469-discovery.h 2021-11-01 17:10:14.602907224 +0100 +@@ -19,8 +19,6 @@ + /* + * Configuration of the external SDRAM memory + */ +-#define CONFIG_SYS_LOAD_ADDR 0x00400000 +-#define CONFIG_LOADADDR 0x00400000 + + #define CONFIG_SYS_MAX_FLASH_SECT 12 + #define CONFIG_SYS_MAX_FLASH_BANKS 2 +@@ -29,15 +27,8 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_CBSIZE 1024 + +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +diff -ruN u-boot-2021.10/include/configs/stm32f746-disco.h u-boot/include/configs/stm32f746-disco.h +--- u-boot-2021.10/include/configs/stm32f746-disco.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32f746-disco.h 2021-11-01 17:10:14.602907224 +0100 +@@ -15,13 +15,6 @@ + #define CONFIG_SYS_FLASH_BASE 0x08000000 + #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 + +-#ifdef CONFIG_SUPPORT_SPL +-#define CONFIG_SYS_LOAD_ADDR 0x08008000 +-#else +-#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +-#define CONFIG_LOADADDR 0xC0400000 +-#endif +- + /* + * Configuration of the external SDRAM memory + */ +@@ -36,15 +29,8 @@ + + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_CBSIZE 1024 + +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +diff -ruN u-boot-2021.10/include/configs/stm32h743-disco.h u-boot/include/configs/stm32h743-disco.h +--- u-boot-2021.10/include/configs/stm32h743-disco.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32h743-disco.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,21 +16,9 @@ + #define CONFIG_SYS_FLASH_BASE 0x08000000 + #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +-/* +- * Configuration of the external SDRAM memory +- */ +-#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +-#define CONFIG_LOADADDR 0xD0400000 +- + #define CONFIG_SYS_HZ_CLOCK 1000000 + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_MAXARGS 16 +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +diff -ruN u-boot-2021.10/include/configs/stm32h743-eval.h u-boot/include/configs/stm32h743-eval.h +--- u-boot-2021.10/include/configs/stm32h743-eval.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32h743-eval.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,21 +16,9 @@ + #define CONFIG_SYS_FLASH_BASE 0x08000000 + #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +-/* +- * Configuration of the external SDRAM memory +- */ +-#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +-#define CONFIG_LOADADDR 0xD0400000 +- + #define CONFIG_SYS_HZ_CLOCK 1000000 + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_MAXARGS 16 +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +diff -ruN u-boot-2021.10/include/configs/stm32h750-art-pi.h u-boot/include/configs/stm32h750-art-pi.h +--- u-boot-2021.10/include/configs/stm32h750-art-pi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32h750-art-pi.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,21 +16,9 @@ + #define CONFIG_SYS_FLASH_BASE 0x90000000 + #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +-/* +- * Configuration of the external SDRAM memory +- */ +-#define CONFIG_SYS_LOAD_ADDR 0xC1800000 +-#define CONFIG_LOADADDR 0xC1800000 +- + #define CONFIG_SYS_HZ_CLOCK 1000000 + +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- + #define CONFIG_SYS_MAXARGS 16 +-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +diff -ruN u-boot-2021.10/include/configs/stm32mp1.h u-boot/include/configs/stm32mp1.h +--- u-boot-2021.10/include/configs/stm32mp1.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stm32mp1.h 2021-11-01 17:10:14.602907224 +0100 +@@ -28,17 +28,6 @@ + #define CONFIG_SYS_CBSIZE SZ_1K + + /* +- * default load address used for command tftp, bootm , loadb, ... +- */ +-#define CONFIG_LOADADDR 0xc2000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- +-/* ATAGs */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +@@ -63,7 +52,6 @@ + #define CONFIG_SYS_MMC_MAX_DEVICE 3 + + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + /* Ethernet need */ +diff -ruN u-boot-2021.10/include/configs/stmark2.h u-boot/include/configs/stmark2.h +--- u-boot-2021.10/include/configs/stmark2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stmark2.h 2021-11-01 17:10:14.602907224 +0100 +@@ -12,7 +12,6 @@ + + #define CONFIG_MCFUART + #define CONFIG_SYS_UART_PORT 0 +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + + #define LDS_BOARD_TEXT \ + board/sysam/stmark2/sbf_dram_init.o (.text*) +@@ -73,7 +72,6 @@ + /* Boot Argument Buffer Size */ + #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + #define CONFIG_SYS_MBAR 0xFC000000 + + /* +@@ -111,8 +109,6 @@ + #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) + /* Reserve 256 kB for Monitor */ + #define CONFIG_SYS_MONITOR_LEN (256 << 10) +-/* Reserve 256 kB for malloc() */ +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) + + /* + * For booting Linux, the board info and command line data +@@ -132,7 +128,6 @@ + #endif + + /* Cache Configuration */ +-#define CONFIG_SYS_CACHELINE_SIZE 16 + #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) + #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ +diff -ruN u-boot-2021.10/include/configs/stv0991.h u-boot/include/configs/stv0991.h +--- u-boot-2021.10/include/configs/stv0991.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/stv0991.h 2021-11-01 17:10:14.602907224 +0100 +@@ -13,13 +13,10 @@ + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define PHYS_SDRAM_1_SIZE 0x00198000 + +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) +- + /* user interface */ + #define CONFIG_SYS_CBSIZE 1024 + + /* MISC */ +-#define CONFIG_SYS_LOAD_ADDR 0x00000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 + #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 + #define CONFIG_SYS_INIT_SP_OFFSET \ +diff -ruN u-boot-2021.10/include/configs/sun20i.h u-boot/include/configs/sun20i.h +--- u-boot-2021.10/include/configs/sun20i.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/configs/sun20i.h 2021-11-01 17:10:14.602907224 +0100 +@@ -0,0 +1,68 @@ ++#include <linux/stringify.h> ++ ++#define CONFIG_SYS_CACHELINE_SIZE 64 ++ ++/* FIXME: Need a real clock driver! */ ++#define CONFIG_SYS_NS16550_CLK 24000000 ++#define CONFIG_SYS_TCLK 24000000 ++ ++#ifdef CONFIG_USB_EHCI_HCD ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 ++#endif ++ ++#define CONFIG_SYS_INIT_SP_ADDR 0x4fe00000 ++#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ ++#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 ++#define CONFIG_SPL_STACK 0x00048000 ++ ++#define SDRAM_OFFSET(x) 0x4##x ++#define BOOTM_SIZE __stringify(0xa000000) ++#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0200000)) ++#define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) ++#define KERNEL_COMP_SIZE __stringify(0xb000000) ++#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) ++#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) ++#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) ++#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) ++#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) ++ ++#define MEM_LAYOUT_ENV_SETTINGS \ ++ "bootm_size=" BOOTM_SIZE "\0" \ ++ "fdt_addr_r=" FDT_ADDR_R "\0" \ ++ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ ++ "kernel_addr_r=" KERNEL_ADDR_R "\0" \ ++ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ ++ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" \ ++ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ ++ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ ++ "scriptaddr=" SCRIPT_ADDR_R "\0" ++ ++#ifdef CONFIG_MMC ++#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) ++#else ++#define BOOT_TARGET_DEVICES_MMC(func) ++#endif ++ ++#ifdef CONFIG_USB_STORAGE ++#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) ++#else ++#define BOOT_TARGET_DEVICES_USB(func) ++#endif ++ ++#ifdef CONFIG_CMD_DHCP ++#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) ++#else ++#define BOOT_TARGET_DEVICES_DHCP(func) ++#endif ++ ++#define BOOT_TARGET_DEVICES(func) \ ++ BOOT_TARGET_DEVICES_MMC(func) \ ++ BOOT_TARGET_DEVICES_USB(func) \ ++ BOOT_TARGET_DEVICES_DHCP(func) ++ ++#include <config_distro_bootcmd.h> ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ MEM_LAYOUT_ENV_SETTINGS \ ++ BOOTENV +diff -ruN u-boot-2021.10/include/configs/sun4i.h u-boot/include/configs/sun4i.h +--- u-boot-2021.10/include/configs/sun4i.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sun4i.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,6 +16,4 @@ + */ + #include <configs/sunxi-common.h> + +-#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/sun5i.h u-boot/include/configs/sun5i.h +--- u-boot-2021.10/include/configs/sun5i.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sun5i.h 2021-11-01 17:10:14.602907224 +0100 +@@ -16,6 +16,4 @@ + */ + #include <configs/sunxi-common.h> + +-#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/sun7i.h u-boot/include/configs/sun7i.h +--- u-boot-2021.10/include/configs/sun7i.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sun7i.h 2021-11-01 17:10:14.602907224 +0100 +@@ -20,6 +20,4 @@ + */ + #include <configs/sunxi-common.h> + +-#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/sunxi-common.h u-boot/include/configs/sunxi-common.h +--- u-boot-2021.10/include/configs/sunxi-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/sunxi-common.h 2021-11-01 17:10:14.602907224 +0100 +@@ -15,22 +15,6 @@ + #include <asm/arch/cpu.h> + #include <linux/stringify.h> + +-#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT +-/* +- * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the +- * expense of restricting some features, so the regular machine id values can +- * be used. +- */ +-# define CONFIG_MACH_TYPE_COMPAT_REV 0 +-#else +-/* +- * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. +- * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass +- * beyond the machine id check. +- */ +-# define CONFIG_MACH_TYPE_COMPAT_REV 1 +-#endif +- + #ifdef CONFIG_ARM64 + #define CONFIG_SYS_BOOTM_LEN (32 << 20) + #endif +@@ -61,7 +45,6 @@ + #ifdef CONFIG_MACH_SUN9I + #define SDRAM_OFFSET(x) 0x2##x + #define CONFIG_SYS_SDRAM_BASE 0x20000000 +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ + /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. */ +@@ -70,7 +53,6 @@ + #else + #define SDRAM_OFFSET(x) 0x4##x + #define CONFIG_SYS_SDRAM_BASE 0x40000000 +-#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ + /* V3s do not have enough memory to place code at 0x4a000000 */ + /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it +@@ -107,14 +89,8 @@ + #define CONFIG_SYS_64BIT_LBA + #endif + +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_INITRD_TAG +-#define CONFIG_SERIAL_TAG +- + #ifdef CONFIG_NAND_SUNXI + #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 8 + #endif + +@@ -137,14 +113,6 @@ + #define CONFIG_SYS_MMC_MAX_DEVICE 4 + #endif + +-#ifndef CONFIG_MACH_SUN8I_V3S +-/* 64MB of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) +-#else +-/* 2MB of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) +-#endif +- + /* + * Miscellaneous configurable options + */ +@@ -192,37 +160,6 @@ + #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ + #endif + +- +-/* I2C */ +-#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ +- defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ +- defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE +-#define CONFIG_SYS_I2C_MVTWSI +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SPEED 400000 +-#define CONFIG_SYS_I2C_SLAVE 0x7f +-#endif +-#endif +- +-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +-#define CONFIG_SYS_I2C_SOFT +-#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +-/* We use pin names in Kconfig and sunxi_name_to_gpio() */ +-#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda +-#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl +-#ifndef __ASSEMBLY__ +-extern int soft_i2c_gpio_sda; +-extern int soft_i2c_gpio_scl; +-#endif +-#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ +-#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ +-#else +-#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ +-#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ +-#endif +- + /* Ethernet support */ + + #ifdef CONFIG_USB_EHCI_HCD +diff -ruN u-boot-2021.10/include/configs/synquacer.h u-boot/include/configs/synquacer.h +--- u-boot-2021.10/include/configs/synquacer.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/synquacer.h 2021-11-01 17:10:14.602907224 +0100 +@@ -24,8 +24,6 @@ + * Boot info + */ + #define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ +-#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ + + /* + * Hardware drivers support +@@ -51,9 +49,6 @@ + #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) + #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) + +-#define CONFIG_BAUDRATE 115200 +-#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } +- + #define CONFIG_SYS_CBSIZE 1024 + #define CONFIG_SYS_MAXARGS 128 + #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +diff -ruN u-boot-2021.10/include/configs/T102xRDB.h u-boot/include/configs/T102xRDB.h +--- u-boot-2021.10/include/configs/T102xRDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/T102xRDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -26,7 +26,6 @@ + #endif + + #ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_PAD_TO 0x40000 + #define CONFIG_SPL_MAX_SIZE 0x28000 +@@ -43,11 +42,6 @@ + #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 + #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 + #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +-#if defined(CONFIG_TARGET_T1024RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg +-#elif defined(CONFIG_TARGET_T1023RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SPIFLASH +@@ -60,11 +54,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#if defined(CONFIG_TARGET_T1024RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg +-#elif defined(CONFIG_TARGET_T1023RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SDCARD +@@ -76,11 +65,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#if defined(CONFIG_TARGET_T1024RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg +-#elif defined(CONFIG_TARGET_T1023RDB) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg +-#endif + #endif + + #endif /* CONFIG_RAMBOOT_PBL */ +@@ -134,11 +118,9 @@ + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 100000000 + + /* + * These can be toggled for performance analysis, otherwise use default. +@@ -147,9 +129,7 @@ + #define CONFIG_BACKSIDE_L2_CACHE + #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E + #define CONFIG_BTB /* toggle branch predition */ +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -170,13 +150,8 @@ + #endif + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + + /* + * DDR Setup +@@ -187,7 +162,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + #if defined(CONFIG_TARGET_T1024RDB) +-#define CONFIG_DDR_SPD + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define SPD_EEPROM_ADDRESS 0x51 + #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +@@ -268,7 +242,6 @@ + #endif + + /* NAND Flash on IFC */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0xff800000 + #ifdef CONFIG_PHYS_64BIT + #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +@@ -290,7 +263,6 @@ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + #elif defined(CONFIG_TARGET_T1023RDB) + #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ +@@ -299,10 +271,8 @@ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + #endif + +-#define CONFIG_SYS_NAND_ONFI_DETECTION + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -392,7 +362,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + + /* Serial Port */ + #define CONFIG_SYS_NS16550_SERIAL +@@ -422,20 +391,7 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + +-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ + #define I2C_PCA6408_BUS_NUM 1 + #define I2C_PCA6408_ADDR 0x20 + +@@ -560,14 +516,6 @@ + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) + #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +-#elif defined(CONFIG_MTD_RAW_NAND) +-#if defined(CONFIG_TARGET_T1024RDB) +-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +-#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +-#elif defined(CONFIG_TARGET_T1023RDB) +-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +-#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +-#endif + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * Slave has no ucode locally, it can fetch this from remote. When implementing +@@ -615,7 +563,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -625,17 +572,12 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ + #define CONFIG_ROOTPATH "/opt/nfsroot" + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +-#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ + #define __USB_PHY_TYPE utmi + + #ifdef CONFIG_ARCH_T1024 +@@ -668,7 +610,7 @@ + "fdtaddr=1e00000\0" \ + "bdev=sda3\0" + +-#define CONFIG_LINUX \ ++#define LINUXBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ +@@ -676,7 +618,7 @@ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -685,7 +627,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_LINUX ++#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/T104xRDB.h u-boot/include/configs/T104xRDB.h +--- u-boot-2021.10/include/configs/T104xRDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/T104xRDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -15,14 +15,6 @@ + #include <asm/config_mpc85xx.h> + + #ifdef CONFIG_RAMBOOT_PBL +- +-#ifndef CONFIG_NXP_ESBC +-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +-#else +-#define CONFIG_SYS_FSL_PBL_PBI \ +- $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg +-#endif +- + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_PAD_TO 0x40000 + #define CONFIG_SPL_MAX_SIZE 0x28000 +@@ -49,26 +41,6 @@ + #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 + #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 + #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +-#ifdef CONFIG_TARGET_T1040RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB_PI +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1040D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SPIFLASH +@@ -81,26 +53,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#ifdef CONFIG_TARGET_T1040RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB_PI +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1040D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SDCARD +@@ -112,26 +64,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#ifdef CONFIG_TARGET_T1040RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB_PI +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1040D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg +-#endif +-#ifdef CONFIG_TARGET_T1042D4RDB +-#define CONFIG_SYS_FSL_PBL_RCW \ +-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg +-#endif + #endif + + #endif +@@ -164,7 +96,6 @@ + #endif + + #define CONFIG_SYS_CLK_FREQ 100000000 +-#define CONFIG_DDR_CLK_FREQ 66666666 + + /* + * These can be toggled for performance analysis, otherwise use default. +@@ -173,9 +104,7 @@ + #define CONFIG_BACKSIDE_L2_CACHE + #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E + #define CONFIG_BTB /* toggle branch predition */ +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -211,8 +140,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +-#define CONFIG_DDR_SPD +- + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define SPD_EEPROM_ADDRESS 0x51 + +@@ -309,7 +236,6 @@ + #define CONFIG_SYS_CS2_FTIM3 0x0 + + /* NAND Flash on IFC */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0xff800000 + #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +@@ -328,8 +254,6 @@ + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -348,8 +272,6 @@ + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +- + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT + #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +@@ -421,7 +343,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + /* Serial Port - controlled on board with jumper J8 + * open - index 2 +@@ -452,26 +373,7 @@ + #endif + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif + +-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ + /* I2C bus multiplexer */ + #define I2C_MUX_PCA_ADDR 0x70 + #define I2C_MUX_CH_DEFAULT 0x8 +@@ -613,8 +515,6 @@ + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +-#elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) + #else + #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 + #endif +@@ -623,8 +523,6 @@ + #define CONFIG_SYS_QE_FW_ADDR 0x130000 + #elif defined(CONFIG_SDCARD) + #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +-#elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) + #else + #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 + #endif +@@ -676,7 +574,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -686,10 +583,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Dynamic MTD Partition support with mtdparts + */ +@@ -701,9 +594,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- + #define __USB_PHY_TYPE utmi + #define RAMDISKFILE "t104xrdb/ramdisk.uboot" + +@@ -746,7 +636,7 @@ + "fdtfile=" __stringify(FDTFILE) "\0" \ + "bdev=sda3\0" + +-#define CONFIG_LINUX \ ++#define LINUXBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ +@@ -754,14 +644,14 @@ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -770,7 +660,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -778,7 +668,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_LINUX ++#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/T208xQDS.h u-boot/include/configs/T208xQDS.h +--- u-boot-2021.10/include/configs/T208xQDS.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/T208xQDS.h 2021-11-01 17:10:14.572908865 +0100 +@@ -29,8 +29,6 @@ + #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS + + #ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg +- + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_PAD_TO 0x40000 + #define CONFIG_SPL_MAX_SIZE 0x28000 +@@ -47,9 +45,6 @@ + #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 + #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 + #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +-#if defined(CONFIG_ARCH_T2080) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SPIFLASH +@@ -62,9 +57,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#if defined(CONFIG_ARCH_T2080) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg +-#endif + #endif + + #ifdef CONFIG_SDCARD +@@ -76,9 +68,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#if defined(CONFIG_ARCH_T2080) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg +-#endif + #endif + + #endif /* CONFIG_RAMBOOT_PBL */ +@@ -101,19 +90,15 @@ + */ + #define CONFIG_SYS_CACHE_STASHING + #define CONFIG_BTB /* toggle branch predition */ +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + + /* + * Config the L3 Cache as L3 SRAM +@@ -130,11 +115,8 @@ + #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + + /* + * DDR Setup +@@ -144,7 +126,6 @@ + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + #define CONFIG_DIMM_SLOTS_PER_CTLR 2 + #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +-#define CONFIG_DDR_SPD + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ + #define SPD_EEPROM_ADDRESS1 0x51 +@@ -233,7 +214,6 @@ + #define CONFIG_SYS_CS3_FTIM3 0x0 + + /* NAND Flash on IFC */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0xff800000 + #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +@@ -252,8 +232,6 @@ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -271,7 +249,6 @@ + #define CONFIG_SYS_NAND_DDR_LAW 11 + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +@@ -352,7 +329,6 @@ + GENERATED_GBL_DATA_SIZE) + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + /* + * Serial Port +@@ -370,23 +346,6 @@ + /* + * I2C + */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +-#define CONFIG_SYS_FSL_I2C_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +-#endif +- +-#define CONFIG_SYS_I2C_FSL + + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ + #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +@@ -537,8 +496,6 @@ + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +-#elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * Slave has no ucode locally, it can fetch this from remote. When implementing +@@ -613,7 +570,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -623,11 +579,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +-#endif +- + /* + * Environment Configuration + */ +@@ -635,8 +586,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 + #define __USB_PHY_TYPE utmi + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -664,7 +613,7 @@ + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +-#define CONFIG_PROOF_POINTS \ ++#define PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ +@@ -676,11 +625,11 @@ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +-#define CONFIG_HVBOOT \ ++#define HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +-#define CONFIG_ALU \ ++#define ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ +@@ -692,7 +641,7 @@ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +-#define CONFIG_LINUX \ ++#define LINUXBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ +@@ -700,14 +649,14 @@ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -716,7 +665,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -724,7 +673,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_LINUX ++#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/T208xRDB.h u-boot/include/configs/T208xRDB.h +--- u-boot-2021.10/include/configs/T208xRDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/T208xRDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -24,8 +24,6 @@ + #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS + + #ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg +- + #define CONFIG_SPL_FLUSH_IMAGE + #define CONFIG_SPL_PAD_TO 0x40000 + #define CONFIG_SPL_MAX_SIZE 0x28000 +@@ -42,7 +40,6 @@ + #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 + #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 + #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg + #endif + + #ifdef CONFIG_SPIFLASH +@@ -55,7 +52,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg + #endif + + #ifdef CONFIG_SDCARD +@@ -67,7 +63,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg + #endif + + #endif /* CONFIG_RAMBOOT_PBL */ +@@ -90,19 +85,15 @@ + */ + #define CONFIG_SYS_CACHE_STASHING + #define CONFIG_BTB /* toggle branch predition */ +-#define CONFIG_DDR_ECC + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + #define CONFIG_SYS_CLK_FREQ 66660000 +-#define CONFIG_DDR_CLK_FREQ 133330000 + + /* + * Config the L3 Cache as L3 SRAM +@@ -119,11 +110,8 @@ + #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + + /* EEPROM */ +-#define CONFIG_ID_EEPROM + #define CONFIG_SYS_I2C_EEPROM_NXID + #define CONFIG_SYS_EEPROM_BUS_NUM 0 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + + /* + * DDR Setup +@@ -133,7 +121,6 @@ + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +-#define CONFIG_DDR_SPD + #define CONFIG_SYS_SPD_BUS_NUM 0 + #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ + #define SPD_EEPROM_ADDRESS1 0x51 +@@ -201,7 +188,6 @@ + #define CONFIG_SYS_CS2_FTIM3 0x0 + + /* NAND Flash on IFC */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_BASE 0xff800000 + #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +@@ -220,8 +206,6 @@ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -239,7 +223,6 @@ + #define CONFIG_SYS_NAND_DDR_LAW 11 + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +@@ -304,7 +287,6 @@ + GENERATED_GBL_DATA_SIZE) + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + /* + * Serial Port +@@ -322,26 +304,6 @@ + /* + * I2C + */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +-#define CONFIG_SYS_FSL_I2C_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +-#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +- +-#define CONFIG_SYS_I2C_FSL + + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ + #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +@@ -488,8 +450,6 @@ + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) + +-#elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * Slave has no ucode locally, it can fetch this from remote. When implementing +@@ -565,7 +525,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -575,11 +534,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +-#endif +- + /* + * Environment Configuration + */ +@@ -587,8 +541,6 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 + #define __USB_PHY_TYPE utmi + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -616,7 +568,7 @@ + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +-#define CONFIG_PROOF_POINTS \ ++#define PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ +@@ -628,11 +580,11 @@ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +-#define CONFIG_HVBOOT \ ++#define HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +-#define CONFIG_ALU \ ++#define ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ +@@ -644,7 +596,7 @@ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +-#define CONFIG_LINUX \ ++#define LINUXBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ +@@ -652,14 +604,14 @@ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -668,7 +620,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -676,7 +628,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_LINUX ++#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/T4240RDB.h u-boot/include/configs/T4240RDB.h +--- u-boot-2021.10/include/configs/T4240RDB.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/T4240RDB.h 2021-11-01 17:10:14.572908865 +0100 +@@ -18,7 +18,6 @@ + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + + #ifdef CONFIG_RAMBOOT_PBL +-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg + #ifndef CONFIG_SDCARD + #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE + #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +@@ -38,7 +37,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_SYS_MPC85XX_NO_RESETVEC + #endif +-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg + #endif + + #ifdef CONFIG_SPL_BUILD +@@ -50,8 +48,6 @@ + #endif + #endif /* CONFIG_RAMBOOT_PBL */ + +-#define CONFIG_DDR_ECC +- + /* High Level Configuration Options */ + #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ + +@@ -72,7 +68,6 @@ + #define CONFIG_SYS_CACHE_STASHING + #define CONFIG_BTB /* toggle branch predition */ + #ifdef CONFIG_DDR_ECC +-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER + #define CONFIG_MEM_INIT_VALUE 0xdeadbeef + #endif + +@@ -102,8 +97,6 @@ + #define CONFIG_DIMM_SLOTS_PER_CTLR 1 + #define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +-#define CONFIG_DDR_SPD +- + /* + * IFC Definitions + */ +@@ -135,7 +128,6 @@ + #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + + #define CONFIG_SYS_MONITOR_LEN (768 * 1024) +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + + /* Serial Port - controlled on board with jumper J8 + * open - index 2 +@@ -154,18 +146,6 @@ + #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + + /* I2C */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +-#else +-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +-#endif +- +-#define CONFIG_SYS_I2C_FSL + + /* + * General PCI +@@ -225,7 +205,6 @@ + /* + * Miscellaneous configurable options + */ +-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + + /* + * For booting Linux, the board info and command line data +@@ -235,10 +214,6 @@ + #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ + #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +-#ifdef CONFIG_CMD_KGDB +-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +-#endif +- + /* + * Environment Configuration + */ +@@ -246,19 +221,14 @@ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +-/* default location for tftp and bootm */ +-#define CONFIG_LOADADDR 1000000 +- +-#define CONFIG_HVBOOT \ ++#define HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + + #define CONFIG_SYS_CLK_FREQ 66666666 +-#define CONFIG_DDR_CLK_FREQ 133333333 + + #ifndef __ASSEMBLY__ + unsigned long get_board_sys_clk(void); +-unsigned long get_board_ddr_clk(void); + #endif + + /* +@@ -314,7 +284,6 @@ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + + /* NAND Flash on IFC */ +-#define CONFIG_NAND_FSL_IFC + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 + #define CONFIG_SYS_NAND_MAX_OOBFREE 2 + #define CONFIG_SYS_NAND_BASE 0xff800000 +@@ -335,8 +304,6 @@ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ + +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- + /* ONFI NAND Flash mode0 Timing Params */ + #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ +@@ -355,8 +322,6 @@ + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + +-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +- + #if defined(CONFIG_MTD_RAW_NAND) + #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT + #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +@@ -429,8 +394,6 @@ + #endif + + /* I2C */ +-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ + #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +@@ -507,8 +470,6 @@ + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ + #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +-#elif defined(CONFIG_MTD_RAW_NAND) +-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) + #else + #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 + #endif +@@ -600,11 +561,11 @@ + "fdtfile=t4240rdb/t4240rdb.dtb\0" \ + "bdev=sda3\0" + +-#define CONFIG_HVBOOT \ ++#define HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +-#define CONFIG_LINUX \ ++#define LINUXBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ +@@ -612,14 +573,14 @@ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_HDBOOT \ ++#define HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +@@ -628,7 +589,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ +@@ -636,7 +597,7 @@ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +-#define CONFIG_BOOTCOMMAND CONFIG_LINUX ++#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND + + #include <asm/fsl_secure_boot.h> + +diff -ruN u-boot-2021.10/include/configs/tam3517-common.h u-boot/include/configs/tam3517-common.h +--- u-boot-2021.10/include/configs/tam3517-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tam3517-common.h 2021-11-01 17:10:14.602907224 +0100 +@@ -20,16 +20,6 @@ + #define V_OSCK 26000000 /* Clock output from T2 */ + #define V_SCLK (V_OSCK >> 1) + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +-#define CONFIG_REVISION_TAG +- +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ +- 2 * 1024 * 1024) + /* + * DDR related + */ +@@ -53,12 +43,7 @@ + + #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +-/* EHCI */ +-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 + +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ + #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 + + /* +@@ -78,10 +63,6 @@ + + #define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +-/* memtest works on */ +- +-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ +- /* address */ + + /* + * AM3517 has 12 GP timers, they can be driven by the system clock +@@ -145,22 +126,14 @@ + #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + + /* NAND boot config */ +-#define CONFIG_SYS_NAND_PAGE_COUNT 64 +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW + + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 + + /* Setup MTD for NAND on the SOM */ +@@ -249,7 +222,7 @@ + + #define TAM3517_READ_EEPROM(info, ret) \ + do { \ +- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ + (void *)info, sizeof(*info))) \ + ret = 1; \ +diff -ruN u-boot-2021.10/include/configs/taurus.h u-boot/include/configs/taurus.h +--- u-boot-2021.10/include/configs/taurus.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/taurus.h 2021-11-01 17:10:14.602907224 +0100 +@@ -33,11 +33,6 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ + + /* Misc CPU related */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + + /* general purpose I/O */ + #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +@@ -102,9 +97,6 @@ + /* SPL related */ + #endif + +-/* load address */ +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 +- + /* bootstrap in spi flash , u-boot + env + linux in nandflash */ + + #ifndef CONFIG_SPL_BUILD +@@ -157,11 +149,6 @@ + "upgrade_available=0\0" + #endif + #endif /* #ifndef CONFIG_SPL_BUILD */ +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN \ +- ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000) + + /* Defines for SPL */ + #define CONFIG_SPL_MAX_SIZE (31 * SZ_512) +@@ -177,21 +164,13 @@ + #define CONFIG_SYS_USE_NANDFLASH 1 + #define CONFIG_SPL_NAND_RAW_ONLY + #define CONFIG_SPL_NAND_SOFTECC +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 + #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE + + #define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) +-#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +-#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCSIZE 256 + #define CONFIG_SYS_NAND_ECCBYTES 3 +-#define CONFIG_SYS_NAND_OOBSIZE 64 + #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +diff -ruN u-boot-2021.10/include/configs/tb100.h u-boot/include/configs/tb100.h +--- u-boot-2021.10/include/configs/tb100.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tb100.h 2021-11-01 17:10:14.602907224 +0100 +@@ -20,9 +20,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_MALLOC_LEN SZ_128K + #define CONFIG_SYS_BOOTM_LEN SZ_32M +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 + + /* + * UART configuration +@@ -51,7 +49,6 @@ + * Environment configuration + */ + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + /* + * Console configuration +diff -ruN u-boot-2021.10/include/configs/tbs2910.h u-boot/include/configs/tbs2910.h +--- u-boot-2021.10/include/configs/tbs2910.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tbs2910.h 2021-11-01 17:10:14.602907224 +0100 +@@ -12,8 +12,6 @@ + + /* General configuration */ + +-#define CONFIG_MACH_TYPE 3980 +- + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -26,8 +24,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +- + #define CONFIG_SYS_BOOTMAPSZ 0x10000000 + + /* Serial console */ +diff -ruN u-boot-2021.10/include/configs/tec-ng.h u-boot/include/configs/tec-ng.h +--- u-boot-2021.10/include/configs/tec-ng.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tec-ng.h 2021-11-01 17:10:14.606240375 +0100 +@@ -22,11 +22,6 @@ + #define CONFIG_TEGRA_SLINK_CTRLS 6 + #define CONFIG_SPI_FLASH_SIZE (4 << 20) + +-/* Tag support */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- + #include "tegra-common-post.h" + + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/tegra114-common.h u-boot/include/configs/tegra114-common.h +--- u-boot-2021.10/include/configs/tegra114-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra114-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -45,11 +45,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x81000000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" +diff -ruN u-boot-2021.10/include/configs/tegra124-common.h u-boot/include/configs/tegra124-common.h +--- u-boot-2021.10/include/configs/tegra124-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra124-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -47,11 +47,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x81000000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" +diff -ruN u-boot-2021.10/include/configs/tegra186-common.h u-boot/include/configs/tegra186-common.h +--- u-boot-2021.10/include/configs/tegra186-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra186-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -17,9 +17,6 @@ + * Physical Memory Map + */ + +-/* Generic Interrupt Controller */ +-#define CONFIG_GICV2 +- + #undef FDTFILE + #define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ +@@ -50,11 +47,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x80080000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +diff -ruN u-boot-2021.10/include/configs/tegra20-common.h u-boot/include/configs/tegra20-common.h +--- u-boot-2021.10/include/configs/tegra20-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra20-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -46,11 +46,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x01000000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x03000000\0" \ + "ramdisk_addr_r=0x03100000\0" +@@ -82,6 +81,5 @@ + #define CONFIG_EHCI_IS_TDI + + #define CONFIG_SYS_NAND_SELF_INIT +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + #endif /* _TEGRA20_COMMON_H_ */ +diff -ruN u-boot-2021.10/include/configs/tegra210-common.h u-boot/include/configs/tegra210-common.h +--- u-boot-2021.10/include/configs/tegra210-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra210-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -14,9 +14,6 @@ + */ + #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +-/* Generic Interrupt Controller */ +-#define CONFIG_GICV2 +- + /* + * Memory layout for where various images get loaded by boot scripts: + * +@@ -41,11 +38,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x80080000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83200000\0" +diff -ruN u-boot-2021.10/include/configs/tegra30-common.h u-boot/include/configs/tegra30-common.h +--- u-boot-2021.10/include/configs/tegra30-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra30-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -42,11 +42,10 @@ + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +-#define CONFIG_LOADADDR 0x81000000 + #define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" +diff -ruN u-boot-2021.10/include/configs/tegra-common.h u-boot/include/configs/tegra-common.h +--- u-boot-2021.10/include/configs/tegra-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra-common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -22,8 +22,6 @@ + #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE + #endif + +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +- + /* Environment */ + + /* +diff -ruN u-boot-2021.10/include/configs/tegra-common-post.h u-boot/include/configs/tegra-common-post.h +--- u-boot-2021.10/include/configs/tegra-common-post.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tegra-common-post.h 2021-11-01 17:10:14.606240375 +0100 +@@ -7,17 +7,6 @@ + #ifndef __TEGRA_COMMON_POST_H + #define __TEGRA_COMMON_POST_H + +-/* +- * Size of malloc() pool +- */ +-#ifdef CONFIG_DFU_OVER_USB +-#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ +- CONFIG_SYS_DFU_DATA_BUF_SIZE + \ +- CONFIG_SYS_DFU_MAX_FILE_SIZE) +-#else +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +-#endif +- + #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ + + #ifndef CONFIG_SPL_BUILD +@@ -81,8 +70,6 @@ + #define BOARD_EXTRA_ENV_SETTINGS + #endif + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + #ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS + #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS + #endif +@@ -111,13 +98,6 @@ + /* overrides for SPL build here */ + #ifdef CONFIG_SPL_BUILD + +-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +- +-/* remove I2C support */ +-#ifdef CONFIG_SYS_I2C_TEGRA +-#undef CONFIG_SYS_I2C_TEGRA +-#endif +- + /* remove USB */ + #ifdef CONFIG_USB_EHCI_TEGRA + #undef CONFIG_USB_EHCI_TEGRA +diff -ruN u-boot-2021.10/include/configs/theadorable.h u-boot/include/configs/theadorable.h +--- u-boot-2021.10/include/configs/theadorable.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/theadorable.h 2021-11-01 17:10:14.606240375 +0100 +@@ -6,6 +6,8 @@ + #ifndef _CONFIG_THEADORABLE_H + #define _CONFIG_THEADORABLE_H + ++#include <linux/sizes.h> ++ + /* + * High Level Configuration Options (easy to change) + */ +@@ -23,12 +25,8 @@ + */ + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MVTWSI + #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE + #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE +-#define CONFIG_SYS_I2C_SLAVE 0x0 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* USB/EHCI configuration */ + #define CONFIG_EHCI_IS_TDI +@@ -93,6 +91,6 @@ + #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + + /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +-#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ ++#define CONFIG_SYS_SDRAM_SIZE SZ_2G + + #endif /* _CONFIG_THEADORABLE_H */ +diff -ruN u-boot-2021.10/include/configs/thuban.h u-boot/include/configs/thuban.h +--- u-boot-2021.10/include/configs/thuban.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/thuban.h 2021-11-01 17:10:14.606240375 +0100 +@@ -27,10 +27,6 @@ + /* Physical Memory Map */ + #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +-/* I2C Configuration */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + #define EEPROM_ADDR_DDR3 0x90 + #define EEPROM_ADDR_CHIP 0x120 + +diff -ruN u-boot-2021.10/include/configs/thunderx_88xx.h u-boot/include/configs/thunderx_88xx.h +--- u-boot-2021.10/include/configs/thunderx_88xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/thunderx_88xx.h 2021-11-01 17:10:14.606240375 +0100 +@@ -25,9 +25,6 @@ + /* Generic Timer Definitions */ + #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +- + /* PL011 Serial Configuration */ + + #define CONFIG_PL011_CLOCK 24000000 +@@ -42,7 +39,6 @@ + #define CONFIG_BOOTP_BOOTFILESIZE + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + + /* Physical Memory Map */ + #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +diff -ruN u-boot-2021.10/include/configs/ti814x_evm.h u-boot/include/configs/ti814x_evm.h +--- u-boot-2021.10/include/configs/ti814x_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti814x_evm.h 2021-11-01 17:10:14.606240375 +0100 +@@ -18,13 +18,6 @@ + + #include <asm/arch/omap.h> + +-#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +-#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG /* for ramdisk support */ +- + /* commands to include */ + + #define CONFIG_EXTRA_ENV_SETTINGS \ +@@ -87,8 +80,6 @@ + /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 512 + +-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ +- + /** + * Physical Memory Map + */ +@@ -137,9 +128,6 @@ + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + /* Ethernet */ + #define CONFIG_NET_RETRY_COUNT 10 +diff -ruN u-boot-2021.10/include/configs/ti816x_evm.h u-boot/include/configs/ti816x_evm.h +--- u-boot-2021.10/include/configs/ti816x_evm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti816x_evm.h 2021-11-01 17:10:14.606240375 +0100 +@@ -12,8 +12,6 @@ + #include <configs/ti_armv7_omap.h> + #include <asm/arch/omap.h> + +-#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ +@@ -59,14 +57,7 @@ + /* NAND: SPL related configs */ + + /* NAND: device related configs */ +-#define CONFIG_SYS_NAND_5_ADDR_CYCLE +-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ +- CONFIG_SYS_NAND_PAGE_SIZE) +-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +-#define CONFIG_SYS_NAND_OOBSIZE 64 +-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) + /* NAND: driver related configs */ +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS + #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ +@@ -77,10 +68,6 @@ + + #define CONFIG_SYS_NAND_ECCSIZE 512 + #define CONFIG_SYS_NAND_ECCBYTES 14 +-#define CONFIG_SYS_NAND_ONFI_DETECTION +-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + + /* SPL */ + /* Defines for SPL */ +@@ -92,9 +79,6 @@ + /* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#ifndef CONFIG_SPL_BUILD +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + /* + * Disable MMC DM for SPL build and can be re-enabled after adding +diff -ruN u-boot-2021.10/include/configs/ti_am335x_common.h u-boot/include/configs/ti_am335x_common.h +--- u-boot-2021.10/include/configs/ti_am335x_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti_am335x_common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -46,9 +46,6 @@ + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + /* + * When building U-Boot such that there is no previous loader +diff -ruN u-boot-2021.10/include/configs/ti_armv7_common.h u-boot/include/configs/ti_armv7_common.h +--- u-boot-2021.10/include/configs/ti_armv7_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti_armv7_common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -16,19 +16,6 @@ + #ifndef __CONFIG_TI_ARMV7_COMMON_H__ + #define __CONFIG_TI_ARMV7_COMMON_H__ + +-/* Support both device trees and ATAGs. */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-/* +- * Our DDR memory always starts at 0x80000000 and U-Boot shall have +- * relocated itself to higher in memory by the time this value is used. +- * However, set this to a 32MB offset to allow for easier Linux kernel +- * booting as the default is often used as the kernel load address. +- */ +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + /* + * We setup defaults based on constraints from the Linux kernel, which should + * also be safe elsewhere. We have the default load at 32MB into DDR (for +@@ -87,9 +74,6 @@ + #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + + /* If DM_I2C, enable non-DM I2C support */ +-#if !CONFIG_IS_ENABLED(DM_I2C) +-#define CONFIG_SYS_I2C_LEGACY +-#endif + + /* + * The following are general good-enough settings for U-Boot. We set a +@@ -100,7 +84,6 @@ + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + + /* As stated above, the following choices are optional. */ + +diff -ruN u-boot-2021.10/include/configs/ti_armv7_keystone2.h u-boot/include/configs/ti_armv7_keystone2.h +--- u-boot-2021.10/include/configs/ti_armv7_keystone2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti_armv7_keystone2.h 2021-11-01 17:10:14.606240375 +0100 +@@ -9,10 +9,7 @@ + #ifndef __CONFIG_KS2_EVM_H + #define __CONFIG_KS2_EVM_H + +-#define CONFIG_SOC_KEYSTONE +- + /* U-Boot Build Configuration */ +-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ + + /* SoC Configuration */ + #define CONFIG_SPL_TARGET "u-boot-spi.gph" +@@ -71,37 +68,6 @@ + #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 + #define CONFIG_SYS_SGMII_RATESCALE 2 + +-/* Keyston Navigator Configuration */ +-#define CONFIG_TI_KSNAV +-#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS +-#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE +-#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE +-#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE +-#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE +-#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE +-#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE +-#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE +-#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE +-#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE +-#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE +-#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE +-#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM +-#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM +- +-/* NETCP pktdma */ +-#define CONFIG_KSNAV_PKTDMA_NETCP +-#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE +-#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE +-#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM +-#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE +-#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM +-#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE +-#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE +-#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM +-#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE +-#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE +-#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE +- + /* Keystone net */ + #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR + #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +@@ -109,8 +75,6 @@ + #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE + #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES + +-#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE +- + /* I2C Configuration */ + #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 + #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +@@ -120,15 +84,8 @@ + #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ + + /* EEPROM definitions */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +-#define CONFIG_ENV_EEPROM_IS_ON_I2C + + /* NAND Configuration */ +-#define CONFIG_KEYSTONE_RBL_NAND +-#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET + #define CONFIG_SYS_NAND_MASK_CLE 0x4000 + #define CONFIG_SYS_NAND_MASK_ALE 0x2000 + #define CONFIG_SYS_NAND_CS 2 +@@ -137,7 +94,6 @@ + #define CONFIG_SYS_NAND_LARGEPAGE + #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + + #define DFU_ALT_INFO_MMC \ +@@ -155,7 +111,6 @@ + #define CONFIG_TIMESTAMP + + /* EDMA3 */ +-#define CONFIG_TI_EDMA3 + + #define KERNEL_MTD_PARTS \ + "mtdparts=" \ +@@ -187,7 +142,7 @@ + + #define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ +- CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ ++ ENV_KS2_BOARD_SETTINGS \ + DFUARGS \ + "bootdir=/boot\0" \ + "tftp_root=/\0" \ +diff -ruN u-boot-2021.10/include/configs/ti_omap4_common.h u-boot/include/configs/ti_omap4_common.h +--- u-boot-2021.10/include/configs/ti_omap4_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ti_omap4_common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -118,7 +118,6 @@ + + #ifdef CONFIG_SPL_BUILD + /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ +-#undef CONFIG_SYS_I2C_LEGACY + #endif + + #endif /* __CONFIG_TI_OMAP4_COMMON_H */ +diff -ruN u-boot-2021.10/include/configs/total_compute.h u-boot/include/configs/total_compute.h +--- u-boot-2021.10/include/configs/total_compute.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/total_compute.h 2021-11-01 17:10:14.606240375 +0100 +@@ -18,14 +18,10 @@ + + #define UART0_BASE 0x7ff80000 + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) +- + /* PL011 Serial Configuration */ + #define CONFIG_PL011_CLOCK 7372800 + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR 0x90000000 + + /* Physical Memory Map */ + #define PHYS_SDRAM_1 0x80000000 +@@ -34,9 +30,7 @@ + #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +-#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000 + #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000 + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x20000000\0" \ +diff -ruN u-boot-2021.10/include/configs/tplink_wdr4300.h u-boot/include/configs/tplink_wdr4300.h +--- u-boot-2021.10/include/configs/tplink_wdr4300.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tplink_wdr4300.h 2021-11-01 17:10:14.606240375 +0100 +@@ -12,12 +12,9 @@ + + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SYS_MALLOC_LEN 0x40000 + #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + + #define CONFIG_SYS_SDRAM_BASE 0xa0000000 +-#define CONFIG_SYS_LOAD_ADDR 0xa1000000 +-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + + #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +@@ -28,8 +25,6 @@ + * Serial Port + */ + #define CONFIG_SYS_NS16550_CLK 40000000 +-#define CONFIG_SYS_BAUDRATE_TABLE \ +- {9600, 19200, 38400, 57600, 115200} + + #define CONFIG_BOOTCOMMAND \ + "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" +diff -ruN u-boot-2021.10/include/configs/tqma6.h u-boot/include/configs/tqma6.h +--- u-boot-2021.10/include/configs/tqma6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tqma6.h 2021-11-01 17:10:14.606240375 +0100 +@@ -36,17 +36,12 @@ + + /* I2C Configs */ + #define CONFIG_I2C_MULTI_BUS +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* I2C EEPROM (M24C64) */ +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ + #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 + + #if !defined(CONFIG_DM_PMIC) +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #define TQMA6_PFUZE100_I2C_BUS 2 +@@ -65,9 +60,6 @@ + + #define CONFIG_ARP_TIMEOUT 200UL + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) +- + #if defined(CONFIG_TQMA6X_MMC_BOOT) + + #define TQMA6_UBOOT_OFFSET SZ_1K +diff -ruN u-boot-2021.10/include/configs/tqma6_wru4.h u-boot/include/configs/tqma6_wru4.h +--- u-boot-2021.10/include/configs/tqma6_wru4.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/tqma6_wru4.h 2021-11-01 17:10:14.606240375 +0100 +@@ -30,6 +30,5 @@ + #define CONFIG_SYS_BOOTCOUNT_BE + + /* I2C */ +-#define CONFIG_SYS_I2C_LEGACY + + #endif /* __CONFIG_TQMA6_WRU4_H */ +diff -ruN u-boot-2021.10/include/configs/trats2.h u-boot/include/configs/trats2.h +--- u-boot-2021.10/include/configs/trats2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/trats2.h 2021-11-01 17:10:14.606240375 +0100 +@@ -24,8 +24,6 @@ + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + + #define CONFIG_BOOTCOMMAND "run autoboot" + +@@ -125,7 +123,7 @@ + "setenv spl_imgsize;" \ + "setenv spl_imgaddr;" \ + "setenv spl_addr_tmp;\0" \ +- CONFIG_EXTRA_ENV_ITB \ ++ ENV_ITB \ + "fdtaddr=40800000\0" \ + + /* GPT */ +diff -ruN u-boot-2021.10/include/configs/trats.h u-boot/include/configs/trats.h +--- u-boot-2021.10/include/configs/trats.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/trats.h 2021-11-01 17:10:14.606240375 +0100 +@@ -26,11 +26,6 @@ + #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ + +-/* memtest works on */ +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) +- +-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS +- + #define CONFIG_BOOTCOMMAND "run autoboot" + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ +@@ -40,9 +35,6 @@ + + #define CONFIG_SYS_MONITOR_BASE 0x00000000 + +-#define CONFIG_BOOTBLOCK "10" +-#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" +- + /* Tizen - partitions definitions */ + #define PARTS_CSA "csa-mmc" + #define PARTS_BOOT "boot" +@@ -94,7 +86,7 @@ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ +- "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ ++ "${netmask}:generic:usb0:off ${console} ${meminfo}" \ + "; run bootk\0" \ + "ramfsboot=" \ + "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ +@@ -112,7 +104,7 @@ + "console=console=ttySAC2,115200n8\0" \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ +- "bootblock=" CONFIG_BOOTBLOCK "\0" \ ++ "bootblock=10\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ + "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ +@@ -141,7 +133,7 @@ + "setenv spl_imgsize;" \ + "setenv spl_imgaddr;" \ + "setenv spl_addr_tmp;\0" \ +- CONFIG_EXTRA_ENV_ITB \ ++ ENV_ITB \ + "fdtaddr=40800000\0" \ + + /* Falcon mode definitions */ +diff -ruN u-boot-2021.10/include/configs/trimslice.h u-boot/include/configs/trimslice.h +--- u-boot-2021.10/include/configs/trimslice.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/trimslice.h 2021-11-01 17:10:14.606240375 +0100 +@@ -18,8 +18,6 @@ + #define CONFIG_TEGRA_UARTA_GPU + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE +- + /* SPI */ + + /* Environment in SPI */ +diff -ruN u-boot-2021.10/include/configs/turris_mox.h u-boot/include/configs/turris_mox.h +--- u-boot-2021.10/include/configs/turris_mox.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/turris_mox.h 2021-11-01 17:10:14.606240375 +0100 +@@ -30,26 +30,11 @@ + 4000000, 4500000, 5000000, 5500000, \ + 6000000 } + +-/* +- * For booting Linux, the board info and command line data +- * have to be in the first 8 MB of memory, since this is +- * the maximum mapped by the Linux kernel during initialization. +- */ +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_INITRD_TAG /* enable INITRD tag */ +-#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ +- + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ + + /* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ +- +-/* + * Other required minimal configurations + */ +-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +@@ -60,7 +45,6 @@ + * I2C + */ + #define CONFIG_I2C_MV +-#define CONFIG_SYS_I2C_SLAVE 0x0 + + /* Environment in SPI NOR flash */ + +diff -ruN u-boot-2021.10/include/configs/udoo.h u-boot/include/configs/udoo.h +--- u-boot-2021.10/include/configs/udoo.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/udoo.h 2021-11-01 17:10:14.606240375 +0100 +@@ -12,12 +12,6 @@ + + #include "imx6_spl.h" + +-/* Provide the MACH_TYPE value that the vendor kernel requires. */ +-#define CONFIG_MACH_TYPE 4800 +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART2_BASE + + /* SATA Configs */ +@@ -43,10 +37,10 @@ + "setenv fdtfile imx6dl-udoo.dtb; fi; " \ + "if test ${fdtfile} = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + BOOTENV + + #define BOOT_TARGET_DEVICES(func) \ +diff -ruN u-boot-2021.10/include/configs/udoo_neo.h u-boot/include/configs/udoo_neo.h +--- u-boot-2021.10/include/configs/udoo_neo.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/udoo_neo.h 2021-11-01 17:10:14.606240375 +0100 +@@ -14,9 +14,6 @@ + + #include "imx6_spl.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +- + /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +@@ -45,10 +42,10 @@ + "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdtfile = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi\0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x84000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + BOOTENV + + #define BOOT_TARGET_DEVICES(func) \ +@@ -70,15 +67,7 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE3000 + #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + #define PFUZE3000_I2C_BUS 0 +diff -ruN u-boot-2021.10/include/configs/uniphier.h u-boot/include/configs/uniphier.h +--- u-boot-2021.10/include/configs/uniphier.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/uniphier.h 2021-11-01 17:10:14.606240375 +0100 +@@ -39,8 +39,6 @@ + #define BOOTENV + #endif + +-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +- + #define CONFIG_TIMESTAMP + + #define CONFIG_SYS_MONITOR_BASE 0 +@@ -56,10 +54,8 @@ + #endif + + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 + #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 +-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + + /* + * Network Configuration +@@ -69,7 +65,6 @@ + #define CONFIG_GATEWAYIP 192.168.11.1 + #define CONFIG_NETMASK 255.255.255.0 + +-#define CONFIG_SYS_LOAD_ADDR 0x85000000 + #define CONFIG_SYS_BOOTM_LEN (32 << 20) + + #if defined(CONFIG_ARM64) +@@ -84,7 +79,7 @@ + #endif + + #define CONFIG_ROOTPATH "/nfs/root/path" +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs $bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ +@@ -198,8 +193,6 @@ + /* only for SPL */ + #define CONFIG_SPL_STACK (0x00100000) + +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +- + /* subtract sizeof(struct image_header) */ + #define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) + +diff -ruN u-boot-2021.10/include/configs/usb_a9263.h u-boot/include/configs/usb_a9263.h +--- u-boot-2021.10/include/configs/usb_a9263.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/usb_a9263.h 2021-11-01 17:10:14.606240375 +0100 +@@ -20,14 +20,6 @@ + #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 + +-#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + /* + * Hardware drivers + */ +@@ -71,16 +63,9 @@ + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 +- + /* bootstrap + u-boot + env + linux in dataflash on CS0 */ + #define CONFIG_BOOTCOMMAND "nboot 21000000 0" + #define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +- + #endif +diff -ruN u-boot-2021.10/include/configs/usbarmory.h u-boot/include/configs/usbarmory.h +--- u-boot-2021.10/include/configs/usbarmory.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/usbarmory.h 2021-11-01 17:10:14.606240375 +0100 +@@ -31,19 +31,9 @@ + #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + #define CONFIG_MXC_USB_FLAGS 0 + +-/* I2C */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +- + /* Fuse */ + #define CONFIG_FSL_IIM + +-/* U-Boot memory offsets */ +-#define CONFIG_LOADADDR 0x72000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Linux boot */ + #define CONFIG_HOSTNAME "usbarmory" + #define CONFIG_BOOTCOMMAND \ +@@ -89,6 +79,4 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +- + #endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/vcoreiii.h u-boot/include/configs/vcoreiii.h +--- u-boot-2021.10/include/configs/vcoreiii.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vcoreiii.h 2021-11-01 17:10:14.606240375 +0100 +@@ -10,8 +10,6 @@ + + /* Onboard devices */ + +-#define CONFIG_SYS_MALLOC_LEN 0x1F0000 +-#define CONFIG_SYS_LOAD_ADDR 0x00100000 + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + + #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) +diff -ruN u-boot-2021.10/include/configs/ventana.h u-boot/include/configs/ventana.h +--- u-boot-2021.10/include/configs/ventana.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/ventana.h 2021-11-01 17:10:14.606240375 +0100 +@@ -17,8 +17,6 @@ + #define CONFIG_TEGRA_ENABLE_UARTD + #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +-#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA +- + /* Environment in eMMC, at the end of 2nd "boot sector" */ + + #include "tegra-common-post.h" +diff -ruN u-boot-2021.10/include/configs/verdin-imx8mm.h u-boot/include/configs/verdin-imx8mm.h +--- u-boot-2021.10/include/configs/verdin-imx8mm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/verdin-imx8mm.h 2021-11-01 17:10:14.606240375 +0100 +@@ -37,9 +37,6 @@ + "ramdisk_addr_r=0x46400000\0" \ + "scriptaddr=0x46000000\0" + +-#define CONFIG_LOADADDR 0x40480000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +- + /* Enable Distro Boot */ + #ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ +@@ -88,8 +85,6 @@ + /* Environment in eMMC, before config block at the end of 1st "boot sector" */ + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN SZ_32M + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + + /* SDRAM configuration */ +@@ -110,7 +105,6 @@ + #define CONFIG_SYS_FSL_USDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* ENET */ + #define CONFIG_ETHPRIME "FEC" +@@ -125,4 +119,3 @@ + #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + + #endif /*_VERDIN_IMX8MM_H */ +- +diff -ruN u-boot-2021.10/include/configs/vexpress_aemv8a.h u-boot/include/configs/vexpress_aemv8a.h +--- u-boot-2021.10/include/configs/vexpress_aemv8a.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vexpress_aemv8a.h 2021-11-01 17:10:14.606240375 +0100 +@@ -85,9 +85,6 @@ + #endif + #endif /* !CONFIG_GICV3 */ + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) +- + #ifndef CONFIG_TARGET_VEXPRESS64_JUNO + /* The Vexpress64 simulators use SMSC91C111 */ + #define CONFIG_SMC91111 1 +@@ -105,7 +102,6 @@ + #define CONFIG_BOOTP_BOOTFILESIZE + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) + + /* Physical Memory Map */ + #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +diff -ruN u-boot-2021.10/include/configs/vexpress_ca9x4.h u-boot/include/configs/vexpress_ca9x4.h +--- u-boot-2021.10/include/configs/vexpress_ca9x4.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/configs/vexpress_ca9x4.h 2021-11-01 17:10:14.606240375 +0100 +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2011 Linaro ++ * Ryan Harkin, <ryan.harkin@linaro.org> ++ * ++ * Configuration for Versatile Express. Parts were derived from other ARM ++ * configurations. ++ */ ++ ++#ifndef __VEXPRESS_CA9X4_H ++#define __VEXPRESS_CA9X4_H ++ ++#define VEXPRESS_ORIGINAL_MEMORY_MAP ++#include "vexpress_common.h" ++ ++#endif /* VEXPRESS_CA9X4_H */ +diff -ruN u-boot-2021.10/include/configs/vexpress_common.h u-boot/include/configs/vexpress_common.h +--- u-boot-2021.10/include/configs/vexpress_common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vexpress_common.h 2021-11-01 17:10:14.606240375 +0100 +@@ -15,7 +15,7 @@ + * Definitions copied from linux kernel: + * arch/arm/mach-vexpress/include/mach/motherboard.h + */ +-#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP ++#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP + /* CS register bases for the original memory map. */ + #define V2M_PA_CS0 0x40000000 + #define V2M_PA_CS1 0x44000000 +@@ -56,7 +56,6 @@ + + /* Common peripherals relative to CS7. */ + #define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) +-#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) + #define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) + #define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) + +@@ -109,15 +108,8 @@ + + /* Board info register */ + #define SYS_ID V2M_SYSREGS +-#define CONFIG_REVISION_TAG 1 + +-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS 1 + #define CONFIG_SYS_L2CACHE_OFF 1 +-#define CONFIG_INITRD_TAG 1 +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ + + #define SCTL_BASE V2M_SYSCTL + #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) +@@ -131,19 +123,15 @@ + #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + #define CONFIG_SYS_SERIAL0 V2M_UART0 + #define CONFIG_SYS_SERIAL1 V2M_UART1 + +-#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI + #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 +-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 + + /* BOOTP options */ + #define CONFIG_BOOTP_BOOTFILESIZE + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) + #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) + + /* Physical Memory Map */ +@@ -169,29 +157,10 @@ + func(DHCP, dhcp, na) + #include <config_distro_bootcmd.h> + +-#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +-#define CONFIG_PLATFORM_ENV_SETTINGS \ +- "loadaddr=0x80008000\0" \ +- "ramdisk_addr_r=0x61000000\0" \ +- "kernel_addr=0x44100000\0" \ +- "ramdisk_addr=0x44800000\0" \ +- "maxramdisk=0x1800000\0" \ +- "pxefile_addr_r=0x88000000\0" \ +- "scriptaddr=0x88000000\0" \ +- "kernel_addr_r=0x80008000\0" +-#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) +-#define CONFIG_PLATFORM_ENV_SETTINGS \ +- "loadaddr=0xa0008000\0" \ +- "ramdisk_addr_r=0x81000000\0" \ +- "kernel_addr=0x0c100000\0" \ +- "ramdisk_addr=0x0c800000\0" \ +- "maxramdisk=0x1800000\0" \ +- "pxefile_addr_r=0xa8000000\0" \ +- "scriptaddr=0xa8000000\0" \ +- "kernel_addr_r=0xa0008000\0" +-#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ +- CONFIG_PLATFORM_ENV_SETTINGS \ ++ "kernel_addr_r=0x60100000\0" \ ++ "fdt_addr_r=0x60000000\0" \ ++ "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ + BOOTENV \ + "console=ttyAMA0,38400n8\0" \ + "dram=1024M\0" \ +diff -ruN u-boot-2021.10/include/configs/vf610twr.h u-boot/include/configs/vf610twr.h +--- u-boot-2021.10/include/configs/vf610twr.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vf610twr.h 2021-11-01 17:10:14.606240375 +0100 +@@ -13,18 +13,7 @@ + + #define CONFIG_SYS_FSL_CLK + +-#define CONFIG_MACH_TYPE 4146 +- +-#define CONFIG_SKIP_LOWLEVEL_INIT +- +-/* Enable passing of ATAGs */ +-#define CONFIG_CMDLINE_TAG +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +- + /* NAND support */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + + #ifdef CONFIG_CMD_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +@@ -42,15 +31,8 @@ + #define CONFIG_FEC_MXC_PHYADDR 0 + + /* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ + #define CONFIG_SYS_SPD_BUS_NUM 0 + +- +-#define CONFIG_SYS_LOAD_ADDR 0x82000000 +- + /* We boot from the gfxRAM area of the OCRAM. */ + #define CONFIG_BOARD_SIZE_LIMIT 520192 + +diff -ruN u-boot-2021.10/include/configs/vinco.h u-boot/include/configs/vinco.h +--- u-boot-2021.10/include/configs/vinco.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vinco.h 2021-11-01 17:10:14.606240375 +0100 +@@ -30,8 +30,6 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +- + /* SerialFlash */ + + #ifdef CONFIG_CMD_SF +diff -ruN u-boot-2021.10/include/configs/vining_2000.h u-boot/include/configs/vining_2000.h +--- u-boot-2021.10/include/configs/vining_2000.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vining_2000.h 2021-11-01 17:10:14.606240375 +0100 +@@ -14,9 +14,6 @@ + #include "imx6_spl.h" + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +- + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ +@@ -42,16 +39,7 @@ + /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +-/* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + #define CONFIG_POWER_PFUZE100 + #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +diff -ruN u-boot-2021.10/include/configs/vocore2.h u-boot/include/configs/vocore2.h +--- u-boot-2021.10/include/configs/vocore2.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/vocore2.h 2021-11-01 17:10:14.606240375 +0100 +@@ -12,14 +12,9 @@ + /* RAM */ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +- + #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + + /* SPL */ +-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif + + #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + #define CONFIG_SPL_BSS_START_ADDR 0x80010000 +@@ -41,7 +36,6 @@ + + /* Memory usage */ + #define CONFIG_SYS_MAXARGS 64 +-#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + #define CONFIG_SYS_CBSIZE 512 + +diff -ruN u-boot-2021.10/include/configs/wandboard.h u-boot/include/configs/wandboard.h +--- u-boot-2021.10/include/configs/wandboard.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/wandboard.h 2021-11-01 17:10:14.606240375 +0100 +@@ -12,11 +12,6 @@ + + #include "imx6_spl.h" + +-#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6 +- +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +- + #define CONFIG_MXC_UART_BASE UART1_BASE + + /* SATA Configs */ +@@ -45,7 +40,7 @@ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ +- "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=undefined\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ +@@ -85,11 +80,11 @@ + "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ +- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ ++ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ +- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + BOOTENV + + #define BOOT_TARGET_DEVICES(func) \ +diff -ruN u-boot-2021.10/include/configs/warp7.h u-boot/include/configs/warp7.h +--- u-boot-2021.10/include/configs/warp7.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/warp7.h 2021-11-01 17:10:14.609573526 +0100 +@@ -13,17 +13,11 @@ + + #define PHYS_SDRAM_SIZE SZ_512M + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) +- + /* MMC Config*/ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR + #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-/* Switch on SERIAL_TAG */ +-#define CONFIG_SERIAL_TAG +- + #define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ + +@@ -34,10 +28,6 @@ + #define BOOT_SCR_STRING "source ${bootscriptaddr}\0" + #endif + +-#ifndef CONFIG_OPTEE_LOAD_ADDR +-#define CONFIG_OPTEE_LOAD_ADDR 0 +-#endif +- + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ +@@ -52,7 +42,6 @@ + "fdt_file=imx7s-warp.dtb\0" \ + "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \ + "fdtovaddr=0x83100000\0" \ +- "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ +@@ -107,7 +96,6 @@ + "fi; " \ + "fi" + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +@@ -135,10 +123,6 @@ + */ + #define CONFIG_BOARD_SIZE_LIMIT 785408 + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* environment organization */ + + #define CONFIG_SYS_FSL_USDHC_NUM 1 +diff -ruN u-boot-2021.10/include/configs/warp.h u-boot/include/configs/warp.h +--- u-boot-2021.10/include/configs/warp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/warp.h 2021-11-01 17:10:14.609573526 +0100 +@@ -14,9 +14,6 @@ + + #include "mx6_common.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ +- + #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + + /* MMC Configs */ +@@ -53,15 +50,8 @@ + #define DFU_DEFAULT_POLL_TIMEOUT 300 + + /* I2C Configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_SPEED 100000 + + /* PMIC */ +-#define CONFIG_POWER +-#define CONFIG_POWER_I2C + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ +diff -ruN u-boot-2021.10/include/configs/work_92105.h u-boot/include/configs/work_92105.h +--- u-boot-2021.10/include/configs/work_92105.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/work_92105.h 2021-11-01 17:10:14.609573526 +0100 +@@ -14,24 +14,11 @@ + #include <asm/arch/cpu.h> + + /* +- * Define work_92105 machine type by hand -- done only for compatibility +- * with original board code +- */ +-#define CONFIG_MACH_TYPE 736 +- +-#if !defined(CONFIG_SPL_BUILD) +-#define CONFIG_SKIP_LOWLEVEL_INIT +-#endif +- +-/* + * Memory configurations + */ +-#define CONFIG_SYS_MALLOC_LEN SZ_1M + #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE + #define CONFIG_SYS_SDRAM_SIZE SZ_128M + +-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) +- + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ + - GENERATED_GBL_DATA_SIZE) + +@@ -43,24 +30,6 @@ + #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN + /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ + +-/* +- * I2C driver +- */ +- +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_SPEED 350000 +- +-/* +- * I2C EEPROM +- */ +- +-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 +-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +- +-/* +- * I2C RTC +- */ +- + #define CONFIG_RTC_DS1374 + + /* +@@ -90,7 +59,6 @@ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_MAX_NAND_CHIPS 1 + #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE +-#define CONFIG_NAND_LPC32XX_MLC + + /* + * GPIO +@@ -105,12 +73,8 @@ + /* + * Boot Linux + */ +-#define CONFIG_CMDLINE_TAG +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG + + #define CONFIG_BOOTFILE "uImage" +-#define CONFIG_LOADADDR 0x80008000 + + /* + * SPL +@@ -122,7 +86,6 @@ + /* Use the framework and generic lib */ + /* SPL will use serial */ + /* SPL will load U-Boot from NAND offset 0x40000 */ +-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 + #define CONFIG_SPL_PAD_TO 0x20000 + /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ + #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ +diff -ruN u-boot-2021.10/include/configs/x530.h u-boot/include/configs/x530.h +--- u-boot-2021.10/include/configs/x530.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/x530.h 2021-11-01 17:10:14.609573526 +0100 +@@ -29,7 +29,6 @@ + */ + + /* NAND */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define BBT_CUSTOM_SCAN +@@ -59,9 +58,6 @@ + #endif + + /* NAND */ +-#define CONFIG_SYS_NAND_ONFI_DETECTION +- +-#define CONFIG_SYS_MALLOC_LEN (4 << 20) + + #include <asm/arch/config.h> + +@@ -75,7 +71,6 @@ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +-#define CONFIG_SYS_LOAD_ADDR 0x1000000 + #define CONFIG_UBI_PART user + #define CONFIG_UBIFS_VOLUME user + +diff -ruN u-boot-2021.10/include/configs/x86-common.h u-boot/include/configs/x86-common.h +--- u-boot-2021.10/include/configs/x86-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/x86-common.h 2021-11-01 17:10:14.609573526 +0100 +@@ -44,24 +44,17 @@ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" + #endif + +-#if defined(CONFIG_CMD_KGDB) +-#define CONFIG_KGDB_BAUDRATE 115200 +-#endif +- + /* + * Miscellaneous configurable options + */ + #define CONFIG_SYS_CBSIZE 512 + +-#define CONFIG_SYS_LOAD_ADDR 0x20000000 +- + /*----------------------------------------------------------------------- + * CPU Features + */ + + #define CONFIG_SYS_STACK_SIZE (32 * 1024) + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_MALLOC_LEN 0x200000 + + /*----------------------------------------------------------------------- + * Environment configuration +@@ -82,7 +75,6 @@ + #define CONFIG_ROOTPATH "/opt/nfsroot" + #define CONFIG_HOSTNAME "x86" + #define CONFIG_BOOTFILE "bzImage" +-#define CONFIG_LOADADDR 0x1000000 + #define CONFIG_RAMDISK_ADDR 0x4000000 + #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) + #define CONFIG_OTHBOOTARGS "othbootargs=\0" +@@ -109,7 +101,7 @@ + "ramdiskfile=initramfs.gz\0" + + +-#define CONFIG_RAMBOOTCOMMAND \ ++#define RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ +@@ -117,7 +109,7 @@ + "tftpboot $ramdisk_addr_r $ramdiskfile;" \ + "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize" + +-#define CONFIG_NFSBOOTCOMMAND \ ++#define NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +diff -ruN u-boot-2021.10/include/configs/xea.h u-boot/include/configs/xea.h +--- u-boot-2021.10/include/configs/xea.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xea.h 2021-11-01 17:10:14.609573526 +0100 +@@ -43,8 +43,6 @@ + /* Booting Linux */ + #define CONFIG_BOOTFILE "uImage" + #define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" +-#define CONFIG_LOADADDR 0x42000000 +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + + /* Extra Environment */ + #define CONFIG_HOSTNAME "xea" +diff -ruN u-boot-2021.10/include/configs/xenguest_arm64.h u-boot/include/configs/xenguest_arm64.h +--- u-boot-2021.10/include/configs/xenguest_arm64.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xenguest_arm64.h 2021-11-01 17:10:14.609573526 +0100 +@@ -20,12 +20,8 @@ + * This can be any arbitrary address as we are using PIE, but + * please note, that CONFIG_SYS_TEXT_BASE must match the below. + */ +-#define CONFIG_SYS_LOAD_ADDR 0x40000000 + #define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) +- + /* Monitor Command Prompt */ + #define CONFIG_SYS_CBSIZE 1024 + #define CONFIG_SYS_MAXARGS 64 +diff -ruN u-boot-2021.10/include/configs/xilinx_versal.h u-boot/include/configs/xilinx_versal.h +--- u-boot-2021.10/include/configs/xilinx_versal.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_versal.h 2021-11-01 17:10:14.609573526 +0100 +@@ -36,7 +36,6 @@ + #define CONFIG_BOOTP_MAY_FAIL + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR 0x8000000 + + /* Monitor Command Prompt */ + /* Console I/O Buffer Size */ +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp.h u-boot/include/configs/xilinx_zynqmp.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp.h 2021-11-01 17:10:14.609573526 +0100 +@@ -15,7 +15,6 @@ + /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + + /* Generic Interrupt Controller Definitions */ +-#define CONFIG_GICV2 + #define GICD_BASE 0xF9010000 + #define GICC_BASE 0xF9020000 + +@@ -26,9 +25,6 @@ + # define COUNTER_FREQUENCY 100000000 + #endif + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000) +- + /* Serial setup */ + #define CONFIG_CPU_ARMV8 + +@@ -41,7 +37,6 @@ + + #ifdef CONFIG_NAND_ARASAN + # define CONFIG_SYS_MAX_NAND_DEVICE 1 +-# define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + #if defined(CONFIG_SPL_BUILD) +@@ -49,7 +44,6 @@ + #endif + + /* Miscellaneous configurable options */ +-#define CONFIG_SYS_LOAD_ADDR 0x8000000 + + #if defined(CONFIG_ZYNQMP_USB) + #define DFU_DEFAULT_POLL_TIMEOUT 300 +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp_mini_emmc.h u-boot/include/configs/xilinx_zynqmp_mini_emmc.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp_mini_emmc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp_mini_emmc.h 2021-11-01 17:10:14.609573526 +0100 +@@ -13,6 +13,5 @@ + #include <configs/xilinx_zynqmp_mini.h> + + #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +-#define CONFIG_SYS_MALLOC_LEN 0x800000 + + #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp_mini.h u-boot/include/configs/xilinx_zynqmp_mini.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp_mini.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp_mini.h 2021-11-01 17:10:14.609573526 +0100 +@@ -17,7 +17,6 @@ + /* Undef unneeded configs */ + #undef CONFIG_BOOTCOMMAND + #undef CONFIG_EXTRA_ENV_SETTINGS +-#undef CONFIG_SYS_MALLOC_LEN + #undef CONFIG_SYS_INIT_SP_ADDR + + /* BOOTP options */ +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp_mini_nand.h u-boot/include/configs/xilinx_zynqmp_mini_nand.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp_mini_nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp_mini_nand.h 2021-11-01 17:10:14.609573526 +0100 +@@ -15,6 +15,5 @@ + #define CONFIG_SYS_SDRAM_SIZE 0x1000000 + #define CONFIG_SYS_SDRAM_BASE 0x0 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) +-#define CONFIG_SYS_MALLOC_LEN 0x800000 + + #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp_mini_qspi.h u-boot/include/configs/xilinx_zynqmp_mini_qspi.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp_mini_qspi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp_mini_qspi.h 2021-11-01 17:10:14.609573526 +0100 +@@ -13,6 +13,5 @@ + #include <configs/xilinx_zynqmp_mini.h> + + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) +-#define CONFIG_SYS_MALLOC_LEN 0x1a00 + + #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ +diff -ruN u-boot-2021.10/include/configs/xilinx_zynqmp_r5.h u-boot/include/configs/xilinx_zynqmp_r5.h +--- u-boot-2021.10/include/configs/xilinx_zynqmp_r5.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xilinx_zynqmp_r5.h 2021-11-01 17:10:14.609573526 +0100 +@@ -17,12 +17,9 @@ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + + /* Boot configuration */ +-#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + + #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +-#define CONFIG_SYS_MALLOC_LEN 0x1400000 +- + #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +@@ -32,6 +29,4 @@ + /* Extend size of kernel image for uncompression */ + #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ +diff -ruN u-boot-2021.10/include/configs/xpress.h u-boot/include/configs/xpress.h +--- u-boot-2021.10/include/configs/xpress.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xpress.h 2021-11-01 17:10:14.609573526 +0100 +@@ -13,25 +13,13 @@ + /* SPL options */ + #include "imx6_spl.h" + +-/* Size of malloc() pool */ +-#define CONFIG_SYS_MALLOC_LEN (16 << 20) +- + #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR + + /* MMC Configs */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +-/* I2C configs */ +-#define CONFIG_SYS_I2C_LEGACY +-#define CONFIG_SYS_I2C_MXC +-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +-#define CONFIG_SYS_I2C_SPEED 100000 +- + /* Miscellaneous configurable options */ + +-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_HZ 1000 + + /* Physical Memory Map */ +diff -ruN u-boot-2021.10/include/configs/xtfpga.h u-boot/include/configs/xtfpga.h +--- u-boot-2021.10/include/configs/xtfpga.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/xtfpga.h 2021-11-01 17:10:14.609573526 +0100 +@@ -65,8 +65,6 @@ + # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ + #endif + +-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ +- + /* Linux boot param area in RAM (used only when booting linux) */ + #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +@@ -98,9 +96,6 @@ + #define XTENSA_SYS_TEXT_ADDR \ + (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) + +-/* Used by tftpboot; env var 'loadaddr' */ +-#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) +- + /*==============================*/ + /* U-Boot general configuration */ + /*==============================*/ +@@ -175,7 +170,6 @@ + + /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ + #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ +-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + /*======================*/ + /* Ethernet Driver Info */ +diff -ruN u-boot-2021.10/include/configs/zmx25.h u-boot/include/configs/zmx25.h +--- u-boot-2021.10/include/configs/zmx25.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/zmx25.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,91 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (c) 2011 Graf-Syteco, Matthias Weisser +- * <weisserm@arcor.de> +- * +- * Configuation settings for the zmx25 board +- */ +- +-#ifndef __CONFIG_H +-#define __CONFIG_H +- +-#include <asm/arch/imx-regs.h> +- +-#define CONFIG_SYS_TIMER_RATE 32768 +-#define CONFIG_SYS_TIMER_COUNTER \ +- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) +- +-#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 +-/* +- * Environment settings +- */ +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "gs_fast_boot=setenv bootdelay 5\0" \ +- "gs_slow_boot=setenv bootdelay 10\0" \ +- "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ +- "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ +- "bootm 0x81000000; bootelf 0x81000000\0" +- +-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +-#define CONFIG_SETUP_MEMORY_TAGS +-#define CONFIG_INITRD_TAG +- +-/* +- * Hardware drivers +- */ +- +-/* +- * Serial +- */ +-#define CONFIG_MXC_UART_BASE UART2_BASE +- +-/* +- * Ethernet +- */ +-#define CONFIG_FEC_MXC +-#define CONFIG_FEC_MXC_PHYADDR 0x00 +- +-/* +- * BOOTP options +- */ +-#define CONFIG_BOOTP_BOOTFILESIZE +- +-/* +- * USB +- */ +-#ifdef CONFIG_CMD_USB +-#define CONFIG_USB_EHCI_MXC +-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +-#define CONFIG_MXC_USB_PORT 1 +-#define CONFIG_MXC_USB_PORTSC PORT_PTS_SERIAL +-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) +-#define CONFIG_EHCI_IS_TDI +-#endif /* CONFIG_CMD_USB */ +- +-/* SDRAM */ +-#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +- +-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +-#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ +- +-/* +- * FLASH and environment organization +- */ +-#define CONFIG_SYS_FLASH_BASE 0xA0000000 +-#define CONFIG_SYS_MAX_FLASH_BANKS 1 +-#define CONFIG_SYS_MAX_FLASH_SECT 256 +- +-/* +- * CFI FLASH driver setup +- */ +- +-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +- +- +-/* +- * Size of malloc() pool +- */ +-#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +- +-#endif /* __CONFIG_H */ +diff -ruN u-boot-2021.10/include/configs/zynq-common.h u-boot/include/configs/zynq-common.h +--- u-boot-2021.10/include/configs/zynq-common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/zynq-common.h 2021-11-01 17:10:14.609573526 +0100 +@@ -52,7 +52,6 @@ + + #ifdef CONFIG_NAND_ZYNQ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 +-#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif + + #ifdef CONFIG_USB_EHCI_ZYNQ +@@ -65,7 +64,6 @@ + /* enable preboot to be loaded before CONFIG_BOOTDELAY */ + + /* Boot configuration */ +-#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ + + #ifdef CONFIG_SPL_BUILD + #define BOOTENV +diff -ruN u-boot-2021.10/include/configs/zynq_cse.h u-boot/include/configs/zynq_cse.h +--- u-boot-2021.10/include/configs/zynq_cse.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/configs/zynq_cse.h 2021-11-01 17:10:14.609573526 +0100 +@@ -9,8 +9,6 @@ + #ifndef __CONFIG_ZYNQ_CSE_H + #define __CONFIG_ZYNQ_CSE_H + +-#define CONFIG_SKIP_LOWLEVEL_INIT +- + #include <configs/zynq-common.h> + + /* Undef unneeded configs */ +diff -ruN u-boot-2021.10/include/div64.h u-boot/include/div64.h +--- u-boot-2021.10/include/div64.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/div64.h 2021-11-01 17:10:14.609573526 +0100 +@@ -220,7 +220,7 @@ + } else if (likely(((n) >> 32) == 0)) { \ + __rem = (u32)(n) % __base; \ + (n) = (u32)(n) / __base; \ +- } else \ ++ } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) +diff -ruN u-boot-2021.10/include/dm/device.h u-boot/include/dm/device.h +--- u-boot-2021.10/include/dm/device.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dm/device.h 2021-11-01 17:10:14.612906677 +0100 +@@ -181,7 +181,7 @@ + u32 flags_; + #endif + int seq_; +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + ofnode node_; + #endif + #ifdef CONFIG_DEVRES +@@ -243,7 +243,7 @@ + */ + static inline ofnode dev_ofnode(const struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + return dev->node_; + #else + return ofnode_null(); +@@ -263,7 +263,7 @@ + + static inline int dev_of_offset(const struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + return ofnode_to_offset(dev_ofnode(dev)); + #else + return -1; +@@ -272,7 +272,7 @@ + + static inline bool dev_has_ofnode(const struct udevice *dev) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + return ofnode_valid(dev_ofnode(dev)); + #else + return false; +@@ -281,7 +281,7 @@ + + static inline void dev_set_ofnode(struct udevice *dev, ofnode node) + { +-#if !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + dev->node_ = node; + #endif + } +@@ -301,7 +301,7 @@ + ulong data; + }; + +-#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ++#if CONFIG_IS_ENABLED(OF_REAL) + #define of_match_ptr(_ptr) (_ptr) + #else + #define of_match_ptr(_ptr) NULL +@@ -739,7 +739,7 @@ + * + * @parent: Parent device to search + * @uclass_id: Uclass to look for +- * @devp: Returns device found, if any ++ * @devp: Returns device found, if any, else NULL + * @return 0 if found, else -ENODEV + */ + int device_find_first_inactive_child(const struct udevice *parent, +@@ -751,7 +751,7 @@ + * + * @parent: Parent device to search + * @uclass_id: Uclass to look for +- * @devp: Returns first child device in that uclass, if any ++ * @devp: Returns first child device in that uclass, if any, else NULL + * @return 0 if found, else -ENODEV + */ + int device_find_first_child_by_uclass(const struct udevice *parent, +diff -ruN u-boot-2021.10/include/dm/ofnode.h u-boot/include/dm/ofnode.h +--- u-boot-2021.10/include/dm/ofnode.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dm/ofnode.h 2021-11-01 17:10:14.612906677 +0100 +@@ -1117,4 +1117,41 @@ + */ + int ofnode_set_enabled(ofnode node, bool value); + ++/** ++ * ofnode_conf_read_bool() - Read a boolean value from the U-Boot config ++ * ++ * This reads a property from the /config node of the devicetree. ++ * ++ * See doc/config.txt for bindings ++ * ++ * @prop_name property name to look up ++ * @return true, if it exists, false if not ++ */ ++bool ofnode_conf_read_bool(const char *prop_name); ++ ++/** ++ * ofnode_conf_read_int() - Read an integer value from the U-Boot config ++ * ++ * This reads a property from the /config node of the devicetree. ++ * ++ * See doc/config.txt for bindings ++ * ++ * @prop_name: property name to look up ++ * @default_val: default value to return if the property is not found ++ * @return integer value, if found, or @default_val if not ++ */ ++int ofnode_conf_read_int(const char *prop_name, int default_val); ++ ++/** ++ * ofnode_conf_read_str() - Read a string value from the U-Boot config ++ * ++ * This reads a property from the /config node of the devicetree. ++ * ++ * See doc/config.txt for bindings ++ * ++ * @prop_name: property name to look up ++ * @return string value, if found, or NULL if not ++ */ ++const char *ofnode_conf_read_str(const char *prop_name); ++ + #endif +diff -ruN u-boot-2021.10/include/dm/platform_data/spi_coldfire.h u-boot/include/dm/platform_data/spi_coldfire.h +--- u-boot-2021.10/include/dm/platform_data/spi_coldfire.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dm/platform_data/spi_coldfire.h 2021-11-01 17:10:14.612906677 +0100 +@@ -26,4 +26,3 @@ + }; + + #endif /* __spi_coldfire_h */ +- +diff -ruN u-boot-2021.10/include/dm/uclass.h u-boot/include/dm/uclass.h +--- u-boot-2021.10/include/dm/uclass.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dm/uclass.h 2021-11-01 17:10:14.612906677 +0100 +@@ -354,7 +354,7 @@ + * The device returned is probed if necessary, and ready for use + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer +- * to the next device in the uclass if no error occurred, or -ENODEV if ++ * to the next device in the uclass if no error occurred, or NULL if + * there is no next device. + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +diff -ruN u-boot-2021.10/include/dm/uclass-id.h u-boot/include/dm/uclass-id.h +--- u-boot-2021.10/include/dm/uclass-id.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dm/uclass-id.h 2021-11-01 17:10:14.612906677 +0100 +@@ -54,6 +54,7 @@ + UCLASS_FIRMWARE, /* Firmware */ + UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ + UCLASS_GPIO, /* Bank of general-purpose I/O pins */ ++ UCLASS_HASH, /* Hash device */ + UCLASS_HWSPINLOCK, /* Hardware semaphores */ + UCLASS_I2C, /* I2C bus */ + UCLASS_I2C_EEPROM, /* I2C EEPROM device */ +diff -ruN u-boot-2021.10/include/dt-bindings/clock/axg-clkc.h u-boot/include/dt-bindings/clock/axg-clkc.h +--- u-boot-2021.10/include/dt-bindings/clock/axg-clkc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/clock/axg-clkc.h 2021-11-01 17:10:14.612906677 +0100 +@@ -70,7 +70,31 @@ + #define CLKID_HIFI_PLL 69 + #define CLKID_PCIE_CML_EN0 79 + #define CLKID_PCIE_CML_EN1 80 +-#define CLKID_MIPI_ENABLE 81 + #define CLKID_GEN_CLK 84 ++#define CLKID_VPU_0_SEL 92 ++#define CLKID_VPU_0 93 ++#define CLKID_VPU_1_SEL 95 ++#define CLKID_VPU_1 96 ++#define CLKID_VPU 97 ++#define CLKID_VAPB_0_SEL 99 ++#define CLKID_VAPB_0 100 ++#define CLKID_VAPB_1_SEL 102 ++#define CLKID_VAPB_1 103 ++#define CLKID_VAPB_SEL 104 ++#define CLKID_VAPB 105 ++#define CLKID_VCLK 106 ++#define CLKID_VCLK2 107 ++#define CLKID_VCLK_DIV1 122 ++#define CLKID_VCLK_DIV2 123 ++#define CLKID_VCLK_DIV4 124 ++#define CLKID_VCLK_DIV6 125 ++#define CLKID_VCLK_DIV12 126 ++#define CLKID_VCLK2_DIV1 127 ++#define CLKID_VCLK2_DIV2 128 ++#define CLKID_VCLK2_DIV4 129 ++#define CLKID_VCLK2_DIV6 130 ++#define CLKID_VCLK2_DIV12 131 ++#define CLKID_CTS_ENCL 133 ++#define CLKID_VDIN_MEAS 136 + + #endif /* __AXG_CLKC_H */ +diff -ruN u-boot-2021.10/include/dt-bindings/clock/g12a-clkc.h u-boot/include/dt-bindings/clock/g12a-clkc.h +--- u-boot-2021.10/include/dt-bindings/clock/g12a-clkc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/clock/g12a-clkc.h 2021-11-01 17:10:14.616239828 +0100 +@@ -147,5 +147,7 @@ + #define CLKID_SPICC1_SCLK 261 + #define CLKID_NNA_AXI_CLK 264 + #define CLKID_NNA_CORE_CLK 267 ++#define CLKID_MIPI_DSI_PXCLK_SEL 269 ++#define CLKID_MIPI_DSI_PXCLK 270 + + #endif /* __G12A_CLKC_H */ +diff -ruN u-boot-2021.10/include/dt-bindings/clock/mt7622-clk.h u-boot/include/dt-bindings/clock/mt7622-clk.h +--- u-boot-2021.10/include/dt-bindings/clock/mt7622-clk.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/clock/mt7622-clk.h 2021-11-01 17:10:14.616239828 +0100 +@@ -268,4 +268,3 @@ + #define CLK_SGMII_CDR_FB 3 + + #endif /* _DT_BINDINGS_CLK_MT7622_H */ +- +diff -ruN u-boot-2021.10/include/dt-bindings/clock/sun20i-d1-ccu.h u-boot/include/dt-bindings/clock/sun20i-d1-ccu.h +--- u-boot-2021.10/include/dt-bindings/clock/sun20i-d1-ccu.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/clock/sun20i-d1-ccu.h 2021-11-01 17:10:14.619572979 +0100 +@@ -0,0 +1,159 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2020 huangzhenwei@allwinnertech.com ++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ ++#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ ++ ++#define CLK_DCXO12M 0 ++#define CLK_PLL_CPUX 1 ++#define CLK_PLL_DDR0 2 ++#define CLK_PLL_PERIPH0_4X 3 ++#define CLK_PLL_PERIPH0_2X 4 ++#define CLK_PLL_PERIPH0_800M 5 ++#define CLK_PLL_PERIPH0 6 ++#define CLK_PLL_PERIPH0_DIV3 7 ++#define CLK_PLL_VIDEO0_4X 8 ++#define CLK_PLL_VIDEO0_2X 9 ++#define CLK_PLL_VIDEO0 10 ++#define CLK_PLL_VIDEO1_4X 11 ++#define CLK_PLL_VIDEO1_2X 12 ++#define CLK_PLL_VIDEO1 13 ++#define CLK_PLL_VE 14 ++#define CLK_PLL_AUDIO0_4X 15 ++#define CLK_PLL_AUDIO0_2X 16 ++#define CLK_PLL_AUDIO0 17 ++#define CLK_PLL_AUDIO1 18 ++#define CLK_PLL_AUDIO1_DIV2 19 ++#define CLK_PLL_AUDIO1_DIV5 20 ++#define CLK_CPUX 21 ++#define CLK_CPUX_AXI 22 ++#define CLK_CPUX_APB 23 ++#define CLK_PSI_AHB 24 ++#define CLK_APB0 25 ++#define CLK_APB1 26 ++#define CLK_MBUS 27 ++#define CLK_DE 28 ++#define CLK_BUS_DE 29 ++#define CLK_DI 30 ++#define CLK_BUS_DI 31 ++#define CLK_G2D 32 ++#define CLK_BUS_G2D 33 ++#define CLK_CE 34 ++#define CLK_BUS_CE 35 ++#define CLK_VE 36 ++#define CLK_BUS_VE 37 ++#define CLK_BUS_DMA 38 ++#define CLK_BUS_MSGBOX0 39 ++#define CLK_BUS_MSGBOX1 40 ++#define CLK_BUS_MSGBOX2 41 ++#define CLK_BUS_SPINLOCK 42 ++#define CLK_BUS_HSTIMER 43 ++#define CLK_AVS 44 ++#define CLK_BUS_DBG 45 ++#define CLK_BUS_PWM 46 ++#define CLK_BUS_IOMMU 47 ++#define CLK_DRAM 48 ++#define CLK_MBUS_DMA 49 ++#define CLK_MBUS_VE 50 ++#define CLK_MBUS_CE 51 ++#define CLK_MBUS_TVIN 52 ++#define CLK_MBUS_CSI 53 ++#define CLK_MBUS_G2D 54 ++#define CLK_MBUS_RISCV 55 ++#define CLK_BUS_DRAM 56 ++#define CLK_MMC0 57 ++#define CLK_MMC1 58 ++#define CLK_MMC2 59 ++#define CLK_BUS_MMC0 60 ++#define CLK_BUS_MMC1 61 ++#define CLK_BUS_MMC2 62 ++#define CLK_BUS_UART0 63 ++#define CLK_BUS_UART1 64 ++#define CLK_BUS_UART2 65 ++#define CLK_BUS_UART3 66 ++#define CLK_BUS_UART4 67 ++#define CLK_BUS_UART5 68 ++#define CLK_BUS_I2C0 69 ++#define CLK_BUS_I2C1 70 ++#define CLK_BUS_I2C2 71 ++#define CLK_BUS_I2C3 72 ++#define CLK_SPI0 73 ++#define CLK_SPI1 74 ++#define CLK_BUS_SPI0 75 ++#define CLK_BUS_SPI1 76 ++#define CLK_EMAC_25M 77 ++#define CLK_BUS_EMAC 78 ++#define CLK_IR_TX 79 ++#define CLK_BUS_IR_TX 80 ++#define CLK_BUS_GPADC 81 ++#define CLK_BUS_THS 82 ++#define CLK_I2S0 83 ++#define CLK_I2S1 84 ++#define CLK_I2S2 85 ++#define CLK_I2S2_ASRC 86 ++#define CLK_BUS_I2S0 87 ++#define CLK_BUS_I2S1 88 ++#define CLK_BUS_I2S2 89 ++#define CLK_SPDIF_TX 90 ++#define CLK_SPDIF_RX 91 ++#define CLK_BUS_SPDIF 92 ++#define CLK_DMIC 93 ++#define CLK_BUS_DMIC 94 ++#define CLK_AUDIO_DAC 95 ++#define CLK_AUDIO_ADC 96 ++#define CLK_BUS_AUDIO 97 ++#define CLK_USB_48M 98 ++#define CLK_USB_12M 99 ++#define CLK_USB_OHCI0 100 ++#define CLK_USB_OHCI1 101 ++#define CLK_BUS_OHCI0 102 ++#define CLK_BUS_OHCI1 103 ++#define CLK_BUS_EHCI0 104 ++#define CLK_BUS_EHCI1 105 ++#define CLK_BUS_OTG 106 ++#define CLK_BUS_LRADC 107 ++#define CLK_BUS_DPSS_TOP 108 ++#define CLK_HDMI_24M 109 ++#define CLK_HDMI_CEC_32K 110 ++#define CLK_HDMI_CEC 111 ++#define CLK_BUS_HDMI 112 ++#define CLK_MIPI_DSI 113 ++#define CLK_BUS_MIPI_DSI 114 ++#define CLK_TCON_LCD0 115 ++#define CLK_BUS_TCON_LCD0 116 ++#define CLK_TCON_TV 117 ++#define CLK_BUS_TCON_TV 118 ++#define CLK_TVE 119 ++#define CLK_BUS_TVE_TOP 120 ++#define CLK_BUS_TVE 121 ++#define CLK_TVD 122 ++#define CLK_BUS_TVD_TOP 123 ++#define CLK_BUS_TVD 124 ++#define CLK_LEDC 125 ++#define CLK_BUS_LEDC 126 ++#define CLK_CSI_TOP 127 ++#define CLK_CSI_MCLK 128 ++#define CLK_BUS_CSI 129 ++#define CLK_TPADC 130 ++#define CLK_BUS_TPADC 131 ++#define CLK_BUS_TZMA 132 ++#define CLK_DSP 133 ++#define CLK_BUS_DSP_CFG 134 ++#define CLK_RISCV 135 ++#define CLK_RISCV_AXI 136 ++#define CLK_BUS_RISCV_CFG 137 ++#define CLK_FANOUT_24M 138 ++#define CLK_FANOUT_12M 139 ++#define CLK_FANOUT_16M 140 ++#define CLK_FANOUT_25M 141 ++#define CLK_FANOUT_32K 142 ++#define CLK_FANOUT_27M 143 ++#define CLK_FANOUT_PCLK 144 ++#define CLK_FANOUT0 145 ++#define CLK_FANOUT1 146 ++#define CLK_FANOUT2 147 ++ ++#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/clock/sun20i-d1-r-ccu.h u-boot/include/dt-bindings/clock/sun20i-d1-r-ccu.h +--- u-boot-2021.10/include/dt-bindings/clock/sun20i-d1-r-ccu.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/clock/sun20i-d1-r-ccu.h 2021-11-01 17:10:14.619572979 +0100 +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ ++#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ ++ ++#define CLK_R_AHB 0 ++ ++#define CLK_BUS_R_TIMER 2 ++#define CLK_BUS_R_TWD 3 ++#define CLK_BUS_R_PPU 4 ++#define CLK_R_IR_RX 5 ++#define CLK_BUS_R_IR_RX 6 ++#define CLK_BUS_R_RTC 7 ++#define CLK_BUS_R_CPUCFG 8 ++ ++#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/clock/sun50i-rtc.h u-boot/include/dt-bindings/clock/sun50i-rtc.h +--- u-boot-2021.10/include/dt-bindings/clock/sun50i-rtc.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/clock/sun50i-rtc.h 2021-11-01 17:10:14.619572979 +0100 +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ ++#define _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ ++ ++#define CLK_OSC32K 0 ++#define CLK_OSC32K_FANOUT 1 ++#define CLK_IOSC 2 ++ ++#define CLK_RTC_SPI 8 ++ ++#endif /* _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/comphy/comphy_data.h u-boot/include/dt-bindings/comphy/comphy_data.h +--- u-boot-2021.10/include/dt-bindings/comphy/comphy_data.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/comphy/comphy_data.h 2021-11-01 17:10:14.622906130 +0100 +@@ -51,4 +51,3 @@ + #define UTMI_PHY_INVALID 0xff + + #endif /* _COMPHY_DATA_H_ */ +- +diff -ruN u-boot-2021.10/include/dt-bindings/leds/common.h u-boot/include/dt-bindings/leds/common.h +--- u-boot-2021.10/include/dt-bindings/leds/common.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/leds/common.h 2021-11-01 17:10:14.622906130 +0100 +@@ -6,6 +6,7 @@ + * Author: Jacek Anaszewski <j.anaszewski@samsung.com> + * + * Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com> ++ * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz> + */ + + #ifndef __DT_BINDINGS_LEDS_H +@@ -29,19 +30,44 @@ + #define LED_COLOR_ID_VIOLET 5 + #define LED_COLOR_ID_YELLOW 6 + #define LED_COLOR_ID_IR 7 +-#define LED_COLOR_ID_MAX 8 ++#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ ++#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, ++ so this would include RGBW and similar */ ++#define LED_COLOR_ID_MAX 10 + + /* Standard LED functions */ ++/* Keyboard LEDs, usually it would be input4::capslock etc. */ ++/* Obsolete equivalent: "shift-key-light" */ ++#define LED_FUNCTION_CAPSLOCK "capslock" ++#define LED_FUNCTION_SCROLLLOCK "scrolllock" ++#define LED_FUNCTION_NUMLOCK "numlock" ++/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), ++ "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ ++#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" ++ ++/* System LEDs, usually found on system body. ++ platform::mute (etc) is sometimes seen, :mute would be better */ ++#define LED_FUNCTION_POWER "power" ++#define LED_FUNCTION_DISK "disk" ++ ++/* Obsolete: "platform:*:charging" (allwinner sun50i) */ ++#define LED_FUNCTION_CHARGING "charging" ++/* Used RGB notification LEDs common on phones. ++ Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), ++ "lp5523:{r,g,b}" (Nokia N900) */ ++#define LED_FUNCTION_STATUS "status" ++ ++#define LED_FUNCTION_MICMUTE "micmute" ++#define LED_FUNCTION_MUTE "mute" ++ ++/* Miscelleaus functions. Use functions above if you can. */ + #define LED_FUNCTION_ACTIVITY "activity" + #define LED_FUNCTION_ALARM "alarm" + #define LED_FUNCTION_BACKLIGHT "backlight" + #define LED_FUNCTION_BLUETOOTH "bluetooth" + #define LED_FUNCTION_BOOT "boot" + #define LED_FUNCTION_CPU "cpu" +-#define LED_FUNCTION_CAPSLOCK "capslock" +-#define LED_FUNCTION_CHARGING "charging" + #define LED_FUNCTION_DEBUG "debug" +-#define LED_FUNCTION_DISK "disk" + #define LED_FUNCTION_DISK_ACTIVITY "disk-activity" + #define LED_FUNCTION_DISK_ERR "disk-err" + #define LED_FUNCTION_DISK_READ "disk-read" +@@ -50,21 +76,14 @@ + #define LED_FUNCTION_FLASH "flash" + #define LED_FUNCTION_HEARTBEAT "heartbeat" + #define LED_FUNCTION_INDICATOR "indicator" +-#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" + #define LED_FUNCTION_LAN "lan" + #define LED_FUNCTION_MAIL "mail" + #define LED_FUNCTION_MTD "mtd" +-#define LED_FUNCTION_MICMUTE "micmute" +-#define LED_FUNCTION_MUTE "mute" +-#define LED_FUNCTION_NUMLOCK "numlock" + #define LED_FUNCTION_PANIC "panic" + #define LED_FUNCTION_PROGRAMMING "programming" +-#define LED_FUNCTION_POWER "power" + #define LED_FUNCTION_RX "rx" + #define LED_FUNCTION_SD "sd" +-#define LED_FUNCTION_SCROLLLOCK "scrolllock" + #define LED_FUNCTION_STANDBY "standby" +-#define LED_FUNCTION_STATUS "status" + #define LED_FUNCTION_TORCH "torch" + #define LED_FUNCTION_TX "tx" + #define LED_FUNCTION_USB "usb" +diff -ruN u-boot-2021.10/include/dt-bindings/mailbox/sun20i-d1-msgbox.h u-boot/include/dt-bindings/mailbox/sun20i-d1-msgbox.h +--- u-boot-2021.10/include/dt-bindings/mailbox/sun20i-d1-msgbox.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/mailbox/sun20i-d1-msgbox.h 2021-11-01 17:10:14.622906130 +0100 +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ ++#define _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ ++ ++/* First cell: channel (transmitting user) */ ++#define MBOX_USER_CPUX 0 ++#define MBOX_USER_DSP 1 ++#define MBOX_USER_RISCV 2 ++ ++/* Second cell: direction (RX if phandle references local mailbox, else TX) */ ++#define MBOX_RX 0 ++#define MBOX_TX 1 ++ ++#endif /* _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/mfd/atmel-flexcom.h u-boot/include/dt-bindings/mfd/atmel-flexcom.h +--- u-boot-2021.10/include/dt-bindings/mfd/atmel-flexcom.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/mfd/atmel-flexcom.h 2021-11-01 17:10:14.622906130 +0100 +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * This header provides macros for Atmel Flexcom DT bindings. ++ * ++ * Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com> ++ */ ++ ++#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ ++#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ ++ ++#define ATMEL_FLEXCOM_MODE_USART 1 ++#define ATMEL_FLEXCOM_MODE_SPI 2 ++#define ATMEL_FLEXCOM_MODE_TWI 3 ++ ++#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ +diff -ruN u-boot-2021.10/include/dt-bindings/mfd/dbx500-prcmu.h u-boot/include/dt-bindings/mfd/dbx500-prcmu.h +--- u-boot-2021.10/include/dt-bindings/mfd/dbx500-prcmu.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/mfd/dbx500-prcmu.h 2021-11-01 17:10:14.622906130 +0100 +@@ -12,64 +12,64 @@ + */ + #define ARMCLK 0 + #define PRCMU_ACLK 1 +-#define PRCMU_SVAMMCSPCLK 2 +-#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ +-#define PRCMU_SIACLK 3 +-#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ +-#define PRCMU_SGACLK 4 +-#define PRCMU_UARTCLK 5 +-#define PRCMU_MSP02CLK 6 +-#define PRCMU_MSP1CLK 7 +-#define PRCMU_I2CCLK 8 +-#define PRCMU_SDMMCCLK 9 +-#define PRCMU_SLIMCLK 10 +-#define PRCMU_CAMCLK 10 /* DBx540 only. */ +-#define PRCMU_PER1CLK 11 +-#define PRCMU_PER2CLK 12 +-#define PRCMU_PER3CLK 13 +-#define PRCMU_PER5CLK 14 +-#define PRCMU_PER6CLK 15 +-#define PRCMU_PER7CLK 16 +-#define PRCMU_LCDCLK 17 +-#define PRCMU_BMLCLK 18 +-#define PRCMU_HSITXCLK 19 +-#define PRCMU_HSIRXCLK 20 ++#define PRCMU_SVAMMCSPCLK 2 ++#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ ++#define PRCMU_SIACLK 3 ++#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ ++#define PRCMU_SGACLK 4 ++#define PRCMU_UARTCLK 5 ++#define PRCMU_MSP02CLK 6 ++#define PRCMU_MSP1CLK 7 ++#define PRCMU_I2CCLK 8 ++#define PRCMU_SDMMCCLK 9 ++#define PRCMU_SLIMCLK 10 ++#define PRCMU_CAMCLK 10 /* DBx540 only. */ ++#define PRCMU_PER1CLK 11 ++#define PRCMU_PER2CLK 12 ++#define PRCMU_PER3CLK 13 ++#define PRCMU_PER5CLK 14 ++#define PRCMU_PER6CLK 15 ++#define PRCMU_PER7CLK 16 ++#define PRCMU_LCDCLK 17 ++#define PRCMU_BMLCLK 18 ++#define PRCMU_HSITXCLK 19 ++#define PRCMU_HSIRXCLK 20 + #define PRCMU_HDMICLK 21 +-#define PRCMU_APEATCLK 22 +-#define PRCMU_APETRACECLK 23 +-#define PRCMU_MCDECLK 24 +-#define PRCMU_IPI2CCLK 25 +-#define PRCMU_DSIALTCLK 26 +-#define PRCMU_DMACLK 27 +-#define PRCMU_B2R2CLK 28 +-#define PRCMU_TVCLK 29 +-#define SPARE_UNIPROCLK 30 +-#define PRCMU_SSPCLK 31 +-#define PRCMU_RNGCLK 32 +-#define PRCMU_UICCCLK 33 ++#define PRCMU_APEATCLK 22 ++#define PRCMU_APETRACECLK 23 ++#define PRCMU_MCDECLK 24 ++#define PRCMU_IPI2CCLK 25 ++#define PRCMU_DSIALTCLK 26 ++#define PRCMU_DMACLK 27 ++#define PRCMU_B2R2CLK 28 ++#define PRCMU_TVCLK 29 ++#define SPARE_UNIPROCLK 30 ++#define PRCMU_SSPCLK 31 ++#define PRCMU_RNGCLK 32 ++#define PRCMU_UICCCLK 33 + #define PRCMU_G1CLK 34 /* DBx540 only. */ + #define PRCMU_HVACLK 35 /* DBx540 only. */ +-#define PRCMU_SPARE1CLK 36 +-#define PRCMU_SPARE2CLK 37 ++#define PRCMU_SPARE1CLK 36 ++#define PRCMU_SPARE2CLK 37 + +-#define PRCMU_NUM_REG_CLOCKS 38 ++#define PRCMU_NUM_REG_CLOCKS 38 + +-#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS +-#define PRCMU_SYSCLK 39 +-#define PRCMU_CDCLK 40 +-#define PRCMU_TIMCLK 41 +-#define PRCMU_PLLSOC0 42 +-#define PRCMU_PLLSOC1 43 +-#define PRCMU_ARMSS 44 +-#define PRCMU_PLLDDR 45 ++#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS ++#define PRCMU_SYSCLK 39 ++#define PRCMU_CDCLK 40 ++#define PRCMU_TIMCLK 41 ++#define PRCMU_PLLSOC0 42 ++#define PRCMU_PLLSOC1 43 ++#define PRCMU_ARMSS 44 ++#define PRCMU_PLLDDR 45 + + /* DSI Clocks */ +-#define PRCMU_PLLDSI 46 +-#define PRCMU_DSI0CLK 47 +-#define PRCMU_DSI1CLK 48 +-#define PRCMU_DSI0ESCCLK 49 +-#define PRCMU_DSI1ESCCLK 50 +-#define PRCMU_DSI2ESCCLK 51 ++#define PRCMU_PLLDSI 46 ++#define PRCMU_DSI0CLK 47 ++#define PRCMU_DSI1CLK 48 ++#define PRCMU_DSI0ESCCLK 49 ++#define PRCMU_DSI1ESCCLK 50 ++#define PRCMU_DSI2ESCCLK 51 + + /* LCD DSI PLL - Ux540 only */ + #define PRCMU_PLLDSI_LCD 52 +@@ -79,6 +79,6 @@ + #define PRCMU_DSI1ESCCLK_LCD 56 + #define PRCMU_DSI2ESCCLK_LCD 57 + +-#define PRCMU_NUM_CLKS 58 ++#define PRCMU_NUM_CLKS 58 + + #endif +diff -ruN u-boot-2021.10/include/dt-bindings/net/ti-dp83867.h u-boot/include/dt-bindings/net/ti-dp83867.h +--- u-boot-2021.10/include/dt-bindings/net/ti-dp83867.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/net/ti-dp83867.h 2021-11-01 17:10:14.626239281 +0100 +@@ -1,7 +1,10 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ ++/* SPDX-License-Identifier: GPL-2.0-only */ + /* +- * TI DP83867 PHY drivers ++ * Device Tree constants for the Texas Instruments DP83867 PHY + * ++ * Author: Dan Murphy <dmurphy@ti.com> ++ * ++ * Copyright: (C) 2015 Texas Instruments, Inc. + */ + + #ifndef _DT_BINDINGS_TI_DP83867_H +@@ -14,22 +17,22 @@ + #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + + /* RGMIIDCTL internal delay for rx and tx */ +-#define DP83867_RGMIIDCTL_250_PS 0x0 +-#define DP83867_RGMIIDCTL_500_PS 0x1 +-#define DP83867_RGMIIDCTL_750_PS 0x2 +-#define DP83867_RGMIIDCTL_1_NS 0x3 +-#define DP83867_RGMIIDCTL_1_25_NS 0x4 +-#define DP83867_RGMIIDCTL_1_50_NS 0x5 +-#define DP83867_RGMIIDCTL_1_75_NS 0x6 +-#define DP83867_RGMIIDCTL_2_00_NS 0x7 +-#define DP83867_RGMIIDCTL_2_25_NS 0x8 +-#define DP83867_RGMIIDCTL_2_50_NS 0x9 +-#define DP83867_RGMIIDCTL_2_75_NS 0xa +-#define DP83867_RGMIIDCTL_3_00_NS 0xb +-#define DP83867_RGMIIDCTL_3_25_NS 0xc +-#define DP83867_RGMIIDCTL_3_50_NS 0xd +-#define DP83867_RGMIIDCTL_3_75_NS 0xe +-#define DP83867_RGMIIDCTL_4_00_NS 0xf ++#define DP83867_RGMIIDCTL_250_PS 0x0 ++#define DP83867_RGMIIDCTL_500_PS 0x1 ++#define DP83867_RGMIIDCTL_750_PS 0x2 ++#define DP83867_RGMIIDCTL_1_NS 0x3 ++#define DP83867_RGMIIDCTL_1_25_NS 0x4 ++#define DP83867_RGMIIDCTL_1_50_NS 0x5 ++#define DP83867_RGMIIDCTL_1_75_NS 0x6 ++#define DP83867_RGMIIDCTL_2_00_NS 0x7 ++#define DP83867_RGMIIDCTL_2_25_NS 0x8 ++#define DP83867_RGMIIDCTL_2_50_NS 0x9 ++#define DP83867_RGMIIDCTL_2_75_NS 0xa ++#define DP83867_RGMIIDCTL_3_00_NS 0xb ++#define DP83867_RGMIIDCTL_3_25_NS 0xc ++#define DP83867_RGMIIDCTL_3_50_NS 0xd ++#define DP83867_RGMIIDCTL_3_75_NS 0xe ++#define DP83867_RGMIIDCTL_4_00_NS 0xf + + /* IO_MUX_CFG - Clock output selection */ + #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +diff -ruN u-boot-2021.10/include/dt-bindings/pinctrl/dra.h u-boot/include/dt-bindings/pinctrl/dra.h +--- u-boot-2021.10/include/dt-bindings/pinctrl/dra.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/pinctrl/dra.h 2021-11-01 17:10:14.626239281 +0100 +@@ -77,4 +77,3 @@ + #define A_DELAY_PS(val) ((val) & 0xffff) + #define G_DELAY_PS(val) ((val) & 0xffff) + #endif +- +diff -ruN u-boot-2021.10/include/dt-bindings/pinctrl/k3.h u-boot/include/dt-bindings/pinctrl/k3.h +--- u-boot-2021.10/include/dt-bindings/pinctrl/k3.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/pinctrl/k3.h 2021-11-01 17:10:14.626239281 +0100 +@@ -1,36 +1,33 @@ + /* SPDX-License-Identifier: GPL-2.0 */ + /* +- * This header provides constants for TI K3-AM65 pinctrl bindings. ++ * This header provides constants for pinctrl bindings for TI's K3 SoC ++ * family. + * +- * Copyright (C) 2018-2021 Texas Instruments ++ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ +-#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H +-#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H ++#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H ++#define _DT_BINDINGS_PINCTRL_TI_K3_H + +-#define PULL_DISABLE (1 << 16) +-#define PULL_UP (1 << 17) +-#define INPUT_EN (1 << 18) +-#define SLEWCTRL_200MHZ 0 +-#define SLEWCTRL_150MHZ (1 << 19) +-#define SLEWCTRL_100MHZ (2 << 19) +-#define SLEWCTRL_50MHZ (3 << 19) +-#define TX_DIS (1 << 21) +-#define ISO_OVR (1 << 22) +-#define ISO_BYPASS (1 << 23) +-#define DS_EN (1 << 24) +-#define DS_INPUT (1 << 25) +-#define DS_FORCE_OUT_HIGH (1 << 26) +-#define DS_PULL_UP_DOWN_EN 0 +-#define DS_PULL_UP_DOWN_DIS (1 << 27) +-#define DS_PULL_UP_SEL (1 << 28) +-#define WAKEUP_ENABLE (1 << 29) +- +-#define PIN_OUTPUT (PULL_DISABLE) +-#define PIN_OUTPUT_PULLUP (PULL_UP) +-#define PIN_OUTPUT_PULLDOWN 0 ++#define PULLUDEN_SHIFT (16) ++#define PULLTYPESEL_SHIFT (17) ++#define RXACTIVE_SHIFT (18) ++ ++#define PULL_DISABLE (1 << PULLUDEN_SHIFT) ++#define PULL_ENABLE (0 << PULLUDEN_SHIFT) ++ ++#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) ++#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) ++ ++#define INPUT_EN (1 << RXACTIVE_SHIFT) ++#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) ++ ++/* Only these macros are expected be used directly in device tree files */ ++#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) ++#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) ++#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) + #define PIN_INPUT (INPUT_EN | PULL_DISABLE) + #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +-#define PIN_INPUT_PULLDOWN (INPUT_EN) ++#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + + #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +diff -ruN u-boot-2021.10/include/dt-bindings/pinctrl/omap.h u-boot/include/dt-bindings/pinctrl/omap.h +--- u-boot-2021.10/include/dt-bindings/pinctrl/omap.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/pinctrl/omap.h 2021-11-01 17:10:14.626239281 +0100 +@@ -89,4 +89,3 @@ + #define OMAP4_UART4_RX 0x11c + + #endif +- +diff -ruN u-boot-2021.10/include/dt-bindings/pinctrl/stm32-pinfunc.h u-boot/include/dt-bindings/pinctrl/stm32-pinfunc.h +--- u-boot-2021.10/include/dt-bindings/pinctrl/stm32-pinfunc.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/pinctrl/stm32-pinfunc.h 2021-11-01 17:10:14.626239281 +0100 +@@ -39,4 +39,3 @@ + #define STM32MP_PKG_AD 0x8 + + #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ +- +diff -ruN u-boot-2021.10/include/dt-bindings/reset/sun20i-d1-ccu.h u-boot/include/dt-bindings/reset/sun20i-d1-ccu.h +--- u-boot-2021.10/include/dt-bindings/reset/sun20i-d1-ccu.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/reset/sun20i-d1-ccu.h 2021-11-01 17:10:14.629572432 +0100 +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (c) 2020 huangzhenwei@allwinnertech.com ++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ ++#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ ++ ++#define RST_MBUS 0 ++#define RST_BUS_DE 1 ++#define RST_BUS_DI 2 ++#define RST_BUS_G2D 3 ++#define RST_BUS_CE 4 ++#define RST_BUS_VE 5 ++#define RST_BUS_DMA 6 ++#define RST_BUS_MSGBOX0 7 ++#define RST_BUS_MSGBOX1 8 ++#define RST_BUS_MSGBOX2 9 ++#define RST_BUS_SPINLOCK 10 ++#define RST_BUS_HSTIMER 11 ++#define RST_BUS_DBG 12 ++#define RST_BUS_PWM 13 ++#define RST_BUS_DRAM 14 ++#define RST_BUS_MMC0 15 ++#define RST_BUS_MMC1 16 ++#define RST_BUS_MMC2 17 ++#define RST_BUS_UART0 18 ++#define RST_BUS_UART1 19 ++#define RST_BUS_UART2 20 ++#define RST_BUS_UART3 21 ++#define RST_BUS_UART4 22 ++#define RST_BUS_UART5 23 ++#define RST_BUS_I2C0 24 ++#define RST_BUS_I2C1 25 ++#define RST_BUS_I2C2 26 ++#define RST_BUS_I2C3 27 ++#define RST_BUS_SPI0 28 ++#define RST_BUS_SPI1 29 ++#define RST_BUS_EMAC 30 ++#define RST_BUS_IR_TX 31 ++#define RST_BUS_GPADC 32 ++#define RST_BUS_THS 33 ++#define RST_BUS_I2S0 34 ++#define RST_BUS_I2S1 35 ++#define RST_BUS_I2S2 36 ++#define RST_BUS_SPDIF 37 ++#define RST_BUS_DMIC 38 ++#define RST_BUS_AUDIO 39 ++#define RST_USB_PHY0 40 ++#define RST_USB_PHY1 41 ++#define RST_BUS_OHCI0 42 ++#define RST_BUS_OHCI1 43 ++#define RST_BUS_EHCI0 44 ++#define RST_BUS_EHCI1 45 ++#define RST_BUS_OTG 46 ++#define RST_BUS_LRADC 47 ++#define RST_BUS_DPSS_TOP 48 ++#define RST_BUS_HDMI_SUB 49 ++#define RST_BUS_HDMI_MAIN 50 ++#define RST_BUS_MIPI_DSI 51 ++#define RST_BUS_TCON_LCD0 52 ++#define RST_BUS_TCON_TV 53 ++#define RST_BUS_LVDS0 54 ++#define RST_BUS_TVE 55 ++#define RST_BUS_TVE_TOP 56 ++#define RST_BUS_TVD 57 ++#define RST_BUS_TVD_TOP 58 ++#define RST_BUS_LEDC 59 ++#define RST_BUS_CSI 60 ++#define RST_BUS_TPADC 61 ++#define RST_DSP 62 ++#define RST_BUS_DSP_CFG 63 ++#define RST_BUS_DSP_DBG 64 ++#define RST_BUS_RISCV_CFG 65 ++ ++#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/reset/sun20i-d1-r-ccu.h u-boot/include/dt-bindings/reset/sun20i-d1-r-ccu.h +--- u-boot-2021.10/include/dt-bindings/reset/sun20i-d1-r-ccu.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/dt-bindings/reset/sun20i-d1-r-ccu.h 2021-11-01 17:10:14.629572432 +0100 +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ ++#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ ++ ++#define RST_BUS_R_TIMER 0 ++#define RST_BUS_R_TWD 1 ++#define RST_BUS_R_PPU 2 ++#define RST_BUS_R_IR_RX 3 ++#define RST_BUS_R_RTC 4 ++#define RST_BUS_R_CPUCFG 5 ++ ++#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ +diff -ruN u-boot-2021.10/include/dt-bindings/thermal/thermal.h u-boot/include/dt-bindings/thermal/thermal.h +--- u-boot-2021.10/include/dt-bindings/thermal/thermal.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-bindings/thermal/thermal.h 2021-11-01 17:10:14.632905584 +0100 +@@ -13,4 +13,3 @@ + #define THERMAL_NO_LIMIT (~0) + + #endif +- +diff -ruN u-boot-2021.10/include/dt-structs.h u-boot/include/dt-structs.h +--- u-boot-2021.10/include/dt-structs.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/dt-structs.h 2021-11-01 17:10:14.632905584 +0100 +@@ -10,16 +10,43 @@ + #if CONFIG_IS_ENABLED(OF_PLATDATA) + struct driver_info; + ++/** ++ * struct phandle_0_arg - hold a phandle record with no arguments ++ * ++ * This holds a phandle pointing to another device. See 'Indexes' in the ++ * of-plat-rst documentation. ++ * ++ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) ++ * @arg: arguments ++ */ + struct phandle_0_arg { + uint idx; + int arg[0]; + }; + ++/** ++ * struct phandle_2_arg - hold a phandle record with up to one argument ++ * ++ * This holds a phandle pointing to another device. See 'Indexes' in the ++ * of-plat-rst documentation. ++ * ++ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) ++ * @arg: arguments ++ */ + struct phandle_1_arg { + uint idx; + int arg[1]; + }; + ++/** ++ * struct phandle_2_arg - hold a phandle record with up to two arguments ++ * ++ * This holds a phandle pointing to another device. See 'Indexes' in the ++ * of-plat-rst documentation. ++ * ++ * @idx: udevice index (or driver_info index if !OF_PLATDATA_INST) ++ * @arg: arguments ++ */ + struct phandle_2_arg { + uint idx; + int arg[2]; +diff -ruN u-boot-2021.10/include/eeprom.h u-boot/include/eeprom.h +--- u-boot-2021.10/include/eeprom.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/eeprom.h 2021-11-01 17:10:14.632905584 +0100 +@@ -21,8 +21,4 @@ + #define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS) + #endif + +-#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +-# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR +-#endif +- + #endif +diff -ruN u-boot-2021.10/include/env_default.h u-boot/include/env_default.h +--- u-boot-2021.10/include/env_default.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/env_default.h 2021-11-01 17:10:14.636238735 +0100 +@@ -82,8 +82,8 @@ + #ifdef CONFIG_BOOTFILE + "bootfile=" CONFIG_BOOTFILE "\0" + #endif +-#ifdef CONFIG_LOADADDR +- "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" ++#ifdef CONFIG_SYS_LOAD_ADDR ++ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" + #endif + #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" +diff -ruN u-boot-2021.10/include/environment/distro/sf.h u-boot/include/environment/distro/sf.h +--- u-boot-2021.10/include/environment/distro/sf.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/environment/distro/sf.h 2021-11-01 17:10:14.636238735 +0100 +@@ -10,16 +10,16 @@ + + #if CONFIG_IS_ENABLED(CMD_SF) + #define BOOTENV_SHARED_SF(devtypel) \ +- #devtypel "_boot=" \ ++ #devtypel "_boot=" \ + "if " #devtypel " probe ${busnum}; then " \ +- "devtype=" #devtypel "; " \ +- "run scan_sf_for_scripts; " \ ++ "devtype=" #devtypel "; " \ ++ "run scan_sf_for_scripts; " \ + "fi\0" +-#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ +- "bootcmd_" #devtypel #instance "=" \ +- "busnum=" #instance "; " \ ++#define BOOTENV_DEV_SF(devtypeu, devtypel, instance) \ ++ "bootcmd_" #devtypel #instance "=" \ ++ "busnum=" #instance "; " \ + "run " #devtypel "_boot\0" +-#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ ++#define BOOTENV_DEV_NAME_SF(devtypeu, devtypel, instance) \ + #devtypel #instance " " + #else + #define BOOTENV_SHARED_SF(devtypel) +diff -ruN u-boot-2021.10/include/environment/ti/nand.h u-boot/include/environment/ti/nand.h +--- u-boot-2021.10/include/environment/ti/nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/environment/ti/nand.h 2021-11-01 17:10:14.636238735 +0100 +@@ -23,4 +23,3 @@ + #else + #define NANDARGS "" + #endif +- +diff -ruN u-boot-2021.10/include/faraday/ftpmu010.h u-boot/include/faraday/ftpmu010.h +--- u-boot-2021.10/include/faraday/ftpmu010.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/faraday/ftpmu010.h 2021-11-01 17:10:14.636238735 +0100 +@@ -137,7 +137,7 @@ + * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: + * Datasheet indicated it starts at bit #21 which was wrong. + * 2. FTPMU010_PDLLCR0_DLLFRAG: +- * Datasheet indicated it has 2 bit which was wrong. ++ * Datasheet indicated it has 2 bit which was wrong. + */ + #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) + #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) +diff -ruN u-boot-2021.10/include/fdtdec.h u-boot/include/fdtdec.h +--- u-boot-2021.10/include/fdtdec.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/fdtdec.h 2021-11-01 17:10:14.636238735 +0100 +@@ -746,39 +746,6 @@ + */ + int fdtdec_get_child_count(const void *blob, int node); + +-/** +- * Look in the FDT for a config item with the given name and return its value +- * as a 32-bit integer. The property must have at least 4 bytes of data. The +- * value of the first cell is returned. +- * +- * @param blob FDT blob to use +- * @param prop_name Node property name +- * @param default_val default value to return if the property is not found +- * @return integer value, if found, or default_val if not +- */ +-int fdtdec_get_config_int(const void *blob, const char *prop_name, +- int default_val); +- +-/** +- * Look in the FDT for a config item with the given name +- * and return whether it exists. +- * +- * @param blob FDT blob +- * @param prop_name property name to look up +- * @return 1, if it exists, or 0 if not +- */ +-int fdtdec_get_config_bool(const void *blob, const char *prop_name); +- +-/** +- * Look in the FDT for a config item with the given name and return its value +- * as a string. +- * +- * @param blob FDT blob +- * @param prop_name property name to look up +- * @returns property string, NULL on error. +- */ +-char *fdtdec_get_config_string(const void *blob, const char *prop_name); +- + /* + * Look up a property in a node and return its contents in a byte + * array of given length. The property must have at least enough data for +diff -ruN u-boot-2021.10/include/fdt_support.h u-boot/include/fdt_support.h +--- u-boot-2021.10/include/fdt_support.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/fdt_support.h 2021-11-01 17:10:14.636238735 +0100 +@@ -203,8 +203,6 @@ + * called at the end of the image_setup_libfdt() is to do that convertion. + */ + void ft_board_setup_ex(void *blob, struct bd_info *bd); +-void ft_cpu_setup(void *blob, struct bd_info *bd); +-void ft_pci_setup(void *blob, struct bd_info *bd); + + /** + * Add system-specific data to the FDT before booting the OS. +diff -ruN u-boot-2021.10/include/fsl-mc/fsl_dpni.h u-boot/include/fsl-mc/fsl_dpni.h +--- u-boot-2021.10/include/fsl-mc/fsl_dpni.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/fsl-mc/fsl_dpni.h 2021-11-01 17:10:14.639571885 +0100 +@@ -173,8 +173,6 @@ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ + } while (0) + +- +- + /* cmd, param, offset, width, type, arg_name */ + #define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ + do { \ +diff -ruN u-boot-2021.10/include/fsl_qe.h u-boot/include/fsl_qe.h +--- u-boot-2021.10/include/fsl_qe.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/fsl_qe.h 2021-11-01 17:10:14.642905036 +0100 +@@ -40,7 +40,7 @@ + #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ + #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ + #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +-#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ ++#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) + #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ +diff -ruN u-boot-2021.10/include/fsl_wdog.h u-boot/include/fsl_wdog.h +--- u-boot-2021.10/include/fsl_wdog.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/fsl_wdog.h 2021-11-01 17:10:14.642905036 +0100 +@@ -14,6 +14,6 @@ + #define WCR_WDE 0x04 + #define WCR_WDT 0x08 + #define WCR_SRS 0x10 +-#define WCR_WDA 0x20 ++#define WCR_WDA 0x20 + #define SET_WCR_WT(x) (x << 8) + #define WCR_WT_MSK SET_WCR_WT(0xFF) +diff -ruN u-boot-2021.10/include/generic-phy.h u-boot/include/generic-phy.h +--- u-boot-2021.10/include/generic-phy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/generic-phy.h 2021-11-01 17:10:14.642905036 +0100 +@@ -201,7 +201,7 @@ + * generic_phy_configure() - configure a PHY device + * + * @phy: PHY port to be configured +- * @params: PHY Parameters, underlying data is specific to the PHY function ++ * @params: PHY Parameters, underlying data is specific to the PHY function + * @return 0 if OK, or a negative error code + */ + int generic_phy_configure(struct phy *phy, void *params); +diff -ruN u-boot-2021.10/include/i2c.h u-boot/include/i2c.h +--- u-boot-2021.10/include/i2c.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/i2c.h 2021-11-01 17:10:14.642905036 +0100 +@@ -610,6 +610,10 @@ + */ + int acpi_i2c_of_to_plat(struct udevice *dev); + ++#ifdef CONFIG_SYS_I2C_EARLY_INIT ++void i2c_early_init_f(void); ++#endif ++ + #if !CONFIG_IS_ENABLED(DM_I2C) + + /* +@@ -743,26 +747,13 @@ + #endif + + /* +- * Many boards/controllers/drivers don't support an I2C slave interface so +- * provide a default slave address for them for use in common code. A real +- * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does +- * support a slave interface. +- */ +-#ifndef CONFIG_SYS_I2C_SLAVE +-#define CONFIG_SYS_I2C_SLAVE 0xfe +-#endif +- +-/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +-#ifdef CONFIG_SYS_I2C_EARLY_INIT +-void i2c_early_init_f(void); +-#endif + void i2c_init(int speed, int slaveaddr); + void i2c_init_board(void); + +-#ifdef CONFIG_SYS_I2C_LEGACY ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + /* + * i2c_get_bus_num: + * +@@ -942,7 +933,7 @@ + * only for backwardcompatibility, should go away if we switched + * completely to new multibus support. + */ +-#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) ++#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) + # if !defined(CONFIG_SYS_MAX_I2C_BUS) + # define CONFIG_SYS_MAX_I2C_BUS 2 + # endif +diff -ruN u-boot-2021.10/include/i8042.h u-boot/include/i8042.h +--- u-boot-2021.10/include/i8042.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/i8042.h 2021-11-01 17:10:14.642905036 +0100 +@@ -20,12 +20,12 @@ + #define STATUS_IBF (1 << 1) + + /* Configuration byte bit defines */ +-#define CONFIG_KIRQ_EN (1 << 0) +-#define CONFIG_MIRQ_EN (1 << 1) +-#define CONFIG_SET_BIST (1 << 2) +-#define CONFIG_KCLK_DIS (1 << 4) +-#define CONFIG_MCLK_DIS (1 << 5) +-#define CONFIG_AT_TRANS (1 << 6) ++#define CFG_KIRQ_EN (1 << 0) ++#define CFG_MIRQ_EN (1 << 1) ++#define CFG_SET_BIST (1 << 2) ++#define CFG_KCLK_DIS (1 << 4) ++#define CFG_MCLK_DIS (1 << 5) ++#define CFG_AT_TRANS (1 << 6) + + /* i8042 commands */ + #define CMD_RD_CONFIG 0x20 /* read configuration byte */ +diff -ruN u-boot-2021.10/include/image.h u-boot/include/image.h +--- u-boot-2021.10/include/image.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/image.h 2021-11-01 17:10:14.646238188 +0100 +@@ -262,6 +262,8 @@ + IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ + IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ + IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ ++ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */ ++ IH_TYPE_SUNXI_TOC1, /* Allwinner TOC1 Boot Image */ + + IH_TYPE_COUNT, /* Number of image types */ + }; +diff -ruN u-boot-2021.10/include/imximage.h u-boot/include/imximage.h +--- u-boot-2021.10/include/imximage.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/imximage.h 2021-11-01 17:10:14.646238188 +0100 +@@ -124,7 +124,7 @@ + } flash_header_v1_t; + + typedef struct { +- uint32_t length; /* Length of data to be read from flash */ ++ uint32_t length; /* Length of data to be read from flash */ + } flash_cfg_parms_t; + + typedef struct { +diff -ruN u-boot-2021.10/include/irq.h u-boot/include/irq.h +--- u-boot-2021.10/include/irq.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/irq.h 2021-11-01 17:10:14.646238188 +0100 +@@ -200,6 +200,35 @@ + */ + int irq_read_and_clear(struct irq *irq); + ++struct phandle_2_arg; ++/** ++ * irq_get_by_phandle() - Get an irq by its phandle information (of-platadata) ++ * ++ * This function is used when of-platdata is enabled. ++ * ++ * This looks up an irq using the phandle info. With dtoc, each phandle in the ++ * 'interrupts-extended ' property is transformed into an idx representing the ++ * device. For example: ++ * ++ * interrupts-extended = <&acpi_gpe 0x3c 0>; ++ * ++ * might result in: ++ * ++ * .interrupts_extended = {6, {0x3c, 0}},}, ++ * ++ * indicating that the irq is udevice idx 6 in dt-plat.c with a arguments of ++ * 0x3c and 0.This function can return a valid irq given the above ++ * information. In this example it would return an irq containing the ++ * 'acpi_gpe' device and the irq ID 0x3c. ++ * ++ * @dev: Device containing the phandle ++ * @cells: Phandle info ++ * @irq: A pointer to a irq struct to initialise ++ * @return 0 if OK, or a negative error code ++ */ ++int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells, ++ struct irq *irq); ++ + /** + * irq_get_by_index - Get/request an irq by integer index. + * +diff -ruN u-boot-2021.10/include/linux/apm_bios.h u-boot/include/linux/apm_bios.h +--- u-boot-2021.10/include/linux/apm_bios.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/apm_bios.h 2021-11-01 17:10:14.649571339 +0100 +@@ -34,7 +34,7 @@ + #define APM_16_BIT_SUPPORT 0x0001 + #define APM_32_BIT_SUPPORT 0x0002 + #define APM_IDLE_SLOWS_CLOCK 0x0004 +-#define APM_BIOS_DISABLED 0x0008 ++#define APM_BIOS_DISABLED 0x0008 + #define APM_BIOS_DISENGAGED 0x0010 + + /* +diff -ruN u-boot-2021.10/include/linux/compiler.h u-boot/include/linux/compiler.h +--- u-boot-2021.10/include/linux/compiler.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/compiler.h 2021-11-01 17:10:14.649571339 +0100 +@@ -203,7 +203,7 @@ + /* + * We can't declare function 'inline' because __no_sanitize_address confilcts + * with inlining. Attempt to inline it may cause a build failure. +- * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 ++ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + * '__maybe_unused' allows us to avoid defined-but-not-used warnings. + */ + # define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused +diff -ruN u-boot-2021.10/include/linux/ioport.h u-boot/include/linux/ioport.h +--- u-boot-2021.10/include/linux/ioport.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/ioport.h 2021-11-01 17:10:14.652904489 +0100 +@@ -63,7 +63,7 @@ + #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) + #define IORESOURCE_IRQ_LOWLEVEL (1<<3) + #define IORESOURCE_IRQ_SHAREABLE (1<<4) +-#define IORESOURCE_IRQ_OPTIONAL (1<<5) ++#define IORESOURCE_IRQ_OPTIONAL (1<<5) + + /* PnP DMA specific bits (IORESOURCE_BITS) */ + #define IORESOURCE_DMA_TYPE_MASK (3<<0) +diff -ruN u-boot-2021.10/include/linux/list.h u-boot/include/linux/list.h +--- u-boot-2021.10/include/linux/list.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/list.h 2021-11-01 17:10:14.652904489 +0100 +@@ -456,7 +456,7 @@ + * Continue to iterate over list of given type, continuing after + * the current position. + */ +-#define list_for_each_entry_continue(pos, head, member) \ ++#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) +@@ -510,7 +510,7 @@ + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +-#define list_for_each_entry_safe_continue(pos, n, head, member) \ ++#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ +diff -ruN u-boot-2021.10/include/linux/mtd/bbm.h u-boot/include/linux/mtd/bbm.h +--- u-boot-2021.10/include/linux/mtd/bbm.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/mtd/bbm.h 2021-11-01 17:10:14.652904489 +0100 +@@ -15,11 +15,6 @@ + #ifndef __LINUX_MTD_BBM_H + #define __LINUX_MTD_BBM_H + +-/* The maximum number of NAND chips in an array */ +-#ifndef CONFIG_SYS_NAND_MAX_CHIPS +-#define CONFIG_SYS_NAND_MAX_CHIPS 1 +-#endif +- + /** + * struct nand_bbt_descr - bad block table descriptor + * @options: options for this descriptor +diff -ruN u-boot-2021.10/include/linux/mtd/doc2000.h u-boot/include/linux/mtd/doc2000.h +--- u-boot-2021.10/include/linux/mtd/doc2000.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/mtd/doc2000.h 2021-11-01 17:10:14.652904489 +0100 +@@ -54,7 +54,7 @@ + #define DoC_Mplus_Configuration 0x100a + #define DoC_Mplus_OutputControl 0x100c + #define DoC_Mplus_FlashControl 0x1020 +-#define DoC_Mplus_FlashSelect 0x1022 ++#define DoC_Mplus_FlashSelect 0x1022 + #define DoC_Mplus_FlashCmd 0x1024 + #define DoC_Mplus_FlashAddress 0x1026 + #define DoC_Mplus_FlashData0 0x1028 +@@ -62,14 +62,14 @@ + #define DoC_Mplus_ReadPipeInit 0x102a + #define DoC_Mplus_LastDataRead 0x102c + #define DoC_Mplus_LastDataRead1 0x102d +-#define DoC_Mplus_WritePipeTerm 0x102e ++#define DoC_Mplus_WritePipeTerm 0x102e + #define DoC_Mplus_ECCSyndrome0 0x1040 + #define DoC_Mplus_ECCSyndrome1 0x1041 + #define DoC_Mplus_ECCSyndrome2 0x1042 + #define DoC_Mplus_ECCSyndrome3 0x1043 + #define DoC_Mplus_ECCSyndrome4 0x1044 + #define DoC_Mplus_ECCSyndrome5 0x1045 +-#define DoC_Mplus_ECCConf 0x1046 ++#define DoC_Mplus_ECCConf 0x1046 + #define DoC_Mplus_Toggle 0x1046 + #define DoC_Mplus_DownloadStatus 0x1074 + #define DoC_Mplus_CtrlConfirm 0x1076 +diff -ruN u-boot-2021.10/include/linux/mtd/flashchip.h u-boot/include/linux/mtd/flashchip.h +--- u-boot-2021.10/include/linux/mtd/flashchip.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/mtd/flashchip.h 2021-11-01 17:10:14.652904489 +0100 +@@ -52,7 +52,6 @@ + } flstate_t; + + +- + /* NOTE: confusingly, this can be used to refer to more than one chip at a time, + if they're interleaved. This can even refer to individual partitions on + the same physical chip when present. */ +diff -ruN u-boot-2021.10/include/linux/mtd/partitions.h u-boot/include/linux/mtd/partitions.h +--- u-boot-2021.10/include/linux/mtd/partitions.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/mtd/partitions.h 2021-11-01 17:10:14.652904489 +0100 +@@ -21,16 +21,16 @@ + * For each partition, these fields are available: + * name: string that will be used to label the partition's MTD device. + * size: the partition size; if defined as MTDPART_SIZ_FULL, the partition +- * will extend to the end of the master MTD device. ++ * will extend to the end of the master MTD device. + * offset: absolute starting position within the master MTD device; if +- * defined as MTDPART_OFS_APPEND, the partition will start where the ++ * defined as MTDPART_OFS_APPEND, the partition will start where the + * previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block; + * if MTDPART_OFS_RETAIN, consume as much as possible, leaving size + * after the end of partition. + * mask_flags: contains flags that have to be masked (removed) from the +- * master MTD flag set for the corresponding MTD partition. +- * For example, to force a read-only partition, simply adding +- * MTD_WRITEABLE to the mask_flags will do the trick. ++ * master MTD flag set for the corresponding MTD partition. ++ * For example, to force a read-only partition, simply adding ++ * MTD_WRITEABLE to the mask_flags will do the trick. + * + * Note: writeable partitions require their size and offset be + * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). +diff -ruN u-boot-2021.10/include/linux/mtd/rawnand.h u-boot/include/linux/mtd/rawnand.h +--- u-boot-2021.10/include/linux/mtd/rawnand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/mtd/rawnand.h 2021-11-01 17:10:14.652904489 +0100 +@@ -945,7 +945,7 @@ + int jedec_version; + struct nand_onfi_params onfi_params; + struct nand_jedec_params jedec_params; +- ++ + struct nand_data_interface *data_interface; + + int read_retries; +diff -ruN u-boot-2021.10/include/linux/screen_info.h u-boot/include/linux/screen_info.h +--- u-boot-2021.10/include/linux/screen_info.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/screen_info.h 2021-11-01 17:10:14.656237640 +0100 +@@ -47,7 +47,7 @@ + } __attribute__((packed)); + + #define VIDEO_TYPE_MDA 0x10 /* Monochrome Text Display */ +-#define VIDEO_TYPE_CGA 0x11 /* CGA Display */ ++#define VIDEO_TYPE_CGA 0x11 /* CGA Display */ + #define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */ + #define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */ + #define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */ +@@ -74,7 +74,7 @@ + #define ORIG_X (screen_info.orig_x) + #define ORIG_Y (screen_info.orig_y) + #define ORIG_VIDEO_MODE (screen_info.orig_video_mode) +-#define ORIG_VIDEO_COLS (screen_info.orig_video_cols) ++#define ORIG_VIDEO_COLS (screen_info.orig_video_cols) + #define ORIG_VIDEO_EGA_BX (screen_info.orig_video_ega_bx) + #define ORIG_VIDEO_LINES (screen_info.orig_video_lines) + #define ORIG_VIDEO_ISVGA (screen_info.orig_video_isVGA) +diff -ruN u-boot-2021.10/include/linux/serial_reg.h u-boot/include/linux/serial_reg.h +--- u-boot-2021.10/include/linux/serial_reg.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/serial_reg.h 2021-11-01 17:10:14.656237640 +0100 +@@ -3,7 +3,7 @@ + * include/linux/serial_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. +- * ++ * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). +@@ -88,7 +88,7 @@ + + #define UART_LCR 3 /* Out: Line Control Register */ + /* +- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting ++ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ + #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +@@ -257,7 +257,7 @@ + */ + #define UART_ASR 0x01 /* Additional Status Register */ + #define UART_RFL 0x03 /* Receiver FIFO level */ +-#define UART_TFL 0x04 /* Transmitter FIFO level */ ++#define UART_TFL 0x04 /* Transmitter FIFO level */ + #define UART_ICR 0x05 /* Index Control Register */ + + /* The 16950 ICR registers */ +@@ -288,7 +288,6 @@ + #define UART_ACR_ASREN 0x80 /* Additional status enable */ + + +- + /* + * These definitions are for the RSA-DV II/S card, from + * +@@ -384,4 +383,3 @@ + #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ + + #endif /* _LINUX_SERIAL_REG_H */ +- +diff -ruN u-boot-2021.10/include/linux/usb/gadget.h u-boot/include/linux/usb/gadget.h +--- u-boot-2021.10/include/linux/usb/gadget.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/linux/usb/gadget.h 2021-11-01 17:10:14.656237640 +0100 +@@ -160,14 +160,14 @@ + * endpoint. It's set once by UDC driver when endpoint is initialized, and + * should not be changed. Should not be confused with maxpacket. + * @max_streams: The maximum number of streams supported +- * by this EP (0 - 16, actual number is 2^n) ++ * by this EP (0 - 16, actual number is 2^n) + * @maxburst: the maximum number of bursts supported by this EP (for usb3) + * @driver_data:for use by the gadget driver. all other fields are + * read-only to gadget drivers. + * @desc: endpoint descriptor. This pointer is set before the endpoint is +- * enabled and remains valid until the endpoint is disabled. ++ * enabled and remains valid until the endpoint is disabled. + * @comp_desc: In case of SuperSpeed support, this is the endpoint companion +- * descriptor that is used to configure the endpoint ++ * descriptor that is used to configure the endpoint + * + * the bus controller driver lists all the general purpose endpoints in + * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, +diff -ruN u-boot-2021.10/include/lmb.h u-boot/include/lmb.h +--- u-boot-2021.10/include/lmb.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/lmb.h 2021-11-01 17:10:14.659570792 +0100 +@@ -122,6 +122,7 @@ + + void board_lmb_reserve(struct lmb *lmb); + void arch_lmb_reserve(struct lmb *lmb); ++void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align); + + /* Low level functions */ + +diff -ruN u-boot-2021.10/include/mc13783.h u-boot/include/mc13783.h +--- u-boot-2021.10/include/mc13783.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mc13783.h 2021-11-01 17:10:14.659570792 +0100 +@@ -18,7 +18,7 @@ + #define VIOLOEN (1 << 6) + #define VIOLOSTBY (1 << 7) + #define VIOLOMODE (1 << 8) +-#define VDIGEN (1 << 9) ++#define VDIGEN (1 << 9) + #define VDIGSTBY (1 << 10) + #define VDIGMODE (1 << 11) + #define VGENEN (1 << 12) +diff -ruN u-boot-2021.10/include/mpc83xx.h u-boot/include/mpc83xx.h +--- u-boot-2021.10/include/mpc83xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mpc83xx.h 2021-11-01 17:10:14.659570792 +0100 +@@ -1372,7 +1372,7 @@ + #endif /* !CONFIG_MPC83XX_SDRAM */ + + /* +- * CONFIG_ADDRESS - PCI Config Address Register ++ * PCI_CONFIG_ADDRESS - PCI Config Address Register + */ + #define PCI_CONFIG_ADDRESS_EN 0x80000000 + #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +diff -ruN u-boot-2021.10/include/mpc85xx.h u-boot/include/mpc85xx.h +--- u-boot-2021.10/include/mpc85xx.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mpc85xx.h 2021-11-01 17:10:14.659570792 +0100 +@@ -42,7 +42,7 @@ + #endif + + #ifndef CONFIG_SYS_CCSRBAR +-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT ++#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT + #endif + + #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +@@ -54,14 +54,14 @@ + #endif + + #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT ++#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + #endif + + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + + #ifndef CONFIG_SYS_IMMR +-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR ++#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + #endif + + #endif /* __MPC85xx_H__ */ +diff -ruN u-boot-2021.10/include/mtd/mtd-abi.h u-boot/include/mtd/mtd-abi.h +--- u-boot-2021.10/include/mtd/mtd-abi.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mtd/mtd-abi.h 2021-11-01 17:10:14.662903943 +0100 +@@ -106,7 +106,7 @@ + #define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode) + #define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme + #define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read) +-#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default ++#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default + + /* OTP mode selection */ + #define MTD_OTP_OFF 0 +diff -ruN u-boot-2021.10/include/mvmfp.h u-boot/include/mvmfp.h +--- u-boot-2021.10/include/mvmfp.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mvmfp.h 2021-11-01 17:10:14.662903943 +0100 +@@ -45,7 +45,7 @@ + /* + * to facilitate the definition, the following macros are provided + * +- * offset, pull,pF, drv,dF, edge,eF ,afn,aF ++ * offset, pull,pF, drv,dF, edge,eF ,afn,aF + */ + #define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) + #define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) +diff -ruN u-boot-2021.10/include/mxs_nand.h u-boot/include/mxs_nand.h +--- u-boot-2021.10/include/mxs_nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/mxs_nand.h 2021-11-01 17:10:14.662903943 +0100 +@@ -8,6 +8,7 @@ + */ + + #include <linux/mtd/mtd.h> ++#include <linux/mtd/rawnand.h> + #include <asm/cache.h> + #include <nand.h> + #include <asm/mach-imx/dma.h> +diff -ruN u-boot-2021.10/include/nand.h u-boot/include/nand.h +--- u-boot-2021.10/include/nand.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/nand.h 2021-11-01 17:10:14.662903943 +0100 +@@ -31,7 +31,6 @@ + + #include <linux/compat.h> + #include <linux/mtd/mtd.h> +-#include <linux/mtd/rawnand.h> + + int nand_mtd_to_devnum(struct mtd_info *mtd); + +@@ -39,6 +38,8 @@ + void board_nand_init(void); + int nand_register(int devnum, struct mtd_info *mtd); + #else ++struct nand_chip; ++ + extern int board_nand_init(struct nand_chip *nand); + #endif + +diff -ruN u-boot-2021.10/include/net/dsa.h u-boot/include/net/dsa.h +--- u-boot-2021.10/include/net/dsa.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/net/dsa.h 2021-11-01 17:10:14.662903943 +0100 +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* +- * Copyright 2019-2021 NXP Semiconductors ++ * Copyright 2019-2021 NXP + */ + + #ifndef __DSA_H__ +@@ -57,7 +57,8 @@ + /** + * struct dsa_ops - DSA operations + * +- * @port_enable: Initialize a switch port for I/O. ++ * @port_probe: Initialize a switch port. ++ * @port_enable: Enable I/O for a port. + * @port_disable: Disable I/O for a port. + * @xmit: Insert the DSA tag for transmission. + * DSA drivers receive a copy of the packet with headroom and +@@ -69,6 +70,8 @@ + * master including any additional headers. + */ + struct dsa_ops { ++ int (*port_probe)(struct udevice *dev, int port, ++ struct phy_device *phy); + int (*port_enable)(struct udevice *dev, int port, + struct phy_device *phy); + void (*port_disable)(struct udevice *dev, int port, +diff -ruN u-boot-2021.10/include/netdev.h u-boot/include/netdev.h +--- u-boot-2021.10/include/netdev.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/netdev.h 2021-11-01 17:10:14.662903943 +0100 +@@ -29,7 +29,6 @@ + int cpu_eth_init(struct bd_info *bis); + + /* Driver initialization prototypes */ +-int at91emac_register(struct bd_info *bis, unsigned long iobase); + int ax88180_initialize(struct bd_info *bis); + int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num); + int bfin_EMAC_initialize(struct bd_info *bis); +diff -ruN u-boot-2021.10/include/os.h u-boot/include/os.h +--- u-boot-2021.10/include/os.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/os.h 2021-11-01 17:10:14.662903943 +0100 +@@ -52,6 +52,14 @@ + #define OS_SEEK_END 2 + + /** ++ * os_filesize() - Calculate the size of a file ++ * ++ * @fd: File descriptor as returned by os_open() ++ * Return: file size or negative error code ++ */ ++int os_filesize(int fd); ++ ++/** + * Access to the OS open() system call + * + * @pathname: Pathname of file to open +@@ -398,6 +406,19 @@ + */ + int os_read_file(const char *name, void **bufp, int *sizep); + ++/** ++ * os_map_file() - Map a file from the host filesystem into memory ++ * ++ * This can be useful when to provide a backing store for an emulated device ++ * ++ * @pathname: File pathname to map ++ * @os_flags: Flags, like OS_O_RDONLY, OS_O_RDWR ++ * @bufp: Returns buffer containing the file ++ * @sizep: Returns size of data ++ * Return: 0 if OK, -ve on error ++ */ ++int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep); ++ + /* + * os_find_text_base() - Find the text section in this running process + * +diff -ruN u-boot-2021.10/include/part.h u-boot/include/part.h +--- u-boot-2021.10/include/part.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/part.h 2021-11-01 17:10:14.662903943 +0100 +@@ -75,7 +75,7 @@ + char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */ + #endif + #ifdef CONFIG_DOS_PARTITION +- uchar sys_ind; /* partition type */ ++ uchar sys_ind; /* partition type */ + #endif + }; + +diff -ruN u-boot-2021.10/include/pci.h u-boot/include/pci.h +--- u-boot-2021.10/include/pci.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/pci.h 2021-11-01 17:10:14.666237093 +0100 +@@ -724,6 +724,7 @@ + */ + int pciauto_region_allocate(struct pci_region *res, pci_size_t size, + pci_addr_t *bar, bool supports_64bit); ++int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); + + #if defined(CONFIG_DM_PCI_COMPAT) + extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, +@@ -741,7 +742,6 @@ + extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); + extern struct pci_controller *pci_get_hose_head(void); + +-extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); + extern int pci_hose_scan(struct pci_controller *hose); + extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); + +diff -ruN u-boot-2021.10/include/phy.h u-boot/include/phy.h +--- u-boot-2021.10/include/phy.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/phy.h 2021-11-01 17:10:14.666237093 +0100 +@@ -368,7 +368,7 @@ + { + return interface == PHY_INTERFACE_MODE_XGMII || + interface == PHY_INTERFACE_MODE_USXGMII || +- interface == PHY_INTERFACE_MODE_XFI; ++ interface == PHY_INTERFACE_MODE_10GBASER; + } + + #endif +@@ -575,8 +575,8 @@ + } + + /* PHY UIDs for various PHYs that are referenced in external code */ +-#define PHY_UID_CS4340 0x13e51002 +-#define PHY_UID_CS4223 0x03e57003 ++#define PHY_UID_CS4340 0x13e51002 ++#define PHY_UID_CS4223 0x03e57003 + #define PHY_UID_TN2020 0x00a19410 + #define PHY_UID_IN112525_S03 0x02107440 + +diff -ruN u-boot-2021.10/include/phy_interface.h u-boot/include/phy_interface.h +--- u-boot-2021.10/include/phy_interface.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/phy_interface.h 2021-11-01 17:10:14.666237093 +0100 +@@ -37,7 +37,7 @@ + PHY_INTERFACE_MODE_CAUI2, + PHY_INTERFACE_MODE_CAUI4, + PHY_INTERFACE_MODE_NCSI, +- PHY_INTERFACE_MODE_XFI, ++ PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_USXGMII, + PHY_INTERFACE_MODE_NONE, /* Must be last */ + +@@ -69,7 +69,7 @@ + [PHY_INTERFACE_MODE_CAUI2] = "caui2", + [PHY_INTERFACE_MODE_CAUI4] = "caui4", + [PHY_INTERFACE_MODE_NCSI] = "NC-SI", +- [PHY_INTERFACE_MODE_XFI] = "xfi", ++ [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", + [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", + [PHY_INTERFACE_MODE_NONE] = "", + }; +diff -ruN u-boot-2021.10/include/power/max77686_pmic.h u-boot/include/power/max77686_pmic.h +--- u-boot-2021.10/include/power/max77686_pmic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/power/max77686_pmic.h 2021-11-01 17:10:14.666237093 +0100 +@@ -154,7 +154,7 @@ + OPMODE_ON, + }; + +-#ifdef CONFIG_POWER ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); + int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); + int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); +diff -ruN u-boot-2021.10/include/power/pmic.h u-boot/include/power/pmic.h +--- u-boot-2021.10/include/power/pmic.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/power/pmic.h 2021-11-01 17:10:14.669570245 +0100 +@@ -17,7 +17,8 @@ + + enum { PMIC_I2C, PMIC_SPI, PMIC_NONE}; + +-#ifdef CONFIG_POWER ++/* TODO: Change to !CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ ++#if CONFIG_IS_ENABLED(POWER_LEGACY) + enum { I2C_PMIC, I2C_NUM, }; + enum { PMIC_READ, PMIC_WRITE, }; + enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; +@@ -82,8 +83,9 @@ + struct pmic *parent; + struct list_head list; + }; +-#endif /* CONFIG_POWER */ ++#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ + ++/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ + #ifdef CONFIG_DM_PMIC + /** + * U-Boot PMIC Framework +@@ -306,9 +308,12 @@ + uint trans_len; + }; + +-#endif /* CONFIG_DM_PMIC */ ++#endif /* DM_PMIC */ + +-#ifdef CONFIG_POWER ++/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ ++#if CONFIG_IS_ENABLED(POWER_LEGACY) ++ ++/* Legacy API, do not use */ + int pmic_init(unsigned char bus); + int power_init_board(void); + int pmic_dialog_init(unsigned char bus); +@@ -319,7 +324,7 @@ + int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); + int pmic_reg_write(struct pmic *p, u32 reg, u32 val); + int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); +-#endif ++#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ + + #define pmic_i2c_addr (p->hw.i2c.addr) + #define pmic_i2c_tx_num (p->hw.i2c.tx_num) +diff -ruN u-boot-2021.10/include/power-domain.h u-boot/include/power-domain.h +--- u-boot-2021.10/include/power-domain.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/power-domain.h 2021-11-01 17:10:14.666237093 +0100 +@@ -162,8 +162,7 @@ + * + * @return 0 if OK, or a negative error code. + */ +-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ +- CONFIG_IS_ENABLED(POWER_DOMAIN) ++#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN) + int dev_power_domain_on(struct udevice *dev); + #else + static inline int dev_power_domain_on(struct udevice *dev) +@@ -179,8 +178,7 @@ + * + * @return 0 if OK, or a negative error code. + */ +-#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ +- CONFIG_IS_ENABLED(POWER_DOMAIN) ++#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(POWER_DOMAIN) + int dev_power_domain_off(struct udevice *dev); + #else + static inline int dev_power_domain_off(struct udevice *dev) +diff -ruN u-boot-2021.10/include/radeon.h u-boot/include/radeon.h +--- u-boot-2021.10/include/radeon.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/radeon.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,1988 +0,0 @@ +-#ifndef _RADEON_H +-#define _RADEON_H +- +- +-#define RADEON_REGSIZE 0x4000 +- +- +-#define MM_INDEX 0x0000 +-#define MM_DATA 0x0004 +-#define BUS_CNTL 0x0030 +-#define HI_STAT 0x004C +-#define BUS_CNTL1 0x0034 +-#define I2C_CNTL_1 0x0094 +-#define CONFIG_CNTL 0x00E0 +-#define CONFIG_MEMSIZE 0x00F8 +-#define CONFIG_APER_0_BASE 0x0100 +-#define CONFIG_APER_1_BASE 0x0104 +-#define CONFIG_APER_SIZE 0x0108 +-#define CONFIG_REG_1_BASE 0x010C +-#define CONFIG_REG_APER_SIZE 0x0110 +-#define PAD_AGPINPUT_DELAY 0x0164 +-#define PAD_CTLR_STRENGTH 0x0168 +-#define PAD_CTLR_UPDATE 0x016C +-#define PAD_CTLR_MISC 0x0aa0 +-#define AGP_CNTL 0x0174 +-#define BM_STATUS 0x0160 +-#define CAP0_TRIG_CNTL 0x0950 +-#define CAP1_TRIG_CNTL 0x09c0 +-#define VIPH_CONTROL 0x0C40 +-#define VENDOR_ID 0x0F00 +-#define DEVICE_ID 0x0F02 +-#define COMMAND 0x0F04 +-#define STATUS 0x0F06 +-#define REVISION_ID 0x0F08 +-#define REGPROG_INF 0x0F09 +-#define SUB_CLASS 0x0F0A +-#define BASE_CODE 0x0F0B +-#define CACHE_LINE 0x0F0C +-#define LATENCY 0x0F0D +-#define HEADER 0x0F0E +-#define BIST 0x0F0F +-#define REG_MEM_BASE 0x0F10 +-#define REG_IO_BASE 0x0F14 +-#define REG_REG_BASE 0x0F18 +-#define ADAPTER_ID 0x0F2C +-#define BIOS_ROM 0x0F30 +-#define CAPABILITIES_PTR 0x0F34 +-#define INTERRUPT_LINE 0x0F3C +-#define INTERRUPT_PIN 0x0F3D +-#define MIN_GRANT 0x0F3E +-#define MAX_LATENCY 0x0F3F +-#define ADAPTER_ID_W 0x0F4C +-#define PMI_CAP_ID 0x0F50 +-#define PMI_NXT_CAP_PTR 0x0F51 +-#define PMI_PMC_REG 0x0F52 +-#define PM_STATUS 0x0F54 +-#define PMI_DATA 0x0F57 +-#define AGP_CAP_ID 0x0F58 +-#define AGP_STATUS 0x0F5C +-#define AGP_COMMAND 0x0F60 +-#define AIC_CTRL 0x01D0 +-#define AIC_STAT 0x01D4 +-#define AIC_PT_BASE 0x01D8 +-#define AIC_LO_ADDR 0x01DC +-#define AIC_HI_ADDR 0x01E0 +-#define AIC_TLB_ADDR 0x01E4 +-#define AIC_TLB_DATA 0x01E8 +-#define DAC_CNTL 0x0058 +-#define DAC_CNTL2 0x007c +-#define CRTC_GEN_CNTL 0x0050 +-#define MEM_CNTL 0x0140 +-#define MC_CNTL 0x0140 +-#define EXT_MEM_CNTL 0x0144 +-#define MC_TIMING_CNTL 0x0144 +-#define MC_AGP_LOCATION 0x014C +-#define MEM_IO_CNTL_A0 0x0178 +-#define MEM_REFRESH_CNTL 0x0178 +-#define MEM_INIT_LATENCY_TIMER 0x0154 +-#define MC_INIT_GFX_LAT_TIMER 0x0154 +-#define MEM_SDRAM_MODE_REG 0x0158 +-#define AGP_BASE 0x0170 +-#define MEM_IO_CNTL_A1 0x017C +-#define MC_READ_CNTL_AB 0x017C +-#define MEM_IO_CNTL_B0 0x0180 +-#define MC_INIT_MISC_LAT_TIMER 0x0180 +-#define MEM_IO_CNTL_B1 0x0184 +-#define MC_IOPAD_CNTL 0x0184 +-#define MC_DEBUG 0x0188 +-#define MC_STATUS 0x0150 +-#define MEM_IO_OE_CNTL 0x018C +-#define MC_CHIP_IO_OE_CNTL_AB 0x018C +-#define MC_FB_LOCATION 0x0148 +-/* #define MC_FB_LOCATION 0x0188 */ +-#define HOST_PATH_CNTL 0x0130 +-#define MEM_VGA_WP_SEL 0x0038 +-#define MEM_VGA_RP_SEL 0x003C +-#define HDP_DEBUG 0x0138 +-#define SW_SEMAPHORE 0x013C +-#define CRTC2_GEN_CNTL 0x03f8 +-#define CRTC2_DISPLAY_BASE_ADDR 0x033c +-#define SURFACE_CNTL 0x0B00 +-#define SURFACE0_LOWER_BOUND 0x0B04 +-#define SURFACE1_LOWER_BOUND 0x0B14 +-#define SURFACE2_LOWER_BOUND 0x0B24 +-#define SURFACE3_LOWER_BOUND 0x0B34 +-#define SURFACE4_LOWER_BOUND 0x0B44 +-#define SURFACE5_LOWER_BOUND 0x0B54 +-#define SURFACE6_LOWER_BOUND 0x0B64 +-#define SURFACE7_LOWER_BOUND 0x0B74 +-#define SURFACE0_UPPER_BOUND 0x0B08 +-#define SURFACE1_UPPER_BOUND 0x0B18 +-#define SURFACE2_UPPER_BOUND 0x0B28 +-#define SURFACE3_UPPER_BOUND 0x0B38 +-#define SURFACE4_UPPER_BOUND 0x0B48 +-#define SURFACE5_UPPER_BOUND 0x0B58 +-#define SURFACE6_UPPER_BOUND 0x0B68 +-#define SURFACE7_UPPER_BOUND 0x0B78 +-#define SURFACE0_INFO 0x0B0C +-#define SURFACE1_INFO 0x0B1C +-#define SURFACE2_INFO 0x0B2C +-#define SURFACE3_INFO 0x0B3C +-#define SURFACE4_INFO 0x0B4C +-#define SURFACE5_INFO 0x0B5C +-#define SURFACE6_INFO 0x0B6C +-#define SURFACE7_INFO 0x0B7C +-#define SURFACE_ACCESS_FLAGS 0x0BF8 +-#define SURFACE_ACCESS_CLR 0x0BFC +-#define GEN_INT_CNTL 0x0040 +-#define GEN_INT_STATUS 0x0044 +-#define CRTC_EXT_CNTL 0x0054 +-#define RB3D_CNTL 0x1C3C +-#define WAIT_UNTIL 0x1720 +-#define ISYNC_CNTL 0x1724 +-#define RBBM_GUICNTL 0x172C +-#define RBBM_STATUS 0x0E40 +-#define RBBM_STATUS_alt_1 0x1740 +-#define RBBM_CNTL 0x00EC +-#define RBBM_CNTL_alt_1 0x0E44 +-#define RBBM_SOFT_RESET 0x00F0 +-#define RBBM_SOFT_RESET_alt_1 0x0E48 +-#define NQWAIT_UNTIL 0x0E50 +-#define RBBM_DEBUG 0x0E6C +-#define RBBM_CMDFIFO_ADDR 0x0E70 +-#define RBBM_CMDFIFO_DATAL 0x0E74 +-#define RBBM_CMDFIFO_DATAH 0x0E78 +-#define RBBM_CMDFIFO_STAT 0x0E7C +-#define CRTC_STATUS 0x005C +-#define GPIO_VGA_DDC 0x0060 +-#define GPIO_DVI_DDC 0x0064 +-#define GPIO_MONID 0x0068 +-#define GPIO_CRT2_DDC 0x006c +-#define PALETTE_INDEX 0x00B0 +-#define PALETTE_DATA 0x00B4 +-#define PALETTE_30_DATA 0x00B8 +-#define CRTC_H_TOTAL_DISP 0x0200 +-#define CRTC_H_SYNC_STRT_WID 0x0204 +-#define CRTC_H_SYNC_POL (1 << 23) +-#define CRTC_V_TOTAL_DISP 0x0208 +-#define CRTC_V_SYNC_STRT_WID 0x020C +-#define CRTC_V_SYNC_POL (1 << 23) +-#define CRTC_VLINE_CRNT_VLINE 0x0210 +-#define CRTC_CRNT_FRAME 0x0214 +-#define CRTC_GUI_TRIG_VLINE 0x0218 +-#define CRTC_DEBUG 0x021C +-#define CRTC_OFFSET_RIGHT 0x0220 +-#define CRTC_OFFSET 0x0224 +-#define CRTC_OFFSET_CNTL 0x0228 +-#define CRTC_PITCH 0x022C +-#define OVR_CLR 0x0230 +-#define OVR_WID_LEFT_RIGHT 0x0234 +-#define OVR_WID_TOP_BOTTOM 0x0238 +-#define DISPLAY_BASE_ADDR 0x023C +-#define SNAPSHOT_VH_COUNTS 0x0240 +-#define SNAPSHOT_F_COUNT 0x0244 +-#define N_VIF_COUNT 0x0248 +-#define SNAPSHOT_VIF_COUNT 0x024C +-#define FP_CRTC_H_TOTAL_DISP 0x0250 +-#define FP_CRTC_V_TOTAL_DISP 0x0254 +-#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +-#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +-#define CUR_OFFSET 0x0260 +-#define CUR_HORZ_VERT_POSN 0x0264 +-#define CUR_HORZ_VERT_OFF 0x0268 +-#define CUR_CLR0 0x026C +-#define CUR_CLR1 0x0270 +-#define FP_HORZ_VERT_ACTIVE 0x0278 +-#define CRTC_MORE_CNTL 0x027C +-#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +-#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +-#define DAC_EXT_CNTL 0x0280 +-#define FP_GEN_CNTL 0x0284 +-#define FP_HORZ_STRETCH 0x028C +-#define FP_VERT_STRETCH 0x0290 +-#define FP_H_SYNC_STRT_WID 0x02C4 +-#define FP_V_SYNC_STRT_WID 0x02C8 +-#define AUX_WINDOW_HORZ_CNTL 0x02D8 +-#define AUX_WINDOW_VERT_CNTL 0x02DC +-/* #define DDA_CONFIG 0x02e0 */ +-/* #define DDA_ON_OFF 0x02e4 */ +-#define DVI_I2C_CNTL_1 0x02e4 +-#define GRPH_BUFFER_CNTL 0x02F0 +-#define GRPH2_BUFFER_CNTL 0x03F0 +-#define VGA_BUFFER_CNTL 0x02F4 +-#define OV0_Y_X_START 0x0400 +-#define OV0_Y_X_END 0x0404 +-#define OV0_PIPELINE_CNTL 0x0408 +-#define OV0_REG_LOAD_CNTL 0x0410 +-#define OV0_SCALE_CNTL 0x0420 +-#define OV0_V_INC 0x0424 +-#define OV0_P1_V_ACCUM_INIT 0x0428 +-#define OV0_P23_V_ACCUM_INIT 0x042C +-#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +-#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +-#define OV0_BASE_ADDR 0x043C +-#define OV0_VID_BUF0_BASE_ADRS 0x0440 +-#define OV0_VID_BUF1_BASE_ADRS 0x0444 +-#define OV0_VID_BUF2_BASE_ADRS 0x0448 +-#define OV0_VID_BUF3_BASE_ADRS 0x044C +-#define OV0_VID_BUF4_BASE_ADRS 0x0450 +-#define OV0_VID_BUF5_BASE_ADRS 0x0454 +-#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +-#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +-#define OV0_AUTO_FLIP_CNTRL 0x0470 +-#define OV0_DEINTERLACE_PATTERN 0x0474 +-#define OV0_SUBMIT_HISTORY 0x0478 +-#define OV0_H_INC 0x0480 +-#define OV0_STEP_BY 0x0484 +-#define OV0_P1_H_ACCUM_INIT 0x0488 +-#define OV0_P23_H_ACCUM_INIT 0x048C +-#define OV0_P1_X_START_END 0x0494 +-#define OV0_P2_X_START_END 0x0498 +-#define OV0_P3_X_START_END 0x049C +-#define OV0_FILTER_CNTL 0x04A0 +-#define OV0_FOUR_TAP_COEF_0 0x04B0 +-#define OV0_FOUR_TAP_COEF_1 0x04B4 +-#define OV0_FOUR_TAP_COEF_2 0x04B8 +-#define OV0_FOUR_TAP_COEF_3 0x04BC +-#define OV0_FOUR_TAP_COEF_4 0x04C0 +-#define OV0_FLAG_CNTRL 0x04DC +-#define OV0_SLICE_CNTL 0x04E0 +-#define OV0_VID_KEY_CLR_LOW 0x04E4 +-#define OV0_VID_KEY_CLR_HIGH 0x04E8 +-#define OV0_GRPH_KEY_CLR_LOW 0x04EC +-#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +-#define OV0_KEY_CNTL 0x04F4 +-#define OV0_TEST 0x04F8 +-#define SUBPIC_CNTL 0x0540 +-#define SUBPIC_DEFCOLCON 0x0544 +-#define SUBPIC_Y_X_START 0x054C +-#define SUBPIC_Y_X_END 0x0550 +-#define SUBPIC_V_INC 0x0554 +-#define SUBPIC_H_INC 0x0558 +-#define SUBPIC_BUF0_OFFSET 0x055C +-#define SUBPIC_BUF1_OFFSET 0x0560 +-#define SUBPIC_LC0_OFFSET 0x0564 +-#define SUBPIC_LC1_OFFSET 0x0568 +-#define SUBPIC_PITCH 0x056C +-#define SUBPIC_BTN_HLI_COLCON 0x0570 +-#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +-#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +-#define SUBPIC_PALETTE_INDEX 0x057C +-#define SUBPIC_PALETTE_DATA 0x0580 +-#define SUBPIC_H_ACCUM_INIT 0x0584 +-#define SUBPIC_V_ACCUM_INIT 0x0588 +-#define DISP_MISC_CNTL 0x0D00 +-#define DAC_MACRO_CNTL 0x0D04 +-#define DISP_PWR_MAN 0x0D08 +-#define DISP_TEST_DEBUG_CNTL 0x0D10 +-#define DISP_HW_DEBUG 0x0D14 +-#define DAC_CRC_SIG1 0x0D18 +-#define DAC_CRC_SIG2 0x0D1C +-#define OV0_LIN_TRANS_A 0x0D20 +-#define OV0_LIN_TRANS_B 0x0D24 +-#define OV0_LIN_TRANS_C 0x0D28 +-#define OV0_LIN_TRANS_D 0x0D2C +-#define OV0_LIN_TRANS_E 0x0D30 +-#define OV0_LIN_TRANS_F 0x0D34 +-#define OV0_GAMMA_0_F 0x0D40 +-#define OV0_GAMMA_10_1F 0x0D44 +-#define OV0_GAMMA_20_3F 0x0D48 +-#define OV0_GAMMA_40_7F 0x0D4C +-#define OV0_GAMMA_380_3BF 0x0D50 +-#define OV0_GAMMA_3C0_3FF 0x0D54 +-#define DISP_MERGE_CNTL 0x0D60 +-#define DISP_OUTPUT_CNTL 0x0D64 +-#define DISP_LIN_TRANS_GRPH_A 0x0D80 +-#define DISP_LIN_TRANS_GRPH_B 0x0D84 +-#define DISP_LIN_TRANS_GRPH_C 0x0D88 +-#define DISP_LIN_TRANS_GRPH_D 0x0D8C +-#define DISP_LIN_TRANS_GRPH_E 0x0D90 +-#define DISP_LIN_TRANS_GRPH_F 0x0D94 +-#define DISP_LIN_TRANS_VID_A 0x0D98 +-#define DISP_LIN_TRANS_VID_B 0x0D9C +-#define DISP_LIN_TRANS_VID_C 0x0DA0 +-#define DISP_LIN_TRANS_VID_D 0x0DA4 +-#define DISP_LIN_TRANS_VID_E 0x0DA8 +-#define DISP_LIN_TRANS_VID_F 0x0DAC +-#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +-#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +-#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +-#define RMX_HORZ_PHASE 0x0DBC +-#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +-#define DAC_BROAD_PULSE 0x0DC4 +-#define DAC_SKEW_CLKS 0x0DC8 +-#define DAC_INCR 0x0DCC +-#define DAC_NEG_SYNC_LEVEL 0x0DD0 +-#define DAC_POS_SYNC_LEVEL 0x0DD4 +-#define DAC_BLANK_LEVEL 0x0DD8 +-#define CLOCK_CNTL_INDEX 0x0008 +-#define CLOCK_CNTL_DATA 0x000C +-#define CP_RB_CNTL 0x0704 +-#define CP_RB_BASE 0x0700 +-#define CP_RB_RPTR_ADDR 0x070C +-#define CP_RB_RPTR 0x0710 +-#define CP_RB_WPTR 0x0714 +-#define CP_RB_WPTR_DELAY 0x0718 +-#define CP_IB_BASE 0x0738 +-#define CP_IB_BUFSZ 0x073C +-#define SCRATCH_REG0 0x15E0 +-#define GUI_SCRATCH_REG0 0x15E0 +-#define SCRATCH_REG1 0x15E4 +-#define GUI_SCRATCH_REG1 0x15E4 +-#define SCRATCH_REG2 0x15E8 +-#define GUI_SCRATCH_REG2 0x15E8 +-#define SCRATCH_REG3 0x15EC +-#define GUI_SCRATCH_REG3 0x15EC +-#define SCRATCH_REG4 0x15F0 +-#define GUI_SCRATCH_REG4 0x15F0 +-#define SCRATCH_REG5 0x15F4 +-#define GUI_SCRATCH_REG5 0x15F4 +-#define SCRATCH_UMSK 0x0770 +-#define SCRATCH_ADDR 0x0774 +-#define DP_BRUSH_FRGD_CLR 0x147C +-#define DP_BRUSH_BKGD_CLR 0x1478 +-#define DST_LINE_START 0x1600 +-#define DST_LINE_END 0x1604 +-#define SRC_OFFSET 0x15AC +-#define SRC_PITCH 0x15B0 +-#define SRC_TILE 0x1704 +-#define SRC_PITCH_OFFSET 0x1428 +-#define SRC_X 0x1414 +-#define SRC_Y 0x1418 +-#define SRC_X_Y 0x1590 +-#define SRC_Y_X 0x1434 +-#define DST_Y_X 0x1438 +-#define DST_WIDTH_HEIGHT 0x1598 +-#define DST_HEIGHT_WIDTH 0x143c +-#define DST_OFFSET 0x1404 +-#define SRC_CLUT_ADDRESS 0x1780 +-#define SRC_CLUT_DATA 0x1784 +-#define SRC_CLUT_DATA_RD 0x1788 +-#define HOST_DATA0 0x17C0 +-#define HOST_DATA1 0x17C4 +-#define HOST_DATA2 0x17C8 +-#define HOST_DATA3 0x17CC +-#define HOST_DATA4 0x17D0 +-#define HOST_DATA5 0x17D4 +-#define HOST_DATA6 0x17D8 +-#define HOST_DATA7 0x17DC +-#define HOST_DATA_LAST 0x17E0 +-#define DP_SRC_ENDIAN 0x15D4 +-#define DP_SRC_FRGD_CLR 0x15D8 +-#define DP_SRC_BKGD_CLR 0x15DC +-#define SC_LEFT 0x1640 +-#define SC_RIGHT 0x1644 +-#define SC_TOP 0x1648 +-#define SC_BOTTOM 0x164C +-#define SRC_SC_RIGHT 0x1654 +-#define SRC_SC_BOTTOM 0x165C +-#define DP_CNTL 0x16C0 +-#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +-#define DP_DATATYPE 0x16C4 +-#define DP_MIX 0x16C8 +-#define DP_WRITE_MSK 0x16CC +-#define DP_XOP 0x17F8 +-#define CLR_CMP_CLR_SRC 0x15C4 +-#define CLR_CMP_CLR_DST 0x15C8 +-#define CLR_CMP_CNTL 0x15C0 +-#define CLR_CMP_MSK 0x15CC +-#define DSTCACHE_MODE 0x1710 +-#define DSTCACHE_CTLSTAT 0x1714 +-#define DEFAULT_PITCH_OFFSET 0x16E0 +-#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +-#define DEFAULT_SC_TOP_LEFT 0x16EC +-#define SRC_PITCH_OFFSET 0x1428 +-#define DST_PITCH_OFFSET 0x142C +-#define DP_GUI_MASTER_CNTL 0x146C +-#define SC_TOP_LEFT 0x16EC +-#define SC_BOTTOM_RIGHT 0x16F0 +-#define SRC_SC_BOTTOM_RIGHT 0x16F4 +-#define RB2D_DSTCACHE_MODE 0x3428 +-#define RB2D_DSTCACHE_CTLSTAT 0x342C +-#define LVDS_GEN_CNTL 0x02d0 +-#define LVDS_PLL_CNTL 0x02d4 +-#define FP2_GEN_CNTL 0x0288 +-#define TMDS_CNTL 0x0294 +-#define TMDS_CRC 0x02a0 +-#define TMDS_TRANSMITTER_CNTL 0x02a4 +-#define MPP_TB_CONFIG 0x01c0 +-#define PAMAC0_DLY_CNTL 0x0a94 +-#define PAMAC1_DLY_CNTL 0x0a98 +-#define PAMAC2_DLY_CNTL 0x0a9c +-#define FW_CNTL 0x0118 +-#define FCP_CNTL 0x0910 +-#define VGA_DDA_ON_OFF 0x02ec +-#define TV_MASTER_CNTL 0x0800 +- +-/* #define BASE_CODE 0x0f0b */ +-#define BIOS_0_SCRATCH 0x0010 +-#define BIOS_1_SCRATCH 0x0014 +-#define BIOS_2_SCRATCH 0x0018 +-#define BIOS_3_SCRATCH 0x001c +-#define BIOS_4_SCRATCH 0x0020 +-#define BIOS_5_SCRATCH 0x0024 +-#define BIOS_6_SCRATCH 0x0028 +-#define BIOS_7_SCRATCH 0x002c +- +-#define HDP_SOFT_RESET (1 << 26) +- +-#define TV_DAC_CNTL 0x088c +-#define GPIOPAD_MASK 0x0198 +-#define GPIOPAD_A 0x019c +-#define GPIOPAD_EN 0x01a0 +-#define GPIOPAD_Y 0x01a4 +-#define ZV_LCDPAD_MASK 0x01a8 +-#define ZV_LCDPAD_A 0x01ac +-#define ZV_LCDPAD_EN 0x01b0 +-#define ZV_LCDPAD_Y 0x01b4 +- +-/* PLL Registers */ +-#define CLK_PIN_CNTL 0x0001 +-#define PPLL_CNTL 0x0002 +-#define PPLL_REF_DIV 0x0003 +-#define PPLL_DIV_0 0x0004 +-#define PPLL_DIV_1 0x0005 +-#define PPLL_DIV_2 0x0006 +-#define PPLL_DIV_3 0x0007 +-#define VCLK_ECP_CNTL 0x0008 +-#define HTOTAL_CNTL 0x0009 +-#define M_SPLL_REF_FB_DIV 0x000a +-#define AGP_PLL_CNTL 0x000b +-#define SPLL_CNTL 0x000c +-#define SCLK_CNTL 0x000d +-#define MPLL_CNTL 0x000e +-#define MDLL_CKO 0x000f +-#define MDLL_RDCKA 0x0010 +-#define MCLK_CNTL 0x0012 +-#define AGP_PLL_CNTL 0x000b +-#define PLL_TEST_CNTL 0x0013 +-#define CLK_PWRMGT_CNTL 0x0014 +-#define PLL_PWRMGT_CNTL 0x0015 +-#define MCLK_MISC 0x001f +-#define P2PLL_CNTL 0x002a +-#define P2PLL_REF_DIV 0x002b +-#define PIXCLKS_CNTL 0x002d +-#define SCLK_MORE_CNTL 0x0035 +- +-/* MCLK_CNTL bit constants */ +-#define FORCEON_MCLKA (1 << 16) +-#define FORCEON_MCLKB (1 << 17) +-#define FORCEON_YCLKA (1 << 18) +-#define FORCEON_YCLKB (1 << 19) +-#define FORCEON_MC (1 << 20) +-#define FORCEON_AIC (1 << 21) +- +-/* SCLK_CNTL bit constants */ +-#define DYN_STOP_LAT_MASK 0x00007ff8 +-#define CP_MAX_DYN_STOP_LAT 0x0008 +-#define SCLK_FORCEON_MASK 0xffff8000 +- +-/* SCLK_MORE_CNTL bit constants */ +-#define SCLK_MORE_FORCEON 0x0700 +- +-/* BUS_CNTL bit constants */ +-#define BUS_DBL_RESYNC 0x00000001 +-#define BUS_MSTR_RESET 0x00000002 +-#define BUS_FLUSH_BUF 0x00000004 +-#define BUS_STOP_REQ_DIS 0x00000008 +-#define BUS_ROTATION_DIS 0x00000010 +-#define BUS_MASTER_DIS 0x00000040 +-#define BUS_ROM_WRT_EN 0x00000080 +-#define BUS_DIS_ROM 0x00001000 +-#define BUS_PCI_READ_RETRY_EN 0x00002000 +-#define BUS_AGP_AD_STEPPING_EN 0x00004000 +-#define BUS_PCI_WRT_RETRY_EN 0x00008000 +-#define BUS_MSTR_RD_MULT 0x00100000 +-#define BUS_MSTR_RD_LINE 0x00200000 +-#define BUS_SUSPEND 0x00400000 +-#define LAT_16X 0x00800000 +-#define BUS_RD_DISCARD_EN 0x01000000 +-#define BUS_RD_ABORT_EN 0x02000000 +-#define BUS_MSTR_WS 0x04000000 +-#define BUS_PARKING_DIS 0x08000000 +-#define BUS_MSTR_DISCONNECT_EN 0x10000000 +-#define BUS_WRT_BURST 0x20000000 +-#define BUS_READ_BURST 0x40000000 +-#define BUS_RDY_READ_DLY 0x80000000 +- +-/* PIXCLKS_CNTL */ +-#define PIX2CLK_SRC_SEL_MASK 0x03 +-#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +-#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +-#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +-#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +-#define PIX2CLK_ALWAYS_ONb (1<<6) +-#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +-#define PIXCLK_TV_SRC_SEL (1 << 8) +-#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +-#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +- +- +-/* CLOCK_CNTL_INDEX bit constants */ +-#define PLL_WR_EN 0x00000080 +- +-/* CONFIG_CNTL bit constants */ +-#define CONFIG_SYS_VGA_RAM_EN 0x00000100 +-#define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16) +-#define CONFIG_SYS_ATI_REV_A11 (0 << 16) +-#define CONFIG_SYS_ATI_REV_A12 (1 << 16) +-#define CONFIG_SYS_ATI_REV_A13 (2 << 16) +- +-/* CRTC_EXT_CNTL bit constants */ +-#define VGA_ATI_LINEAR 0x00000008 +-#define VGA_128KAP_PAGING 0x00000010 +-#define XCRT_CNT_EN (1 << 6) +-#define CRTC_HSYNC_DIS (1 << 8) +-#define CRTC_VSYNC_DIS (1 << 9) +-#define CRTC_DISPLAY_DIS (1 << 10) +-#define CRTC_CRT_ON (1 << 15) +- +- +-/* DSTCACHE_CTLSTAT bit constants */ +-#define RB2D_DC_FLUSH (3 << 0) +-#define RB2D_DC_FLUSH_ALL 0xf +-#define RB2D_DC_BUSY (1 << 31) +- +- +-/* CRTC_GEN_CNTL bit constants */ +-#define CRTC_DBL_SCAN_EN 0x00000001 +-#define CRTC_CUR_EN 0x00010000 +-#define CRTC_INTERLACE_EN (1 << 1) +-#define CRTC_BYPASS_LUT_EN (1 << 14) +-#define CRTC_EXT_DISP_EN (1 << 24) +-#define CRTC_EN (1 << 25) +-#define CRTC_DISP_REQ_EN_B (1 << 26) +- +-/* CRTC_STATUS bit constants */ +-#define CRTC_VBLANK 0x00000001 +- +-/* CRTC2_GEN_CNTL bit constants */ +-#define CRT2_ON (1 << 7) +-#define CRTC2_DISPLAY_DIS (1 << 23) +-#define CRTC2_EN (1 << 25) +-#define CRTC2_DISP_REQ_EN_B (1 << 26) +- +-/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +-#define CUR_LOCK 0x80000000 +- +-/* GPIO bit constants */ +-#define GPIO_A_0 (1 << 0) +-#define GPIO_A_1 (1 << 1) +-#define GPIO_Y_0 (1 << 8) +-#define GPIO_Y_1 (1 << 9) +-#define GPIO_EN_0 (1 << 16) +-#define GPIO_EN_1 (1 << 17) +-#define GPIO_MASK_0 (1 << 24) +-#define GPIO_MASK_1 (1 << 25) +-#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +-#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +-#define VGA_DDC_DATA_INPUT GPIO_Y_0 +-#define VGA_DDC_CLK_INPUT GPIO_Y_1 +-#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +-#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 +- +- +-/* FP bit constants */ +-#define FP_CRTC_H_TOTAL_MASK 000003ff +-#define FP_CRTC_H_DISP_MASK 0x01ff0000 +-#define FP_CRTC_V_TOTAL_MASK 0x00000fff +-#define FP_CRTC_V_DISP_MASK 0x0fff0000 +-#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +-#define FP_H_SYNC_WID_MASK 0x003f0000 +-#define FP_V_SYNC_STRT_MASK 0x00000fff +-#define FP_V_SYNC_WID_MASK 0x001f0000 +-#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +-#define FP_CRTC_H_DISP_SHIFT 0x00000010 +-#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +-#define FP_CRTC_V_DISP_SHIFT 0x00000010 +-#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +-#define FP_H_SYNC_WID_SHIFT 0x00000010 +-#define FP_V_SYNC_STRT_SHIFT 0x00000000 +-#define FP_V_SYNC_WID_SHIFT 0x00000010 +- +-/* FP_GEN_CNTL bit constants */ +-#define FP_FPON (1 << 0) +-#define FP_TMDS_EN (1 << 2) +-#define FP_PANEL_FORMAT (1 << 3) +-#define FP_EN_TMDS (1 << 7) +-#define FP_DETECT_SENSE (1 << 8) +-#define R200_FP_SOURCE_SEL_MASK (3 << 10) +-#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +-#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +-#define R200_FP_SOURCE_SEL_RMX (2 << 10) +-#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +-#define FP_SEL_CRTC1 (0 << 13) +-#define FP_SEL_CRTC2 (1 << 13) +-#define FP_USE_VGA_HSYNC (1 << 14) +-#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +-#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +-#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +-#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +-#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +-#define FP_DFP_SYNC_SEL (1 << 21) +-#define FP_CRTC_LOCK_8DOT (1 << 22) +-#define FP_CRT_SYNC_SEL (1 << 23) +-#define FP_USE_SHADOW_EN (1 << 24) +-#define FP_CRT_SYNC_ALT (1 << 26) +- +-/* FP2_GEN_CNTL bit constants */ +-#define FP2_BLANK_EN (1 << 1) +-#define FP2_ON (1 << 2) +-#define FP2_PANEL_FORMAT (1 << 3) +-#define FP2_SOURCE_SEL_MASK (3 << 10) +-#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +-#define FP2_SRC_SEL_MASK (3 << 13) +-#define FP2_SRC_SEL_CRTC2 (1 << 13) +-#define FP2_FP_POL (1 << 16) +-#define FP2_LP_POL (1 << 17) +-#define FP2_SCK_POL (1 << 18) +-#define FP2_LCD_CNTL_MASK (7 << 19) +-#define FP2_PAD_FLOP_EN (1 << 22) +-#define FP2_CRC_EN (1 << 23) +-#define FP2_CRC_READ_EN (1 << 24) +-#define FP2_DV0_EN (1 << 25) +-#define FP2_DV0_RATE_SEL_SDR (1 << 26) +- +- +-/* LVDS_GEN_CNTL bit constants */ +-#define LVDS_ON (1 << 0) +-#define LVDS_DISPLAY_DIS (1 << 1) +-#define LVDS_PANEL_TYPE (1 << 2) +-#define LVDS_PANEL_FORMAT (1 << 3) +-#define LVDS_EN (1 << 7) +-#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +-#define LVDS_BL_MOD_LEVEL_SHIFT 8 +-#define LVDS_BL_MOD_EN (1 << 16) +-#define LVDS_DIGON (1 << 18) +-#define LVDS_BLON (1 << 19) +-#define LVDS_SEL_CRTC2 (1 << 23) +-#define LVDS_STATE_MASK \ +- (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) +- +-/* LVDS_PLL_CNTL bit constatns */ +-#define HSYNC_DELAY_SHIFT 0x1c +-#define HSYNC_DELAY_MASK (0xf << 0x1c) +- +-/* TMDS_TRANSMITTER_CNTL bit constants */ +-#define TMDS_PLL_EN (1 << 0) +-#define TMDS_PLLRST (1 << 1) +-#define TMDS_RAN_PAT_RST (1 << 7) +-#define TMDS_ICHCSEL (1 << 28) +- +-/* FP_HORZ_STRETCH bit constants */ +-#define HORZ_STRETCH_RATIO_MASK 0xffff +-#define HORZ_STRETCH_RATIO_MAX 4096 +-#define HORZ_PANEL_SIZE (0x1ff << 16) +-#define HORZ_PANEL_SHIFT 16 +-#define HORZ_STRETCH_PIXREP (0 << 25) +-#define HORZ_STRETCH_BLEND (1 << 26) +-#define HORZ_STRETCH_ENABLE (1 << 25) +-#define HORZ_AUTO_RATIO (1 << 27) +-#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +-#define HORZ_AUTO_RATIO_INC (1 << 31) +- +- +-/* FP_VERT_STRETCH bit constants */ +-#define VERT_STRETCH_RATIO_MASK 0xfff +-#define VERT_STRETCH_RATIO_MAX 4096 +-#define VERT_PANEL_SIZE (0xfff << 12) +-#define VERT_PANEL_SHIFT 12 +-#define VERT_STRETCH_LINREP (0 << 26) +-#define VERT_STRETCH_BLEND (1 << 26) +-#define VERT_STRETCH_ENABLE (1 << 25) +-#define VERT_AUTO_RATIO_EN (1 << 27) +-#define VERT_FP_LOOP_STRETCH (0x7 << 28) +-#define VERT_STRETCH_RESERVED 0xf1000000 +- +-/* DAC_CNTL bit constants */ +-#define DAC_8BIT_EN 0x00000100 +-#define DAC_4BPP_PIX_ORDER 0x00000200 +-#define DAC_CRC_EN 0x00080000 +-#define DAC_MASK_ALL (0xff << 24) +-#define DAC_PDWN (1 << 15) +-#define DAC_EXPAND_MODE (1 << 14) +-#define DAC_VGA_ADR_EN (1 << 13) +-#define DAC_RANGE_CNTL (3 << 0) +-#define DAC_RANGE_CNTL_MASK 0x03 +-#define DAC_BLANKING (1 << 2) +-#define DAC_CMP_EN (1 << 3) +-#define DAC_CMP_OUTPUT (1 << 7) +- +-/* DAC_CNTL2 bit constants */ +-#define DAC2_EXPAND_MODE (1 << 14) +-#define DAC2_CMP_EN (1 << 7) +-#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) +- +-/* DAC_EXT_CNTL bit constants */ +-#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +-#define DAC_FORCE_DATA_EN (1 << 5) +-#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +-#define DAC_FORCE_DATA_MASK 0x0003ff00 +-#define DAC_FORCE_DATA_SHIFT 8 +- +-/* GEN_RESET_CNTL bit constants */ +-#define SOFT_RESET_GUI 0x00000001 +-#define SOFT_RESET_VCLK 0x00000100 +-#define SOFT_RESET_PCLK 0x00000200 +-#define SOFT_RESET_ECP 0x00000400 +-#define SOFT_RESET_DISPENG_XCLK 0x00000800 +- +-/* MEM_CNTL bit constants */ +-#define MEM_CTLR_STATUS_IDLE 0x00000000 +-#define MEM_CTLR_STATUS_BUSY 0x00100000 +-#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +-#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +-#define MEM_ARBITER_STATUS_IDLE 0x00000000 +-#define MEM_ARBITER_STATUS_BUSY 0x00400000 +-#define MEM_REQ_UNLOCK 0x00000000 +-#define MEM_REQ_LOCK 0x00800000 +-#define MEM_NUM_CHANNELS_MASK 0x00000001 +-#define MEM_USE_B_CH_ONLY 0x00000002 +-#define RV100_MEM_HALF_MODE 0x00000008 +-#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +-#define R300_MEM_USE_CD_CH_ONLY 0x00000004 +- +- +-/* RBBM_SOFT_RESET bit constants */ +-#define SOFT_RESET_CP (1 << 0) +-#define SOFT_RESET_HI (1 << 1) +-#define SOFT_RESET_SE (1 << 2) +-#define SOFT_RESET_RE (1 << 3) +-#define SOFT_RESET_PP (1 << 4) +-#define SOFT_RESET_E2 (1 << 5) +-#define SOFT_RESET_RB (1 << 6) +-#define SOFT_RESET_HDP (1 << 7) +- +-/* SURFACE_CNTL bit consants */ +-#define SURF_TRANSLATION_DIS (1 << 8) +-#define NONSURF_AP0_SWP_16BPP (1 << 20) +-#define NONSURF_AP0_SWP_32BPP (1 << 21) +-#define NONSURF_AP1_SWP_16BPP (1 << 22) +-#define NONSURF_AP1_SWP_32BPP (1 << 23) +- +-#define R200_SURF_TILE_COLOR_MACRO (1 << 16) +- +-/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +-#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +-#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +- +-/* MM_INDEX bit constants */ +-#define MM_APER 0x80000000 +- +-/* CLR_CMP_CNTL bit constants */ +-#define COMPARE_SRC_FALSE 0x00000000 +-#define COMPARE_SRC_TRUE 0x00000001 +-#define COMPARE_SRC_NOT_EQUAL 0x00000004 +-#define COMPARE_SRC_EQUAL 0x00000005 +-#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +-#define COMPARE_DST_FALSE 0x00000000 +-#define COMPARE_DST_TRUE 0x00000100 +-#define COMPARE_DST_NOT_EQUAL 0x00000400 +-#define COMPARE_DST_EQUAL 0x00000500 +-#define COMPARE_DESTINATION 0x00000000 +-#define COMPARE_SOURCE 0x01000000 +-#define COMPARE_SRC_AND_DST 0x02000000 +- +- +-/* DP_CNTL bit constants */ +-#define DST_X_RIGHT_TO_LEFT 0x00000000 +-#define DST_X_LEFT_TO_RIGHT 0x00000001 +-#define DST_Y_BOTTOM_TO_TOP 0x00000000 +-#define DST_Y_TOP_TO_BOTTOM 0x00000002 +-#define DST_X_MAJOR 0x00000000 +-#define DST_Y_MAJOR 0x00000004 +-#define DST_X_TILE 0x00000008 +-#define DST_Y_TILE 0x00000010 +-#define DST_LAST_PEL 0x00000020 +-#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +-#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +-#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +-#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +-#define DST_BRES_SIGN 0x00000100 +-#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +-#define DST_POLYLINE_NONLAST 0x00008000 +-#define DST_RASTER_STALL 0x00010000 +-#define DST_POLY_EDGE 0x00040000 +- +- +-/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ +-#define DST_X_MAJOR_S 0x00000000 +-#define DST_Y_MAJOR_S 0x00000001 +-#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +-#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +-#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +-#define DST_X_LEFT_TO_RIGHT_S 0x80000000 +- +- +-/* DP_DATATYPE bit constants */ +-#define DST_8BPP 0x00000002 +-#define DST_15BPP 0x00000003 +-#define DST_16BPP 0x00000004 +-#define DST_24BPP 0x00000005 +-#define DST_32BPP 0x00000006 +-#define DST_8BPP_RGB332 0x00000007 +-#define DST_8BPP_Y8 0x00000008 +-#define DST_8BPP_RGB8 0x00000009 +-#define DST_16BPP_VYUY422 0x0000000b +-#define DST_16BPP_YVYU422 0x0000000c +-#define DST_32BPP_AYUV444 0x0000000e +-#define DST_16BPP_ARGB4444 0x0000000f +-#define BRUSH_SOLIDCOLOR 0x00000d00 +-#define SRC_MONO 0x00000000 +-#define SRC_MONO_LBKGD 0x00010000 +-#define SRC_DSTCOLOR 0x00030000 +-#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +-#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +-#define DP_CONVERSION_TEMP 0x80000000 +-#define HOST_BIG_ENDIAN_EN (1 << 29) +- +- +-/* DP_GUI_MASTER_CNTL bit constants */ +-#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +-#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +-#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +-#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +-#define GMC_SRC_CLIP_DEFAULT 0x00000000 +-#define GMC_SRC_CLIP_LEAVE 0x00000004 +-#define GMC_DST_CLIP_DEFAULT 0x00000000 +-#define GMC_DST_CLIP_LEAVE 0x00000008 +-#define GMC_BRUSH_8x8MONO 0x00000000 +-#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +-#define GMC_BRUSH_8x1MONO 0x00000020 +-#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +-#define GMC_BRUSH_1x8MONO 0x00000040 +-#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +-#define GMC_BRUSH_32x1MONO 0x00000060 +-#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +-#define GMC_BRUSH_32x32MONO 0x00000080 +-#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +-#define GMC_BRUSH_8x8COLOR 0x000000a0 +-#define GMC_BRUSH_8x1COLOR 0x000000b0 +-#define GMC_BRUSH_1x8COLOR 0x000000c0 +-#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +-#define GMC_DST_8BPP 0x00000200 +-#define GMC_DST_15BPP 0x00000300 +-#define GMC_DST_16BPP 0x00000400 +-#define GMC_DST_24BPP 0x00000500 +-#define GMC_DST_32BPP 0x00000600 +-#define GMC_DST_8BPP_RGB332 0x00000700 +-#define GMC_DST_8BPP_Y8 0x00000800 +-#define GMC_DST_8BPP_RGB8 0x00000900 +-#define GMC_DST_16BPP_VYUY422 0x00000b00 +-#define GMC_DST_16BPP_YVYU422 0x00000c00 +-#define GMC_DST_32BPP_AYUV444 0x00000e00 +-#define GMC_DST_16BPP_ARGB4444 0x00000f00 +-#define GMC_SRC_MONO 0x00000000 +-#define GMC_SRC_MONO_LBKGD 0x00001000 +-#define GMC_SRC_DSTCOLOR 0x00003000 +-#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +-#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +-#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +-#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +-#define GMC_DP_SRC_RECT 0x02000000 +-#define GMC_DP_SRC_HOST 0x03000000 +-#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +-#define GMC_3D_FCN_EN_CLR 0x00000000 +-#define GMC_3D_FCN_EN_SET 0x08000000 +-#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +-#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +-#define GMC_AUX_CLIP_LEAVE 0x00000000 +-#define GMC_AUX_CLIP_CLEAR 0x20000000 +-#define GMC_WRITE_MASK_LEAVE 0x00000000 +-#define GMC_WRITE_MASK_SET 0x40000000 +-#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +-#define GMC_SRC_DATATYPE_COLOR (3 << 12) +-#define ROP3_S 0x00cc0000 +-#define ROP3_SRCCOPY 0x00cc0000 +-#define ROP3_P 0x00f00000 +-#define ROP3_PATCOPY 0x00f00000 +-#define DP_SRC_SOURCE_MASK (7 << 24) +-#define GMC_BRUSH_NONE (15 << 4) +-#define DP_SRC_SOURCE_MEMORY (2 << 24) +-#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +- +-/* DP_MIX bit constants */ +-#define DP_SRC_RECT 0x00000200 +-#define DP_SRC_HOST 0x00000300 +-#define DP_SRC_HOST_BYTEALIGN 0x00000400 +- +-/* MPLL_CNTL bit constants */ +-#define MPLL_RESET 0x00000001 +- +-/* MDLL_CKO bit constants */ +-#define MCKOA_SLEEP 0x00000001 +-#define MCKOA_RESET 0x00000002 +-#define MCKOA_REF_SKEW_MASK 0x00000700 +-#define MCKOA_FB_SKEW_MASK 0x00007000 +- +-/* MDLL_RDCKA bit constants */ +-#define MRDCKA0_SLEEP 0x00000001 +-#define MRDCKA0_RESET 0x00000002 +-#define MRDCKA1_SLEEP 0x00010000 +-#define MRDCKA1_RESET 0x00020000 +- +-/* VCLK_ECP_CNTL constants */ +-#define VCLK_SRC_SEL_MASK 0x03 +-#define VCLK_SRC_SEL_CPUCLK 0x00 +-#define VCLK_SRC_SEL_PSCANCLK 0x01 +-#define VCLK_SRC_SEL_BYTECLK 0x02 +-#define VCLK_SRC_SEL_PPLLCLK 0x03 +-#define PIXCLK_ALWAYS_ONb 0x00000040 +-#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 +- +-/* BUS_CNTL1 constants */ +-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +-#define BUS_CNTL1_AGPCLK_VALID 0x80000000 +- +-/* PLL_PWRMGT_CNTL constants */ +-#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +-#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +-#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +-#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +-#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +-#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +-#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 +- +-/* TV_DAC_CNTL constants */ +-#define TV_DAC_CNTL_BGSLEEP 0x00000040 +-#define TV_DAC_CNTL_DETECT 0x00000010 +-#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +-#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +-#define TV_DAC_CNTL_BGADJ__SHIFT 16 +-#define TV_DAC_CNTL_DACADJ__SHIFT 20 +-#define TV_DAC_CNTL_RDACPD 0x01000000 +-#define TV_DAC_CNTL_GDACPD 0x02000000 +-#define TV_DAC_CNTL_BDACPD 0x04000000 +- +-/* DISP_MISC_CNTL constants */ +-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +-#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +-#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +-#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +-#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +-#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +-#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) +- +-/* DISP_PWR_MAN constants */ +-#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +-#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +-#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +-#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +-#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +-#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +-#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +-#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +-#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +-#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +-#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +-#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +-#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) +- +-/* masks */ +- +-#define CONFIG_MEMSIZE_MASK 0x1f000000 +-#define MEM_CFG_TYPE 0x40000000 +-#define DST_OFFSET_MASK 0x003fffff +-#define DST_PITCH_MASK 0x3fc00000 +-#define DEFAULT_TILE_MASK 0xc0000000 +-#define PPLL_DIV_SEL_MASK 0x00000300 +-#define PPLL_RESET 0x00000001 +-#define PPLL_SLEEP 0x00000002 +-#define PPLL_ATOMIC_UPDATE_EN 0x00010000 +-#define PPLL_REF_DIV_MASK 0x000003ff +-#define PPLL_FB3_DIV_MASK 0x000007ff +-#define PPLL_POST3_DIV_MASK 0x00070000 +-#define PPLL_ATOMIC_UPDATE_R 0x00008000 +-#define PPLL_ATOMIC_UPDATE_W 0x00008000 +-#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +-#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +-#define R300_PPLL_REF_DIV_ACC_SHIFT 18 +- +-#define GUI_ACTIVE 0x80000000 +- +- +-#define MC_IND_INDEX 0x01F8 +-#define MC_IND_DATA 0x01FC +- +-/* PAD_CTLR_STRENGTH */ +-#define PAD_MANUAL_OVERRIDE 0x80000000 +- +-/* pllCLK_PIN_CNTL */ +-#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +-#define CLK_PIN_CNTL__OSC_EN 0x00000001L +-#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +-#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +-#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +-#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +-#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +-#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +-#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +-#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +-#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +-#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L +- +-/* pllCLK_PWRMGT_CNTL */ +-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +-#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +-#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +-#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +-#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +-#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +-#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +-#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +-#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +-#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +-#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f +- +-/* pllP2PLL_CNTL */ +-#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +-#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +-#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +-#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +-#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +-#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +-#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +-#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +-#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +-#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +-#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +-#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +-#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +-#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +-#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +-#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +-#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L +- +-/* pllPIXCLKS_CNTL */ +-#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +-#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +-#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +-#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +-#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +-#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +-#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +-#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +-#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +-#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +-#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f +- +- +-/* pllPIXCLKS_CNTL */ +-#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +-#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +-#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +-#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +-#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +-#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +-#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +-#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +-#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +-#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +-#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +-#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +-#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +-#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +-#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +-#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +-#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +-#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +-#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +- +- +-/* pllP2PLL_DIV_0 */ +-#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +-#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L +- +-/* pllSCLK_CNTL */ +-#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +-#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +-#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +-#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +-#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +-#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +-#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +-#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +-#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +-#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +-#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +-#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +-#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +-#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +-#define SCLK_CNTL__FORCE_DISP2 0x00008000L +-#define SCLK_CNTL__FORCE_CP 0x00010000L +-#define SCLK_CNTL__FORCE_HDP 0x00020000L +-#define SCLK_CNTL__FORCE_DISP1 0x00040000L +-#define SCLK_CNTL__FORCE_TOP 0x00080000L +-#define SCLK_CNTL__FORCE_E2 0x00100000L +-#define SCLK_CNTL__FORCE_SE 0x00200000L +-#define SCLK_CNTL__FORCE_IDCT 0x00400000L +-#define SCLK_CNTL__FORCE_VIP 0x00800000L +-#define SCLK_CNTL__FORCE_RE 0x01000000L +-#define SCLK_CNTL__FORCE_PB 0x02000000L +-#define SCLK_CNTL__FORCE_TAM 0x04000000L +-#define SCLK_CNTL__FORCE_TDM 0x08000000L +-#define SCLK_CNTL__FORCE_RB 0x10000000L +-#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +-#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +-#define SCLK_CNTL__FORCE_OV0 0x80000000L +-#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +-#define SCLK_CNTL__R300_FORCE_SR (1<<25) +-#define SCLK_CNTL__R300_FORCE_PX (1<<26) +-#define SCLK_CNTL__R300_FORCE_TX (1<<27) +-#define SCLK_CNTL__R300_FORCE_US (1<<28) +-#define SCLK_CNTL__R300_FORCE_SU (1<<30) +-#define SCLK_CNTL__FORCEON_MASK 0xffff8000L +- +-/* pllSCLK_CNTL2 */ +-#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +-#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +-#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +-#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +-#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +-#define SCLK_CNTL2__R300_FORCE_GA (1<<15) +- +-/* SCLK_MORE_CNTL */ +-#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +-#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +-#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +-#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +-#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +-#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +-#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +-#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +-#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +-#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +-#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +-#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +-#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +-#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +-#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +-#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +-#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +-#define SCLK_MORE_CNTL__FORCEON 0x00000700L +- +-/* MCLK_CNTL */ +-#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +-#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +-#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +-#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +-#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +-#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +-#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +-#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +-#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +-#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +-#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +-#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +-#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +-#define MCLK_CNTL__FORCE_MC 0x00100000L +-#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +-#define MCLK_CNTL__FORCE_AIC 0x00200000L +-#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +-#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +-#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +-#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +-#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +-#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) +- +-/* MCLK_MISC */ +-#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +-#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +-#define MCLK_MISC__DLL_READY_LAT 0x00000100L +-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +-#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +-#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +-#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +-#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +-#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +-#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +-#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +-#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +-#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +-#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +-#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +-#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +-#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L +- +-/* VCLK_ECP_CNTL */ +-#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +-#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +-#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +-#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +-#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +-#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +-#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +-#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +-#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) +- +-/* PLL_PWRMGT_CNTL */ +-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +-#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +-#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +-#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +-#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +-#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +-#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +-#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +-#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +-#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +-#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L +- +-/* CLK_PWRMGT_CNTL */ +-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +-#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +-#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +-#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +-#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +-#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +-#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +-#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +-#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +-#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +-#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +-#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +-#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +-#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +-#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +-#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +-#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +-#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L +- +-/* BUS_CNTL1 */ +-#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +-#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +-#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +-#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +-#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +-#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +-#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +-#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +-#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +-#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +-#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +-#define BUS_CNTL1__AGPCLK_VALID 0x80000000L +- +-/* BUS_CNTL1 */ +-#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +-#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +-#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +-#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +-#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +-#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +-#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f +- +-/* CRTC_OFFSET_CNTL */ +-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L +- +-/* CRTC_GEN_CNTL */ +-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +-#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +-#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +-#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +-#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +-#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +-#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +-#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +-#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +-#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L +- +-/* CRTC2_GEN_CNTL */ +-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +-#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +-#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +-#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +-#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +-#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +-#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L +- +-/* AGP_CNTL */ +-#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +-#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +-#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +-#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +-#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +-#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +-#define AGP_CNTL__EN_2X_STBB 0x00000400L +-#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +-#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +-#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +-#define AGP_CNTL__SBA_DIS 0x00001000L +-#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +-#define AGP_CNTL__AGP_REV_ID 0x00002000L +-#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +-#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +-#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +-#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +-#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +-#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +-#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +-#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +-#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +-#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +-#define AGP_CNTL__EN_RBFCALM 0x00800000L +-#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +-#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +-#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +-#define AGP_CNTL__DIS_RBF 0x02000000L +-#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +-#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +-#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +-#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L +- +-/* AGP_CNTL */ +-#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +-#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +-#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +-#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +-#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +-#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +-#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +-#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +-#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +-#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +-#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +-#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +-#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +-#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +-#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +-#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +-#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +-#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e +- +-/* DISP_MISC_CNTL */ +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +-#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +-#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +-#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +-#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +-#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +-#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +-#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +-#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +-#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +-#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L +- +-/* DISP_PWR_MAN */ +-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +-#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +-#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +-#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +-#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +-#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +-#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +-#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +-#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +-#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +-#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +-#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +-#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +-#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L +- +-/* MC_IND_INDEX */ +-#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +-#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +-#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L +- +-/* MC_IND_DATA */ +-#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL +- +-/* MC_CHP_IO_CNTL_A1 */ +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f +- +-/* MC_CHP_IO_CNTL_B1 */ +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f +- +-/* MC_CHP_IO_CNTL_A1 */ +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L +- +-/* MC_CHP_IO_CNTL_B1 */ +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L +- +-/* MEM_SDRAM_MODE_REG */ +-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L +- +-/* MEM_SDRAM_MODE_REG */ +-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f +- +-/* MEM_REFRESH_CNTL */ +-#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +-#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L +- +-/* MC_STATUS */ +-#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +-#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +-#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +-#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +-#define MC_STATUS__MC_IDLE_MASK 0x00000004L +-#define MC_STATUS__MC_IDLE 0x00000004L +-#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +-#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +-#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +-#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +-#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +-#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +-#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +-#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +-#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +-#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L +- +-/* MDLL_CKO */ +-#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +-#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +-#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +-#define MDLL_CKO__MCKOA_RESET 0x00000002L +-#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +-#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +-#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +-#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +-#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +-#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +-#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +-#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +-#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +-#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +-#define MDLL_CKO__MCKOB_RESET 0x00020000L +-#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +-#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +-#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +-#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +-#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +-#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +-#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L +- +-/* MDLL_RDCKA */ +-#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +-#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +-#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +-#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +-#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +-#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +-#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +-#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +-#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +-#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +-#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +-#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +-#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +-#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +-#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +-#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +-#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +-#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +-#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +-#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +-#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +-#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +-#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +-#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +-#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +-#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L +- +-/* MDLL_RDCKB */ +-#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +-#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +-#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +-#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +-#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +-#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +-#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +-#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +-#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +-#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +-#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +-#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +-#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +-#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +-#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +-#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +-#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +-#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +-#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +-#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +-#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +-#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +-#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +-#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +-#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +-#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L +- +-#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +-#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +-#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +-#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +-#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +-#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +-#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +-#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L +- +-#define pllCLK_PIN_CNTL 0x0001 +-#define pllPPLL_CNTL 0x0002 +-#define pllPPLL_REF_DIV 0x0003 +-#define pllPPLL_DIV_0 0x0004 +-#define pllPPLL_DIV_1 0x0005 +-#define pllPPLL_DIV_2 0x0006 +-#define pllPPLL_DIV_3 0x0007 +-#define pllVCLK_ECP_CNTL 0x0008 +-#define pllHTOTAL_CNTL 0x0009 +-#define pllM_SPLL_REF_FB_DIV 0x000A +-#define pllAGP_PLL_CNTL 0x000B +-#define pllSPLL_CNTL 0x000C +-#define pllSCLK_CNTL 0x000D +-#define pllMPLL_CNTL 0x000E +-#define pllMDLL_CKO 0x000F +-#define pllMDLL_RDCKA 0x0010 +-#define pllMDLL_RDCKB 0x0011 +-#define pllMCLK_CNTL 0x0012 +-#define pllPLL_TEST_CNTL 0x0013 +-#define pllCLK_PWRMGT_CNTL 0x0014 +-#define pllPLL_PWRMGT_CNTL 0x0015 +-#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +-#define pllCG_TEST_MACRO_RW_READ 0x0017 +-#define pllCG_TEST_MACRO_RW_DATA 0x0018 +-#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +-#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +-#define pllDISP_TEST_MACRO_RW_READ 0x001B +-#define pllDISP_TEST_MACRO_RW_DATA 0x001C +-#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +-#define pllSCLK_CNTL2 0x001E +-#define pllMCLK_MISC 0x001F +-#define pllTV_PLL_FINE_CNTL 0x0020 +-#define pllTV_PLL_CNTL 0x0021 +-#define pllTV_PLL_CNTL1 0x0022 +-#define pllTV_DTO_INCREMENTS 0x0023 +-#define pllSPLL_AUX_CNTL 0x0024 +-#define pllMPLL_AUX_CNTL 0x0025 +-#define pllP2PLL_CNTL 0x002A +-#define pllP2PLL_REF_DIV 0x002B +-#define pllP2PLL_DIV_0 0x002C +-#define pllPIXCLKS_CNTL 0x002D +-#define pllHTOTAL2_CNTL 0x002E +-#define pllSSPLL_CNTL 0x0030 +-#define pllSSPLL_REF_DIV 0x0031 +-#define pllSSPLL_DIV_0 0x0032 +-#define pllSS_INT_CNTL 0x0033 +-#define pllSS_TST_CNTL 0x0034 +-#define pllSCLK_MORE_CNTL 0x0035 +- +-#define ixMC_PERF_CNTL 0x0000 +-#define ixMC_PERF_SEL 0x0001 +-#define ixMC_PERF_REGION_0 0x0002 +-#define ixMC_PERF_REGION_1 0x0003 +-#define ixMC_PERF_COUNT_0 0x0004 +-#define ixMC_PERF_COUNT_1 0x0005 +-#define ixMC_PERF_COUNT_2 0x0006 +-#define ixMC_PERF_COUNT_3 0x0007 +-#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +-#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +-#define ixMC_IMP_CNTL 0x000A +-#define ixMC_CHP_IO_CNTL_A0 0x000B +-#define ixMC_CHP_IO_CNTL_A1 0x000C +-#define ixMC_CHP_IO_CNTL_B0 0x000D +-#define ixMC_CHP_IO_CNTL_B1 0x000E +-#define ixMC_IMP_CNTL_0 0x000F +-#define ixTC_MISMATCH_1 0x0010 +-#define ixTC_MISMATCH_2 0x0011 +-#define ixMC_BIST_CTRL 0x0012 +-#define ixREG_COLLAR_WRITE 0x0013 +-#define ixREG_COLLAR_READ 0x0014 +-#define ixR300_MC_IMP_CNTL 0x0018 +-#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +-#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +-#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +-#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +-#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +-#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +-#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +-#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +-#define ixR300_MC_IMP_CNTL_0 0x0021 +-#define ixR300_MC_ELPIDA_CNTL 0x0022 +-#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +-#define ixR300_MC_READ_CNTL_CD 0x0024 +-#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +-#define ixR300_MC_DEBUG_CNTL 0x0026 +-#define ixR300_MC_BIST_CNTL_0 0x0028 +-#define ixR300_MC_BIST_CNTL_1 0x0029 +-#define ixR300_MC_BIST_CNTL_2 0x002a +-#define ixR300_MC_BIST_CNTL_3 0x002b +-#define ixR300_MC_BIST_CNTL_4 0x002c +-#define ixR300_MC_BIST_CNTL_5 0x002d +-#define ixR300_MC_IMP_STATUS 0x002e +-#define ixR300_MC_DLL_CNTL 0x002f +-#define NB_TOM 0x15C +- +-#endif /* _RADEON_H */ +diff -ruN u-boot-2021.10/include/smem.h u-boot/include/smem.h +--- u-boot-2021.10/include/smem.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/smem.h 2021-11-01 17:10:14.672903396 +0100 +@@ -88,4 +88,3 @@ + int smem_get_free_space(struct udevice *dev, unsigned int host); + + #endif /* _smem_h_ */ +- +diff -ruN u-boot-2021.10/include/stdio.h u-boot/include/stdio.h +--- u-boot-2021.10/include/stdio.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/stdio.h 2021-11-01 17:10:14.672903396 +0100 +@@ -10,9 +10,9 @@ + + /* stdout */ + #if !defined(CONFIG_SPL_BUILD) || \ +- (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \ ++ (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL)) || \ + (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \ +- defined(CONFIG_SPL_SERIAL_SUPPORT)) ++ defined(CONFIG_SPL_SERIAL)) + void putc(const char c); + void puts(const char *s); + int __printf(1, 2) printf(const char *fmt, ...); +diff -ruN u-boot-2021.10/include/st_logo_data.h u-boot/include/st_logo_data.h +--- u-boot-2021.10/include/st_logo_data.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/st_logo_data.h 2021-11-01 17:10:14.672903396 +0100 +@@ -3263,4 +3263,3 @@ + 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, + 0xe1, 0x00, 0x00, 0x01 + }; +- +diff -ruN u-boot-2021.10/include/sunxi_image.h u-boot/include/sunxi_image.h +--- u-boot-2021.10/include/sunxi_image.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/sunxi_image.h 2021-11-01 17:10:14.676236547 +0100 +@@ -9,9 +9,12 @@ + * + * Shared between mkimage and the SPL. + */ ++ + #ifndef SUNXI_IMAGE_H + #define SUNXI_IMAGE_H + ++#include <linux/types.h> ++ + #define BOOT0_MAGIC "eGON.BT0" + #define BROM_STAMP_VALUE 0x5f0a6c39 + #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ +@@ -79,4 +82,63 @@ + /* Compile time check to assure proper alignment of structure */ + typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)]; + ++struct toc0_main_info { ++ uint8_t name[8]; ++ __le32 magic; ++ __le32 checksum; ++ __le32 serial; ++ __le32 status; ++ __le32 num_items; ++ __le32 length; ++ uint8_t platform[4]; ++ uint8_t reserved[8]; ++ uint8_t end[4]; ++}; ++ ++#define TOC0_MAIN_INFO_NAME "TOC0.GLH" ++#define TOC0_MAIN_INFO_MAGIC 0x89119800 ++#define TOC0_MAIN_INFO_END "MIE;" ++ ++struct toc0_item_info { ++ __le32 name; ++ __le32 offset; ++ __le32 length; ++ __le32 status; ++ __le32 type; ++ __le32 load_addr; ++ uint8_t reserved[4]; ++ uint8_t end[4]; ++}; ++ ++#define TOC0_ITEM_INFO_NAME_CERT 0x00010101 ++#define TOC0_ITEM_INFO_NAME_FIRMWARE 0x00010202 ++#define TOC0_ITEM_INFO_NAME_KEY 0x00010303 ++#define TOC0_ITEM_INFO_END "IIE;" ++ ++struct toc1_main_info { ++ uint8_t name[16]; ++ __le32 magic; ++ __le32 checksum; ++ __le32 serial; ++ __le32 status; ++ __le32 num_items; ++ __le32 length; ++ __le32 major_version; ++ __le32 minor_version; ++ __le32 reserved[3]; ++ uint8_t end[4]; ++}; ++ ++struct toc1_item_info { ++ uint8_t name[64]; ++ __le32 offset; ++ __le32 length; ++ __le32 encryption; ++ __le32 type; ++ __le32 load_addr; ++ __le32 index; ++ __le32 reserved[69]; ++ uint8_t end[4]; ++}; ++ + #endif +diff -ruN u-boot-2021.10/include/sysreset.h u-boot/include/sysreset.h +--- u-boot-2021.10/include/sysreset.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/sysreset.h 2021-11-01 17:10:14.676236547 +0100 +@@ -118,4 +118,18 @@ + */ + void reset_cpu(void); + ++/** ++ * sysreset_register_wdt() - register a watchdog for use with sysreset ++ * ++ * This registers the given watchdog timer to be used to reset the system. ++ * ++ * @dev: WDT device ++ * @return: 0 if OK, -errno if error ++ */ ++#if IS_ENABLED(CONFIG_SYSRESET_WATCHDOG_AUTO) ++int sysreset_register_wdt(struct udevice *dev); ++#else ++static inline int sysreset_register_wdt(struct udevice *dev) { return 0; } ++#endif ++ + #endif +diff -ruN u-boot-2021.10/include/tee/optee.h u-boot/include/tee/optee.h +--- u-boot-2021.10/include/tee/optee.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/tee/optee.h 2021-11-01 17:10:14.676236547 +0100 +@@ -43,21 +43,7 @@ + return optee_image_get_entry_point(hdr) - sizeof(struct optee_header); + } + +-#if defined(CONFIG_OPTEE) +-int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start, +- unsigned long tzdram_len, unsigned long image_len); +-#else +-static inline int optee_verify_image(struct optee_header *hdr, +- unsigned long tzdram_start, +- unsigned long tzdram_len, +- unsigned long image_len) +-{ +- return -EPERM; +-} +- +-#endif +- +-#if defined(CONFIG_OPTEE) ++#if defined(CONFIG_OPTEE_IMAGE) + int optee_verify_bootm_image(unsigned long image_addr, + unsigned long image_load_addr, + unsigned long image_len); +@@ -70,7 +56,7 @@ + } + #endif + +-#if defined(CONFIG_OPTEE) && defined(CONFIG_OF_LIBFDT) ++#if defined(CONFIG_OPTEE_LIB) && defined(CONFIG_OF_LIBFDT) + int optee_copy_fdt_nodes(void *new_blob); + #else + static inline int optee_copy_fdt_nodes(void *new_blob) +diff -ruN u-boot-2021.10/include/tee.h u-boot/include/tee.h +--- u-boot-2021.10/include/tee.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/tee.h 2021-11-01 17:10:14.676236547 +0100 +@@ -307,11 +307,22 @@ + * Returns a probed TEE device of the first TEE device matched by the + * match() callback or NULL. + */ ++#if CONFIG_IS_ENABLED(TEE) + struct udevice *tee_find_device(struct udevice *start, + int (*match)(struct tee_version_data *vers, + const void *data), + const void *data, + struct tee_version_data *vers); ++#else ++static inline struct udevice *tee_find_device(struct udevice *start, ++ int (*match)(struct tee_version_data *vers, ++ const void *data), ++ const void *data, ++ struct tee_version_data *vers) ++{ ++ return NULL; ++} ++#endif + + /** + * tee_get_version() - Query capabilities of TEE device +diff -ruN u-boot-2021.10/include/test/ut.h u-boot/include/test/ut.h +--- u-boot-2021.10/include/test/ut.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/test/ut.h 2021-11-01 17:10:14.676236547 +0100 +@@ -83,6 +83,21 @@ + int ut_check_skipline(struct unit_test_state *uts); + + /** ++ * ut_check_skip_to_line() - skip output until a line is found ++ * ++ * This creates a string and then checks it against the following lines of ++ * console output obtained with console_record_readline() until it is found. ++ * ++ * After the function returns, uts->expect_str holds the expected string and ++ * uts->actual_str holds the actual string read from the console. ++ * ++ * @uts: Test state ++ * @fmt: printf() format string to look for, followed by args ++ * @return 0 if OK, -ENOENT if not found, other value on error ++ */ ++int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...); ++ ++/** + * ut_check_console_end() - Check there is no more console output + * + * After the function returns, uts->actual_str holds the actual string read +@@ -286,6 +301,15 @@ + return CMD_RET_FAILURE; \ + } \ + ++/* Assert that a following console output line matches */ ++#define ut_assert_skip_to_line(fmt, args...) \ ++ if (ut_check_skip_to_line(uts, fmt, ##args)) { \ ++ ut_failf(uts, __FILE__, __LINE__, __func__, \ ++ "console", "\nExpected '%s',\n got to '%s'", \ ++ uts->expect_str, uts->actual_str); \ ++ return CMD_RET_FAILURE; \ ++ } \ ++ + /* Assert that there is no more console output */ + #define ut_assert_console_end() \ + if (ut_check_console_end(uts)) { \ +diff -ruN u-boot-2021.10/include/tsec.h u-boot/include/tsec.h +--- u-boot-2021.10/include/tsec.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/tsec.h 2021-11-01 17:10:14.676236547 +0100 +@@ -25,7 +25,7 @@ + #define TSEC_SIZE 0x40000 + #define TSEC_MDIO_OFFSET 0x40000 + #else +-#define TSEC_SIZE 0x01000 ++#define TSEC_SIZE 0x01000 + #define TSEC_MDIO_OFFSET 0x01000 + #endif + +diff -ruN u-boot-2021.10/include/u-boot/hash.h u-boot/include/u-boot/hash.h +--- u-boot-2021.10/include/u-boot/hash.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/u-boot/hash.h 2021-11-01 17:10:14.679569698 +0100 +@@ -0,0 +1,61 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2021 ASPEED Technology Inc. ++ */ ++#ifndef _UBOOT_HASH_H ++#define _UBOOT_HASH_H ++ ++enum HASH_ALGO { ++ HASH_ALGO_CRC16_CCITT, ++ HASH_ALGO_CRC32, ++ HASH_ALGO_MD5, ++ HASH_ALGO_SHA1, ++ HASH_ALGO_SHA256, ++ HASH_ALGO_SHA384, ++ HASH_ALGO_SHA512, ++ ++ HASH_ALGO_NUM, ++ ++ HASH_ALGO_INVALID = 0xffffffff, ++}; ++ ++/* general APIs for hash algo information */ ++enum HASH_ALGO hash_algo_lookup_by_name(const char *name); ++ssize_t hash_algo_digest_size(enum HASH_ALGO algo); ++const char *hash_algo_name(enum HASH_ALGO algo); ++ ++/* device-dependent APIs */ ++int hash_digest(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf); ++int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf, uint32_t chunk_sz); ++int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); ++int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); ++int hash_finish(struct udevice *dev, void *ctx, void *obuf); ++ ++/* ++ * struct hash_ops - Driver model for Hash operations ++ * ++ * The uclass interface is implemented by all hash devices ++ * which use driver model. ++ */ ++struct hash_ops { ++ /* progressive operations */ ++ int (*hash_init)(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); ++ int (*hash_update)(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); ++ int (*hash_finish)(struct udevice *dev, void *ctx, void *obuf); ++ ++ /* all-in-one operation */ ++ int (*hash_digest)(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf); ++ ++ /* all-in-one operation with watchdog triggering every chunk_sz */ ++ int (*hash_digest_wd)(struct udevice *dev, enum HASH_ALGO algo, ++ const void *ibuf, const uint32_t ilen, ++ void *obuf, uint32_t chunk_sz); ++}; ++ ++#endif +diff -ruN u-boot-2021.10/include/u-boot/md5.h u-boot/include/u-boot/md5.h +--- u-boot-2021.10/include/u-boot/md5.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/u-boot/md5.h 2021-11-01 17:10:14.679569698 +0100 +@@ -19,6 +19,10 @@ + }; + }; + ++void MD5Init(struct MD5Context *ctx); ++void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len); ++void MD5Final(unsigned char digest[16], struct MD5Context *ctx); ++ + /* + * Calculate and store in 'output' the MD5 digest of 'len' bytes at + * 'input'. 'output' must have enough space to hold 16 bytes. +diff -ruN u-boot-2021.10/include/version.h u-boot/include/version.h +--- u-boot-2021.10/include/version.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/version.h 2021-11-01 17:10:14.679569698 +0100 +@@ -7,16 +7,8 @@ + #ifndef __VERSION_H__ + #define __VERSION_H__ + +-#include <timestamp.h> +- + #ifndef DO_DEPS_ONLY + #include "generated/version_autogenerated.h" + #endif + +-#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ +- U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING +- +-#ifndef __ASSEMBLY__ +-extern const char version_string[]; +-#endif /* __ASSEMBLY__ */ + #endif /* __VERSION_H__ */ +diff -ruN u-boot-2021.10/include/version_string.h u-boot/include/version_string.h +--- u-boot-2021.10/include/version_string.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/version_string.h 2021-11-01 17:10:14.679569698 +0100 +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __VERSION_STRING_H__ ++#define __VERSION_STRING_H__ ++ ++extern const char version_string[]; ++ ++#endif /* __VERSION_STRING_H__ */ +diff -ruN u-boot-2021.10/include/video_font_4x6.h u-boot/include/video_font_4x6.h +--- u-boot-2021.10/include/video_font_4x6.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/video_font_4x6.h 2021-11-01 17:10:14.682902849 +0100 +@@ -49,7 +49,7 @@ + static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { + + /*{*/ +- /* Char 0: ' ' */ ++ /* Char 0: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -58,7 +58,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 1: ' ' */ ++ /* Char 1: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -67,7 +67,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 2: ' ' */ ++ /* Char 2: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -76,7 +76,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 3: ' ' */ ++ /* Char 3: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -85,7 +85,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 4: ' ' */ ++ /* Char 4: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -94,7 +94,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 5: ' ' */ ++ /* Char 5: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -103,7 +103,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 6: ' ' */ ++ /* Char 6: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -112,7 +112,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 7: ' ' */ ++ /* Char 7: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -121,7 +121,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 8: ' ' */ ++ /* Char 8: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -130,7 +130,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 9: ' ' */ ++ /* Char 9: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -139,7 +139,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 10: '' */ ++ /* Char 10: '' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -148,7 +148,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 11: ' ' */ ++ /* Char 11: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -157,7 +157,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 12: ' ' */ ++ /* Char 12: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -166,7 +166,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 13: ' ' */ ++ /* Char 13: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -175,7 +175,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 14: ' ' */ ++ /* Char 14: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -184,7 +184,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 15: ' ' */ ++ /* Char 15: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -193,7 +193,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 16: ' ' */ ++ /* Char 16: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -202,7 +202,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 17: ' ' */ ++ /* Char 17: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -211,7 +211,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 18: ' ' */ ++ /* Char 18: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -220,7 +220,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 19: ' ' */ ++ /* Char 19: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -229,7 +229,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 20: ' ' */ ++ /* Char 20: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -238,7 +238,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 21: ' ' */ ++ /* Char 21: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -247,7 +247,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 22: ' ' */ ++ /* Char 22: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -256,7 +256,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 23: ' ' */ ++ /* Char 23: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -265,7 +265,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 24: ' ' */ ++ /* Char 24: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -274,7 +274,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 25: ' ' */ ++ /* Char 25: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -283,7 +283,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 26: ' ' */ ++ /* Char 26: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -292,7 +292,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 27: ' ' */ ++ /* Char 27: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -301,7 +301,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 28: ' ' */ ++ /* Char 28: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -310,7 +310,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 29: ' ' */ ++ /* Char 29: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -319,7 +319,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 30: ' ' */ ++ /* Char 30: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -328,7 +328,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 31: ' ' */ ++ /* Char 31: ' ' */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -337,7 +337,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 32: ' ' */ ++ /* Char 32: ' ' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ +@@ -346,7 +346,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 33: '!' */ ++ /* Char 33: '!' */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -355,7 +355,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 34: '"' */ ++ /* Char 34: '"' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ +@@ -364,7 +364,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 35: '#' */ ++ /* Char 35: '#' */ + 0xaa, /*= [* * ] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ +@@ -373,7 +373,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 36: '$' */ ++ /* Char 36: '$' */ + 0x44, /*= [ * ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ +@@ -382,7 +382,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 37: '%' */ ++ /* Char 37: '%' */ + 0xaa, /*= [* * ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -391,7 +391,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 38: '&' */ ++ /* Char 38: '&' */ + 0x66, /*= [ ** ] */ + 0x99, /*= [* *] */ + 0x66, /*= [ ** ] */ +@@ -400,7 +400,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 39: ''' */ ++ /* Char 39: ''' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ +@@ -409,7 +409,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 40: '(' */ ++ /* Char 40: '(' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -418,7 +418,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 41: ')' */ ++ /* Char 41: ')' */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ +@@ -427,7 +427,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 42: '*' */ ++ /* Char 42: '*' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -436,7 +436,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 43: '+' */ ++ /* Char 43: '+' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ +@@ -445,7 +445,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 44: ',' */ ++ /* Char 44: ',' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ +@@ -454,7 +454,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 45: '-' */ ++ /* Char 45: '-' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ +@@ -463,7 +463,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 46: '.' */ ++ /* Char 46: '.' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ +@@ -472,7 +472,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 47: '/' */ ++ /* Char 47: '/' */ + 0x00, /*= [ ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -481,7 +481,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 48: '0' */ ++ /* Char 48: '0' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -490,7 +490,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 49: '1' */ ++ /* Char 49: '1' */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ +@@ -499,7 +499,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 50: '2' */ ++ /* Char 50: '2' */ + 0xcc, /*= [** ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -508,7 +508,7 @@ + 0x00, /*= [ ] */ + /*}*/ + /*{*/ +- /* Char 51: '3' */ ++ /* Char 51: '3' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ +@@ -516,7 +516,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 52: '4' */ ++ /*{*/ /* Char 52: '4' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -524,7 +524,7 @@ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 53: '5' */ ++ /*{*/ /* Char 53: '5' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ +@@ -532,7 +532,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 54: '6' */ ++ /*{*/ /* Char 54: '6' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ +@@ -540,7 +540,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 55: '7' */ ++ /*{*/ /* Char 55: '7' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ +@@ -548,7 +548,7 @@ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 56: '8' */ ++ /*{*/ /* Char 56: '8' */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -556,7 +556,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 57: '9' */ ++ /*{*/ /* Char 57: '9' */ + 0xee, /*= [*** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -564,7 +564,7 @@ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 58: ':' */ ++ /*{*/ /* Char 58: ':' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ +@@ -572,7 +572,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 59: ';' */ ++ /*{*/ /* Char 59: ';' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ +@@ -580,7 +580,7 @@ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ + /*}*/ +- /*{*/ /* Char 60: '<' */ ++ /*{*/ /* Char 60: '<' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x88, /*= [* ] */ +@@ -588,7 +588,7 @@ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 61: '=' */ ++ /*{*/ /* Char 61: '=' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ +@@ -596,7 +596,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 62: '>' */ ++ /*{*/ /* Char 62: '>' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x22, /*= [ * ] */ +@@ -604,7 +604,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 63: '?' */ ++ /*{*/ /* Char 63: '?' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ +@@ -612,7 +612,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 64: '@' */ ++ /*{*/ /* Char 64: '@' */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -620,7 +620,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 65: 'A' */ ++ /*{*/ /* Char 65: 'A' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -628,7 +628,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 66: 'B' */ ++ /*{*/ /* Char 66: 'B' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ +@@ -636,7 +636,7 @@ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 67: 'C' */ ++ /*{*/ /* Char 67: 'C' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ +@@ -644,7 +644,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 68: 'D' */ ++ /*{*/ /* Char 68: 'D' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -652,7 +652,7 @@ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 69: 'E' */ ++ /*{*/ /* Char 69: 'E' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ +@@ -660,7 +660,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 70: 'F' */ ++ /*{*/ /* Char 70: 'F' */ + 0xee, /*= [*** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ +@@ -668,7 +668,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 71: 'G' */ ++ /*{*/ /* Char 71: 'G' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0xee, /*= [*** ] */ +@@ -676,7 +676,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 72: 'H' */ ++ /*{*/ /* Char 72: 'H' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -684,7 +684,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 73: 'I' */ ++ /*{*/ /* Char 73: 'I' */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -692,7 +692,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 74: 'J' */ ++ /*{*/ /* Char 74: 'J' */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ +@@ -700,7 +700,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 75: 'K' */ ++ /*{*/ /* Char 75: 'K' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ +@@ -708,7 +708,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 76: 'L' */ ++ /*{*/ /* Char 76: 'L' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ +@@ -716,7 +716,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 77: 'M' */ ++ /*{*/ /* Char 77: 'M' */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -724,7 +724,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 78: 'N' */ ++ /*{*/ /* Char 78: 'N' */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -732,7 +732,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 79: 'O' */ ++ /*{*/ /* Char 79: 'O' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -740,7 +740,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 80: 'P' */ ++ /*{*/ /* Char 80: 'P' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xcc, /*= [** ] */ +@@ -748,7 +748,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 81: 'Q' */ ++ /*{*/ /* Char 81: 'Q' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -756,7 +756,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 82: 'R' */ ++ /*{*/ /* Char 82: 'R' */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -764,7 +764,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 83: 'S' */ ++ /*{*/ /* Char 83: 'S' */ + 0x66, /*= [ ** ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ +@@ -772,7 +772,7 @@ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 84: 'T' */ ++ /*{*/ /* Char 84: 'T' */ + 0xee, /*= [*** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -780,7 +780,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 85: 'U' */ ++ /*{*/ /* Char 85: 'U' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -788,7 +788,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 86: 'V' */ ++ /*{*/ /* Char 86: 'V' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -796,7 +796,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 87: 'W' */ ++ /*{*/ /* Char 87: 'W' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0xee, /*= [*** ] */ +@@ -804,7 +804,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 88: 'X' */ ++ /*{*/ /* Char 88: 'X' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ +@@ -812,7 +812,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 89: 'Y' */ ++ /*{*/ /* Char 89: 'Y' */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ + 0x44, /*= [ * ] */ +@@ -820,7 +820,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 90: 'Z' */ ++ /*{*/ /* Char 90: 'Z' */ + 0xee, /*= [*** ] */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -828,7 +828,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 91: '[' */ ++ /*{*/ /* Char 91: '[' */ + 0x66, /*= [ ** ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -836,7 +836,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 92: '\' */ ++ /*{*/ /* Char 92: '\' */ + 0x00, /*= [ ] */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ +@@ -844,7 +844,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 93: ']' */ ++ /*{*/ /* Char 93: ']' */ + 0x66, /*= [ ** ] */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ +@@ -852,7 +852,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 94: '^' */ ++ /*{*/ /* Char 94: '^' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ +@@ -860,7 +860,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 95: '_' */ ++ /*{*/ /* Char 95: '_' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ +@@ -868,7 +868,7 @@ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ + /*}*/ +- /*{*/ /* Char 96: '`' */ ++ /*{*/ /* Char 96: '`' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ +@@ -876,7 +876,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 97: 'a' */ ++ /*{*/ /* Char 97: 'a' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ +@@ -884,7 +884,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 98: 'b' */ ++ /*{*/ /* Char 98: 'b' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0xcc, /*= [** ] */ +@@ -892,7 +892,7 @@ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 99: 'c' */ ++ /*{*/ /* Char 99: 'c' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ +@@ -900,7 +900,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 100: 'd' */ ++ /*{*/ /* Char 100: 'd' */ + 0x22, /*= [ * ] */ + 0x22, /*= [ * ] */ + 0x66, /*= [ ** ] */ +@@ -908,7 +908,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 101: 'e' */ ++ /*{*/ /* Char 101: 'e' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -916,7 +916,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 102: 'f' */ ++ /*{*/ /* Char 102: 'f' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ +@@ -924,7 +924,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 103: 'g' */ ++ /*{*/ /* Char 103: 'g' */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xaa, /*= [* * ] */ +@@ -932,7 +932,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 104: 'h' */ ++ /*{*/ /* Char 104: 'h' */ + 0x88, /*= [* ] */ + 0x88, /*= [* ] */ + 0xcc, /*= [** ] */ +@@ -940,7 +940,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 105: 'i' */ ++ /*{*/ /* Char 105: 'i' */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ +@@ -948,7 +948,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 106: 'j' */ ++ /*{*/ /* Char 106: 'j' */ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ +@@ -956,7 +956,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 107: 'k' */ ++ /*{*/ /* Char 107: 'k' */ + 0x00, /*= [ ] */ + 0x88, /*= [* ] */ + 0xaa, /*= [* * ] */ +@@ -964,7 +964,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 108: 'l' */ ++ /*{*/ /* Char 108: 'l' */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0x44, /*= [ * ] */ +@@ -972,7 +972,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 109: 'm' */ ++ /*{*/ /* Char 109: 'm' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ +@@ -980,7 +980,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 110: 'n' */ ++ /*{*/ /* Char 110: 'n' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ +@@ -988,7 +988,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 111: 'o' */ ++ /*{*/ /* Char 111: 'o' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ +@@ -996,7 +996,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 112: 'p' */ ++ /*{*/ /* Char 112: 'p' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ +@@ -1004,7 +1004,7 @@ + 0xcc, /*= [** ] */ + 0x88, /*= [* ] */ + /*}*/ +- /*{*/ /* Char 113: 'q' */ ++ /*{*/ /* Char 113: 'q' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ +@@ -1012,7 +1012,7 @@ + 0x66, /*= [ ** ] */ + 0x22, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 114: 'r' */ ++ /*{*/ /* Char 114: 'r' */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0xaa, /*= [* * ] */ +@@ -1020,7 +1020,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 115: 's' */ ++ /*{*/ /* Char 115: 's' */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ +@@ -1028,7 +1028,7 @@ + 0xcc, /*= [** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 116: 't' */ ++ /*{*/ /* Char 116: 't' */ + 0x00, /*= [ ] */ + 0x44, /*= [ * ] */ + 0xee, /*= [*** ] */ +@@ -1036,7 +1036,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 117: 'u' */ ++ /*{*/ /* Char 117: 'u' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ +@@ -1044,7 +1044,7 @@ + 0x66, /*= [ ** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 118: 'v' */ ++ /*{*/ /* Char 118: 'v' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ +@@ -1052,7 +1052,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 119: 'w' */ ++ /*{*/ /* Char 119: 'w' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ +@@ -1060,7 +1060,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 120: 'x' */ ++ /*{*/ /* Char 120: 'x' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ +@@ -1068,7 +1068,7 @@ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 121: 'y' */ ++ /*{*/ /* Char 121: 'y' */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xaa, /*= [* * ] */ +@@ -1076,7 +1076,7 @@ + 0x22, /*= [ * ] */ + 0xcc, /*= [** ] */ + /*}*/ +- /*{*/ /* Char 122: 'z' */ ++ /*{*/ /* Char 122: 'z' */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ + 0x66, /*= [ ** ] */ +@@ -1084,7 +1084,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 123: '{' */ ++ /*{*/ /* Char 123: '{' */ + 0x22, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ +@@ -1092,7 +1092,7 @@ + 0x22, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 124: '|' */ ++ /*{*/ /* Char 124: '|' */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -1100,7 +1100,7 @@ + 0x44, /*= [ * ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 125: '}' */ ++ /*{*/ /* Char 125: '}' */ + 0x88, /*= [* ] */ + 0x44, /*= [ * ] */ + 0x66, /*= [ ** ] */ +@@ -1108,7 +1108,7 @@ + 0x88, /*= [* ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 126: '~' */ ++ /*{*/ /* Char 126: '~' */ + 0x55, /*= [ * *] */ + 0xaa, /*= [* * ] */ + 0x00, /*= [ ] */ +@@ -1116,7 +1116,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 127: '' */ ++ /*{*/ /* Char 127: '' */ + 0x44, /*= [ * ] */ + 0xaa, /*= [* * ] */ + 0xaa, /*= [* * ] */ +@@ -1124,7 +1124,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 128: */ ++ /*{*/ /* Char 128: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1132,7 +1132,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 129: */ ++ /*{*/ /* Char 129: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1140,7 +1140,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 130: */ ++ /*{*/ /* Char 130: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1148,7 +1148,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 131: */ ++ /*{*/ /* Char 131: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1156,7 +1156,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 132: */ ++ /*{*/ /* Char 132: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1164,7 +1164,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 133: */ ++ /*{*/ /* Char 133: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1172,7 +1172,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 134: */ ++ /*{*/ /* Char 134: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1180,7 +1180,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 135: */ ++ /*{*/ /* Char 135: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1188,7 +1188,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 136: */ ++ /*{*/ /* Char 136: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1196,7 +1196,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 137: */ ++ /*{*/ /* Char 137: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1204,7 +1204,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 138: */ ++ /*{*/ /* Char 138: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1212,7 +1212,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 139: */ ++ /*{*/ /* Char 139: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1220,7 +1220,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 140: */ ++ /*{*/ /* Char 140: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1228,7 +1228,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 141: */ ++ /*{*/ /* Char 141: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1236,7 +1236,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 142: */ ++ /*{*/ /* Char 142: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1244,7 +1244,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 143: */ ++ /*{*/ /* Char 143: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1252,7 +1252,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 144: */ ++ /*{*/ /* Char 144: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1260,7 +1260,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 145: */ ++ /*{*/ /* Char 145: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1268,7 +1268,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 146: */ ++ /*{*/ /* Char 146: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1276,7 +1276,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 147: */ ++ /*{*/ /* Char 147: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1284,7 +1284,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 148: */ ++ /*{*/ /* Char 148: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1292,7 +1292,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 149: */ ++ /*{*/ /* Char 149: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1300,7 +1300,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 150: */ ++ /*{*/ /* Char 150: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1308,7 +1308,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 151: */ ++ /*{*/ /* Char 151: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1316,7 +1316,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 152: */ ++ /*{*/ /* Char 152: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1324,7 +1324,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 153: */ ++ /*{*/ /* Char 153: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1332,7 +1332,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 154: */ ++ /*{*/ /* Char 154: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1340,7 +1340,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 155: */ ++ /*{*/ /* Char 155: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1348,7 +1348,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 156: */ ++ /*{*/ /* Char 156: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1356,7 +1356,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 157: */ ++ /*{*/ /* Char 157: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1364,7 +1364,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 158: */ ++ /*{*/ /* Char 158: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1372,7 +1372,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 159: */ ++ /*{*/ /* Char 159: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1380,7 +1380,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 160: */ ++ /*{*/ /* Char 160: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1388,7 +1388,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 161: */ ++ /*{*/ /* Char 161: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1396,7 +1396,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 162: */ ++ /*{*/ /* Char 162: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1404,7 +1404,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 163: */ ++ /*{*/ /* Char 163: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1412,7 +1412,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 164: */ ++ /*{*/ /* Char 164: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1420,7 +1420,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 165: */ ++ /*{*/ /* Char 165: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1428,7 +1428,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 166: */ ++ /*{*/ /* Char 166: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1436,7 +1436,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 167: */ ++ /*{*/ /* Char 167: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1444,7 +1444,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 168: */ ++ /*{*/ /* Char 168: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1452,7 +1452,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 169: */ ++ /*{*/ /* Char 169: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1460,7 +1460,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 170: */ ++ /*{*/ /* Char 170: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1468,7 +1468,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 171: */ ++ /*{*/ /* Char 171: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1476,7 +1476,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 172: */ ++ /*{*/ /* Char 172: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1484,7 +1484,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 173: */ ++ /*{*/ /* Char 173: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1492,7 +1492,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 174: */ ++ /*{*/ /* Char 174: */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ + 0xcc, /*= [** ] */ +@@ -1500,7 +1500,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 175: */ ++ /*{*/ /* Char 175: */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ + 0x66, /*= [ ** ] */ +@@ -1508,7 +1508,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 176: */ ++ /*{*/ /* Char 176: */ + 0x88, /*= [* ] */ + 0x22, /*= [ * ] */ + 0x88, /*= [* ] */ +@@ -1516,7 +1516,7 @@ + 0x88, /*= [* ] */ + 0x22, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 177: */ ++ /*{*/ /* Char 177: */ + 0xaa, /*= [* * ] */ + 0x55, /*= [ * *] */ + 0xaa, /*= [* * ] */ +@@ -1524,7 +1524,7 @@ + 0xaa, /*= [* * ] */ + 0x55, /*= [ * *] */ + /*}*/ +- /*{*/ /* Char 178: */ ++ /*{*/ /* Char 178: */ + 0xdd, /*= [** *] */ + 0xbb, /*= [* **] */ + 0xdd, /*= [** *] */ +@@ -1532,7 +1532,7 @@ + 0xdd, /*= [** *] */ + 0xbb, /*= [* **] */ + /*}*/ +- /*{*/ /* Char 179: */ ++ /*{*/ /* Char 179: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ +@@ -1540,7 +1540,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 180: */ ++ /*{*/ /* Char 180: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ +@@ -1548,7 +1548,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 181: */ ++ /*{*/ /* Char 181: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ +@@ -1556,7 +1556,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 182: */ ++ /*{*/ /* Char 182: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ +@@ -1564,7 +1564,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 183: */ ++ /*{*/ /* Char 183: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ +@@ -1572,7 +1572,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 184: */ ++ /*{*/ /* Char 184: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ +@@ -1580,7 +1580,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 185: */ ++ /*{*/ /* Char 185: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ +@@ -1588,7 +1588,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 186: */ ++ /*{*/ /* Char 186: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ +@@ -1596,7 +1596,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 187: */ ++ /*{*/ /* Char 187: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xee, /*= [*** ] */ +@@ -1604,7 +1604,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 188: */ ++ /*{*/ /* Char 188: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ +@@ -1612,7 +1612,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 189: */ ++ /*{*/ /* Char 189: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xee, /*= [*** ] */ +@@ -1620,7 +1620,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 190: */ ++ /*{*/ /* Char 190: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ +@@ -1628,7 +1628,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 191: */ ++ /*{*/ /* Char 191: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xcc, /*= [** ] */ +@@ -1636,7 +1636,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 192: */ ++ /*{*/ /* Char 192: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ +@@ -1644,7 +1644,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 193: */ ++ /*{*/ /* Char 193: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ +@@ -1652,7 +1652,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 194: */ ++ /*{*/ /* Char 194: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1660,7 +1660,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 195: */ ++ /*{*/ /* Char 195: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ +@@ -1668,7 +1668,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 196: */ ++ /*{*/ /* Char 196: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1676,7 +1676,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 197: */ ++ /*{*/ /* Char 197: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ +@@ -1684,7 +1684,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 198: */ ++ /*{*/ /* Char 198: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ +@@ -1692,7 +1692,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 199: */ ++ /*{*/ /* Char 199: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ +@@ -1700,7 +1700,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 200: */ ++ /*{*/ /* Char 200: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ +@@ -1708,7 +1708,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 201: */ ++ /*{*/ /* Char 201: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ +@@ -1716,7 +1716,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 202: */ ++ /*{*/ /* Char 202: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ +@@ -1724,7 +1724,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 203: */ ++ /*{*/ /* Char 203: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1732,7 +1732,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 204: */ ++ /*{*/ /* Char 204: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ +@@ -1740,7 +1740,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 205: */ ++ /*{*/ /* Char 205: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1748,7 +1748,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 206: */ ++ /*{*/ /* Char 206: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ +@@ -1756,7 +1756,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 207: */ ++ /*{*/ /* Char 207: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ +@@ -1764,7 +1764,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 208: */ ++ /*{*/ /* Char 208: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ +@@ -1772,7 +1772,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 209: */ ++ /*{*/ /* Char 209: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1780,7 +1780,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 210: */ ++ /*{*/ /* Char 210: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0xff, /*= [****] */ +@@ -1788,7 +1788,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 211: */ ++ /*{*/ /* Char 211: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0x77, /*= [ ***] */ +@@ -1796,7 +1796,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 212: */ ++ /*{*/ /* Char 212: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0x77, /*= [ ***] */ +@@ -1804,7 +1804,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 213: */ ++ /*{*/ /* Char 213: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ +@@ -1812,7 +1812,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 214: */ ++ /*{*/ /* Char 214: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ +@@ -1820,7 +1820,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 215: */ ++ /*{*/ /* Char 215: */ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + 0xff, /*= [****] */ +@@ -1828,7 +1828,7 @@ + 0x66, /*= [ ** ] */ + 0x66, /*= [ ** ] */ + /*}*/ +- /*{*/ /* Char 216: */ ++ /*{*/ /* Char 216: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xff, /*= [****] */ +@@ -1836,7 +1836,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 217: */ ++ /*{*/ /* Char 217: */ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + 0xcc, /*= [** ] */ +@@ -1844,7 +1844,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 218: */ ++ /*{*/ /* Char 218: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x77, /*= [ ***] */ +@@ -1852,7 +1852,7 @@ + 0x44, /*= [ * ] */ + 0x44, /*= [ * ] */ + /*}*/ +- /*{*/ /* Char 219: */ ++ /*{*/ /* Char 219: */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ +@@ -1860,7 +1860,7 @@ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + /*}*/ +- /*{*/ /* Char 220: */ ++ /*{*/ /* Char 220: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ +@@ -1868,7 +1868,7 @@ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + /*}*/ +- /*{*/ /* Char 221: */ ++ /*{*/ /* Char 221: */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ +@@ -1876,7 +1876,7 @@ + 0xcc, /*= [** ] */ + 0xcc, /*= [** ] */ + /*}*/ +- /*{*/ /* Char 222: */ ++ /*{*/ /* Char 222: */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ +@@ -1884,7 +1884,7 @@ + 0x33, /*= [ **] */ + 0x33, /*= [ **] */ + /*}*/ +- /*{*/ /* Char 223: */ ++ /*{*/ /* Char 223: */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ + 0xff, /*= [****] */ +@@ -1892,7 +1892,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 224: */ ++ /*{*/ /* Char 224: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1900,7 +1900,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 225: */ ++ /*{*/ /* Char 225: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1908,7 +1908,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 226: */ ++ /*{*/ /* Char 226: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1916,7 +1916,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 227: */ ++ /*{*/ /* Char 227: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1924,7 +1924,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 228: */ ++ /*{*/ /* Char 228: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1932,7 +1932,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 229: */ ++ /*{*/ /* Char 229: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1940,7 +1940,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 230: */ ++ /*{*/ /* Char 230: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1948,7 +1948,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 231: */ ++ /*{*/ /* Char 231: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1956,7 +1956,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 232: */ ++ /*{*/ /* Char 232: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1964,7 +1964,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 233: */ ++ /*{*/ /* Char 233: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1972,7 +1972,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 234: */ ++ /*{*/ /* Char 234: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1980,7 +1980,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 235: */ ++ /*{*/ /* Char 235: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1988,7 +1988,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 236: */ ++ /*{*/ /* Char 236: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -1996,7 +1996,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 237: */ ++ /*{*/ /* Char 237: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2004,7 +2004,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 238: */ ++ /*{*/ /* Char 238: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2012,7 +2012,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 239: */ ++ /*{*/ /* Char 239: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2020,7 +2020,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 240: */ ++ /*{*/ /* Char 240: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2028,7 +2028,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 241: */ ++ /*{*/ /* Char 241: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2036,7 +2036,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 242: */ ++ /*{*/ /* Char 242: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2044,7 +2044,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 243: */ ++ /*{*/ /* Char 243: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2052,7 +2052,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 244: */ ++ /*{*/ /* Char 244: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2060,7 +2060,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 245: */ ++ /*{*/ /* Char 245: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2068,7 +2068,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 246: */ ++ /*{*/ /* Char 246: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2076,7 +2076,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 247: */ ++ /*{*/ /* Char 247: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2084,7 +2084,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 248: */ ++ /*{*/ /* Char 248: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2092,7 +2092,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 249: */ ++ /*{*/ /* Char 249: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2100,7 +2100,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 250: */ ++ /*{*/ /* Char 250: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2108,7 +2108,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 251: */ ++ /*{*/ /* Char 251: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2116,7 +2116,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 252: */ ++ /*{*/ /* Char 252: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2124,7 +2124,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 253: */ ++ /*{*/ /* Char 253: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +@@ -2132,7 +2132,7 @@ + 0xee, /*= [*** ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 254: */ ++ /*{*/ /* Char 254: */ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + 0x66, /*= [ ** ] */ +@@ -2140,7 +2140,7 @@ + 0x00, /*= [ ] */ + 0x00, /*= [ ] */ + /*}*/ +- /*{*/ /* Char 255: */ ++ /*{*/ /* Char 255: */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ + 0xee, /*= [*** ] */ +diff -ruN u-boot-2021.10/include/wdt.h u-boot/include/wdt.h +--- u-boot-2021.10/include/wdt.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/include/wdt.h 2021-11-01 17:10:14.682902849 +0100 +@@ -38,6 +38,14 @@ + int wdt_stop(struct udevice *dev); + + /* ++ * Stop all registered watchdog devices. ++ * ++ * @return: 0 if ok, first error encountered otherwise (but wdt_stop() ++ * is still called on following devices) ++ */ ++int wdt_stop_all(void); ++ ++/* + * Reset the timer, typically restoring the counter to + * the value configured by start() + * +diff -ruN u-boot-2021.10/Kconfig u-boot/Kconfig +--- u-boot-2021.10/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/Kconfig 2021-11-01 17:10:13.536298895 +0100 +@@ -12,6 +12,8 @@ + # Allow defaults in arch-specific code to override any given here + source "arch/Kconfig" + ++source "board/sunxi/Kconfig" ++ + menu "General setup" + + config BROKEN +@@ -83,7 +85,6 @@ + + config OPTIMIZE_INLINING + bool "Allow compiler to uninline functions marked 'inline' in full U-Boot" +- default n + help + This option determines if U-Boot forces gcc to inline the functions + developers have marked 'inline'. Doing so takes away freedom from gcc to +@@ -93,7 +94,6 @@ + config SPL_OPTIMIZE_INLINING + bool "Allow compiler to uninline functions marked 'inline' in SPL" + depends on SPL +- default n + help + This option determines if U-Boot forces gcc to inline the functions + developers have marked 'inline'. Doing so takes away freedom from gcc to +@@ -106,7 +106,6 @@ + config LTO + bool "Enable Link Time Optimizations" + depends on ARCH_SUPPORTS_LTO +- default n + help + This option enables Link Time Optimization (LTO), a mechanism which + allows the compiler to optimize between different compilation units. +@@ -127,7 +126,6 @@ + config TPL_OPTIMIZE_INLINING + bool "Allow compiler to uninline functions marked 'inline' in TPL" + depends on TPL +- default n + help + This option determines if U-Boot forces gcc to inline the functions + developers have marked 'inline'. Doing so takes away freedom from gcc to +@@ -239,7 +237,7 @@ + default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ + ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ + ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ +- ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL) ++ ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL || TARGET_SUNXI) + default 0x400 + help + Before relocation, memory is very limited on many platforms. Still, +@@ -249,8 +247,11 @@ + + config SYS_MALLOC_LEN + hex "Define memory for Dynamic allocation" +- depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP +- default 0x2000000 if ARCH_ROCKCHIP ++ default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON ++ default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S ++ default 0x200000 if ARCH_BMIPS || X86 ++ default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S ++ default 0x400000 + help + This defines memory to be allocated for Dynamic allocation + TODO: Use for other architectures +@@ -307,7 +308,6 @@ + + config SYS_MALLOC_DEFAULT_TO_INIT + bool "Default malloc to init while reserving the memory for it" +- default n + help + It may happen that one needs to move the dynamic allocation + from one to another memory range, eg. when moving the malloc +@@ -389,6 +389,20 @@ + Path within the source tree to the linker script to use for the + main U-Boot binary. + ++config SYS_LOAD_ADDR ++ hex "Address in memory to use by default" ++ default 0x01000000 if ARCH_SOCFPGA ++ default 0x02000000 if PPC || X86 ++ default 0x22000000 if MACH_SUN9I ++ default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I ++ default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 ++ default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) ++ default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) ++ default 0x80800000 if ARCH_MX7 ++ default 0x90000000 if FSL_LSCH2 || FSL_LSCH3 ++ help ++ Address in memory to use as the default safe load address. ++ + config ERR_PTR_OFFSET + hex + default 0x0 +@@ -423,7 +437,6 @@ + default y if TARGET_PIC32MZDASK + default y if TARGET_DEVKIT8000 + default y if TARGET_TRICORDER +- default n + help + Enable this to allow support for the on board SRAM. + SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. +diff -ruN u-boot-2021.10/lib/acpi/acpi_table.c u-boot/lib/acpi/acpi_table.c +--- u-boot-2021.10/lib/acpi/acpi_table.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/acpi/acpi_table.c 2021-11-01 17:10:14.686236000 +0100 +@@ -11,11 +11,28 @@ + #include <log.h> + #include <mapmem.h> + #include <tables_csum.h> ++#include <timestamp.h> + #include <version.h> + #include <acpi/acpi_table.h> + #include <asm/global_data.h> + #include <dm/acpi.h> + ++/* ++ * OEM_REVISION is 32-bit unsigned number. It should be increased only when ++ * changing software version. Therefore it should not depend on build time. ++ * U-Boot calculates it from U-Boot version and represent it in hexadecimal ++ * notation. As U-Boot version is in form year.month set low 8 bits to 0x01 ++ * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to ++ * value 0x20210401. ++ */ ++#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ ++ (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ ++ (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ ++ ((U_BOOT_VERSION_NUM % 10) << 16) | \ ++ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ ++ ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ ++ 0x01) ++ + int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) + { + struct acpi_table_header *header = &dmar->header; +@@ -100,7 +117,7 @@ + memcpy(header->signature, signature, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); +- header->oem_revision = U_BOOT_BUILD_DATE; ++ header->oem_revision = OEM_REVISION; + memcpy(header->aslc_id, ASLC_ID, 4); + } + +diff -ruN u-boot-2021.10/lib/crc32.c u-boot/lib/crc32.c +--- u-boot-2021.10/lib/crc32.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/crc32.c 2021-11-01 17:10:14.689569151 +0100 +@@ -84,7 +84,7 @@ + } + crc_table_empty = 0; + } +-#else ++#elif !defined(CONFIG_ARM64_CRC32) + /* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ +@@ -184,6 +184,12 @@ + */ + uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) + { ++#ifdef CONFIG_ARM64_CRC32 ++ crc = cpu_to_le32(crc); ++ while (len--) ++ crc = __builtin_aarch64_crc32b(crc, *buf++); ++ return le32_to_cpu(crc); ++#else + const uint32_t *tab = crc_table; + const uint32_t *b =(const uint32_t *)buf; + size_t rem_len; +@@ -221,6 +227,7 @@ + } + + return le32_to_cpu(crc); ++#endif + } + #undef DO_CRC + +diff -ruN u-boot-2021.10/lib/display_options.c u-boot/lib/display_options.c +--- u-boot-2021.10/lib/display_options.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/display_options.c 2021-11-01 17:10:14.692902302 +0100 +@@ -8,7 +8,7 @@ + #include <compiler.h> + #include <console.h> + #include <div64.h> +-#include <version.h> ++#include <version_string.h> + #include <linux/ctype.h> + #include <asm/io.h> + +diff -ruN u-boot-2021.10/lib/efi_loader/efi_tcg2.c u-boot/lib/efi_loader/efi_tcg2.c +--- u-boot-2021.10/lib/efi_loader/efi_tcg2.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/efi_loader/efi_tcg2.c 2021-11-01 17:10:14.699568604 +0100 +@@ -14,7 +14,7 @@ + #include <efi_tcg2.h> + #include <log.h> + #include <malloc.h> +-#include <version.h> ++#include <version_string.h> + #include <tpm-v2.h> + #include <u-boot/hash-checksum.h> + #include <u-boot/sha1.h> +@@ -1343,10 +1343,11 @@ + */ + static efi_status_t efi_append_scrtm_version(struct udevice *dev) + { +- u8 ver[] = U_BOOT_VERSION_STRING; + efi_status_t ret; + +- ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, sizeof(ver), ver); ++ ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, ++ strlen(version_string) + 1, ++ (u8 *)version_string); + + return ret; + } +diff -ruN u-boot-2021.10/lib/efi_loader/Kconfig u-boot/lib/efi_loader/Kconfig +--- u-boot-2021.10/lib/efi_loader/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/efi_loader/Kconfig 2021-11-01 17:10:14.692902302 +0100 +@@ -39,7 +39,6 @@ + + config EFI_SETUP_EARLY + bool +- default n + + choice + prompt "Store for non-volatile UEFI variables" +@@ -113,7 +112,6 @@ + bool "SetTime() runtime service" + depends on EFI_GET_TIME + default y if ARCH_QEMU || SANDBOX +- default n + help + Provide the SetTime() runtime service at boottime. This service + can be used by an EFI application to adjust the real time clock. +@@ -123,7 +121,6 @@ + + config EFI_RUNTIME_UPDATE_CAPSULE + bool "UpdateCapsule() runtime service" +- default n + select EFI_HAVE_CAPSULE_SUPPORT + help + Select this option if you want to use UpdateCapsule and +@@ -132,7 +129,6 @@ + config EFI_CAPSULE_ON_DISK + bool "Enable capsule-on-disk support" + select EFI_HAVE_CAPSULE_SUPPORT +- default n + help + Select this option if you want to use capsule-on-disk feature, + that is, capsules can be fetched and executed from files +@@ -142,7 +138,6 @@ + config EFI_IGNORE_OSINDICATIONS + bool "Ignore OsIndications for CapsuleUpdate on-disk" + depends on EFI_CAPSULE_ON_DISK +- default n + help + There are boards where U-Boot does not support SetVariable at runtime. + Select this option if you want to use the capsule-on-disk feature +@@ -152,7 +147,6 @@ + config EFI_CAPSULE_ON_DISK_EARLY + bool "Initiate capsule-on-disk at U-Boot boottime" + depends on EFI_CAPSULE_ON_DISK +- default n + select EFI_SETUP_EARLY + help + Normally, without this option enabled, capsules will be +@@ -163,7 +157,6 @@ + + config EFI_CAPSULE_FIRMWARE + bool +- default n + + config EFI_CAPSULE_FIRMWARE_MANAGEMENT + bool "Capsule: Firmware Management Protocol" +@@ -210,7 +203,6 @@ + select PKCS7_VERIFY + select IMAGE_SIGN_INFO + select EFI_SIGNATURE_SUPPORT +- default n + help + Select this option if you want to enable capsule + authentication +@@ -271,7 +263,6 @@ + config EFI_LOADER_BOUNCE_BUFFER + bool "EFI Applications use bounce buffers for DMA operations" + depends on ARM64 +- default n + help + Some hardware does not support DMA to full 64bit addresses. For this + hardware we can create a bounce buffer so that payloads don't have to +@@ -357,7 +348,6 @@ + select PKCS7_MESSAGE_PARSER + select PKCS7_VERIFY + select EFI_SIGNATURE_SUPPORT +- default n + help + Select this option to enable EFI secure boot support. + Once SecureBoot mode is enforced, any EFI binary can run only if +diff -ruN u-boot-2021.10/lib/fdtdec.c u-boot/lib/fdtdec.c +--- u-boot-2021.10/lib/fdtdec.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/fdtdec.c 2021-11-01 17:10:14.702901755 +0100 +@@ -870,50 +870,6 @@ + return cell; + } + +-int fdtdec_get_config_int(const void *blob, const char *prop_name, +- int default_val) +-{ +- int config_node; +- +- debug("%s: %s\n", __func__, prop_name); +- config_node = fdt_path_offset(blob, "/config"); +- if (config_node < 0) +- return default_val; +- return fdtdec_get_int(blob, config_node, prop_name, default_val); +-} +- +-int fdtdec_get_config_bool(const void *blob, const char *prop_name) +-{ +- int config_node; +- const void *prop; +- +- debug("%s: %s\n", __func__, prop_name); +- config_node = fdt_path_offset(blob, "/config"); +- if (config_node < 0) +- return 0; +- prop = fdt_get_property(blob, config_node, prop_name, NULL); +- +- return prop != NULL; +-} +- +-char *fdtdec_get_config_string(const void *blob, const char *prop_name) +-{ +- const char *nodep; +- int nodeoffset; +- int len; +- +- debug("%s: %s\n", __func__, prop_name); +- nodeoffset = fdt_path_offset(blob, "/config"); +- if (nodeoffset < 0) +- return NULL; +- +- nodep = fdt_getprop(blob, nodeoffset, prop_name, &len); +- if (!nodep) +- return NULL; +- +- return (char *)nodep; +-} +- + u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells) + { + u64 number = 0; +diff -ruN u-boot-2021.10/lib/hang.c u-boot/lib/hang.c +--- u-boot-2021.10/lib/hang.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/hang.c 2021-11-01 17:10:14.702901755 +0100 +@@ -24,7 +24,7 @@ + { + #if !defined(CONFIG_SPL_BUILD) || \ + (CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \ +- CONFIG_IS_ENABLED(SERIAL_SUPPORT)) ++ CONFIG_IS_ENABLED(SERIAL)) + puts("### ERROR ### Please RESET the board ###\n"); + #endif + bootstage_error(BOOTSTAGE_ID_NEED_RESET); +diff -ruN u-boot-2021.10/lib/Kconfig u-boot/lib/Kconfig +--- u-boot-2021.10/lib/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/Kconfig 2021-11-01 17:10:14.686236000 +0100 +@@ -92,7 +92,6 @@ + + config SSCANF + bool +- default n + + config STRTO + bool +@@ -348,7 +347,6 @@ + config LIBAVB + bool "Android Verified Boot 2.0 support" + depends on ANDROID_BOOT_IMAGE +- default n + help + This enables support of Android Verified Boot 2.0 which can be used + to assure the end user of the integrity of the software running on a +@@ -769,7 +767,6 @@ + + config PHANDLE_CHECK_SEQ + bool "Enable phandle check while getting sequence number" +- default n + help + When there are multiple device tree nodes with same name, + enable this config option to distinguish them using +diff -ruN u-boot-2021.10/lib/lmb.c u-boot/lib/lmb.c +--- u-boot-2021.10/lib/lmb.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/lmb.c 2021-11-01 17:10:14.706234906 +0100 +@@ -12,6 +12,10 @@ + #include <log.h> + #include <malloc.h> + ++#include <asm/global_data.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ + #define LMB_ALLOC_ANYWHERE 0 + + static void lmb_dump_region(struct lmb_region *rgn, char *name) +@@ -113,6 +117,37 @@ + lmb->reserved.cnt = 0; + } + ++void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align) ++{ ++ ulong bank_end; ++ int bank; ++ ++ /* ++ * Reserve memory from aligned address below the bottom of U-Boot stack ++ * until end of U-Boot area using LMB to prevent U-Boot from overwriting ++ * that memory. ++ */ ++ debug("## Current stack ends at 0x%08lx ", sp); ++ ++ /* adjust sp by 4K to be safe */ ++ sp -= align; ++ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { ++ if (!gd->bd->bi_dram[bank].size || ++ sp < gd->bd->bi_dram[bank].start) ++ continue; ++ /* Watch out for RAM at end of address space! */ ++ bank_end = gd->bd->bi_dram[bank].start + ++ gd->bd->bi_dram[bank].size - 1; ++ if (sp > bank_end) ++ continue; ++ if (bank_end > end) ++ bank_end = end - 1; ++ ++ lmb_reserve(lmb, sp, bank_end - sp + 1); ++ break; ++ } ++} ++ + static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob) + { + arch_lmb_reserve(lmb); +diff -ruN u-boot-2021.10/lib/Makefile u-boot/lib/Makefile +--- u-boot-2021.10/lib/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/Makefile 2021-11-01 17:10:14.686236000 +0100 +@@ -16,7 +16,7 @@ + obj-$(CONFIG_OF_LIVE) += of_live.o + obj-$(CONFIG_CMD_DHRYSTONE) += dhry/ + obj-$(CONFIG_ARCH_AT91) += at91/ +-obj-$(CONFIG_OPTEE) += optee/ ++obj-$(CONFIG_OPTEE_LIB) += optee/ + obj-$(CONFIG_ASN1_DECODER) += asn1_decoder.o + obj-y += crypto/ + +@@ -80,14 +80,12 @@ + obj-$(CONFIG_LIBAVB) += libavb/ + + obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ +-ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) +-obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o +-obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o +-endif ++obj-$(CONFIG_$(SPL_TPL_)OF_REAL) += fdtdec_common.o fdtdec.o + + ifdef CONFIG_SPL_BUILD + obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o + obj-$(CONFIG_$(SPL_TPL_)HASH) += crc16.o ++obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16.o + obj-y += net_utils.o + endif + obj-$(CONFIG_ADDR_MAP) += addr_map.o +diff -ruN u-boot-2021.10/lib/md5.c u-boot/lib/md5.c +--- u-boot-2021.10/lib/md5.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/md5.c 2021-11-01 17:10:14.706234906 +0100 +@@ -55,7 +55,7 @@ + * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious + * initialization constants. + */ +-static void ++void + MD5Init(struct MD5Context *ctx) + { + ctx->buf[0] = 0x67452301; +@@ -71,7 +71,7 @@ + * Update context to reflect the concatenation of another buffer full + * of bytes. + */ +-static void ++void + MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len) + { + register __u32 t; +@@ -120,7 +120,7 @@ + * Final wrapup - pad to 64-byte boundary with the bit pattern + * 1 0* (64-bit count of bits processed, MSB-first) + */ +-static void ++void + MD5Final(unsigned char digest[16], struct MD5Context *ctx) + { + unsigned int count; +diff -ruN u-boot-2021.10/lib/optee/Kconfig u-boot/lib/optee/Kconfig +--- u-boot-2021.10/lib/optee/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/optee/Kconfig 2021-11-01 17:10:14.709568057 +0100 +@@ -1,40 +1,20 @@ +-config OPTEE +- bool "Support OPTEE images" +- help +- U-Boot can be configured to boot OPTEE images. +- Selecting this option will enable shared OPTEE library code and +- enable an OPTEE specific bootm command that will perform additional +- OPTEE specific checks before booting an OPTEE image created with +- mkimage. +- +-config OPTEE_LOAD_ADDR +- hex "OPTEE load address" +- default 0x00000000 +- depends on OPTEE ++config OPTEE_LIB ++ bool "Support OPTEE library" ++ default y if OPTEE || OPTEE_IMAGE + help +- The load address of the bootable OPTEE binary. ++ Selecting this option will enable the shared OPTEE library code. + +-config OPTEE_TZDRAM_SIZE +- hex "Amount of Trust-Zone RAM for the OPTEE image" +- default 0x0000000 +- depends on OPTEE +- help +- The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE +- runtime. +- +-config OPTEE_TZDRAM_BASE +- hex "Base address of Trust-Zone RAM for the OPTEE image" +- default 0x00000000 +- depends on OPTEE ++config OPTEE_IMAGE ++ bool "Support OPTEE images" + help +- The base address of pre-allocated Trust Zone DRAM for +- the OPTEE runtime. ++ Selecting this option to boot OPTEE images. ++ This option enable the OPTEE specific checks done before booting ++ an OPTEE image created with mkimage + + config BOOTM_OPTEE + bool "Support OPTEE bootm command" + select BOOTM_LINUX +- depends on OPTEE +- default n ++ select OPTEE_IMAGE + help + Select this command to enable chain-loading of a Linux kernel + via an OPTEE firmware. +diff -ruN u-boot-2021.10/lib/optee/Makefile u-boot/lib/optee/Makefile +--- u-boot-2021.10/lib/optee/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/optee/Makefile 2021-11-01 17:10:14.709568057 +0100 +@@ -2,4 +2,4 @@ + # + # (C) Copyright 2017 Linaro + +-obj-$(CONFIG_OPTEE) += optee.o ++obj-y += optee.o +diff -ruN u-boot-2021.10/lib/optee/optee.c u-boot/lib/optee/optee.c +--- u-boot-2021.10/lib/optee/optee.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/optee/optee.c 2021-11-01 17:10:14.709568057 +0100 +@@ -16,14 +16,13 @@ + + #define optee_hdr_err_msg \ + "OPTEE verification error:" \ +- "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx " \ ++ "\n\thdr=%p image=0x%08lx magic=0x%08x" \ + "\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x" \ + "\n\tuimage params 0x%08lx-0x%08lx\n" + +-int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start, +- unsigned long tzdram_len, unsigned long image_len) ++#if defined(CONFIG_OPTEE_IMAGE) ++static int optee_verify_image(struct optee_header *hdr, unsigned long image_len) + { +- unsigned long tzdram_end = tzdram_start + tzdram_len; + uint32_t tee_file_size; + + tee_file_size = hdr->init_size + hdr->paged_size + +@@ -31,11 +30,7 @@ + + if (hdr->magic != OPTEE_MAGIC || + hdr->version != OPTEE_VERSION || +- hdr->init_load_addr_hi > tzdram_end || +- hdr->init_load_addr_lo < tzdram_start || +- tee_file_size > tzdram_len || +- tee_file_size != image_len || +- (hdr->init_load_addr_lo + tee_file_size) > tzdram_end) { ++ tee_file_size != image_len) { + return -EINVAL; + } + +@@ -47,12 +42,9 @@ + unsigned long image_len) + { + struct optee_header *hdr = (struct optee_header *)image_addr; +- unsigned long tzdram_start = CONFIG_OPTEE_TZDRAM_BASE; +- unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE; +- + int ret; + +- ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len); ++ ret = optee_verify_image(hdr, image_len); + if (ret) + goto error; + +@@ -63,13 +55,14 @@ + + return ret; + error: +- printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, tzdram_start, +- tzdram_start + tzdram_len, hdr->init_load_addr_lo, ++ printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, ++ hdr->init_load_addr_lo, + hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr, + image_load_addr + image_len); + + return ret; + } ++#endif + + #if defined(CONFIG_OF_LIBFDT) + static int optee_copy_firmware_node(ofnode node, void *fdt_blob) +diff -ruN u-boot-2021.10/lib/rsa/Kconfig u-boot/lib/rsa/Kconfig +--- u-boot-2021.10/lib/rsa/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/rsa/Kconfig 2021-11-01 17:10:14.709568057 +0100 +@@ -20,6 +20,7 @@ + + config SPL_RSA_VERIFY + bool ++ depends on SPL_RSA + help + Add RSA signature verification support in SPL. + +diff -ruN u-boot-2021.10/lib/rsa/rsa-sign.c u-boot/lib/rsa/rsa-sign.c +--- u-boot-2021.10/lib/rsa/rsa-sign.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/rsa/rsa-sign.c 2021-11-01 17:10:14.709568057 +0100 +@@ -19,24 +19,6 @@ + #include <openssl/evp.h> + #include <openssl/engine.h> + +-#if OPENSSL_VERSION_NUMBER >= 0x10000000L +-#define HAVE_ERR_REMOVE_THREAD_STATE +-#endif +- +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +-static void RSA_get0_key(const RSA *r, +- const BIGNUM **n, const BIGNUM **e, const BIGNUM **d) +-{ +- if (n != NULL) +- *n = r->n; +- if (e != NULL) +- *e = r->e; +- if (d != NULL) +- *d = r->d; +-} +-#endif +- + static int rsa_err(const char *msg) + { + unsigned long sslErr = ERR_get_error(); +@@ -272,7 +254,7 @@ + else if (name) + snprintf(key_id, sizeof(key_id), + "%s", +- name); ++ name ? name : ""); + else if (keyfile) + snprintf(key_id, sizeof(key_id), "%s", keyfile); + else +@@ -314,24 +296,11 @@ + { + int ret; + +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- ret = SSL_library_init(); +-#else + ret = OPENSSL_init_ssl(0, NULL); +-#endif + if (!ret) { + fprintf(stderr, "Failure to init SSL library\n"); + return -1; + } +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- SSL_load_error_strings(); +- +- OpenSSL_add_all_algorithms(); +- OpenSSL_add_all_digests(); +- OpenSSL_add_all_ciphers(); +-#endif + + return 0; + } +@@ -347,8 +316,7 @@ + e = ENGINE_by_id(engine_id); + if (!e) { + fprintf(stderr, "Engine isn't available\n"); +- ret = -1; +- goto err_engine_by_id; ++ return -1; + } + + if (!ENGINE_init(e)) { +@@ -381,29 +349,9 @@ + ENGINE_finish(e); + err_engine_init: + ENGINE_free(e); +-err_engine_by_id: +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- ENGINE_cleanup(); +-#endif + return ret; + } + +-static void rsa_remove(void) +-{ +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- CRYPTO_cleanup_all_ex_data(); +- ERR_free_strings(); +-#ifdef HAVE_ERR_REMOVE_THREAD_STATE +- ERR_remove_thread_state(NULL); +-#else +- ERR_remove_state(0); +-#endif +- EVP_cleanup(); +-#endif +-} +- + static void rsa_engine_remove(ENGINE *e) + { + if (e) { +@@ -476,12 +424,7 @@ + goto err_sign; + } + +- #if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- EVP_MD_CTX_cleanup(context); +- #else +- EVP_MD_CTX_reset(context); +- #endif ++ EVP_MD_CTX_reset(context); + EVP_MD_CTX_destroy(context); + + debug("Got signature: %zu bytes, expected %d\n", size, EVP_PKEY_size(pkey)); +@@ -513,7 +456,7 @@ + if (info->engine_id) { + ret = rsa_engine_init(info->engine_id, &e); + if (ret) +- goto err_engine; ++ return ret; + } + + ret = rsa_get_priv_key(info->keydir, info->keyname, info->keyfile, +@@ -528,7 +471,6 @@ + EVP_PKEY_free(pkey); + if (info->engine_id) + rsa_engine_remove(e); +- rsa_remove(); + + return ret; + +@@ -537,8 +479,6 @@ + err_priv: + if (info->engine_id) + rsa_engine_remove(e); +-err_engine: +- rsa_remove(); + return ret; + } + +@@ -686,12 +626,8 @@ + ret = rsa_get_pub_key(info->keydir, info->keyname, e, &pkey); + if (ret) + goto err_get_pub_key; +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- rsa = EVP_PKEY_get1_RSA(pkey); +-#else ++ + rsa = EVP_PKEY_get0_RSA(pkey); +-#endif + ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); + if (ret) + goto err_get_params; +@@ -761,10 +697,6 @@ + if (ret) + ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; + err_get_params: +-#if OPENSSL_VERSION_NUMBER < 0x10100000L || \ +- (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) +- RSA_free(rsa); +-#endif + EVP_PKEY_free(pkey); + err_get_pub_key: + if (info->engine_id) +diff -ruN u-boot-2021.10/lib/tiny-printf.c u-boot/lib/tiny-printf.c +--- u-boot-2021.10/lib/tiny-printf.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/lib/tiny-printf.c 2021-11-01 17:10:14.709568057 +0100 +@@ -48,7 +48,7 @@ + out_dgt(info, dgt); + } + +-#ifdef CONFIG_SPL_NET_SUPPORT ++#ifdef CONFIG_SPL_NET + static void string(struct printf_info *info, char *s) + { + char ch; +@@ -178,7 +178,7 @@ + } + break; + #endif +-#ifdef CONFIG_SPL_NET_SUPPORT ++#ifdef CONFIG_SPL_NET + case 'm': + return mac_address_string(info, ptr, false); + case 'M': +@@ -270,7 +270,7 @@ + } + break; + case 'p': +- if (CONFIG_IS_ENABLED(NET_SUPPORT) || _DEBUG) { ++ if (CONFIG_IS_ENABLED(NET) || _DEBUG) { + pointer(info, fmt, va_arg(va, void *)); + /* + * Skip this because it pulls in _ctype which is +diff -ruN u-boot-2021.10/Licenses/lgpl-2.0.txt u-boot/Licenses/lgpl-2.0.txt +diff -ruN u-boot-2021.10/.mailmap u-boot/.mailmap +--- u-boot-2021.10/.mailmap 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/.mailmap 2021-11-01 17:10:13.536298895 +0100 +@@ -29,6 +29,7 @@ + Jagan Teki <jaganna@xilinx.com> + Jagan Teki <jagannadh.teki@gmail.com> + Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> ++Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net> + Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> + Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com> + Markus Klotzbuecher <mk@denx.de> +diff -ruN u-boot-2021.10/MAINTAINERS u-boot/MAINTAINERS +--- u-boot-2021.10/MAINTAINERS 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/MAINTAINERS 2021-11-01 17:10:13.539632046 +0100 +@@ -312,6 +312,7 @@ + F: board/atmel/ + F: drivers/cpu/at91_cpu.c + F: drivers/misc/microchip_flexcom.c ++F: include/dt-bindings/mfd/atmel-flexcom.h + F: drivers/timer/mchp-pit64b-timer.c + + ARM NEXELL S5P4418 +@@ -525,7 +526,12 @@ + S: Maintained + F: arch/arm/dts/ste-* + F: arch/arm/mach-u8500/ ++F: drivers/gpio/nmk_gpio.c ++F: drivers/phy/phy-ab8500-usb.c ++F: drivers/power/pmic/ab8500.c + F: drivers/timer/nomadik-mtu-timer.c ++F: drivers/usb/musb-new/ux500.c ++F: drivers/video/mcde_simple.c + + ARM UNIPHIER + S: Orphan (Since 2020-09) +@@ -769,6 +775,16 @@ + T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git + F: drivers/i2c/ + ++KWBIMAGE / KWBOOT TOOLS ++M: Pali Rohár <pali@kernel.org> ++M: Marek Behún <marek.behun@nic.cz> ++M: Stefan Roese <sr@denx.de> ++S: Maintained ++T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git ++F: doc/README.kwbimage ++F: doc/kwboot.1 ++F: tools/kwb* ++ + LOGGING + M: Simon Glass <sjg@chromium.org> + S: Maintained +@@ -1010,6 +1026,7 @@ + F: arch/riscv/ + F: cmd/riscv/ + F: doc/usage/sbi.rst ++F: drivers/sysreset/sysreset_sbi.c + F: drivers/timer/andes_plmt_timer.c + F: drivers/timer/sifive_clint_timer.c + F: tools/prelink-riscv.c +diff -ruN u-boot-2021.10/Makefile u-boot/Makefile +--- u-boot-2021.10/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/Makefile 2021-11-01 17:10:13.539632046 +0100 +@@ -327,14 +327,14 @@ + $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + + os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \ +- $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) ++ $(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;) + + # Snow Leopards build environment has no longer restrictions as described above + HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc") + KBUILD_HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") + KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") + +-# macOS Mojave (10.14.X) ++# macOS Mojave (10.14.X) + # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple" + KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "") + endif +@@ -813,23 +813,9 @@ + libs-y += net/ + libs-y += disk/ + libs-y += drivers/ +-libs-y += drivers/dma/ +-libs-y += drivers/gpio/ +-libs-y += drivers/net/ +-libs-y += drivers/net/phy/ +-libs-y += drivers/power/ \ +- drivers/power/domain/ \ +- drivers/power/fuel_gauge/ \ +- drivers/power/mfd/ \ +- drivers/power/pmic/ \ +- drivers/power/battery/ \ +- drivers/power/regulator/ +-libs-y += drivers/spi/ +-libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ + libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ + libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ + libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/ +-libs-y += drivers/serial/ + libs-y += drivers/usb/cdns3/ + libs-y += drivers/usb/dwc3/ + libs-y += drivers/usb/common/ +@@ -1306,10 +1292,6 @@ + # Use 'make BINMAN_VERBOSE=3' to set vebosity level + default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE)) + +-# Tell binman whether we have a devicetree for SPL and TPL +-have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL)) +-have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL)) +- + quiet_cmd_binman = BINMAN $@ + cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ + --toolpath $(objtree)/tools \ +@@ -1323,7 +1305,8 @@ + -a scp-path=$(SCP) \ + -a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \ + -a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \ +- -a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \ ++ -a spl-dtb=$(CONFIG_SPL_OF_REAL) \ ++ -a tpl-dtb=$(CONFIG_SPL_OF_REAL) \ + $(BINMAN_$(@F)) + + OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex +@@ -1756,7 +1739,7 @@ + # May be overridden by arch/$(ARCH)/config.mk + ifdef CONFIG_LTO + quiet_cmd_u-boot__ ?= LTO $@ +- cmd_u-boot__ ?= \ ++ cmd_u-boot__ ?= \ + $(CC) -nostdlib -nostartfiles \ + $(LTO_FINAL_LDFLAGS) $(c_flags) \ + $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \ +@@ -1907,7 +1890,6 @@ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ +- LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \ + else \ + return 42; \ +@@ -1916,7 +1898,6 @@ + LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ + LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ +- LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \ + fi) + endef +diff -ruN u-boot-2021.10/net/cdp.c u-boot/net/cdp.c +--- u-boot-2021.10/net/cdp.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/cdp.c 2021-11-01 17:10:14.719567510 +0100 +@@ -11,9 +11,6 @@ + + #include <common.h> + #include <net.h> +-#if defined(CONFIG_CDP_VERSION) +-#include <timestamp.h> +-#endif + + #include "cdp.h" + +diff -ruN u-boot-2021.10/net/dsa-uclass.c u-boot/net/dsa-uclass.c +--- u-boot-2021.10/net/dsa-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/dsa-uclass.c 2021-11-01 17:10:14.719567510 +0100 +@@ -100,7 +100,7 @@ + + port_pdata = dev_get_parent_plat(pdev); + ops->port_disable(dev, port_pdata->index, port_pdata->phy); +- ops->port_disable(dev, priv->cpu_port, NULL); ++ ops->port_disable(dev, priv->cpu_port, priv->cpu_port_fixed_phy); + } + + eth_get_ops(master)->stop(master); +@@ -199,9 +199,7 @@ + static int dsa_port_of_to_pdata(struct udevice *pdev) + { + struct dsa_port_pdata *port_pdata; +- struct dsa_pdata *dsa_pdata; + struct eth_pdata *eth_pdata; +- struct udevice *dev; + const char *label; + u32 index; + int err; +@@ -213,15 +211,12 @@ + if (err) + return err; + +- dev = dev_get_parent(pdev); +- dsa_pdata = dev_get_uclass_plat(dev); +- + port_pdata = dev_get_parent_plat(pdev); + port_pdata->index = index; + + label = ofnode_read_string(dev_ofnode(pdev), "label"); + if (label) +- strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH); ++ strlcpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH); + + eth_pdata = dev_get_plat(pdev); + eth_pdata->priv_pdata = port_pdata; +@@ -240,18 +235,42 @@ + .free_pkt = dsa_port_free_pkt, + }; + +-static int dsa_port_probe(struct udevice *pdev) ++/* ++ * Inherit port's hwaddr from the DSA master, unless the port already has a ++ * unique MAC address specified in the environment. ++ */ ++static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master) + { +- struct udevice *dev = dev_get_parent(pdev); + struct eth_pdata *eth_pdata, *master_pdata; + unsigned char env_enetaddr[ARP_HLEN]; ++ ++ eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr); ++ if (!is_zero_ethaddr(env_enetaddr)) { ++ /* individual port mac addrs require master to be promisc */ ++ struct eth_ops *eth_ops = eth_get_ops(master); ++ ++ if (eth_ops->set_promisc) ++ eth_ops->set_promisc(master, 1); ++ ++ return; ++ } ++ ++ master_pdata = dev_get_plat(master); ++ eth_pdata = dev_get_plat(pdev); ++ memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN); ++ eth_env_set_enetaddr_by_index("eth", dev_seq(pdev), ++ master_pdata->enetaddr); ++} ++ ++static int dsa_port_probe(struct udevice *pdev) ++{ ++ struct udevice *dev = dev_get_parent(pdev); ++ struct dsa_ops *ops = dsa_get_ops(dev); + struct dsa_port_pdata *port_pdata; +- struct dsa_priv *dsa_priv; + struct udevice *master; +- int ret; ++ int err; + + port_pdata = dev_get_parent_plat(pdev); +- dsa_priv = dev_get_uclass_priv(dev); + + port_pdata->phy = dm_eth_phy_connect(pdev); + if (!port_pdata->phy) +@@ -268,42 +287,25 @@ + * TODO: we assume the master device is always there and doesn't get + * removed during runtime. + */ +- ret = device_probe(master); +- if (ret) +- return ret; +- +- /* +- * Inherit port's hwaddr from the DSA master, unless the port already +- * has a unique MAC address specified in the environment. +- */ +- eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr); +- if (!is_zero_ethaddr(env_enetaddr)) { +- /* individual port mac addrs require master to be promisc */ +- struct eth_ops *eth_ops = eth_get_ops(master); ++ err = device_probe(master); ++ if (err) ++ return err; + +- if (eth_ops->set_promisc) +- eth_ops->set_promisc(master, 1); ++ dsa_port_set_hwaddr(pdev, master); + +- return 0; ++ if (ops->port_probe) { ++ err = ops->port_probe(dev, port_pdata->index, ++ port_pdata->phy); ++ if (err) ++ return err; + } + +- master_pdata = dev_get_plat(master); +- eth_pdata = dev_get_plat(pdev); +- memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN); +- eth_env_set_enetaddr_by_index("eth", dev_seq(pdev), +- master_pdata->enetaddr); +- + return 0; + } + + static int dsa_port_remove(struct udevice *pdev) + { +- struct udevice *dev = dev_get_parent(pdev); +- struct dsa_port_pdata *port_pdata; +- struct dsa_priv *dsa_priv; +- +- port_pdata = dev_get_parent_plat(pdev); +- dsa_priv = dev_get_uclass_priv(dev); ++ struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev); + + port_pdata->phy = NULL; + +@@ -419,7 +421,7 @@ + struct dsa_port_pdata *port_pdata; + + port_pdata = dev_get_parent_plat(pdev); +- strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH); ++ strlcpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH); + pdev->name = port_pdata->name; + } + +diff -ruN u-boot-2021.10/net/eth_common.c u-boot/net/eth_common.c +--- u-boot-2021.10/net/eth_common.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/eth_common.c 2021-11-01 17:10:14.719567510 +0100 +@@ -32,6 +32,7 @@ + void eth_common_init(void) + { + bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); ++#if CONFIG_IS_ENABLED(ETH) + #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_init(); + #endif +@@ -39,6 +40,7 @@ + #ifdef CONFIG_PHYLIB + phy_init(); + #endif ++#endif + } + + int eth_mac_skip(int index) +diff -ruN u-boot-2021.10/net/Kconfig u-boot/net/Kconfig +--- u-boot-2021.10/net/Kconfig 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/Kconfig 2021-11-01 17:10:14.719567510 +0100 +@@ -40,7 +40,6 @@ + + config IP_DEFRAG + bool "Support IP datagram reassembly" +- default n + help + Selecting this will enable IP datagram reassembly according + to the algorithm in RFC815. +diff -ruN u-boot-2021.10/net/mdio-uclass.c u-boot/net/mdio-uclass.c +--- u-boot-2021.10/net/mdio-uclass.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/mdio-uclass.c 2021-11-01 17:10:14.719567510 +0100 +@@ -101,7 +101,7 @@ + pdata->mii_bus->write = mdio_write; + pdata->mii_bus->reset = mdio_reset; + pdata->mii_bus->priv = dev; +- strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1); ++ strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN); + + return mdio_register(pdata->mii_bus); + } +diff -ruN u-boot-2021.10/net/tftp.c u-boot/net/tftp.c +--- u-boot-2021.10/net/tftp.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/net/tftp.c 2021-11-01 17:10:14.722900661 +0100 +@@ -925,4 +925,3 @@ + memset(net_server_ethaddr, 0, 6); + } + #endif /* CONFIG_CMD_TFTPSRV */ +- +diff -ruN u-boot-2021.10/post/cpu/mpc83xx/ecc.c u-boot/post/cpu/mpc83xx/ecc.c +--- u-boot-2021.10/post/cpu/mpc83xx/ecc.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/post/cpu/mpc83xx/ecc.c 2021-11-01 17:10:14.722900661 +0100 +@@ -70,10 +70,6 @@ + int_state = disable_interrupts(); + icache_enable(); + +-#ifdef CONFIG_DDR_32BIT +- /* It seems like no one really uses the CONFIG_DDR_32BIT mode */ +-#error "Add ECC POST support for CONFIG_DDR_32BIT here!" +-#else + for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0; + addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { + +@@ -138,7 +134,6 @@ + + errbit %= 63; + } +-#endif /* !CONFIG_DDR_32BIT */ + + ecc_clear(ddr); + +diff -ruN u-boot-2021.10/README u-boot/README +--- u-boot-2021.10/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/README 2021-11-01 17:10:13.542965197 +0100 +@@ -300,7 +300,6 @@ + - loads U-Boot or (in falcon mode) Linux + + +- + Configuration Options: + ---------------------- + +@@ -465,10 +464,6 @@ + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + +- CONFIG_SYS_FSL_DDR4 +- Board config to use DDR4. It can be enabled for SoCs with +- DDR4 controllers. +- + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + +@@ -481,15 +476,6 @@ + CONFIG_SYS_FSL_LBC_CLK_DIV + Defines divider of platform clock(clock input to eLBC controller). + +- CONFIG_SYS_FSL_PBL_PBI +- It enables addition of RCW (Power on reset configuration) in built image. +- Please refer doc/README.pblimage for more details +- +- CONFIG_SYS_FSL_PBL_RCW +- It adds PBI(pre-boot instructions) commands in u-boot build image. +- PBI commands can be used to configure SoC before it starts the execution. +- Please refer doc/README.pblimage for more details +- + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + +@@ -599,16 +585,6 @@ + crash. This is needed for buggy hardware (uc101) where + no pull down resistor is connected to the signal IDE5V_DD7. + +- CONFIG_MACH_TYPE [relevant for ARM only][mandatory] +- +- This setting is mandatory for all boards that have only one +- machine type and must be used to specify the machine type +- number as it appears in the ARM machine registry +- (see https://www.arm.linux.org.uk/developer/machines/). +- Only boards that have multiple machine types supported +- in a single configuration file and the machine type is +- runtime discoverable, do not have to use this setting. +- + - vxWorks boot parameters: + + bootvx constructs a valid bootline using the following +@@ -671,11 +647,6 @@ + time on others. This setting #define's the initial + value of the "loads_echo" environment variable. + +-- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) +- CONFIG_KGDB_BAUDRATE +- Select one of the baudrates listed in +- CONFIG_SYS_BAUDRATE_TABLE, see below. +- + - Removal of commands + If no commands are needed to boot, you can disable + CONFIG_CMDLINE to remove them. In this case, the command line +@@ -879,17 +850,6 @@ + Support for National dp8382[01] gigabit chips. + + - NETWORK Support (other): +- +- CONFIG_DRIVER_AT91EMAC +- Support for AT91RM9200 EMAC. +- +- CONFIG_RMII +- Define this to use reduced MII inteface +- +- CONFIG_DRIVER_AT91EMAC_QUIET +- If this defined, the driver is quiet. +- The driver doen't show link status messages. +- + CONFIG_CALXEDA_XGMAC + Support for the Calxeda XGMAC device + +@@ -1461,129 +1421,7 @@ + In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined + with a list of GPIO LEDs that have inverted polarity. + +-- I2C Support: CONFIG_SYS_I2C_LEGACY +- +- Note: This is deprecated in favour of driver model. Use +- CONFIG_DM_I2C instead. +- +- This enable the legacy i2c subsystem, and will allow you to use +- i2c commands at the u-boot command line (as long as you set +- CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE +- for defining speed and slave address +- - activate second bus with I2C_SOFT_DECLARATIONS2 define +- CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2 +- for defining speed and slave address +- - activate third bus with I2C_SOFT_DECLARATIONS3 define +- CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3 +- for defining speed and slave address +- - activate fourth bus with I2C_SOFT_DECLARATIONS4 define +- CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4 +- for defining speed and slave address +- +- - drivers/i2c/fsl_i2c.c: +- - activate i2c driver with CONFIG_SYS_I2C_FSL +- define CONFIG_SYS_FSL_I2C_OFFSET for setting the register +- offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and +- CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first +- bus. +- - If your board supports a second fsl i2c bus, define +- CONFIG_SYS_FSL_I2C2_OFFSET for the register offset +- CONFIG_SYS_FSL_I2C2_SPEED for the speed and +- CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the +- second bus. +- +- - drivers/i2c/tegra_i2c.c: +- - activate this driver with CONFIG_SYS_I2C_TEGRA +- - This driver adds 4 i2c buses with a fix speed from +- 100000 and the slave addr 0! +- +- - drivers/i2c/ppc4xx_i2c.c +- - activate this driver with CONFIG_SYS_I2C_PPC4XX +- - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 +- - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 +- +- - drivers/i2c/i2c_mxc.c +- - activate this driver with CONFIG_SYS_I2C_MXC +- - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 +- - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 +- - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 +- - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 +- - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED +- - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE +- - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED +- - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE +- - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED +- - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE +- - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED +- - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE +- If those defines are not set, default value is 100000 +- for speed, and 0 for slave. +- +- - drivers/i2c/rcar_i2c.c: +- - activate this driver with CONFIG_SYS_I2C_RCAR +- - This driver adds 4 i2c buses +- +- - drivers/i2c/sh_i2c.c: +- - activate this driver with CONFIG_SYS_I2C_SH +- - This driver adds from 2 to 5 i2c buses +- +- - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 +- - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 +- - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 +- - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 +- - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 +- - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 +- - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 +- - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 +- - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 +- - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 +- - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses +- +- - drivers/i2c/omap24xx_i2c.c +- - activate this driver with CONFIG_SYS_I2C_OMAP24XX +- - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 +- - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 +- - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 +- - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 +- - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 +- - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 +- - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 +- - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 +- - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 +- - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 +- +- - drivers/i2c/s3c24x0_i2c.c: +- - activate this driver with CONFIG_SYS_I2C_S3C24X0 +- - This driver adds i2c buses (11 for Exynos5250, Exynos5420 +- 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) +- with a fix speed from 100000 and the slave addr 0! +- +- - drivers/i2c/ihs_i2c.c +- - activate this driver with CONFIG_SYS_I2C_IHS +- - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0 +- - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0 +- - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0 +- - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1 +- - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1 +- - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1 +- - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2 +- - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2 +- - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2 +- - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 +- - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 +- - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 +- - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL +- - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1 +- - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1 +- - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1 +- - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1 +- - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1 +- - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1 +- - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1 +- - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1 +- +- additional defines: +- ++- I2C Support: + CONFIG_SYS_NUM_I2C_BUSES + Hold the number of i2c buses you want to use. + +@@ -2236,9 +2074,6 @@ + Defines the size and behavior of the NAND that SPL uses + to read U-Boot + +- CONFIG_SYS_NAND_U_BOOT_OFFS +- Location in NAND to read U-Boot from +- + CONFIG_SYS_NAND_U_BOOT_DST + Location in memory to load U-Boot to + +@@ -2873,22 +2708,6 @@ + This only takes effect if the memory commands are activated + globally (CONFIG_CMD_MEMORY). + +-- CONFIG_SKIP_LOWLEVEL_INIT +- [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain +- low level initializations (like setting up the memory +- controller) are omitted and/or U-Boot does not +- relocate itself into RAM. +- +- Normally this variable MUST NOT be defined. The only +- exception is when U-Boot is loaded (to RAM) by some +- other boot loader or by a debugger which performs +- these initializations itself. +- +-- CONFIG_SKIP_LOWLEVEL_INIT_ONLY +- [ARM926EJ-S only] This allows just the call to lowlevel_init() +- to be skipped. The normal CP15 init (such as enabling the +- instruction cache) is still performed. +- + - CONFIG_SPL_BUILD + Set when the currently-running compilation is for an artifact + that will end up in the SPL (as opposed to the TPL or U-Boot +diff -ruN u-boot-2021.10/scripts/basic/Makefile u-boot/scripts/basic/Makefile +--- u-boot-2021.10/scripts/basic/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/basic/Makefile 2021-11-01 17:10:14.726233812 +0100 +@@ -7,7 +7,7 @@ + # when kernel configuration changes (which is what happens when + # .config is included by main Makefile. + # --------------------------------------------------------------------------- +-# fixdep: Used to generate dependency information during build process ++# fixdep: Used to generate dependency information during build process + + hostprogs-y := fixdep + always := $(hostprogs-y) +diff -ruN u-boot-2021.10/scripts/checkpatch.pl u-boot/scripts/checkpatch.pl +--- u-boot-2021.10/scripts/checkpatch.pl 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/checkpatch.pl 2021-11-01 17:10:14.726233812 +0100 +@@ -23,6 +23,9 @@ + use Getopt::Long qw(:config no_auto_abbrev); + + my $quiet = 0; ++my $verbose = 0; ++my %verbose_messages = (); ++my %verbose_emitted = (); + my $tree = 1; + my $chk_signoff = 1; + my $chk_patch = 1; +@@ -43,6 +46,8 @@ + my $fix = 0; + my $fix_inplace = 0; + my $root; ++my $gitroot = $ENV{'GIT_DIR'}; ++$gitroot = ".git" if !defined($gitroot); + my %debug; + my %camelcase = (); + my %use_type = (); +@@ -59,13 +64,15 @@ + my $codespell = 0; + my $codespellfile = "/usr/share/codespell/dictionary.txt"; + my $conststructsfile = "$D/const_structs.checkpatch"; +-my $typedefsfile = ""; + my $u_boot = 0; ++my $docsfile = "$D/../doc/develop/checkpatch.rst"; ++my $typedefsfile; + my $color = "auto"; + my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE + # git output parsing needs US English output, so first set backtick child process LANGUAGE + my $git_command ='export LANGUAGE=en_US.UTF-8; git'; + my $tabsize = 8; ++my ${CONFIG_} = "CONFIG_"; + + sub help { + my ($exitcode) = @_; +@@ -76,6 +83,7 @@ + + Options: + -q, --quiet quiet ++ -v, --verbose verbose mode + --no-tree run without a kernel tree + --no-signoff do not check for 'Signed-off-by' line + --patch treat FILE as patchfile (default) +@@ -129,6 +137,8 @@ + --color[=WHEN] Use colors 'always', 'never', or only when output + is a terminal ('auto'). Default is 'auto'. + --u-boot Run additional checks for U-Boot ++ --kconfig-prefix=WORD use WORD as a prefix for Kconfig symbols (default ++ ${CONFIG_}) + -h, --help, --version display this help and exit + + When FILE is - read standard input. +@@ -155,15 +165,51 @@ + my $text = <$script>; + close($script); + +- my @types = (); ++ my %types = (); + # Also catch when type or level is passed through a variable +- for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { +- push (@types, $_); ++ while ($text =~ /(?:(\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { ++ if (defined($1)) { ++ if (exists($types{$2})) { ++ $types{$2} .= ",$1" if ($types{$2} ne $1); ++ } else { ++ $types{$2} = $1; ++ } ++ } else { ++ $types{$2} = "UNDETERMINED"; ++ } + } +- @types = sort(uniq(@types)); ++ + print("#\tMessage type\n\n"); +- foreach my $type (@types) { ++ if ($color) { ++ print(" ( Color coding: "); ++ print(RED . "ERROR" . RESET); ++ print(" | "); ++ print(YELLOW . "WARNING" . RESET); ++ print(" | "); ++ print(GREEN . "CHECK" . RESET); ++ print(" | "); ++ print("Multiple levels / Undetermined"); ++ print(" )\n\n"); ++ } ++ ++ foreach my $type (sort keys %types) { ++ my $orig_type = $type; ++ if ($color) { ++ my $level = $types{$type}; ++ if ($level eq "ERROR") { ++ $type = RED . $type . RESET; ++ } elsif ($level eq "WARN") { ++ $type = YELLOW . $type . RESET; ++ } elsif ($level eq "CHK") { ++ $type = GREEN . $type . RESET; ++ } ++ } + print(++$count . "\t" . $type . "\n"); ++ if ($verbose && exists($verbose_messages{$orig_type})) { ++ my $message = $verbose_messages{$orig_type}; ++ $message =~ s/\n/\n\t/g; ++ print("\t" . $message . "\n\n"); ++ } + } + + exit($exitcode); +@@ -195,6 +241,46 @@ + unshift(@ARGV, @conf_args) if @conf_args; + } + ++sub load_docs { ++ open(my $docs, '<', "$docsfile") ++ or warn "$P: Can't read the documentation file $docsfile $!\n"; ++ ++ my $type = ''; ++ my $desc = ''; ++ my $in_desc = 0; ++ ++ while (<$docs>) { ++ chomp; ++ my $line = $_; ++ $line =~ s/\s+$//; ++ ++ if ($line =~ /^\s*\*\*(.+)\*\*$/) { ++ if ($desc ne '') { ++ $verbose_messages{$type} = trim($desc); ++ } ++ $type = $1; ++ $desc = ''; ++ $in_desc = 1; ++ } elsif ($in_desc) { ++ if ($line =~ /^(?:\s{4,}|$)/) { ++ $line =~ s/^\s{4}//; ++ $desc .= $line; ++ $desc .= "\n"; ++ } else { ++ $verbose_messages{$type} = trim($desc); ++ $type = ''; ++ $desc = ''; ++ $in_desc = 0; ++ } ++ } ++ } ++ ++ if ($desc ne '') { ++ $verbose_messages{$type} = trim($desc); ++ } ++ close($docs); ++} ++ + # Perl's Getopt::Long allows options to take optional arguments after a space. + # Prevent --color by itself from consuming other arguments + foreach (@ARGV) { +@@ -205,6 +291,7 @@ + + GetOptions( + 'q|quiet+' => \$quiet, ++ 'v|verbose!' => \$verbose, + 'tree!' => \$tree, + 'signoff!' => \$chk_signoff, + 'patch!' => \$chk_patch, +@@ -238,12 +325,29 @@ + 'color=s' => \$color, + 'no-color' => \$color, #keep old behaviors of -nocolor + 'nocolor' => \$color, #keep old behaviors of -nocolor ++ 'kconfig-prefix=s' => \${CONFIG_}, + 'h|help' => \$help, + 'version' => \$help + ) or help(1); + + help(0) if ($help); + ++die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix)); ++die "$P: --verbose cannot be used with --terse\n" if ($verbose && $terse); ++ ++if ($color =~ /^[01]$/) { ++ $color = !$color; ++} elsif ($color =~ /^always$/i) { ++ $color = 1; ++} elsif ($color =~ /^never$/i) { ++ $color = 0; ++} elsif ($color =~ /^auto$/i) { ++ $color = (-t STDOUT); ++} else { ++ die "$P: Invalid color mode: $color\n"; ++} ++ ++load_docs() if ($verbose); + list_types(0) if ($list_types); + + $fix = 1 if ($fix_inplace); +@@ -263,20 +367,8 @@ + push(@ARGV, '-'); + } + +-if ($color =~ /^[01]$/) { +- $color = !$color; +-} elsif ($color =~ /^always$/i) { +- $color = 1; +-} elsif ($color =~ /^never$/i) { +- $color = 0; +-} elsif ($color =~ /^auto$/i) { +- $color = (-t STDOUT); +-} else { +- die "Invalid color mode: $color\n"; +-} +- + # skip TAB size 1 to avoid additional checks on $tabsize - 1 +-die "Invalid TAB size: $tabsize\n" if ($tabsize < 2); ++die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2); + + sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; +@@ -377,6 +469,7 @@ + # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check + our $Attribute = qr{ + const| ++ volatile| + __percpu| + __nocast| + __safe| +@@ -483,7 +576,7 @@ + + our $allocFunctions = qr{(?x: + (?:(?:devm_)? +- (?:kv|k|v)[czm]alloc(?:_node|_array)? | ++ (?:kv|k|v)[czm]alloc(?:_array)?(?:_node)? | + kstrdup(?:_const)? | + kmemdup(?:_nul)?) | + (?:\w+)?alloc_skb(?:_ip_align)? | +@@ -503,6 +596,88 @@ + Cc: + )}; + ++our $tracing_logging_tags = qr{(?xi: ++ [=-]*> | ++ <[=-]* | ++ \[ | ++ \] | ++ start | ++ called | ++ entered | ++ entry | ++ enter | ++ in | ++ inside | ++ here | ++ begin | ++ exit | ++ end | ++ done | ++ leave | ++ completed | ++ out | ++ return | ++ [\.\!:\s]* ++)}; ++ ++sub edit_distance_min { ++ my (@arr) = @_; ++ my $len = scalar @arr; ++ if ((scalar @arr) < 1) { ++ # if underflow, return ++ return; ++ } ++ my $min = $arr[0]; ++ for my $i (0 .. ($len-1)) { ++ if ($arr[$i] < $min) { ++ $min = $arr[$i]; ++ } ++ } ++ return $min; ++} ++ ++sub get_edit_distance { ++ my ($str1, $str2) = @_; ++ $str1 = lc($str1); ++ $str2 = lc($str2); ++ $str1 =~ s/-//g; ++ $str2 =~ s/-//g; ++ my $len1 = length($str1); ++ my $len2 = length($str2); ++ # two dimensional array storing minimum edit distance ++ my @distance; ++ for my $i (0 .. $len1) { ++ for my $j (0 .. $len2) { ++ if ($i == 0) { ++ $distance[$i][$j] = $j; ++ } elsif ($j == 0) { ++ $distance[$i][$j] = $i; ++ } elsif (substr($str1, $i-1, 1) eq substr($str2, $j-1, 1)) { ++ $distance[$i][$j] = $distance[$i - 1][$j - 1]; ++ } else { ++ my $dist1 = $distance[$i][$j - 1]; #insert distance ++ my $dist2 = $distance[$i - 1][$j]; # remove ++ my $dist3 = $distance[$i - 1][$j - 1]; #replace ++ $distance[$i][$j] = 1 + edit_distance_min($dist1, $dist2, $dist3); ++ } ++ } ++ } ++ return $distance[$len1][$len2]; ++} ++ ++sub find_standard_signature { ++ my ($sign_off) = @_; ++ my @standard_signature_tags = ( ++ 'Signed-off-by:', 'Co-developed-by:', 'Acked-by:', 'Tested-by:', ++ 'Reviewed-by:', 'Reported-by:', 'Suggested-by:' ++ ); ++ foreach my $signature (@standard_signature_tags) { ++ return $signature if (get_edit_distance($sign_off, $signature) <= 2); ++ } ++ ++ return ""; ++} ++ + our @typeListMisordered = ( + qr{char\s+(?:un)?signed}, + qr{int\s+(?:(?:un)?signed\s+)?short\s}, +@@ -591,6 +766,8 @@ + ["__ATTR", 2], + ); + ++my $word_pattern = '\b[A-Z]?[a-z]{2,}\b'; ++ + #Create a search pattern for all these functions to speed up a loop below + our $mode_perms_search = ""; + foreach my $entry (@mode_permission_funcs) { +@@ -759,7 +936,7 @@ + next; + } + +- $$wordsRef .= '|' if ($$wordsRef ne ""); ++ $$wordsRef .= '|' if (defined $$wordsRef); + $$wordsRef .= $line; + } + close($file); +@@ -769,16 +946,18 @@ + return 0; + } + +-my $const_structs = ""; +-read_words(\$const_structs, $conststructsfile) +- or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; ++my $const_structs; ++if (show_type("CONST_STRUCT")) { ++ read_words(\$const_structs, $conststructsfile) ++ or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; ++} + +-my $typeOtherTypedefs = ""; +-if (length($typedefsfile)) { ++if (defined($typedefsfile)) { ++ my $typeOtherTypedefs; + read_words(\$typeOtherTypedefs, $typedefsfile) + or warn "No additional types will be considered - file '$typedefsfile': $!\n"; ++ $typeTypedefs .= '|' . $typeOtherTypedefs if (defined $typeOtherTypedefs); + } +-$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne ""); + + sub build_types { + my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)"; +@@ -843,10 +1022,16 @@ + our $declaration_macros = qr{(?x: + (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| + (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| +- (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(| + (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\( + )}; + ++our %allow_repeated_words = ( ++ add => '', ++ added => '', ++ bad => '', ++ be => '', ++); ++ + sub deparenthesize { + my ($string) = @_; + return "" if (!defined($string)); +@@ -904,7 +1089,7 @@ + sub is_SPDX_License_valid { + my ($license) = @_; + +- return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$root/.git")); ++ return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$gitroot")); + + my $root_path = abs_path($root); + my $status = `cd "$root_path"; echo "$license" | python scripts/spdxcheck.py -`; +@@ -922,7 +1107,7 @@ + + $camelcase_seeded = 1; + +- if (-e ".git") { ++ if (-e "$gitroot") { + my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; +@@ -950,7 +1135,7 @@ + return; + } + +- if (-e ".git") { ++ if (-e "$gitroot") { + $files = `${git_command} ls-files "include/*.h"`; + @include_files = split('\n', $files); + } +@@ -970,10 +1155,20 @@ + } + } + ++sub git_is_single_file { ++ my ($filename) = @_; ++ ++ return 0 if ((which("git") eq "") || !(-e "$gitroot")); ++ ++ my $output = `${git_command} ls-files -- $filename 2>/dev/null`; ++ my $count = $output =~ tr/\n//; ++ return $count eq 1 && $output =~ m{^${filename}$}; ++} ++ + sub git_commit_info { + my ($commit, $id, $desc) = @_; + +- return ($id, $desc) if ((which("git") eq "") || !(-e ".git")); ++ return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`; + $output =~ s/^\s*//gm; +@@ -1012,7 +1207,7 @@ + + # If input is git commits, extract all commits from the commit expressions. + # For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'. +-die "$P: No git repository found\n" if ($git && !-e ".git"); ++die "$P: No git repository found\n" if ($git && !-e "$gitroot"); + + if ($git) { + my @commits = (); +@@ -1043,6 +1238,9 @@ + $allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"}; + for my $filename (@ARGV) { + my $FILE; ++ my $is_git_file = git_is_single_file($filename); ++ my $oldfile = $file; ++ $file = 1 if ($is_git_file); + if ($git) { + open($FILE, '-|', "git format-patch -M --stdout -1 $filename") || + die "$P: $filename: git format-patch failed - $!\n"; +@@ -1065,6 +1263,7 @@ + while (<$FILE>) { + chomp; + push(@rawlines, $_); ++ $vname = qq("$1") if ($filename eq '-' && $_ =~ m/^Subject:\s+(.+)/i); + } + close($FILE); + +@@ -1086,6 +1285,7 @@ + @modifierListFile = (); + @typeListFile = (); + build_types(); ++ $file = $oldfile if ($is_git_file); + } + + if (!$quiet) { +@@ -1131,6 +1331,7 @@ + my ($formatted_email) = @_; + + my $name = ""; ++ my $quoted = ""; + my $name_comment = ""; + my $address = ""; + my $comment = ""; +@@ -1162,14 +1363,20 @@ + } + } + +- $name = trim($name); +- $name =~ s/^\"|\"$//g; +- $name =~ s/(\s*\([^\)]+\))\s*//; +- if (defined($1)) { +- $name_comment = trim($1); ++ # Extract comments from names excluding quoted parts ++ # "John D. (Doe)" - Do not extract ++ if ($name =~ s/\"(.+)\"//) { ++ $quoted = $1; ++ } ++ while ($name =~ s/\s*($balanced_parens)\s*/ /) { ++ $name_comment .= trim($1); + } ++ $name =~ s/^[ \"]+|[ \"]+$//g; ++ $name = trim("$quoted $name"); ++ + $address = trim($address); + $address =~ s/^\<|\>$//g; ++ $comment = trim($comment); + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?<!\\)"/\\"/g; ##escape quotes +@@ -1180,25 +1387,30 @@ + } + + sub format_email { +- my ($name, $address) = @_; ++ my ($name, $name_comment, $address, $comment) = @_; + + my $formatted_email; + +- $name = trim($name); +- $name =~ s/^\"|\"$//g; ++ $name =~ s/^[ \"]+|[ \"]+$//g; + $address = trim($address); ++ $address =~ s/(?:\.|\,|\")+$//; ##trailing commas, dots or quotes + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?<!\\)"/\\"/g; ##escape quotes + $name = "\"$name\""; + } + ++ $name_comment = trim($name_comment); ++ $name_comment = " $name_comment" if ($name_comment ne ""); ++ $comment = trim($comment); ++ $comment = " $comment" if ($comment ne ""); ++ + if ("$name" eq "") { + $formatted_email = "$address"; + } else { +- $formatted_email = "$name <$address>"; ++ $formatted_email = "$name$name_comment <$address>"; + } +- ++ $formatted_email .= "$comment"; + return $formatted_email; + } + +@@ -1206,7 +1418,7 @@ + my ($email) = @_; + + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); +- return format_email($email_name, $email_address); ++ return format_email($email_name, $name_comment, $email_address, $comment); + } + + sub same_email_addresses { +@@ -1216,7 +1428,9 @@ + my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2); + + return $email1_name eq $email2_name && +- $email1_address eq $email2_address; ++ $email1_address eq $email2_address && ++ $name1_comment eq $name2_comment && ++ $comment1 eq $comment2; + } + + sub which { +@@ -1681,8 +1895,16 @@ + sub ctx_locate_comment { + my ($first_line, $end_line) = @_; + ++ # If c99 comment on the current line, or the line before or after ++ my ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\+.*(//.*$)@); ++ return $current_comment if (defined $current_comment); ++ ($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\+ ].*(//.*$)@); ++ return $current_comment if (defined $current_comment); ++ ($current_comment) = ($rawlines[$end_line] =~ m@^[\+ ].*(//.*$)@); ++ return $current_comment if (defined $current_comment); ++ + # Catch a comment on the end of the line itself. +- my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); ++ ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + return $current_comment if (defined $current_comment); + + # Look through the context and try and figure out if there is a +@@ -2076,7 +2298,16 @@ + splice(@lines, 1, 1); + $output = join("\n", @lines); + } +- $output = (split('\n', $output))[0] . "\n" if ($terse); ++ ++ if ($terse) { ++ $output = (split('\n', $output))[0] . "\n"; ++ } ++ ++ if ($verbose && exists($verbose_messages{$type}) && ++ !exists($verbose_emitted{$type})) { ++ $output .= $verbose_messages{$type} . "\n\n"; ++ $verbose_emitted{$type} = 1; ++ } + + push(our @report, $output); + +@@ -2425,6 +2656,15 @@ + "DEVICE_PLAT_AUTO", $herecurr); + } + ++sub exclude_global_initialisers { ++ my ($realfile) = @_; ++ ++ # Do not check for BPF programs (tools/testing/selftests/bpf/progs/*.c, samples/bpf/*_kern.c, *.bpf.c). ++ return $realfile =~ m@^tools/testing/selftests/bpf/progs/.*\.c$@ || ++ $realfile =~ m@^samples/bpf/.*_kern\.c$@ || ++ $realfile =~ m@/bpf/.*\.bpf\.c$@; ++} ++ + sub process { + my $filename = shift; + +@@ -2443,6 +2683,7 @@ + my $signoff = 0; + my $author = ''; + my $authorsignoff = 0; ++ my $author_sob = ''; + my $is_patch = 0; + my $is_binding_patch = -1; + my $in_header_lines = $file ? 0 : 1; +@@ -2506,7 +2747,7 @@ + + if ($rawline=~/^\+\+\+\s+(\S+)/) { + $setup_docs = 0; +- if ($1 =~ m@Documentation/admin-guide/kernel-parameters.rst$@) { ++ if ($1 =~ m@Documentation/admin-guide/kernel-parameters.txt$@) { + $setup_docs = 1; + } + #next; +@@ -2706,7 +2947,7 @@ + if (($last_binding_patch != -1) && + ($last_binding_patch ^ $is_binding_patch)) { + WARN("DT_SPLIT_BINDING_PATCH", +- "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt\n"); ++ "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst\n"); + } + } + +@@ -2735,8 +2976,8 @@ + + # Check if the commit log has what seems like a diff which can confuse patch + if ($in_commit_log && !$commit_log_has_diff && +- (($line =~ m@^\s+diff\b.*a/[\w/]+@ && +- $line =~ m@^\s+diff\b.*a/([\w/]+)\s+b/$1\b@) || ++ (($line =~ m@^\s+diff\b.*a/([\w/]+)@ && ++ $line =~ m@^\s+diff\b.*a/[\w/]+\s+b/$1\b@) || + $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ || + $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) { + ERROR("DIFF_IN_COMMIT_MSG", +@@ -2757,6 +2998,10 @@ + # Check the patch for a From: + if (decode("MIME-Header", $line) =~ /^From:\s*(.*)/) { + $author = $1; ++ my $curline = $linenr; ++ while(defined($rawlines[$curline]) && ($rawlines[$curline++] =~ /^[ \t]\s*(.*)/)) { ++ $author .= $1; ++ } + $author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i); + $author =~ s/"//g; + $author = reformat_email($author); +@@ -2766,9 +3011,37 @@ + if ($line =~ /^\s*signed-off-by:\s*(.*)/i) { + $signoff++; + $in_commit_log = 0; +- if ($author ne '') { ++ if ($author ne '' && $authorsignoff != 1) { + if (same_email_addresses($1, $author)) { + $authorsignoff = 1; ++ } else { ++ my $ctx = $1; ++ my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx); ++ my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author); ++ ++ if ($email_address eq $author_address && $email_name eq $author_name) { ++ $author_sob = $ctx; ++ $authorsignoff = 2; ++ } elsif ($email_address eq $author_address) { ++ $author_sob = $ctx; ++ $authorsignoff = 3; ++ } elsif ($email_name eq $author_name) { ++ $author_sob = $ctx; ++ $authorsignoff = 4; ++ ++ my $address1 = $email_address; ++ my $address2 = $author_address; ++ ++ if ($address1 =~ /(\S+)\+\S+(\@.*)/) { ++ $address1 = "$1$2"; ++ } ++ if ($address2 =~ /(\S+)\+\S+(\@.*)/) { ++ $address2 = "$1$2"; ++ } ++ if ($address1 eq $address2) { ++ $authorsignoff = 5; ++ } ++ } + } + } + } +@@ -2795,8 +3068,17 @@ + my $ucfirst_sign_off = ucfirst(lc($sign_off)); + + if ($sign_off !~ /$signature_tags/) { +- WARN("BAD_SIGN_OFF", +- "Non-standard signature: $sign_off\n" . $herecurr); ++ my $suggested_signature = find_standard_signature($sign_off); ++ if ($suggested_signature eq "") { ++ WARN("BAD_SIGN_OFF", ++ "Non-standard signature: $sign_off\n" . $herecurr); ++ } else { ++ if (WARN("BAD_SIGN_OFF", ++ "Non-standard signature: '$sign_off' - perhaps '$suggested_signature'?\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/$sign_off/$suggested_signature/; ++ } ++ } + } + if (defined $space_before && $space_before ne "") { + if (WARN("BAD_SIGN_OFF", +@@ -2825,7 +3107,7 @@ + } + + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); +- my $suggested_email = format_email(($email_name, $email_address)); ++ my $suggested_email = format_email(($email_name, $name_comment, $email_address, $comment)); + if ($suggested_email eq "") { + ERROR("BAD_SIGN_OFF", + "Unrecognized email address: '$email'\n" . $herecurr); +@@ -2836,8 +3118,76 @@ + # Don't force email to have quotes + # Allow just an angle bracketed address + if (!same_email_addresses($email, $suggested_email)) { ++ if (WARN("BAD_SIGN_OFF", ++ "email address '$email' might be better as '$suggested_email'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\Q$email\E/$suggested_email/; ++ } ++ } ++ ++ # Address part shouldn't have comments ++ my $stripped_address = $email_address; ++ $stripped_address =~ s/\([^\(\)]*\)//g; ++ if ($email_address ne $stripped_address) { ++ if (WARN("BAD_SIGN_OFF", ++ "address part of email should not have comments: '$email_address'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\Q$email_address\E/$stripped_address/; ++ } ++ } ++ ++ # Only one name comment should be allowed ++ my $comment_count = () = $name_comment =~ /\([^\)]+\)/g; ++ if ($comment_count > 1) { + WARN("BAD_SIGN_OFF", +- "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); ++ "Use a single name comment in email: '$email'\n" . $herecurr); ++ } ++ ++ ++ # stable@vger.kernel.org or stable@kernel.org shouldn't ++ # have an email name. In addition comments should strictly ++ # begin with a # ++ if ($email =~ /^.*stable\@(?:vger\.)?kernel\.org/i) { ++ if (($comment ne "" && $comment !~ /^#.+/) || ++ ($email_name ne "")) { ++ my $cur_name = $email_name; ++ my $new_comment = $comment; ++ $cur_name =~ s/[a-zA-Z\s\-\"]+//g; ++ ++ # Remove brackets enclosing comment text ++ # and # from start of comments to get comment text ++ $new_comment =~ s/^\((.*)\)$/$1/; ++ $new_comment =~ s/^\[(.*)\]$/$1/; ++ $new_comment =~ s/^[\s\#]+|\s+$//g; ++ ++ $new_comment = trim("$new_comment $cur_name") if ($cur_name ne $new_comment); ++ $new_comment = " # $new_comment" if ($new_comment ne ""); ++ my $new_email = "$email_address$new_comment"; ++ ++ if (WARN("BAD_STABLE_ADDRESS_STYLE", ++ "Invalid email format for stable: '$email', prefer '$new_email'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; ++ } ++ } ++ } elsif ($comment ne "" && $comment !~ /^(?:#.+|\(.+\))$/) { ++ my $new_comment = $comment; ++ ++ # Extract comment text from within brackets or ++ # c89 style /*...*/ comments ++ $new_comment =~ s/^\[(.*)\]$/$1/; ++ $new_comment =~ s/^\/\*(.*)\*\/$/$1/; ++ ++ $new_comment = trim($new_comment); ++ $new_comment =~ s/^[^\w]$//; # Single lettered comment with non word character is usually a typo ++ $new_comment = "($new_comment)" if ($new_comment ne ""); ++ my $new_email = format_email($email_name, $name_comment, $email_address, $new_comment); ++ ++ if (WARN("BAD_SIGN_OFF", ++ "Unexpected content after email: '$email', should be: '$new_email'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\Q$email\E/$new_email/; ++ } + } + } + +@@ -2860,7 +3210,7 @@ + } + if (!defined $lines[$linenr]) { + WARN("BAD_SIGN_OFF", +- "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline); ++ "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline); + } elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) { + WARN("BAD_SIGN_OFF", + "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]); +@@ -2880,8 +3230,11 @@ + + # Check for Gerrit Change-Ids not in any patch context + if ($realfile eq '' && !$has_patch_separator && $line =~ /^\s*change-id:/i) { +- ERROR("GERRIT_CHANGE_ID", +- "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr); ++ if (ERROR("GERRIT_CHANGE_ID", ++ "Remove Gerrit Change-Id's before submitting upstream\n" . $herecurr) && ++ $fix) { ++ fix_delete_line($fixlinenr, $rawline); ++ } + } + + # Check if the commit log is in a possible stack dump +@@ -2903,8 +3256,8 @@ + # file delta changes + $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ || + # filename then : +- $line =~ /^\s*(?:Fixes:|Link:)/i || +- # A Fixes: or Link: line ++ $line =~ /^\s*(?:Fixes:|Link:|$signature_tags)/i || ++ # A Fixes: or Link: line or signature tag line + $commit_log_possible_stack_dump)) { + WARN("COMMIT_LOG_LONG_LINE", + "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr); +@@ -2917,6 +3270,15 @@ + $commit_log_possible_stack_dump = 0; + } + ++# Check for lines starting with a # ++ if ($in_commit_log && $line =~ /^#/) { ++ if (WARN("COMMIT_COMMENT_SYMBOL", ++ "Commit log lines starting with '#' are dropped by git as comments\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/^/ /; ++ } ++ } ++ + # Check for git id commit length and improperly formed commit descriptions + if ($in_commit_log && !$commit_log_possible_stack_dump && + $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i && +@@ -2993,7 +3355,7 @@ + ($line =~ /^new file mode\s*\d+\s*$/) && + ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) { + WARN("DT_SCHEMA_BINDING_PATCH", +- "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n"); ++ "DT bindings should be in DT schema format. See: Documentation/devicetree/bindings/writing-schema.rst\n"); + } + + # Check for wrappage within a valid hunk of the file +@@ -3057,15 +3419,18 @@ + # Check for various typo / spelling mistakes + if (defined($misspellings) && + ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { +- while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) { ++ while ($rawline =~ /(?:^|[^\w\-'`])($misspellings)(?:[^\w\-'`]|$)/gi) { + my $typo = $1; ++ my $blank = copy_spacing($rawline); ++ my $ptr = substr($blank, 0, $-[1]) . "^" x length($typo); ++ my $hereptr = "$hereline$ptr\n"; + my $typo_fix = $spelling_fix{lc($typo)}; + $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); + $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("TYPO_SPELLING", +- "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && ++ "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $hereptr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; + } +@@ -3083,6 +3448,60 @@ + } + } + ++# check for repeated words separated by a single space ++# avoid false positive from list command eg, '-rw-r--r-- 1 root root' ++ if (($rawline =~ /^\+/ || $in_commit_log) && ++ $rawline !~ /[bcCdDlMnpPs\?-][rwxsStT-]{9}/) { ++ pos($rawline) = 1 if (!$in_commit_log); ++ while ($rawline =~ /\b($word_pattern) (?=($word_pattern))/g) { ++ ++ my $first = $1; ++ my $second = $2; ++ my $start_pos = $-[1]; ++ my $end_pos = $+[2]; ++ if ($first =~ /(?:struct|union|enum)/) { ++ pos($rawline) += length($first) + length($second) + 1; ++ next; ++ } ++ ++ next if (lc($first) ne lc($second)); ++ next if ($first eq 'long'); ++ ++ # check for character before and after the word matches ++ my $start_char = ''; ++ my $end_char = ''; ++ $start_char = substr($rawline, $start_pos - 1, 1) if ($start_pos > ($in_commit_log ? 0 : 1)); ++ $end_char = substr($rawline, $end_pos, 1) if ($end_pos < length($rawline)); ++ ++ next if ($start_char =~ /^\S$/); ++ next if (index(" \t.,;?!", $end_char) == -1); ++ ++ # avoid repeating hex occurrences like 'ff ff fe 09 ...' ++ if ($first =~ /\b[0-9a-f]{2,}\b/i) { ++ next if (!exists($allow_repeated_words{lc($first)})); ++ } ++ ++ if (WARN("REPEATED_WORD", ++ "Possible repeated word: '$first'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\b$first $second\b/$first/; ++ } ++ } ++ ++ # if it's a repeated word on consecutive lines in a comment block ++ if ($prevline =~ /$;+\s*$/ && ++ $prevrawline =~ /($word_pattern)\s*$/) { ++ my $last_word = $1; ++ if ($rawline =~ /^\+\s*\*\s*$last_word /) { ++ if (WARN("REPEATED_WORD", ++ "Possible repeated word: '$last_word'\n" . $hereprev) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/(\+\s*\*\s*)$last_word /$1/; ++ } ++ } ++ } ++ } ++ + # ignore non-hunk lines and lines being removed + next if (!$hunk_line || $line =~ /^-/); + +@@ -3141,11 +3560,7 @@ + + if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) { + $is_start = 1; +- } elsif ($lines[$ln - 1] =~ /^\+\s*(?:help|---help---)\s*$/) { +- if ($lines[$ln - 1] =~ "---help---") { +- WARN("CONFIG_DESCRIPTION", +- "prefer 'help' over '---help---' for new help texts\n" . $herecurr); +- } ++ } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) { + $length = -1; + } + +@@ -3172,22 +3587,44 @@ + #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; + } + +-# check for MAINTAINERS entries that don't have the right form +- if ($realfile =~ /^MAINTAINERS$/ && +- $rawline =~ /^\+[A-Z]:/ && +- $rawline !~ /^\+[A-Z]:\t\S/) { +- if (WARN("MAINTAINERS_STYLE", +- "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && +- $fix) { +- $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; ++# check MAINTAINERS entries ++ if ($realfile =~ /^MAINTAINERS$/) { ++# check MAINTAINERS entries for the right form ++ if ($rawline =~ /^\+[A-Z]:/ && ++ $rawline !~ /^\+[A-Z]:\t\S/) { ++ if (WARN("MAINTAINERS_STYLE", ++ "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; ++ } ++ } ++# check MAINTAINERS entries for the right ordering too ++ my $preferred_order = 'MRLSWQBCPTFXNK'; ++ if ($rawline =~ /^\+[A-Z]:/ && ++ $prevrawline =~ /^[\+ ][A-Z]:/) { ++ $rawline =~ /^\+([A-Z]):\s*(.*)/; ++ my $cur = $1; ++ my $curval = $2; ++ $prevrawline =~ /^[\+ ]([A-Z]):\s*(.*)/; ++ my $prev = $1; ++ my $prevval = $2; ++ my $curindex = index($preferred_order, $cur); ++ my $previndex = index($preferred_order, $prev); ++ if ($curindex < 0) { ++ WARN("MAINTAINERS_STYLE", ++ "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr); ++ } else { ++ if ($previndex >= 0 && $curindex < $previndex) { ++ WARN("MAINTAINERS_STYLE", ++ "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev); ++ } elsif ((($prev eq 'F' && $cur eq 'F') || ++ ($prev eq 'X' && $cur eq 'X')) && ++ ($prevval cmp $curval) > 0) { ++ WARN("MAINTAINERS_STYLE", ++ "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev); ++ } ++ } + } +- } +- +-# discourage the use of boolean for type definition attributes of Kconfig options +- if ($realfile =~ /Kconfig/ && +- $line =~ /^\+\s*\bboolean\b/) { +- WARN("CONFIG_TYPE_BOOLEAN", +- "Use of boolean is deprecated, please use bool instead.\n" . $herecurr); + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && +@@ -3284,6 +3721,12 @@ + } + } + ++# check for embedded filenames ++ if ($rawline =~ /^\+.*\Q$realfile\E/) { ++ WARN("EMBEDDED_FILENAME", ++ "It's generally not useful to have the filename in the file\n" . $herecurr); ++ } ++ + # check we are in a valid source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); + +@@ -3361,8 +3804,18 @@ + + # check for adding lines without a newline. + if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { +- WARN("MISSING_EOF_NEWLINE", +- "adding a line without newline at end of file\n" . $herecurr); ++ if (WARN("MISSING_EOF_NEWLINE", ++ "adding a line without newline at end of file\n" . $herecurr) && ++ $fix) { ++ fix_delete_line($fixlinenr+1, "No newline at end of file"); ++ } ++ } ++ ++# check for .L prefix local symbols in .S files ++ if ($realfile =~ /\.S$/ && ++ $line =~ /^\+\s*(?:[A-Z]+_)?SYM_[A-Z]+_(?:START|END)(?:_[A-Z_]+)?\s*\(\s*\.L/) { ++ WARN("AVOID_L_PREFIX", ++ "Avoid using '.L' prefixed local symbol names for denoting a range of code via 'SYM_*_START/END' annotations; see Documentation/asm-annotations.rst\n" . $herecurr); + } + + if ($u_boot) { +@@ -3400,14 +3853,28 @@ + + # check for assignments on the start of a line + if ($sline =~ /^\+\s+($Assignment)[^=]/) { +- CHK("ASSIGNMENT_CONTINUATIONS", +- "Assignment operator '$1' should be on the previous line\n" . $hereprev); ++ my $operator = $1; ++ if (CHK("ASSIGNMENT_CONTINUATIONS", ++ "Assignment operator '$1' should be on the previous line\n" . $hereprev) && ++ $fix && $prevrawline =~ /^\+/) { ++ # add assignment operator to the previous line, remove from current line ++ $fixed[$fixlinenr - 1] .= " $operator"; ++ $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; ++ } + } + + # check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { +- CHK("LOGICAL_CONTINUATIONS", +- "Logical continuations should be on the previous line\n" . $hereprev); ++ my $operator = $1; ++ if (CHK("LOGICAL_CONTINUATIONS", ++ "Logical continuations should be on the previous line\n" . $hereprev) && ++ $fix && $prevrawline =~ /^\+/) { ++ # insert logical operator at last non-comment, non-whitepsace char on previous line ++ $prevline =~ /[\s$;]*$/; ++ my $line_end = substr($prevrawline, $-[0]); ++ $fixed[$fixlinenr - 1] =~ s/\Q$line_end\E$/ $operator$line_end/; ++ $fixed[$fixlinenr] =~ s/\Q$operator\E\s*//; ++ } + } + + # check indentation starts on a tab stop +@@ -3475,7 +3942,7 @@ + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/ && +- $realline > 2) { ++ $realline > 3) { # Do not warn about the initial copyright comment block after SPDX-License-Identifier + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } +@@ -3557,43 +4024,48 @@ + } + + # check for missing blank lines after declarations +- if ($sline =~ /^\+\s+\S/ && #Not at char 1 +- # actual declarations +- ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || ++# (declarations must have the same indentation and not be at the start of line) ++ if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) { ++ # use temporaries ++ my $sl = $sline; ++ my $pl = $prevline; ++ # remove $Attribute/$Sparse uses to simplify comparisons ++ $sl =~ s/\b(?:$Attribute|$Sparse)\b//g; ++ $pl =~ s/\b(?:$Attribute|$Sparse)\b//g; ++ if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations +- $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || ++ $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define +- $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || ++ $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros +- $prevline =~ /^\+\s+$declaration_macros/) && ++ $pl =~ /^\+\s+$declaration_macros/) && + # for "else if" which can look like "$Ident $Ident" +- !($prevline =~ /^\+\s+$c90_Keywords\b/ || ++ !($pl =~ /^\+\s+$c90_Keywords\b/ || + # other possible extensions of declaration lines +- $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || ++ $pl =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + # not starting a section or a macro "\" extended line +- $prevline =~ /(?:\{\s*|\\)$/) && ++ $pl =~ /(?:\{\s*|\\)$/) && + # looks like a declaration +- !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || ++ !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations +- $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || ++ $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define +- $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || ++ $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros +- $sline =~ /^\+\s+$declaration_macros/ || ++ $sl =~ /^\+\s+$declaration_macros/ || + # start of struct or union or enum +- $sline =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || ++ $sl =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || + # start or end of block or continuation of declaration +- $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || ++ $sl =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + # bitfield continuation +- $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || ++ $sl =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + # other possible extensions of declaration lines +- $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) && +- # indentation of previous and current line are the same +- (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) { +- if (WARN("LINE_SPACING", +- "Missing a blank line after declarations\n" . $hereprev) && +- $fix) { +- fix_insert_line($fixlinenr, "\+"); ++ $sl =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/)) { ++ if (WARN("LINE_SPACING", ++ "Missing a blank line after declarations\n" . $hereprev) && ++ $fix) { ++ fix_insert_line($fixlinenr, "\+"); ++ } + } + } + +@@ -3646,12 +4118,16 @@ + } + + # check indentation of a line with a break; +-# if the previous line is a goto or return and is indented the same # of tabs ++# if the previous line is a goto, return or break ++# and is indented the same # of tabs + if ($sline =~ /^\+([\t]+)break\s*;\s*$/) { + my $tabs = $1; +- if ($prevline =~ /^\+$tabs(?:goto|return)\b/) { +- WARN("UNNECESSARY_BREAK", +- "break is not useful after a goto or return\n" . $hereprev); ++ if ($prevline =~ /^\+$tabs(goto|return|break)\b/) { ++ if (WARN("UNNECESSARY_BREAK", ++ "break is not useful after a $1\n" . $hereprev) && ++ $fix) { ++ fix_delete_line($fixlinenr, $rawline); ++ } + } + } + +@@ -3934,6 +4410,17 @@ + #ignore lines not being added + next if ($line =~ /^[^\+]/); + ++# check for self assignments used to avoid compiler warnings ++# e.g.: int foo = foo, *bar = NULL; ++# struct foo bar = *(&(bar)); ++ if ($line =~ /^\+\s*(?:$Declare)?([A-Za-z_][A-Za-z\d_]*)\s*=/) { ++ my $var = $1; ++ if ($line =~ /^\+\s*(?:$Declare)?$var\s*=\s*(?:$var|\*\s*\(?\s*&\s*\(?\s*$var\s*\)?\s*\)?)\s*[;,]/) { ++ WARN("SELF_ASSIGNMENT", ++ "Do not use self-assignments to avoid compiler warnings\n" . $herecurr); ++ } ++ } ++ + # check for dereferences that span multiple lines + if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ && + $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) { +@@ -4049,8 +4536,7 @@ + if (defined $realline_next && + exists $lines[$realline_next - 1] && + !defined $suppress_export{$realline_next} && +- ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || +- $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { ++ ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/)) { + # Handle definitions which produce identifiers with + # a prefix: + # XXX(foo); +@@ -4077,8 +4563,7 @@ + } + if (!defined $suppress_export{$linenr} && + $prevline =~ /^.\s*$/ && +- ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || +- $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { ++ ($line =~ /EXPORT_SYMBOL.*\((.*)\)/)) { + #print "FOO B <$lines[$linenr - 1]>\n"; + $suppress_export{$linenr} = 2; + } +@@ -4089,7 +4574,8 @@ + } + + # check for global initialisers. +- if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) { ++ if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/ && ++ !exclude_global_initialisers($realfile)) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to $1\n" . $herecurr) && + $fix) { +@@ -4168,12 +4654,24 @@ + } + } + ++# check for const static or static <non ptr type> const declarations ++# prefer 'static const <foo>' over 'const static <foo>' and 'static <foo> const' ++ if ($sline =~ /^\+\s*const\s+static\s+($Type)\b/ || ++ $sline =~ /^\+\s*static\s+($BasicType)\s+const\b/) { ++ if (WARN("STATIC_CONST", ++ "Move const after static - use 'static const $1'\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\bconst\s+static\b/static const/; ++ $fixed[$fixlinenr] =~ s/\bstatic\s+($BasicType)\s+const\b/static const $1/; ++ } ++ } ++ + # check for non-global char *foo[] = {"bar", ...} declarations. + if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "char * array declaration might be better as static const\n" . + $herecurr); +- } ++ } + + # check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo) + if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) { +@@ -4290,16 +4788,23 @@ + "printk() should include KERN_<LEVEL> facility level\n" . $herecurr); + } + +- if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { +- my $orig = $1; ++# prefer variants of (subsystem|netdev|dev|pr)_<level> to printk(KERN_<LEVEL> ++ if ($line =~ /\b(printk(_once|_ratelimited)?)\s*\(\s*KERN_([A-Z]+)/) { ++ my $printk = $1; ++ my $modifier = $2; ++ my $orig = $3; ++ $modifier = "" if (!defined($modifier)); + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); ++ $level .= $modifier; ++ $level2 .= $modifier; + WARN("PREFER_PR_LEVEL", +- "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); ++ "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to $printk(KERN_$orig ...\n" . $herecurr); + } + ++# prefer dev_<level> to dev_printk(KERN_<LEVEL> + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); +@@ -4309,6 +4814,12 @@ + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + ++# trace_printk should not be used in production code. ++ if ($line =~ /\b(trace_printk|trace_puts|ftrace_vprintk)\s*\(/) { ++ WARN("TRACE_PRINTK", ++ "Do not use $1() in production code (this can be ignored if built only with a debug config option)\n" . $herecurr); ++ } ++ + # ENOSYS means "bad syscall nr" and nothing else. This will have a small + # number of false positives, but assembly files are not checked, so at + # least the arch entry code will not trigger this warning. +@@ -4317,6 +4828,17 @@ + "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr); + } + ++# ENOTSUPP is not a standard error code and should be avoided in new patches. ++# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP. ++# Similarly to ENOSYS warning a small number of false positives is expected. ++ if (!$file && $line =~ /\bENOTSUPP\b/) { ++ if (WARN("ENOTSUPP", ++ "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\n" . $herecurr) && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\bENOTSUPP\b/EOPNOTSUPP/; ++ } ++ } ++ + # function brace can't be on same line, except for #defines of do while, + # or if closed on same line + if ($perl_version_ok && +@@ -4328,7 +4850,7 @@ + $fix) { + fix_delete_line($fixlinenr, $rawline); + my $fixed_line = $rawline; +- $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/; ++ $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*)\{(.*)$/; + my $line1 = $1; + my $line2 = $2; + fix_insert_line($fixlinenr, ltrim($line1)); +@@ -4739,7 +5261,7 @@ + # A colon needs no spaces before when it is + # terminating a case value or a label. + } elsif ($opv eq ':C' || $opv eq ':L') { +- if ($ctx =~ /Wx./) { ++ if ($ctx =~ /Wx./ and $realfile !~ m@.*\.lds\.h$@) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); +@@ -4823,7 +5345,7 @@ + ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { + ## + ## # Remove any bracketed sections to ensure we do not +-## # falsly report the parameters of functions. ++## # falsely report the parameters of functions. + ## my $ln = $line; + ## while ($ln =~ s/\([^\(\)]*\)//g) { + ## } +@@ -4964,6 +5486,17 @@ + } + } + ++# check if a statement with a comma should be two statements like: ++# foo = bar(), /* comma should be semicolon */ ++# bar = baz(); ++ if (defined($stat) && ++ $stat =~ /^\+\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*,\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*;\s*$/) { ++ my $cnt = statement_rawlines($stat); ++ my $herectx = get_stat_here($linenr, $cnt, $here); ++ WARN("SUSPECT_COMMA_SEMICOLON", ++ "Possible comma where semicolon could be used\n" . $herectx); ++ } ++ + # return is not a function + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { + my $spacing = $1; +@@ -4991,7 +5524,7 @@ + $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { + WARN("RETURN_VOID", + "void function return statements are not generally useful\n" . $hereprev); +- } ++ } + + # if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($perl_version_ok && +@@ -5084,8 +5617,30 @@ + my ($s, $c) = ($stat, $cond); + + if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { +- ERROR("ASSIGN_IN_IF", +- "do not use assignment in if condition\n" . $herecurr); ++ if (ERROR("ASSIGN_IN_IF", ++ "do not use assignment in if condition\n" . $herecurr) && ++ $fix && $perl_version_ok) { ++ if ($rawline =~ /^\+(\s+)if\s*\(\s*(\!)?\s*\(\s*(($Lval)\s*=\s*$LvalOrFunc)\s*\)\s*(?:($Compare)\s*($FuncArg))?\s*\)\s*(\{)?\s*$/) { ++ my $space = $1; ++ my $not = $2; ++ my $statement = $3; ++ my $assigned = $4; ++ my $test = $8; ++ my $against = $9; ++ my $brace = $15; ++ fix_delete_line($fixlinenr, $rawline); ++ fix_insert_line($fixlinenr, "$space$statement;"); ++ my $newline = "${space}if ("; ++ $newline .= '!' if defined($not); ++ $newline .= '(' if (defined $not && defined($test) && defined($against)); ++ $newline .= "$assigned"; ++ $newline .= " $test $against" if (defined($test) && defined($against)); ++ $newline .= ')' if (defined $not && defined($test) && defined($against)); ++ $newline .= ')'; ++ $newline .= " {" if (defined($brace)); ++ fix_insert_line($fixlinenr + 1, $newline); ++ } ++ } + } + + # Find out what is on the end of the line after the +@@ -5206,6 +5761,8 @@ + #CamelCase + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && ++#Ignore some autogenerated defines and enum values ++ $var !~ /^(?:[A-Z]+_){1,5}[A-Z]{1,3}[a-z]/ && + #Ignore Page<foo> variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && + #Ignore SI style variants like nS, mV and dB +@@ -5301,9 +5858,9 @@ + $dstat =~ s/\s*$//s; + + # Flatten any parentheses and braces +- while ($dstat =~ s/\([^\(\)]*\)/1/ || +- $dstat =~ s/\{[^\{\}]*\}/1/ || +- $dstat =~ s/.\[[^\[\]]*\]/1/) ++ while ($dstat =~ s/\([^\(\)]*\)/1u/ || ++ $dstat =~ s/\{[^\{\}]*\}/1u/ || ++ $dstat =~ s/.\[[^\[\]]*\]/1u/) + { + } + +@@ -5344,6 +5901,7 @@ + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) ++ $dstat !~ /^while\s*$Constant\s*$Constant\s*$/ && # while (...) {...} + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... +@@ -5385,7 +5943,7 @@ + next if ($arg =~ /\.\.\./); + next if ($arg =~ /^type$/i); + my $tmp_stmt = $define_stmt; +- $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; ++ $tmp_stmt =~ s/\b(__must_be_array|offsetof|sizeof|sizeof_field|__stringify|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; + $tmp_stmt =~ s/\#+\s*$arg\b//g; + $tmp_stmt =~ s/\b$arg\s*\#\#//g; + my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g; +@@ -5662,6 +6220,17 @@ + "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr); + } + ++# check for unnecessary function tracing like uses ++# This does not use $logFunctions because there are many instances like ++# 'dprintk(FOO, "%s()\n", __func__);' which do not match $logFunctions ++ if ($rawline =~ /^\+.*\([^"]*"$tracing_logging_tags{0,3}%s(?:\s*\(\s*\)\s*)?$tracing_logging_tags{0,3}(?:\\n)?"\s*,\s*__func__\s*\)\s*;/) { ++ if (WARN("TRACING_LOGGING", ++ "Unnecessary ftrace-like logging - prefer using ftrace\n" . $herecurr) && ++ $fix) { ++ fix_delete_line($fixlinenr, $rawline); ++ } ++ } ++ + # check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", +@@ -5808,6 +6377,28 @@ + "Avoid logging continuation uses where feasible\n" . $herecurr); + } + ++# check for unnecessary use of %h[xudi] and %hh[xudi] in logging functions ++ if (defined $stat && ++ $line =~ /\b$logFunctions\s*\(/ && ++ index($stat, '"') >= 0) { ++ my $lc = $stat =~ tr@\n@@; ++ $lc = $lc + $linenr; ++ my $stat_real = get_stat_real($linenr, $lc); ++ pos($stat_real) = index($stat_real, '"'); ++ while ($stat_real =~ /[^\"%]*(%[\#\d\.\*\-]*(h+)[idux])/g) { ++ my $pspec = $1; ++ my $h = $2; ++ my $lineoff = substr($stat_real, 0, $-[1]) =~ tr@\n@@; ++ if (WARN("UNNECESSARY_MODIFIER", ++ "Integer promotion: Using '$h' in '$pspec' is unnecessary\n" . "$here\n$stat_real\n") && ++ $fix && $fixed[$fixlinenr + $lineoff] =~ /^\+/) { ++ my $nspec = $pspec; ++ $nspec =~ s/h//g; ++ $fixed[$fixlinenr + $lineoff] =~ s/\Q$pspec\E/$nspec/; ++ } ++ } ++ } ++ + # check for mask then right shift without a parentheses + if ($perl_version_ok && + $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ && +@@ -5966,8 +6557,7 @@ + my $barriers = qr{ + mb| + rmb| +- wmb| +- read_barrier_depends ++ wmb + }x; + my $barrier_stems = qr{ + mb__before_atomic| +@@ -6008,10 +6598,12 @@ + } + } + +-# check for smp_read_barrier_depends and read_barrier_depends +- if (!$file && $line =~ /\b(smp_|)read_barrier_depends\s*\(/) { +- WARN("READ_BARRIER_DEPENDS", +- "$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\n" . $herecurr); ++# check for data_race without a comment. ++ if ($line =~ /\bdata_race\s*\(/) { ++ if (!ctx_has_comment($first_line, $linenr)) { ++ WARN("DATA_RACE", ++ "data_race without comment\n" . $herecurr); ++ } + } + + # check of hardware specific defines +@@ -6053,50 +6645,68 @@ + } + } + +-# Check for __attribute__ packed, prefer __packed +- if ($realfile !~ m@\binclude/uapi/@ && +- $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { +- WARN("PREFER_PACKED", +- "__packed is preferred over __attribute__((packed))\n" . $herecurr); +- } +- +-# Check for __attribute__ aligned, prefer __aligned +- if ($realfile !~ m@\binclude/uapi/@ && +- $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { +- WARN("PREFER_ALIGNED", +- "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); +- } +- +-# Check for __attribute__ section, prefer __section +- if ($realfile !~ m@\binclude/uapi/@ && +- $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) { +- my $old = substr($rawline, $-[1], $+[1] - $-[1]); +- my $new = substr($old, 1, -1); +- if (WARN("PREFER_SECTION", +- "__section(\"$new\") is preferred over __attribute__((section($old)))\n" . $herecurr) && +- $fix) { +- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/; +- } +- } +- +-# Check for __attribute__ format(printf, prefer __printf ++# Check for compiler attributes + if ($realfile !~ m@\binclude/uapi/@ && +- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { +- if (WARN("PREFER_PRINTF", +- "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && +- $fix) { +- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; ++ $rawline =~ /\b__attribute__\s*\(\s*($balanced_parens)\s*\)/) { ++ my $attr = $1; ++ $attr =~ s/\s*\(\s*(.*)\)\s*/$1/; + ++ my %attr_list = ( ++ "alias" => "__alias", ++ "aligned" => "__aligned", ++ "always_inline" => "__always_inline", ++ "assume_aligned" => "__assume_aligned", ++ "cold" => "__cold", ++ "const" => "__attribute_const__", ++ "copy" => "__copy", ++ "designated_init" => "__designated_init", ++ "externally_visible" => "__visible", ++ "format" => "printf|scanf", ++ "gnu_inline" => "__gnu_inline", ++ "malloc" => "__malloc", ++ "mode" => "__mode", ++ "no_caller_saved_registers" => "__no_caller_saved_registers", ++ "noclone" => "__noclone", ++ "noinline" => "noinline", ++ "nonstring" => "__nonstring", ++ "noreturn" => "__noreturn", ++ "packed" => "__packed", ++ "pure" => "__pure", ++ "section" => "__section", ++ "used" => "__used", ++ "weak" => "__weak" ++ ); ++ ++ while ($attr =~ /\s*(\w+)\s*(${balanced_parens})?/g) { ++ my $orig_attr = $1; ++ my $params = ''; ++ $params = $2 if defined($2); ++ my $curr_attr = $orig_attr; ++ $curr_attr =~ s/^[\s_]+|[\s_]+$//g; ++ if (exists($attr_list{$curr_attr})) { ++ my $new = $attr_list{$curr_attr}; ++ if ($curr_attr eq "format" && $params) { ++ $params =~ /^\s*\(\s*(\w+)\s*,\s*(.*)/; ++ $new = "__$1\($2"; ++ } else { ++ $new = "$new$params"; ++ } ++ if (WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", ++ "Prefer $new over __attribute__(($orig_attr$params))\n" . $herecurr) && ++ $fix) { ++ my $remove = "\Q$orig_attr\E" . '\s*' . "\Q$params\E" . '(?:\s*,\s*)?'; ++ $fixed[$fixlinenr] =~ s/$remove//; ++ $fixed[$fixlinenr] =~ s/\b__attribute__/$new __attribute__/; ++ $fixed[$fixlinenr] =~ s/\}\Q$new\E/} $new/; ++ $fixed[$fixlinenr] =~ s/ __attribute__\s*\(\s*\(\s*\)\s*\)//; ++ } ++ } + } +- } + +-# Check for __attribute__ format(scanf, prefer __scanf +- if ($realfile !~ m@\binclude/uapi/@ && +- $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { +- if (WARN("PREFER_SCANF", +- "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && +- $fix) { +- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; ++ # Check for __attribute__ unused, prefer __always_unused or __maybe_unused ++ if ($attr =~ /^_*unused/) { ++ WARN("PREFER_DEFINED_ATTRIBUTE_MACRO", ++ "__always_unused or __maybe_unused is preferred over __attribute__((__unused__))\n" . $herecurr); + } + } + +@@ -6132,18 +6742,18 @@ + if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) { + my $cast = $1; + my $const = $2; ++ my $suffix = ""; ++ my $newconst = $const; ++ $newconst =~ s/${Int_type}$//; ++ $suffix .= 'U' if ($cast =~ /\bunsigned\b/); ++ if ($cast =~ /\blong\s+long\b/) { ++ $suffix .= 'LL'; ++ } elsif ($cast =~ /\blong\b/) { ++ $suffix .= 'L'; ++ } + if (WARN("TYPECAST_INT_CONSTANT", +- "Unnecessary typecast of c90 int constant\n" . $herecurr) && ++ "Unnecessary typecast of c90 int constant - '$cast$const' could be '$const$suffix'\n" . $herecurr) && + $fix) { +- my $suffix = ""; +- my $newconst = $const; +- $newconst =~ s/${Int_type}$//; +- $suffix .= 'U' if ($cast =~ /\bunsigned\b/); +- if ($cast =~ /\blong\s+long\b/) { +- $suffix .= 'LL'; +- } elsif ($cast =~ /\blong\b/) { +- $suffix .= 'L'; +- } + $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/; + } + } +@@ -6203,9 +6813,11 @@ + $specifier = $1; + $extension = $2; + $qualifier = $3; +- if ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ || ++ if ($extension !~ /[4SsBKRraEehMmIiUDdgVCbGNOxtf]/ || + ($extension eq "f" && +- defined $qualifier && $qualifier !~ /^w/)) { ++ defined $qualifier && $qualifier !~ /^w/) || ++ ($extension eq "4" && ++ defined $qualifier && $qualifier !~ /^cc/)) { + $bad_specifier = $specifier; + last; + } +@@ -6385,8 +6997,7 @@ + if (defined $cond) { + substr($s, 0, length($cond), ''); + } +- if ($s =~ /^\s*;/ && +- $function_name ne 'uninitialized_var') ++ if ($s =~ /^\s*;/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); +@@ -6405,17 +7016,13 @@ + } + + # check for function declarations that have arguments without identifier names +-# while avoiding uninitialized_var(x) + if (defined $stat && +- $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:($Ident)|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && +- (!defined($1) || +- (defined($1) && $1 ne "uninitialized_var")) && +- $2 ne "void") { +- my $args = trim($2); ++ $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && ++ $1 ne "void") { ++ my $args = trim($1); + while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) { + my $arg = trim($1); +- if ($arg =~ /^$Type$/ && +- $arg !~ /enum\s+$Ident$/) { ++ if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) { + WARN("FUNCTION_ARGUMENTS", + "function definition argument '$arg' should also have an identifier name\n" . $herecurr); + } +@@ -6451,7 +7058,7 @@ + + if (!grep(/$name/, @setup_docs)) { + CHK("UNDOCUMENTED_SETUP", +- "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.rst\n" . $herecurr); ++ "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.txt\n" . $herecurr); + } + } + +@@ -6507,7 +7114,7 @@ + } + + # check for alloc argument mismatch +- if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { ++ if ($line =~ /\b((?:devm_)?(?:kcalloc|kmalloc_array))\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } +@@ -6533,41 +7140,22 @@ + } + } + ++# check for IS_ENABLED() without CONFIG_<FOO> ($rawline for comments too) ++ if ($rawline =~ /\bIS_ENABLED\s*\(\s*(\w+)\s*\)/ && $1 !~ /^${CONFIG_}/) { ++ WARN("IS_ENABLED_CONFIG", ++ "IS_ENABLED($1) is normally used as IS_ENABLED(${CONFIG_}$1)\n" . $herecurr); ++ } ++ + # check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE +- if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { ++ if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(${CONFIG_}[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { + my $config = $1; + if (WARN("PREFER_IS_ENABLED", +- "Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\n" . $herecurr) && ++ "Prefer IS_ENABLED(<FOO>) to ${CONFIG_}<FOO> || ${CONFIG_}<FOO>_MODULE\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; + } + } + +-# check for case / default statements not preceded by break/fallthrough/switch +- if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { +- my $has_break = 0; +- my $has_statement = 0; +- my $count = 0; +- my $prevline = $linenr; +- while ($prevline > 1 && ($file || $count < 3) && !$has_break) { +- $prevline--; +- my $rline = $rawlines[$prevline - 1]; +- my $fline = $lines[$prevline - 1]; +- last if ($fline =~ /^\@\@/); +- next if ($fline =~ /^\-/); +- next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/); +- $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i); +- next if ($fline =~ /^.[\s$;]*$/); +- $has_statement = 1; +- $count++; +- $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/); +- } +- if (!$has_break && $has_statement) { +- WARN("MISSING_BREAK", +- "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr); +- } +- } +- + # check for /* fallthrough */ like comment, prefer fallthrough; + my @fallthroughs = ( + 'fallthrough', +@@ -6683,7 +7271,8 @@ + + # check for various structs that are normally const (ops, kgdb, device_tree) + # and avoid what seem like struct definitions 'struct foo {' +- if ($line !~ /\bconst\b/ && ++ if (defined($const_structs) && ++ $line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) { + WARN("CONST_STRUCT", + "struct $1 should normally be const\n" . $herecurr); +@@ -6691,12 +7280,14 @@ + + # use of NR_CPUS is usually wrong + # ignore definitions of NR_CPUS and usage to define arrays as likely right ++# ignore designated initializers using NR_CPUS + if ($line =~ /\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && +- $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) ++ $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/ && ++ $line !~ /^.\s*\.\w+\s*=\s*.*\bNR_CPUS\b/) + { + WARN("NR_CPUS", + "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); +@@ -6715,6 +7306,17 @@ + "Using $1 should generally have parentheses around the comparison\n" . $herecurr); + } + ++# return sysfs_emit(foo, fmt, ...) fmt without newline ++ if ($line =~ /\breturn\s+sysfs_emit\s*\(\s*$FuncArg\s*,\s*($String)/ && ++ substr($rawline, $-[6], $+[6] - $-[6]) !~ /\\n"$/) { ++ my $offset = $+[6] - 1; ++ if (WARN("SYSFS_EMIT", ++ "return sysfs_emit(...) formats should include a terminating newline\n" . $herecurr) && ++ $fix) { ++ substr($fixed[$fixlinenr], $offset, 0) = '\\n'; ++ } ++ } ++ + # nested likely/unlikely calls + if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) { + WARN("LIKELY_MISUSE", +@@ -6732,12 +7334,6 @@ + } + } + +-# check for mutex_trylock_recursive usage +- if ($line =~ /mutex_trylock_recursive/) { +- ERROR("LOCKING", +- "recursive locking is bad, do not use this ever.\n" . $herecurr); +- } +- + # check for lockdep_set_novalidate_class + if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ || + $line =~ /__lockdep_no_validate__\s*\)/ ) { +@@ -6900,7 +7496,7 @@ + exit(0); + } + +- # This is not a patch, and we are are in 'no-patch' mode so ++ # This is not a patch, and we are in 'no-patch' mode so + # just keep quiet. + if (!$chk_patch && !$is_patch) { + exit(0); +@@ -6914,9 +7510,33 @@ + if ($signoff == 0) { + ERROR("MISSING_SIGN_OFF", + "Missing Signed-off-by: line(s)\n"); +- } elsif (!$authorsignoff) { +- WARN("NO_AUTHOR_SIGN_OFF", +- "Missing Signed-off-by: line by nominal patch author '$author'\n"); ++ } elsif ($authorsignoff != 1) { ++ # authorsignoff values: ++ # 0 -> missing sign off ++ # 1 -> sign off identical ++ # 2 -> names and addresses match, comments mismatch ++ # 3 -> addresses match, names different ++ # 4 -> names match, addresses different ++ # 5 -> names match, addresses excluding subaddress details (refer RFC 5233) match ++ ++ my $sob_msg = "'From: $author' != 'Signed-off-by: $author_sob'"; ++ ++ if ($authorsignoff == 0) { ++ ERROR("NO_AUTHOR_SIGN_OFF", ++ "Missing Signed-off-by: line by nominal patch author '$author'\n"); ++ } elsif ($authorsignoff == 2) { ++ CHK("FROM_SIGN_OFF_MISMATCH", ++ "From:/Signed-off-by: email comments mismatch: $sob_msg\n"); ++ } elsif ($authorsignoff == 3) { ++ WARN("FROM_SIGN_OFF_MISMATCH", ++ "From:/Signed-off-by: email name mismatch: $sob_msg\n"); ++ } elsif ($authorsignoff == 4) { ++ WARN("FROM_SIGN_OFF_MISMATCH", ++ "From:/Signed-off-by: email address mismatch: $sob_msg\n"); ++ } elsif ($authorsignoff == 5) { ++ WARN("FROM_SIGN_OFF_MISMATCH", ++ "From:/Signed-off-by: email subaddress mismatch: $sob_msg\n"); ++ } + } + } + +diff -ruN u-boot-2021.10/scripts/coccinelle/net/mdio_register.cocci u-boot/scripts/coccinelle/net/mdio_register.cocci +--- u-boot-2021.10/scripts/coccinelle/net/mdio_register.cocci 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/coccinelle/net/mdio_register.cocci 2021-11-01 17:10:14.726233812 +0100 +@@ -16,12 +16,12 @@ + - miiphy_register(devname, readfunc, writefunc); + + struct mii_dev *mdiodev = mdio_alloc(); + + if (!mdiodev) return -ENOMEM; +-+ strncpy(mdiodev->name, devname, MDIO_NAME_LEN); +++ strlcpy(mdiodev->name, devname, MDIO_NAME_LEN); + + mdiodev->read = readfunc; + + mdiodev->write = writefunc; + + + + retval = mdio_register(mdiodev); +-+ if (retval < 0) return retval; +++ if (retval < 0) { mdio_free(mdiodev); return retval; } + + @ update_read_sig @ + identifier mii_reg.readfunc; +diff -ruN u-boot-2021.10/scripts/config_whitelist.txt u-boot/scripts/config_whitelist.txt +--- u-boot-2021.10/scripts/config_whitelist.txt 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/config_whitelist.txt 2021-11-01 17:10:14.729566963 +0100 +@@ -1,34 +1,16 @@ +-CONFIG_16BIT + CONFIG_64BIT_PHYS_ADDR +-CONFIG_8349_CLKIN + CONFIG_83XX +-CONFIG_83XX_CLKIN +-CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES + CONFIG_83XX_PCICLK +-CONFIG_83XX_PCI_STREAMING + CONFIG_88F5182 + CONFIG_A003399_NOR_WORKAROUND + CONFIG_A008044_WORKAROUND +-CONFIG_ACX517AKN +-CONFIG_ACX544AKN +-CONFIG_ADDRESS +-CONFIG_ADDR_AUTO_INCR_BIT +-CONFIG_ADNPESC1 + CONFIG_AEABI +-CONFIG_AEMIF_CNTRL_BASE +-CONFIG_ALTERA_SPI_IDLE_VAL +-CONFIG_ALU + CONFIG_AM335X_USB0 + CONFIG_AM335X_USB0_MODE + CONFIG_AM335X_USB1 + CONFIG_AM335X_USB1_MODE +-CONFIG_AM437X_USB2PHY2_HOST + CONFIG_ANDES_PCU + CONFIG_ANDES_PCU_BASE +-CONFIG_APER_0_BASE +-CONFIG_APER_1_BASE +-CONFIG_APER_SIZE +-CONFIG_APUS_FAST_EXCEPT + CONFIG_ARCH_ADPAG101P + CONFIG_ARCH_HAS_ILOG2_U32 + CONFIG_ARCH_HAS_ILOG2_U64 +@@ -37,22 +19,12 @@ + CONFIG_ARCH_RMOBILE_EXTRAM_BOOT + CONFIG_ARCH_USE_BUILTIN_BSWAP + CONFIG_ARC_MMU_VER +-CONFIG_ARMADA100 +-CONFIG_ARMADA168 + CONFIG_ARMV7_SECURE_BASE + CONFIG_ARMV7_SECURE_MAX_SIZE + CONFIG_ARMV7_SECURE_RESERVE_SIZE + CONFIG_ARMV8_SWITCH_TO_EL1 +-CONFIG_ARM_ARCH_CP15_ERRATA + CONFIG_ARM_GIC_BASE_ADDRESS +-CONFIG_ARM_PL180_MMCI_BASE +-CONFIG_ARM_PL180_MMCI_CLOCK_FREQ + CONFIG_ARP_TIMEOUT +-CONFIG_ASTRO_COFDMDUOS2 +-CONFIG_ASTRO_TWIN7S2 +-CONFIG_ASTRO_V512 +-CONFIG_ASTRO_V532 +-CONFIG_ASTRO_V912 + CONFIG_AT91C_PQFP_UHPBUG + CONFIG_AT91RESET_EXTRST + CONFIG_AT91RM9200 +@@ -77,7 +49,6 @@ + CONFIG_ATMEL_LEGACY + CONFIG_ATMEL_MCI_8BIT + CONFIG_ATMEL_SPI0 +-CONFIG_AT_TRANS + CONFIG_AUTO_ZRELADDR + CONFIG_BACKSIDE_L2_CACHE + CONFIG_BCH_CONST_M +@@ -101,7 +72,6 @@ + CONFIG_BOARD_POSTCLK_INIT + CONFIG_BOARD_SIZE_LIMIT + CONFIG_BOOGER +-CONFIG_BOOTBLOCK + CONFIG_BOOTFILE + CONFIG_BOOTMODE + CONFIG_BOOTP_ +@@ -119,7 +89,6 @@ + CONFIG_BOOTSCRIPT_COPY_RAM + CONFIG_BOOTSCRIPT_HDR_ADDR + CONFIG_BOOTSCRIPT_KEY_HASH +-CONFIG_BOOT_MODE_BIT + CONFIG_BOOT_RETRY_MIN + CONFIG_BOOT_RETRY_TIME + CONFIG_BPTR_VIRT_ADDR +@@ -132,7 +101,6 @@ + CONFIG_BS_HDR_SIZE + CONFIG_BS_SIZE + CONFIG_BTB +-CONFIG_BUFNO_AUTO_INCR_BIT + CONFIG_BUILD_ENVCRC + CONFIG_BUS_WIDTH + CONFIG_CDP_APPLIANCE_VLAN_TYPE +@@ -166,16 +134,11 @@ + CONFIG_CLOCK_SYNTHESIZER + CONFIG_CM922T_XA10 + CONFIG_CMDLINE_PS_SUPPORT +-CONFIG_CMDLINE_TAG + CONFIG_CM_INIT + CONFIG_CM_MULTIPLE_SSRAM + CONFIG_CM_REMAP + CONFIG_CM_SPD_DETECT +-CONFIG_CM_T335 +-CONFIG_CM_T3X +-CONFIG_CM_T43 + CONFIG_CM_TCRAM +-CONFIG_CNTL + CONFIG_COLDFIRE + CONFIG_COMMANDS + CONFIG_COMMON_BOOT +@@ -222,20 +185,6 @@ + CONFIG_DCACHE + CONFIG_DCACHE_OFF + CONFIG_DCFG_ADDR +-CONFIG_DDR3 +-CONFIG_DDR_2T_TIMING +-CONFIG_DDR_32BIT +-CONFIG_DDR_64BIT +-CONFIG_DDR_CLK_FREQ +-CONFIG_DDR_DEFAULT_CL +-CONFIG_DDR_ECC +-CONFIG_DDR_ECC_CMD +-CONFIG_DDR_ECC_INIT_VIA_DMA +-CONFIG_DDR_FIXED_SIZE +-CONFIG_DDR_II +-CONFIG_DDR_LOG_LEVEL +-CONFIG_DDR_MB +-CONFIG_DDR_SPD + CONFIG_DEBUG + CONFIG_DEBUG_FS + CONFIG_DEBUG_LED +@@ -266,38 +215,14 @@ + CONFIG_DM9000_USE_16BIT + CONFIG_DMA_COHERENT + CONFIG_DMA_COHERENT_SIZE +-CONFIG_DMA_LPC32XX + CONFIG_DMA_NONCOHERENT +-CONFIG_DMA_REQ_BIT + CONFIG_DNET_AUTONEG_TIMEOUT + CONFIG_DP_DDR_CTRL + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR + CONFIG_DP_DDR_NUM_CTRLS + CONFIG_DRAM_TIMINGS_ +-CONFIG_DRIVER_AT91EMAC_PHYADDR +-CONFIG_DRIVER_AT91EMAC_QUIET + CONFIG_DRIVER_DM9000 + CONFIG_DSP_CLUSTER_START +-CONFIG_DWC2_DFLT_SPEED_FULL +-CONFIG_DWC2_DMA_BURST_SIZE +-CONFIG_DWC2_DMA_ENABLE +-CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +-CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE +-CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE +-CONFIG_DWC2_HOST_RX_FIFO_SIZE +-CONFIG_DWC2_I2C_ENABLE +-CONFIG_DWC2_IC_USB_CAP +-CONFIG_DWC2_MAX_CHANNELS +-CONFIG_DWC2_MAX_PACKET_COUNT +-CONFIG_DWC2_MAX_TRANSFER_SIZE +-CONFIG_DWC2_PHY_TYPE +-CONFIG_DWC2_PHY_ULPI_DDR +-CONFIG_DWC2_PHY_ULPI_EXT_VBUS +-CONFIG_DWC2_THR_CTL +-CONFIG_DWC2_TS_DLINE +-CONFIG_DWC2_TX_THR_LENGTH +-CONFIG_DWC2_ULPI_FS_LS +-CONFIG_DWC2_UTMI_WIDTH + CONFIG_DWCDDR21MCTL + CONFIG_DWCDDR21MCTL_BASE + CONFIG_DWC_AHSATA_BASE_ADDR +@@ -312,12 +237,6 @@ + CONFIG_E300 + CONFIG_E5500 + CONFIG_ECC +-CONFIG_ECC_INIT_VIA_DDRCONTROLLER +-CONFIG_ECC_MODE_MASK +-CONFIG_ECC_MODE_SHIFT +-CONFIG_ECC_SRAM_ADDR_MASK +-CONFIG_ECC_SRAM_ADDR_SHIFT +-CONFIG_ECC_SRAM_REQ_BIT + CONFIG_EDB9301 + CONFIG_EDB93XX_INDUSTRIAL + CONFIG_EDB93XX_SDCS0 +@@ -338,11 +257,8 @@ + CONFIG_ENV_ADDR_FLEX + CONFIG_ENV_CALLBACK_LIST_DEFAULT + CONFIG_ENV_CALLBACK_LIST_STATIC +-CONFIG_ENV_COMMON_BOOT +-CONFIG_ENV_EEPROM_IS_ON_I2C + CONFIG_ENV_FLAGS_LIST_DEFAULT + CONFIG_ENV_FLAGS_LIST_STATIC +-CONFIG_ENV_FLASHBOOT + CONFIG_ENV_IS_EMBEDDED + CONFIG_ENV_IS_IN_ + CONFIG_ENV_MAX_ENTRIES +@@ -358,8 +274,6 @@ + CONFIG_ENV_SIZE_FLEX + CONFIG_ENV_SROM_BANK + CONFIG_ENV_TOTAL_SIZE +-CONFIG_ENV_UBIFS_OPTION +-CONFIG_ENV_UBI_MTD + CONFIG_ENV_VERSION + CONFIG_EPH_POWER_EN + CONFIG_EPOLL +@@ -372,20 +286,11 @@ + CONFIG_ET1100_BASE + CONFIG_ETHADDR + CONFIG_ETHBASE +-CONFIG_ETHER_INDEX +-CONFIG_ETHER_NONE +-CONFIG_ETHER_ON_FCC +-CONFIG_ETHER_ON_FCC1 +-CONFIG_ETHER_ON_FCC2 +-CONFIG_ETHER_ON_FCC3 + CONFIG_ETHPRIME + CONFIG_ETH_BUFSIZE + CONFIG_ETH_RXSIZE + CONFIG_EXTRA_CLOCK + CONFIG_EXTRA_ENV +-CONFIG_EXTRA_ENV_BOARD_SETTINGS +-CONFIG_EXTRA_ENV_ITB +-CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS_COMMON + CONFIG_EXT_AHB2AHB_BASE +@@ -410,7 +315,6 @@ + CONFIG_EXYNOS_SPL + CONFIG_EXYNOS_TMU + CONFIG_FACTORYSET +-CONFIG_FAST_FLASH_BIT + CONFIG_FB_ADDR + CONFIG_FB_BACKLIGHT + CONFIG_FB_DEFERRED_IO +@@ -455,7 +359,6 @@ + CONFIG_FSL_DEVICE_DISABLE + CONFIG_FSL_DIU_CH7301 + CONFIG_FSL_DIU_FB +-CONFIG_FSL_DMA + CONFIG_FSL_DSPI1 + CONFIG_FSL_ESDHC_PIN_MUX + CONFIG_FSL_FIXED_MMC_LOCATION +@@ -520,7 +423,6 @@ + CONFIG_FTWDT010_WATCHDOG + CONFIG_FZOTG266HD0A_BASE + CONFIG_GATEWAYIP +-CONFIG_GICV2 + CONFIG_GLOBAL_DATA_NOT_REG10 + CONFIG_GLOBAL_TIMER + CONFIG_GMII +@@ -541,7 +443,6 @@ + CONFIG_HAS_FEC + CONFIG_HAS_FSL_DR_USB + CONFIG_HAS_FSL_MPH_USB +-CONFIG_HDBOOT + CONFIG_HDMI_ENCODER_I2C_ADDR + CONFIG_HETROGENOUS_CLUSTERS + CONFIG_HIDE_LOGO_VERSION +@@ -694,7 +595,6 @@ + CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP + CONFIG_HSMMC2_8BIT + CONFIG_HUSH_INIT_VAR +-CONFIG_HVBOOT + CONFIG_HWCONFIG + CONFIG_HW_ENV_SETTINGS + CONFIG_I2C_ENV_EEPROM_BUS +@@ -718,15 +618,12 @@ + CONFIG_IDE_PREINIT + CONFIG_IDE_RESET + CONFIG_IDE_SWAP_IO +-CONFIG_ID_EEPROM + CONFIG_IMA + CONFIG_IMX + CONFIG_IMX6_PWM_PER_CLK + CONFIG_IMX_HDMI +-CONFIG_IMX_NAND + CONFIG_IMX_VIDEO_SKIP + CONFIG_INETSPACE_V2 +-CONFIG_INITRD_TAG + CONFIG_INIT_IGNORE_ERROR + CONFIG_INI_ALLOW_MULTILINE + CONFIG_INI_CASE_INSENSITIVE +@@ -757,20 +654,13 @@ + CONFIG_JFFS2_SUMMARY + CONFIG_JRSTARTR_JR0 + CONFIG_JTAG_CONSOLE +-CONFIG_KCLK_DIS + CONFIG_KEEP_SERVERADDR + CONFIG_KEYBOARD +-CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE +-CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE +-CONFIG_KEYSTONE_RBL_NAND + CONFIG_KEY_REVOCATION +-CONFIG_KGDB_BAUDRATE +-CONFIG_KGDB_SER_INDEX + CONFIG_KIRKWOOD_EGIGA_INIT + CONFIG_KIRKWOOD_GPIO + CONFIG_KIRKWOOD_PCIE_INIT + CONFIG_KIRKWOOD_RGMII_PAD_1V8 +-CONFIG_KIRQ_EN + CONFIG_KM8321 + CONFIG_KMTEGR1 + CONFIG_KM_BOARD_EXTRA_ENV +@@ -800,32 +690,6 @@ + CONFIG_KM_UBI_PART_BOOT_OPTS + CONFIG_KM_UIMAGE_NAME + CONFIG_KM_UPDATE_UBOOT +-CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE +-CONFIG_KSNAV_NETCP_PDMA_RX_BASE +-CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM +-CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE +-CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM +-CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE +-CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE +-CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE +-CONFIG_KSNAV_NETCP_PDMA_TX_BASE +-CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM +-CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE +-CONFIG_KSNAV_PKTDMA_NETCP +-CONFIG_KSNAV_QM_BASE_ADDRESS +-CONFIG_KSNAV_QM_CONF_BASE +-CONFIG_KSNAV_QM_DESC_SETUP_BASE +-CONFIG_KSNAV_QM_INTD_CONF_BASE +-CONFIG_KSNAV_QM_LINK_RAM_BASE +-CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE +-CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE +-CONFIG_KSNAV_QM_PDSP1_CMD_BASE +-CONFIG_KSNAV_QM_PDSP1_CTRL_BASE +-CONFIG_KSNAV_QM_PDSP1_IRAM_BASE +-CONFIG_KSNAV_QM_QPOOL_NUM +-CONFIG_KSNAV_QM_QUEUE_STATUS_BASE +-CONFIG_KSNAV_QM_REGION_NUM +-CONFIG_KSNAV_QM_STATUS_RAM_BASE + CONFIG_KSNET_CPSW_NUM_PORTS + CONFIG_KSNET_MAC_ID_BASE + CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE +@@ -856,10 +720,8 @@ + CONFIG_LD9040 + CONFIG_LEGACY + CONFIG_LEGACY_BOOTCMD_ENV +-CONFIG_LINUX + CONFIG_LITTLETON_LCD + CONFIG_LMS283GF05 +-CONFIG_LOADADDR + CONFIG_LOADS_ECHO + CONFIG_LOWPOWER_ADDR + CONFIG_LOWPOWER_FLAG +@@ -895,14 +757,10 @@ + CONFIG_M520x + CONFIG_M5301x + CONFIG_MACB_SEARCH_PHY +-CONFIG_MACH_OMAPL138_LCDK +-CONFIG_MACH_TYPE +-CONFIG_MACH_TYPE_COMPAT_REV + CONFIG_MACRESET_TIMEOUT + CONFIG_MALLOC_F_ADDR + CONFIG_MALTA + CONFIG_MARCO_MEMSET +-CONFIG_MARVELL_MFP + CONFIG_MASK_AER_AO + CONFIG_MAX_DSP_CPUS + CONFIG_MAX_FPGA_DEVICES +@@ -913,11 +771,8 @@ + CONFIG_MCF5253 + CONFIG_MCFRTC + CONFIG_MCFTMR +-CONFIG_MCLK_DIS + CONFIG_MDIO_TIMEOUT +-CONFIG_MEMSIZE + CONFIG_MEMSIZE_IN_BYTES +-CONFIG_MEMSIZE_MASK + CONFIG_MEM_HOLE_16M + CONFIG_MEM_INIT_VALUE + CONFIG_MEM_REMAP +@@ -926,13 +781,11 @@ + CONFIG_MII_INIT + CONFIG_MIPS_HUGE_TLB_SUPPORT + CONFIG_MIPS_MT_FPAFF +-CONFIG_MIRQ_EN + CONFIG_MISC_COMMON + CONFIG_MIU_1BIT_INTERLEAVED + CONFIG_MIU_2BIT_21_7_INTERLEAVED + CONFIG_MIU_2BIT_INTERLEAVED + CONFIG_MIU_LINEAR +-CONFIG_MMCBOOTCOMMAND + CONFIG_MMCROOT + CONFIG_MMC_DEFAULT_DEV + CONFIG_MMC_RPMB_TRACE +@@ -945,7 +798,6 @@ + CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION + CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN + CONFIG_MPC83XX_GPIO_1_INIT_VALUE +-CONFIG_MPC83XX_PCI2 + CONFIG_MPC85XX_FEC + CONFIG_MPC85XX_FEC_NAME + CONFIG_MPC8xxx_DISABLE_BPTR +@@ -973,15 +825,10 @@ + CONFIG_MV_ETH_RXQ + CONFIG_MV_I2C_NUM + CONFIG_MV_I2C_REG +-CONFIG_MX25_CLK32 +-CONFIG_MX25_HCLK_FREQ + CONFIG_MX27 + CONFIG_MX27_CLK32 + CONFIG_MX27_TIMER_HIGH_PRECISION + CONFIG_MX28_FEC_MAC_IN_OCOTP +-CONFIG_MX35 +-CONFIG_MX35_CLK32 +-CONFIG_MX35_HCLK_FREQ + CONFIG_MXC_EPDC + CONFIG_MXC_GPT_HCLK + CONFIG_MXC_NAND_HWECC +@@ -991,7 +838,6 @@ + CONFIG_MXC_USB_FLAGS + CONFIG_MXC_USB_PORT + CONFIG_MXC_USB_PORTSC +-CONFIG_MXS + CONFIG_MXS_AUART + CONFIG_MXS_AUART_BASE + CONFIG_MXS_OCOTP +@@ -1002,13 +848,9 @@ + CONFIG_NAND_DATA_REG + CONFIG_NAND_ECC_BCH + CONFIG_NAND_ENV_DST +-CONFIG_NAND_FSL_ELBC +-CONFIG_NAND_FSL_IFC + CONFIG_NAND_KIRKWOOD + CONFIG_NAND_KMETER1 +-CONFIG_NAND_LPC32XX_MLC + CONFIG_NAND_MODE_REG +-CONFIG_NAND_OMAP_ECCSCHEME + CONFIG_NAND_OMAP_GPMC_WSCFG + CONFIG_NAND_SECBOOT + CONFIG_NAND_SPL +@@ -1046,16 +888,9 @@ + CONFIG_ODROID_REV_AIN + CONFIG_OFF_PADCONF + CONFIG_OF_ +-CONFIG_OMAP_EHCI_PHY1_RESET_GPIO +-CONFIG_OMAP_EHCI_PHY2_RESET_GPIO +-CONFIG_OMAP_EHCI_PHY3_RESET_GPIO +-CONFIG_OMAP_USB2PHY2_HOST +-CONFIG_OMAP_USB3PHY1_HOST + CONFIG_ORIGEN + CONFIG_OTHBOOTARGS + CONFIG_OVERWRITE_ETHADDR_ONCE +-CONFIG_PAGE_CNT_MASK +-CONFIG_PAGE_CNT_SHIFT + CONFIG_PALMAS_AUDPWR + CONFIG_PALMAS_POWER + CONFIG_PALMAS_SMPS7_FPWM +@@ -1073,7 +908,6 @@ + CONFIG_PCIE_IMX + CONFIG_PCIE_IMX_PERST_GPIO + CONFIG_PCIE_IMX_POWER_GPIO +-CONFIG_PCISLAVE + CONFIG_PCI_BOOTDELAY + CONFIG_PCI_CLK_FREQ + CONFIG_PCI_CONFIG_HOST_BRIDGE +@@ -1110,7 +944,6 @@ + CONFIG_PL011_CLOCK + CONFIG_PL011_SERIAL_RLCR + CONFIG_PL01x_PORTS +-CONFIG_PLATFORM_ENV_SETTINGS + CONFIG_PM + CONFIG_PMC_BR_PRELIM + CONFIG_PMC_OR_PRELIM +@@ -1129,11 +962,9 @@ + CONFIG_POST_SKIP_ENV_FLAGS + CONFIG_POST_UART + CONFIG_POST_WATCHDOG +-CONFIG_POWER + CONFIG_POWER_FSL + CONFIG_POWER_FSL_MC13892 + CONFIG_POWER_HI6553 +-CONFIG_POWER_I2C + CONFIG_POWER_LTC3676 + CONFIG_POWER_LTC3676_I2C_ADDR + CONFIG_POWER_MAX77696_I2C_ADDR +@@ -1155,7 +986,6 @@ + CONFIG_PROC_FS + CONFIG_PROFILE_ALL_BRANCHES + CONFIG_PROFILING +-CONFIG_PROOF_POINTS + CONFIG_PSRAM_SCFG + CONFIG_PWM + CONFIG_PXA_LCD +@@ -1169,7 +999,6 @@ + CONFIG_QUOTA + CONFIG_RAMBOOTCOMMAND + CONFIG_RAMBOOT_NAND +-CONFIG_RAMBOOT_PBL + CONFIG_RAMBOOT_SPIFLASH + CONFIG_RAMBOOT_TEXT_BASE + CONFIG_RAMDISKFILE +@@ -1180,11 +1009,9 @@ + CONFIG_RED_LED + CONFIG_REG + CONFIG_REG_0 +-CONFIG_REG_1_BASE + CONFIG_REG_2 + CONFIG_REG_3 + CONFIG_REG_8 +-CONFIG_REG_APER_SIZE + CONFIG_REMAKE_ELF + CONFIG_REQ + CONFIG_RESERVED_01_BASE +@@ -1196,7 +1023,6 @@ + CONFIG_RESET_VECTOR_ADDRESS + CONFIG_RESTORE_FLASH + CONFIG_RES_BLOCK_SIZE +-CONFIG_REVISION_TAG + CONFIG_RMII + CONFIG_RMSTP0_ENA + CONFIG_RMSTP10_ENA +@@ -1237,7 +1063,6 @@ + CONFIG_S5PC110 + CONFIG_S5P_PA_SYSRAM + CONFIG_S6E8AX0 +-CONFIG_SABRELITE + CONFIG_SAMA5D3_LCD_BASE + CONFIG_SAMSUNG + CONFIG_SAMSUNG_ONENAND +@@ -1270,21 +1095,16 @@ + CONFIG_SERIAL_HW_FLOW_CONTROL + CONFIG_SERIAL_MULTI + CONFIG_SERIAL_SOFTWARE_FIFO +-CONFIG_SERIAL_TAG + CONFIG_SERIRQ_CONTINUOUS_MODE + CONFIG_SERVERIP + CONFIG_SETUP_INITRD_TAG +-CONFIG_SETUP_MEMORY_TAGS +-CONFIG_SET_BIST + CONFIG_SET_BOOTARGS + CONFIG_SET_DFU_ALT_BUF_LEN +-CONFIG_SFIO + CONFIG_SGI_IP28 + CONFIG_SH73A0 + CONFIG_SH7751_PCI + CONFIG_SHARP_LM8V31 + CONFIG_SHEEVA_88SV131 +-CONFIG_SHEEVA_88SV331xV5 + CONFIG_SH_CMT_CLK_FREQ + CONFIG_SH_DSP + CONFIG_SH_ETHER_ALIGNE_SIZE +@@ -1296,19 +1116,12 @@ + CONFIG_SH_ETHER_SH7734_MII + CONFIG_SH_ETHER_USE_PORT + CONFIG_SH_GPIO_PFC +-CONFIG_SH_I2C_8BIT +-CONFIG_SH_I2C_CLOCK +-CONFIG_SH_I2C_DATA_HIGH +-CONFIG_SH_I2C_DATA_LOW + CONFIG_SH_MMCIF_CLK + CONFIG_SH_QSPI_BASE + CONFIG_SH_SCIF_CLK_FREQ + CONFIG_SH_SDHI_FREQ + CONFIG_SH_SDRAM_OFFSET +-CONFIG_SIEMENS_MACH_TYPE + CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION +-CONFIG_SKIP_LOWLEVEL_INIT +-CONFIG_SKIP_LOWLEVEL_INIT_ONLY + CONFIG_SKIP_TRUNOFF_WATCHDOG + CONFIG_SLIC + CONFIG_SLTTMR +@@ -1335,11 +1148,6 @@ + CONFIG_SMSTP8_ENA + CONFIG_SMSTP9_ENA + CONFIG_SOCRATES +-CONFIG_SOC_K2E +-CONFIG_SOC_K2G +-CONFIG_SOC_K2HK +-CONFIG_SOC_K2L +-CONFIG_SOC_KEYSTONE + CONFIG_SOC_OMAP3430 + CONFIG_SOFT_I2C_GPIO_SCL + CONFIG_SOFT_I2C_GPIO_SDA +@@ -1379,7 +1187,6 @@ + CONFIG_SPL_MAX_SIZE + CONFIG_SPL_MXS_PSWITCH_WAIT + CONFIG_SPL_NAND_INIT +-CONFIG_SPL_NAND_LOAD + CONFIG_SPL_NAND_MINIMAL + CONFIG_SPL_NAND_RAW_ONLY + CONFIG_SPL_NAND_SOFTECC +@@ -1446,7 +1253,6 @@ + CONFIG_SYS_AMASK5 + CONFIG_SYS_AMASK6 + CONFIG_SYS_AMASK7 +-CONFIG_SYS_AT91_CPU_NAME + CONFIG_SYS_AT91_MAIN_CLOCK + CONFIG_SYS_AT91_PLLA + CONFIG_SYS_AT91_PLLB +@@ -1459,10 +1265,6 @@ + CONFIG_SYS_ATA_PORT_ADDR + CONFIG_SYS_ATA_REG_OFFSET + CONFIG_SYS_ATA_STRIDE +-CONFIG_SYS_ATI_REV_A11 +-CONFIG_SYS_ATI_REV_A12 +-CONFIG_SYS_ATI_REV_A13 +-CONFIG_SYS_ATI_REV_ID_MASK + CONFIG_SYS_ATMEL_CPU_NAME + CONFIG_SYS_AUTOLOAD + CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +@@ -1528,12 +1330,6 @@ + CONFIG_SYS_CMD_IAS + CONFIG_SYS_CMD_INT + CONFIG_SYS_CMD_SUSPEND +-CONFIG_SYS_CMXFCR_MASK1 +-CONFIG_SYS_CMXFCR_MASK2 +-CONFIG_SYS_CMXFCR_MASK3 +-CONFIG_SYS_CMXFCR_VALUE1 +-CONFIG_SYS_CMXFCR_VALUE2 +-CONFIG_SYS_CMXFCR_VALUE3 + CONFIG_SYS_CORE_SRAM + CONFIG_SYS_CORE_SRAM_SIZE + CONFIG_SYS_CPC_REINIT_F +@@ -1548,7 +1344,6 @@ + CONFIG_SYS_CPLD_FTIM2 + CONFIG_SYS_CPLD_FTIM3 + CONFIG_SYS_CPLD_SIZE +-CONFIG_SYS_CPMFCR_RAMTYPE + CONFIG_SYS_CPM_INTERRUPT + CONFIG_SYS_CPRI + CONFIG_SYS_CPRI_CLK +@@ -1800,7 +1595,6 @@ + CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR + CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS + CONFIG_SYS_DEFAULT_VIDEO_MODE +-CONFIG_SYS_DEF_EEPROM_ADDR + CONFIG_SYS_DIALOG_PMIC_I2C_ADDR + CONFIG_SYS_DIMM_SLOTS_PER_CTLR + CONFIG_SYS_DIRECT_FLASH_NFS +@@ -1846,7 +1640,6 @@ + CONFIG_SYS_FAST_CLK + CONFIG_SYS_FAULT_ECHO_LINK_DOWN + CONFIG_SYS_FAULT_MII_ADDR +-CONFIG_SYS_FCC_PSMR + CONFIG_SYS_FDT_BASE + CONFIG_SYS_FDT_LOAD_ADDR + CONFIG_SYS_FDT_PAD +@@ -1862,12 +1655,10 @@ + CONFIG_SYS_FLASH1_BASE_PHYS + CONFIG_SYS_FLASH1_BASE_PHYS_EARLY + CONFIG_SYS_FLASHBOOT +-CONFIG_SYS_FLASH_ADDR_BASE + CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + CONFIG_SYS_FLASH_AUTOPROTECT_LIST + CONFIG_SYS_FLASH_BANKS_LIST + CONFIG_SYS_FLASH_BANKS_SIZES +-CONFIG_SYS_FLASH_BANK_SIZE + CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_BASE0 + CONFIG_SYS_FLASH_BASE1 +@@ -2074,18 +1865,6 @@ + CONFIG_SYS_FSL_FMAN_ADDR + CONFIG_SYS_FSL_GUTS_ADDR + CONFIG_SYS_FSL_I2C +-CONFIG_SYS_FSL_I2C2_OFFSET +-CONFIG_SYS_FSL_I2C2_SLAVE +-CONFIG_SYS_FSL_I2C2_SPEED +-CONFIG_SYS_FSL_I2C3_OFFSET +-CONFIG_SYS_FSL_I2C3_SLAVE +-CONFIG_SYS_FSL_I2C3_SPEED +-CONFIG_SYS_FSL_I2C4_OFFSET +-CONFIG_SYS_FSL_I2C4_SLAVE +-CONFIG_SYS_FSL_I2C4_SPEED +-CONFIG_SYS_FSL_I2C_OFFSET +-CONFIG_SYS_FSL_I2C_SLAVE +-CONFIG_SYS_FSL_I2C_SPEED + CONFIG_SYS_FSL_IFC_BASE + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_BASE2 +@@ -2113,8 +1892,6 @@ + CONFIG_SYS_FSL_OCRAM_SIZE + CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS + CONFIG_SYS_FSL_PAMU_OFFSET +-CONFIG_SYS_FSL_PBL_PBI +-CONFIG_SYS_FSL_PBL_RCW + CONFIG_SYS_FSL_PCIE_COMPAT + CONFIG_SYS_FSL_PCI_VER_3_X + CONFIG_SYS_FSL_PEBUF_BASE +@@ -2298,10 +2075,8 @@ + CONFIG_SYS_I2C_DIRECT_BUS + CONFIG_SYS_I2C_DVI_ADDR + CONFIG_SYS_I2C_DVI_BUS_NUM +-CONFIG_SYS_I2C_EARLY_INIT + CONFIG_SYS_I2C_EEPROM_CCID + CONFIG_SYS_I2C_EEPROM_NXID +-CONFIG_SYS_I2C_EEPROM_NXID_MAC + CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS + CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS + CONFIG_SYS_I2C_EXPANDER_ADDR +@@ -2309,41 +2084,12 @@ + CONFIG_SYS_I2C_FRAM + CONFIG_SYS_I2C_G762_ADDR + CONFIG_SYS_I2C_IFDR_DIV +-CONFIG_SYS_I2C_IHS_CH0 +-CONFIG_SYS_I2C_IHS_CH1 +-CONFIG_SYS_I2C_IHS_CH2 +-CONFIG_SYS_I2C_IHS_CH3 +-CONFIG_SYS_I2C_IHS_DUAL +-CONFIG_SYS_I2C_IHS_SLAVE_0 +-CONFIG_SYS_I2C_IHS_SLAVE_0_1 +-CONFIG_SYS_I2C_IHS_SLAVE_1 +-CONFIG_SYS_I2C_IHS_SLAVE_1_1 +-CONFIG_SYS_I2C_IHS_SLAVE_2 +-CONFIG_SYS_I2C_IHS_SLAVE_2_1 +-CONFIG_SYS_I2C_IHS_SLAVE_3 +-CONFIG_SYS_I2C_IHS_SLAVE_3_1 +-CONFIG_SYS_I2C_IHS_SPEED_0 +-CONFIG_SYS_I2C_IHS_SPEED_0_1 +-CONFIG_SYS_I2C_IHS_SPEED_1 +-CONFIG_SYS_I2C_IHS_SPEED_1_1 +-CONFIG_SYS_I2C_IHS_SPEED_2 +-CONFIG_SYS_I2C_IHS_SPEED_2_1 +-CONFIG_SYS_I2C_IHS_SPEED_3 +-CONFIG_SYS_I2C_IHS_SPEED_3_1 + CONFIG_SYS_I2C_INIT_BOARD + CONFIG_SYS_I2C_LDI_ADDR +-CONFIG_SYS_I2C_LEGACY + CONFIG_SYS_I2C_LPC32XX_SLAVE + CONFIG_SYS_I2C_LPC32XX_SPEED +-CONFIG_SYS_I2C_MAC1_BUS +-CONFIG_SYS_I2C_MAC1_CHIP_ADDR +-CONFIG_SYS_I2C_MAC1_DATA_ADDR +-CONFIG_SYS_I2C_MAC2_BUS +-CONFIG_SYS_I2C_MAC2_CHIP_ADDR +-CONFIG_SYS_I2C_MAC2_DATA_ADDR + CONFIG_SYS_I2C_MAX_HOPS + CONFIG_SYS_I2C_NOPROBES +-CONFIG_SYS_I2C_OFFSET + CONFIG_SYS_I2C_PCA953X_ADDR + CONFIG_SYS_I2C_PCA953X_WIDTH + CONFIG_SYS_I2C_PCA9557_ADDR +@@ -2353,53 +2099,6 @@ + CONFIG_SYS_I2C_PXA + CONFIG_SYS_I2C_QIXIS_ADDR + CONFIG_SYS_I2C_RTC_ADDR +-CONFIG_SYS_I2C_S3C24X0_SLAVE +-CONFIG_SYS_I2C_S3C24X0_SPEED +-CONFIG_SYS_I2C_SH +-CONFIG_SYS_I2C_SH_BASE0 +-CONFIG_SYS_I2C_SH_BASE1 +-CONFIG_SYS_I2C_SH_BASE2 +-CONFIG_SYS_I2C_SH_BASE3 +-CONFIG_SYS_I2C_SH_BASE4 +-CONFIG_SYS_I2C_SH_NUM_CONTROLLERS +-CONFIG_SYS_I2C_SH_SPEED0 +-CONFIG_SYS_I2C_SH_SPEED1 +-CONFIG_SYS_I2C_SH_SPEED2 +-CONFIG_SYS_I2C_SH_SPEED3 +-CONFIG_SYS_I2C_SH_SPEED4 +-CONFIG_SYS_I2C_SLAVE +-CONFIG_SYS_I2C_SLAVE1 +-CONFIG_SYS_I2C_SLAVE2 +-CONFIG_SYS_I2C_SLAVE3 +-CONFIG_SYS_I2C_SOFT +-CONFIG_SYS_I2C_SOFT_SLAVE +-CONFIG_SYS_I2C_SOFT_SLAVE_10 +-CONFIG_SYS_I2C_SOFT_SLAVE_11 +-CONFIG_SYS_I2C_SOFT_SLAVE_12 +-CONFIG_SYS_I2C_SOFT_SLAVE_2 +-CONFIG_SYS_I2C_SOFT_SLAVE_3 +-CONFIG_SYS_I2C_SOFT_SLAVE_4 +-CONFIG_SYS_I2C_SOFT_SLAVE_5 +-CONFIG_SYS_I2C_SOFT_SLAVE_6 +-CONFIG_SYS_I2C_SOFT_SLAVE_7 +-CONFIG_SYS_I2C_SOFT_SLAVE_8 +-CONFIG_SYS_I2C_SOFT_SLAVE_9 +-CONFIG_SYS_I2C_SOFT_SPEED +-CONFIG_SYS_I2C_SOFT_SPEED_10 +-CONFIG_SYS_I2C_SOFT_SPEED_11 +-CONFIG_SYS_I2C_SOFT_SPEED_12 +-CONFIG_SYS_I2C_SOFT_SPEED_2 +-CONFIG_SYS_I2C_SOFT_SPEED_3 +-CONFIG_SYS_I2C_SOFT_SPEED_4 +-CONFIG_SYS_I2C_SOFT_SPEED_5 +-CONFIG_SYS_I2C_SOFT_SPEED_6 +-CONFIG_SYS_I2C_SOFT_SPEED_7 +-CONFIG_SYS_I2C_SOFT_SPEED_8 +-CONFIG_SYS_I2C_SOFT_SPEED_9 +-CONFIG_SYS_I2C_SPEED +-CONFIG_SYS_I2C_SPEED1 +-CONFIG_SYS_I2C_SPEED2 +-CONFIG_SYS_I2C_SPEED3 + CONFIG_SYS_I2C_TCA642X_ADDR + CONFIG_SYS_I2C_TCA642X_BUS_NUM + CONFIG_SYS_IBAT0L +@@ -2484,7 +2183,6 @@ + CONFIG_SYS_LIME_SIZE + CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE + CONFIG_SYS_LOADS_BAUD_CHANGE +-CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_LOW + CONFIG_SYS_LOWMEM_BASE + CONFIG_SYS_LOW_RES_TIMER +@@ -2654,15 +2352,12 @@ + CONFIG_SYS_MX7_HCLK + CONFIG_SYS_MXS_VDD5V_ONLY + CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +-CONFIG_SYS_NAND_4_ADDR_CYCLE +-CONFIG_SYS_NAND_5_ADDR_CYCLE + CONFIG_SYS_NAND_ACTL_ALE + CONFIG_SYS_NAND_ACTL_CLE + CONFIG_SYS_NAND_ACTL_DELAY + CONFIG_SYS_NAND_ACTL_NCE + CONFIG_SYS_NAND_ALE + CONFIG_SYS_NAND_AMASK +-CONFIG_SYS_NAND_BAD_BLOCK_POS + CONFIG_SYS_NAND_BASE + CONFIG_SYS_NAND_BASE2 + CONFIG_SYS_NAND_BASE_LIST +@@ -2702,11 +2397,9 @@ + CONFIG_SYS_NAND_MAX_OOBFREE + CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES + CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +-CONFIG_SYS_NAND_ONFI_DETECTION + CONFIG_SYS_NAND_OR_PRELIM + CONFIG_SYS_NAND_PAGE_2K + CONFIG_SYS_NAND_PAGE_4K +-CONFIG_SYS_NAND_PAGE_COUNT + CONFIG_SYS_NAND_QUIET + CONFIG_SYS_NAND_READY_PIN + CONFIG_SYS_NAND_REGS_BASE +@@ -2760,14 +2453,6 @@ + CONFIG_SYS_OBIR + CONFIG_SYS_OHCI_BE_CONTROLLER + CONFIG_SYS_OHCI_SWAP_REG_ACCESS +-CONFIG_SYS_OMAP24_I2C_SLAVE1 +-CONFIG_SYS_OMAP24_I2C_SLAVE2 +-CONFIG_SYS_OMAP24_I2C_SLAVE3 +-CONFIG_SYS_OMAP24_I2C_SLAVE4 +-CONFIG_SYS_OMAP24_I2C_SPEED1 +-CONFIG_SYS_OMAP24_I2C_SPEED2 +-CONFIG_SYS_OMAP24_I2C_SPEED3 +-CONFIG_SYS_OMAP24_I2C_SPEED4 + CONFIG_SYS_OMAP_ABE_SYSCK + CONFIG_SYS_ONENAND_BASE + CONFIG_SYS_ONENAND_BLOCK_SIZE +@@ -2808,19 +2493,7 @@ + CONFIG_SYS_PCI1_MEM_PHYS + CONFIG_SYS_PCI1_MEM_SIZE + CONFIG_SYS_PCI1_MEM_VIRT +-CONFIG_SYS_PCI1_MMIO_BASE +-CONFIG_SYS_PCI1_MMIO_PHYS +-CONFIG_SYS_PCI1_MMIO_SIZE + CONFIG_SYS_PCI2_ADDR +-CONFIG_SYS_PCI2_IO_BASE +-CONFIG_SYS_PCI2_IO_PHYS +-CONFIG_SYS_PCI2_IO_SIZE +-CONFIG_SYS_PCI2_MEM_BASE +-CONFIG_SYS_PCI2_MEM_PHYS +-CONFIG_SYS_PCI2_MEM_SIZE +-CONFIG_SYS_PCI2_MMIO_BASE +-CONFIG_SYS_PCI2_MMIO_PHYS +-CONFIG_SYS_PCI2_MMIO_SIZE + CONFIG_SYS_PCI64_MEMORY_BUS + CONFIG_SYS_PCIE + CONFIG_SYS_PCIE1_ADDR +@@ -3002,7 +2675,6 @@ + CONFIG_SYS_RCAR_I2C1_BASE + CONFIG_SYS_RCAR_I2C2_BASE + CONFIG_SYS_RCAR_I2C3_BASE +-CONFIG_SYS_RCWH_PCIHOST + CONFIG_SYS_READ_SPD + CONFIG_SYS_RESET_ADDR + CONFIG_SYS_RESET_ADDRESS +@@ -3133,8 +2805,6 @@ + CONFIG_SYS_SMC0_SETUP0_VAL + CONFIG_SYS_SMC_CSR0_VAL + CONFIG_SYS_SPCR_OPT +-CONFIG_SYS_SPCR_TSEC1EP +-CONFIG_SYS_SPCR_TSEC2EP + CONFIG_SYS_SPD_BUS_NUM + CONFIG_SYS_SPI_ARGS_OFFS + CONFIG_SYS_SPI_ARGS_SIZE +@@ -3186,9 +2856,7 @@ + CONFIG_SYS_TMRINTR_PRI + CONFIG_SYS_TMRPND_REG + CONFIG_SYS_TMR_BASE +-CONFIG_SYS_TSEC1 + CONFIG_SYS_TSEC1_OFFSET +-CONFIG_SYS_TSEC2 + CONFIG_SYS_TSEC2_OFFSET + CONFIG_SYS_TSEC3_OFFSET + CONFIG_SYS_TX_ETH_BUFFER +@@ -3231,7 +2899,6 @@ + CONFIG_SYS_USE_FLASH + CONFIG_SYS_USE_MAIN_OSCILLATOR + CONFIG_SYS_USE_MMC +-CONFIG_SYS_USE_MPC834XSYS_USB_PHY + CONFIG_SYS_USE_NAND + CONFIG_SYS_USE_NANDFLASH + CONFIG_SYS_USE_NORFLASH +@@ -3255,7 +2922,6 @@ + CONFIG_SYS_VCXK_RESET_DDR + CONFIG_SYS_VCXK_RESET_PIN + CONFIG_SYS_VCXK_RESET_PORT +-CONFIG_SYS_VGA_RAM_EN + CONFIG_SYS_VIDEO_LOGO_MAX_SIZE + CONFIG_SYS_VSC7385_BASE + CONFIG_SYS_VSC7385_BASE_PHYS +@@ -3269,7 +2935,6 @@ + CONFIG_SYS_XHCI_USB2_ADDR + CONFIG_SYS_XHCI_USB3_ADDR + CONFIG_SYS_XIMG_LEN +-CONFIG_SYS_i2C_FSL + CONFIG_TAM3517_SETTINGS + CONFIG_TCA642X + CONFIG_TEGRA_BOARD_STRING +@@ -3298,7 +2963,6 @@ + CONFIG_THUNDERX + CONFIG_TIMESTAMP + CONFIG_TIZEN +-CONFIG_TI_KSNAV + CONFIG_TMU_TIMER + CONFIG_TPL_PAD_TO + CONFIG_TPM_TIS_BASE_ADDRESS +@@ -3319,12 +2983,10 @@ + CONFIG_TWL6030_POWER + CONFIG_TX_DESCR_NUM + CONFIG_TZSW_RESERVED_DRAM_SIZE +-CONFIG_UBIBLOCK + CONFIG_UBIFS_VOLUME + CONFIG_UBI_PART + CONFIG_UBI_SIZE + CONFIG_UBOOTPATH +-CONFIG_UBOOT_ENABLE_PADS_ALL + CONFIG_UBOOT_SECTOR_COUNT + CONFIG_UBOOT_SECTOR_START + CONFIG_UDP_CHECKSUM +@@ -3374,7 +3036,6 @@ + CONFIG_USB_EHCI_EXYNOS + CONFIG_USB_EHCI_FARADAY + CONFIG_USB_EHCI_KIRKWOOD +-CONFIG_USB_EHCI_MXC + CONFIG_USB_EHCI_MXS + CONFIG_USB_EHCI_TXFIFO_THRESH + CONFIG_USB_ETH_QMULT +@@ -3413,7 +3074,6 @@ + CONFIG_USB_TUSB_OMAP_DMA + CONFIG_USB_ULPI_TIMEOUT + CONFIG_USB_XHCI_EXYNOS +-CONFIG_USB_XHCI_OMAP + CONFIG_USER_LOWLEVEL_INIT + CONFIG_USE_INTERRUPT + CONFIG_USE_ONENAND_BOARD_INIT +@@ -3423,7 +3083,6 @@ + CONFIG_VAL + CONFIG_VAR_SIZE_SPL + CONFIG_VERY_BIG_RAM +-CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP + CONFIG_VIDEO_BCM2835 + CONFIG_VIDEO_BMP_LOGO + CONFIG_VIDEO_DA8XX +diff -ruN u-boot-2021.10/scripts/dtc/treesource.c u-boot/scripts/dtc/treesource.c +--- u-boot-2021.10/scripts/dtc/treesource.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/dtc/treesource.c 2021-11-01 17:10:14.732900114 +0100 +@@ -281,4 +281,3 @@ + + write_tree_source_node(f, dti->dt, 0); + } +- +diff -ruN u-boot-2021.10/scripts/kconfig/expr.c u-boot/scripts/kconfig/expr.c +--- u-boot-2021.10/scripts/kconfig/expr.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/kconfig/expr.c 2021-11-01 17:10:14.732900114 +0100 +@@ -894,7 +894,7 @@ + default: + ; + } +- return false; ++ return false; + } + + /* +diff -ruN u-boot-2021.10/scripts/kconfig/gconf.c u-boot/scripts/kconfig/gconf.c +--- u-boot-2021.10/scripts/kconfig/gconf.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/kconfig/gconf.c 2021-11-01 17:10:14.732900114 +0100 +@@ -639,7 +639,7 @@ + void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data) + { + GtkWidget *dialog; +- const gchar *intro_text = ++ const gchar *intro_text = + "Welcome to gkc, the GTK+ graphical configuration tool\n" + "For each option, a blank box indicates the feature is disabled, a\n" + "check indicates it is enabled, and a dot indicates that it is to\n" +diff -ruN u-boot-2021.10/scripts/kconfig/list.h u-boot/scripts/kconfig/list.h +--- u-boot-2021.10/scripts/kconfig/list.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/kconfig/list.h 2021-11-01 17:10:14.736233265 +0100 +@@ -48,7 +48,7 @@ + */ + #define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ +- &pos->member != (head); \ ++ &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + + /** +diff -ruN u-boot-2021.10/scripts/kconfig/Makefile u-boot/scripts/kconfig/Makefile +--- u-boot-2021.10/scripts/kconfig/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/kconfig/Makefile 2021-11-01 17:10:14.732900114 +0100 +@@ -50,7 +50,7 @@ + + localyesconfig localmodconfig: $(obj)/conf + $(Q)perl $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config +- $(Q)if [ -f .config ]; then \ ++ $(Q)if [ -f .config ]; then \ + cmp -s .tmp.config .config || \ + (mv -f .config .config.old.1; \ + mv -f .tmp.config .config; \ +diff -ruN u-boot-2021.10/scripts/Makefile.spl u-boot/scripts/Makefile.spl +--- u-boot-2021.10/scripts/Makefile.spl 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/scripts/Makefile.spl 2021-11-01 17:10:14.726233812 +0100 +@@ -108,7 +108,7 @@ + libs-y += dts/ + libs-y += fs/ + libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ +-libs-$(CONFIG_SPL_NET_SUPPORT) += net/ ++libs-$(CONFIG_SPL_NET) += net/ + libs-$(CONFIG_SPL_UNIT_TEST) += test/ + + head-y := $(addprefix $(obj)/,$(head-y)) +@@ -260,6 +260,10 @@ + endif + endif + ++ifdef CONFIG_TARGET_SUNXI ++INPUTS-y += $(obj)/sunxi-spl.bin ++endif ++ + ifeq ($(CONFIG_SYS_SOC),"at91") + INPUTS-y += $(obj)/boot.bin + endif +@@ -295,18 +299,15 @@ + FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit + endif + +-# Build the .dtb file if: +-# - we are not using OF_PLATDATA +-# - we are using OF_CONTROL ++# Build the .dtb file if needed ++# - OF_REAL is enabled + # - we have either OF_SEPARATE or OF_HOSTFILE + build_dtb := +-ifeq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA),) +-ifneq ($(CONFIG_$(SPL_TPL_)OF_CONTROL),) ++ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),) + ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y) + build_dtb := y + endif + endif +-endif + + ifneq ($(build_dtb),) + $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ +@@ -414,7 +415,10 @@ + $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE + $(call if_changed,mkimage) + +-MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ ++MKIMAGEFLAGS_sunxi-spl.bin = \ ++ -A $(ARCH) \ ++ -T $(CONFIG_SPL_IMAGE_TYPE) \ ++ -a $(CONFIG_SPL_TEXT_BASE) \ + -n $(CONFIG_DEFAULT_DEVICE_TREE) + + OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) +diff -ruN u-boot-2021.10/scripts/spdxcheck.py u-boot/scripts/spdxcheck.py +--- u-boot-2021.10/scripts/spdxcheck.py 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/scripts/spdxcheck.py 2021-11-01 17:10:14.739566416 +0100 +@@ -0,0 +1,296 @@ ++#!/usr/bin/env python3 ++# SPDX-License-Identifier: GPL-2.0 ++# Copyright Thomas Gleixner <tglx@linutronix.de> ++ ++from argparse import ArgumentParser ++from ply import lex, yacc ++import locale ++import traceback ++import sys ++import git ++import re ++import os ++ ++class ParserException(Exception): ++ def __init__(self, tok, txt): ++ self.tok = tok ++ self.txt = txt ++ ++class SPDXException(Exception): ++ def __init__(self, el, txt): ++ self.el = el ++ self.txt = txt ++ ++class SPDXdata(object): ++ def __init__(self): ++ self.license_files = 0 ++ self.exception_files = 0 ++ self.licenses = [ ] ++ self.exceptions = { } ++ ++# Read the spdx data from the LICENSES directory ++def read_spdxdata(repo): ++ ++ # The subdirectories of LICENSES in the kernel source ++ # Note: exceptions needs to be parsed as last directory. ++ license_dirs = [ "preferred", "dual", "deprecated", "exceptions" ] ++ lictree = repo.head.commit.tree['LICENSES'] ++ ++ spdx = SPDXdata() ++ ++ for d in license_dirs: ++ for el in lictree[d].traverse(): ++ if not os.path.isfile(el.path): ++ continue ++ ++ exception = None ++ for l in open(el.path).readlines(): ++ if l.startswith('Valid-License-Identifier:'): ++ lid = l.split(':')[1].strip().upper() ++ if lid in spdx.licenses: ++ raise SPDXException(el, 'Duplicate License Identifier: %s' %lid) ++ else: ++ spdx.licenses.append(lid) ++ ++ elif l.startswith('SPDX-Exception-Identifier:'): ++ exception = l.split(':')[1].strip().upper() ++ spdx.exceptions[exception] = [] ++ ++ elif l.startswith('SPDX-Licenses:'): ++ for lic in l.split(':')[1].upper().strip().replace(' ', '').replace('\t', '').split(','): ++ if not lic in spdx.licenses: ++ raise SPDXException(None, 'Exception %s missing license %s' %(exception, lic)) ++ spdx.exceptions[exception].append(lic) ++ ++ elif l.startswith("License-Text:"): ++ if exception: ++ if not len(spdx.exceptions[exception]): ++ raise SPDXException(el, 'Exception %s is missing SPDX-Licenses' %exception) ++ spdx.exception_files += 1 ++ else: ++ spdx.license_files += 1 ++ break ++ return spdx ++ ++class id_parser(object): ++ ++ reserved = [ 'AND', 'OR', 'WITH' ] ++ tokens = [ 'LPAR', 'RPAR', 'ID', 'EXC' ] + reserved ++ ++ precedence = ( ('nonassoc', 'AND', 'OR'), ) ++ ++ t_ignore = ' \t' ++ ++ def __init__(self, spdx): ++ self.spdx = spdx ++ self.lasttok = None ++ self.lastid = None ++ self.lexer = lex.lex(module = self, reflags = re.UNICODE) ++ # Initialize the parser. No debug file and no parser rules stored on disk ++ # The rules are small enough to be generated on the fly ++ self.parser = yacc.yacc(module = self, write_tables = False, debug = False) ++ self.lines_checked = 0 ++ self.checked = 0 ++ self.spdx_valid = 0 ++ self.spdx_errors = 0 ++ self.curline = 0 ++ self.deepest = 0 ++ ++ # Validate License and Exception IDs ++ def validate(self, tok): ++ id = tok.value.upper() ++ if tok.type == 'ID': ++ if not id in self.spdx.licenses: ++ raise ParserException(tok, 'Invalid License ID') ++ self.lastid = id ++ elif tok.type == 'EXC': ++ if id not in self.spdx.exceptions: ++ raise ParserException(tok, 'Invalid Exception ID') ++ if self.lastid not in self.spdx.exceptions[id]: ++ raise ParserException(tok, 'Exception not valid for license %s' %self.lastid) ++ self.lastid = None ++ elif tok.type != 'WITH': ++ self.lastid = None ++ ++ # Lexer functions ++ def t_RPAR(self, tok): ++ r'\)' ++ self.lasttok = tok.type ++ return tok ++ ++ def t_LPAR(self, tok): ++ r'\(' ++ self.lasttok = tok.type ++ return tok ++ ++ def t_ID(self, tok): ++ r'[A-Za-z.0-9\-+]+' ++ ++ if self.lasttok == 'EXC': ++ print(tok) ++ raise ParserException(tok, 'Missing parentheses') ++ ++ tok.value = tok.value.strip() ++ val = tok.value.upper() ++ ++ if val in self.reserved: ++ tok.type = val ++ elif self.lasttok == 'WITH': ++ tok.type = 'EXC' ++ ++ self.lasttok = tok.type ++ self.validate(tok) ++ return tok ++ ++ def t_error(self, tok): ++ raise ParserException(tok, 'Invalid token') ++ ++ def p_expr(self, p): ++ '''expr : ID ++ | ID WITH EXC ++ | expr AND expr ++ | expr OR expr ++ | LPAR expr RPAR''' ++ pass ++ ++ def p_error(self, p): ++ if not p: ++ raise ParserException(None, 'Unfinished license expression') ++ else: ++ raise ParserException(p, 'Syntax error') ++ ++ def parse(self, expr): ++ self.lasttok = None ++ self.lastid = None ++ self.parser.parse(expr, lexer = self.lexer) ++ ++ def parse_lines(self, fd, maxlines, fname): ++ self.checked += 1 ++ self.curline = 0 ++ try: ++ for line in fd: ++ line = line.decode(locale.getpreferredencoding(False), errors='ignore') ++ self.curline += 1 ++ if self.curline > maxlines: ++ break ++ self.lines_checked += 1 ++ if line.find("SPDX-License-Identifier:") < 0: ++ continue ++ expr = line.split(':')[1].strip() ++ # Remove trailing comment closure ++ if line.strip().endswith('*/'): ++ expr = expr.rstrip('*/').strip() ++ # Remove trailing xml comment closure ++ if line.strip().endswith('-->'): ++ expr = expr.rstrip('-->').strip() ++ # Special case for SH magic boot code files ++ if line.startswith('LIST \"'): ++ expr = expr.rstrip('\"').strip() ++ self.parse(expr) ++ self.spdx_valid += 1 ++ # ++ # Should we check for more SPDX ids in the same file and ++ # complain if there are any? ++ # ++ break ++ ++ except ParserException as pe: ++ if pe.tok: ++ col = line.find(expr) + pe.tok.lexpos ++ tok = pe.tok.value ++ sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok)) ++ else: ++ sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, col, pe.txt)) ++ self.spdx_errors += 1 ++ ++def scan_git_tree(tree): ++ for el in tree.traverse(): ++ # Exclude stuff which would make pointless noise ++ # FIXME: Put this somewhere more sensible ++ if el.path.startswith("LICENSES"): ++ continue ++ if el.path.find("license-rules.rst") >= 0: ++ continue ++ if not os.path.isfile(el.path): ++ continue ++ with open(el.path, 'rb') as fd: ++ parser.parse_lines(fd, args.maxlines, el.path) ++ ++def scan_git_subtree(tree, path): ++ for p in path.strip('/').split('/'): ++ tree = tree[p] ++ scan_git_tree(tree) ++ ++if __name__ == '__main__': ++ ++ ap = ArgumentParser(description='SPDX expression checker') ++ ap.add_argument('path', nargs='*', help='Check path or file. If not given full git tree scan. For stdin use "-"') ++ ap.add_argument('-m', '--maxlines', type=int, default=15, ++ help='Maximum number of lines to scan in a file. Default 15') ++ ap.add_argument('-v', '--verbose', action='store_true', help='Verbose statistics output') ++ args = ap.parse_args() ++ ++ # Sanity check path arguments ++ if '-' in args.path and len(args.path) > 1: ++ sys.stderr.write('stdin input "-" must be the only path argument\n') ++ sys.exit(1) ++ ++ try: ++ # Use git to get the valid license expressions ++ repo = git.Repo(os.getcwd()) ++ assert not repo.bare ++ ++ # Initialize SPDX data ++ spdx = read_spdxdata(repo) ++ ++ # Initialize the parser ++ parser = id_parser(spdx) ++ ++ except SPDXException as se: ++ if se.el: ++ sys.stderr.write('%s: %s\n' %(se.el.path, se.txt)) ++ else: ++ sys.stderr.write('%s\n' %se.txt) ++ sys.exit(1) ++ ++ except Exception as ex: ++ sys.stderr.write('FAIL: %s\n' %ex) ++ sys.stderr.write('%s\n' %traceback.format_exc()) ++ sys.exit(1) ++ ++ try: ++ if len(args.path) and args.path[0] == '-': ++ stdin = os.fdopen(sys.stdin.fileno(), 'rb') ++ parser.parse_lines(stdin, args.maxlines, '-') ++ else: ++ if args.path: ++ for p in args.path: ++ if os.path.isfile(p): ++ parser.parse_lines(open(p, 'rb'), args.maxlines, p) ++ elif os.path.isdir(p): ++ scan_git_subtree(repo.head.reference.commit.tree, p) ++ else: ++ sys.stderr.write('path %s does not exist\n' %p) ++ sys.exit(1) ++ else: ++ # Full git tree scan ++ scan_git_tree(repo.head.commit.tree) ++ ++ if args.verbose: ++ sys.stderr.write('\n') ++ sys.stderr.write('License files: %12d\n' %spdx.license_files) ++ sys.stderr.write('Exception files: %12d\n' %spdx.exception_files) ++ sys.stderr.write('License IDs %12d\n' %len(spdx.licenses)) ++ sys.stderr.write('Exception IDs %12d\n' %len(spdx.exceptions)) ++ sys.stderr.write('\n') ++ sys.stderr.write('Files checked: %12d\n' %parser.checked) ++ sys.stderr.write('Lines checked: %12d\n' %parser.lines_checked) ++ sys.stderr.write('Files with SPDX: %12d\n' %parser.spdx_valid) ++ sys.stderr.write('Files with errors: %12d\n' %parser.spdx_errors) ++ ++ sys.exit(0) ++ ++ except Exception as ex: ++ sys.stderr.write('FAIL: %s\n' %ex) ++ sys.stderr.write('%s\n' %traceback.format_exc()) ++ sys.exit(1) +diff -ruN u-boot-2021.10/test/bloblist.c u-boot/test/bloblist.c +--- u-boot-2021.10/test/bloblist.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/bloblist.c 2021-11-01 17:10:14.739566416 +0100 +@@ -14,7 +14,7 @@ + + DECLARE_GLOBAL_DATA_PTR; + +-/* Declare a new compression test */ ++/* Declare a new bloblist test */ + #define BLOBLIST_TEST(_name, _flags) \ + UNIT_TEST(_name, _flags, bloblist_test) + +diff -ruN u-boot-2021.10/test/dm/acpi.c u-boot/test/dm/acpi.c +--- u-boot-2021.10/test/dm/acpi.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/acpi.c 2021-11-01 17:10:14.742899567 +0100 +@@ -11,6 +11,7 @@ + #include <dm.h> + #include <malloc.h> + #include <mapmem.h> ++#include <timestamp.h> + #include <version.h> + #include <tables_csum.h> + #include <version.h> +@@ -25,6 +26,14 @@ + + #define BUF_SIZE 4096 + ++#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ ++ (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ ++ (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ ++ ((U_BOOT_VERSION_NUM % 10) << 16) | \ ++ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ ++ ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ ++ 0x01) ++ + /** + * struct testacpi_plat - Platform data for the test ACPI device + * +@@ -218,7 +227,7 @@ + ut_asserteq_mem(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id)); + ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id, + sizeof(hdr.oem_table_id)); +- ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision); ++ ut_asserteq(OEM_REVISION, hdr.oem_revision); + ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id)); + ut_asserteq(0x44, hdr.aslc_revision); + +@@ -365,20 +374,20 @@ + addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); + ut_assert_nextline("RSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", + addr, sizeof(struct acpi_table_header) + +- 3 * sizeof(u32), U_BOOT_BUILD_DATE); ++ 3 * sizeof(u32), OEM_REVISION); + addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); + ut_assert_nextline("XSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", + addr, sizeof(struct acpi_table_header) + +- 3 * sizeof(u64), U_BOOT_BUILD_DATE); ++ 3 * sizeof(u64), OEM_REVISION); + addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); + ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", +- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); ++ addr, sizeof(struct acpi_dmar), OEM_REVISION); + addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); + ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", +- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); ++ addr, sizeof(struct acpi_dmar), OEM_REVISION); + addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); + ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", +- addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); ++ addr, sizeof(struct acpi_dmar), OEM_REVISION); + ut_assert_console_end(); + + return 0; +diff -ruN u-boot-2021.10/test/dm/cpu.c u-boot/test/dm/cpu.c +--- u-boot-2021.10/test/dm/cpu.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/cpu.c 2021-11-01 17:10:14.742899567 +0100 +@@ -27,7 +27,7 @@ + uclass_find_next_device(&dev)) + ut_assert(dev_get_flags(dev) & DM_FLAG_ACTIVATED); + +- ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu-test1", &dev)); ++ ut_assertok(uclass_get_device_by_name(UCLASS_CPU, "cpu@1", &dev)); + ut_asserteq_ptr(cpu_get_current_dev(), dev); + ut_asserteq(cpu_is_current(dev), 1); + +diff -ruN u-boot-2021.10/test/dm/dsa.c u-boot/test/dm/dsa.c +--- u-boot-2021.10/test/dm/dsa.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/dsa.c 2021-11-01 17:10:14.742899567 +0100 +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Copyright 2020-2021 NXP Semiconductors ++ * Copyright 2020-2021 NXP + */ + + #include <net/dsa.h> +diff -ruN u-boot-2021.10/test/dm/k210_pll.c u-boot/test/dm/k210_pll.c +--- u-boot-2021.10/test/dm/k210_pll.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/k210_pll.c 2021-11-01 17:10:14.742899567 +0100 +@@ -69,27 +69,25 @@ + &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_config(1500000000, 20000000, + &theirs)); ++ ut_asserteq(-EINVAL, k210_pll_calc_config(1750000000, 13300000, ++ &theirs)); + + /* Verify we get the same output with brute-force */ +- ut_assertok(dm_test_k210_pll_calc_config(390000000, 26000000, &ours)); +- ut_assertok(k210_pll_calc_config(390000000, 26000000, &theirs)); +- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); +- +- ut_assertok(dm_test_k210_pll_calc_config(26000000, 390000000, &ours)); +- ut_assertok(k210_pll_calc_config(26000000, 390000000, &theirs)); +- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); +- +- ut_assertok(dm_test_k210_pll_calc_config(400000000, 26000000, &ours)); +- ut_assertok(k210_pll_calc_config(400000000, 26000000, &theirs)); +- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); +- +- ut_assertok(dm_test_k210_pll_calc_config(27000000, 26000000, &ours)); +- ut_assertok(k210_pll_calc_config(27000000, 26000000, &theirs)); +- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); +- +- ut_assertok(dm_test_k210_pll_calc_config(26000000, 27000000, &ours)); +- ut_assertok(k210_pll_calc_config(26000000, 27000000, &theirs)); +- ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); ++#define compare(rate, rate_in) do { \ ++ ut_assertok(dm_test_k210_pll_calc_config(rate, rate_in, &ours)); \ ++ ut_assertok(k210_pll_calc_config(rate, rate_in, &theirs)); \ ++ ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); \ ++} while (0) ++ ++ compare(390000000, 26000000); ++ compare(26000000, 390000000); ++ compare(400000000, 26000000); ++ compare(27000000, 26000000); ++ compare(26000000, 27000000); ++ compare(13300000 * 64, 13300000); ++ compare(21250000, 21250000 * 70); ++ compare(21250000, 1750000000); ++ compare(1750000000, 1750000000); + + return 0; + } +diff -ruN u-boot-2021.10/test/dm/ofnode.c u-boot/test/dm/ofnode.c +--- u-boot-2021.10/test/dm/ofnode.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/ofnode.c 2021-11-01 17:10:14.746232718 +0100 +@@ -318,3 +318,18 @@ + return 0; + } + DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); ++ ++static int dm_test_ofnode_conf(struct unit_test_state *uts) ++{ ++ ut_assert(!ofnode_conf_read_bool("missing")); ++ ut_assert(ofnode_conf_read_bool("testing-bool")); ++ ++ ut_asserteq(123, ofnode_conf_read_int("testing-int", 0)); ++ ut_asserteq(6, ofnode_conf_read_int("missing", 6)); ++ ++ ut_assertnull(ofnode_conf_read_str("missing")); ++ ut_asserteq_str("testing", ofnode_conf_read_str("testing-str")); ++ ++ return 0; ++} ++DM_TEST(dm_test_ofnode_conf, 0); +diff -ruN u-boot-2021.10/test/dm/of_platdata.c u-boot/test/dm/of_platdata.c +--- u-boot-2021.10/test/dm/of_platdata.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/of_platdata.c 2021-11-01 17:10:14.746232718 +0100 +@@ -1,11 +1,14 @@ + // SPDX-License-Identifier: GPL-2.0+ + + #include <common.h> ++#include <clk.h> + #include <dm.h> + #include <dt-structs.h> ++#include <irq.h> + #include <dm/test.h> + #include <test/test.h> + #include <test/ut.h> ++#include <asm-generic/gpio.h> + #include <asm/global_data.h> + + /* Test that we can find a device using of-platdata */ +@@ -27,11 +30,9 @@ + struct udevice *dev; + int i; + +- /* Skip the clock */ +- ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); +- ut_asserteq_str("sandbox_clk_test", dev->name); ++ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_spl_test", ++ &dev)); + +- ut_assertok(uclass_next_device_err(&dev)); + plat = dev_get_plat(dev); + ut_assert(plat->boolval); + ut_asserteq(1, plat->intval); +@@ -222,3 +223,59 @@ + } + DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA); + #endif ++ ++/* Test clocks with of-platdata */ ++static int dm_test_of_plat_clk(struct unit_test_state *uts) ++{ ++ struct dtd_sandbox_clk_test *plat; ++ struct udevice *dev; ++ struct clk clk; ++ ++ ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev)); ++ ut_asserteq_str("sandbox_clk_test", dev->name); ++ plat = dev_get_plat(dev); ++ ++ ut_assertok(clk_get_by_phandle(dev, &plat->clocks[0], &clk)); ++ ut_asserteq_str("sandbox_fixed_clock", clk.dev->name); ++ ++ return 0; ++} ++DM_TEST(dm_test_of_plat_clk, UT_TESTF_SCAN_PDATA); ++ ++/* Test irqs with of-platdata */ ++static int dm_test_of_plat_irq(struct unit_test_state *uts) ++{ ++ struct dtd_sandbox_irq_test *plat; ++ struct udevice *dev; ++ struct irq irq; ++ ++ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_irq_test", ++ &dev)); ++ plat = dev_get_plat(dev); ++ ++ ut_assertok(irq_get_by_phandle(dev, &plat->interrupts_extended[0], ++ &irq)); ++ ut_asserteq_str("sandbox_irq", irq.dev->name); ++ ++ return 0; ++} ++DM_TEST(dm_test_of_plat_irq, UT_TESTF_SCAN_PDATA); ++ ++/* Test GPIOs with of-platdata */ ++static int dm_test_of_plat_gpio(struct unit_test_state *uts) ++{ ++ struct dtd_sandbox_gpio_test *plat; ++ struct udevice *dev; ++ struct gpio_desc desc; ++ ++ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "sandbox_gpio_test", ++ &dev)); ++ plat = dev_get_plat(dev); ++ ++ ut_assertok(gpio_request_by_phandle(dev, &plat->test_gpios[0], &desc, ++ GPIOD_IS_OUT)); ++ ut_asserteq_str("sandbox_gpio", desc.dev->name); ++ ++ return 0; ++} ++DM_TEST(dm_test_of_plat_gpio, UT_TESTF_SCAN_PDATA); +diff -ruN u-boot-2021.10/test/dm/pci_ep.c u-boot/test/dm/pci_ep.c +--- u-boot-2021.10/test/dm/pci_ep.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/pci_ep.c 2021-11-01 17:10:14.746232718 +0100 +@@ -62,4 +62,3 @@ + } + + DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +- +diff -ruN u-boot-2021.10/test/dm/smem.c u-boot/test/dm/smem.c +--- u-boot-2021.10/test/dm/smem.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/smem.c 2021-11-01 17:10:14.746232718 +0100 +@@ -25,4 +25,3 @@ + return 0; + } + DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +- +diff -ruN u-boot-2021.10/test/dm/timer.c u-boot/test/dm/timer.c +--- u-boot-2021.10/test/dm/timer.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/timer.c 2021-11-01 17:10:14.746232718 +0100 +@@ -33,16 +33,16 @@ + { + struct udevice *dev; + +- cpu_sandbox_set_current("cpu-test1"); ++ cpu_sandbox_set_current("cpu@1"); + ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev)); + ut_asserteq(3000000, timer_get_rate(dev)); + ut_assertok(device_remove(dev, DM_REMOVE_NORMAL)); + +- cpu_sandbox_set_current("cpu-test2"); ++ cpu_sandbox_set_current("cpu@2"); + ut_assertok(uclass_get_device_by_name(UCLASS_TIMER, "timer@1", &dev)); + ut_asserteq(2000000, timer_get_rate(dev)); + +- cpu_sandbox_set_current("cpu-test1"); ++ cpu_sandbox_set_current("cpu@1"); + + return 0; + } +diff -ruN u-boot-2021.10/test/dm/wdt.c u-boot/test/dm/wdt.c +--- u-boot-2021.10/test/dm/wdt.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/dm/wdt.c 2021-11-01 17:10:14.746232718 +0100 +@@ -6,11 +6,14 @@ + #include <common.h> + #include <dm.h> + #include <wdt.h> ++#include <asm/gpio.h> + #include <asm/state.h> + #include <asm/test.h> + #include <dm/test.h> + #include <test/test.h> + #include <test/ut.h> ++#include <linux/delay.h> ++#include <watchdog.h> + + /* Test that watchdog driver functions are called */ + static int dm_test_wdt_base(struct unit_test_state *uts) +@@ -19,7 +22,8 @@ + struct udevice *dev; + const u64 timeout = 42; + +- ut_assertok(uclass_get_device(UCLASS_WDT, 0, &dev)); ++ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, ++ DM_DRIVER_GET(wdt_sandbox), &dev)); + ut_assertnonnull(dev); + ut_asserteq(0, state->wdt.counter); + ut_asserteq(false, state->wdt.running); +@@ -39,3 +43,87 @@ + return 0; + } + DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); ++ ++static int dm_test_wdt_gpio(struct unit_test_state *uts) ++{ ++ /* ++ * The sandbox wdt gpio is "connected" to gpio bank a, offset ++ * 7. Use the sandbox back door to verify that the gpio-wdt ++ * driver behaves as expected. ++ */ ++ struct udevice *wdt, *gpio; ++ const u64 timeout = 42; ++ const int offset = 7; ++ int val; ++ ++ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, ++ DM_DRIVER_GET(wdt_gpio), &wdt)); ++ ut_assertnonnull(wdt); ++ ++ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio)); ++ ut_assertnonnull(gpio); ++ ut_assertok(wdt_start(wdt, timeout, 0)); ++ ++ val = sandbox_gpio_get_value(gpio, offset); ++ ut_assertok(wdt_reset(wdt)); ++ ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset)); ++ ut_assertok(wdt_reset(wdt)); ++ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); ++ ++ ut_asserteq(-ENOSYS, wdt_stop(wdt)); ++ ++ return 0; ++} ++DM_TEST(dm_test_wdt_gpio, UT_TESTF_SCAN_FDT); ++ ++static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts) ++{ ++ struct sandbox_state *state = state_get_current(); ++ struct udevice *gpio_wdt, *sandbox_wdt; ++ struct udevice *gpio; ++ const u64 timeout = 42; ++ const int offset = 7; ++ uint reset_count; ++ int val; ++ ++ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, ++ DM_DRIVER_GET(wdt_gpio), &gpio_wdt)); ++ ut_assertnonnull(gpio_wdt); ++ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT, ++ DM_DRIVER_GET(wdt_sandbox), &sandbox_wdt)); ++ ut_assertnonnull(sandbox_wdt); ++ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio)); ++ ut_assertnonnull(gpio); ++ ++ /* Neither device should be "started", so watchdog_reset() should be a no-op. */ ++ reset_count = state->wdt.reset_count; ++ val = sandbox_gpio_get_value(gpio, offset); ++ watchdog_reset(); ++ ut_asserteq(reset_count, state->wdt.reset_count); ++ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); ++ ++ /* Start both devices. */ ++ ut_assertok(wdt_start(gpio_wdt, timeout, 0)); ++ ut_assertok(wdt_start(sandbox_wdt, timeout, 0)); ++ ++ /* Make sure both devices have just been pinged. */ ++ timer_test_add_offset(100); ++ watchdog_reset(); ++ reset_count = state->wdt.reset_count; ++ val = sandbox_gpio_get_value(gpio, offset); ++ ++ /* The gpio watchdog should be pinged, the sandbox one not. */ ++ timer_test_add_offset(30); ++ watchdog_reset(); ++ ut_asserteq(reset_count, state->wdt.reset_count); ++ ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset)); ++ ++ /* After another ~30ms, both devices should get pinged. */ ++ timer_test_add_offset(30); ++ watchdog_reset(); ++ ut_asserteq(reset_count + 1, state->wdt.reset_count); ++ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset)); ++ ++ return 0; ++} ++DM_TEST(dm_test_wdt_watchdog_reset, UT_TESTF_SCAN_FDT); +diff -ruN u-boot-2021.10/test/print_ut.c u-boot/test/print_ut.c +--- u-boot-2021.10/test/print_ut.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/print_ut.c 2021-11-01 17:10:14.749565869 +0100 +@@ -9,7 +9,7 @@ + #include <display_options.h> + #include <log.h> + #include <mapmem.h> +-#include <version.h> ++#include <version_string.h> + #include <test/suites.h> + #include <test/test.h> + #include <test/ut.h> +diff -ruN u-boot-2021.10/test/py/tests/test_fit_hashes.py u-boot/test/py/tests/test_fit_hashes.py +--- u-boot-2021.10/test/py/tests/test_fit_hashes.py 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/test/py/tests/test_fit_hashes.py 2021-11-01 17:10:14.752899021 +0100 +@@ -0,0 +1,111 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (c) 2021 Alexandru Gagniuc <mr.nuke.me@gmail.com> ++ ++""" ++Check hashes produced by mkimage against known values ++ ++This test checks the correctness of mkimage's hashes. by comparing the mkimage ++output of a fixed data block with known good hashes. ++This test doesn't run the sandbox. It only checks the host tool 'mkimage' ++""" ++ ++import pytest ++import u_boot_utils as util ++ ++kernel_hashes = { ++ "sha512" : "f18c1486a2c29f56360301576cdfce4dfd8e8e932d0ed8e239a1f314b8ae1d77b2a58cd7fe32e4075e69448e623ce53b0b6aa6ce5626d2c189a5beae29a68d93", ++ "sha384" : "16e28976740048485d08d793d8bf043ebc7826baf2bc15feac72825ad67530ceb3d09e0deb6932c62a5a0e9f3936baf4", ++ "sha256" : "2955c56bc1e5050c111ba6e089e0f5342bb47dedf77d87e3f429095feb98a7e5", ++ "sha1" : "652383e1a6d946953e1f65092c9435f6452c2ab7", ++ "md5" : "4879e5086e4c76128e525b5fe2af55f1", ++ "crc32" : "32eddfdf", ++ "crc16-ccitt" : "d4be" ++} ++ ++class ReadonlyFitImage(object): ++ """ Helper to manipulate a FIT image on disk """ ++ def __init__(self, cons, file_name): ++ self.fit = file_name ++ self.cons = cons ++ self.hashable_nodes = set() ++ ++ def __fdt_list(self, path): ++ return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}') ++ ++ def __fdt_get(self, node, prop): ++ val = util.run_and_log(self.cons, f'fdtget {self.fit} {node} {prop}') ++ return val.rstrip('\n') ++ ++ def __fdt_get_sexadecimal(self, node, prop): ++ numbers = util.run_and_log(self.cons, f'fdtget -tbx {self.fit} {node} {prop}') ++ ++ sexadecimal = '' ++ for num in numbers.rstrip('\n').split(' '): ++ sexadecimal += num.zfill(2) ++ return sexadecimal ++ ++ def find_hashable_image_nodes(self): ++ for node in self.__fdt_list('/images').split(): ++ # We only have known hashes for the kernel node ++ if 'kernel' not in node: ++ continue ++ self.hashable_nodes.add(f'/images/{node}') ++ ++ return self.hashable_nodes ++ ++ def verify_hashes(self): ++ for image in self.hashable_nodes: ++ algos = set() ++ for node in self.__fdt_list(image).split(): ++ if "hash-" not in node: ++ continue ++ ++ raw_hash = self.__fdt_get_sexadecimal(f'{image}/{node}', 'value') ++ algo = self.__fdt_get(f'{image}/{node}', 'algo') ++ algos.add(algo) ++ ++ good_hash = kernel_hashes[algo] ++ if good_hash != raw_hash: ++ raise ValueError(f'{image} Borked hash: {algo}'); ++ ++ # Did we test all the hashes we set out to test? ++ missing_algos = kernel_hashes.keys() - algos ++ if (missing_algos): ++ raise ValueError(f'Missing hashes from FIT: {missing_algos}') ++ ++ ++@pytest.mark.buildconfigspec('hash') ++@pytest.mark.requiredtool('dtc') ++@pytest.mark.requiredtool('fdtget') ++@pytest.mark.requiredtool('fdtput') ++def test_mkimage_hashes(u_boot_console): ++ """ Test that hashes generated by mkimage are correct. """ ++ ++ def assemble_fit_image(dest_fit, its, destdir): ++ dtc_args = f'-I dts -O dtb -i {destdir}' ++ util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit]) ++ ++ def dtc(dts): ++ dtb = dts.replace('.dts', '.dtb') ++ util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}') ++ ++ cons = u_boot_console ++ mkimage = cons.config.build_dir + '/tools/mkimage' ++ datadir = cons.config.source_dir + '/test/py/tests/vboot/' ++ tempdir = cons.config.result_dir ++ fit_file = f'{tempdir}/test.fit' ++ dtc('sandbox-kernel.dts') ++ ++ # Create a fake kernel image -- Avoid zeroes or crc16 will be zero ++ with open(f'{tempdir}/test-kernel.bin', 'w') as fd: ++ fd.write(500 * chr(0xa5)) ++ ++ assemble_fit_image(fit_file, f'{datadir}/hash-images.its', tempdir) ++ ++ fit = ReadonlyFitImage(cons, fit_file) ++ nodes = fit.find_hashable_image_nodes() ++ if len(nodes) == 0: ++ raise ValueError('FIT image has no "/image" nodes with "hash-..."') ++ ++ fit.verify_hashes() +diff -ruN u-boot-2021.10/test/py/tests/test_hush_if_test.py u-boot/test/py/tests/test_hush_if_test.py +--- u-boot-2021.10/test/py/tests/test_hush_if_test.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/py/tests/test_hush_if_test.py 2021-11-01 17:10:14.752899021 +0100 +@@ -119,11 +119,6 @@ + ('test ! ! aaa != aaa -o ! ! bbb = bbb', True), + ('test ! ! aaa = aaa -o ! ! bbb != bbb', True), + ('test ! ! aaa = aaa -o ! ! bbb = bbb', True), +- +- # -z operator. +- +- ('test -z "$ut_var_nonexistent"', True), +- ('test -z "$ut_var_exists"', False), + ) + + def exec_hush_if(u_boot_console, expr, result): +@@ -141,12 +136,6 @@ + response = u_boot_console.run_command(cmd) + assert response.strip() == str(result).lower() + +-def test_hush_if_test_setup(u_boot_console): +- """Set up environment variables used during the "if" tests.""" +- +- u_boot_console.run_command('setenv ut_var_nonexistent') +- u_boot_console.run_command('setenv ut_var_exists 1') +- + @pytest.mark.buildconfigspec('cmd_echo') + @pytest.mark.parametrize('expr,result', subtests) + def test_hush_if_test(u_boot_console, expr, result): +@@ -154,9 +143,12 @@ + + exec_hush_if(u_boot_console, expr, result) + +-def test_hush_if_test_teardown(u_boot_console): +- """Clean up environment variables used during the "if" tests.""" +- ++def test_hush_z(u_boot_console): ++ """Test the -z operator""" ++ u_boot_console.run_command('setenv ut_var_nonexistent') ++ u_boot_console.run_command('setenv ut_var_exists 1') ++ exec_hush_if(u_boot_console, 'test -z "$ut_var_nonexistent"', True) ++ exec_hush_if(u_boot_console, 'test -z "$ut_var_exists"', False) + u_boot_console.run_command('setenv ut_var_exists') + + # We might test this on real filesystems via UMS, DFU, 'save', etc. +diff -ruN u-boot-2021.10/test/py/tests/test_tpm2.py u-boot/test/py/tests/test_tpm2.py +--- u-boot-2021.10/test/py/tests/test_tpm2.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/py/tests/test_tpm2.py 2021-11-01 17:10:14.756232171 +0100 +@@ -52,14 +52,17 @@ + u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM') + u_boot_console.run_command('echo --- end of init ---') + ++def is_sandbox(cons): ++ # Array slice removes leading/trailing quotes. ++ sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1] ++ return sys_arch == 'sandbox' ++ + @pytest.mark.buildconfigspec('cmd_tpm_v2') + def test_tpm2_init(u_boot_console): + """Init the software stack to use TPMv2 commands.""" +- + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') +- + u_boot_console.run_command('tpm2 init') + output = u_boot_console.run_command('echo $?') + assert output.endswith('0') +@@ -70,6 +73,19 @@ + + Initiate the TPM internal state machine. + """ ++ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR') ++ output = u_boot_console.run_command('echo $?') ++ assert output.endswith('0') ++ ++def tpm2_sandbox_init(u_boot_console): ++ """Put sandbox back into a known state so we can run a test ++ ++ This allows all tests to run in parallel, since no test depends on another. ++ """ ++ u_boot_console.restart_uboot() ++ u_boot_console.run_command('tpm2 init') ++ output = u_boot_console.run_command('echo $?') ++ assert output.endswith('0') + + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: +@@ -78,12 +94,25 @@ + output = u_boot_console.run_command('echo $?') + assert output.endswith('0') + ++ u_boot_console.run_command('tpm2 self_test full') ++ output = u_boot_console.run_command('echo $?') ++ assert output.endswith('0') ++ + @pytest.mark.buildconfigspec('cmd_tpm_v2') +-def test_tpm2_self_test_full(u_boot_console): ++def test_tpm2_sandbox_self_test_full(u_boot_console): + """Execute a TPM2_SelfTest (full) command. + + Ask the TPM to perform all self tests to also enable full capabilities. + """ ++ if is_sandbox(u_boot_console): ++ u_boot_console.restart_uboot() ++ u_boot_console.run_command('tpm2 init') ++ output = u_boot_console.run_command('echo $?') ++ assert output.endswith('0') ++ ++ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR') ++ output = u_boot_console.run_command('echo $?') ++ assert output.endswith('0') + + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: +@@ -103,6 +132,8 @@ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + u_boot_console.run_command('tpm2 self_test continue') + output = u_boot_console.run_command('echo $?') + assert output.endswith('0') +@@ -119,6 +150,8 @@ + not have a password set, otherwise this test will fail. ENDORSEMENT and + PLATFORM hierarchies are also available. + """ ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: +@@ -140,7 +173,8 @@ + Use the LOCKOUT hierarchy for this. ENDORSEMENT and PLATFORM hierarchies are + also available. + """ +- ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + force_init(u_boot_console) + + u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn') +@@ -164,6 +198,8 @@ + There is no expected default values because it would depend on the chip + used. We can still save them in order to check they have changed later. + """ ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + + force_init(u_boot_console) + ram = u_boot_utils.find_ram_base(u_boot_console) +@@ -186,7 +222,8 @@ + the authentication, otherwise the lockout will be engaged after the first + failed authentication attempt. + """ +- ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + force_init(u_boot_console) + ram = u_boot_utils.find_ram_base(u_boot_console) + +@@ -209,6 +246,8 @@ + + Perform a PCR read of the 0th PCR. Must be zero. + """ ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + + force_init(u_boot_console) + ram = u_boot_utils.find_ram_base(u_boot_console) +@@ -236,7 +275,8 @@ + No authentication mechanism is used here, not protecting against packet + replay, yet. + """ +- ++ if is_sandbox(u_boot_console): ++ tpm2_sandbox_init(u_boot_console) + force_init(u_boot_console) + ram = u_boot_utils.find_ram_base(u_boot_console) + +diff -ruN u-boot-2021.10/test/py/tests/test_vboot.py u-boot/test/py/tests/test_vboot.py +--- u-boot-2021.10/test/py/tests/test_vboot.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/py/tests/test_vboot.py 2021-11-01 17:10:14.756232171 +0100 +@@ -24,6 +24,7 @@ + Tests run with both SHA1 and SHA256 hashing. + """ + ++import os + import shutil + import struct + import pytest +@@ -34,16 +35,16 @@ + # Only run the full suite on a few combinations, since it doesn't add any more + # test coverage. + TESTDATA = [ +- ['sha1', '', None, False, True], +- ['sha1', '', '-E -p 0x10000', False, False], +- ['sha1', '-pss', None, False, False], +- ['sha1', '-pss', '-E -p 0x10000', False, False], +- ['sha256', '', None, False, False], +- ['sha256', '', '-E -p 0x10000', False, False], +- ['sha256', '-pss', None, False, False], +- ['sha256', '-pss', '-E -p 0x10000', False, False], +- ['sha256', '-pss', None, True, False], +- ['sha256', '-pss', '-E -p 0x10000', True, True], ++ ['sha1-basic', 'sha1', '', None, False, True], ++ ['sha1-pad', 'sha1', '', '-E -p 0x10000', False, False], ++ ['sha1-pss', 'sha1', '-pss', None, False, False], ++ ['sha1-pss-pad', 'sha1', '-pss', '-E -p 0x10000', False, False], ++ ['sha256-basic', 'sha256', '', None, False, False], ++ ['sha256-pad', 'sha256', '', '-E -p 0x10000', False, False], ++ ['sha256-pss', 'sha256', '-pss', None, False, False], ++ ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x10000', False, False], ++ ['sha256-pss-required', 'sha256', '-pss', None, True, False], ++ ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x10000', True, True], + ] + + @pytest.mark.boardspec('sandbox') +@@ -52,9 +53,9 @@ + @pytest.mark.requiredtool('fdtget') + @pytest.mark.requiredtool('fdtput') + @pytest.mark.requiredtool('openssl') +-@pytest.mark.parametrize("sha_algo,padding,sign_options,required,full_test", ++@pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test", + TESTDATA) +-def test_vboot(u_boot_console, sha_algo, padding, sign_options, required, ++def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required, + full_test): + """Test verified boot signing with mkimage and verification with 'bootm'. + +@@ -365,7 +366,9 @@ + run_bootm(sha_algo, 'multi required key', '', False) + + cons = u_boot_console +- tmpdir = cons.config.result_dir + '/' ++ tmpdir = os.path.join(cons.config.result_dir, name) + '/' ++ if not os.path.exists(tmpdir): ++ os.mkdir(tmpdir) + datadir = cons.config.source_dir + '/test/py/tests/vboot/' + fit = '%stest.fit' % tmpdir + mkimage = cons.config.build_dir + '/tools/mkimage' +diff -ruN u-boot-2021.10/test/py/tests/vboot/hash-images.its u-boot/test/py/tests/vboot/hash-images.its +--- u-boot-2021.10/test/py/tests/vboot/hash-images.its 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/test/py/tests/vboot/hash-images.its 2021-11-01 17:10:14.756232171 +0100 +@@ -0,0 +1,76 @@ ++/dts-v1/; ++ ++/ { ++ description = "Chrome OS kernel image with one or more FDT blobs"; ++ #address-cells = <1>; ++ ++ images { ++ kernel { ++ data = /incbin/("test-kernel.bin"); ++ type = "kernel_noload"; ++ arch = "sandbox"; ++ os = "linux"; ++ compression = "none"; ++ load = <0x4>; ++ entry = <0x8>; ++ kernel-version = <1>; ++ hash-0 { ++ algo = "crc16-ccitt"; ++ }; ++ hash-1 { ++ algo = "crc32"; ++ }; ++ hash-2 { ++ algo = "md5"; ++ }; ++ hash-3 { ++ algo = "sha1"; ++ }; ++ hash-4 { ++ algo = "sha256"; ++ }; ++ hash-5 { ++ algo = "sha384"; ++ }; ++ hash-6 { ++ algo = "sha512"; ++ }; ++ }; ++ fdt-1 { ++ description = "snow"; ++ data = /incbin/("sandbox-kernel.dtb"); ++ type = "flat_dt"; ++ arch = "sandbox"; ++ compression = "none"; ++ fdt-version = <1>; ++ hash-0 { ++ algo = "crc16-ccitt"; ++ }; ++ hash-1 { ++ algo = "crc32"; ++ }; ++ hash-2 { ++ algo = "md5"; ++ }; ++ hash-3 { ++ algo = "sha1"; ++ }; ++ hash-4 { ++ algo = "sha256"; ++ }; ++ hash-5 { ++ algo = "sha384"; ++ }; ++ hash-6 { ++ algo = "sha512"; ++ }; ++ }; ++ }; ++ configurations { ++ default = "conf-1"; ++ conf-1 { ++ kernel = "kernel"; ++ fdt = "fdt-1"; ++ }; ++ }; ++}; +diff -ruN u-boot-2021.10/test/py/u_boot_console_base.py u-boot/test/py/u_boot_console_base.py +--- u-boot-2021.10/test/py/u_boot_console_base.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/py/u_boot_console_base.py 2021-11-01 17:10:14.756232171 +0100 +@@ -351,13 +351,13 @@ + self.p.logfile_read = self.logstream + bcfg = self.config.buildconfig + config_spl = bcfg.get('config_spl', 'n') == 'y' +- config_spl_serial_support = bcfg.get('config_spl_serial_support', ++ config_spl_serial = bcfg.get('config_spl_serial', + 'n') == 'y' + env_spl_skipped = self.config.env.get('env__spl_skipped', + False) + env_spl2_skipped = self.config.env.get('env__spl2_skipped', + True) +- if config_spl and config_spl_serial_support and not env_spl_skipped: ++ if config_spl and config_spl_serial and not env_spl_skipped: + m = self.p.expect([pattern_u_boot_spl_signon] + + self.bad_patterns) + if m != 0: +diff -ruN u-boot-2021.10/test/ut.c u-boot/test/ut.c +--- u-boot-2021.10/test/ut.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/test/ut.c 2021-11-01 17:10:14.756232171 +0100 +@@ -121,6 +121,32 @@ + return 0; + } + ++int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...) ++{ ++ va_list args; ++ int len; ++ int ret; ++ ++ va_start(args, fmt); ++ len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); ++ va_end(args); ++ if (len >= sizeof(uts->expect_str)) { ++ ut_fail(uts, __FILE__, __LINE__, __func__, ++ "unit_test_state->expect_str too small"); ++ return -EOVERFLOW; ++ } ++ while (1) { ++ if (!console_record_avail()) ++ return -ENOENT; ++ ret = readline_check(uts); ++ if (ret < 0) ++ return ret; ++ ++ if (!strcmp(uts->expect_str, uts->actual_str)) ++ return 0; ++ } ++} ++ + int ut_check_console_end(struct unit_test_state *uts) + { + int ret; +diff -ruN u-boot-2021.10/tools/asn1_compiler.c u-boot/tools/asn1_compiler.c +--- u-boot-2021.10/tools/asn1_compiler.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/asn1_compiler.c 2021-11-01 17:10:14.756232171 +0100 +@@ -427,7 +427,7 @@ + } + memcpy(tokens[tix].content, start, tokens[tix].size); + tokens[tix].content[tokens[tix].size] = 0; +- ++ + /* If it begins with a lowercase letter then + * it's an element name + */ +diff -ruN u-boot-2021.10/tools/binman/control.py u-boot/tools/binman/control.py +--- u-boot-2021.10/tools/binman/control.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/binman/control.py 2021-11-01 17:10:14.759565322 +0100 +@@ -565,12 +565,9 @@ + global state + + if args.full_help: +- pager = os.getenv('PAGER') +- if not pager: +- pager = 'more' +- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), +- 'README.rst') +- command.Run(pager, fname) ++ tools.PrintFullHelp( ++ os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README.rst') ++ ) + return 0 + + # Put these here so that we can import this module without libfdt +diff -ruN u-boot-2021.10/tools/binman/missing-blob-help u-boot/tools/binman/missing-blob-help +--- u-boot-2021.10/tools/binman/missing-blob-help 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/binman/missing-blob-help 2021-11-01 17:10:14.762898474 +0100 +@@ -17,3 +17,8 @@ + scp-sunxi: + SCP firmware is required for system suspend, but is otherwise optional. + Please read the section on SCP firmware in board/sunxi/README.sunxi64 ++ ++k3-rti-wdt-firmware: ++If CONFIG_WDT_K3_RTI_LOAD_FW is enabled, a firmware image is needed for ++the R5F core(s) to trigger the system reset. One possible source is ++https://github.com/siemens/k3-rti-wdt. +diff -ruN u-boot-2021.10/tools/buildman/control.py u-boot/tools/buildman/control.py +--- u-boot-2021.10/tools/buildman/control.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/buildman/control.py 2021-11-01 17:10:14.772897926 +0100 +@@ -16,6 +16,7 @@ + from patman import gitutil + from patman import patchstream + from patman import terminal ++from patman import tools + from patman.terminal import Print + + def GetPlural(count): +@@ -133,12 +134,9 @@ + global builder + + if options.full_help: +- pager = os.getenv('PAGER') +- if not pager: +- pager = 'more' +- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), +- 'README') +- command.Run(pager, fname) ++ tools.PrintFullHelp( ++ os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), 'README') ++ ) + return 0 + + gitutil.Setup() +diff -ruN u-boot-2021.10/tools/buildman/README u-boot/tools/buildman/README +--- u-boot-2021.10/tools/buildman/README 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/buildman/README 2021-11-01 17:10:14.769564775 +0100 +@@ -1010,13 +1010,13 @@ + ... + 43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig + arm: +- + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 +- + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 +- + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 ++ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 ++ + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 ++ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 + am335x_evm_usbspl : +- + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 +- + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 +- + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1 ++ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 ++ + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 ++ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 + 44: Convert CONFIG_SPL_USB_HOST to Kconfig + ... + +diff -ruN u-boot-2021.10/tools/docker/Dockerfile u-boot/tools/docker/Dockerfile +--- u-boot-2021.10/tools/docker/Dockerfile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/docker/Dockerfile 2021-11-01 17:10:14.772897926 +0100 +@@ -2,7 +2,7 @@ + # This Dockerfile is used to build an image containing basic stuff to be used + # to build U-Boot and run our test suites. + +-FROM ubuntu:focal-20210723 ++FROM ubuntu:focal-20210827 + MAINTAINER Tom Rini <trini@konsulko.com> + LABEL Description=" This image is for building U-Boot inside a container" + +@@ -60,6 +60,7 @@ + iasl \ + imagemagick \ + iputils-ping \ ++ libconfuse-dev \ + libgit2-dev \ + libguestfs-tools \ + liblz4-tool \ +@@ -76,6 +77,7 @@ + mount \ + mtd-utils \ + mtools \ ++ ninja-build \ + openssl \ + picocom \ + parted \ +@@ -166,11 +168,24 @@ + RUN git clone git://git.qemu.org/qemu.git /tmp/qemu && \ + cd /tmp/qemu && \ + git submodule update --init dtc && \ +- git checkout v4.2.0 && \ ++ git checkout v6.1.0 && \ ++ # config user.name and user.email to make 'git am' happy ++ git config user.name u-boot && \ ++ git config user.email u-boot@denx.de && \ ++ # manually apply the bug fix for QEMU 6.1.0 Xilinx Zynq UART emulation codes ++ wget -O - http://patchwork.ozlabs.org/project/qemu-devel/patch/20210823020813.25192-2-bmeng.cn@gmail.com/mbox/ | git am && \ + ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ + make -j$(nproc) all install && \ + rm -rf /tmp/qemu + ++# Build genimage (required by some targets to generate disk images) ++RUN wget -O - https://github.com/pengutronix/genimage/releases/download/v14/genimage-14.tar.xz | tar -C /tmp -xJ && \ ++ cd /tmp/genimage-14 && \ ++ ./configure && \ ++ make -j$(nproc) && \ ++ make install && \ ++ rm -rf /tmp/genimage-14 ++ + # Create our user/group + RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot + RUN useradd -m -U uboot +diff -ruN u-boot-2021.10/tools/dtoc/dtb_platdata.py u-boot/tools/dtoc/dtb_platdata.py +--- u-boot-2021.10/tools/dtoc/dtb_platdata.py 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/dtoc/dtb_platdata.py 2021-11-01 17:10:14.776231078 +0100 +@@ -62,6 +62,7 @@ + # a phandle property. + PHANDLE_PROPS = { + 'clocks': '#clock-cells', ++ 'interrupts-extended': '#interrupt-cells', + 'gpios': '#gpio-cells', + 'sandbox,emul': '#emul-cells', + } +diff -ruN u-boot-2021.10/tools/env/fw_env.c u-boot/tools/env/fw_env.c +--- u-boot-2021.10/tools/env/fw_env.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/env/fw_env.c 2021-11-01 17:10:14.776231078 +0100 +@@ -951,21 +951,23 @@ + DEVNAME(dev), strerror(errno)); + return -1; + } +- if (rc != readlen) { +- fprintf(stderr, +- "Read error on %s: Attempted to read %zd bytes but got %d\n", +- DEVNAME(dev), readlen, rc); +- return -1; +- } + #ifdef DEBUG + fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n", + rc, (unsigned long long)blockstart + block_seek, + DEVNAME(dev)); + #endif +- processed += readlen; +- readlen = min(blocklen, count - processed); +- block_seek = 0; +- blockstart += blocklen; ++ processed += rc; ++ if (rc != readlen) { ++ fprintf(stderr, ++ "Warning on %s: Attempted to read %zd bytes but got %d\n", ++ DEVNAME(dev), readlen, rc); ++ readlen -= rc; ++ block_seek += rc; ++ } else { ++ blockstart += blocklen; ++ readlen = min(blocklen, count - processed); ++ block_seek = 0; ++ } + } + + return processed; +diff -ruN u-boot-2021.10/tools/imagetool.h u-boot/tools/imagetool.h +--- u-boot-2021.10/tools/imagetool.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/imagetool.h 2021-11-01 17:10:14.779564229 +0100 +@@ -51,6 +51,7 @@ + int pflag; + int vflag; + int xflag; ++ int Aflag; + int skipcpy; + int os; + int arch; +diff -ruN u-boot-2021.10/tools/kwbimage.c u-boot/tools/kwbimage.c +--- u-boot-2021.10/tools/kwbimage.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/kwbimage.c 2021-11-01 17:10:14.782897380 +0100 +@@ -1,7 +1,8 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* + * Image manipulator for Marvell SoCs +- * supports Kirkwood, Dove, Armada 370, Armada XP, and Armada 38x ++ * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and ++ * Armada 39x + * + * (C) Copyright 2013 Thomas Petazzoni + * <thomas.petazzoni@free-electrons.com> +@@ -280,14 +281,6 @@ + return csum; + } + +-size_t kwbimage_header_size(unsigned char *ptr) +-{ +- if (image_version((void *)ptr) == 0) +- return sizeof(struct main_hdr_v0); +- else +- return KWBHEADER_V1_SIZE((struct main_hdr_v1 *)ptr); +-} +- + /* + * Verify checksum over a complete header that includes the checksum field. + * Return 1 when OK, otherwise 0. +@@ -298,7 +291,7 @@ + struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr; + uint8_t checksum; + +- checksum = image_checksum8(hdr, kwbimage_header_size(hdr)); ++ checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr)); + /* Calculated checksum includes the header checksum field. Compensate + * for that. + */ +@@ -542,7 +535,7 @@ + } + + if (4 + size_seq > sizeof(dst->key)) { +- fprintf(stderr, "export pk failed: seq too large (%d, %lu)\n", ++ fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n", + 4 + size_seq, sizeof(dst->key)); + fprintf(stderr, errmsg, keyname); + return -ENOBUFS; +@@ -1618,34 +1611,20 @@ + static void kwbimage_print_header(const void *ptr) + { + struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr; ++ struct opt_hdr_v1 *ohdr; + + printf("Image Type: MVEBU Boot from %s Image\n", + image_boot_mode_name(mhdr->blockid)); +- printf("Image version:%d\n", image_version((void *)ptr)); +- if (image_version((void *)ptr) == 1) { +- struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; ++ printf("Image version:%d\n", kwbimage_version(ptr)); + +- if (mhdr->ext & 0x1) { +- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) +- ((uint8_t *)ptr + +- sizeof(*mhdr)); +- +- while (1) { +- uint32_t ohdr_size; +- +- ohdr_size = (ohdr->headersz_msb << 16) | +- le16_to_cpu(ohdr->headersz_lsb); +- if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { +- printf("BIN Hdr Size: "); +- genimg_print_size(ohdr_size - 12 - 4 * ohdr->data[0]); +- } +- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) +- break; +- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + +- ohdr_size); +- } ++ for_each_opt_hdr_v1 (ohdr, mhdr) { ++ if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { ++ printf("BIN Hdr Size: "); ++ genimg_print_size(opt_hdr_v1_size(ohdr) - 12 - ++ 4 * ohdr->data[0]); + } + } ++ + printf("Data Size: "); + genimg_print_size(mhdr->blocksize - sizeof(uint32_t)); + printf("Load Address: %08x\n", mhdr->destaddr); +@@ -1663,8 +1642,8 @@ + static int kwbimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) + { +- uint8_t checksum; +- size_t header_size = kwbimage_header_size(ptr); ++ size_t header_size = kwbheader_size(ptr); ++ uint8_t csum; + + if (header_size > image_size) + return -FDT_ERR_BADSTRUCTURE; +@@ -1673,52 +1652,27 @@ + return -FDT_ERR_BADSTRUCTURE; + + /* Only version 0 extended header has checksum */ +- if (image_version((void *)ptr) == 0) { ++ if (kwbimage_version(ptr) == 0) { + struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr; + + if (mhdr->ext & 0x1) { +- struct ext_hdr_v0 *ext_hdr; +- +- if (header_size + sizeof(*ext_hdr) > image_size) +- return -FDT_ERR_BADSTRUCTURE; ++ struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1); + +- ext_hdr = (struct ext_hdr_v0 *) +- (ptr + sizeof(struct main_hdr_v0)); +- checksum = image_checksum8(ext_hdr, +- sizeof(struct ext_hdr_v0) +- - sizeof(uint8_t)); +- if (checksum != ext_hdr->checksum) ++ csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1); ++ if (csum != ext_hdr->checksum) + return -FDT_ERR_BADSTRUCTURE; + } +- } else if (image_version((void *)ptr) == 1) { ++ } else if (kwbimage_version(ptr) == 1) { + struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; ++ const uint8_t *mhdr_end; ++ struct opt_hdr_v1 *ohdr; + uint32_t offset; + uint32_t size; + +- if (mhdr->ext & 0x1) { +- uint32_t ohdr_size; +- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) +- (ptr + sizeof(*mhdr)); +- +- while (1) { +- if ((uint8_t *)ohdr + sizeof(*ohdr) > +- (uint8_t *)mhdr + header_size) +- return -FDT_ERR_BADSTRUCTURE; +- +- ohdr_size = (ohdr->headersz_msb << 16) | +- le16_to_cpu(ohdr->headersz_lsb); +- +- if (ohdr_size < 8 || +- (uint8_t *)ohdr + ohdr_size > +- (uint8_t *)mhdr + header_size) +- return -FDT_ERR_BADSTRUCTURE; +- +- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) +- break; +- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + +- ohdr_size); +- } +- } ++ mhdr_end = (uint8_t *)mhdr + header_size; ++ for_each_opt_hdr_v1 (ohdr, ptr) ++ if (!opt_hdr_v1_valid_size(ohdr, mhdr_end)) ++ return -FDT_ERR_BADSTRUCTURE; + + offset = le32_to_cpu(mhdr->srcaddr); + +@@ -1864,37 +1818,25 @@ + static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params) + { + struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; +- size_t header_size = kwbimage_header_size(ptr); ++ size_t header_size = kwbheader_size(ptr); ++ struct opt_hdr_v1 *ohdr; + int idx = params->pflag; + int cur_idx = 0; + uint32_t offset; + ulong image; + ulong size; + +- if (image_version((void *)ptr) == 1 && (mhdr->ext & 0x1)) { +- struct opt_hdr_v1 *ohdr = (struct opt_hdr_v1 *) +- ((uint8_t *)ptr + +- sizeof(*mhdr)); +- +- while (1) { +- uint32_t ohdr_size = (ohdr->headersz_msb << 16) | +- le16_to_cpu(ohdr->headersz_lsb); ++ for_each_opt_hdr_v1 (ohdr, ptr) { ++ if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE) ++ continue; + +- if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) { +- if (idx == cur_idx) { +- image = (ulong)&ohdr->data[4 + +- 4 * ohdr->data[0]]; +- size = ohdr_size - 12 - +- 4 * ohdr->data[0]; +- goto extract; +- } +- ++cur_idx; +- } +- if (!(*((uint8_t *)ohdr + ohdr_size - 4) & 0x1)) +- break; +- ohdr = (struct opt_hdr_v1 *)((uint8_t *)ohdr + +- ohdr_size); ++ if (idx == cur_idx) { ++ image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]]; ++ size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0]; ++ goto extract; + } ++ ++ ++cur_idx; + } + + if (idx != cur_idx) { +diff -ruN u-boot-2021.10/tools/kwbimage.h u-boot/tools/kwbimage.h +--- u-boot-2021.10/tools/kwbimage.h 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/kwbimage.h 2021-11-01 17:10:14.782897380 +0100 +@@ -23,8 +23,8 @@ + /* NAND ECC Mode */ + #define IBR_HDR_ECC_DEFAULT 0x00 + #define IBR_HDR_ECC_FORCED_HAMMING 0x01 +-#define IBR_HDR_ECC_FORCED_RS 0x02 +-#define IBR_HDR_ECC_DISABLED 0x03 ++#define IBR_HDR_ECC_FORCED_RS 0x02 ++#define IBR_HDR_ECC_DISABLED 0x03 + + /* Boot Type - block ID */ + #define IBR_HDR_I2C_ID 0x4D +@@ -69,12 +69,7 @@ + uint8_t checksum; + } __packed; + +-struct kwb_header { +- struct main_hdr_v0 kwb_hdr; +- struct ext_hdr_v0 kwb_exthdr; +-} __packed; +- +-/* Structure of the main header, version 1 (Armada 370/38x/XP) */ ++/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */ + struct main_hdr_v1 { + uint8_t blockid; /* 0x0 */ + uint8_t flags; /* 0x1 */ +@@ -108,7 +103,7 @@ + #define MAIN_HDR_V1_OPT_BAUD_115200 0x7 + + /* +- * Header for the optional headers, version 1 (Armada 370, Armada XP) ++ * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x) + */ + struct opt_hdr_v1 { + uint8_t headertype; +@@ -132,7 +127,7 @@ + } __packed; + + /* +- * Structure of secure header (Armada 38x) ++ * Structure of secure header (Armada XP/375/38x/39x) + */ + struct secure_hdr_v1 { + uint8_t headertype; /* 0x0 */ +@@ -195,9 +190,6 @@ + #define OPT_HDR_V1_BINARY_TYPE 0x2 + #define OPT_HDR_V1_REGISTER_TYPE 0x3 + +-#define KWBHEADER_V1_SIZE(hdr) \ +- (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb)) +- + enum kwbimage_cmd { + CMD_INVALID, + CMD_BOOT_FROM, +@@ -225,10 +217,91 @@ + * header, byte 8 was reserved, and always set to 0. In the v1 header, + * byte 8 has been changed to a proper field, set to 1. + */ +-static inline unsigned int image_version(void *header) ++static inline unsigned int kwbimage_version(const void *header) + { +- unsigned char *ptr = header; ++ const unsigned char *ptr = header; + return ptr[8]; + } + ++static inline size_t kwbheader_size(const void *header) ++{ ++ if (kwbimage_version(header) == 0) { ++ const struct main_hdr_v0 *hdr = header; ++ ++ return sizeof(*hdr) + ++ (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0; ++ } else { ++ const struct main_hdr_v1 *hdr = header; ++ ++ return (hdr->headersz_msb << 16) | ++ le16_to_cpu(hdr->headersz_lsb); ++ } ++} ++ ++static inline size_t kwbheader_size_for_csum(const void *header) ++{ ++ if (kwbimage_version(header) == 0) ++ return sizeof(struct main_hdr_v0); ++ else ++ return kwbheader_size(header); ++} ++ ++static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr) ++{ ++ return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb); ++} ++ ++static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr, ++ const void *mhdr_end) ++{ ++ uint32_t ohdr_size; ++ ++ if ((void *)(ohdr + 1) > mhdr_end) ++ return 0; ++ ++ ohdr_size = opt_hdr_v1_size(ohdr); ++ if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end) ++ return 0; ++ ++ return 1; ++} ++ ++static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) { ++ struct main_hdr_v1 *mhdr; ++ ++ if (kwbimage_version(img) != 1) ++ return NULL; ++ ++ mhdr = img; ++ if (mhdr->ext & 0x1) ++ return (struct opt_hdr_v1 *)(mhdr + 1); ++ else ++ return NULL; ++} ++ ++static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur) ++{ ++ uint32_t size = opt_hdr_v1_size(cur); ++ ++ return (uint8_t *)cur + size - 4; ++} ++ ++static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur) ++{ ++ return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur)); ++} ++ ++static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur) ++{ ++ if (*opt_hdr_v1_ext(cur) & 0x1) ++ return _opt_hdr_v1_next(cur); ++ else ++ return NULL; ++} ++ ++#define for_each_opt_hdr_v1(ohdr, img) \ ++ for ((ohdr) = opt_hdr_v1_first((img)); \ ++ (ohdr) != NULL; \ ++ (ohdr) = opt_hdr_v1_next((ohdr))) ++ + #endif /* _KWBIMAGE_H_ */ +diff -ruN u-boot-2021.10/tools/kwboot.c u-boot/tools/kwboot.c +--- u-boot-2021.10/tools/kwboot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/kwboot.c 2021-11-01 17:10:14.782897380 +0100 +@@ -1,8 +1,11 @@ + /* + * Boot a Marvell SoC, with Xmodem over UART0. +- * supports Kirkwood, Dove, Armada 370, Armada XP ++ * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and ++ * Armada 39x + * + * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com> ++ * (c) 2021 Pali Rohár <pali@kernel.org> ++ * (c) 2021 Marek Behún <marek.behun@nic.cz> + * + * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281 + * Integrated Controller: Functional Specifications" December 2, +@@ -11,6 +14,7 @@ + + #include "kwbimage.h" + #include "mkimage.h" ++#include "version.h" + + #include <stdlib.h> + #include <stdio.h> +@@ -22,10 +26,15 @@ + #include <errno.h> + #include <unistd.h> + #include <stdint.h> +-#include <termios.h> +-#include <sys/mman.h> ++#include <time.h> + #include <sys/stat.h> + ++#ifdef __linux__ ++#include "termios_linux.h" ++#else ++#include <termios.h> ++#endif ++ + /* + * Marvell BootROM UART Sensing + */ +@@ -56,15 +65,199 @@ + #define NAK 21 /* target block negative ack */ + #define CAN 24 /* target/sender transfer cancellation */ + ++#define KWBOOT_XM_BLKSZ 128 /* xmodem block size */ ++ + struct kwboot_block { + uint8_t soh; + uint8_t pnum; + uint8_t _pnum; +- uint8_t data[128]; ++ uint8_t data[KWBOOT_XM_BLKSZ]; + uint8_t csum; + } __packed; + + #define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ ++#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */ ++ ++/* ARM code making baudrate changing function return to original exec address */ ++static unsigned char kwboot_pre_baud_code[] = { ++ /* exec_addr: */ ++ 0x00, 0x00, 0x00, 0x00, /* .word 0 */ ++ 0x0c, 0xe0, 0x1f, 0xe5, /* ldr lr, exec_addr */ ++}; ++ ++/* ARM code for binary header injection to change baudrate */ ++static unsigned char kwboot_baud_code[] = { ++ /* ; #define UART_BASE 0xd0012000 */ ++ /* ; #define THR 0x00 */ ++ /* ; #define DLL 0x00 */ ++ /* ; #define DLH 0x04 */ ++ /* ; #define LCR 0x0c */ ++ /* ; #define DLAB 0x80 */ ++ /* ; #define LSR 0x14 */ ++ /* ; #define THRE 0x20 */ ++ /* ; #define TEMT 0x40 */ ++ /* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */ ++ /* ; */ ++ /* ; u32 set_baudrate(u32 old_b, u32 new_b) { */ ++ /* ; const u8 *str = "$baudratechange"; */ ++ /* ; u8 c; */ ++ /* ; do { */ ++ /* ; c = *str++; */ ++ /* ; writel(UART_BASE + THR, c); */ ++ /* ; } while (c); */ ++ /* ; while */ ++ /* ; (!(readl(UART_BASE + LSR) & TEMT)); */ ++ /* ; u32 lcr = readl(UART_BASE + LCR); */ ++ /* ; writel(UART_BASE + LCR, lcr | DLAB); */ ++ /* ; u8 old_dll = readl(UART_BASE + DLL); */ ++ /* ; u8 old_dlh = readl(UART_BASE + DLH); */ ++ /* ; u16 old_dl = old_dll | (old_dlh << 8); */ ++ /* ; u32 clk = old_b * old_dl; */ ++ /* ; u16 new_dl = DIV_ROUND(clk, new_b); */ ++ /* ; u8 new_dll = new_dl & 0xff; */ ++ /* ; u8 new_dlh = (new_dl >> 8) & 0xff; */ ++ /* ; writel(UART_BASE + DLL, new_dll); */ ++ /* ; writel(UART_BASE + DLH, new_dlh); */ ++ /* ; writel(UART_BASE + LCR, lcr & ~DLAB); */ ++ /* ; msleep(1); */ ++ /* ; return 0; */ ++ /* ; } */ ++ ++ 0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */ ++ ++ /* ; r0 = UART_BASE */ ++ 0x02, 0x0a, 0xa0, 0xe3, /* mov r0, #0x2000 */ ++ 0x01, 0x00, 0x4d, 0xe3, /* movt r0, #0xd001 */ ++ ++ /* ; r2 = address of preamble string */ ++ 0xd0, 0x20, 0x8f, 0xe2, /* adr r2, preamble */ ++ ++ /* ; Send preamble string over UART */ ++ /* .Lloop_preamble: */ ++ /* */ ++ /* ; Wait until Transmitter Holding is Empty */ ++ /* .Lloop_thre: */ ++ /* ; r1 = UART_BASE[LSR] & THRE */ ++ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */ ++ 0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */ ++ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */ ++ ++ /* ; Put character into Transmitter FIFO */ ++ /* ; r1 = *r2++ */ ++ 0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */ ++ /* ; UART_BASE[THR] = r1 */ ++ 0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */ ++ ++ /* ; Loop until end of preamble string */ ++ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */ ++ 0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */ ++ ++ /* ; Wait until Transmitter FIFO is Empty */ ++ /* .Lloop_txempty: */ ++ /* ; r1 = UART_BASE[LSR] & TEMT */ ++ 0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */ ++ 0x40, 0x00, 0x11, 0xe3, /* tst r1, #0x40 */ ++ 0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_txempty */ ++ ++ /* ; Set Divisor Latch Access Bit */ ++ /* ; UART_BASE[LCR] |= DLAB */ ++ 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */ ++ 0x80, 0x10, 0x81, 0xe3, /* orr r1, r1, #0x80 */ ++ 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */ ++ ++ /* ; Read current Divisor Latch */ ++ /* ; r1 = UART_BASE[DLH]<<8 | UART_BASE[DLL] */ ++ 0x00, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x00] */ ++ 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */ ++ 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */ ++ 0x04, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x04] */ ++ 0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */ ++ 0x41, 0x14, 0xa0, 0xe1, /* asr r1, r1, #8 */ ++ 0x02, 0x10, 0x81, 0xe1, /* orr r1, r1, r2 */ ++ ++ /* ; Read old baudrate value */ ++ /* ; r2 = old_baudrate */ ++ 0x8c, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */ ++ ++ /* ; Calculate base clock */ ++ /* ; r1 = r2 * r1 */ ++ 0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */ ++ ++ /* ; Read new baudrate value */ ++ /* ; r2 = baudrate */ ++ 0x88, 0x20, 0x9f, 0xe5, /* ldr r2, baudrate */ ++ ++ /* ; Calculate new Divisor Latch */ ++ /* ; r1 = DIV_ROUND(r1, r2) = */ ++ /* ; = (r1 + r2/2) / r2 */ ++ 0xa2, 0x10, 0x81, 0xe0, /* add r1, r1, r2, lsr #1 */ ++ 0x02, 0x40, 0xa0, 0xe1, /* mov r4, r2 */ ++ 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */ ++ /* .Lloop_div1: */ ++ 0x84, 0x40, 0xa0, 0x91, /* movls r4, r4, lsl #1 */ ++ 0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */ ++ 0xfc, 0xff, 0xff, 0x9a, /* bls .Lloop_div1 */ ++ 0x00, 0x30, 0xa0, 0xe3, /* mov r3, #0 */ ++ /* .Lloop_div2: */ ++ 0x04, 0x00, 0x51, 0xe1, /* cmp r1, r4 */ ++ 0x04, 0x10, 0x41, 0x20, /* subhs r1, r1, r4 */ ++ 0x03, 0x30, 0xa3, 0xe0, /* adc r3, r3, r3 */ ++ 0xa4, 0x40, 0xa0, 0xe1, /* mov r4, r4, lsr #1 */ ++ 0x02, 0x00, 0x54, 0xe1, /* cmp r4, r2 */ ++ 0xf9, 0xff, 0xff, 0x2a, /* bhs .Lloop_div2 */ ++ 0x03, 0x10, 0xa0, 0xe1, /* mov r1, r3 */ ++ ++ /* ; Set new Divisor Latch Low */ ++ /* ; UART_BASE[DLL] = r1 & 0xff */ ++ 0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */ ++ 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */ ++ 0x00, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x00] */ ++ ++ /* ; Set new Divisor Latch High */ ++ /* ; UART_BASE[DLH] = r1>>8 & 0xff */ ++ 0x41, 0x24, 0xa0, 0xe1, /* asr r2, r1, #8 */ ++ 0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */ ++ 0x04, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x04] */ ++ ++ /* ; Clear Divisor Latch Access Bit */ ++ /* ; UART_BASE[LCR] &= ~DLAB */ ++ 0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */ ++ 0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */ ++ 0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */ ++ ++ /* ; Sleep 1ms ~~ 600000 cycles at 1200 MHz */ ++ /* ; r1 = 600000 */ ++ 0x9f, 0x1d, 0xa0, 0xe3, /* mov r1, #0x27c0 */ ++ 0x09, 0x10, 0x40, 0xe3, /* movt r1, #0x0009 */ ++ /* .Lloop_sleep: */ ++ 0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */ ++ 0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */ ++ 0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */ ++ ++ /* ; Return 0 - no error */ ++ 0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */ ++ 0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */ ++ ++ /* ; Preamble string */ ++ /* preamble: */ ++ 0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */ ++ 0x64, 0x72, 0x61, 0x74, ++ 0x65, 0x63, 0x68, 0x61, ++ 0x6e, 0x67, 0x65, 0x00, ++ ++ /* ; Placeholder for old baudrate value */ ++ /* old_baudrate: */ ++ 0x00, 0x00, 0x00, 0x00, /* .word 0 */ ++ ++ /* ; Placeholder for new baudrate value */ ++ /* new_baudrate: */ ++ 0x00, 0x00, 0x00, 0x00, /* .word 0 */ ++}; ++ ++#define KWBOOT_BAUDRATE_BIN_HEADER_SZ (sizeof(kwboot_baud_code) + \ ++ sizeof(struct opt_hdr_v1) + 8) ++ ++static const char kwb_baud_magic[16] = "$baudratechange"; + + static int kwboot_verbose; + +@@ -72,6 +265,23 @@ + static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO; + static int blk_rsp_timeo = KWBOOT_BLK_RSP_TIMEO; + ++static ssize_t ++kwboot_write(int fd, const char *buf, size_t len) ++{ ++ size_t tot = 0; ++ ++ while (tot < len) { ++ ssize_t wr = write(fd, buf + tot, len - tot); ++ ++ if (wr < 0) ++ return -1; ++ ++ tot += wr; ++ } ++ ++ return tot; ++} ++ + static void + kwboot_printv(const char *fmt, ...) + { +@@ -122,12 +332,14 @@ + fputc(c, stdout); + + nl = "]\n"; +- pos++; ++ pos = (pos + 1) % width; + + if (pct == 100) { +- while (pos++ < width) ++ while (pos && pos++ < width) + fputc(' ', stdout); + fputs(nl, stdout); ++ nl = ""; ++ pos = 0; + } + + fflush(stdout); +@@ -144,6 +356,9 @@ + + if (kwboot_verbose) + __progress(pct, c); ++ ++ if (pct == 100) ++ pct = 0; + } + + static int +@@ -191,26 +406,13 @@ + static int + kwboot_tty_send(int fd, const void *buf, size_t len) + { +- int rc; +- ssize_t n; +- + if (!buf) + return 0; + +- rc = -1; +- +- do { +- n = write(fd, buf, len); +- if (n < 0) +- goto out; +- +- buf = (char *)buf + n; +- len -= n; +- } while (len > 0); ++ if (kwboot_write(fd, buf, len) < 0) ++ return -1; + +- rc = tcdrain(fd); +-out: +- return rc; ++ return tcdrain(fd); + } + + static int +@@ -220,51 +422,260 @@ + } + + static speed_t +-kwboot_tty_speed(int baudrate) ++kwboot_tty_baudrate_to_speed(int baudrate) + { + switch (baudrate) { ++#ifdef B4000000 ++ case 4000000: ++ return B4000000; ++#endif ++#ifdef B3500000 ++ case 3500000: ++ return B3500000; ++#endif ++#ifdef B3000000 ++ case 3000000: ++ return B3000000; ++#endif ++#ifdef B2500000 ++ case 2500000: ++ return B2500000; ++#endif ++#ifdef B2000000 ++ case 2000000: ++ return B2000000; ++#endif ++#ifdef B1500000 ++ case 1500000: ++ return B1500000; ++#endif ++#ifdef B1152000 ++ case 1152000: ++ return B1152000; ++#endif ++#ifdef B1000000 ++ case 1000000: ++ return B1000000; ++#endif ++#ifdef B921600 ++ case 921600: ++ return B921600; ++#endif ++#ifdef B614400 ++ case 614400: ++ return B614400; ++#endif ++#ifdef B576000 ++ case 576000: ++ return B576000; ++#endif ++#ifdef B500000 ++ case 500000: ++ return B500000; ++#endif ++#ifdef B460800 ++ case 460800: ++ return B460800; ++#endif ++#ifdef B307200 ++ case 307200: ++ return B307200; ++#endif ++#ifdef B230400 ++ case 230400: ++ return B230400; ++#endif ++#ifdef B153600 ++ case 153600: ++ return B153600; ++#endif ++#ifdef B115200 + case 115200: + return B115200; ++#endif ++#ifdef B76800 ++ case 76800: ++ return B76800; ++#endif ++#ifdef B57600 + case 57600: + return B57600; ++#endif ++#ifdef B38400 + case 38400: + return B38400; ++#endif ++#ifdef B19200 + case 19200: + return B19200; ++#endif ++#ifdef B9600 + case 9600: + return B9600; ++#endif ++#ifdef B4800 ++ case 4800: ++ return B4800; ++#endif ++#ifdef B2400 ++ case 2400: ++ return B2400; ++#endif ++#ifdef B1800 ++ case 1800: ++ return B1800; ++#endif ++#ifdef B1200 ++ case 1200: ++ return B1200; ++#endif ++#ifdef B600 ++ case 600: ++ return B600; ++#endif ++#ifdef B300 ++ case 300: ++ return B300; ++#endif ++#ifdef B200 ++ case 200: ++ return B200; ++#endif ++#ifdef B150 ++ case 150: ++ return B150; ++#endif ++#ifdef B134 ++ case 134: ++ return B134; ++#endif ++#ifdef B110 ++ case 110: ++ return B110; ++#endif ++#ifdef B75 ++ case 75: ++ return B75; ++#endif ++#ifdef B50 ++ case 50: ++ return B50; ++#endif ++ default: ++#ifdef BOTHER ++ return BOTHER; ++#else ++ return B0; ++#endif + } ++} ++ ++static int ++_is_within_tolerance(int value, int reference, int tolerance) ++{ ++ return 100 * value >= reference * (100 - tolerance) && ++ 100 * value <= reference * (100 + tolerance); ++} + ++static int ++kwboot_tty_change_baudrate(int fd, int baudrate) ++{ ++ struct termios tio; ++ speed_t speed; ++ int rc; ++ ++ rc = tcgetattr(fd, &tio); ++ if (rc) ++ return rc; ++ ++ speed = kwboot_tty_baudrate_to_speed(baudrate); ++ if (speed == B0) { ++ errno = EINVAL; ++ return -1; ++ } ++ ++#ifdef BOTHER ++ if (speed == BOTHER) ++ tio.c_ospeed = tio.c_ispeed = baudrate; ++#endif ++ ++ rc = cfsetospeed(&tio, speed); ++ if (rc) ++ return rc; ++ ++ rc = cfsetispeed(&tio, speed); ++ if (rc) ++ return rc; ++ ++ rc = tcsetattr(fd, TCSANOW, &tio); ++ if (rc) ++ return rc; ++ ++ rc = tcgetattr(fd, &tio); ++ if (rc) ++ return rc; ++ ++ if (cfgetospeed(&tio) != speed || cfgetispeed(&tio) != speed) ++ goto baud_fail; ++ ++#ifdef BOTHER ++ /* ++ * Check whether set baudrate is within 3% tolerance. ++ * If BOTHER is defined, Linux always fills out c_ospeed / c_ispeed ++ * with real values. ++ */ ++ if (!_is_within_tolerance(tio.c_ospeed, baudrate, 3)) ++ goto baud_fail; ++ ++ if (!_is_within_tolerance(tio.c_ispeed, baudrate, 3)) ++ goto baud_fail; ++#endif ++ ++ return 0; ++ ++baud_fail: ++ fprintf(stderr, "Could not set baudrate to requested value\n"); ++ errno = EINVAL; + return -1; + } + + static int +-kwboot_open_tty(const char *path, speed_t speed) ++kwboot_open_tty(const char *path, int baudrate) + { +- int rc, fd; ++ int rc, fd, flags; + struct termios tio; + + rc = -1; + +- fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY); ++ fd = open(path, O_RDWR | O_NOCTTY | O_NDELAY); + if (fd < 0) + goto out; + +- memset(&tio, 0, sizeof(tio)); +- +- tio.c_iflag = 0; +- tio.c_cflag = CREAD|CLOCAL|CS8; ++ rc = tcgetattr(fd, &tio); ++ if (rc) ++ goto out; + ++ cfmakeraw(&tio); ++ tio.c_cflag |= CREAD | CLOCAL; + tio.c_cc[VMIN] = 1; +- tio.c_cc[VTIME] = 10; +- +- cfsetospeed(&tio, speed); +- cfsetispeed(&tio, speed); ++ tio.c_cc[VTIME] = 0; + + rc = tcsetattr(fd, TCSANOW, &tio); + if (rc) + goto out; + ++ flags = fcntl(fd, F_GETFL); ++ if (flags < 0) ++ goto out; ++ ++ rc = fcntl(fd, F_SETFL, flags & ~O_NDELAY); ++ if (rc) ++ goto out; ++ ++ rc = kwboot_tty_change_baudrate(fd, baudrate); ++ if (rc) ++ goto out; ++ + rc = fd; + out: + if (rc < 0) { +@@ -342,21 +753,19 @@ + return rc; + } + +-static int ++static size_t + kwboot_xm_makeblock(struct kwboot_block *block, const void *data, + size_t size, int pnum) + { +- const size_t blksz = sizeof(block->data); +- size_t n; +- int i; ++ size_t i, n; + + block->soh = SOH; + block->pnum = pnum; + block->_pnum = ~block->pnum; + +- n = size < blksz ? size : blksz; ++ n = size < KWBOOT_XM_BLKSZ ? size : KWBOOT_XM_BLKSZ; + memcpy(&block->data[0], data, n); +- memset(&block->data[n], 0, blksz - n); ++ memset(&block->data[n], 0, KWBOOT_XM_BLKSZ - n); + + block->csum = 0; + for (i = 0; i < n; i++) +@@ -365,34 +774,36 @@ + return n; + } + +-static int +-kwboot_xm_sendblock(int fd, struct kwboot_block *block) ++static uint64_t ++_now(void) + { +- int rc, retries; +- char c; ++ struct timespec ts; + +- retries = 16; +- do { +- rc = kwboot_tty_send(fd, block, sizeof(*block)); +- if (rc) +- break; ++ if (clock_gettime(CLOCK_MONOTONIC, &ts)) { ++ static int err_print; + +- do { +- rc = kwboot_tty_recv(fd, &c, 1, blk_rsp_timeo); +- if (rc) +- break; +- +- if (c != ACK && c != NAK && c != CAN) +- printf("%c", c); ++ if (!err_print) { ++ perror("clock_gettime() does not work"); ++ err_print = 1; ++ } + +- } while (c != ACK && c != NAK && c != CAN); ++ /* this will just make the timeout not work */ ++ return -1ULL; ++ } + +- if (c != ACK) +- kwboot_progress(-1, '+'); ++ return ts.tv_sec * 1000ULL + (ts.tv_nsec + 500000) / 1000000; ++} + +- } while (c == NAK && retries-- > 0); ++static int ++_is_xm_reply(char c) ++{ ++ return c == ACK || c == NAK || c == CAN; ++} + +- rc = -1; ++static int ++_xm_reply_to_error(int c) ++{ ++ int rc = -1; + + switch (c) { + case ACK: +@@ -413,56 +824,269 @@ + } + + static int +-kwboot_xmodem(int tty, const void *_data, size_t size) ++kwboot_baud_magic_handle(int fd, char c, int baudrate) + { +- const uint8_t *data = _data; +- int rc, pnum, N, err; ++ static size_t rcv_len; + +- pnum = 1; +- N = 0; ++ if (rcv_len < sizeof(kwb_baud_magic)) { ++ /* try to recognize whole magic word */ ++ if (c == kwb_baud_magic[rcv_len]) { ++ rcv_len++; ++ } else { ++ printf("%.*s%c", (int)rcv_len, kwb_baud_magic, c); ++ fflush(stdout); ++ rcv_len = 0; ++ } ++ } + +- kwboot_printv("Sending boot image...\n"); ++ if (rcv_len == sizeof(kwb_baud_magic)) { ++ /* magic word received */ ++ kwboot_printv("\nChanging baudrate to %d Bd\n", baudrate); + +- sleep(2); /* flush isn't effective without it */ +- tcflush(tty, TCIOFLUSH); ++ return kwboot_tty_change_baudrate(fd, baudrate) ? : 1; ++ } else { ++ return 0; ++ } ++} ++ ++static int ++kwboot_xm_recv_reply(int fd, char *c, int allow_non_xm, int *non_xm_print, ++ int baudrate, int *baud_changed) ++{ ++ int timeout = allow_non_xm ? KWBOOT_HDR_RSP_TIMEO : blk_rsp_timeo; ++ uint64_t recv_until = _now() + timeout; ++ int rc; ++ ++ if (non_xm_print) ++ *non_xm_print = 0; ++ if (baud_changed) ++ *baud_changed = 0; ++ ++ while (1) { ++ rc = kwboot_tty_recv(fd, c, 1, timeout); ++ if (rc) { ++ if (errno != ETIMEDOUT) ++ return rc; ++ else if (allow_non_xm && *non_xm_print) ++ return -1; ++ else ++ *c = NAK; ++ } ++ ++ /* If received xmodem reply, end. */ ++ if (_is_xm_reply(*c)) ++ break; ++ ++ /* ++ * If receiving/printing non-xmodem text output is allowed and ++ * such a byte was received, we want to increase receiving time ++ * and either: ++ * - print the byte, if it is not part of baudrate change magic ++ * sequence while baudrate change was requested (-B option) ++ * - change baudrate ++ * Otherwise decrease timeout by time elapsed. ++ */ ++ if (allow_non_xm) { ++ recv_until = _now() + timeout; ++ ++ if (baudrate && !*baud_changed) { ++ rc = kwboot_baud_magic_handle(fd, *c, baudrate); ++ if (rc == 1) ++ *baud_changed = 1; ++ else if (!rc) ++ *non_xm_print = 1; ++ else ++ return rc; ++ } else if (!baudrate || !*baud_changed) { ++ putchar(*c); ++ fflush(stdout); ++ *non_xm_print = 1; ++ } ++ } else { ++ timeout = recv_until - _now(); ++ if (timeout < 0) { ++ errno = ETIMEDOUT; ++ return -1; ++ } ++ } ++ } ++ ++ return 0; ++} + ++static int ++kwboot_xm_sendblock(int fd, struct kwboot_block *block, int allow_non_xm, ++ int *done_print, int baudrate) ++{ ++ int non_xm_print, baud_changed; ++ int rc, err, retries; ++ char c; ++ ++ *done_print = 0; ++ ++ retries = 16; + do { +- struct kwboot_block block; +- int n; ++ rc = kwboot_tty_send(fd, block, sizeof(*block)); ++ if (rc) ++ return rc; ++ ++ if (allow_non_xm && !*done_print) { ++ kwboot_progress(100, '.'); ++ kwboot_printv("Done\n"); ++ *done_print = 1; ++ } + +- n = kwboot_xm_makeblock(&block, +- data + N, size - N, +- pnum++); +- if (n < 0) ++ rc = kwboot_xm_recv_reply(fd, &c, allow_non_xm, &non_xm_print, ++ baudrate, &baud_changed); ++ if (rc) + goto can; + +- if (!n) +- break; ++ if (!allow_non_xm && c != ACK) ++ kwboot_progress(-1, '+'); ++ } while (c == NAK && retries-- > 0); ++ ++ if (non_xm_print) ++ kwboot_printv("\n"); ++ ++ if (allow_non_xm && baudrate && !baud_changed) { ++ fprintf(stderr, "Baudrate was not changed\n"); ++ rc = -1; ++ errno = EPROTO; ++ goto can; ++ } ++ ++ return _xm_reply_to_error(c); ++can: ++ err = errno; ++ kwboot_tty_send_char(fd, CAN); ++ kwboot_printv("\n"); ++ errno = err; ++ return rc; ++} ++ ++static int ++kwboot_xm_finish(int fd) ++{ ++ int rc, retries; ++ char c; ++ ++ kwboot_printv("Finishing transfer\n"); ++ ++ retries = 16; ++ do { ++ rc = kwboot_tty_send_char(fd, EOT); ++ if (rc) ++ return rc; + +- rc = kwboot_xm_sendblock(tty, &block); ++ rc = kwboot_xm_recv_reply(fd, &c, 0, NULL, 0, NULL); ++ if (rc) ++ return rc; ++ } while (c == NAK && retries-- > 0); ++ ++ return _xm_reply_to_error(c); ++} ++ ++static int ++kwboot_xmodem_one(int tty, int *pnum, int header, const uint8_t *data, ++ size_t size, int baudrate) ++{ ++ int done_print = 0; ++ size_t sent, left; ++ int rc; ++ ++ kwboot_printv("Sending boot image %s (%zu bytes)...\n", ++ header ? "header" : "data", size); ++ ++ left = size; ++ sent = 0; ++ ++ while (sent < size) { ++ struct kwboot_block block; ++ int last_block; ++ size_t blksz; ++ ++ blksz = kwboot_xm_makeblock(&block, data, left, (*pnum)++); ++ data += blksz; ++ ++ last_block = (left <= blksz); ++ ++ rc = kwboot_xm_sendblock(tty, &block, header && last_block, ++ &done_print, baudrate); + if (rc) + goto out; + +- N += n; +- kwboot_progress(N * 100 / size, '.'); +- } while (1); ++ sent += blksz; ++ left -= blksz; + +- rc = kwboot_tty_send_char(tty, EOT); ++ if (!done_print) ++ kwboot_progress(sent * 100 / size, '.'); ++ } ++ ++ if (!done_print) ++ kwboot_printv("Done\n"); + ++ return 0; + out: ++ kwboot_printv("\n"); + return rc; ++} + +-can: +- err = errno; +- kwboot_tty_send_char(tty, CAN); +- errno = err; +- goto out; ++static int ++kwboot_xmodem(int tty, const void *_img, size_t size, int baudrate) ++{ ++ const uint8_t *img = _img; ++ int rc, pnum; ++ size_t hdrsz; ++ ++ hdrsz = kwbheader_size(img); ++ ++ kwboot_printv("Waiting 2s and flushing tty\n"); ++ sleep(2); /* flush isn't effective without it */ ++ tcflush(tty, TCIOFLUSH); ++ ++ pnum = 1; ++ ++ rc = kwboot_xmodem_one(tty, &pnum, 1, img, hdrsz, baudrate); ++ if (rc) ++ return rc; ++ ++ img += hdrsz; ++ size -= hdrsz; ++ ++ rc = kwboot_xmodem_one(tty, &pnum, 0, img, size, 0); ++ if (rc) ++ return rc; ++ ++ rc = kwboot_xm_finish(tty); ++ if (rc) ++ return rc; ++ ++ if (baudrate) { ++ char buf[sizeof(kwb_baud_magic)]; ++ ++ /* Wait 1s for baudrate change magic */ ++ rc = kwboot_tty_recv(tty, buf, sizeof(buf), 1000); ++ if (rc) ++ return rc; ++ ++ if (memcmp(buf, kwb_baud_magic, sizeof(buf))) { ++ errno = EPROTO; ++ return -1; ++ } ++ ++ kwboot_printv("\nChanging baudrate back to 115200 Bd\n\n"); ++ rc = kwboot_tty_change_baudrate(tty, 115200); ++ if (rc) ++ return rc; ++ } ++ ++ return 0; + } + + static int +-kwboot_term_pipe(int in, int out, char *quit, int *s) ++kwboot_term_pipe(int in, int out, const char *quit, int *s) + { +- ssize_t nin, nout; ++ ssize_t nin; + char _buf[128], *buf = _buf; + + nin = read(in, buf, sizeof(_buf)); +@@ -480,22 +1104,15 @@ + buf++; + nin--; + } else { +- while (*s > 0) { +- nout = write(out, quit, *s); +- if (nout <= 0) +- return -1; +- (*s) -= nout; +- } ++ if (kwboot_write(out, quit, *s) < 0) ++ return -1; ++ *s = 0; + } + } + } + +- while (nin > 0) { +- nout = write(out, buf, nin); +- if (nout <= 0) +- return -1; +- nin -= nout; +- } ++ if (kwboot_write(out, buf, nin) < 0) ++ return -1; + + return 0; + } +@@ -504,7 +1121,7 @@ + kwboot_terminal(int tty) + { + int rc, in, s; +- char *quit = "\34c"; ++ const char *quit = "\34c"; + struct termios otio, tio; + + rc = -1; +@@ -523,7 +1140,7 @@ + } + + kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n", +- quit[0]|0100, quit[1]); ++ quit[0] | 0100, quit[1]); + } else + in = -1; + +@@ -552,7 +1169,7 @@ + break; + } + +- if (FD_ISSET(in, &rfds)) { ++ if (in >= 0 && FD_ISSET(in, &rfds)) { + rc = kwboot_term_pipe(in, tty, quit, &s); + if (rc) + break; +@@ -567,11 +1184,12 @@ + } + + static void * +-kwboot_mmap_image(const char *path, size_t *size, int prot) ++kwboot_read_image(const char *path, size_t *size, size_t reserve) + { +- int rc, fd, flags; ++ int rc, fd; + struct stat st; + void *img; ++ off_t tot; + + rc = -1; + img = NULL; +@@ -584,19 +1202,30 @@ + if (rc) + goto out; + +- flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED; +- +- img = mmap(NULL, st.st_size, prot, flags, fd, 0); +- if (img == MAP_FAILED) { +- img = NULL; ++ img = malloc(st.st_size + reserve); ++ if (!img) + goto out; ++ ++ tot = 0; ++ while (tot < st.st_size) { ++ ssize_t rd = read(fd, img + tot, st.st_size - tot); ++ ++ if (rd < 0) ++ goto out; ++ ++ tot += rd; ++ ++ if (!rd && tot < st.st_size) { ++ errno = EIO; ++ goto out; ++ } + } + + rc = 0; + *size = st.st_size; + out: + if (rc && img) { +- munmap(img, st.st_size); ++ free(img); + img = NULL; + } + if (fd >= 0) +@@ -606,9 +1235,13 @@ + } + + static uint8_t +-kwboot_img_csum8(void *_data, size_t size) ++kwboot_hdr_csum8(const void *hdr) + { +- uint8_t *data = _data, csum; ++ const uint8_t *data = hdr; ++ uint8_t csum; ++ size_t size; ++ ++ size = kwbheader_size_for_csum(hdr); + + for (csum = 0; size-- > 0; data++) + csum += *data; +@@ -617,80 +1250,299 @@ + } + + static int +-kwboot_img_patch_hdr(void *img, size_t size) ++kwboot_img_is_secure(void *img) ++{ ++ struct opt_hdr_v1 *ohdr; ++ ++ for_each_opt_hdr_v1 (ohdr, img) ++ if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) ++ return 1; ++ ++ return 0; ++} ++ ++static void * ++kwboot_img_grow_data_left(void *img, size_t *size, size_t grow) ++{ ++ uint32_t hdrsz, datasz, srcaddr; ++ struct main_hdr_v1 *hdr = img; ++ uint8_t *data; ++ ++ srcaddr = le32_to_cpu(hdr->srcaddr); ++ ++ hdrsz = kwbheader_size(hdr); ++ data = (uint8_t *)img + srcaddr; ++ datasz = *size - srcaddr; ++ ++ /* only move data if there is not enough space */ ++ if (hdrsz + grow > srcaddr) { ++ size_t need = hdrsz + grow - srcaddr; ++ ++ /* move data by enough bytes */ ++ memmove(data + need, data, datasz); ++ *size += need; ++ srcaddr += need; ++ } ++ ++ srcaddr -= grow; ++ hdr->srcaddr = cpu_to_le32(srcaddr); ++ hdr->destaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) - grow); ++ hdr->blocksize = cpu_to_le32(le32_to_cpu(hdr->blocksize) + grow); ++ ++ return (uint8_t *)img + srcaddr; ++} ++ ++static void ++kwboot_img_grow_hdr(void *img, size_t *size, size_t grow) ++{ ++ uint32_t hdrsz, datasz, srcaddr; ++ struct main_hdr_v1 *hdr = img; ++ uint8_t *data; ++ ++ srcaddr = le32_to_cpu(hdr->srcaddr); ++ ++ hdrsz = kwbheader_size(img); ++ data = (uint8_t *)img + srcaddr; ++ datasz = *size - srcaddr; ++ ++ /* only move data if there is not enough space */ ++ if (hdrsz + grow > srcaddr) { ++ size_t need = hdrsz + grow - srcaddr; ++ ++ /* move data by enough bytes */ ++ memmove(data + need, data, datasz); ++ ++ hdr->srcaddr = cpu_to_le32(srcaddr + need); ++ *size += need; ++ } ++ ++ if (kwbimage_version(img) == 1) { ++ hdrsz += grow; ++ hdr->headersz_msb = hdrsz >> 16; ++ hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff); ++ } ++} ++ ++static void * ++kwboot_add_bin_ohdr_v1(void *img, size_t *size, uint32_t binsz) ++{ ++ struct main_hdr_v1 *hdr = img; ++ struct opt_hdr_v1 *ohdr; ++ uint32_t ohdrsz; ++ ++ ohdrsz = binsz + 8 + sizeof(*ohdr); ++ kwboot_img_grow_hdr(img, size, ohdrsz); ++ ++ if (hdr->ext & 0x1) { ++ for_each_opt_hdr_v1 (ohdr, img) ++ if (opt_hdr_v1_next(ohdr) == NULL) ++ break; ++ ++ *opt_hdr_v1_ext(ohdr) |= 1; ++ ohdr = opt_hdr_v1_next(ohdr); ++ } else { ++ hdr->ext |= 1; ++ ohdr = (void *)(hdr + 1); ++ } ++ ++ ohdr->headertype = OPT_HDR_V1_BINARY_TYPE; ++ ohdr->headersz_msb = ohdrsz >> 16; ++ ohdr->headersz_lsb = cpu_to_le16(ohdrsz & 0xffff); ++ ++ memset(&ohdr->data[0], 0, ohdrsz - sizeof(*ohdr)); ++ ++ return &ohdr->data[4]; ++} ++ ++static void ++_copy_baudrate_change_code(struct main_hdr_v1 *hdr, void *dst, int pre, ++ int old_baud, int new_baud) ++{ ++ size_t codesz = sizeof(kwboot_baud_code); ++ uint8_t *code = dst; ++ ++ if (pre) { ++ size_t presz = sizeof(kwboot_pre_baud_code); ++ ++ /* ++ * We need to prepend code that loads lr register with original ++ * value of hdr->execaddr. We do this by putting the original ++ * exec address before the code that loads it relatively from ++ * it's beginning. ++ * Afterwards we change the exec address to this code (which is ++ * at offset 4, because the first 4 bytes contain the original ++ * exec address). ++ */ ++ memcpy(code, kwboot_pre_baud_code, presz); ++ *(uint32_t *)code = hdr->execaddr; ++ ++ hdr->execaddr = cpu_to_le32(le32_to_cpu(hdr->destaddr) + 4); ++ ++ code += presz; ++ } ++ ++ memcpy(code, kwboot_baud_code, codesz - 8); ++ *(uint32_t *)(code + codesz - 8) = cpu_to_le32(old_baud); ++ *(uint32_t *)(code + codesz - 4) = cpu_to_le32(new_baud); ++} ++ ++static int ++kwboot_img_patch(void *img, size_t *size, int baudrate) + { +- int rc; + struct main_hdr_v1 *hdr; ++ uint32_t srcaddr; + uint8_t csum; +- size_t hdrsz = sizeof(*hdr); ++ size_t hdrsz; + int image_ver; ++ int is_secure; + +- rc = -1; + hdr = img; + +- if (size < hdrsz) { +- errno = EINVAL; +- goto out; +- } ++ if (*size < sizeof(struct main_hdr_v1)) ++ goto err; + +- image_ver = image_version(img); ++ image_ver = kwbimage_version(img); + if (image_ver != 0 && image_ver != 1) { + fprintf(stderr, "Invalid image header version\n"); +- errno = EINVAL; +- goto out; ++ goto err; + } + +- if (image_ver == 0) +- hdrsz = sizeof(*hdr); +- else +- hdrsz = KWBHEADER_V1_SIZE(hdr); ++ hdrsz = kwbheader_size(hdr); + +- if (size < hdrsz) { +- errno = EINVAL; +- goto out; ++ if (*size < hdrsz) ++ goto err; ++ ++ csum = kwboot_hdr_csum8(hdr) - hdr->checksum; ++ if (csum != hdr->checksum) ++ goto err; ++ ++ if (image_ver == 0) { ++ struct main_hdr_v0 *hdr_v0 = img; ++ ++ hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED; ++ hdr_v0->nandpagesize = 0; + } + +- csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum; +- if (csum != hdr->checksum) { +- errno = EINVAL; +- goto out; ++ srcaddr = le32_to_cpu(hdr->srcaddr); ++ ++ switch (hdr->blockid) { ++ case IBR_HDR_SATA_ID: ++ if (srcaddr < 1) ++ goto err; ++ ++ hdr->srcaddr = cpu_to_le32((srcaddr - 1) * 512); ++ break; ++ ++ case IBR_HDR_SDIO_ID: ++ hdr->srcaddr = cpu_to_le32(srcaddr * 512); ++ break; ++ ++ case IBR_HDR_PEX_ID: ++ if (srcaddr == 0xFFFFFFFF) ++ hdr->srcaddr = cpu_to_le32(hdrsz); ++ break; ++ ++ case IBR_HDR_SPI_ID: ++ if (hdr->destaddr == cpu_to_le32(0xFFFFFFFF)) { ++ kwboot_printv("Patching destination and execution addresses from SPI/NOR XIP area to DDR area 0x00800000\n"); ++ hdr->destaddr = cpu_to_le32(0x00800000); ++ hdr->execaddr = cpu_to_le32(0x00800000); ++ } ++ break; + } + +- if (hdr->blockid == IBR_HDR_UART_ID) { +- rc = 0; +- goto out; ++ if (hdrsz > le32_to_cpu(hdr->srcaddr) || ++ *size < le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize)) ++ goto err; ++ ++ is_secure = kwboot_img_is_secure(img); ++ ++ if (hdr->blockid != IBR_HDR_UART_ID) { ++ if (is_secure) { ++ fprintf(stderr, ++ "Image has secure header with signature for non-UART booting\n"); ++ goto err; ++ } ++ ++ kwboot_printv("Patching image boot signature to UART\n"); ++ hdr->blockid = IBR_HDR_UART_ID; + } + +- hdr->blockid = IBR_HDR_UART_ID; ++ if (baudrate) { ++ uint32_t codesz = sizeof(kwboot_baud_code); ++ void *code; ++ ++ if (image_ver == 0) { ++ fprintf(stderr, ++ "Cannot inject code for changing baudrate into v0 image header\n"); ++ goto err; ++ } + +- if (image_ver == 0) { +- struct main_hdr_v0 *hdr_v0 = img; ++ if (is_secure) { ++ fprintf(stderr, ++ "Cannot inject code for changing baudrate into image with secure header\n"); ++ goto err; ++ } + +- hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED; +- hdr_v0->nandpagesize = 0; ++ /* ++ * First inject code that changes the baudrate from the default ++ * value of 115200 Bd to requested value. This code is inserted ++ * as a new opt hdr, so it is executed by BootROM after the ++ * header part is received. ++ */ ++ kwboot_printv("Injecting binary header code for changing baudrate to %d Bd\n", ++ baudrate); ++ ++ code = kwboot_add_bin_ohdr_v1(img, size, codesz); ++ _copy_baudrate_change_code(hdr, code, 0, 115200, baudrate); ++ ++ /* ++ * Now inject code that changes the baudrate back to 115200 Bd. ++ * This code is prepended to the data part of the image, so it ++ * is executed before U-Boot proper. ++ */ ++ kwboot_printv("Injecting code for changing baudrate back\n"); ++ ++ codesz += sizeof(kwboot_pre_baud_code); ++ code = kwboot_img_grow_data_left(img, size, codesz); ++ _copy_baudrate_change_code(hdr, code, 1, baudrate, 115200); ++ ++ /* recompute header size */ ++ hdrsz = kwbheader_size(hdr); ++ } ++ ++ if (hdrsz % KWBOOT_XM_BLKSZ) { ++ size_t offset = (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) % ++ KWBOOT_XM_BLKSZ; ++ ++ if (is_secure) { ++ fprintf(stderr, "Cannot align image with secure header\n"); ++ goto err; ++ } + +- hdr_v0->srcaddr = hdr_v0->ext +- ? sizeof(struct kwb_header) +- : sizeof(*hdr_v0); ++ kwboot_printv("Aligning image header to Xmodem block size\n"); ++ kwboot_img_grow_hdr(img, size, offset); + } + +- hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum; ++ hdr->checksum = kwboot_hdr_csum8(hdr) - csum; + +- rc = 0; +-out: +- return rc; ++ *size = le32_to_cpu(hdr->srcaddr) + le32_to_cpu(hdr->blocksize); ++ return 0; ++err: ++ errno = EINVAL; ++ return -1; + } + + static void + kwboot_usage(FILE *stream, char *progname) + { ++ fprintf(stream, "kwboot version %s\n", PLAIN_VERSION); + fprintf(stream, + "Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n", + progname); + fprintf(stream, "\n"); + fprintf(stream, + " -b <image>: boot <image> with preamble (Kirkwood, Armada 370/XP)\n"); +- fprintf(stream, " -p: patch <image> to type 0x69 (uart boot)\n"); + fprintf(stream, + " -D <image>: boot <image> without preamble (Dove)\n"); + fprintf(stream, " -d: enter debug mode\n"); +@@ -710,12 +1562,13 @@ + main(int argc, char **argv) + { + const char *ttypath, *imgpath; +- int rv, rc, tty, term, prot, patch; ++ int rv, rc, tty, term; + void *bootmsg; + void *debugmsg; + void *img; + size_t size; +- speed_t speed; ++ size_t after_img_rsv; ++ int baudrate; + + rv = 1; + tty = -1; +@@ -724,9 +1577,9 @@ + imgpath = NULL; + img = NULL; + term = 0; +- patch = 0; + size = 0; +- speed = B115200; ++ after_img_rsv = KWBOOT_XM_BLKSZ; ++ baudrate = 115200; + + kwboot_verbose = isatty(STDOUT_FILENO); + +@@ -751,7 +1604,7 @@ + break; + + case 'p': +- patch = 1; ++ /* nop, for backward compatibility */ + break; + + case 't': +@@ -776,9 +1629,7 @@ + break; + + case 'B': +- speed = kwboot_tty_speed(atoi(optarg)); +- if (speed == -1) +- goto usage; ++ baudrate = atoi(optarg); + break; + + case 'h': +@@ -791,32 +1642,34 @@ + if (!bootmsg && !term && !debugmsg) + goto usage; + +- if (patch && !imgpath) +- goto usage; +- + if (argc - optind < 1) + goto usage; + + ttypath = argv[optind++]; + +- tty = kwboot_open_tty(ttypath, speed); ++ tty = kwboot_open_tty(ttypath, imgpath ? 115200 : baudrate); + if (tty < 0) { + perror(ttypath); + goto out; + } + +- if (imgpath) { +- prot = PROT_READ | (patch ? PROT_WRITE : 0); ++ if (baudrate == 115200) ++ /* do not change baudrate during Xmodem to the same value */ ++ baudrate = 0; ++ else ++ /* ensure we have enough space for baudrate change code */ ++ after_img_rsv += KWBOOT_BAUDRATE_BIN_HEADER_SZ + ++ sizeof(kwboot_pre_baud_code) + ++ sizeof(kwboot_baud_code); + +- img = kwboot_mmap_image(imgpath, &size, prot); ++ if (imgpath) { ++ img = kwboot_read_image(imgpath, &size, after_img_rsv); + if (!img) { + perror(imgpath); + goto out; + } +- } + +- if (patch) { +- rc = kwboot_img_patch_hdr(img, size); ++ rc = kwboot_img_patch(img, &size, baudrate); + if (rc) { + fprintf(stderr, "%s: Invalid image.\n", imgpath); + goto out; +@@ -838,7 +1691,7 @@ + } + + if (img) { +- rc = kwboot_xmodem(tty, img, size); ++ rc = kwboot_xmodem(tty, img, size, baudrate); + if (rc) { + perror("xmodem"); + goto out; +@@ -859,7 +1712,7 @@ + close(tty); + + if (img) +- munmap(img, size); ++ free(img); + + return rv; + +diff -ruN u-boot-2021.10/tools/Makefile u-boot/tools/Makefile +--- u-boot-2021.10/tools/Makefile 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/Makefile 2021-11-01 17:10:14.756232171 +0100 +@@ -94,9 +94,12 @@ + AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \ + aes-encrypt.o aes-decrypt.o) + +-# Cryptographic helpers that depend on openssl/libcrypto +-LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/, \ +- fdt-libcrypto.o) ++# Cryptographic helpers and image types that depend on openssl/libcrypto ++LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \ ++ lib/fdt-libcrypto.o \ ++ kwbimage.o \ ++ mxsimage.o \ ++ sunxi_toc0.o + + ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o + +@@ -117,10 +120,8 @@ + imximage.o \ + imx8image.o \ + imx8mimage.o \ +- kwbimage.o \ + lib/md5.o \ + lpc32xximage.o \ +- mxsimage.o \ + omapimage.o \ + os_support.o \ + pblimage.o \ +@@ -130,6 +131,7 @@ + $(ROCKCHIP_OBS) \ + socfpgaimage.o \ + sunxi_egon.o \ ++ sunxi_toc1.o \ + lib/crc16.o \ + lib/hash-checksum.o \ + lib/sha1.o \ +@@ -155,22 +157,13 @@ + fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o + file2include-objs := file2include.o + +-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),) +-# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +-# the mxsimage support within tools/mxsimage.c . +-HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS +-endif +- + ifdef CONFIG_TOOLS_LIBCRYPTO + # This affects include/image.h, but including the board config file + # is tricky, so manually define this options here. + HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE + HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE_MAX_SIZE=0xffffffff + HOST_EXTRACFLAGS += -DCONFIG_FIT_CIPHER +-endif + +-# MXSImage needs LibSSL +-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_TOOLS_LIBCRYPTO),) + HOSTCFLAGS_kwbimage.o += \ + $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "") + HOSTLDLIBS_mkimage += \ +diff -ruN u-boot-2021.10/tools/mkimage.c u-boot/tools/mkimage.c +--- u-boot-2021.10/tools/mkimage.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/mkimage.c 2021-11-01 17:10:14.786230530 +0100 +@@ -171,6 +171,7 @@ + show_valid_options(IH_ARCH); + usage("Invalid architecture"); + } ++ params.Aflag = 1; + break; + case 'b': + if (add_content(IH_TYPE_FLATDT, optarg)) { +@@ -732,6 +733,12 @@ + exit (EXIT_FAILURE); + } + ++ if (sbuf.st_size == 0) { ++ fprintf (stderr, "%s: Input file %s is empty, bailing out\n", ++ params.cmdname, datafile); ++ exit (EXIT_FAILURE); ++ } ++ + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == MAP_FAILED) { + fprintf (stderr, "%s: Can't read %s: %s\n", +diff -ruN u-boot-2021.10/tools/mksunxiboot.c u-boot/tools/mksunxiboot.c +--- u-boot-2021.10/tools/mksunxiboot.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/mksunxiboot.c 2021-11-01 17:10:14.786230530 +0100 +@@ -12,10 +12,10 @@ + #include <stdlib.h> + #include <string.h> + #include <errno.h> ++#include <sunxi_image.h> + #include <sys/types.h> + #include <sys/stat.h> + #include "imagetool.h" +-#include "../arch/arm/include/asm/arch-sunxi/spl.h" + + #define STAMP_VALUE 0x5F0A6C39 + +diff -ruN u-boot-2021.10/tools/mxsimage.c u-boot/tools/mxsimage.c +--- u-boot-2021.10/tools/mxsimage.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/mxsimage.c 2021-11-01 17:10:14.786230530 +0100 +@@ -5,8 +5,6 @@ + * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> + */ + +-#ifdef CONFIG_MXS +- + #include <errno.h> + #include <fcntl.h> + #include <stdio.h> +@@ -2363,4 +2361,3 @@ + NULL, + mxsimage_generate + ); +-#endif +diff -ruN u-boot-2021.10/tools/patman/main.py u-boot/tools/patman/main.py +diff -ruN u-boot-2021.10/tools/patman/patman u-boot/tools/patman/patman +diff -ruN u-boot-2021.10/tools/patman/test/test01.txt u-boot/tools/patman/test/test01.txt +diff -ruN u-boot-2021.10/tools/patman/tools.py u-boot/tools/patman/tools.py +diff -ruN u-boot-2021.10/tools/sunxi_egon.c u-boot/tools/sunxi_egon.c +--- u-boot-2021.10/tools/sunxi_egon.c 2021-10-04 17:09:26.000000000 +0200 ++++ u-boot/tools/sunxi_egon.c 2021-11-01 17:10:14.792896833 +0100 +@@ -14,9 +14,29 @@ + */ + #define PAD_SIZE 8192 + ++static int egon_get_arch(struct image_tool_params *params) ++{ ++ if (params->Aflag) ++ return params->arch; ++ ++ /* For compatibility, assume ARM when no architecture specified */ ++ return IH_ARCH_ARM; ++} ++ + static int egon_check_params(struct image_tool_params *params) + { +- /* We just need a binary image file. */ ++ /* ++ * Check whether the architecture is supported. ++ */ ++ switch (egon_get_arch(params)) { ++ case IH_ARCH_ARM: ++ case IH_ARCH_RISCV: ++ break; ++ default: ++ return EXIT_FAILURE; ++ } ++ ++ /* We need a binary image file. */ + return !params->dflag; + } + +@@ -26,9 +46,22 @@ + const struct boot_file_head *header = (void *)ptr; + uint32_t length; + +- /* First 4 bytes must be an ARM branch instruction. */ +- if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000) +- return EXIT_FAILURE; ++ /* ++ * First 4 bytes must be a branch instruction of the corresponding ++ * architecture. ++ */ ++ switch (egon_get_arch(params)) { ++ case IH_ARCH_ARM: ++ if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000) ++ return EXIT_FAILURE; ++ break; ++ case IH_ARCH_RISCV: ++ if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 0x0000006f) ++ return EXIT_FAILURE; ++ break; ++ default: ++ return EXIT_FAILURE; /* Unknown architecture */ ++ } + + if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic))) + return EXIT_FAILURE; +@@ -77,9 +110,35 @@ + uint32_t checksum = 0, value; + int i; + +- /* Generate an ARM branch instruction to jump over the header. */ +- value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2); +- header->b_instruction = cpu_to_le32(value); ++ /* ++ * Different architectures need different first instruction to ++ * branch to the body. ++ */ ++ switch (egon_get_arch(params)) { ++ case IH_ARCH_ARM: ++ /* Generate an ARM branch instruction to jump over the header. */ ++ value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2); ++ header->b_instruction = cpu_to_le32(value); ++ break; ++ case IH_ARCH_RISCV: ++ /* ++ * Generate a RISC-V JAL instruction with rd=x0 ++ * (pseudo instruction J, jump without side effects). ++ * ++ * The following weird bit operation maps imm[20] ++ * to inst[31], imm[10:1] to inst[30:21], ++ * imm[11] to inst[20], imm[19:12] to inst[19:12], ++ * and imm[0] is dropped (because 1-byte RISC-V instruction ++ * is not allowed). ++ */ ++ value = 0x0000006f | ++ ((sizeof(struct boot_file_head) & 0x00100000) << 11) | ++ ((sizeof(struct boot_file_head) & 0x000007fe) << 20) | ++ ((sizeof(struct boot_file_head) & 0x00000800) << 9) | ++ ((sizeof(struct boot_file_head) & 0x000ff000) << 0); ++ header->b_instruction = cpu_to_le32(value); ++ break; ++ } + + memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic)); + header->check_sum = cpu_to_le32(BROM_STAMP_VALUE); +diff -ruN u-boot-2021.10/tools/sunxi_toc0.c u-boot/tools/sunxi_toc0.c +--- u-boot-2021.10/tools/sunxi_toc0.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/tools/sunxi_toc0.c 2021-11-01 17:10:14.792896833 +0100 +@@ -0,0 +1,907 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018 Arm Ltd. ++ * (C) Copyright 2020-2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#include <assert.h> ++#include <stdint.h> ++#include <stdio.h> ++#include <stdlib.h> ++#include <string.h> ++ ++#include <openssl/asn1t.h> ++#include <openssl/pem.h> ++#include <openssl/rsa.h> ++ ++#include <image.h> ++#include <sunxi_image.h> ++ ++#include "imagetool.h" ++#include "mkimage.h" ++ ++/* ++ * NAND requires 8K padding. For other devices, BROM requires only ++ * 512B padding, but let's use the larger padding to cover everything. ++ */ ++#define PAD_SIZE 8192 ++ ++#define pr_fmt(fmt) "mkimage (TOC0): %s: " fmt ++#define pr_err(fmt, args...) fprintf(stderr, pr_fmt(fmt), "error", ##args) ++#define pr_warn(fmt, args...) fprintf(stderr, pr_fmt(fmt), "warning", ##args) ++#define pr_info(fmt, args...) fprintf(stderr, pr_fmt(fmt), "info", ##args) ++ ++struct toc0_key_item { ++ __le32 vendor_id; ++ __le32 key0_n_len; ++ __le32 key0_e_len; ++ __le32 key1_n_len; ++ __le32 key1_e_len; ++ __le32 sig_len; ++ uint8_t key0[512]; ++ uint8_t key1[512]; ++ uint8_t reserved[32]; ++ uint8_t sig[256]; ++}; ++ ++/* ++ * This looks somewhat like an X.509 certificate, but it is not valid BER. ++ * ++ * Some differences: ++ * - Some X.509 certificate fields are missing or rearranged. ++ * - Some sequences have the wrong tag. ++ * - Zero-length sequences are accepted. ++ * - Large strings and integers must be an even number of bytes long. ++ * - Positive integers are not zero-extended to maintain their sign. ++ * ++ * See https://linux-sunxi.org/TOC0 for more information. ++ */ ++struct toc0_small_tag { ++ uint8_t tag; ++ uint8_t length; ++}; ++ ++typedef struct toc0_small_tag toc0_small_int; ++typedef struct toc0_small_tag toc0_small_oct; ++typedef struct toc0_small_tag toc0_small_seq; ++typedef struct toc0_small_tag toc0_small_exp; ++ ++#define TOC0_SMALL_INT(len) { 0x02, (len) } ++#define TOC0_SMALL_SEQ(len) { 0x30, (len) } ++#define TOC0_SMALL_EXP(tag, len) { 0xa0 | (tag), len } ++ ++struct toc0_large_tag { ++ uint8_t tag; ++ uint8_t prefix; ++ uint8_t length_hi; ++ uint8_t length_lo; ++}; ++ ++typedef struct toc0_large_tag toc0_large_int; ++typedef struct toc0_large_tag toc0_large_bit; ++typedef struct toc0_large_tag toc0_large_seq; ++ ++#define TOC0_LARGE_INT(len) { 0x02, 0x82, (len) >> 8, (len) & 0xff } ++#define TOC0_LARGE_BIT(len) { 0x03, 0x82, (len) >> 8, (len) & 0xff } ++#define TOC0_LARGE_SEQ(len) { 0x30, 0x82, (len) >> 8, (len) & 0xff } ++ ++struct toc0_cert_item { ++ toc0_large_seq tag_totalSequence; ++ struct toc0_totalSequence { ++ toc0_large_seq tag_mainSequence; ++ struct toc0_mainSequence { ++ toc0_small_exp tag_explicit0; ++ struct toc0_explicit0 { ++ toc0_small_int tag_version; ++ uint8_t version; ++ } explicit0; ++ toc0_small_int tag_serialNumber; ++ uint8_t serialNumber; ++ toc0_small_seq tag_signature; ++ toc0_small_seq tag_issuer; ++ toc0_small_seq tag_validity; ++ toc0_small_seq tag_subject; ++ toc0_large_seq tag_subjectPublicKeyInfo; ++ struct toc0_subjectPublicKeyInfo { ++ toc0_small_seq tag_algorithm; ++ toc0_large_seq tag_publicKey; ++ struct toc0_publicKey { ++ toc0_large_int tag_n; ++ uint8_t n[256]; ++ toc0_small_int tag_e; ++ uint8_t e[3]; ++ } publicKey; ++ } subjectPublicKeyInfo; ++ toc0_small_exp tag_explicit3; ++ struct toc0_explicit3 { ++ toc0_small_seq tag_extension; ++ struct toc0_extension { ++ toc0_small_int tag_digest; ++ uint8_t digest[32]; ++ } extension; ++ } explicit3; ++ } mainSequence; ++ toc0_large_bit tag_sigSequence; ++ struct toc0_sigSequence { ++ toc0_small_seq tag_algorithm; ++ toc0_large_bit tag_signature; ++ uint8_t signature[256]; ++ } sigSequence; ++ } totalSequence; ++}; ++ ++#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) ++ ++static const struct toc0_cert_item cert_item_template = { ++ TOC0_LARGE_SEQ(sizeof(struct toc0_totalSequence)), ++ { ++ TOC0_LARGE_SEQ(sizeof(struct toc0_mainSequence)), ++ { ++ TOC0_SMALL_EXP(0, sizeof(struct toc0_explicit0)), ++ { ++ TOC0_SMALL_INT(sizeof_field(struct toc0_explicit0, version)), ++ 0, ++ }, ++ TOC0_SMALL_INT(sizeof_field(struct toc0_mainSequence, serialNumber)), ++ 0, ++ TOC0_SMALL_SEQ(0), ++ TOC0_SMALL_SEQ(0), ++ TOC0_SMALL_SEQ(0), ++ TOC0_SMALL_SEQ(0), ++ TOC0_LARGE_SEQ(sizeof(struct toc0_subjectPublicKeyInfo)), ++ { ++ TOC0_SMALL_SEQ(0), ++ TOC0_LARGE_SEQ(sizeof(struct toc0_publicKey)), ++ { ++ TOC0_LARGE_INT(sizeof_field(struct toc0_publicKey, n)), ++ {}, ++ TOC0_SMALL_INT(sizeof_field(struct toc0_publicKey, e)), ++ {}, ++ }, ++ }, ++ TOC0_SMALL_EXP(3, sizeof(struct toc0_explicit3)), ++ { ++ TOC0_SMALL_SEQ(sizeof(struct toc0_extension)), ++ { ++ TOC0_SMALL_INT(sizeof_field(struct toc0_extension, digest)), ++ {}, ++ }, ++ }, ++ }, ++ TOC0_LARGE_BIT(sizeof(struct toc0_sigSequence)), ++ { ++ TOC0_SMALL_SEQ(0), ++ TOC0_LARGE_BIT(sizeof_field(struct toc0_sigSequence, signature)), ++ {}, ++ }, ++ }, ++}; ++ ++#define TOC0_DEFAULT_NUM_ITEMS 3 ++#define TOC0_DEFAULT_HEADER_LEN \ ++ ALIGN( \ ++ sizeof(struct toc0_main_info) + \ ++ sizeof(struct toc0_item_info) * TOC0_DEFAULT_NUM_ITEMS + \ ++ sizeof(struct toc0_cert_item) + \ ++ sizeof(struct toc0_key_item), \ ++ 32) ++ ++static char *fw_key_file = "fw_key.pem"; ++static char *key_item_file = "key_item.bin"; ++static char *root_key_file = "root_key.pem"; ++ ++/* ++ * Create a key item in @buf, containing the public keys @root_key and @fw_key, ++ * and signed by the RSA key @root_key. ++ */ ++static int toc0_create_key_item(uint8_t *buf, uint32_t *len, ++ RSA *root_key, RSA *fw_key) ++{ ++ struct toc0_key_item *key_item = (void *)buf; ++ uint8_t digest[SHA256_DIGEST_LENGTH]; ++ int ret = EXIT_FAILURE; ++ unsigned int sig_len; ++ int n_len, e_len; ++ ++ /* Store key 0. */ ++ n_len = BN_bn2bin(RSA_get0_n(root_key), key_item->key0); ++ e_len = BN_bn2bin(RSA_get0_e(root_key), key_item->key0 + n_len); ++ if (n_len + e_len > sizeof(key_item->key0)) { ++ pr_err("Root key is too big for key item\n"); ++ goto err; ++ } ++ key_item->key0_n_len = cpu_to_le32(n_len); ++ key_item->key0_e_len = cpu_to_le32(e_len); ++ ++ /* Store key 1. */ ++ n_len = BN_bn2bin(RSA_get0_n(fw_key), key_item->key1); ++ e_len = BN_bn2bin(RSA_get0_e(fw_key), key_item->key1 + n_len); ++ if (n_len + e_len > sizeof(key_item->key1)) { ++ pr_err("Firmware key is too big for key item\n"); ++ goto err; ++ } ++ key_item->key1_n_len = cpu_to_le32(n_len); ++ key_item->key1_e_len = cpu_to_le32(e_len); ++ ++ /* Sign the key item. */ ++ key_item->sig_len = cpu_to_le32(RSA_size(root_key)); ++ SHA256(buf, key_item->sig - buf, digest); ++ if (!RSA_sign(NID_sha256, digest, sizeof(digest), ++ key_item->sig, &sig_len, root_key)) { ++ pr_err("Failed to sign key item\n"); ++ goto err; ++ } ++ if (sig_len != sizeof(key_item->sig)) { ++ pr_err("Bad key item signature length\n"); ++ goto err; ++ } ++ ++ *len = sizeof(*key_item); ++ ret = EXIT_SUCCESS; ++ ++err: ++ return ret; ++} ++ ++/* ++ * Verify the key item in @buf, containing two public keys @key0 and @key1, ++ * and signed by the RSA key @key0. If @root_key is provided, only signatures ++ * by that key will be accepted. @key1 is returned in @key. ++ */ ++static int toc0_verify_key_item(const uint8_t *buf, uint32_t len, ++ RSA *root_key, RSA **fw_key) ++{ ++ struct toc0_key_item *key_item = (void *)buf; ++ uint8_t digest[SHA256_DIGEST_LENGTH]; ++ int ret = EXIT_FAILURE; ++ int n_len, e_len; ++ RSA *key0 = NULL; ++ RSA *key1 = NULL; ++ BIGNUM *n, *e; ++ ++ if (len < sizeof(*key_item)) ++ goto err; ++ ++ /* Load key 0. */ ++ n_len = le32_to_cpu(key_item->key0_n_len); ++ e_len = le32_to_cpu(key_item->key0_e_len); ++ if (n_len + e_len > sizeof(key_item->key0)) { ++ pr_err("Bad root key size in key item\n"); ++ goto err; ++ } ++ n = BN_bin2bn(key_item->key0, n_len, NULL); ++ e = BN_bin2bn(key_item->key0 + n_len, e_len, NULL); ++ key0 = RSA_new(); ++ if (!key0) ++ goto err; ++ if (!RSA_set0_key(key0, n, e, NULL)) ++ goto err; ++ ++ /* If a root key was provided, compare it to key 0. */ ++ if (root_key && (BN_cmp(n, RSA_get0_n(root_key)) || ++ BN_cmp(e, RSA_get0_e(root_key)))) { ++ pr_err("Wrong root key in key item\n"); ++ goto err; ++ } ++ ++ /* Verify the key item signature. */ ++ SHA256(buf, key_item->sig - buf, digest); ++ if (!RSA_verify(NID_sha256, digest, sizeof(digest), ++ key_item->sig, le32_to_cpu(key_item->sig_len), key0)) { ++ pr_err("Bad key item signature\n"); ++ goto err; ++ } ++ ++ if (fw_key) { ++ /* Load key 1. */ ++ n_len = le32_to_cpu(key_item->key1_n_len); ++ e_len = le32_to_cpu(key_item->key1_e_len); ++ if (n_len + e_len > sizeof(key_item->key1)) { ++ pr_err("Bad firmware key size in key item\n"); ++ goto err; ++ } ++ n = BN_bin2bn(key_item->key1, n_len, NULL); ++ e = BN_bin2bn(key_item->key1 + n_len, e_len, NULL); ++ key1 = RSA_new(); ++ if (!key1) ++ goto err; ++ if (!RSA_set0_key(key1, n, e, NULL)) ++ goto err; ++ ++ if (*fw_key) { ++ /* If a FW key was provided, compare it to key 1. */ ++ if (BN_cmp(n, RSA_get0_n(*fw_key)) || ++ BN_cmp(e, RSA_get0_e(*fw_key))) { ++ pr_err("Wrong firmware key in key item\n"); ++ goto err; ++ } ++ } else { ++ /* Otherwise, send key1 back to the caller. */ ++ *fw_key = key1; ++ key1 = NULL; ++ } ++ } ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ RSA_free(key0); ++ RSA_free(key1); ++ ++ return ret; ++} ++ ++/* ++ * Create a certificate in @buf, describing the firmware with SHA256 digest ++ * @digest, and signed by the RSA key @fw_key. ++ */ ++static int toc0_create_cert_item(uint8_t *buf, uint32_t *len, RSA *fw_key, ++ uint8_t digest[static SHA256_DIGEST_LENGTH]) ++{ ++ struct toc0_cert_item *cert_item = (void *)buf; ++ uint8_t cert_digest[SHA256_DIGEST_LENGTH]; ++ struct toc0_totalSequence *totalSequence; ++ struct toc0_sigSequence *sigSequence; ++ struct toc0_extension *extension; ++ struct toc0_publicKey *publicKey; ++ int ret = EXIT_FAILURE; ++ unsigned int sig_len; ++ ++ memcpy(cert_item, &cert_item_template, sizeof(*cert_item)); ++ *len = sizeof(*cert_item); ++ ++ /* ++ * Fill in the public key. ++ * ++ * Only 2048-bit RSA keys are supported. Since this uses a fixed-size ++ * structure, it may fail for non-standard exponents. ++ */ ++ totalSequence = &cert_item->totalSequence; ++ publicKey = &totalSequence->mainSequence.subjectPublicKeyInfo.publicKey; ++ if (BN_bn2binpad(RSA_get0_n(fw_key), publicKey->n, sizeof(publicKey->n)) < 0 || ++ BN_bn2binpad(RSA_get0_e(fw_key), publicKey->e, sizeof(publicKey->e)) < 0) { ++ pr_err("Firmware key is too big for certificate\n"); ++ goto err; ++ } ++ ++ /* Fill in the firmware digest. */ ++ extension = &totalSequence->mainSequence.explicit3.extension; ++ memcpy(&extension->digest, digest, SHA256_DIGEST_LENGTH); ++ ++ /* ++ * Sign the certificate. ++ * ++ * In older SBROM versions (and by default in newer versions), ++ * the last 4 bytes of the certificate are not signed. ++ * ++ * (The buffer passed to SHA256 starts at tag_mainSequence, but ++ * the buffer size does not include the length of that tag.) ++ */ ++ SHA256((uint8_t *)totalSequence, sizeof(struct toc0_mainSequence), cert_digest); ++ sigSequence = &totalSequence->sigSequence; ++ if (!RSA_sign(NID_sha256, cert_digest, SHA256_DIGEST_LENGTH, ++ sigSequence->signature, &sig_len, fw_key)) { ++ pr_err("Failed to sign certificate\n"); ++ goto err; ++ } ++ if (sig_len != sizeof(sigSequence->signature)) { ++ pr_err("Bad certificate signature length\n"); ++ goto err; ++ } ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ return ret; ++} ++ ++/* ++ * Verify the certificate in @buf, describing the firmware with SHA256 digest ++ * @digest, and signed by the RSA key contained within. If @fw_key is provided, ++ * only that key will be accepted. ++ * ++ * This function is only expected to work with images created by mkimage. ++ */ ++static int toc0_verify_cert_item(const uint8_t *buf, uint32_t len, RSA *fw_key, ++ uint8_t digest[static SHA256_DIGEST_LENGTH]) ++{ ++ const struct toc0_cert_item *cert_item = (const void *)buf; ++ uint8_t cert_digest[SHA256_DIGEST_LENGTH]; ++ const struct toc0_totalSequence *totalSequence; ++ const struct toc0_sigSequence *sigSequence; ++ const struct toc0_extension *extension; ++ const struct toc0_publicKey *publicKey; ++ int ret = EXIT_FAILURE; ++ RSA *key = NULL; ++ BIGNUM *n, *e; ++ ++ /* Extract the public key from the certificate. */ ++ totalSequence = &cert_item->totalSequence; ++ publicKey = &totalSequence->mainSequence.subjectPublicKeyInfo.publicKey; ++ n = BN_bin2bn(publicKey->n, sizeof(publicKey->n), NULL); ++ e = BN_bin2bn(publicKey->e, sizeof(publicKey->e), NULL); ++ key = RSA_new(); ++ if (!key) ++ goto err; ++ if (!RSA_set0_key(key, n, e, NULL)) ++ goto err; ++ ++ /* If a key was provided, compare it to the embedded key. */ ++ if (fw_key && (BN_cmp(RSA_get0_n(key), RSA_get0_n(fw_key)) || ++ BN_cmp(RSA_get0_e(key), RSA_get0_e(fw_key)))) { ++ pr_err("Wrong firmware key in certificate\n"); ++ goto err; ++ } ++ ++ /* If a digest was provided, compare it to the embedded digest. */ ++ extension = &totalSequence->mainSequence.explicit3.extension; ++ if (digest && memcmp(&extension->digest, digest, SHA256_DIGEST_LENGTH)) { ++ pr_err("Wrong firmware digest in certificate\n"); ++ goto err; ++ } ++ ++ /* Verify the certificate's signature. See the comment above. */ ++ SHA256((uint8_t *)totalSequence, sizeof(struct toc0_mainSequence), cert_digest); ++ sigSequence = &totalSequence->sigSequence; ++ if (!RSA_verify(NID_sha256, cert_digest, SHA256_DIGEST_LENGTH, ++ sigSequence->signature, ++ sizeof(sigSequence->signature), key)) { ++ pr_err("Bad certificate signature\n"); ++ goto err; ++ } ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ RSA_free(key); ++ ++ return ret; ++} ++ ++/* ++ * Always create a TOC0 containing 3 items. The extra item will be ignored on ++ * SoCs which do not support it. ++ */ ++static int toc0_create(uint8_t *buf, uint32_t len, RSA *root_key, RSA *fw_key, ++ uint8_t *key_item, uint32_t key_item_len, ++ uint8_t *fw_item, uint32_t fw_item_len, uint32_t fw_addr) ++{ ++ struct toc0_main_info *main_info = (void *)buf; ++ struct toc0_item_info *item_info = (void *)(main_info + 1); ++ uint8_t digest[SHA256_DIGEST_LENGTH]; ++ uint32_t *buf32 = (void *)buf; ++ RSA *orig_fw_key = fw_key; ++ int ret = EXIT_FAILURE; ++ uint32_t checksum = 0; ++ uint32_t item_offset; ++ uint32_t item_length; ++ int i; ++ ++ /* Hash the firmware for inclusion in the certificate. */ ++ SHA256(fw_item, fw_item_len, digest); ++ ++ /* Create the main TOC0 header, containing three items. */ ++ memcpy(main_info->name, TOC0_MAIN_INFO_NAME, sizeof(main_info->name)); ++ main_info->magic = cpu_to_le32(TOC0_MAIN_INFO_MAGIC); ++ main_info->checksum = cpu_to_le32(BROM_STAMP_VALUE); ++ main_info->num_items = cpu_to_le32(TOC0_DEFAULT_NUM_ITEMS); ++ memcpy(main_info->end, TOC0_MAIN_INFO_END, sizeof(main_info->end)); ++ ++ /* The first item links the ROTPK to the signing key. */ ++ item_offset = sizeof(*main_info) + ++ sizeof(*item_info) * TOC0_DEFAULT_NUM_ITEMS; ++ /* Using an existing key item avoids needing the root private key. */ ++ if (key_item) { ++ item_length = sizeof(*key_item); ++ if (toc0_verify_key_item(key_item, item_length, ++ root_key, &fw_key)) ++ goto err; ++ memcpy(buf + item_offset, key_item, item_length); ++ } else if (toc0_create_key_item(buf + item_offset, &item_length, ++ root_key, fw_key)) { ++ goto err; ++ } ++ ++ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_KEY); ++ item_info->offset = cpu_to_le32(item_offset); ++ item_info->length = cpu_to_le32(item_length); ++ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end)); ++ ++ /* The second item contains a certificate signed by the firmware key. */ ++ item_offset = item_offset + item_length; ++ if (toc0_create_cert_item(buf + item_offset, &item_length, ++ fw_key, digest)) ++ goto err; ++ ++ item_info++; ++ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_CERT); ++ item_info->offset = cpu_to_le32(item_offset); ++ item_info->length = cpu_to_le32(item_length); ++ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end)); ++ ++ /* The third item contains the actual boot code. */ ++ item_offset = ALIGN(item_offset + item_length, 32); ++ item_length = fw_item_len; ++ if (buf + item_offset != fw_item) ++ memmove(buf + item_offset, fw_item, item_length); ++ ++ item_info++; ++ item_info->name = cpu_to_le32(TOC0_ITEM_INFO_NAME_FIRMWARE); ++ item_info->offset = cpu_to_le32(item_offset); ++ item_info->length = cpu_to_le32(item_length); ++ item_info->load_addr = cpu_to_le32(fw_addr); ++ memcpy(item_info->end, TOC0_ITEM_INFO_END, sizeof(item_info->end)); ++ ++ /* Pad to the required block size with 0xff to be flash-friendly. */ ++ item_offset = item_offset + item_length; ++ item_length = ALIGN(item_offset, PAD_SIZE) - item_offset; ++ memset(buf + item_offset, 0xff, item_length); ++ ++ /* Fill in the total padded file length. */ ++ item_offset = item_offset + item_length; ++ main_info->length = cpu_to_le32(item_offset); ++ ++ /* Verify enough space was provided when creating the image. */ ++ assert(len >= item_offset); ++ ++ /* Calculate the checksum. Yes, it's that simple. */ ++ for (i = 0; i < item_offset / 4; ++i) ++ checksum += le32_to_cpu(buf32[i]); ++ main_info->checksum = cpu_to_le32(checksum); ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ if (fw_key != orig_fw_key) ++ RSA_free(fw_key); ++ ++ return ret; ++} ++ ++static const struct toc0_item_info * ++toc0_find_item(const struct toc0_main_info *main_info, uint32_t name, ++ uint32_t *offset, uint32_t *length) ++{ ++ const struct toc0_item_info *item_info = (void *)(main_info + 1); ++ uint32_t item_offset, item_length; ++ uint32_t num_items, main_length; ++ int i; ++ ++ num_items = le32_to_cpu(main_info->num_items); ++ main_length = le32_to_cpu(main_info->length); ++ ++ for (i = 0; i < num_items; ++i, ++item_info) { ++ if (le32_to_cpu(item_info->name) != name) ++ continue; ++ ++ item_offset = le32_to_cpu(item_info->offset); ++ item_length = le32_to_cpu(item_info->length); ++ ++ if (item_offset > main_length || ++ item_length > main_length - item_offset) ++ continue; ++ ++ *offset = item_offset; ++ *length = item_length; ++ ++ return item_info; ++ } ++ ++ return NULL; ++} ++ ++static int toc0_verify(const uint8_t *buf, uint32_t len, RSA *root_key) ++{ ++ const struct toc0_main_info *main_info = (void *)buf; ++ const struct toc0_item_info *item_info; ++ uint8_t digest[SHA256_DIGEST_LENGTH]; ++ uint32_t main_length = le32_to_cpu(main_info->length); ++ uint32_t checksum = BROM_STAMP_VALUE; ++ uint32_t *buf32 = (void *)buf; ++ uint32_t length, offset; ++ int ret = EXIT_FAILURE; ++ RSA *fw_key = NULL; ++ int i; ++ ++ if (len < main_length) ++ goto err; ++ ++ /* Verify the main header. */ ++ if (memcmp(main_info->name, TOC0_MAIN_INFO_NAME, sizeof(main_info->name))) ++ goto err; ++ if (le32_to_cpu(main_info->magic) != TOC0_MAIN_INFO_MAGIC) ++ goto err; ++ /* Verify the checksum without modifying the buffer. */ ++ for (i = 0; i < main_length / 4; ++i) ++ checksum += le32_to_cpu(buf32[i]); ++ if (checksum != 2 * le32_to_cpu(main_info->checksum)) ++ goto err; ++ /* The length must be at least 512 byte aligned. */ ++ if (main_length % 512) ++ goto err; ++ if (memcmp(main_info->end, TOC0_MAIN_INFO_END, sizeof(main_info->end))) ++ goto err; ++ ++ /* Verify the key item if present (it is optional). */ ++ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_KEY, ++ &offset, &length); ++ if (!item_info) ++ fw_key = root_key; ++ else if (toc0_verify_key_item(buf + offset, length, root_key, &fw_key)) ++ goto err; ++ ++ /* Hash the firmware to compare with the certificate. */ ++ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_FIRMWARE, ++ &offset, &length); ++ if (!item_info) { ++ pr_err("Missing firmware item\n"); ++ goto err; ++ } ++ SHA256(buf + offset, length, digest); ++ ++ /* Verify the certificate item. */ ++ item_info = toc0_find_item(main_info, TOC0_ITEM_INFO_NAME_CERT, ++ &offset, &length); ++ if (!item_info) { ++ pr_err("Missing certificate item\n"); ++ goto err; ++ } ++ if (toc0_verify_cert_item(buf + offset, length, fw_key, digest)) ++ goto err; ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ if (fw_key != root_key) ++ RSA_free(fw_key); ++ ++ return ret; ++} ++ ++static int toc0_check_params(struct image_tool_params *params) ++{ ++ if (!params->dflag) ++ return -EINVAL; ++ ++ /* ++ * If a key directory was provided, look for key files there. ++ * Otherwise, look for them in the current directory. The key files are ++ * the "quoted" terms in the description below. ++ * ++ * A summary of the chain of trust on most SoCs: ++ * 1) eFuse contains a SHA256 digest of the public "root key". ++ * 2) Private "root key" signs the certificate item (generated here). ++ * 3) Certificate item contains a SHA256 digest of the firmware item. ++ * ++ * A summary of the chain of trust on the H6 (by default; a bit in the ++ * BROM_CONFIG eFuse makes it work like above): ++ * 1) eFuse contains a SHA256 digest of the public "root key". ++ * 2) Private "root key" signs the "key item" (generated here). ++ * 3) "Key item" contains the public "root key" and public "fw key". ++ * 4) Private "fw key" signs the certificate item (generated here). ++ * 5) Certificate item contains a SHA256 digest of the firmware item. ++ * ++ * This means there are three valid ways to generate a TOC0: ++ * 1) Provide the private "root key" only. This works everywhere. ++ * For H6, the "root key" will also be used as the "fw key". ++ * 2) FOR H6 ONLY: Provide the private "root key" and a separate ++ * private "fw key". ++ * 3) FOR H6 ONLY: Provide the private "fw key" and a pre-existing ++ * "key item" containing the corresponding public "fw key". ++ * In this case, the private "root key" can be kept offline. The ++ * "key item" can be extracted from a TOC0 image generated using ++ * method #2 above. ++ * ++ * Note that until the ROTPK_HASH eFuse is programmed, any "root key" ++ * will be accepted by the BROM. ++ */ ++ if (params->keydir) { ++ if (asprintf(&fw_key_file, "%s/%s", params->keydir, fw_key_file) < 0) ++ return -ENOMEM; ++ if (asprintf(&key_item_file, "%s/%s", params->keydir, key_item_file) < 0) ++ return -ENOMEM; ++ if (asprintf(&root_key_file, "%s/%s", params->keydir, root_key_file) < 0) ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int toc0_verify_header(unsigned char *buf, int image_size, ++ struct image_tool_params *params) ++{ ++ int ret = EXIT_FAILURE; ++ RSA *root_key = NULL; ++ FILE *fp; ++ ++ /* A root public key is optional. */ ++ fp = fopen(root_key_file, "rb"); ++ if (fp) { ++ pr_info("Verifying image with existing root key\n"); ++ root_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL); ++ if (!root_key) ++ root_key = PEM_read_RSAPublicKey(fp, NULL, NULL, NULL); ++ fclose(fp); ++ if (!root_key) { ++ pr_err("Failed to read public key from '%s'\n", ++ root_key_file); ++ goto err; ++ } ++ } ++ ++ ret = toc0_verify(buf, image_size, root_key); ++ ++err: ++ RSA_free(root_key); ++ ++ return ret; ++} ++ ++static const char *toc0_item_name(uint32_t name) ++{ ++ if (name == TOC0_ITEM_INFO_NAME_CERT) ++ return "Certificate"; ++ if (name == TOC0_ITEM_INFO_NAME_FIRMWARE) ++ return "Firmware"; ++ if (name == TOC0_ITEM_INFO_NAME_KEY) ++ return "Key"; ++ return "(unknown)"; ++} ++ ++static void toc0_print_header(const void *buf) ++{ ++ const struct toc0_main_info *main_info = buf; ++ const struct toc0_item_info *item_info = (void *)(main_info + 1); ++ uint32_t head_length, main_length, num_items; ++ uint32_t item_offset, item_length, item_name; ++ int load_addr = -1; ++ int i; ++ ++ num_items = le32_to_cpu(main_info->num_items); ++ head_length = sizeof(*main_info) + num_items * sizeof(*item_info); ++ main_length = le32_to_cpu(main_info->length); ++ ++ printf("Allwinner TOC0 Image\n" ++ "Size: %d bytes\n" ++ "Contents: %d items\n" ++ " 00000000:%08x Headers\n", ++ main_length, num_items, head_length); ++ ++ for (i = 0; i < num_items; ++i, ++item_info) { ++ item_offset = le32_to_cpu(item_info->offset); ++ item_length = le32_to_cpu(item_info->length); ++ item_name = le32_to_cpu(item_info->name); ++ ++ if (item_name == TOC0_ITEM_INFO_NAME_FIRMWARE) ++ load_addr = le32_to_cpu(item_info->load_addr); ++ ++ printf(" %08x:%08x %s\n", ++ item_offset, item_length, ++ toc0_item_name(item_name)); ++ } ++ ++ if (num_items && item_offset + item_length < main_length) { ++ item_offset = item_offset + item_length; ++ item_length = main_length - item_offset; ++ ++ printf(" %08x:%08x Padding\n", ++ item_offset, item_length); ++ } ++ ++ if (load_addr != -1) ++ printf("Load address: 0x%08x\n", load_addr); ++} ++ ++static void toc0_set_header(void *buf, struct stat *sbuf, int ifd, ++ struct image_tool_params *params) ++{ ++ uint32_t key_item_len = 0; ++ uint8_t *key_item = NULL; ++ int ret = EXIT_FAILURE; ++ RSA *root_key = NULL; ++ RSA *fw_key = NULL; ++ FILE *fp; ++ ++ /* Either a key item or the root private key is required. */ ++ fp = fopen(key_item_file, "rb"); ++ if (fp) { ++ pr_info("Creating image using existing key item\n"); ++ key_item_len = sizeof(struct toc0_key_item); ++ key_item = OPENSSL_malloc(key_item_len); ++ if (!key_item || fread(key_item, key_item_len, 1, fp) != 1) { ++ pr_err("Failed to read key item from '%s'\n", ++ root_key_file); ++ goto err; ++ } ++ fclose(fp); ++ fp = NULL; ++ } ++ ++ fp = fopen(root_key_file, "rb"); ++ if (fp) { ++ root_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL); ++ if (!root_key) ++ root_key = PEM_read_RSAPublicKey(fp, NULL, NULL, NULL); ++ fclose(fp); ++ fp = NULL; ++ } ++ ++ /* When using an existing key item, the root key is optional. */ ++ if (!key_item && (!root_key || !RSA_get0_d(root_key))) { ++ pr_err("Failed to read private key from '%s'\n", ++ root_key_file); ++ pr_info("Try 'openssl genrsa -out root_key.pem'\n"); ++ goto err; ++ } ++ ++ /* The certificate/firmware private key is always required. */ ++ fp = fopen(fw_key_file, "rb"); ++ if (fp) { ++ fw_key = PEM_read_RSAPrivateKey(fp, NULL, NULL, NULL); ++ fclose(fp); ++ fp = NULL; ++ } ++ if (!fw_key) { ++ /* If the root key is a private key, it can be used instead. */ ++ if (root_key && RSA_get0_d(root_key)) { ++ pr_info("Using root key as firmware key\n"); ++ fw_key = root_key; ++ } else { ++ pr_err("Failed to read private key from '%s'\n", ++ fw_key_file); ++ goto err; ++ } ++ } ++ ++ /* Warn about potential compatibility issues. */ ++ if (key_item || fw_key != root_key) ++ pr_warn("Only H6 supports separate root and firmware keys\n"); ++ ++ ret = toc0_create(buf, params->file_size, root_key, fw_key, ++ key_item, key_item_len, ++ buf + TOC0_DEFAULT_HEADER_LEN, ++ params->orig_file_size, params->addr); ++ ++err: ++ OPENSSL_free(key_item); ++ OPENSSL_free(root_key); ++ if (fw_key != root_key) ++ OPENSSL_free(fw_key); ++ if (fp) ++ fclose(fp); ++ ++ if (ret != EXIT_SUCCESS) ++ exit(ret); ++} ++ ++static int toc0_check_image_type(uint8_t type) ++{ ++ return type == IH_TYPE_SUNXI_TOC0 ? 0 : 1; ++} ++ ++static int toc0_vrec_header(struct image_tool_params *params, ++ struct image_type_params *tparams) ++{ ++ tparams->hdr = calloc(tparams->header_size, 1); ++ ++ /* Save off the unpadded data size for SHA256 calculation. */ ++ params->orig_file_size = params->file_size - TOC0_DEFAULT_HEADER_LEN; ++ ++ /* Return padding to 8K blocks. */ ++ return ALIGN(params->file_size, PAD_SIZE) - params->file_size; ++} ++ ++U_BOOT_IMAGE_TYPE( ++ sunxi_toc0, ++ "Allwinner TOC0 Boot Image support", ++ TOC0_DEFAULT_HEADER_LEN, ++ NULL, ++ toc0_check_params, ++ toc0_verify_header, ++ toc0_print_header, ++ toc0_set_header, ++ NULL, ++ toc0_check_image_type, ++ NULL, ++ toc0_vrec_header ++); +diff -ruN u-boot-2021.10/tools/sunxi_toc1.c u-boot/tools/sunxi_toc1.c +--- u-boot-2021.10/tools/sunxi_toc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/tools/sunxi_toc1.c 2021-11-01 17:10:14.792896833 +0100 +@@ -0,0 +1,314 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018 Arm Ltd. ++ * (C) Copyright 2020-2021 Samuel Holland <samuel@sholland.org> ++ */ ++ ++#include <assert.h> ++#include <stdint.h> ++#include <stdio.h> ++#include <stdlib.h> ++#include <string.h> ++ ++#include <image.h> ++#include <sunxi_image.h> ++ ++#include "imagetool.h" ++#include "mkimage.h" ++ ++#define SECTOR_SIZE 512 ++ ++struct item_desc { ++ const char *name; ++ const char *file; ++ unsigned long addr; ++ long length; ++}; ++ ++static uint32_t toc1_header_length(uint32_t num_items) ++{ ++ return ALIGN(sizeof(struct toc1_main_info) + ++ sizeof(struct toc1_item_info) * num_items, SECTOR_SIZE); ++} ++ ++static int toc1_parse_cfg(const char *file, struct item_desc **desc, ++ uint32_t *main_length, uint32_t *num_items) ++{ ++ struct item_desc *descs = NULL; ++ int ret = EXIT_FAILURE; ++ FILE *cfg, *fp = NULL; ++ uint32_t ndescs = 0; ++ char *line = NULL; ++ size_t len = 0; ++ ++ *desc = NULL; ++ *main_length = 0; ++ *num_items = 0; ++ ++ cfg = fopen(file, "r"); ++ if (!cfg) ++ return ret; ++ ++ while (getline(&line, &len, cfg) > 0) { ++ char *end, *s; ++ ++ if (line[0] == '[') { ++ s = line + 1; ++ if (!(end = strchr(s, ']')) || end[1] != '\n') ++ goto err; ++ end[0] = '\0'; ++ ++ ndescs++; ++ descs = reallocarray(descs, ndescs, sizeof(*descs)); ++ if (!descs) ++ goto err; ++ ++ descs[ndescs - 1].name = strdup(s); ++ } else if (line[0] != '#' && line[0] != '\n') { ++ if (!(s = strchr(line, '='))) ++ goto err; ++ while ((++s)[0] == ' '); ++ if (!(end = strchr(s, '\n'))) ++ goto err; ++ end[0] = '\0'; ++ ++ if (!strncmp(line, "file", strlen("file"))) { ++ fp = fopen(s, "rb"); ++ if (!fp) ++ goto err; ++ if (fseek(fp, 0, SEEK_END) < 0) ++ goto err; ++ descs[ndescs - 1].file = strdup(s); ++ descs[ndescs - 1].length = ftell(fp); ++ *main_length += ALIGN(descs[ndescs - 1].length, ++ SECTOR_SIZE); ++ fclose(fp); ++ fp = NULL; ++ } else if (!strncmp(line, "addr", strlen("addr"))) { ++ descs[ndescs - 1].addr = strtoul(s, NULL, 0); ++ } else { ++ goto err; ++ } ++ } ++ } ++ ++ *desc = descs; ++ *main_length += toc1_header_length(ndescs); ++ *num_items = ndescs; ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ if (fp) ++ fclose(fp); ++ if (ret) ++ free(descs); ++ free(line); ++ fclose(cfg); ++ ++ return ret; ++} ++ ++static int toc1_create(uint8_t *buf, uint32_t len, ++ const struct item_desc *desc, uint32_t num_items) ++{ ++ struct toc1_main_info *main = (void *)buf; ++ struct toc1_item_info *item = (void *)(main + 1); ++ uint32_t item_offset, item_length; ++ uint32_t *buf32 = (void *)buf; ++ int ret = EXIT_FAILURE; ++ uint32_t checksum = 0; ++ FILE *fp = NULL; ++ int i; ++ ++ /* Create the main TOC1 header. */ ++ main->magic = cpu_to_le32(TOC0_MAIN_INFO_MAGIC); ++ main->checksum = cpu_to_le32(BROM_STAMP_VALUE); ++ main->num_items = cpu_to_le32(num_items); ++ memcpy(main->end, TOC0_MAIN_INFO_END, sizeof(main->end)); ++ ++ item_offset = 0; ++ item_length = toc1_header_length(num_items); ++ ++ for (i = 0; i < num_items; ++i, ++item, ++desc) { ++ item_offset = item_offset + item_length; ++ item_length = desc->length; ++ ++ /* Create the item header. */ ++ memcpy(item->name, desc->name, ++ strnlen(desc->name, sizeof(item->name))); ++ item->offset = cpu_to_le32(item_offset); ++ item->length = cpu_to_le32(item_length); ++ item->load_addr = cpu_to_le32(desc->addr); ++ memcpy(item->end, TOC0_ITEM_INFO_END, sizeof(item->end)); ++ ++ /* Read in the data. */ ++ fp = fopen(desc->file, "rb"); ++ if (!fp) ++ goto err; ++ if (!fread(buf + item_offset, item_length, 1, fp)) ++ goto err; ++ fclose(fp); ++ fp = NULL; ++ ++ /* Pad the sectors with 0xff to be flash-friendly. */ ++ item_offset = item_offset + item_length; ++ item_length = ALIGN(item_offset, SECTOR_SIZE) - item_offset; ++ memset(buf + item_offset, 0xff, item_length); ++ } ++ ++ /* Fill in the total padded file length. */ ++ item_offset = item_offset + item_length; ++ main->length = cpu_to_le32(item_offset); ++ ++ /* Verify enough space was provided when creating the image. */ ++ assert(len >= item_offset); ++ ++ /* Calculate the checksum. Yes, it's that simple. */ ++ for (i = 0; i < item_offset / 4; ++i) ++ checksum += le32_to_cpu(buf32[i]); ++ main->checksum = cpu_to_le32(checksum); ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ if (fp) ++ fclose(fp); ++ ++ return ret; ++} ++ ++static int toc1_verify(const uint8_t *buf, uint32_t len) ++{ ++ const struct toc1_main_info *main = (void *)buf; ++ const struct toc1_item_info *item = (void *)(main + 1); ++ uint32_t checksum = BROM_STAMP_VALUE; ++ uint32_t main_length, num_items; ++ uint32_t *buf32 = (void *)buf; ++ int ret = EXIT_FAILURE; ++ int i; ++ ++ num_items = le32_to_cpu(main->num_items); ++ main_length = le32_to_cpu(main->length); ++ ++ if (len < main_length || main_length < toc1_header_length(num_items)) ++ goto err; ++ ++ /* Verify the main header. */ ++ if (le32_to_cpu(main->magic) != TOC0_MAIN_INFO_MAGIC) ++ goto err; ++ /* Verify the checksum without modifying the buffer. */ ++ for (i = 0; i < main_length / 4; ++i) ++ checksum += le32_to_cpu(buf32[i]); ++ if (checksum != 2 * le32_to_cpu(main->checksum)) ++ goto err; ++ /* The length must be at least 512 byte aligned. */ ++ if (main_length % 512) ++ goto err; ++ if (memcmp(main->end, TOC0_MAIN_INFO_END, sizeof(main->end))) ++ goto err; ++ ++ /* Verify each item header. */ ++ for (i = 0; i < num_items; ++i, ++item) ++ if (memcmp(item->end, TOC0_ITEM_INFO_END, sizeof(item->end))) ++ goto err; ++ ++ ret = EXIT_SUCCESS; ++ ++err: ++ return ret; ++} ++ ++static int toc1_check_params(struct image_tool_params *params) ++{ ++ if (!params->dflag) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int toc1_verify_header(unsigned char *buf, int image_size, ++ struct image_tool_params *params) ++{ ++ return toc1_verify(buf, image_size); ++} ++ ++static void toc1_print_header(const void *buf) ++{ ++ const struct toc1_main_info *main = buf; ++ const struct toc1_item_info *item = (void *)(main + 1); ++ uint32_t head_length, main_length, num_items; ++ uint32_t item_offset, item_length, item_addr; ++ int i; ++ ++ num_items = le32_to_cpu(main->num_items); ++ head_length = sizeof(*main) + num_items * sizeof(*item); ++ main_length = le32_to_cpu(main->length); ++ ++ printf("Allwinner TOC1 Image\n" ++ "Size: %d bytes\n" ++ "Contents: %d items\n" ++ " 00000000:%08x Headers\n", ++ main_length, num_items, head_length); ++ ++ for (i = 0; i < num_items; ++i, ++item) { ++ item_offset = le32_to_cpu(item->offset); ++ item_length = le32_to_cpu(item->length); ++ item_addr = le32_to_cpu(item->load_addr); ++ ++ printf(" %08x:%08x => %08x %s\n", ++ item_offset, item_length, item_addr, item->name); ++ } ++} ++ ++static void toc1_set_header(void *buf, struct stat *sbuf, int ifd, ++ struct image_tool_params *params) ++{ ++ /* Image is already written below. */ ++} ++ ++static int toc1_check_image_type(uint8_t type) ++{ ++ return type == IH_TYPE_SUNXI_TOC1 ? 0 : 1; ++} ++ ++static int toc1_vrec_header(struct image_tool_params *params, ++ struct image_type_params *tparams) ++{ ++ uint32_t main_length, num_items; ++ struct item_desc *desc; ++ int ret; ++ ++ /* This "header" contains the entire image. */ ++ params->skipcpy = 1; ++ ++ ret = toc1_parse_cfg(params->datafile, &desc, &main_length, &num_items); ++ if (ret) ++ exit(ret); ++ ++ tparams->header_size = main_length; ++ tparams->hdr = calloc(tparams->header_size, 1); ++ if (!tparams->hdr) ++ exit(ret); ++ ++ ret = toc1_create(tparams->hdr, tparams->header_size, desc, num_items); ++ if (ret) ++ exit(ret); ++ ++ return 0; ++} ++ ++U_BOOT_IMAGE_TYPE( ++ sunxi_toc1, ++ "Allwinner TOC1 Boot Image support", ++ 0, ++ NULL, ++ toc1_check_params, ++ toc1_verify_header, ++ toc1_print_header, ++ toc1_set_header, ++ NULL, ++ toc1_check_image_type, ++ NULL, ++ toc1_vrec_header ++); +diff -ruN u-boot-2021.10/tools/termios_linux.h u-boot/tools/termios_linux.h +--- u-boot-2021.10/tools/termios_linux.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/tools/termios_linux.h 2021-11-01 17:10:14.792896833 +0100 +@@ -0,0 +1,189 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * termios fuctions to support arbitrary baudrates (on Linux) ++ * ++ * Copyright (c) 2021 Pali Rohár <pali@kernel.org> ++ * Copyright (c) 2021 Marek Behún <marek.behun@nic.cz> ++ */ ++ ++#ifndef _TERMIOS_LINUX_H_ ++#define _TERMIOS_LINUX_H_ ++ ++/* ++ * We need to use raw TCGETS2/TCSETS2 or TCGETS/TCSETS ioctls with the BOTHER ++ * flag in struct termios2/termios, defined in Linux headers <asm/ioctls.h> ++ * (included by <sys/ioctl.h>) and <asm/termbits.h>. Since these headers ++ * conflict with glibc's header file <termios.h>, it is not possible to use ++ * libc's termios functions and we need to reimplement them via ioctl() calls. ++ * ++ * An arbitrary baudrate is supported when the macro BOTHER is defined. The ++ * baudrate value itself is then stored into the c_ospeed and c_ispeed members. ++ * If ioctls TCGETS2/TCSETS2 are defined and supported then these fields are ++ * present in struct termios2, otherwise these fields are present in struct ++ * termios. ++ * ++ * Note that the Bnnn constants from <termios.h> need not be compatible with Bnnn ++ * constants from <asm/termbits.h>. ++ */ ++ ++#include <errno.h> ++#include <sys/ioctl.h> ++#include <sys/types.h> ++#include <asm/termbits.h> ++ ++#if defined(BOTHER) && defined(TCGETS2) ++#define termios termios2 ++#endif ++ ++static inline int tcgetattr(int fd, struct termios *t) ++{ ++#if defined(BOTHER) && defined(TCGETS2) ++ return ioctl(fd, TCGETS2, t); ++#else ++ return ioctl(fd, TCGETS, t); ++#endif ++} ++ ++static inline int tcsetattr(int fd, int a, const struct termios *t) ++{ ++ int cmd; ++ ++ switch (a) { ++#if defined(BOTHER) && defined(TCGETS2) ++ case TCSANOW: ++ cmd = TCSETS2; ++ break; ++ case TCSADRAIN: ++ cmd = TCSETSW2; ++ break; ++ case TCSAFLUSH: ++ cmd = TCSETSF2; ++ break; ++#else ++ case TCSANOW: ++ cmd = TCSETS; ++ break; ++ case TCSADRAIN: ++ cmd = TCSETSW; ++ break; ++ case TCSAFLUSH: ++ cmd = TCSETSF; ++ break; ++#endif ++ default: ++ errno = EINVAL; ++ return -1; ++ } ++ ++ return ioctl(fd, cmd, t); ++} ++ ++static inline int tcdrain(int fd) ++{ ++ return ioctl(fd, TCSBRK, 1); ++} ++ ++static inline int tcflush(int fd, int q) ++{ ++ return ioctl(fd, TCFLSH, q); ++} ++ ++static inline int tcsendbreak(int fd, int d) ++{ ++ return ioctl(fd, TCSBRK, d); ++} ++ ++static inline int tcflow(int fd, int a) ++{ ++ return ioctl(fd, TCXONC, a); ++} ++ ++static inline pid_t tcgetsid(int fd) ++{ ++ pid_t sid; ++ ++ if (ioctl(fd, TIOCGSID, &sid) < 0) ++ return (pid_t)-1; ++ ++ return sid; ++} ++ ++static inline speed_t cfgetospeed(const struct termios *t) ++{ ++ return t->c_cflag & CBAUD; ++} ++ ++static inline int cfsetospeed(struct termios *t, speed_t s) ++{ ++ if (s & ~CBAUD) { ++ errno = EINVAL; ++ return -1; ++ } ++ ++ t->c_cflag &= ~CBAUD; ++ t->c_cflag |= s; ++ ++ return 0; ++} ++ ++#ifdef IBSHIFT ++static inline speed_t cfgetispeed(const struct termios *t) ++{ ++ speed_t s = (t->c_cflag >> IBSHIFT) & CBAUD; ++ ++ if (s == B0) ++ return cfgetospeed(t); ++ else ++ return s; ++} ++ ++static inline int cfsetispeed(struct termios *t, speed_t s) ++{ ++ if (s == 0) ++ s = B0; ++ ++ if (s & ~CBAUD) { ++ errno = EINVAL; ++ return -1; ++ } ++ ++ t->c_cflag &= ~(CBAUD << IBSHIFT); ++ t->c_cflag |= s << IBSHIFT; ++ ++ return 0; ++} ++#else /* !IBSHIFT */ ++static inline speed_t cfgetispeed(const struct termios *t) ++{ ++ return cfgetospeed(t); ++} ++ ++static inline int cfsetispeed(struct termios *t, speed_t s) ++{ ++ return cfsetospeed(t, s); ++} ++#endif /* !IBSHIFT */ ++ ++static inline int cfsetspeed(struct termios *t, speed_t s) ++{ ++ if (cfsetospeed(t, s)) ++ return -1; ++#ifdef IBSHIFT ++ if (cfsetispeed(t, s)) ++ return -1; ++#endif ++ ++ return 0; ++} ++ ++static void cfmakeraw(struct termios *t) ++{ ++ t->c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | ++ ICRNL | IXON); ++ t->c_oflag &= ~OPOST; ++ t->c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); ++ t->c_cflag &= ~(CSIZE | PARENB); ++ t->c_cflag |= CS8; ++} ++ ++#endif /* _TERMIOS_LINUX_H_ */ diff --git a/package/boot/uboot-sunxid1/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-sunxid1/patches/002-spl-remove-dtoc-of-pdata-generation.patch new file mode 100644 index 0000000000..14bcbfb630 --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -0,0 +1,28 @@ +From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001 +From: David Bauer <mail@david-bauer.net> +Date: Tue, 14 Jul 2020 22:44:22 +0200 +Subject: [PATCH] spl: remove dtoc of-pdata generation + +Remove the dtoc of-pdata generation. This generation is dependant on +libpython-dev. As OpenWrt does not ship with this dependency, use +pre-generated pdata files and remove the generation from the +build-process. + +This only affects RK3328 boards. + +Signed-off-by: David Bauer <mail@david-bauer.net> +--- + scripts/Makefile.spl | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/scripts/Makefile.spl ++++ b/scripts/Makefile.spl +@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) + @# of OF_PLATDATA_INST and this might change between builds. Leaving old + @# ones around is confusing and it is possible that switching the + @# setting again will use the old one instead of regenerating it. +- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) +- $(call if_changed,dtoc) + + ifdef CONFIG_SAMSUNG + ifdef CONFIG_VAR_SIZE_SPL diff --git a/package/boot/uboot-sunxid1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch b/package/boot/uboot-sunxid1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch new file mode 100644 index 0000000000..482aa1a369 --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/100-mkimage-check-environment-for-dtc-binary-location.patch @@ -0,0 +1,35 @@ +From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Wed, 19 Jul 2017 22:23:15 +0200 +Subject: mkimage: check environment for dtc binary location + +Currently mkimage assumes the dtc binary is in the path and fails +otherwise. This patch makes it check the DTC environment variable first +for the dtc binary and then fall back to the default path. This makes +it possible to call the u-boot build with make DTC=... and build a fit +image with the dtc binary not being the the default path. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +Cc: Simon Glass <sjg@chromium.org> +--- + tools/fit_image.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/tools/fit_image.c ++++ b/tools/fit_image.c +@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_ + } + *cmd = '\0'; + } else if (params->datafile) { ++ const char* dtc = getenv("DTC"); ++ ++ if (!dtc) ++ dtc = MKIMAGE_DTC; ++ + /* dtc -I dts -O dtb -p 500 -o tmpfile datafile */ + snprintf(cmd, sizeof(cmd), "%s %s -o \"%s\" \"%s\"", +- MKIMAGE_DTC, params->dtc, tmpfile, params->datafile); ++ dtc, params->dtc, tmpfile, params->datafile); + debug("Trying to execute \"%s\"\n", cmd); + } else { + snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"", diff --git a/package/boot/uboot-sunxid1/patches/102-disable-libcrypto.diff b/package/boot/uboot-sunxid1/patches/102-disable-libcrypto.diff new file mode 100644 index 0000000000..bfa68ebbad --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/102-disable-libcrypto.diff @@ -0,0 +1,32 @@ +diff -ruN u-boot-2021.10.old/arch/arm/Kconfig u-boot-2021.10/arch/arm/Kconfig +--- u-boot-2021.10.old/arch/arm/Kconfig 2021-11-09 16:09:43.034360581 +0100 ++++ u-boot-2021.10/arch/arm/Kconfig 2021-11-09 16:04:49.197044604 +0100 +@@ -1046,7 +1046,7 @@ + select SUNXI_GPIO + select SYS_NS16550 + select SYS_THUMB_BUILD if !ARM64 +- select TOOLS_LIBCRYPTO ++# select TOOLS_LIBCRYPTO + select USB if DISTRO_DEFAULTS + select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST + select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST +diff -ruN u-boot-2021.10.old/board/sunxi/Kconfig u-boot-2021.10/board/sunxi/Kconfig +--- u-boot-2021.10.old/board/sunxi/Kconfig 2021-11-09 16:09:50.733940804 +0100 ++++ u-boot-2021.10/board/sunxi/Kconfig 2021-11-09 16:06:23.691894152 +0100 +@@ -90,7 +90,7 @@ + select SPL_PINCTRL if SPL_DM + select SPL_SEPARATE_BSS if SPL + select SUPPORT_SPL +- select TOOLS_LIBCRYPTO ++# select TOOLS_LIBCRYPTO + imply CMD_MMC + imply CMD_USB + imply DISTRO_DEFAULTS +diff -ruN u-boot-2021.10.old/configs/nezha_defconfig u-boot-2021.10/configs/nezha_defconfig +--- u-boot-2021.10.old/configs/nezha_defconfig 2021-11-09 16:02:08.392474691 +0100 ++++ u-boot-2021.10/configs/nezha_defconfig 2021-11-09 16:13:19.585885123 +0100 +@@ -30,3 +30,4 @@ + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_FUNCTION_MASS_STORAGE=y ++CONFIG_TOOLS_LIBCRYPTO=n diff --git a/package/boot/uboot-sunxid1/patches/103-increate-bootm-size-to-32M.patch b/package/boot/uboot-sunxid1/patches/103-increate-bootm-size-to-32M.patch new file mode 100644 index 0000000000..378b5828cc --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/103-increate-bootm-size-to-32M.patch @@ -0,0 +1,12 @@ +diff -ruN u-boot-2021.10.old/include/configs/sun20i.h u-boot-2021.10/include/configs/sun20i.h +--- u-boot-2021.10.old/include/configs/sun20i.h 2021-11-10 23:35:28.812751311 +0100 ++++ u-boot-2021.10/include/configs/sun20i.h 2021-11-11 00:06:30.907626642 +0100 +@@ -11,6 +11,8 @@ + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + #endif + ++#define CONFIG_SYS_BOOTM_LEN (32 << 20) ++ + #define CONFIG_SYS_INIT_SP_ADDR 0x4fe00000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ + #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 diff --git a/package/boot/uboot-sunxid1/patches/104-arch-riscv-dts-sun20i-d1.dtsi-adjust-plic-compatible.patch b/package/boot/uboot-sunxid1/patches/104-arch-riscv-dts-sun20i-d1.dtsi-adjust-plic-compatible.patch new file mode 100644 index 0000000000..3524f44a61 --- /dev/null +++ b/package/boot/uboot-sunxid1/patches/104-arch-riscv-dts-sun20i-d1.dtsi-adjust-plic-compatible.patch @@ -0,0 +1,36 @@ +From 99cf8f37ceb1def9e7bbaccc395cf2275723e03d Mon Sep 17 00:00:00 2001 +From: Peter Korsgaard <peter@korsgaard.com> +Date: Thu, 4 Nov 2021 22:15:13 +0100 +Subject: [PATCH] arch/riscv/dts/sun20i-d1.dtsi: adjust plic compatible to + match opensbi + +The T-HEAD PLIC is by default not accessible from S-mode, and access must be +enabled by opensbi to make it accessible to Linux. + +The DTB is used both by U-Boot and opensbi (but the PLIC node is ignored by +U-Boot), so change the compatible to match what opensbi expects to fix a +crash during Linux boot: + +https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd + +Signed-off-by: Peter Korsgaard <peter@korsgaard.com> +--- + arch/riscv/dts/sun20i-d1.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/dts/sun20i-d1.dtsi b/arch/riscv/dts/sun20i-d1.dtsi +index 280e0336d4..56d02c33b0 100644 +--- a/arch/riscv/dts/sun20i-d1.dtsi ++++ b/arch/riscv/dts/sun20i-d1.dtsi +@@ -1136,7 +1136,7 @@ + + plic: interrupt-controller@10000000 { + compatible = "allwinner,sun20i-d1-plic", +- "sifive,plic-1.0.0"; ++ "thead,c900-plic"; + reg = <0x10000000 0x4000000>; + #address-cells = <0>; + interrupts-extended = <&cpu0_intc 11>, +-- +2.20.1 + diff --git a/package/boot/uboot-sunxid1/uEnv-default.txt b/package/boot/uboot-sunxid1/uEnv-default.txt new file mode 100644 index 0000000000..362cadcbcf --- /dev/null +++ b/package/boot/uboot-sunxid1/uEnv-default.txt @@ -0,0 +1,4 @@ +setenv loadkernel fatload mmc 0 0x45000000 uImage +setenv bootargs console=ttyS0,115200 earlycon=sbi root=/dev/mmcblk0p2 rootwait +setenv uenvcmd run loadkernel \&\& bootm 0x45000000 +run uenvcmd -- 2.30.2