From 77f3e2ea17a751aee5d3cbd2abf83dd94911e38c Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Mon, 17 Jan 2022 21:48:51 +0100 Subject: [PATCH] realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filtering Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall Signed-off-by: Birger Koblitz --- .../files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 39 +++++++++----- .../drivers/net/dsa/rtl83xx/rtl838x.c | 36 +++++++++++-- .../drivers/net/dsa/rtl83xx/rtl838x.h | 19 +++++-- .../drivers/net/dsa/rtl83xx/rtl839x.c | 36 +++++++++++-- .../drivers/net/dsa/rtl83xx/rtl930x.c | 36 +++++++++++-- .../drivers/net/dsa/rtl83xx/rtl931x.c | 51 +++++++++++++++++-- 6 files changed, 189 insertions(+), 28 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index 345b94bcdc..0cd4e0d5dd 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -142,8 +142,12 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) priv->r->vlan_set_tagged(i, &info); // reset PVIDs; defaults to 1 on reset - for (i = 0; i <= priv->ds->num_ports; i++) - sw_w32(0, priv->r->vlan_port_pb + (i << 2)); + for (i = 0; i <= priv->ds->num_ports; i++) { + priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0); + priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0); + priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG); + priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG); + } // Set forwarding action based on inner VLAN tag for (i = 0; i < priv->cpu_port; i++) @@ -1223,15 +1227,15 @@ static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port, * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED) */ if (port != priv->cpu_port) - sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1), - priv->r->vlan_port_igr_filter + ((port >> 4) << 2)); - sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 5) << 2)); + priv->r->set_vlan_igr_filter(port, IGR_DROP); + + priv->r->set_vlan_egr_filter(port, EGR_ENABLE); } else { /* Disable ingress and egress filtering */ if (port != priv->cpu_port) - sw_w32_mask(0b11 << ((port % 16) << 1), 0, - priv->r->vlan_port_igr_filter + ((port >> 4) << 2)); - sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 5) << 2)); + priv->r->set_vlan_igr_filter(port, IGR_FORWARD); + + priv->r->set_vlan_egr_filter(port, EGR_DISABLE); } /* Do we need to do something to the CPU-Port, too? */ @@ -1289,7 +1293,13 @@ static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, if (!v) continue; /* Set both inner and outer PVID of the port */ - sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2)); + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v); + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + priv->ports[port].pvid = vlan->vid_end; } } @@ -1346,9 +1356,14 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { /* Reset to default if removing the current PVID */ - if (v == pvid) - sw_w32(0, priv->r->vlan_port_pb + (port << 2)); - + if (v == pvid) { + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0); + priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, + PBVLAN_MODE_UNTAG_AND_PRITAG); + } /* Get port memberships of this vlan */ priv->r->vlan_tables_read(v, &info); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c index 7470fff5eb..cefae82573 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c @@ -1581,6 +1581,35 @@ static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv) return 0; } +void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl838x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), + RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl838x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d), + RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); +} + + const struct rtl838x_reg rtl838x_reg = { .mask_port_reg_be = rtl838x_mask_port_reg, .set_port_reg_be = rtl838x_set_port_reg, @@ -1615,6 +1644,8 @@ const struct rtl838x_reg rtl838x_reg = { .vlan_profile_dump = rtl838x_vlan_profile_dump, .vlan_profile_setup = rtl838x_vlan_profile_setup, .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner, + .set_vlan_igr_filter = rtl838x_set_igr_filter, + .set_vlan_egr_filter = rtl838x_set_egr_filter, .stp_get = rtl838x_stp_get, .stp_set = rtl838x_stp_set, .mac_port_ctrl = rtl838x_mac_port_ctrl, @@ -1632,10 +1663,9 @@ const struct rtl838x_reg rtl838x_reg = { .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash, .read_cam = rtl838x_read_cam, .write_cam = rtl838x_write_cam, - .vlan_port_egr_filter = RTL838X_VLAN_PORT_EGR_FLTR, - .vlan_port_igr_filter = RTL838X_VLAN_PORT_IGR_FLTR, - .vlan_port_pb = RTL838X_VLAN_PORT_PB_VLAN, .vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL, + .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set, .trk_mbr_ctr = rtl838x_trk_mbr_ctr, .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK, .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL, diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h index a334a5ddbb..fd2c6d3245 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h @@ -86,6 +86,7 @@ #define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28))) #define RTL931X_VLAN_CTRL (0x94E4) +#define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8) #define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4) #define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4) #define RTL931X_VLAN_PORT_TAG_CTRL (0x4860) @@ -458,6 +459,17 @@ enum phy_type { PHY_RTL930X_SDS = 6, }; +enum pbvlan_type { + PBVLAN_TYPE_INNER = 0, + PBVLAN_TYPE_OUTER, +}; + +enum pbvlan_mode { + PBVLAN_MODE_UNTAG_AND_PRITAG = 0, + PBVLAN_MODE_UNTAG_ONLY, + PBVLAN_MODE_ALL_PKT, +}; + struct rtl838x_port { bool enable; u64 pm; @@ -816,6 +828,10 @@ struct rtl838x_reg { void (*vlan_set_untagged)(u32 vlan, u64 portmask); void (*vlan_profile_dump)(int index); void (*vlan_profile_setup)(int profile); + void (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode); + void (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid); + void (*set_vlan_igr_filter)(int port, enum igr_filter state); + void (*set_vlan_egr_filter)(int port, enum egr_filter state); void (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); int (*mac_force_mode_ctrl)(int port); @@ -834,9 +850,6 @@ struct rtl838x_reg { void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e); u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e); void (*write_cam)(int idx, struct rtl838x_l2_entry *e); - int vlan_port_egr_filter; - int vlan_port_igr_filter; - int vlan_port_pb; int vlan_port_tag_sts_ctrl; int (*rtl838x_vlan_port_tag_sts_ctrl)(int port); int (*trk_mbr_ctr)(int group); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c index 3c85e736c9..8253cf1b34 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c @@ -1705,6 +1705,35 @@ int rtl839x_l3_setup(struct rtl838x_switch_priv *priv) return 0; } +void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl839x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), + RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl839x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), + RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); +} + + const struct rtl838x_reg rtl839x_reg = { .mask_port_reg_be = rtl839x_mask_port_reg_be, .set_port_reg_be = rtl839x_set_port_reg_be, @@ -1738,6 +1767,10 @@ const struct rtl838x_reg rtl839x_reg = { .vlan_profile_dump = rtl839x_vlan_profile_dump, .vlan_profile_setup = rtl839x_vlan_profile_setup, .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner, + .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set, + .set_vlan_igr_filter = rtl839x_set_igr_filter, + .set_vlan_egr_filter = rtl839x_set_egr_filter, .stp_get = rtl839x_stp_get, .stp_set = rtl839x_stp_set, .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, @@ -1756,9 +1789,6 @@ const struct rtl838x_reg rtl839x_reg = { .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash, .read_cam = rtl839x_read_cam, .write_cam = rtl839x_write_cam, - .vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR, - .vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR, - .vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN, .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL, .trk_mbr_ctr = rtl839x_trk_mbr_ctr, .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK, diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c index 92426be1f3..04be44fc90 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c @@ -688,7 +688,6 @@ void rtl9300_dump_debug(void) irqreturn_t rtl930x_switch_irq(int irq, void *dev_id) { struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL930X_ISR_GLB); u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG); u32 link; int i; @@ -2317,6 +2316,34 @@ static void rtl930x_packet_cntr_clear(int counter) rtl_table_release(r); } +void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); + else + sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); +} + +static void rtl930x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), + RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl930x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D), + RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); +} + const struct rtl838x_reg rtl930x_reg = { .mask_port_reg_be = rtl838x_mask_port_reg, .set_port_reg_be = rtl838x_set_port_reg, @@ -2349,6 +2376,8 @@ const struct rtl838x_reg rtl930x_reg = { .vlan_profile_dump = rtl930x_vlan_profile_dump, .vlan_profile_setup = rtl930x_vlan_profile_setup, .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner, + .set_vlan_igr_filter = rtl930x_set_igr_filter, + .set_vlan_egr_filter = rtl930x_set_egr_filter, .stp_get = rtl930x_stp_get, .stp_set = rtl930x_stp_set, .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl, @@ -2367,10 +2396,9 @@ const struct rtl838x_reg rtl930x_reg = { .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash, .read_cam = rtl930x_read_cam, .write_cam = rtl930x_write_cam, - .vlan_port_egr_filter = RTL930X_VLAN_PORT_EGR_FLTR, - .vlan_port_igr_filter = RTL930X_VLAN_PORT_IGR_FLTR, - .vlan_port_pb = RTL930X_VLAN_PORT_PB_VLAN, .vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL, + .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set, .trk_mbr_ctr = rtl930x_trk_mbr_ctr, .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK, .init_eee = rtl930x_init_eee, diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c index d347b9543e..f61652f393 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c @@ -342,6 +342,50 @@ void rtl931x_print_matrix(void) pr_info("CPU_PORT> %16llx\n", ptr[52]); } + +static int rtl931x_set_ageing_time(unsigned long msec) +{ + int t = sw_r32(RTL931X_L2_AGE_CTRL); + + t &= 0x1FFFFF; + t = (t * 8) / 10; + pr_debug("L2 AGING time: %d sec\n", t); + + t = (msec / 100 + 7) / 8; + t = t > 0x1FFFFF ? 0x1FFFFF : t; + sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL)); + return 0; +} + +void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); + else + sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); +} + +void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) +{ + if (type == PBVLAN_TYPE_INNER) + sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); + else + sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); +} + +static void rtl931x_set_igr_filter(int port, enum igr_filter state) +{ + sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), + RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); +} + +static void rtl931x_set_egr_filter(int port, enum egr_filter state) +{ + sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), + RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); +} + const struct rtl838x_reg rtl931x_reg = { .mask_port_reg_be = rtl839x_mask_port_reg_be, .set_port_reg_be = rtl839x_set_port_reg_be, @@ -384,10 +428,11 @@ const struct rtl838x_reg rtl931x_reg = { .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS, .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash, .read_cam = rtl931x_read_cam, - .vlan_port_egr_filter = RTL931X_VLAN_PORT_EGR_FLTR, - .vlan_port_igr_filter = RTL931X_VLAN_PORT_IGR_FLTR, -// .vlan_port_pb = does not exist .vlan_port_tag_sts_ctrl = RTL931X_VLAN_PORT_TAG_CTRL, + .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set, + .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set, .trk_mbr_ctr = rtl931x_trk_mbr_ctr, + .set_vlan_igr_filter = rtl931x_set_igr_filter, + .set_vlan_egr_filter = rtl931x_set_egr_filter, }; -- 2.30.2