From 75cbec033c08f6d41c4775784f66ab860d02a6b5 Mon Sep 17 00:00:00 2001 From: =?utf8?q?os=C3=A9=20Roberto=20de=20Souza?= Date: Wed, 25 Apr 2018 14:23:31 -0700 Subject: [PATCH] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Any write in any display register was causing HW to exit PSR, masking it to allow more power savings. Writes to pipe related registers will still cause HW to exit PSR. This is already masked for PSR2. It also do not break the Display WA #0884, writes to CURSURFLIVE are still causing hardware to exit PSR. This was tested in CNL machine by triggering a write to CURSURFLIVE when a debugfs was read by user. Bspec: 7721 and 8042 v4: Checked that it do not breaks WA #0884 and added this information to the commit message. Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20180425212334.21109-1-jose.souza@intel.com --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0d548292dd09..e35a3b94fa69 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -667,7 +667,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, I915_WRITE(EDP_PSR_DEBUG, EDP_PSR_DEBUG_MASK_MEMUP | EDP_PSR_DEBUG_MASK_HPD | - EDP_PSR_DEBUG_MASK_LPSP); + EDP_PSR_DEBUG_MASK_LPSP | + EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); } } -- 2.30.2