From 74eb26e4098d0a1f5c6ef49c1355e99d80027f36 Mon Sep 17 00:00:00 2001 From: Juan Castillo Date: Wed, 13 Jan 2016 15:01:09 +0000 Subject: [PATCH] ARM platforms: rationalise memory attributes of shared memory The shared memory region on ARM platforms contains the mailboxes and, on Juno, the payload area for communication with the SCP. This shared memory may be configured as normal memory or device memory at build time by setting the platform flag 'PLAT_ARM_SHARED_RAM_CACHED' (on Juno, the value of this flag is defined by 'MHU_PAYLOAD_CACHED'). When set as normal memory, the platform port performs the corresponding cache maintenance operations. From a functional point of view, this is the equivalent of setting the shared memory as device memory, so there is no need to maintain both options. This patch removes the option to specify the shared memory as normal memory on ARM platforms. Shared memory is always treated as device memory. Cache maintenance operations are no longer needed and have been replaced by data memory barriers to guarantee that payload and MHU are accessed in the right order. Change-Id: I7f958621d6a536dd4f0fa8768385eedc4295e79f --- include/lib/aarch64/arch_helpers.h | 2 ++ include/plat/arm/common/arm_def.h | 6 +----- include/plat/arm/css/common/css_def.h | 4 ---- plat/arm/board/fvp/include/platform_def.h | 2 -- plat/arm/common/arm_pm.c | 5 ----- plat/arm/css/common/css_scp_bootloader.c | 15 ++++++++------- plat/arm/css/common/css_scpi.c | 15 ++++++++------- 7 files changed, 19 insertions(+), 30 deletions(-) diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 067b8302..d1ad31dc 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -194,6 +194,8 @@ DEFINE_SYSOP_FUNC(wfe) DEFINE_SYSOP_FUNC(sev) DEFINE_SYSOP_TYPE_FUNC(dsb, sy) DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, st) +DEFINE_SYSOP_TYPE_FUNC(dmb, ld) DEFINE_SYSOP_TYPE_FUNC(dsb, ish) DEFINE_SYSOP_TYPE_FUNC(dmb, ish) DEFINE_SYSOP_FUNC(isb) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index b2db6160..60491711 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -151,14 +151,10 @@ #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ ARM_IRQ_SEC_SGI_6 -#define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ - MT_MEMORY : MT_DEVICE) \ - | MT_RW | MT_SECURE) - #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ - ARM_SHARED_RAM_ATTR) + MT_DEVICE | MT_RW | MT_SECURE) #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ ARM_NS_DRAM1_BASE, \ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index c900278b..7a5d1939 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -37,8 +37,6 @@ /************************************************************************* * Definitions common to all ARM Compute SubSystems (CSS) *************************************************************************/ -#define MHU_PAYLOAD_CACHED 0 - #define NSROM_BASE 0x1f000000 #define NSROM_SIZE 0x00001000 @@ -118,8 +116,6 @@ #define SCP_BL2U_BASE BL31_BASE -#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED - /* Load address of Non-Secure Image for CSS platform ports */ #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 0d671dc0..9b853423 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -64,8 +64,6 @@ #define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) -#define PLAT_ARM_SHARED_RAM_CACHED 1 - /* * Load address of BL33 for this platform port */ diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 2ddc5833..1e756a9e 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -192,11 +192,6 @@ void arm_program_trusted_mailbox(uintptr_t address) assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); - - /* Flush data cache if the mail box shared RAM is cached */ -#if PLAT_ARM_SHARED_RAM_CACHED - flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox)); -#endif } /******************************************************************************* diff --git a/plat/arm/css/common/css_scp_bootloader.c b/plat/arm/css/common/css_scp_bootloader.c index c01f42fb..43674593 100644 --- a/plat/arm/css/common/css_scp_bootloader.c +++ b/plat/arm/css/common/css_scp_bootloader.c @@ -77,10 +77,10 @@ static void scp_boot_message_start(void) static void scp_boot_message_send(size_t payload_size) { - /* Make sure payload can be seen by SCP */ - if (MHU_PAYLOAD_CACHED) - flush_dcache_range(BOM_SHARED_MEM, - sizeof(bom_cmd_t) + payload_size); + /* Ensure that any write to the BOM payload area is seen by SCP before + * we write to the MHU register. If these 2 writes were reordered by + * the CPU then SCP would read stale payload data */ + dmbst(); /* Send command to SCP */ mhu_secure_message_send(BOM_MHU_SLOT_ID); @@ -99,9 +99,10 @@ static uint32_t scp_boot_message_wait(size_t size) panic(); } - /* Make sure we see the reply from the SCP and not any stale data */ - if (MHU_PAYLOAD_CACHED) - inv_dcache_range(BOM_SHARED_MEM, size); + /* Ensure that any read to the BOM payload area is done after reading + * the MHU register. If these 2 reads were reordered then the CPU would + * read invalid payload data */ + dmbld(); return *(uint32_t *) BOM_SHARED_MEM; } diff --git a/plat/arm/css/common/css_scpi.c b/plat/arm/css/common/css_scpi.c index 0a4eafe0..829a1742 100644 --- a/plat/arm/css/common/css_scpi.c +++ b/plat/arm/css/common/css_scpi.c @@ -55,10 +55,10 @@ static void scpi_secure_message_start(void) static void scpi_secure_message_send(size_t payload_size) { - /* Make sure payload can be seen by SCP */ - if (MHU_PAYLOAD_CACHED) - flush_dcache_range(SCPI_SHARED_MEM_AP_TO_SCP, - sizeof(scpi_cmd_t) + payload_size); + /* Ensure that any write to the SCPI payload area is seen by SCP before + * we write to the MHU register. If these 2 writes were reordered by + * the CPU then SCP would read stale payload data */ + dmbst(); mhu_secure_message_send(SCPI_MHU_SLOT_ID); } @@ -78,9 +78,10 @@ static void scpi_secure_message_receive(scpi_cmd_t *cmd) panic(); } - /* Make sure we don't read stale data */ - if (MHU_PAYLOAD_CACHED) - inv_dcache_range(SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); + /* Ensure that any read to the SCPI payload area is done after reading + * the MHU register. If these 2 reads were reordered then the CPU would + * read invalid payload data */ + dmbld(); memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); } -- 2.30.2