From 7479a33f456ddf70a795ec0bdf2ab2c00ee507c7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 14 Jun 2019 01:35:59 +0200 Subject: [PATCH] rcar_gen3: drivers: qos: H3: Drop MD pin check The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: Marek Vasut Change-Id: I4d8926eb3c44c61ec777c05c581ce8247f13daa6 --- .../renesas/rcar/qos/H3/qos_init_h3_v11.c | 24 ++----------------- .../renesas/rcar/qos/H3/qos_init_h3_v20.c | 24 ++----------------- .../renesas/rcar/qos/H3/qos_init_h3_v30.c | 24 ++----------------- .../renesas/rcar/qos/H3/qos_init_h3n_v30.c | 24 ++----------------- 4 files changed, 8 insertions(+), 88 deletions(-) diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c index db337b67..63129483 100644 --- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c +++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c @@ -20,8 +20,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* BUFCAM settings */ /* DBSC_DBCAM0CNF0 not set */ io_write_32(DBSC_DBCAM0CNF1, 0x00044218); @@ -32,26 +30,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001); io_write_32(DBSC_DBSCHRW0, 0x22421111); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x0000F000); diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c index 9c64e513..c54aca0b 100644 --- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c +++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c @@ -57,8 +57,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* Register write enable */ io_write_32(DBSC_DBSYSCNT0, 0x00001234U); @@ -70,26 +68,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHRW0, 0x22421111U); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c index 730ef0da..44b58cbb 100644 --- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c +++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c @@ -57,8 +57,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* Register write enable */ io_write_32(DBSC_DBSYSCNT0, 0x00001234U); @@ -70,26 +68,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHRW0, 0x22421111U); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c index f03f0c0c..80870fbf 100644 --- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c +++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c @@ -57,8 +57,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* Register write enable */ io_write_32(DBSC_DBSYSCNT0, 0x00001234U); @@ -70,26 +68,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001U); io_write_32(DBSC_DBSCHRW0, 0x22421111U); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123U); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123U); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00U); -- 2.30.2