From 70855bb5c608e4ac9dde5b669c3cf56914b713a2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 23 Jul 2013 09:25:56 +0200 Subject: [PATCH] clk: sunxi: Allow to specify the divider width from the dividers data MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by: Maxime Ripard Reviewed-by: Emilio López --- drivers/clk/sunxi/clk-sunxi.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 5fac1aa87bdb..2cafda88b7f6 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -279,26 +279,28 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, * sunxi_divider_clk_setup() - Setup function for simple divider clocks */ -#define SUNXI_DIVISOR_WIDTH 2 - struct div_data { - u8 shift; - u8 pow; + u8 shift; + u8 pow; + u8 width; }; static const __initconst struct div_data sun4i_axi_data = { - .shift = 0, - .pow = 0, + .shift = 0, + .pow = 0, + .width = 2, }; static const __initconst struct div_data sun4i_ahb_data = { - .shift = 4, - .pow = 1, + .shift = 4, + .pow = 1, + .width = 2, }; static const __initconst struct div_data sun4i_apb0_data = { - .shift = 8, - .pow = 1, + .shift = 8, + .pow = 1, + .width = 2, }; static void __init sunxi_divider_clk_setup(struct device_node *node, @@ -314,7 +316,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, clk_parent = of_clk_get_parent_name(node, 0); clk = clk_register_divider(NULL, clk_name, clk_parent, 0, - reg, data->shift, SUNXI_DIVISOR_WIDTH, + reg, data->shift, data->width, data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, &clk_lock); if (clk) { -- 2.30.2