From 6a0f7c0077983f1f56b4214f05a22fb93beb9593 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 4 Sep 2018 17:49:32 +0530 Subject: [PATCH] zynqmp: pm_service: Ignore enable/disable of PLL type clocks PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable them based on their user count. So, it should not be handled from ATF. Put PLL type clock into bypass and reset mode only while changing PLL rate (FBDIV). Signed-off-by: Tejas Patel Acked-by: Will Wong Signed-off-by: Siva Durga Prasad Paladugu --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 25 +++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index dab9edab..cecd5587 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -2627,10 +2627,11 @@ enum pm_ret_status pm_api_clock_enable(unsigned int clock_id) if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) return PM_RET_ERROR_NOTSUPPORTED; - if (ISPLL(clock_id)) - ret = pm_api_pll_bypass_and_reset(clock_id, - CLK_PLL_RESET_PULSE); - else + /* + * PLL type clock should not enable explicitly. + * It is done by FSBL on boot-up and by PMUFW whenever required. + */ + if (!ISPLL(clock_id)) ret = pm_api_clk_enable_disable(clock_id, 1); return ret; @@ -2656,10 +2657,11 @@ enum pm_ret_status pm_api_clock_disable(unsigned int clock_id) if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT) return PM_RET_ERROR_NOTSUPPORTED; - if (ISPLL(clock_id)) - ret = pm_api_pll_bypass_and_reset(clock_id, - CLK_PLL_RESET_ASSERT); - else + /* + * PLL type clock should not be disabled explicitly. + * It is done by PMUFW if required. + */ + if (!ISPLL(clock_id)) ret = pm_api_clk_enable_disable(clock_id, 0); return ret; @@ -2807,8 +2809,13 @@ static enum pm_ret_status pm_api_pll_set_divider(unsigned int clock_id, unsigned int divider) { unsigned int reg = clocks[clock_id].control_reg; + enum pm_ret_status ret; - return pm_mmio_write(reg, PLL_FBDIV_MASK, divider << PLL_FBDIV_SHIFT); + pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_ASSERT); + ret = pm_mmio_write(reg, PLL_FBDIV_MASK, divider << PLL_FBDIV_SHIFT); + pm_api_pll_bypass_and_reset(clock_id, CLK_PLL_RESET_RELEASE); + + return ret; } /** -- 2.30.2