From 6286c19540c65b89f4ad241d74b4cd21481ae35f Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 31 Dec 2007 14:18:42 +0000 Subject: [PATCH] split up olpc patches SVN-Revision: 10069 --- target/linux/olpc/patches/100-olpc.patch | 20392 +++------------- .../linux/olpc/patches/110-olpc_sound.patch | 414 + 2 files changed, 4254 insertions(+), 16552 deletions(-) create mode 100644 target/linux/olpc/patches/110-olpc_sound.patch diff --git a/target/linux/olpc/patches/100-olpc.patch b/target/linux/olpc/patches/100-olpc.patch index a1ce5687e307..abbf61f808e8 100644 --- a/target/linux/olpc/patches/100-olpc.patch +++ b/target/linux/olpc/patches/100-olpc.patch @@ -1,21 +1,3 @@ -diff --git a/MAINTAINERS b/MAINTAINERS -index 9c54a5e..f88d691 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3026,6 +3026,13 @@ L: linux-wireless@vger.kernel.org - W: http://prism54.org - S: Maintained - -+ADM8211 WIRELESS DRIVER -+P: Michael Wu -+M: flamingice@sourmilk.net -+L: netdev@vger.kernel.org -+W: http://aluminum.sourmilk.net/adm8211/netdev/ -+S: Maintained -+ - PROMISE DC4030 CACHING DISK CONTROLLER DRIVER - P: Peter Denison - M: promise@pnd-pc.demon.co.uk diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig index 97b64d7..92ceab7 100644 --- a/arch/i386/Kconfig @@ -111,5508 +93,6 @@ index 97b64d7..92ceab7 100644 source "drivers/pcmcia/Kconfig" source "drivers/pci/hotplug/Kconfig" -diff --git a/arch/i386/boot/setup.S b/arch/i386/boot/setup.S -new file mode 100644 -index 0000000..4cf6e23 ---- /dev/null -+++ b/arch/i386/boot/setup.S -@@ -0,0 +1,1080 @@ -+/* -+ * setup.S Copyright (C) 1991, 1992 Linus Torvalds -+ * -+ * setup.s is responsible for getting the system data from the BIOS, -+ * and putting them into the appropriate places in system memory. -+ * both setup.s and system has been loaded by the bootblock. -+ * -+ * This code asks the bios for memory/disk/other parameters, and -+ * puts them in a "safe" place: 0x90000-0x901FF, ie where the -+ * boot-block used to be. It is then up to the protected mode -+ * system to read them from there before the area is overwritten -+ * for buffer-blocks. -+ * -+ * Move PS/2 aux init code to psaux.c -+ * (troyer@saifr00.cfsat.Honeywell.COM) 03Oct92 -+ * -+ * some changes and additional features by Christoph Niemann, -+ * March 1993/June 1994 (Christoph.Niemann@linux.org) -+ * -+ * add APM BIOS checking by Stephen Rothwell, May 1994 -+ * (sfr@canb.auug.org.au) -+ * -+ * High load stuff, initrd support and position independency -+ * by Hans Lermen & Werner Almesberger, February 1996 -+ * , -+ * -+ * Video handling moved to video.S by Martin Mares, March 1996 -+ * -+ * -+ * Extended memory detection scheme retwiddled by orc@pell.chi.il.us (david -+ * parsons) to avoid loadlin confusion, July 1997 -+ * -+ * Transcribed from Intel (as86) -> AT&T (gas) by Chris Noe, May 1999. -+ * -+ * -+ * Fix to work around buggy BIOSes which don't use carry bit correctly -+ * and/or report extended memory in CX/DX for e801h memory size detection -+ * call. As a result the kernel got wrong figures. The int15/e801h docs -+ * from Ralf Brown interrupt list seem to indicate AX/BX should be used -+ * anyway. So to avoid breaking many machines (presumably there was a reason -+ * to orginally use CX/DX instead of AX/BX), we do a kludge to see -+ * if CX/DX have been changed in the e801 call and if so use AX/BX . -+ * Michael Miller, April 2001 -+ * -+ * New A20 code ported from SYSLINUX by H. Peter Anvin. AMD Elan bugfixes -+ * by Robert Schwebel, December 2001 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Signature words to ensure LILO loaded us right */ -+#define SIG1 0xAA55 -+#define SIG2 0x5A5A -+ -+INITSEG = DEF_INITSEG # 0x9000, we move boot here, out of the way -+SYSSEG = DEF_SYSSEG # 0x1000, system loaded at 0x10000 (65536). -+SETUPSEG = DEF_SETUPSEG # 0x9020, this is the current segment -+ # ... and the former contents of CS -+ -+DELTA_INITSEG = SETUPSEG - INITSEG # 0x0020 -+ -+.code16 -+.globl begtext, begdata, begbss, endtext, enddata, endbss -+ -+.text -+begtext: -+.data -+begdata: -+.bss -+begbss: -+.text -+ -+start: -+ jmp trampoline -+ -+# This is the setup header, and it must start at %cs:2 (old 0x9020:2) -+ -+ .ascii "HdrS" # header signature -+ .word 0x0206 # header version number (>= 0x0105) -+ # or else old loadlin-1.5 will fail) -+realmode_swtch: .word 0, 0 # default_switch, SETUPSEG -+start_sys_seg: .word SYSSEG -+ .word kernel_version # pointing to kernel version string -+ # above section of header is compatible -+ # with loadlin-1.5 (header v1.5). Don't -+ # change it. -+ -+type_of_loader: .byte 0 # = 0, old one (LILO, Loadlin, -+ # Bootlin, SYSLX, bootsect...) -+ # See Documentation/i386/boot.txt for -+ # assigned ids -+ -+# flags, unused bits must be zero (RFU) bit within loadflags -+loadflags: -+LOADED_HIGH = 1 # If set, the kernel is loaded high -+CAN_USE_HEAP = 0x80 # If set, the loader also has set -+ # heap_end_ptr to tell how much -+ # space behind setup.S can be used for -+ # heap purposes. -+ # Only the loader knows what is free -+#ifndef __BIG_KERNEL__ -+ .byte 0 -+#else -+ .byte LOADED_HIGH -+#endif -+ -+setup_move_size: .word 0x8000 # size to move, when setup is not -+ # loaded at 0x90000. We will move setup -+ # to 0x90000 then just before jumping -+ # into the kernel. However, only the -+ # loader knows how much data behind -+ # us also needs to be loaded. -+ -+code32_start: # here loaders can put a different -+ # start address for 32-bit code. -+#ifndef __BIG_KERNEL__ -+ .long 0x1000 # 0x1000 = default for zImage -+#else -+ .long 0x100000 # 0x100000 = default for big kernel -+#endif -+ -+ramdisk_image: .long 0 # address of loaded ramdisk image -+ # Here the loader puts the 32-bit -+ # address where it loaded the image. -+ # This only will be read by the kernel. -+ -+ramdisk_size: .long 0 # its size in bytes -+ -+bootsect_kludge: -+ .long 0 # obsolete -+ -+heap_end_ptr: .word modelist+1024 # (Header version 0x0201 or later) -+ # space from here (exclusive) down to -+ # end of setup code can be used by setup -+ # for local heap purposes. -+ -+pad1: .word 0 -+cmd_line_ptr: .long 0 # (Header version 0x0202 or later) -+ # If nonzero, a 32-bit pointer -+ # to the kernel command line. -+ # The command line should be -+ # located between the start of -+ # setup and the end of low -+ # memory (0xa0000), or it may -+ # get overwritten before it -+ # gets read. If this field is -+ # used, there is no longer -+ # anything magical about the -+ # 0x90000 segment; the setup -+ # can be located anywhere in -+ # low memory 0x10000 or higher. -+ -+ramdisk_max: .long (-__PAGE_OFFSET-(512 << 20)-1) & 0x7fffffff -+ # (Header version 0x0203 or later) -+ # The highest safe address for -+ # the contents of an initrd -+ -+kernel_alignment: .long CONFIG_PHYSICAL_ALIGN #physical addr alignment -+ #required for protected mode -+ #kernel -+#ifdef CONFIG_RELOCATABLE -+relocatable_kernel: .byte 1 -+#else -+relocatable_kernel: .byte 0 -+#endif -+pad2: .byte 0 -+pad3: .word 0 -+ -+cmdline_size: .long COMMAND_LINE_SIZE-1 #length of the command line, -+ #added with boot protocol -+ #version 2.06 -+ -+trampoline: call start_of_setup -+ .align 16 -+ # The offset at this point is 0x240 -+ .space (0xeff-0x240+1) # E820 & EDD space (ending at 0xeff) -+# End of setup header ##################################################### -+ -+start_of_setup: -+# Bootlin depends on this being done early -+ movw $0x01500, %ax -+ movb $0x81, %dl -+ int $0x13 -+ -+#ifdef SAFE_RESET_DISK_CONTROLLER -+# Reset the disk controller. -+ movw $0x0000, %ax -+ movb $0x80, %dl -+ int $0x13 -+#endif -+ -+# Set %ds = %cs, we know that SETUPSEG = %cs at this point -+ movw %cs, %ax # aka SETUPSEG -+ movw %ax, %ds -+# Check signature at end of setup -+ cmpw $SIG1, setup_sig1 -+ jne bad_sig -+ -+ cmpw $SIG2, setup_sig2 -+ jne bad_sig -+ -+ jmp good_sig1 -+ -+# Routine to print asciiz string at ds:si -+prtstr: -+ lodsb -+ andb %al, %al -+ jz fin -+ -+ call prtchr -+ jmp prtstr -+ -+fin: ret -+ -+# Space printing -+prtsp2: call prtspc # Print double space -+prtspc: movb $0x20, %al # Print single space (note: fall-thru) -+ -+# Part of above routine, this one just prints ascii al -+prtchr: pushw %ax -+ pushw %cx -+ movw $7,%bx -+ movw $0x01, %cx -+ movb $0x0e, %ah -+ int $0x10 -+ popw %cx -+ popw %ax -+ ret -+ -+beep: movb $0x07, %al -+ jmp prtchr -+ -+no_sig_mess: .string "No setup signature found ..." -+ -+good_sig1: -+ jmp good_sig -+ -+# We now have to find the rest of the setup code/data -+bad_sig: -+ movw %cs, %ax # SETUPSEG -+ subw $DELTA_INITSEG, %ax # INITSEG -+ movw %ax, %ds -+ xorb %bh, %bh -+ movb (497), %bl # get setup sect from bootsect -+ subw $4, %bx # LILO loads 4 sectors of setup -+ shlw $8, %bx # convert to words (1sect=2^8 words) -+ movw %bx, %cx -+ shrw $3, %bx # convert to segment -+ addw $SYSSEG, %bx -+ movw %bx, %cs:start_sys_seg -+# Move rest of setup code/data to here -+ movw $2048, %di # four sectors loaded by LILO -+ subw %si, %si -+ pushw %cs -+ popw %es -+ movw $SYSSEG, %ax -+ movw %ax, %ds -+ rep -+ movsw -+ movw %cs, %ax # aka SETUPSEG -+ movw %ax, %ds -+ cmpw $SIG1, setup_sig1 -+ jne no_sig -+ -+ cmpw $SIG2, setup_sig2 -+ jne no_sig -+ -+ jmp good_sig -+ -+no_sig: -+ lea no_sig_mess, %si -+ call prtstr -+ -+no_sig_loop: -+ hlt -+ jmp no_sig_loop -+ -+good_sig: -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ax, %ds -+# Check if an old loader tries to load a big-kernel -+ testb $LOADED_HIGH, %cs:loadflags # Do we have a big kernel? -+ jz loader_ok # No, no danger for old loaders. -+ -+ cmpb $0, %cs:type_of_loader # Do we have a loader that -+ # can deal with us? -+ jnz loader_ok # Yes, continue. -+ -+ pushw %cs # No, we have an old loader, -+ popw %ds # die. -+ lea loader_panic_mess, %si -+ call prtstr -+ -+ jmp no_sig_loop -+ -+loader_panic_mess: .string "Wrong loader, giving up..." -+ -+# check minimum cpuid -+# we do this here because it is the last place we can actually -+# show a user visible error message. Later the video modus -+# might be already messed up. -+loader_ok: -+ call verify_cpu -+ testl %eax,%eax -+ jz cpu_ok -+ movw %cs,%ax # aka SETUPSEG -+ movw %ax,%ds -+ lea cpu_panic_mess,%si -+ call prtstr -+1: jmp 1b -+ -+cpu_panic_mess: -+ .asciz "PANIC: CPU too old for this kernel." -+ -+#include "../kernel/verify_cpu.S" -+ -+cpu_ok: -+# Get memory size (extended mem, kB) -+ -+ xorl %eax, %eax -+ movl %eax, (0x1e0) -+#ifndef STANDARD_MEMORY_BIOS_CALL -+ movb %al, (E820NR) -+# Try three different memory detection schemes. First, try -+# e820h, which lets us assemble a memory map, then try e801h, -+# which returns a 32-bit memory size, and finally 88h, which -+# returns 0-64m -+ -+# method E820H: -+# the memory map from hell. e820h returns memory classified into -+# a whole bunch of different types, and allows memory holes and -+# everything. We scan through this memory map and build a list -+# of the first 32 memory areas, which we return at [E820MAP]. -+# This is documented at http://www.acpi.info/, in the ACPI 2.0 specification. -+ -+#define SMAP 0x534d4150 -+ -+meme820: -+ xorl %ebx, %ebx # continuation counter -+ movw $E820MAP, %di # point into the whitelist -+ # so we can have the bios -+ # directly write into it. -+ -+jmpe820: -+ movl $0x0000e820, %eax # e820, upper word zeroed -+ movl $SMAP, %edx # ascii 'SMAP' -+ movl $20, %ecx # size of the e820rec -+ pushw %ds # data record. -+ popw %es -+ int $0x15 # make the call -+ jc bail820 # fall to e801 if it fails -+ -+ cmpl $SMAP, %eax # check the return is `SMAP' -+ jne bail820 # fall to e801 if it fails -+ -+# cmpl $1, 16(%di) # is this usable memory? -+# jne again820 -+ -+ # If this is usable memory, we save it by simply advancing %di by -+ # sizeof(e820rec). -+ # -+good820: -+ movb (E820NR), %al # up to 128 entries -+ cmpb $E820MAX, %al -+ jae bail820 -+ -+ incb (E820NR) -+ movw %di, %ax -+ addw $20, %ax -+ movw %ax, %di -+again820: -+ cmpl $0, %ebx # check to see if -+ jne jmpe820 # %ebx is set to EOF -+bail820: -+ -+ -+# method E801H: -+# memory size is in 1k chunksizes, to avoid confusing loadlin. -+# we store the 0xe801 memory size in a completely different place, -+# because it will most likely be longer than 16 bits. -+# (use 1e0 because that's what Larry Augustine uses in his -+# alternative new memory detection scheme, and it's sensible -+# to write everything into the same place.) -+ -+meme801: -+ stc # fix to work around buggy -+ xorw %cx,%cx # BIOSes which don't clear/set -+ xorw %dx,%dx # carry on pass/error of -+ # e801h memory size call -+ # or merely pass cx,dx though -+ # without changing them. -+ movw $0xe801, %ax -+ int $0x15 -+ jc mem88 -+ -+ cmpw $0x0, %cx # Kludge to handle BIOSes -+ jne e801usecxdx # which report their extended -+ cmpw $0x0, %dx # memory in AX/BX rather than -+ jne e801usecxdx # CX/DX. The spec I have read -+ movw %ax, %cx # seems to indicate AX/BX -+ movw %bx, %dx # are more reasonable anyway... -+ -+e801usecxdx: -+ andl $0xffff, %edx # clear sign extend -+ shll $6, %edx # and go from 64k to 1k chunks -+ movl %edx, (0x1e0) # store extended memory size -+ andl $0xffff, %ecx # clear sign extend -+ addl %ecx, (0x1e0) # and add lower memory into -+ # total size. -+ -+# Ye Olde Traditional Methode. Returns the memory size (up to 16mb or -+# 64mb, depending on the bios) in ax. -+mem88: -+ -+#endif -+ movb $0x88, %ah -+ int $0x15 -+ movw %ax, (2) -+ -+# Set the keyboard repeat rate to the max -+ movw $0x0305, %ax -+ xorw %bx, %bx -+ int $0x16 -+ -+#ifndef CONFIG_VGA_NOPROBE -+ -+# Check for video adapter and its parameters and allow the -+# user to browse video modes. -+ call video # NOTE: we need %ds pointing -+ # to bootsector -+#endif -+ -+# Get hd0 data... -+ xorw %ax, %ax -+ movw %ax, %ds -+ ldsw (4 * 0x41), %si -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ pushw %ax -+ movw %ax, %es -+ movw $0x0080, %di -+ movw $0x10, %cx -+ pushw %cx -+ cld -+ rep -+ movsb -+# Get hd1 data... -+ xorw %ax, %ax -+ movw %ax, %ds -+ ldsw (4 * 0x46), %si -+ popw %cx -+ popw %es -+ movw $0x0090, %di -+ rep -+ movsb -+# Check that there IS a hd1 :-) -+ movw $0x01500, %ax -+ movb $0x81, %dl -+ int $0x13 -+ jc no_disk1 -+ -+ cmpb $3, %ah -+ je is_disk1 -+ -+no_disk1: -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ax, %es -+ movw $0x0090, %di -+ movw $0x10, %cx -+ xorw %ax, %ax -+ cld -+ rep -+ stosb -+is_disk1: -+# check for Micro Channel (MCA) bus -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ax, %ds -+ xorw %ax, %ax -+ movw %ax, (0xa0) # set table length to 0 -+ movb $0xc0, %ah -+ stc -+ int $0x15 # moves feature table to es:bx -+ jc no_mca -+ -+ pushw %ds -+ movw %es, %ax -+ movw %ax, %ds -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ax, %es -+ movw %bx, %si -+ movw $0xa0, %di -+ movw (%si), %cx -+ addw $2, %cx # table length is a short -+ cmpw $0x10, %cx -+ jc sysdesc_ok -+ -+ movw $0x10, %cx # we keep only first 16 bytes -+sysdesc_ok: -+ rep -+ movsb -+ popw %ds -+no_mca: -+#ifdef CONFIG_X86_VOYAGER -+ movb $0xff, 0x40 # flag on config found -+ movb $0xc0, %al -+ mov $0xff, %ah -+ int $0x15 # put voyager config info at es:di -+ jc no_voyager -+ movw $0x40, %si # place voyager info in apm table -+ cld -+ movw $7, %cx -+voyager_rep: -+ movb %es:(%di), %al -+ movb %al,(%si) -+ incw %di -+ incw %si -+ decw %cx -+ jnz voyager_rep -+no_voyager: -+#endif -+# Check for PS/2 pointing device -+ movw %cs, %ax # aka SETUPSEG -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ax, %ds -+ movb $0, (0x1ff) # default is no pointing device -+ int $0x11 # int 0x11: equipment list -+ testb $0x04, %al # check if mouse installed -+ jz no_psmouse -+ -+ movb $0xAA, (0x1ff) # device present -+no_psmouse: -+ -+#if defined(CONFIG_X86_SPEEDSTEP_SMI) || defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE) -+ movl $0x0000E980, %eax # IST Support -+ movl $0x47534943, %edx # Request value -+ int $0x15 -+ -+ movl %eax, (96) -+ movl %ebx, (100) -+ movl %ecx, (104) -+ movl %edx, (108) -+#endif -+ -+#if defined(CONFIG_APM) || defined(CONFIG_APM_MODULE) -+# Then check for an APM BIOS... -+ # %ds points to the bootsector -+ movw $0, 0x40 # version = 0 means no APM BIOS -+ movw $0x05300, %ax # APM BIOS installation check -+ xorw %bx, %bx -+ int $0x15 -+ jc done_apm_bios # Nope, no APM BIOS -+ -+ cmpw $0x0504d, %bx # Check for "PM" signature -+ jne done_apm_bios # No signature, no APM BIOS -+ -+ andw $0x02, %cx # Is 32 bit supported? -+ je done_apm_bios # No 32-bit, no (good) APM BIOS -+ -+ movw $0x05304, %ax # Disconnect first just in case -+ xorw %bx, %bx -+ int $0x15 # ignore return code -+ movw $0x05303, %ax # 32 bit connect -+ xorl %ebx, %ebx -+ xorw %cx, %cx # paranoia :-) -+ xorw %dx, %dx # ... -+ xorl %esi, %esi # ... -+ xorw %di, %di # ... -+ int $0x15 -+ jc no_32_apm_bios # Ack, error. -+ -+ movw %ax, (66) # BIOS code segment -+ movl %ebx, (68) # BIOS entry point offset -+ movw %cx, (72) # BIOS 16 bit code segment -+ movw %dx, (74) # BIOS data segment -+ movl %esi, (78) # BIOS code segment lengths -+ movw %di, (82) # BIOS data segment length -+# Redo the installation check as the 32 bit connect -+# modifies the flags returned on some BIOSs -+ movw $0x05300, %ax # APM BIOS installation check -+ xorw %bx, %bx -+ xorw %cx, %cx # paranoia -+ int $0x15 -+ jc apm_disconnect # error -> shouldn't happen -+ -+ cmpw $0x0504d, %bx # check for "PM" signature -+ jne apm_disconnect # no sig -> shouldn't happen -+ -+ movw %ax, (64) # record the APM BIOS version -+ movw %cx, (76) # and flags -+ jmp done_apm_bios -+ -+apm_disconnect: # Tidy up -+ movw $0x05304, %ax # Disconnect -+ xorw %bx, %bx -+ int $0x15 # ignore return code -+ -+ jmp done_apm_bios -+ -+no_32_apm_bios: -+ andw $0xfffd, (76) # remove 32 bit support bit -+done_apm_bios: -+#endif -+ -+#include "edd.S" -+ -+# Now we want to move to protected mode ... -+ cmpw $0, %cs:realmode_swtch -+ jz rmodeswtch_normal -+ -+ lcall *%cs:realmode_swtch -+ -+ jmp rmodeswtch_end -+ -+rmodeswtch_normal: -+ pushw %cs -+ call default_switch -+ -+rmodeswtch_end: -+# Now we move the system to its rightful place ... but we check if we have a -+# big-kernel. In that case we *must* not move it ... -+ testb $LOADED_HIGH, %cs:loadflags -+ jz do_move0 # .. then we have a normal low -+ # loaded zImage -+ # .. or else we have a high -+ # loaded bzImage -+ jmp end_move # ... and we skip moving -+ -+do_move0: -+ movw $0x100, %ax # start of destination segment -+ movw %cs, %bp # aka SETUPSEG -+ subw $DELTA_INITSEG, %bp # aka INITSEG -+ movw %cs:start_sys_seg, %bx # start of source segment -+ cld -+do_move: -+ movw %ax, %es # destination segment -+ incb %ah # instead of add ax,#0x100 -+ movw %bx, %ds # source segment -+ addw $0x100, %bx -+ subw %di, %di -+ subw %si, %si -+ movw $0x800, %cx -+ rep -+ movsw -+ cmpw %bp, %bx # assume start_sys_seg > 0x200, -+ # so we will perhaps read one -+ # page more than needed, but -+ # never overwrite INITSEG -+ # because destination is a -+ # minimum one page below source -+ jb do_move -+ -+end_move: -+# then we load the segment descriptors -+ movw %cs, %ax # aka SETUPSEG -+ movw %ax, %ds -+ -+# Check whether we need to be downward compatible with version <=201 -+ cmpl $0, cmd_line_ptr -+ jne end_move_self # loader uses version >=202 features -+ cmpb $0x20, type_of_loader -+ je end_move_self # bootsect loader, we know of it -+ -+# Boot loader doesnt support boot protocol version 2.02. -+# If we have our code not at 0x90000, we need to move it there now. -+# We also then need to move the params behind it (commandline) -+# Because we would overwrite the code on the current IP, we move -+# it in two steps, jumping high after the first one. -+ movw %cs, %ax -+ cmpw $SETUPSEG, %ax -+ je end_move_self -+ -+ cli # make sure we really have -+ # interrupts disabled ! -+ # because after this the stack -+ # should not be used -+ subw $DELTA_INITSEG, %ax # aka INITSEG -+ movw %ss, %dx -+ cmpw %ax, %dx -+ jb move_self_1 -+ -+ addw $INITSEG, %dx -+ subw %ax, %dx # this will go into %ss after -+ # the move -+move_self_1: -+ movw %ax, %ds -+ movw $INITSEG, %ax # real INITSEG -+ movw %ax, %es -+ movw %cs:setup_move_size, %cx -+ std # we have to move up, so we use -+ # direction down because the -+ # areas may overlap -+ movw %cx, %di -+ decw %di -+ movw %di, %si -+ subw $move_self_here+0x200, %cx -+ rep -+ movsb -+ ljmp $SETUPSEG, $move_self_here -+ -+move_self_here: -+ movw $move_self_here+0x200, %cx -+ rep -+ movsb -+ movw $SETUPSEG, %ax -+ movw %ax, %ds -+ movw %dx, %ss -+end_move_self: # now we are at the right place -+ -+# -+# Enable A20. This is at the very best an annoying procedure. -+# A20 code ported from SYSLINUX 1.52-1.63 by H. Peter Anvin. -+# AMD Elan bug fix by Robert Schwebel. -+# -+ -+#if defined(CONFIG_X86_ELAN) -+ movb $0x02, %al # alternate A20 gate -+ outb %al, $0x92 # this works on SC410/SC520 -+a20_elan_wait: -+ call a20_test -+ jz a20_elan_wait -+ jmp a20_done -+#endif -+ -+ -+A20_TEST_LOOPS = 32 # Iterations per wait -+A20_ENABLE_LOOPS = 255 # Total loops to try -+ -+ -+#ifndef CONFIG_X86_VOYAGER -+a20_try_loop: -+ -+ # First, see if we are on a system with no A20 gate. -+a20_none: -+ call a20_test -+ jnz a20_done -+ -+ # Next, try the BIOS (INT 0x15, AX=0x2401) -+a20_bios: -+ movw $0x2401, %ax -+ pushfl # Be paranoid about flags -+ int $0x15 -+ popfl -+ -+ call a20_test -+ jnz a20_done -+ -+ # Try enabling A20 through the keyboard controller -+#endif /* CONFIG_X86_VOYAGER */ -+a20_kbc: -+ call empty_8042 -+ -+#ifndef CONFIG_X86_VOYAGER -+ call a20_test # Just in case the BIOS worked -+ jnz a20_done # but had a delayed reaction. -+#endif -+ -+ movb $0xD1, %al # command write -+ outb %al, $0x64 -+ call empty_8042 -+ -+ movb $0xDF, %al # A20 on -+ outb %al, $0x60 -+ call empty_8042 -+ -+#ifndef CONFIG_X86_VOYAGER -+ # Wait until a20 really *is* enabled; it can take a fair amount of -+ # time on certain systems; Toshiba Tecras are known to have this -+ # problem. -+a20_kbc_wait: -+ xorw %cx, %cx -+a20_kbc_wait_loop: -+ call a20_test -+ jnz a20_done -+ loop a20_kbc_wait_loop -+ -+ # Final attempt: use "configuration port A" -+a20_fast: -+ inb $0x92, %al # Configuration Port A -+ orb $0x02, %al # "fast A20" version -+ andb $0xFE, %al # don't accidentally reset -+ outb %al, $0x92 -+ -+ # Wait for configuration port A to take effect -+a20_fast_wait: -+ xorw %cx, %cx -+a20_fast_wait_loop: -+ call a20_test -+ jnz a20_done -+ loop a20_fast_wait_loop -+ -+ # A20 is still not responding. Try frobbing it again. -+ # -+ decb (a20_tries) -+ jnz a20_try_loop -+ -+ movw $a20_err_msg, %si -+ call prtstr -+ -+a20_die: -+ hlt -+ jmp a20_die -+ -+a20_tries: -+ .byte A20_ENABLE_LOOPS -+ -+a20_err_msg: -+ .ascii "linux: fatal error: A20 gate not responding!" -+ .byte 13, 10, 0 -+ -+ # If we get here, all is good -+a20_done: -+ -+#endif /* CONFIG_X86_VOYAGER */ -+# set up gdt and idt and 32bit start address -+ lidt idt_48 # load idt with 0,0 -+ xorl %eax, %eax # Compute gdt_base -+ movw %ds, %ax # (Convert %ds:gdt to a linear ptr) -+ shll $4, %eax -+ addl %eax, code32 -+ addl $gdt, %eax -+ movl %eax, (gdt_48+2) -+ lgdt gdt_48 # load gdt with whatever is -+ # appropriate -+ -+# make sure any possible coprocessor is properly reset.. -+ xorw %ax, %ax -+ outb %al, $0xf0 -+ call delay -+ -+ outb %al, $0xf1 -+ call delay -+ -+# well, that went ok, I hope. Now we mask all interrupts - the rest -+# is done in init_IRQ(). -+ movb $0xFF, %al # mask all interrupts for now -+ outb %al, $0xA1 -+ call delay -+ -+ movb $0xFB, %al # mask all irq's but irq2 which -+ outb %al, $0x21 # is cascaded -+ -+# Well, that certainly wasn't fun :-(. Hopefully it works, and we don't -+# need no steenking BIOS anyway (except for the initial loading :-). -+# The BIOS-routine wants lots of unnecessary data, and it's less -+# "interesting" anyway. This is how REAL programmers do it. -+# -+# Well, now's the time to actually move into protected mode. To make -+# things as simple as possible, we do no register set-up or anything, -+# we let the gnu-compiled 32-bit programs do that. We just jump to -+# absolute address 0x1000 (or the loader supplied one), -+# in 32-bit protected mode. -+# -+# Note that the short jump isn't strictly needed, although there are -+# reasons why it might be a good idea. It won't hurt in any case. -+ movw $1, %ax # protected mode (PE) bit -+ lmsw %ax # This is it! -+ jmp flush_instr -+ -+flush_instr: -+ xorw %bx, %bx # Flag to indicate a boot -+ xorl %esi, %esi # Pointer to real-mode code -+ movw %cs, %si -+ subw $DELTA_INITSEG, %si -+ shll $4, %esi # Convert to 32-bit pointer -+ -+# jump to startup_32 in arch/i386/boot/compressed/head.S -+# -+# NOTE: For high loaded big kernels we need a -+# jmpi 0x100000,__BOOT_CS -+# -+# but we yet haven't reloaded the CS register, so the default size -+# of the target offset still is 16 bit. -+# However, using an operand prefix (0x66), the CPU will properly -+# take our 48 bit far pointer. (INTeL 80386 Programmer's Reference -+# Manual, Mixing 16-bit and 32-bit code, page 16-6) -+ -+ .byte 0x66, 0xea # prefix + jmpi-opcode -+code32: .long startup_32 # will be set to %cs+startup_32 -+ .word __BOOT_CS -+.code32 -+startup_32: -+ movl $(__BOOT_DS), %eax -+ movl %eax, %ds -+ movl %eax, %es -+ movl %eax, %fs -+ movl %eax, %gs -+ movl %eax, %ss -+ -+ xorl %eax, %eax -+1: incl %eax # check that A20 really IS enabled -+ movl %eax, 0x00000000 # loop forever if it isn't -+ cmpl %eax, 0x00100000 -+ je 1b -+ -+ # Jump to the 32bit entry point -+ jmpl *(code32_start - start + (DELTA_INITSEG << 4))(%esi) -+.code16 -+ -+# Here's a bunch of information about your current kernel.. -+kernel_version: .ascii UTS_RELEASE -+ .ascii " (" -+ .ascii LINUX_COMPILE_BY -+ .ascii "@" -+ .ascii LINUX_COMPILE_HOST -+ .ascii ") " -+ .ascii UTS_VERSION -+ .byte 0 -+ -+# This is the default real mode switch routine. -+# to be called just before protected mode transition -+default_switch: -+ cli # no interrupts allowed ! -+ movb $0x80, %al # disable NMI for bootup -+ # sequence -+ outb %al, $0x70 -+ lret -+ -+ -+#ifndef CONFIG_X86_VOYAGER -+# This routine tests whether or not A20 is enabled. If so, it -+# exits with zf = 0. -+# -+# The memory address used, 0x200, is the int $0x80 vector, which -+# should be safe. -+ -+A20_TEST_ADDR = 4*0x80 -+ -+a20_test: -+ pushw %cx -+ pushw %ax -+ xorw %cx, %cx -+ movw %cx, %fs # Low memory -+ decw %cx -+ movw %cx, %gs # High memory area -+ movw $A20_TEST_LOOPS, %cx -+ movw %fs:(A20_TEST_ADDR), %ax -+ pushw %ax -+a20_test_wait: -+ incw %ax -+ movw %ax, %fs:(A20_TEST_ADDR) -+ call delay # Serialize and make delay constant -+ cmpw %gs:(A20_TEST_ADDR+0x10), %ax -+ loope a20_test_wait -+ -+ popw %fs:(A20_TEST_ADDR) -+ popw %ax -+ popw %cx -+ ret -+ -+#endif /* CONFIG_X86_VOYAGER */ -+ -+# This routine checks that the keyboard command queue is empty -+# (after emptying the output buffers) -+# -+# Some machines have delusions that the keyboard buffer is always full -+# with no keyboard attached... -+# -+# If there is no keyboard controller, we will usually get 0xff -+# to all the reads. With each IO taking a microsecond and -+# a timeout of 100,000 iterations, this can take about half a -+# second ("delay" == outb to port 0x80). That should be ok, -+# and should also be plenty of time for a real keyboard controller -+# to empty. -+# -+ -+empty_8042: -+ pushl %ecx -+ movl $100000, %ecx -+ -+empty_8042_loop: -+ decl %ecx -+ jz empty_8042_end_loop -+ -+ call delay -+ -+ inb $0x64, %al # 8042 status port -+ testb $1, %al # output buffer? -+ jz no_output -+ -+ call delay -+ inb $0x60, %al # read it -+ jmp empty_8042_loop -+ -+no_output: -+ testb $2, %al # is input buffer full? -+ jnz empty_8042_loop # yes - loop -+empty_8042_end_loop: -+ popl %ecx -+ ret -+ -+# Read the cmos clock. Return the seconds in al -+gettime: -+ pushw %cx -+ movb $0x02, %ah -+ int $0x1a -+ movb %dh, %al # %dh contains the seconds -+ andb $0x0f, %al -+ movb %dh, %ah -+ movb $0x04, %cl -+ shrb %cl, %ah -+ aad -+ popw %cx -+ ret -+ -+# Delay is needed after doing I/O -+delay: -+ outb %al,$0x80 -+ ret -+ -+# Descriptor tables -+# -+# NOTE: The intel manual says gdt should be sixteen bytes aligned for -+# efficiency reasons. However, there are machines which are known not -+# to boot with misaligned GDTs, so alter this at your peril! If you alter -+# GDT_ENTRY_BOOT_CS (in asm/segment.h) remember to leave at least two -+# empty GDT entries (one for NULL and one reserved). -+# -+# NOTE: On some CPUs, the GDT must be 8 byte aligned. This is -+# true for the Voyager Quad CPU card which will not boot without -+# This directive. 16 byte aligment is recommended by intel. -+# -+ .align 16 -+gdt: -+ .fill GDT_ENTRY_BOOT_CS,8,0 -+ -+ .word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb) -+ .word 0 # base address = 0 -+ .word 0x9A00 # code read/exec -+ .word 0x00CF # granularity = 4096, 386 -+ # (+5th nibble of limit) -+ -+ .word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb) -+ .word 0 # base address = 0 -+ .word 0x9200 # data read/write -+ .word 0x00CF # granularity = 4096, 386 -+ # (+5th nibble of limit) -+gdt_end: -+ .align 4 -+ -+ .word 0 # alignment byte -+idt_48: -+ .word 0 # idt limit = 0 -+ .word 0, 0 # idt base = 0L -+ -+ .word 0 # alignment byte -+gdt_48: -+ .word gdt_end - gdt - 1 # gdt limit -+ .word 0, 0 # gdt base (filled in later) -+ -+#ifndef CONFIG_VGA_NOPROBE -+# Include video setup & detection code -+ -+#include "video.S" -+#endif -+ -+# Setup signature -- must be last -+setup_sig1: .word SIG1 -+setup_sig2: .word SIG2 -+ -+# After this point, there is some free space which is used by the video mode -+# handling code to store the temporary mode table (not used by the kernel). -+ -+modelist: -+ -+.text -+endtext: -+.data -+enddata: -+.bss -+endbss: -diff --git a/arch/i386/configs/olpc_defconfig b/arch/i386/configs/olpc_defconfig -new file mode 100644 -index 0000000..f1675e8 ---- /dev/null -+++ b/arch/i386/configs/olpc_defconfig -@@ -0,0 +1,2183 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.22-rc5 -+# Wed Jun 20 08:26:53 2007 -+# -+CONFIG_X86_32=y -+CONFIG_GENERIC_TIME=y -+CONFIG_CLOCKSOURCE_WATCHDOG=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_SEMAPHORE_SLEEPERS=y -+CONFIG_X86=y -+CONFIG_MMU=y -+CONFIG_ZONE_DMA=y -+CONFIG_QUICKLIST=y -+CONFIG_GENERIC_ISA_DMA=y -+CONFIG_GENERIC_IOMAP=y -+CONFIG_GENERIC_BUG=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_ARCH_MAY_HAVE_PC_FDC=y -+CONFIG_DMI=y -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# Code maturity level options -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+ -+# -+# General setup -+# -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+# CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_BSD_PROCESS_ACCT=y -+# CONFIG_BSD_PROCESS_ACCT_V3 is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_UTS_NS is not set -+CONFIG_AUDIT=y -+CONFIG_AUDITSYSCALL=y -+# CONFIG_IKCONFIG is not set -+CONFIG_LOG_BUF_SHIFT=17 -+# CONFIG_SYSFS_DEPRECATED is not set -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+# CONFIG_SYSCTL_SYSCALL is not set -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+CONFIG_KALLSYMS_EXTRA_PASS=y -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+# CONFIG_BASE_FULL is not set -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=1 -+ -+# -+# Loadable module support -+# -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_KMOD=y -+ -+# -+# Block layer -+# -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+# CONFIG_IOSCHED_AS is not set -+# CONFIG_IOSCHED_DEADLINE is not set -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+ -+# -+# Processor type and features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+# CONFIG_SMP is not set -+CONFIG_X86_PC=y -+# CONFIG_X86_ELAN is not set -+# CONFIG_X86_VOYAGER is not set -+# CONFIG_X86_NUMAQ is not set -+# CONFIG_X86_SUMMIT is not set -+# CONFIG_X86_BIGSMP is not set -+# CONFIG_X86_VISWS is not set -+# CONFIG_X86_GENERICARCH is not set -+# CONFIG_X86_ES7000 is not set -+# CONFIG_PARAVIRT is not set -+# CONFIG_M386 is not set -+# CONFIG_M486 is not set -+# CONFIG_M586 is not set -+# CONFIG_M586TSC is not set -+# CONFIG_M586MMX is not set -+# CONFIG_M686 is not set -+# CONFIG_MPENTIUMII is not set -+# CONFIG_MPENTIUMIII is not set -+# CONFIG_MPENTIUMM is not set -+# CONFIG_MCORE2 is not set -+# CONFIG_MPENTIUM4 is not set -+# CONFIG_MK6 is not set -+# CONFIG_MK7 is not set -+# CONFIG_MK8 is not set -+# CONFIG_MCRUSOE is not set -+# CONFIG_MEFFICEON is not set -+# CONFIG_MWINCHIPC6 is not set -+# CONFIG_MWINCHIP2 is not set -+# CONFIG_MWINCHIP3D is not set -+# CONFIG_MGEODEGX1 is not set -+CONFIG_MGEODE_LX=y -+# CONFIG_MCYRIXIII is not set -+# CONFIG_MVIAC3_2 is not set -+# CONFIG_MVIAC7 is not set -+# CONFIG_X86_GENERIC is not set -+CONFIG_X86_CMPXCHG=y -+CONFIG_X86_L1_CACHE_SHIFT=5 -+CONFIG_X86_XADD=y -+CONFIG_RWSEM_XCHGADD_ALGORITHM=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_X86_WP_WORKS_OK=y -+CONFIG_X86_INVLPG=y -+CONFIG_X86_BSWAP=y -+CONFIG_X86_POPAD_OK=y -+CONFIG_X86_USE_PPRO_CHECKSUM=y -+CONFIG_X86_USE_3DNOW=y -+CONFIG_X86_TSC=y -+CONFIG_X86_MINIMUM_CPU_MODEL=4 -+# CONFIG_HPET_TIMER is not set -+# CONFIG_PREEMPT_NONE is not set -+# CONFIG_PREEMPT_VOLUNTARY is not set -+CONFIG_PREEMPT=y -+CONFIG_PREEMPT_BKL=y -+# CONFIG_X86_UP_APIC is not set -+# CONFIG_X86_MCE is not set -+# CONFIG_VM86 is not set -+# CONFIG_TOSHIBA is not set -+# CONFIG_I8K is not set -+CONFIG_X86_REBOOTFIXUPS=y -+# CONFIG_MICROCODE is not set -+CONFIG_X86_MSR=y -+CONFIG_X86_CPUID=m -+ -+# -+# Firmware Drivers -+# -+# CONFIG_EDD is not set -+# CONFIG_DELL_RBU is not set -+# CONFIG_DCDBAS is not set -+CONFIG_NOHIGHMEM=y -+# CONFIG_HIGHMEM4G is not set -+# CONFIG_HIGHMEM64G is not set -+CONFIG_VMSPLIT_3G=y -+# CONFIG_VMSPLIT_3G_OPT is not set -+# CONFIG_VMSPLIT_2G is not set -+# CONFIG_VMSPLIT_2G_OPT is not set -+# CONFIG_VMSPLIT_1G is not set -+CONFIG_PAGE_OFFSET=0xC0000000 -+CONFIG_ARCH_FLATMEM_ENABLE=y -+CONFIG_ARCH_SPARSEMEM_ENABLE=y -+CONFIG_ARCH_SELECT_MEMORY_MODEL=y -+CONFIG_ARCH_POPULATES_NODE_MAP=y -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_SPARSEMEM_STATIC=y -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_NR_QUICK=1 -+# CONFIG_MATH_EMULATION is not set -+# CONFIG_MTRR is not set -+# CONFIG_SECCOMP is not set -+# CONFIG_VGA_NOPROBE is not set -+CONFIG_HZ_100=y -+# CONFIG_HZ_250 is not set -+# CONFIG_HZ_300 is not set -+# CONFIG_HZ_1000 is not set -+CONFIG_HZ=100 -+CONFIG_KEXEC=y -+CONFIG_PHYSICAL_START=0x400000 -+# CONFIG_RELOCATABLE is not set -+CONFIG_PHYSICAL_ALIGN=0x100000 -+# CONFIG_COMPAT_VDSO is not set -+ -+# -+# Power management options (ACPI, APM) -+# -+CONFIG_PM=y -+CONFIG_PM_LEGACY=y -+CONFIG_PM_DEBUG=y -+CONFIG_DISABLE_SUSPEND_VT_SWITCH=y -+# CONFIG_PM_TRACE is not set -+# CONFIG_PM_SYSFS_DEPRECATED is not set -+CONFIG_SOFTWARE_SUSPEND=y -+CONFIG_PM_STD_PARTITION="" -+ -+# -+# ACPI (Advanced Configuration and Power Interface) Support -+# -+# CONFIG_ACPI is not set -+# CONFIG_APM is not set -+ -+# -+# CPU Frequency scaling -+# -+# CONFIG_CPU_FREQ is not set -+ -+# -+# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -+# -+CONFIG_PCI=y -+# CONFIG_PCI_GOBIOS is not set -+# CONFIG_PCI_GOMMCONFIG is not set -+# CONFIG_PCI_GODIRECT is not set -+# CONFIG_PCI_GOANY is not set -+CONFIG_PCI_GOOLPC=y -+CONFIG_PCI_DIRECT=y -+CONFIG_PCI_OLPC=y -+# CONFIG_PCIEPORTBUS is not set -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+# CONFIG_PCI_DEBUG is not set -+CONFIG_ISA_DMA_API=y -+# CONFIG_ISA is not set -+# CONFIG_MCA is not set -+# CONFIG_SCx200 is not set -+CONFIG_GEODE_MFGPT_TIMER=y -+CONFIG_OLPC=y -+CONFIG_OLPC_PM=y -+CONFIG_OPEN_FIRMWARE=y -+ -+# -+# PCCARD (PCMCIA/CardBus) support -+# -+# CONFIG_PCCARD is not set -+# CONFIG_HOTPLUG_PCI is not set -+ -+# -+# Executable file formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+CONFIG_BINFMT_MISC=y -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+CONFIG_XFRM_USER=y -+# CONFIG_XFRM_SUB_POLICY is not set -+CONFIG_XFRM_MIGRATE=y -+CONFIG_NET_KEY=m -+CONFIG_NET_KEY_MIGRATE=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_ASK_IP_FIB_HASH=y -+# CONFIG_IP_FIB_TRIE is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set -+CONFIG_IP_ROUTE_VERBOSE=y -+# CONFIG_IP_PNP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+CONFIG_SYN_COOKIES=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_TUNNEL=m -+CONFIG_INET_TUNNEL=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_DIAG is not set -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=y -+CONFIG_TCP_CONG_CUBIC=m -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_VEGAS=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=m -+CONFIG_TCP_CONG_ILLINOIS=m -+CONFIG_DEFAULT_BIC=y -+# CONFIG_DEFAULT_CUBIC is not set -+# CONFIG_DEFAULT_HTCP is not set -+# CONFIG_DEFAULT_VEGAS is not set -+# CONFIG_DEFAULT_WESTWOOD is not set -+# CONFIG_DEFAULT_RENO is not set -+CONFIG_DEFAULT_TCP_CONG="bic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IP_VS is not set -+CONFIG_IPV6=y -+CONFIG_IPV6_PRIVACY=y -+CONFIG_IPV6_ROUTER_PREF=y -+CONFIG_IPV6_ROUTE_INFO=y -+CONFIG_IPV6_OPTIMISTIC_DAD=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=y -+CONFIG_INET6_XFRM_TUNNEL=m -+CONFIG_INET6_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_IPV6_SIT=m -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_SUBTREES=y -+# CONFIG_NETLABEL is not set -+CONFIG_NETWORK_SECMARK=y -+CONFIG_NETFILTER=y -+# CONFIG_NETFILTER_DEBUG is not set -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_NETLINK=m -+# CONFIG_NETFILTER_NETLINK_QUEUE is not set -+# CONFIG_NETFILTER_NETLINK_LOG is not set -+CONFIG_NF_CONNTRACK_ENABLED=m -+CONFIG_NF_CONNTRACK=m -+# CONFIG_NF_CT_ACCT is not set -+# CONFIG_NF_CONNTRACK_MARK is not set -+# CONFIG_NF_CONNTRACK_SECMARK is not set -+# CONFIG_NF_CONNTRACK_EVENTS is not set -+# CONFIG_NF_CT_PROTO_SCTP is not set -+# CONFIG_NF_CONNTRACK_AMANDA is not set -+CONFIG_NF_CONNTRACK_FTP=m -+# CONFIG_NF_CONNTRACK_H323 is not set -+CONFIG_NF_CONNTRACK_IRC=m -+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -+# CONFIG_NF_CONNTRACK_PPTP is not set -+# CONFIG_NF_CONNTRACK_SANE is not set -+# CONFIG_NF_CONNTRACK_SIP is not set -+# CONFIG_NF_CONNTRACK_TFTP is not set -+# CONFIG_NF_CT_NETLINK is not set -+CONFIG_NETFILTER_XTABLES=m -+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -+# CONFIG_NETFILTER_XT_TARGET_MARK is not set -+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set -+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set -+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -+# CONFIG_NETFILTER_XT_MATCH_ESP is not set -+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set -+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set -+# CONFIG_NETFILTER_XT_MATCH_MAC is not set -+# CONFIG_NETFILTER_XT_MATCH_MARK is not set -+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set -+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -+# CONFIG_NETFILTER_XT_MATCH_REALM is not set -+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -+# CONFIG_NETFILTER_XT_MATCH_STRING is not set -+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -+ -+# -+# IP: Netfilter Configuration -+# -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+# CONFIG_IP_NF_QUEUE is not set -+CONFIG_IP_NF_IPTABLES=m -+# CONFIG_IP_NF_MATCH_IPRANGE is not set -+# CONFIG_IP_NF_MATCH_TOS is not set -+# CONFIG_IP_NF_MATCH_RECENT is not set -+# CONFIG_IP_NF_MATCH_ECN is not set -+# CONFIG_IP_NF_MATCH_AH is not set -+# CONFIG_IP_NF_MATCH_TTL is not set -+# CONFIG_IP_NF_MATCH_OWNER is not set -+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -+CONFIG_IP_NF_FILTER=m -+# CONFIG_IP_NF_TARGET_REJECT is not set -+CONFIG_IP_NF_TARGET_LOG=m -+# CONFIG_IP_NF_TARGET_ULOG is not set -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+# CONFIG_IP_NF_TARGET_REDIRECT is not set -+# CONFIG_IP_NF_TARGET_NETMAP is not set -+# CONFIG_IP_NF_TARGET_SAME is not set -+# CONFIG_NF_NAT_SNMP_BASIC is not set -+CONFIG_NF_NAT_FTP=m -+CONFIG_NF_NAT_IRC=m -+# CONFIG_NF_NAT_TFTP is not set -+# CONFIG_NF_NAT_AMANDA is not set -+# CONFIG_NF_NAT_PPTP is not set -+# CONFIG_NF_NAT_H323 is not set -+# CONFIG_NF_NAT_SIP is not set -+# CONFIG_IP_NF_MANGLE is not set -+# CONFIG_IP_NF_RAW is not set -+# CONFIG_IP_NF_ARPTABLES is not set -+ -+# -+# IPv6: Netfilter Configuration (EXPERIMENTAL) -+# -+# CONFIG_NF_CONNTRACK_IPV6 is not set -+# CONFIG_IP6_NF_QUEUE is not set -+# CONFIG_IP6_NF_IPTABLES is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+ -+# -+# QoS and/or fair queueing -+# -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_FIFO=y -+ -+# -+# Queueing/Scheduling -+# -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_INGRESS=m -+ -+# -+# Classification -+# -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_ROUTE=y -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_STACK=32 -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+# CONFIG_NET_ACT_IPT is not set -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_ESTIMATOR=y -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_NET_TCPPROBE is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+CONFIG_FIB_RULES=y -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+CONFIG_WIRELESS_EXT=y -+# CONFIG_MAC80211 is not set -+CONFIG_IEEE80211=m -+# CONFIG_IEEE80211_DEBUG is not set -+CONFIG_IEEE80211_CRYPT_WEP=m -+CONFIG_IEEE80211_CRYPT_CCMP=m -+CONFIG_IEEE80211_CRYPT_TKIP=m -+CONFIG_IEEE80211_SOFTMAC=m -+CONFIG_IEEE80211_SOFTMAC_DEBUG=y -+# CONFIG_RFKILL is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+ -+# -+# Connector - unified userspace <-> kernelspace linker -+# -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+CONFIG_MTD_CONCAT=m -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+# CONFIG_MTD_CMDLINE_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=m -+CONFIG_MTD_BLKDEVS=m -+CONFIG_MTD_BLOCK=m -+CONFIG_MTD_BLOCK_RO=m -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_TS5500 is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_PMC551 is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+CONFIG_MTD_NAND_CAFE=y -+# CONFIG_MTD_NAND_CS553X is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+ -+# -+# Parallel port support -+# -+# CONFIG_PARPORT is not set -+ -+# -+# Plug and Play support -+# -+# CONFIG_PNPACPI is not set -+ -+# -+# Block devices -+# -+# CONFIG_BLK_DEV_FD is not set -+# CONFIG_BLK_CPQ_DA is not set -+# CONFIG_BLK_CPQ_CISS_DA is not set -+# CONFIG_BLK_DEV_DAC960 is not set -+# CONFIG_BLK_DEV_UMEM is not set -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=m -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_NBD=m -+# CONFIG_BLK_DEV_SX8 is not set -+CONFIG_BLK_DEV_UB=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=16384 -+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+ -+# -+# Misc devices -+# -+# CONFIG_IBM_ASM is not set -+# CONFIG_PHANTOM is not set -+# CONFIG_SGI_IOC4 is not set -+# CONFIG_TIFM_CORE is not set -+# CONFIG_EEPROM_93CX6 is not set -+CONFIG_IDE=m -+CONFIG_IDE_MAX_HWIFS=4 -+CONFIG_BLK_DEV_IDE=m -+ -+# -+# Please see Documentation/ide.txt for help/info on IDE drives -+# -+# CONFIG_BLK_DEV_IDE_SATA is not set -+# CONFIG_BLK_DEV_HD_IDE is not set -+CONFIG_BLK_DEV_IDEDISK=m -+CONFIG_IDEDISK_MULTI_MODE=y -+# CONFIG_BLK_DEV_IDECD is not set -+# CONFIG_BLK_DEV_IDETAPE is not set -+# CONFIG_BLK_DEV_IDEFLOPPY is not set -+# CONFIG_BLK_DEV_IDESCSI is not set -+CONFIG_IDE_TASK_IOCTL=y -+# CONFIG_IDE_PROC_FS is not set -+ -+# -+# IDE chipset support/bugfixes -+# -+CONFIG_IDE_GENERIC=m -+# CONFIG_BLK_DEV_CMD640 is not set -+CONFIG_BLK_DEV_IDEPCI=y -+CONFIG_IDEPCI_SHARE_IRQ=y -+# CONFIG_IDEPCI_PCIBUS_ORDER is not set -+# CONFIG_BLK_DEV_OFFBOARD is not set -+# CONFIG_BLK_DEV_GENERIC is not set -+# CONFIG_BLK_DEV_OPTI621 is not set -+# CONFIG_BLK_DEV_RZ1000 is not set -+CONFIG_BLK_DEV_IDEDMA_PCI=y -+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -+CONFIG_IDEDMA_ONLYDISK=y -+# CONFIG_BLK_DEV_AEC62XX is not set -+# CONFIG_BLK_DEV_ALI15X3 is not set -+# CONFIG_BLK_DEV_AMD74XX is not set -+# CONFIG_BLK_DEV_ATIIXP is not set -+# CONFIG_BLK_DEV_CMD64X is not set -+# CONFIG_BLK_DEV_TRIFLEX is not set -+# CONFIG_BLK_DEV_CY82C693 is not set -+# CONFIG_BLK_DEV_CS5520 is not set -+# CONFIG_BLK_DEV_CS5530 is not set -+# CONFIG_BLK_DEV_CS5535 is not set -+# CONFIG_BLK_DEV_HPT34X is not set -+# CONFIG_BLK_DEV_HPT366 is not set -+# CONFIG_BLK_DEV_JMICRON is not set -+# CONFIG_BLK_DEV_SC1200 is not set -+CONFIG_BLK_DEV_PIIX=m -+# CONFIG_BLK_DEV_IT8213 is not set -+# CONFIG_BLK_DEV_IT821X is not set -+# CONFIG_BLK_DEV_NS87415 is not set -+# CONFIG_BLK_DEV_PDC202XX_OLD is not set -+# CONFIG_BLK_DEV_PDC202XX_NEW is not set -+# CONFIG_BLK_DEV_SVWKS is not set -+# CONFIG_BLK_DEV_SIIMAGE is not set -+# CONFIG_BLK_DEV_SIS5513 is not set -+# CONFIG_BLK_DEV_SLC90E66 is not set -+# CONFIG_BLK_DEV_TRM290 is not set -+# CONFIG_BLK_DEV_VIA82CXXX is not set -+# CONFIG_BLK_DEV_TC86C001 is not set -+# CONFIG_IDE_ARM is not set -+CONFIG_BLK_DEV_IDEDMA=y -+# CONFIG_IDEDMA_IVB is not set -+# CONFIG_BLK_DEV_HD is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=m -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=m -+CONFIG_CHR_DEV_SCH=m -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+ -+# -+# SCSI low-level drivers -+# -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC7XXX_OLD is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_DPT_I2O is not set -+# CONFIG_SCSI_ADVANSYS is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_HPTIOP is not set -+# CONFIG_SCSI_BUSLOGIC is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_EATA is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+# CONFIG_SCSI_GDTH is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_FC is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_LPFC is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_DC390T is not set -+# CONFIG_SCSI_NSP32 is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_SRP is not set -+# CONFIG_ATA is not set -+ -+# -+# Multi-device support (RAID and LVM) -+# -+# CONFIG_MD is not set -+ -+# -+# Fusion MPT device support -+# -+# CONFIG_FUSION is not set -+# CONFIG_FUSION_SPI is not set -+# CONFIG_FUSION_FC is not set -+# CONFIG_FUSION_SAS is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_IEEE1394 is not set -+ -+# -+# I2O device support -+# -+# CONFIG_I2O is not set -+# CONFIG_MACINTOSH_DRIVERS is not set -+ -+# -+# Network device support -+# -+CONFIG_NETDEVICES=y -+CONFIG_IFB=m -+CONFIG_DUMMY=m -+# CONFIG_BONDING is not set -+# CONFIG_EQUALIZER is not set -+CONFIG_TUN=m -+# CONFIG_ARCNET is not set -+# CONFIG_PHYLIB is not set -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=m -+# CONFIG_HAPPYMEAL is not set -+# CONFIG_SUNGEM is not set -+# CONFIG_CASSINI is not set -+# CONFIG_NET_VENDOR_3COM is not set -+ -+# -+# Tulip family network device support -+# -+# CONFIG_NET_TULIP is not set -+# CONFIG_HP100 is not set -+CONFIG_NET_PCI=y -+CONFIG_PCNET32=m -+# CONFIG_PCNET32_NAPI is not set -+# CONFIG_AMD8111_ETH is not set -+# CONFIG_ADAPTEC_STARFIRE is not set -+# CONFIG_B44 is not set -+# CONFIG_FORCEDETH is not set -+# CONFIG_DGRS is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_E100 is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NATSEMI is not set -+CONFIG_NE2K_PCI=m -+CONFIG_8139CP=m -+# CONFIG_8139TOO is not set -+# CONFIG_SIS900 is not set -+# CONFIG_EPIC100 is not set -+# CONFIG_SUNDANCE is not set -+# CONFIG_TLAN is not set -+# CONFIG_VIA_RHINE is not set -+# CONFIG_SC92031 is not set -+CONFIG_NETDEV_1000=y -+# CONFIG_ACENIC is not set -+# CONFIG_DL2K is not set -+# CONFIG_E1000 is not set -+# CONFIG_NS83820 is not set -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+# CONFIG_R8169 is not set -+# CONFIG_SIS190 is not set -+# CONFIG_SKGE is not set -+# CONFIG_SKY2 is not set -+# CONFIG_SK98LIN is not set -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_TIGON3 is not set -+# CONFIG_BNX2 is not set -+# CONFIG_QLA3XXX is not set -+# CONFIG_ATL1 is not set -+CONFIG_NETDEV_10000=y -+# CONFIG_CHELSIO_T1 is not set -+# CONFIG_CHELSIO_T3 is not set -+# CONFIG_IXGB is not set -+# CONFIG_S2IO is not set -+# CONFIG_MYRI10GE is not set -+# CONFIG_NETXEN_NIC is not set -+# CONFIG_MLX4_CORE is not set -+# CONFIG_TR is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+CONFIG_WLAN_80211=y -+# CONFIG_IPW2100 is not set -+# CONFIG_IPW2200 is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_DEBUG=y -+# CONFIG_AIRO is not set -+# CONFIG_HERMES is not set -+# CONFIG_ATMEL is not set -+# CONFIG_PRISM54 is not set -+# CONFIG_USB_ZD1201 is not set -+# CONFIG_PRISM54_USB is not set -+# CONFIG_HOSTAP is not set -+# CONFIG_BCM43XX is not set -+# CONFIG_ZD1211RW is not set -+# CONFIG_ADM8211 is not set -+# CONFIG_ACX_PCI is not set -+# CONFIG_ACX_USB is not set -+ -+# -+# USB Network Adapters -+# -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_USBNET_MII=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_RNDIS_HOST=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+CONFIG_USB_EPSON2888=y -+# CONFIG_USB_KC2190 is not set -+CONFIG_USB_NET_ZAURUS=m -+# CONFIG_WAN is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+CONFIG_PPP=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+# CONFIG_PPP_BSDCOMP is not set -+CONFIG_PPP_MPPE=m -+CONFIG_PPPOE=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLHC=m -+CONFIG_SLIP_SMART=y -+# CONFIG_SLIP_MODE_SLIP6 is not set -+# CONFIG_NET_FC is not set -+# CONFIG_SHAPER is not set -+CONFIG_NETCONSOLE=m -+CONFIG_NETPOLL=y -+CONFIG_NETPOLL_TRAP=y -+CONFIG_NET_POLL_CONTROLLER=y -+ -+# -+# ISDN subsystem -+# -+# CONFIG_ISDN is not set -+ -+# -+# Telephony Support -+# -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+CONFIG_INPUT_JOYDEV=m -+# CONFIG_INPUT_TSDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+CONFIG_KEYBOARD_ATKBD=y -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+CONFIG_INPUT_MOUSE=y -+CONFIG_MOUSE_PS2=m -+# CONFIG_MOUSE_PS2_ALPS is not set -+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -+# CONFIG_MOUSE_PS2_SYNAPTICS is not set -+# CONFIG_MOUSE_PS2_LIFEBOOK is not set -+# CONFIG_MOUSE_PS2_TRACKPOINT is not set -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+CONFIG_MOUSE_PS2_OLPC=y -+# CONFIG_MOUSE_SERIAL is not set -+# CONFIG_MOUSE_APPLETOUCH is not set -+# CONFIG_MOUSE_VSXXXAA is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PCSPKR=m -+# CONFIG_INPUT_WISTRON_BTNS is not set -+# CONFIG_INPUT_ATI_REMOTE is not set -+# CONFIG_INPUT_ATI_REMOTE2 is not set -+# CONFIG_INPUT_KEYSPAN_REMOTE is not set -+# CONFIG_INPUT_POWERMATE is not set -+# CONFIG_INPUT_YEALINK is not set -+CONFIG_INPUT_UINPUT=m -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_I8042=y -+CONFIG_SERIO_SERPORT=y -+# CONFIG_SERIO_CT82C710 is not set -+# CONFIG_SERIO_PCIPS2 is not set -+CONFIG_SERIO_LIBPS2=y -+CONFIG_SERIO_RAW=m -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_PCI=y -+CONFIG_SERIAL_8250_NR_UARTS=1 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DETECT_IRQ=y -+CONFIG_SERIAL_8250_RSA=y -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+CONFIG_UNIX98_PTYS=y -+# CONFIG_LEGACY_PTYS is not set -+ -+# -+# IPMI -+# -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_WATCHDOG=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+ -+# -+# Watchdog Device Drivers -+# -+CONFIG_SOFT_WATCHDOG=m -+# CONFIG_ACQUIRE_WDT is not set -+# CONFIG_ADVANTECH_WDT is not set -+# CONFIG_ALIM1535_WDT is not set -+# CONFIG_ALIM7101_WDT is not set -+# CONFIG_SC520_WDT is not set -+# CONFIG_EUROTECH_WDT is not set -+# CONFIG_IB700_WDT is not set -+# CONFIG_IBMASR is not set -+# CONFIG_WAFER_WDT is not set -+# CONFIG_I6300ESB_WDT is not set -+# CONFIG_ITCO_WDT is not set -+# CONFIG_SC1200_WDT is not set -+# CONFIG_PC87413_WDT is not set -+# CONFIG_60XX_WDT is not set -+# CONFIG_SBC8360_WDT is not set -+# CONFIG_CPU5_WDT is not set -+# CONFIG_SMSC37B787_WDT is not set -+# CONFIG_W83627HF_WDT is not set -+# CONFIG_W83697HF_WDT is not set -+# CONFIG_W83877F_WDT is not set -+# CONFIG_W83977F_WDT is not set -+# CONFIG_MACHZ_WDT is not set -+# CONFIG_SBC_EPX_C3_WATCHDOG is not set -+ -+# -+# PCI-based Watchdog Cards -+# -+# CONFIG_PCIPCWATCHDOG is not set -+# CONFIG_WDTPCI is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_HW_RANDOM=y -+# CONFIG_HW_RANDOM_INTEL is not set -+# CONFIG_HW_RANDOM_AMD is not set -+CONFIG_HW_RANDOM_GEODE=y -+# CONFIG_HW_RANDOM_VIA is not set -+CONFIG_NVRAM=y -+# CONFIG_RTC is not set -+# CONFIG_GEN_RTC is not set -+# CONFIG_R3964 is not set -+# CONFIG_APPLICOM is not set -+# CONFIG_SONYPI is not set -+# CONFIG_AGP is not set -+# CONFIG_DRM is not set -+# CONFIG_MWAVE is not set -+# CONFIG_PC8736x_GPIO is not set -+# CONFIG_NSC_GPIO is not set -+CONFIG_CS5535_GPIO=m -+# CONFIG_RAW_DRIVER is not set -+CONFIG_HANGCHECK_TIMER=m -+ -+# -+# TPM devices -+# -+# CONFIG_TCG_TPM is not set -+# CONFIG_TELCLOCK is not set -+CONFIG_DEVPORT=y -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_CHARDEV=m -+ -+# -+# I2C Algorithms -+# -+# CONFIG_I2C_ALGOBIT is not set -+# CONFIG_I2C_ALGOPCF is not set -+# CONFIG_I2C_ALGOPCA is not set -+ -+# -+# I2C Hardware Bus support -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_I810 is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_PROSAVAGE is not set -+# CONFIG_I2C_SAVAGE4 is not set -+# CONFIG_I2C_SIMTEC is not set -+CONFIG_SCx200_ACB=y -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_TINY_USB is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+# CONFIG_I2C_VOODOO3 is not set -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_SENSORS_DS1337 is not set -+# CONFIG_SENSORS_DS1374 is not set -+# CONFIG_SENSORS_EEPROM is not set -+# CONFIG_SENSORS_PCF8574 is not set -+# CONFIG_SENSORS_PCA9539 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_MAX6875 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+ -+# -+# SPI support -+# -+# CONFIG_SPI is not set -+# CONFIG_SPI_MASTER is not set -+ -+# -+# Dallas's 1-wire bus -+# -+# CONFIG_W1 is not set -+CONFIG_POWER_SUPPLY=y -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+# CONFIG_PDA_POWER is not set -+# CONFIG_BATTERY_DS2760 is not set -+CONFIG_BATTERY_OLPC=y -+# CONFIG_HWMON is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+ -+# -+# Multimedia devices -+# -+CONFIG_VIDEO_DEV=y -+# CONFIG_VIDEO_V4L1 is not set -+CONFIG_VIDEO_V4L1_COMPAT=y -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_CAPTURE_DRIVERS=y -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -+ -+# -+# Encoders/decoders and other helper chips -+# -+ -+# -+# Audio decoders -+# -+# CONFIG_VIDEO_TDA9840 is not set -+# CONFIG_VIDEO_TEA6415C is not set -+# CONFIG_VIDEO_TEA6420 is not set -+# CONFIG_VIDEO_MSP3400 is not set -+# CONFIG_VIDEO_CS53L32A is not set -+# CONFIG_VIDEO_TLV320AIC23B is not set -+# CONFIG_VIDEO_WM8775 is not set -+# CONFIG_VIDEO_WM8739 is not set -+ -+# -+# Video decoders -+# -+CONFIG_VIDEO_OV7670=y -+# CONFIG_VIDEO_SAA711X is not set -+# CONFIG_VIDEO_TVP5150 is not set -+ -+# -+# Video and audio decoders -+# -+# CONFIG_VIDEO_CX25840 is not set -+ -+# -+# MPEG video encoders -+# -+# CONFIG_VIDEO_CX2341X is not set -+ -+# -+# Video encoders -+# -+# CONFIG_VIDEO_SAA7127 is not set -+ -+# -+# Video improvement chips -+# -+# CONFIG_VIDEO_UPD64031A is not set -+# CONFIG_VIDEO_UPD64083 is not set -+# CONFIG_VIDEO_VIVI is not set -+# CONFIG_VIDEO_SAA5246A is not set -+# CONFIG_VIDEO_SAA5249 is not set -+# CONFIG_VIDEO_SAA7134 is not set -+# CONFIG_VIDEO_HEXIUM_ORION is not set -+# CONFIG_VIDEO_HEXIUM_GEMINI is not set -+# CONFIG_VIDEO_CX88 is not set -+CONFIG_VIDEO_CAFE_CCIC=y -+CONFIG_V4L_USB_DRIVERS=y -+# CONFIG_VIDEO_PVRUSB2 is not set -+# CONFIG_VIDEO_USBVISION is not set -+# CONFIG_USB_SN9C102 is not set -+# CONFIG_USB_ZR364XX is not set -+CONFIG_RADIO_ADAPTERS=y -+# CONFIG_RADIO_GEMTEK_PCI is not set -+# CONFIG_RADIO_MAXIRADIO is not set -+# CONFIG_RADIO_MAESTRO is not set -+# CONFIG_USB_DSBR is not set -+# CONFIG_DVB_CORE is not set -+CONFIG_DAB=y -+# CONFIG_USB_DABUSB is not set -+ -+# -+# Graphics support -+# -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_LCD_CLASS_DEVICE=y -+# CONFIG_BACKLIGHT_PROGEAR is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+CONFIG_VGASTATE=m -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_SYS_FILLRECT is not set -+# CONFIG_FB_SYS_COPYAREA is not set -+# CONFIG_FB_SYS_IMAGEBLIT is not set -+# CONFIG_FB_SYS_FOPS is not set -+CONFIG_FB_DEFERRED_IO=y -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+CONFIG_FB_MODE_HELPERS=y -+CONFIG_FB_TILEBLITTING=y -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_CIRRUS is not set -+# CONFIG_FB_PM2 is not set -+# CONFIG_FB_CYBER2000 is not set -+# CONFIG_FB_ARC is not set -+# CONFIG_FB_ASILIANT is not set -+# CONFIG_FB_IMSTT is not set -+CONFIG_FB_VGA16=m -+CONFIG_FB_VESA=y -+# CONFIG_FB_HECUBA is not set -+# CONFIG_FB_HGA is not set -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_NVIDIA is not set -+# CONFIG_FB_RIVA is not set -+# CONFIG_FB_I810 is not set -+# CONFIG_FB_LE80578 is not set -+# CONFIG_FB_INTEL is not set -+# CONFIG_FB_MATROX is not set -+# CONFIG_FB_RADEON is not set -+# CONFIG_FB_ATY128 is not set -+# CONFIG_FB_ATY is not set -+# CONFIG_FB_S3 is not set -+# CONFIG_FB_SAVAGE is not set -+# CONFIG_FB_SIS is not set -+# CONFIG_FB_NEOMAGIC is not set -+# CONFIG_FB_KYRO is not set -+# CONFIG_FB_3DFX is not set -+# CONFIG_FB_VOODOO1 is not set -+# CONFIG_FB_VT8623 is not set -+# CONFIG_FB_CYBLA is not set -+# CONFIG_FB_TRIDENT is not set -+# CONFIG_FB_ARK is not set -+# CONFIG_FB_PM3 is not set -+CONFIG_FB_GEODE=y -+CONFIG_FB_GEODE_LX=y -+CONFIG_FB_GEODE_GX=y -+# CONFIG_FB_GEODE_GX1 is not set -+CONFIG_FB_OLPC_DCON=y -+# CONFIG_FB_VIRTUAL is not set -+ -+# -+# Console display driver support -+# -+CONFIG_VGA_CONSOLE=y -+CONFIG_VGACON_SOFT_SCROLLBACK=y -+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -+CONFIG_VIDEO_SELECT=y -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -+CONFIG_FONTS=y -+# CONFIG_FONT_8x8 is not set -+CONFIG_FONT_8x16=y -+# CONFIG_FONT_6x11 is not set -+# CONFIG_FONT_7x14 is not set -+# CONFIG_FONT_PEARL_8x8 is not set -+# CONFIG_FONT_ACORN_8x8 is not set -+# CONFIG_FONT_MINI_4x6 is not set -+# CONFIG_FONT_SUN8x16 is not set -+CONFIG_FONT_SUN12x22=y -+# CONFIG_FONT_10x18 is not set -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_LOGO_LINUX_CLUT224=y -+ -+# -+# Sound -+# -+CONFIG_SOUND=y -+ -+# -+# Advanced Linux Sound Architecture -+# -+CONFIG_SND=y -+CONFIG_SND_TIMER=y -+CONFIG_SND_PCM=y -+CONFIG_SND_HWDEP=m -+CONFIG_SND_RAWMIDI=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_PCM_OSS_PLUGINS=y -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_DYNAMIC_MINORS=y -+# CONFIG_SND_SUPPORT_OLD_API is not set -+CONFIG_SND_VERBOSE_PROCFS=y -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+ -+# -+# Generic devices -+# -+CONFIG_SND_MPU401_UART=m -+CONFIG_SND_AC97_CODEC=y -+CONFIG_SND_DUMMY=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+# CONFIG_SND_SERIAL_U16550 is not set -+CONFIG_SND_MPU401=m -+ -+# -+# PCI devices -+# -+# CONFIG_SND_AD1889 is not set -+# CONFIG_SND_ALS300 is not set -+# CONFIG_SND_ALS4000 is not set -+# CONFIG_SND_ALI5451 is not set -+# CONFIG_SND_ATIIXP is not set -+# CONFIG_SND_ATIIXP_MODEM is not set -+# CONFIG_SND_AU8810 is not set -+# CONFIG_SND_AU8820 is not set -+# CONFIG_SND_AU8830 is not set -+# CONFIG_SND_AZT3328 is not set -+# CONFIG_SND_BT87X is not set -+# CONFIG_SND_CA0106 is not set -+# CONFIG_SND_CMIPCI is not set -+# CONFIG_SND_CS4281 is not set -+# CONFIG_SND_CS46XX is not set -+CONFIG_SND_CS5535AUDIO=y -+# CONFIG_SND_DARLA20 is not set -+# CONFIG_SND_GINA20 is not set -+# CONFIG_SND_LAYLA20 is not set -+# CONFIG_SND_DARLA24 is not set -+# CONFIG_SND_GINA24 is not set -+# CONFIG_SND_LAYLA24 is not set -+# CONFIG_SND_MONA is not set -+# CONFIG_SND_MIA is not set -+# CONFIG_SND_ECHO3G is not set -+# CONFIG_SND_INDIGO is not set -+# CONFIG_SND_INDIGOIO is not set -+# CONFIG_SND_INDIGODJ is not set -+# CONFIG_SND_EMU10K1 is not set -+# CONFIG_SND_EMU10K1X is not set -+CONFIG_SND_ENS1370=m -+CONFIG_SND_ENS1371=m -+# CONFIG_SND_ES1938 is not set -+# CONFIG_SND_ES1968 is not set -+# CONFIG_SND_FM801 is not set -+# CONFIG_SND_HDA_INTEL is not set -+# CONFIG_SND_HDSP is not set -+# CONFIG_SND_HDSPM is not set -+# CONFIG_SND_ICE1712 is not set -+# CONFIG_SND_ICE1724 is not set -+CONFIG_SND_INTEL8X0=m -+# CONFIG_SND_INTEL8X0M is not set -+# CONFIG_SND_KORG1212 is not set -+# CONFIG_SND_MAESTRO3 is not set -+# CONFIG_SND_MIXART is not set -+# CONFIG_SND_NM256 is not set -+# CONFIG_SND_PCXHR is not set -+# CONFIG_SND_RIPTIDE is not set -+# CONFIG_SND_RME32 is not set -+# CONFIG_SND_RME96 is not set -+# CONFIG_SND_RME9652 is not set -+# CONFIG_SND_SONICVIBES is not set -+# CONFIG_SND_TRIDENT is not set -+# CONFIG_SND_VIA82XX is not set -+# CONFIG_SND_VIA82XX_MODEM is not set -+# CONFIG_SND_VX222 is not set -+# CONFIG_SND_YMFPCI is not set -+CONFIG_SND_AC97_POWER_SAVE=y -+ -+# -+# USB devices -+# -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_USX2Y=m -+# CONFIG_SND_USB_CAIAQ is not set -+ -+# -+# System on Chip audio support -+# -+# CONFIG_SND_SOC is not set -+ -+# -+# Open Sound System -+# -+# CONFIG_SOUND_PRIME is not set -+CONFIG_AC97_BUS=y -+ -+# -+# HID Devices -+# -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+CONFIG_USB_HIDDEV=y -+ -+# -+# USB support -+# -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+# CONFIG_USB_DEVICE_CLASS is not set -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_SUSPEND is not set -+CONFIG_USB_PERSIST=y -+# CONFIG_USB_OTG is not set -+ -+# -+# USB Host Controller Drivers -+# -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_SPLIT_ISO=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+# CONFIG_USB_EHCI_TT_NEWSCHED is not set -+# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set -+# CONFIG_USB_ISP116X_HCD is not set -+CONFIG_USB_OHCI_HCD=y -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -+CONFIG_USB_OHCI_LITTLE_ENDIAN=y -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+ -+# -+# USB Device Class drivers -+# -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+CONFIG_USB_STORAGE_DPCM=y -+CONFIG_USB_STORAGE_USBAT=y -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+CONFIG_USB_STORAGE_ALAUDA=y -+# CONFIG_USB_STORAGE_KARMA is not set -+CONFIG_USB_LIBUSUAL=y -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+CONFIG_USB_MON=y -+ -+# -+# USB port drivers -+# -+ -+# -+# USB Serial Converter support -+# -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+# CONFIG_USB_SERIAL_AIRCABLE is not set -+# CONFIG_USB_SERIAL_AIRPRIME is not set -+# CONFIG_USB_SERIAL_ARK3116 is not set -+# CONFIG_USB_SERIAL_BELKIN is not set -+# CONFIG_USB_SERIAL_WHITEHEAT is not set -+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -+CONFIG_USB_SERIAL_CP2101=m -+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -+# CONFIG_USB_SERIAL_EMPEG is not set -+CONFIG_USB_SERIAL_FTDI_SIO=m -+# CONFIG_USB_SERIAL_FUNSOFT is not set -+# CONFIG_USB_SERIAL_VISOR is not set -+# CONFIG_USB_SERIAL_IPAQ is not set -+# CONFIG_USB_SERIAL_IR is not set -+# CONFIG_USB_SERIAL_EDGEPORT is not set -+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -+# CONFIG_USB_SERIAL_GARMIN is not set -+# CONFIG_USB_SERIAL_IPW is not set -+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -+# CONFIG_USB_SERIAL_KEYSPAN is not set -+# CONFIG_USB_SERIAL_KLSI is not set -+# CONFIG_USB_SERIAL_KOBIL_SCT is not set -+# CONFIG_USB_SERIAL_MCT_U232 is not set -+# CONFIG_USB_SERIAL_MOS7720 is not set -+# CONFIG_USB_SERIAL_MOS7840 is not set -+# CONFIG_USB_SERIAL_NAVMAN is not set -+CONFIG_USB_SERIAL_PL2303=m -+# CONFIG_USB_SERIAL_HP4X is not set -+# CONFIG_USB_SERIAL_SAFE is not set -+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -+# CONFIG_USB_SERIAL_TI is not set -+# CONFIG_USB_SERIAL_CYBERJACK is not set -+# CONFIG_USB_SERIAL_XIRCOM is not set -+# CONFIG_USB_SERIAL_OPTION is not set -+# CONFIG_USB_SERIAL_OMNINET is not set -+# CONFIG_USB_SERIAL_DEBUG is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_PHIDGET is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+ -+# -+# USB DSL modem support -+# -+ -+# -+# USB Gadget Support -+# -+# CONFIG_USB_GADGET is not set -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+# CONFIG_MMC_UNSAFE_RESUME is not set -+ -+# -+# MMC/SD Card Drivers -+# -+CONFIG_MMC_BLOCK=y -+ -+# -+# MMC/SD Host Controller Drivers -+# -+CONFIG_MMC_SDHCI=y -+# CONFIG_MMC_WBSD is not set -+# CONFIG_MMC_TIFM_SD is not set -+ -+# -+# LED devices -+# -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+ -+# -+# LED drivers -+# -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+ -+# -+# InfiniBand support -+# -+# CONFIG_INFINIBAND is not set -+ -+# -+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -+# -+# CONFIG_EDAC is not set -+ -+# -+# Real Time Clock -+# -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_HCTOSYS is not set -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+ -+# -+# SPI RTC drivers -+# -+ -+# -+# Platform RTC drivers -+# -+CONFIG_RTC_DRV_CMOS=y -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+ -+# -+# DMA Engine support -+# -+# CONFIG_DMA_ENGINE is not set -+ -+# -+# DMA Clients -+# -+ -+# -+# DMA Devices -+# -+ -+# -+# Virtualization -+# -+# CONFIG_KVM is not set -+ -+# -+# Sysprof -+# -+CONFIG_SYSPROF=m -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+# CONFIG_EXT2_FS_POSIX_ACL is not set -+CONFIG_EXT2_FS_SECURITY=y -+CONFIG_EXT2_FS_XIP=y -+CONFIG_FS_XIP=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_XATTR=y -+# CONFIG_EXT3_FS_POSIX_ACL is not set -+CONFIG_EXT3_FS_SECURITY=y -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_JBD_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_ROMFS_FS is not set -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_QUOTA=y -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y -+CONFIG_DNOTIFY=y -+CONFIG_AUTOFS_FS=m -+CONFIG_AUTOFS4_FS=m -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=m -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_KCORE=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+CONFIG_HUGETLBFS=y -+CONFIG_HUGETLB_PAGE=y -+CONFIG_PROMFS_FS=y -+CONFIG_RAMFS=y -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_ECRYPT_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+CONFIG_JFFS2_FS_WBUF_VERIFY=y -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+# CONFIG_JFFS2_FS_POSIX_ACL is not set -+CONFIG_JFFS2_FS_SECURITY=y -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=m -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+ -+# -+# Network File Systems -+# -+CONFIG_NFS_FS=m -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+CONFIG_NFS_V4=y -+CONFIG_NFS_DIRECTIO=y -+# CONFIG_NFSD is not set -+CONFIG_LOCKD=m -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=m -+CONFIG_SUNRPC_GSS=m -+# CONFIG_SUNRPC_BIND34 is not set -+CONFIG_RPCSEC_GSS_KRB5=m -+CONFIG_RPCSEC_GSS_SPKM3=m -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+# CONFIG_9P_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+ -+# -+# Native Language Support -+# -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=m -+ -+# -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# -+# Instrumentation Support -+# -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y -+ -+# -+# Kernel hacking -+# -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_PRINTK_TIME=y -+# CONFIG_ENABLE_MUST_CHECK is not set -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_UNUSED_SYMBOLS=y -+CONFIG_DEBUG_FS=y -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+CONFIG_SCHEDSTATS=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_SLAB is not set -+CONFIG_DEBUG_PREEMPT=y -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+CONFIG_DEBUG_SPINLOCK=y -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+CONFIG_DEBUG_SPINLOCK_SLEEP=y -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_VM=y -+CONFIG_DEBUG_LIST=y -+# CONFIG_FRAME_POINTER is not set -+# CONFIG_FORCED_INLINING is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_LKDTM is not set -+# CONFIG_FAULT_INJECTION is not set -+CONFIG_EARLY_PRINTK=y -+CONFIG_DEBUG_STACKOVERFLOW=y -+CONFIG_DEBUG_STACK_USAGE=y -+ -+# -+# Page alloc debug is incompatible with Software Suspend on i386 -+# -+CONFIG_DEBUG_RODATA=y -+CONFIG_4KSTACKS=y -+CONFIG_DOUBLEFAULT=y -+ -+# -+# Security options -+# -+CONFIG_KEYS=y -+CONFIG_KEYS_DEBUG_PROC_KEYS=y -+CONFIG_SECURITY=y -+CONFIG_SECURITY_NETWORK=y -+CONFIG_SECURITY_NETWORK_XFRM=y -+CONFIG_SECURITY_CAPABILITIES=y -+# CONFIG_SECURITY_ROOTPLUG is not set -+CONFIG_SECURITY_SELINUX=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 -+# CONFIG_SECURITY_SELINUX_DISABLE is not set -+CONFIG_SECURITY_SELINUX_DEVELOP=y -+CONFIG_SECURITY_SELINUX_AVC_STATS=y -+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -+# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set -+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set -+ -+# -+# Cryptographic options -+# -+CONFIG_CRYPTO=y -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_NULL=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_GF128MUL=m -+CONFIG_CRYPTO_ECB=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_LRW=m -+# CONFIG_CRYPTO_CRYPTD is not set -+CONFIG_CRYPTO_DES=m -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_TWOFISH_COMMON=m -+# CONFIG_CRYPTO_TWOFISH_586 is not set -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_AES=m -+CONFIG_CRYPTO_AES_586=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_ARC4=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_DEFLATE=m -+CONFIG_CRYPTO_MICHAEL_MIC=m -+CONFIG_CRYPTO_CRC32C=m -+CONFIG_CRYPTO_CAMELLIA=m -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Hardware crypto devices -+# -+# CONFIG_CRYPTO_DEV_PADLOCK is not set -+CONFIG_CRYPTO_DEV_GEODE=y -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC16=m -+# CONFIG_CRC_ITU_T is not set -+CONFIG_CRC32=y -+CONFIG_LIBCRC32C=m -+CONFIG_AUDIT_GENERIC=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_REED_SOLOMON=y -+CONFIG_REED_SOLOMON_DEC16=y -+CONFIG_TEXTSEARCH=y -+CONFIG_TEXTSEARCH_KMP=m -+CONFIG_TEXTSEARCH_BM=m -+CONFIG_TEXTSEARCH_FSM=m -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_X86_BIOS_REBOOT=y -+CONFIG_KTIME_SCALAR=y -diff --git a/arch/i386/configs/xs_defconfig b/arch/i386/configs/xs_defconfig -new file mode 100644 -index 0000000..b937de5 ---- /dev/null -+++ b/arch/i386/configs/xs_defconfig -@@ -0,0 +1,2221 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.22-rc5 -+# Wed Jun 20 08:26:53 2007 -+# -+CONFIG_X86_32=y -+CONFIG_GENERIC_TIME=y -+CONFIG_CLOCKSOURCE_WATCHDOG=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_SEMAPHORE_SLEEPERS=y -+CONFIG_X86=y -+CONFIG_MMU=y -+CONFIG_ZONE_DMA=y -+CONFIG_QUICKLIST=y -+CONFIG_GENERIC_ISA_DMA=y -+CONFIG_GENERIC_IOMAP=y -+CONFIG_GENERIC_BUG=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_ARCH_MAY_HAVE_PC_FDC=y -+CONFIG_DMI=y -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# Code maturity level options -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+ -+# -+# General setup -+# -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+# CONFIG_IPC_NS is not set -+CONFIG_SYSVIPC_SYSCTL=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_BSD_PROCESS_ACCT=y -+# CONFIG_BSD_PROCESS_ACCT_V3 is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_UTS_NS is not set -+CONFIG_AUDIT=y -+CONFIG_AUDITSYSCALL=y -+# CONFIG_IKCONFIG is not set -+CONFIG_LOG_BUF_SHIFT=17 -+# CONFIG_SYSFS_DEPRECATED is not set -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+# CONFIG_SYSCTL_SYSCALL is not set -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+CONFIG_KALLSYMS_EXTRA_PASS=y -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+# CONFIG_BASE_FULL is not set -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=1 -+ -+# -+# Loadable module support -+# -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_KMOD=y -+ -+# -+# Block layer -+# -+CONFIG_BLOCK=y -+# CONFIG_LBD is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+# CONFIG_IOSCHED_AS is not set -+# CONFIG_IOSCHED_DEADLINE is not set -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+ -+# -+# Processor type and features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+# CONFIG_SMP is not set -+CONFIG_X86_PC=y -+# CONFIG_X86_ELAN is not set -+# CONFIG_X86_VOYAGER is not set -+# CONFIG_X86_NUMAQ is not set -+# CONFIG_X86_SUMMIT is not set -+# CONFIG_X86_BIGSMP is not set -+# CONFIG_X86_VISWS is not set -+# CONFIG_X86_GENERICARCH is not set -+# CONFIG_X86_ES7000 is not set -+# CONFIG_PARAVIRT is not set -+# CONFIG_M386 is not set -+# CONFIG_M486 is not set -+# CONFIG_M586 is not set -+# CONFIG_M586TSC is not set -+# CONFIG_M586MMX is not set -+# CONFIG_M686 is not set -+# CONFIG_MPENTIUMII is not set -+# CONFIG_MPENTIUMIII is not set -+# CONFIG_MPENTIUMM is not set -+# CONFIG_MCORE2 is not set -+# CONFIG_MPENTIUM4 is not set -+# CONFIG_MK6 is not set -+# CONFIG_MK7 is not set -+# CONFIG_MK8 is not set -+# CONFIG_MCRUSOE is not set -+# CONFIG_MEFFICEON is not set -+# CONFIG_MWINCHIPC6 is not set -+# CONFIG_MWINCHIP2 is not set -+# CONFIG_MWINCHIP3D is not set -+# CONFIG_MGEODEGX1 is not set -+CONFIG_MGEODE_LX=y -+# CONFIG_MCYRIXIII is not set -+# CONFIG_MVIAC3_2 is not set -+# CONFIG_MVIAC7 is not set -+# CONFIG_X86_GENERIC is not set -+CONFIG_X86_CMPXCHG=y -+CONFIG_X86_L1_CACHE_SHIFT=5 -+CONFIG_X86_XADD=y -+CONFIG_RWSEM_XCHGADD_ALGORITHM=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_X86_WP_WORKS_OK=y -+CONFIG_X86_INVLPG=y -+CONFIG_X86_BSWAP=y -+CONFIG_X86_POPAD_OK=y -+CONFIG_X86_CMPXCHG64=y -+CONFIG_X86_USE_PPRO_CHECKSUM=y -+CONFIG_X86_USE_3DNOW=y -+CONFIG_X86_TSC=y -+CONFIG_X86_MINIMUM_CPU_MODEL=4 -+# CONFIG_HPET_TIMER is not set -+# CONFIG_PREEMPT_NONE is not set -+# CONFIG_PREEMPT_VOLUNTARY is not set -+CONFIG_PREEMPT=y -+CONFIG_PREEMPT_BKL=y -+# CONFIG_X86_UP_APIC is not set -+# CONFIG_X86_MCE is not set -+# CONFIG_VM86 is not set -+# CONFIG_TOSHIBA is not set -+# CONFIG_I8K is not set -+CONFIG_X86_REBOOTFIXUPS=y -+# CONFIG_MICROCODE is not set -+CONFIG_X86_MSR=y -+CONFIG_X86_CPUID=m -+ -+# -+# Firmware Drivers -+# -+# CONFIG_EDD is not set -+# CONFIG_DELL_RBU is not set -+# CONFIG_DCDBAS is not set -+CONFIG_NOHIGHMEM=y -+# CONFIG_HIGHMEM4G is not set -+# CONFIG_HIGHMEM64G is not set -+CONFIG_VMSPLIT_3G=y -+# CONFIG_VMSPLIT_3G_OPT is not set -+# CONFIG_VMSPLIT_2G is not set -+# CONFIG_VMSPLIT_2G_OPT is not set -+# CONFIG_VMSPLIT_1G is not set -+CONFIG_PAGE_OFFSET=0xC0000000 -+CONFIG_ARCH_FLATMEM_ENABLE=y -+CONFIG_ARCH_SPARSEMEM_ENABLE=y -+CONFIG_ARCH_SELECT_MEMORY_MODEL=y -+CONFIG_ARCH_POPULATES_NODE_MAP=y -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_SPARSEMEM_STATIC=y -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_NR_QUICK=1 -+# CONFIG_MATH_EMULATION is not set -+# CONFIG_MTRR is not set -+# CONFIG_SECCOMP is not set -+# CONFIG_VGA_NOPROBE is not set -+CONFIG_HZ_100=y -+# CONFIG_HZ_250 is not set -+# CONFIG_HZ_300 is not set -+# CONFIG_HZ_1000 is not set -+CONFIG_HZ=100 -+CONFIG_KEXEC=y -+CONFIG_PHYSICAL_START=0x400000 -+# CONFIG_RELOCATABLE is not set -+CONFIG_PHYSICAL_ALIGN=0x100000 -+# CONFIG_COMPAT_VDSO is not set -+ -+# -+# Power management options (ACPI, APM) -+# -+CONFIG_PM=y -+CONFIG_PM_LEGACY=y -+CONFIG_PM_DEBUG=y -+# CONFIG_DISABLE_CONSOLE_SUSPEND is not set -+CONFIG_DISABLE_SUSPEND_VT_SWITCH=y -+# CONFIG_PM_TRACE is not set -+# CONFIG_PM_SYSFS_DEPRECATED is not set -+CONFIG_SOFTWARE_SUSPEND=y -+CONFIG_PM_STD_PARTITION="" -+ -+# -+# ACPI (Advanced Configuration and Power Interface) Support -+# -+# CONFIG_ACPI is not set -+# CONFIG_APM is not set -+ -+# -+# CPU Frequency scaling -+# -+# CONFIG_CPU_FREQ is not set -+ -+# -+# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -+# -+CONFIG_PCI=y -+# CONFIG_PCI_GOBIOS is not set -+# CONFIG_PCI_GOMMCONFIG is not set -+# CONFIG_PCI_GODIRECT is not set -+# CONFIG_PCI_GOANY is not set -+CONFIG_PCI_GOOLPC=y -+CONFIG_PCI_DIRECT=y -+CONFIG_PCI_OLPC=y -+# CONFIG_PCIEPORTBUS is not set -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+# CONFIG_PCI_DEBUG is not set -+CONFIG_ISA_DMA_API=y -+# CONFIG_ISA is not set -+# CONFIG_MCA is not set -+# CONFIG_SCx200 is not set -+CONFIG_GEODE_MFGPT_TIMER=y -+CONFIG_OLPC=y -+CONFIG_OLPC_PM=y -+CONFIG_OPEN_FIRMWARE=y -+ -+# -+# PCCARD (PCMCIA/CardBus) support -+# -+# CONFIG_PCCARD is not set -+# CONFIG_HOTPLUG_PCI is not set -+ -+# -+# Executable file formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+CONFIG_BINFMT_MISC=y -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+CONFIG_XFRM_USER=y -+# CONFIG_XFRM_SUB_POLICY is not set -+CONFIG_XFRM_MIGRATE=y -+CONFIG_NET_KEY=m -+CONFIG_NET_KEY_MIGRATE=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_ASK_IP_FIB_HASH=y -+# CONFIG_IP_FIB_TRIE is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set -+CONFIG_IP_ROUTE_VERBOSE=y -+# CONFIG_IP_PNP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_IP_MROUTE is not set -+# CONFIG_ARPD is not set -+CONFIG_SYN_COOKIES=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_TUNNEL=m -+CONFIG_INET_TUNNEL=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_DIAG is not set -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=y -+CONFIG_TCP_CONG_CUBIC=m -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_VEGAS=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=m -+CONFIG_TCP_CONG_ILLINOIS=m -+CONFIG_DEFAULT_BIC=y -+# CONFIG_DEFAULT_CUBIC is not set -+# CONFIG_DEFAULT_HTCP is not set -+# CONFIG_DEFAULT_VEGAS is not set -+# CONFIG_DEFAULT_WESTWOOD is not set -+# CONFIG_DEFAULT_RENO is not set -+CONFIG_DEFAULT_TCP_CONG="bic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IP_VS is not set -+CONFIG_IPV6=m -+CONFIG_IPV6_PRIVACY=y -+CONFIG_IPV6_ROUTER_PREF=y -+CONFIG_IPV6_ROUTE_INFO=y -+CONFIG_IPV6_OPTIMISTIC_DAD=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=y -+CONFIG_INET6_XFRM_TUNNEL=m -+CONFIG_INET6_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_IPV6_SIT=m -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_SUBTREES=y -+# CONFIG_NETLABEL is not set -+CONFIG_NETWORK_SECMARK=y -+CONFIG_NETFILTER=y -+# CONFIG_NETFILTER_DEBUG is not set -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_NETLINK=m -+# CONFIG_NETFILTER_NETLINK_QUEUE is not set -+# CONFIG_NETFILTER_NETLINK_LOG is not set -+CONFIG_NF_CONNTRACK_ENABLED=m -+CONFIG_NF_CONNTRACK=m -+# CONFIG_NF_CT_ACCT is not set -+# CONFIG_NF_CONNTRACK_MARK is not set -+# CONFIG_NF_CONNTRACK_SECMARK is not set -+# CONFIG_NF_CONNTRACK_EVENTS is not set -+# CONFIG_NF_CT_PROTO_SCTP is not set -+# CONFIG_NF_CONNTRACK_AMANDA is not set -+CONFIG_NF_CONNTRACK_FTP=m -+# CONFIG_NF_CONNTRACK_H323 is not set -+CONFIG_NF_CONNTRACK_IRC=m -+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -+# CONFIG_NF_CONNTRACK_PPTP is not set -+# CONFIG_NF_CONNTRACK_SANE is not set -+# CONFIG_NF_CONNTRACK_SIP is not set -+# CONFIG_NF_CONNTRACK_TFTP is not set -+# CONFIG_NF_CT_NETLINK is not set -+CONFIG_NETFILTER_XTABLES=m -+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -+# CONFIG_NETFILTER_XT_TARGET_MARK is not set -+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set -+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set -+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set -+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -+# CONFIG_NETFILTER_XT_MATCH_ESP is not set -+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set -+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set -+# CONFIG_NETFILTER_XT_MATCH_MAC is not set -+# CONFIG_NETFILTER_XT_MATCH_MARK is not set -+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set -+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -+# CONFIG_NETFILTER_XT_MATCH_REALM is not set -+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -+# CONFIG_NETFILTER_XT_MATCH_STRING is not set -+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -+ -+# -+# IP: Netfilter Configuration -+# -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+# CONFIG_IP_NF_QUEUE is not set -+CONFIG_IP_NF_IPTABLES=m -+# CONFIG_IP_NF_MATCH_IPRANGE is not set -+# CONFIG_IP_NF_MATCH_TOS is not set -+# CONFIG_IP_NF_MATCH_RECENT is not set -+# CONFIG_IP_NF_MATCH_ECN is not set -+# CONFIG_IP_NF_MATCH_AH is not set -+# CONFIG_IP_NF_MATCH_TTL is not set -+# CONFIG_IP_NF_MATCH_OWNER is not set -+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -+CONFIG_IP_NF_FILTER=m -+# CONFIG_IP_NF_TARGET_REJECT is not set -+CONFIG_IP_NF_TARGET_LOG=m -+# CONFIG_IP_NF_TARGET_ULOG is not set -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+# CONFIG_IP_NF_TARGET_REDIRECT is not set -+# CONFIG_IP_NF_TARGET_NETMAP is not set -+# CONFIG_IP_NF_TARGET_SAME is not set -+# CONFIG_NF_NAT_SNMP_BASIC is not set -+CONFIG_NF_NAT_FTP=m -+CONFIG_NF_NAT_IRC=m -+# CONFIG_NF_NAT_TFTP is not set -+# CONFIG_NF_NAT_AMANDA is not set -+# CONFIG_NF_NAT_PPTP is not set -+# CONFIG_NF_NAT_H323 is not set -+# CONFIG_NF_NAT_SIP is not set -+# CONFIG_IP_NF_MANGLE is not set -+# CONFIG_IP_NF_RAW is not set -+# CONFIG_IP_NF_ARPTABLES is not set -+ -+# -+# IPv6: Netfilter Configuration (EXPERIMENTAL) -+# -+# CONFIG_NF_CONNTRACK_IPV6 is not set -+# CONFIG_IP6_NF_QUEUE is not set -+# CONFIG_IP6_NF_IPTABLES is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+ -+# -+# QoS and/or fair queueing -+# -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_FIFO=y -+ -+# -+# Queueing/Scheduling -+# -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_INGRESS=m -+ -+# -+# Classification -+# -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_ROUTE=y -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_STACK=32 -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+# CONFIG_NET_ACT_IPT is not set -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_ESTIMATOR=y -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_NET_TCPPROBE is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+CONFIG_FIB_RULES=y -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+CONFIG_WIRELESS_EXT=y -+# CONFIG_MAC80211 is not set -+CONFIG_IEEE80211=m -+# CONFIG_IEEE80211_DEBUG is not set -+CONFIG_IEEE80211_CRYPT_WEP=m -+CONFIG_IEEE80211_CRYPT_CCMP=m -+CONFIG_IEEE80211_CRYPT_TKIP=m -+CONFIG_IEEE80211_SOFTMAC=m -+CONFIG_IEEE80211_SOFTMAC_DEBUG=y -+# CONFIG_RFKILL is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+ -+# -+# Connector - unified userspace <-> kernelspace linker -+# -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+CONFIG_MTD_CONCAT=m -+CONFIG_MTD_PARTITIONS=y -+CONFIG_MTD_REDBOOT_PARTS=m -+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=m -+CONFIG_MTD_BLKDEVS=m -+CONFIG_MTD_BLOCK=m -+CONFIG_MTD_BLOCK_RO=m -+CONFIG_FTL=m -+CONFIG_NFTL=m -+CONFIG_NFTL_RW=y -+CONFIG_INFTL=m -+CONFIG_RFD_FTL=m -+# CONFIG_SSFDC is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=m -+CONFIG_MTD_JEDECPROBE=m -+CONFIG_MTD_GEN_PROBE=m -+# CONFIG_MTD_CFI_ADV_OPTIONS is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+CONFIG_MTD_CFI_INTELEXT=m -+CONFIG_MTD_CFI_AMDSTD=m -+CONFIG_MTD_CFI_STAA=m -+CONFIG_MTD_CFI_UTIL=m -+CONFIG_MTD_RAM=m -+CONFIG_MTD_ROM=m -+CONFIG_MTD_ABSENT=m -+ -+# -+# Mapping drivers for chip access -+# -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+# CONFIG_MTD_PHYSMAP is not set -+# CONFIG_MTD_PNC2000 is not set -+CONFIG_MTD_SC520CDP=m -+CONFIG_MTD_NETSC520=m -+CONFIG_MTD_TS5500=m -+# CONFIG_MTD_SBC_GXX is not set -+# CONFIG_MTD_AMD76XROM is not set -+# CONFIG_MTD_ICHXROM is not set -+# CONFIG_MTD_ESB2ROM is not set -+# CONFIG_MTD_CK804XROM is not set -+CONFIG_MTD_SCB2_FLASH=m -+# CONFIG_MTD_NETtel is not set -+# CONFIG_MTD_DILNETPC is not set -+# CONFIG_MTD_L440GX is not set -+CONFIG_MTD_PCI=m -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+CONFIG_MTD_PMC551=m -+# CONFIG_MTD_PMC551_BUGFIX is not set -+# CONFIG_MTD_PMC551_DEBUG is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+CONFIG_MTD_MTDRAM=m -+CONFIG_MTDRAM_TOTAL_SIZE=4096 -+CONFIG_MTDRAM_ERASE_SIZE=128 -+CONFIG_MTD_BLOCK2MTD=m -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+CONFIG_MTD_NAND_IDS=y -+CONFIG_MTD_NAND_DISKONCHIP=m -+# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set -+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 -+# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set -+CONFIG_MTD_NAND_CAFE=y -+CONFIG_MTD_NAND_CS553X=y -+CONFIG_MTD_NAND_NANDSIM=m -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+ -+# -+# Parallel port support -+# -+# CONFIG_PARPORT is not set -+ -+# -+# Plug and Play support -+# -+# CONFIG_PNPACPI is not set -+ -+# -+# Block devices -+# -+# CONFIG_BLK_DEV_FD is not set -+# CONFIG_BLK_CPQ_DA is not set -+# CONFIG_BLK_CPQ_CISS_DA is not set -+# CONFIG_BLK_DEV_DAC960 is not set -+# CONFIG_BLK_DEV_UMEM is not set -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=m -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_NBD=m -+# CONFIG_BLK_DEV_SX8 is not set -+CONFIG_BLK_DEV_UB=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=16384 -+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+ -+# -+# Misc devices -+# -+# CONFIG_IBM_ASM is not set -+# CONFIG_PHANTOM is not set -+# CONFIG_SGI_IOC4 is not set -+# CONFIG_TIFM_CORE is not set -+# CONFIG_BLINK is not set -+# CONFIG_EEPROM_93CX6 is not set -+CONFIG_IDE=m -+CONFIG_IDE_MAX_HWIFS=4 -+CONFIG_BLK_DEV_IDE=m -+ -+# -+# Please see Documentation/ide.txt for help/info on IDE drives -+# -+# CONFIG_BLK_DEV_IDE_SATA is not set -+# CONFIG_BLK_DEV_HD_IDE is not set -+CONFIG_BLK_DEV_IDEDISK=m -+CONFIG_IDEDISK_MULTI_MODE=y -+# CONFIG_BLK_DEV_IDECD is not set -+# CONFIG_BLK_DEV_IDETAPE is not set -+# CONFIG_BLK_DEV_IDEFLOPPY is not set -+# CONFIG_BLK_DEV_IDESCSI is not set -+CONFIG_IDE_TASK_IOCTL=y -+# CONFIG_IDE_PROC_FS is not set -+ -+# -+# IDE chipset support/bugfixes -+# -+CONFIG_IDE_GENERIC=m -+# CONFIG_BLK_DEV_CMD640 is not set -+CONFIG_BLK_DEV_IDEPCI=y -+CONFIG_IDEPCI_SHARE_IRQ=y -+# CONFIG_IDEPCI_PCIBUS_ORDER is not set -+# CONFIG_BLK_DEV_OFFBOARD is not set -+# CONFIG_BLK_DEV_GENERIC is not set -+# CONFIG_BLK_DEV_OPTI621 is not set -+# CONFIG_BLK_DEV_RZ1000 is not set -+CONFIG_BLK_DEV_IDEDMA_PCI=y -+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -+CONFIG_IDEDMA_ONLYDISK=y -+# CONFIG_BLK_DEV_AEC62XX is not set -+# CONFIG_BLK_DEV_ALI15X3 is not set -+# CONFIG_BLK_DEV_AMD74XX is not set -+# CONFIG_BLK_DEV_ATIIXP is not set -+# CONFIG_BLK_DEV_CMD64X is not set -+# CONFIG_BLK_DEV_TRIFLEX is not set -+# CONFIG_BLK_DEV_CY82C693 is not set -+# CONFIG_BLK_DEV_CS5520 is not set -+# CONFIG_BLK_DEV_CS5530 is not set -+# CONFIG_BLK_DEV_CS5535 is not set -+# CONFIG_BLK_DEV_HPT34X is not set -+# CONFIG_BLK_DEV_HPT366 is not set -+# CONFIG_BLK_DEV_JMICRON is not set -+# CONFIG_BLK_DEV_SC1200 is not set -+CONFIG_BLK_DEV_PIIX=m -+# CONFIG_BLK_DEV_IT8213 is not set -+# CONFIG_BLK_DEV_IT821X is not set -+# CONFIG_BLK_DEV_NS87415 is not set -+# CONFIG_BLK_DEV_PDC202XX_OLD is not set -+# CONFIG_BLK_DEV_PDC202XX_NEW is not set -+# CONFIG_BLK_DEV_SVWKS is not set -+# CONFIG_BLK_DEV_SIIMAGE is not set -+# CONFIG_BLK_DEV_SIS5513 is not set -+# CONFIG_BLK_DEV_SLC90E66 is not set -+# CONFIG_BLK_DEV_TRM290 is not set -+# CONFIG_BLK_DEV_VIA82CXXX is not set -+# CONFIG_BLK_DEV_TC86C001 is not set -+# CONFIG_IDE_ARM is not set -+CONFIG_BLK_DEV_IDEDMA=y -+# CONFIG_IDEDMA_IVB is not set -+# CONFIG_BLK_DEV_HD is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=m -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=m -+CONFIG_CHR_DEV_SCH=m -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+ -+# -+# SCSI low-level drivers -+# -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC7XXX_OLD is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_DPT_I2O is not set -+# CONFIG_SCSI_ADVANSYS is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_HPTIOP is not set -+# CONFIG_SCSI_BUSLOGIC is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_EATA is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+# CONFIG_SCSI_GDTH is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_FC is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_LPFC is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_DC390T is not set -+# CONFIG_SCSI_NSP32 is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_SRP is not set -+# CONFIG_ATA is not set -+ -+# -+# Multi-device support (RAID and LVM) -+# -+# CONFIG_MD is not set -+ -+# -+# Fusion MPT device support -+# -+# CONFIG_FUSION is not set -+# CONFIG_FUSION_SPI is not set -+# CONFIG_FUSION_FC is not set -+# CONFIG_FUSION_SAS is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_IEEE1394 is not set -+ -+# -+# I2O device support -+# -+# CONFIG_I2O is not set -+ -+# -+# Battery support -+# -+# CONFIG_BATTERY_CLASS is not set -+# CONFIG_MACINTOSH_DRIVERS is not set -+ -+# -+# Network device support -+# -+CONFIG_NETDEVICES=y -+CONFIG_IFB=m -+CONFIG_DUMMY=m -+# CONFIG_BONDING is not set -+# CONFIG_EQUALIZER is not set -+CONFIG_TUN=m -+# CONFIG_ARCNET is not set -+# CONFIG_PHYLIB is not set -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=m -+# CONFIG_HAPPYMEAL is not set -+# CONFIG_SUNGEM is not set -+# CONFIG_CASSINI is not set -+# CONFIG_NET_VENDOR_3COM is not set -+ -+# -+# Tulip family network device support -+# -+# CONFIG_NET_TULIP is not set -+# CONFIG_HP100 is not set -+CONFIG_NET_PCI=y -+# CONFIG_PCNET32 is not set -+# CONFIG_AMD8111_ETH is not set -+# CONFIG_ADAPTEC_STARFIRE is not set -+# CONFIG_B44 is not set -+# CONFIG_FORCEDETH is not set -+# CONFIG_DGRS is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_E100 is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NATSEMI is not set -+CONFIG_NE2K_PCI=m -+# CONFIG_8139CP is not set -+# CONFIG_8139TOO is not set -+# CONFIG_SIS900 is not set -+# CONFIG_EPIC100 is not set -+# CONFIG_SUNDANCE is not set -+# CONFIG_TLAN is not set -+# CONFIG_VIA_RHINE is not set -+# CONFIG_SC92031 is not set -+CONFIG_NETDEV_1000=y -+# CONFIG_ACENIC is not set -+# CONFIG_DL2K is not set -+# CONFIG_E1000 is not set -+# CONFIG_NS83820 is not set -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+# CONFIG_R8169 is not set -+# CONFIG_SIS190 is not set -+# CONFIG_SKGE is not set -+# CONFIG_SKY2 is not set -+# CONFIG_SK98LIN is not set -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_TIGON3 is not set -+# CONFIG_BNX2 is not set -+# CONFIG_QLA3XXX is not set -+# CONFIG_ATL1 is not set -+CONFIG_NETDEV_10000=y -+# CONFIG_CHELSIO_T1 is not set -+# CONFIG_CHELSIO_T3 is not set -+# CONFIG_IXGB is not set -+# CONFIG_S2IO is not set -+# CONFIG_MYRI10GE is not set -+# CONFIG_NETXEN_NIC is not set -+# CONFIG_MLX4_CORE is not set -+# CONFIG_TR is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+CONFIG_WLAN_80211=y -+# CONFIG_IPW2100 is not set -+# CONFIG_IPW2200 is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_DEBUG=y -+# CONFIG_AIRO is not set -+# CONFIG_HERMES is not set -+# CONFIG_ATMEL is not set -+# CONFIG_PRISM54 is not set -+# CONFIG_USB_ZD1201 is not set -+# CONFIG_PRISM54_USB is not set -+# CONFIG_HOSTAP is not set -+# CONFIG_BCM43XX is not set -+# CONFIG_ZD1211RW is not set -+# CONFIG_ADM8211 is not set -+# CONFIG_ACX_PCI is not set -+# CONFIG_ACX_USB is not set -+ -+# -+# USB Network Adapters -+# -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_USBNET_MII=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_RNDIS_HOST=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+CONFIG_USB_EPSON2888=y -+# CONFIG_USB_KC2190 is not set -+CONFIG_USB_NET_ZAURUS=m -+# CONFIG_WAN is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+CONFIG_PPP=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+# CONFIG_PPP_BSDCOMP is not set -+CONFIG_PPP_MPPE=m -+CONFIG_PPPOE=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLHC=m -+CONFIG_SLIP_SMART=y -+# CONFIG_SLIP_MODE_SLIP6 is not set -+# CONFIG_NET_FC is not set -+# CONFIG_SHAPER is not set -+CONFIG_NETCONSOLE=m -+CONFIG_NETPOLL=y -+CONFIG_NETPOLL_TRAP=y -+CONFIG_NET_POLL_CONTROLLER=y -+ -+# -+# ISDN subsystem -+# -+# CONFIG_ISDN is not set -+ -+# -+# Telephony Support -+# -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+CONFIG_INPUT_JOYDEV=m -+# CONFIG_INPUT_TSDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+CONFIG_KEYBOARD_ATKBD=y -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+CONFIG_INPUT_MOUSE=y -+CONFIG_MOUSE_PS2=m -+# CONFIG_MOUSE_PS2_ALPS is not set -+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -+# CONFIG_MOUSE_PS2_SYNAPTICS is not set -+# CONFIG_MOUSE_PS2_LIFEBOOK is not set -+# CONFIG_MOUSE_PS2_TRACKPOINT is not set -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+CONFIG_MOUSE_PS2_OLPC=y -+# CONFIG_MOUSE_SERIAL is not set -+# CONFIG_MOUSE_APPLETOUCH is not set -+# CONFIG_MOUSE_VSXXXAA is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PCSPKR=m -+# CONFIG_INPUT_WISTRON_BTNS is not set -+# CONFIG_INPUT_ATI_REMOTE is not set -+# CONFIG_INPUT_ATI_REMOTE2 is not set -+# CONFIG_INPUT_KEYSPAN_REMOTE is not set -+# CONFIG_INPUT_POWERMATE is not set -+# CONFIG_INPUT_YEALINK is not set -+CONFIG_INPUT_UINPUT=m -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_I8042=y -+CONFIG_SERIO_SERPORT=y -+# CONFIG_SERIO_CT82C710 is not set -+# CONFIG_SERIO_PCIPS2 is not set -+CONFIG_SERIO_LIBPS2=y -+CONFIG_SERIO_RAW=m -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_PCI=y -+CONFIG_SERIAL_8250_NR_UARTS=1 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DETECT_IRQ=y -+CONFIG_SERIAL_8250_RSA=y -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+CONFIG_UNIX98_PTYS=y -+# CONFIG_LEGACY_PTYS is not set -+ -+# -+# IPMI -+# -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_WATCHDOG=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+ -+# -+# Watchdog Device Drivers -+# -+CONFIG_SOFT_WATCHDOG=m -+# CONFIG_ACQUIRE_WDT is not set -+# CONFIG_ADVANTECH_WDT is not set -+# CONFIG_ALIM1535_WDT is not set -+# CONFIG_ALIM7101_WDT is not set -+# CONFIG_SC520_WDT is not set -+# CONFIG_EUROTECH_WDT is not set -+# CONFIG_IB700_WDT is not set -+# CONFIG_IBMASR is not set -+# CONFIG_WAFER_WDT is not set -+# CONFIG_I6300ESB_WDT is not set -+# CONFIG_ITCO_WDT is not set -+# CONFIG_SC1200_WDT is not set -+# CONFIG_PC87413_WDT is not set -+# CONFIG_60XX_WDT is not set -+# CONFIG_SBC8360_WDT is not set -+# CONFIG_CPU5_WDT is not set -+# CONFIG_SMSC37B787_WDT is not set -+# CONFIG_W83627HF_WDT is not set -+# CONFIG_W83697HF_WDT is not set -+# CONFIG_W83877F_WDT is not set -+# CONFIG_W83977F_WDT is not set -+# CONFIG_MACHZ_WDT is not set -+# CONFIG_SBC_EPX_C3_WATCHDOG is not set -+ -+# -+# PCI-based Watchdog Cards -+# -+# CONFIG_PCIPCWATCHDOG is not set -+# CONFIG_WDTPCI is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_HW_RANDOM=y -+# CONFIG_HW_RANDOM_INTEL is not set -+# CONFIG_HW_RANDOM_AMD is not set -+CONFIG_HW_RANDOM_GEODE=y -+# CONFIG_HW_RANDOM_VIA is not set -+CONFIG_NVRAM=y -+# CONFIG_RTC is not set -+# CONFIG_GEN_RTC is not set -+# CONFIG_R3964 is not set -+# CONFIG_APPLICOM is not set -+# CONFIG_SONYPI is not set -+# CONFIG_AGP is not set -+# CONFIG_DRM is not set -+# CONFIG_MWAVE is not set -+# CONFIG_PC8736x_GPIO is not set -+# CONFIG_NSC_GPIO is not set -+CONFIG_CS5535_GPIO=m -+# CONFIG_RAW_DRIVER is not set -+CONFIG_HANGCHECK_TIMER=m -+ -+# -+# TPM devices -+# -+# CONFIG_TCG_TPM is not set -+# CONFIG_TELCLOCK is not set -+CONFIG_DEVPORT=y -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_CHARDEV=m -+ -+# -+# I2C Algorithms -+# -+# CONFIG_I2C_ALGOBIT is not set -+# CONFIG_I2C_ALGOPCF is not set -+# CONFIG_I2C_ALGOPCA is not set -+ -+# -+# I2C Hardware Bus support -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_I810 is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_OCORES is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_PROSAVAGE is not set -+# CONFIG_I2C_SAVAGE4 is not set -+# CONFIG_I2C_SIMTEC is not set -+CONFIG_SCx200_ACB=y -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_STUB is not set -+# CONFIG_I2C_TINY_USB is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+# CONFIG_I2C_VOODOO3 is not set -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_SENSORS_DS1337 is not set -+# CONFIG_SENSORS_DS1374 is not set -+# CONFIG_SENSORS_EEPROM is not set -+# CONFIG_SENSORS_PCF8574 is not set -+# CONFIG_SENSORS_PCA9539 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_MAX6875 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+ -+# -+# SPI support -+# -+# CONFIG_SPI is not set -+# CONFIG_SPI_MASTER is not set -+ -+# -+# Dallas's 1-wire bus -+# -+# CONFIG_W1 is not set -+CONFIG_POWER_SUPPLY=m -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+# CONFIG_PDA_POWER is not set -+# CONFIG_BATTERY_DS2760 is not set -+CONFIG_BATTERY_OLPC=m -+# CONFIG_HWMON is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+ -+# -+# Multimedia devices -+# -+CONFIG_VIDEO_DEV=m -+# CONFIG_VIDEO_V4L1 is not set -+CONFIG_VIDEO_V4L1_COMPAT=y -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_CAPTURE_DRIVERS=y -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -+ -+# -+# Encoders/decoders and other helper chips -+# -+ -+# -+# Audio decoders -+# -+# CONFIG_VIDEO_TDA9840 is not set -+# CONFIG_VIDEO_TEA6415C is not set -+# CONFIG_VIDEO_TEA6420 is not set -+# CONFIG_VIDEO_MSP3400 is not set -+# CONFIG_VIDEO_CS53L32A is not set -+# CONFIG_VIDEO_TLV320AIC23B is not set -+# CONFIG_VIDEO_WM8775 is not set -+# CONFIG_VIDEO_WM8739 is not set -+ -+# -+# Video decoders -+# -+CONFIG_VIDEO_OV7670=m -+# CONFIG_VIDEO_SAA711X is not set -+# CONFIG_VIDEO_TVP5150 is not set -+ -+# -+# Video and audio decoders -+# -+# CONFIG_VIDEO_CX25840 is not set -+ -+# -+# MPEG video encoders -+# -+# CONFIG_VIDEO_CX2341X is not set -+ -+# -+# Video encoders -+# -+# CONFIG_VIDEO_SAA7127 is not set -+ -+# -+# Video improvement chips -+# -+# CONFIG_VIDEO_UPD64031A is not set -+# CONFIG_VIDEO_UPD64083 is not set -+# CONFIG_VIDEO_VIVI is not set -+# CONFIG_VIDEO_SAA5246A is not set -+# CONFIG_VIDEO_SAA5249 is not set -+# CONFIG_VIDEO_SAA7134 is not set -+# CONFIG_VIDEO_HEXIUM_ORION is not set -+# CONFIG_VIDEO_HEXIUM_GEMINI is not set -+# CONFIG_VIDEO_CX88 is not set -+CONFIG_VIDEO_CAFE_CCIC=m -+CONFIG_V4L_USB_DRIVERS=y -+# CONFIG_VIDEO_PVRUSB2 is not set -+# CONFIG_VIDEO_USBVISION is not set -+# CONFIG_USB_SN9C102 is not set -+# CONFIG_USB_ZR364XX is not set -+CONFIG_RADIO_ADAPTERS=y -+# CONFIG_RADIO_GEMTEK_PCI is not set -+# CONFIG_RADIO_MAXIRADIO is not set -+# CONFIG_RADIO_MAESTRO is not set -+# CONFIG_USB_DSBR is not set -+# CONFIG_DVB_CORE is not set -+CONFIG_DAB=y -+# CONFIG_USB_DABUSB is not set -+ -+# -+# Graphics support -+# -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_LCD_CLASS_DEVICE=y -+# CONFIG_BACKLIGHT_PROGEAR is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+CONFIG_VGASTATE=m -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_SYS_FILLRECT is not set -+# CONFIG_FB_SYS_COPYAREA is not set -+# CONFIG_FB_SYS_IMAGEBLIT is not set -+# CONFIG_FB_SYS_FOPS is not set -+CONFIG_FB_DEFERRED_IO=y -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+CONFIG_FB_MODE_HELPERS=y -+CONFIG_FB_TILEBLITTING=y -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_CIRRUS is not set -+# CONFIG_FB_PM2 is not set -+# CONFIG_FB_CYBER2000 is not set -+# CONFIG_FB_ARC is not set -+# CONFIG_FB_ASILIANT is not set -+# CONFIG_FB_IMSTT is not set -+CONFIG_FB_VGA16=m -+CONFIG_FB_VESA=y -+# CONFIG_FB_HECUBA is not set -+# CONFIG_FB_HGA is not set -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_NVIDIA is not set -+# CONFIG_FB_RIVA is not set -+# CONFIG_FB_I810 is not set -+# CONFIG_FB_LE80578 is not set -+# CONFIG_FB_INTEL is not set -+# CONFIG_FB_MATROX is not set -+# CONFIG_FB_RADEON is not set -+# CONFIG_FB_ATY128 is not set -+# CONFIG_FB_ATY is not set -+# CONFIG_FB_S3 is not set -+# CONFIG_FB_SAVAGE is not set -+# CONFIG_FB_SIS is not set -+# CONFIG_FB_NEOMAGIC is not set -+# CONFIG_FB_KYRO is not set -+# CONFIG_FB_3DFX is not set -+# CONFIG_FB_VOODOO1 is not set -+# CONFIG_FB_VT8623 is not set -+# CONFIG_FB_CYBLA is not set -+# CONFIG_FB_TRIDENT is not set -+# CONFIG_FB_ARK is not set -+# CONFIG_FB_PM3 is not set -+CONFIG_FB_GEODE=y -+CONFIG_FB_GEODE_LX=y -+CONFIG_FB_GEODE_GX=y -+# CONFIG_FB_GEODE_GX1 is not set -+CONFIG_FB_OLPC_DCON=y -+# CONFIG_FB_VIRTUAL is not set -+ -+# -+# Console display driver support -+# -+CONFIG_VGA_CONSOLE=y -+CONFIG_VGACON_SOFT_SCROLLBACK=y -+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -+CONFIG_VIDEO_SELECT=y -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -+CONFIG_FONTS=y -+# CONFIG_FONT_8x8 is not set -+CONFIG_FONT_8x16=y -+# CONFIG_FONT_6x11 is not set -+# CONFIG_FONT_7x14 is not set -+# CONFIG_FONT_PEARL_8x8 is not set -+# CONFIG_FONT_ACORN_8x8 is not set -+# CONFIG_FONT_MINI_4x6 is not set -+# CONFIG_FONT_SUN8x16 is not set -+CONFIG_FONT_SUN12x22=y -+# CONFIG_FONT_10x18 is not set -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_LOGO_LINUX_CLUT224=y -+ -+# -+# Sound -+# -+CONFIG_SOUND=m -+ -+# -+# Advanced Linux Sound Architecture -+# -+CONFIG_SND=m -+CONFIG_SND_TIMER=m -+CONFIG_SND_PCM=m -+CONFIG_SND_HWDEP=m -+CONFIG_SND_RAWMIDI=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_PCM_OSS_PLUGINS=y -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_DYNAMIC_MINORS=y -+# CONFIG_SND_SUPPORT_OLD_API is not set -+CONFIG_SND_VERBOSE_PROCFS=y -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+ -+# -+# Generic devices -+# -+CONFIG_SND_MPU401_UART=m -+CONFIG_SND_AC97_CODEC=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+# CONFIG_SND_SERIAL_U16550 is not set -+CONFIG_SND_MPU401=m -+ -+# -+# PCI devices -+# -+# CONFIG_SND_AD1889 is not set -+# CONFIG_SND_ALS300 is not set -+# CONFIG_SND_ALS4000 is not set -+# CONFIG_SND_ALI5451 is not set -+# CONFIG_SND_ATIIXP is not set -+# CONFIG_SND_ATIIXP_MODEM is not set -+# CONFIG_SND_AU8810 is not set -+# CONFIG_SND_AU8820 is not set -+# CONFIG_SND_AU8830 is not set -+# CONFIG_SND_AZT3328 is not set -+# CONFIG_SND_BT87X is not set -+# CONFIG_SND_CA0106 is not set -+# CONFIG_SND_CMIPCI is not set -+# CONFIG_SND_CS4281 is not set -+# CONFIG_SND_CS46XX is not set -+CONFIG_SND_CS5535AUDIO=m -+# CONFIG_SND_DARLA20 is not set -+# CONFIG_SND_GINA20 is not set -+# CONFIG_SND_LAYLA20 is not set -+# CONFIG_SND_DARLA24 is not set -+# CONFIG_SND_GINA24 is not set -+# CONFIG_SND_LAYLA24 is not set -+# CONFIG_SND_MONA is not set -+# CONFIG_SND_MIA is not set -+# CONFIG_SND_ECHO3G is not set -+# CONFIG_SND_INDIGO is not set -+# CONFIG_SND_INDIGOIO is not set -+# CONFIG_SND_INDIGODJ is not set -+# CONFIG_SND_EMU10K1 is not set -+# CONFIG_SND_EMU10K1X is not set -+CONFIG_SND_ENS1370=m -+# CONFIG_SND_ENS1371 is not set -+# CONFIG_SND_ES1938 is not set -+# CONFIG_SND_ES1968 is not set -+# CONFIG_SND_FM801 is not set -+# CONFIG_SND_HDA_INTEL is not set -+# CONFIG_SND_HDSP is not set -+# CONFIG_SND_HDSPM is not set -+# CONFIG_SND_ICE1712 is not set -+# CONFIG_SND_ICE1724 is not set -+# CONFIG_SND_INTEL8X0 is not set -+# CONFIG_SND_INTEL8X0M is not set -+# CONFIG_SND_KORG1212 is not set -+# CONFIG_SND_MAESTRO3 is not set -+# CONFIG_SND_MIXART is not set -+# CONFIG_SND_NM256 is not set -+# CONFIG_SND_PCXHR is not set -+# CONFIG_SND_RIPTIDE is not set -+# CONFIG_SND_RME32 is not set -+# CONFIG_SND_RME96 is not set -+# CONFIG_SND_RME9652 is not set -+# CONFIG_SND_SONICVIBES is not set -+# CONFIG_SND_TRIDENT is not set -+# CONFIG_SND_VIA82XX is not set -+# CONFIG_SND_VIA82XX_MODEM is not set -+# CONFIG_SND_VX222 is not set -+# CONFIG_SND_YMFPCI is not set -+CONFIG_SND_AC97_POWER_SAVE=y -+ -+# -+# USB devices -+# -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_USX2Y=m -+# CONFIG_SND_USB_CAIAQ is not set -+ -+# -+# System on Chip audio support -+# -+# CONFIG_SND_SOC is not set -+ -+# -+# Open Sound System -+# -+# CONFIG_SOUND_PRIME is not set -+CONFIG_AC97_BUS=m -+ -+# -+# HID Devices -+# -+CONFIG_HID=y -+# CONFIG_HID_DEBUG is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_USB_HIDINPUT_POWERBOOK is not set -+# CONFIG_HID_FF is not set -+CONFIG_USB_HIDDEV=y -+ -+# -+# USB support -+# -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+# CONFIG_USB_DEVICE_CLASS is not set -+# CONFIG_USB_DYNAMIC_MINORS is not set -+# CONFIG_USB_SUSPEND is not set -+CONFIG_USB_PERSIST=y -+# CONFIG_USB_OTG is not set -+ -+# -+# USB Host Controller Drivers -+# -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_SPLIT_ISO=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+# CONFIG_USB_EHCI_TT_NEWSCHED is not set -+# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set -+# CONFIG_USB_ISP116X_HCD is not set -+CONFIG_USB_OHCI_HCD=y -+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -+CONFIG_USB_OHCI_LITTLE_ENDIAN=y -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+ -+# -+# USB Device Class drivers -+# -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+ -+# -+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# -+ -+# -+# may also be needed; see USB_STORAGE Help for more information -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+CONFIG_USB_STORAGE_DPCM=y -+CONFIG_USB_STORAGE_USBAT=y -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+CONFIG_USB_STORAGE_ALAUDA=y -+# CONFIG_USB_STORAGE_KARMA is not set -+CONFIG_USB_LIBUSUAL=y -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+CONFIG_USB_MON=y -+ -+# -+# USB port drivers -+# -+ -+# -+# USB Serial Converter support -+# -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+# CONFIG_USB_SERIAL_AIRCABLE is not set -+# CONFIG_USB_SERIAL_AIRPRIME is not set -+# CONFIG_USB_SERIAL_ARK3116 is not set -+# CONFIG_USB_SERIAL_BELKIN is not set -+# CONFIG_USB_SERIAL_WHITEHEAT is not set -+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -+CONFIG_USB_SERIAL_CP2101=m -+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -+# CONFIG_USB_SERIAL_EMPEG is not set -+# CONFIG_USB_SERIAL_FTDI_SIO is not set -+# CONFIG_USB_SERIAL_FUNSOFT is not set -+# CONFIG_USB_SERIAL_VISOR is not set -+# CONFIG_USB_SERIAL_IPAQ is not set -+# CONFIG_USB_SERIAL_IR is not set -+# CONFIG_USB_SERIAL_EDGEPORT is not set -+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -+# CONFIG_USB_SERIAL_GARMIN is not set -+# CONFIG_USB_SERIAL_IPW is not set -+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -+# CONFIG_USB_SERIAL_KEYSPAN is not set -+# CONFIG_USB_SERIAL_KLSI is not set -+# CONFIG_USB_SERIAL_KOBIL_SCT is not set -+# CONFIG_USB_SERIAL_MCT_U232 is not set -+# CONFIG_USB_SERIAL_MOS7720 is not set -+# CONFIG_USB_SERIAL_MOS7840 is not set -+# CONFIG_USB_SERIAL_NAVMAN is not set -+CONFIG_USB_SERIAL_PL2303=m -+# CONFIG_USB_SERIAL_HP4X is not set -+# CONFIG_USB_SERIAL_SAFE is not set -+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -+# CONFIG_USB_SERIAL_TI is not set -+# CONFIG_USB_SERIAL_CYBERJACK is not set -+# CONFIG_USB_SERIAL_XIRCOM is not set -+# CONFIG_USB_SERIAL_OPTION is not set -+# CONFIG_USB_SERIAL_OMNINET is not set -+# CONFIG_USB_SERIAL_DEBUG is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_AUERSWALD is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_PHIDGET is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+ -+# -+# USB DSL modem support -+# -+ -+# -+# USB Gadget Support -+# -+# CONFIG_USB_GADGET is not set -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+# CONFIG_MMC_UNSAFE_RESUME is not set -+ -+# -+# MMC/SD Card Drivers -+# -+CONFIG_MMC_BLOCK=y -+ -+# -+# MMC/SD Host Controller Drivers -+# -+CONFIG_MMC_SDHCI=y -+# CONFIG_MMC_WBSD is not set -+# CONFIG_MMC_TIFM_SD is not set -+ -+# -+# LED devices -+# -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+ -+# -+# LED drivers -+# -+CONFIG_LEDS_OLPC=y -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+ -+# -+# InfiniBand support -+# -+# CONFIG_INFINIBAND is not set -+ -+# -+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -+# -+# CONFIG_EDAC is not set -+ -+# -+# Real Time Clock -+# -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_HCTOSYS is not set -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+ -+# -+# SPI RTC drivers -+# -+ -+# -+# Platform RTC drivers -+# -+CONFIG_RTC_DRV_CMOS=y -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+ -+# -+# DMA Engine support -+# -+# CONFIG_DMA_ENGINE is not set -+ -+# -+# DMA Clients -+# -+ -+# -+# DMA Devices -+# -+ -+# -+# Virtualization -+# -+# CONFIG_KVM is not set -+ -+# -+# Sysprof -+# -+CONFIG_SYSPROF=m -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT2_FS_SECURITY=y -+CONFIG_EXT2_FS_XIP=y -+CONFIG_FS_XIP=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_XATTR=y -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_SECURITY=y -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+# CONFIG_JBD_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+CONFIG_FS_POSIX_ACL=y -+# CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_ROMFS_FS is not set -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_QUOTA=y -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y -+CONFIG_DNOTIFY=y -+CONFIG_AUTOFS_FS=m -+CONFIG_AUTOFS4_FS=m -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=y -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=m -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_KCORE=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+CONFIG_HUGETLBFS=y -+CONFIG_HUGETLB_PAGE=y -+CONFIG_PROMFS_FS=y -+CONFIG_RAMFS=y -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_ECRYPT_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_FS_POSIX_ACL=y -+CONFIG_JFFS2_FS_SECURITY=y -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_CRAMFS=m -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+ -+# -+# Network File Systems -+# -+CONFIG_NFS_FS=m -+CONFIG_NFS_V3=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_DIRECTIO=y -+# CONFIG_NFSD is not set -+CONFIG_LOCKD=m -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_ACL_SUPPORT=m -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=m -+CONFIG_SUNRPC_GSS=m -+# CONFIG_SUNRPC_BIND34 is not set -+CONFIG_RPCSEC_GSS_KRB5=m -+CONFIG_RPCSEC_GSS_SPKM3=m -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+# CONFIG_9P_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+ -+# -+# Native Language Support -+# -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=m -+ -+# -+# Distributed Lock Manager -+# -+# CONFIG_DLM is not set -+ -+# -+# Instrumentation Support -+# -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y -+ -+# -+# Kernel hacking -+# -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_PRINTK_TIME=y -+# CONFIG_ENABLE_MUST_CHECK is not set -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_UNUSED_SYMBOLS=y -+CONFIG_DEBUG_FS=y -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+CONFIG_SCHEDSTATS=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_SLAB is not set -+CONFIG_DEBUG_PREEMPT=y -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+CONFIG_DEBUG_SPINLOCK=y -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+CONFIG_DEBUG_SPINLOCK_SLEEP=y -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_VM=y -+CONFIG_DEBUG_LIST=y -+# CONFIG_FRAME_POINTER is not set -+# CONFIG_FORCED_INLINING is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_LKDTM is not set -+# CONFIG_FAULT_INJECTION is not set -+CONFIG_EARLY_PRINTK=y -+CONFIG_DEBUG_STACKOVERFLOW=y -+CONFIG_DEBUG_STACK_USAGE=y -+ -+# -+# Page alloc debug is incompatible with Software Suspend on i386 -+# -+CONFIG_DEBUG_RODATA=y -+CONFIG_4KSTACKS=y -+CONFIG_DOUBLEFAULT=y -+ -+# -+# Security options -+# -+CONFIG_KEYS=y -+CONFIG_KEYS_DEBUG_PROC_KEYS=y -+CONFIG_SECURITY=y -+CONFIG_SECURITY_NETWORK=y -+CONFIG_SECURITY_NETWORK_XFRM=y -+CONFIG_SECURITY_CAPABILITIES=y -+# CONFIG_SECURITY_ROOTPLUG is not set -+CONFIG_SECURITY_SELINUX=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 -+# CONFIG_SECURITY_SELINUX_DISABLE is not set -+CONFIG_SECURITY_SELINUX_DEVELOP=y -+CONFIG_SECURITY_SELINUX_AVC_STATS=y -+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -+# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set -+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set -+ -+# -+# Cryptographic options -+# -+CONFIG_CRYPTO=y -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_NULL=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_GF128MUL=m -+CONFIG_CRYPTO_ECB=m -+CONFIG_CRYPTO_CBC=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_LRW=m -+# CONFIG_CRYPTO_CRYPTD is not set -+CONFIG_CRYPTO_DES=m -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_TWOFISH_COMMON=m -+# CONFIG_CRYPTO_TWOFISH_586 is not set -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_AES=m -+CONFIG_CRYPTO_AES_586=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_ARC4=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_DEFLATE=m -+CONFIG_CRYPTO_MICHAEL_MIC=m -+CONFIG_CRYPTO_CRC32C=m -+CONFIG_CRYPTO_CAMELLIA=m -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Hardware crypto devices -+# -+# CONFIG_CRYPTO_DEV_PADLOCK is not set -+CONFIG_CRYPTO_DEV_GEODE=y -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC16=m -+# CONFIG_CRC_ITU_T is not set -+CONFIG_CRC32=y -+CONFIG_LIBCRC32C=m -+CONFIG_AUDIT_GENERIC=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_REED_SOLOMON=y -+CONFIG_REED_SOLOMON_DEC16=y -+CONFIG_TEXTSEARCH=y -+CONFIG_TEXTSEARCH_KMP=m -+CONFIG_TEXTSEARCH_BM=m -+CONFIG_TEXTSEARCH_FSM=m -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_X86_BIOS_REBOOT=y -+CONFIG_KTIME_SCALAR=y diff --git a/arch/i386/kernel/Makefile b/arch/i386/kernel/Makefile index 9d33b00..2e2cf42 100644 --- a/arch/i386/kernel/Makefile @@ -5702,10033 +182,4176 @@ index 8f03821..3176280 100644 page_pde_offset = (__PAGE_OFFSET >> 20); movl $(pg0 - __PAGE_OFFSET), %edi -diff --git a/arch/i386/kernel/mfgpt.c b/arch/i386/kernel/mfgpt.c -new file mode 100644 -index 0000000..2e62a41 ---- /dev/null -+++ b/arch/i386/kernel/mfgpt.c -@@ -0,0 +1,354 @@ -+/* Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT) -+ * -+ * Copyright (C) 2006, Advanced Micro Devices, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+/* The MFPGT timers on the CS5536 provide us with suitable timers to use -+ * as clock event sources - not as good as a HPET or APIC, but certainly -+ * better then the PIT. This isn't a general purpose MFGPT driver, but -+ * a simplified one designed specifically to act as a clock event source. -+ * For full details about the MFGPT, please consult the CS5536 data sheet. -+*/ + + +diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c +index d474cd6..c4b26ba 100644 +--- a/arch/i386/kernel/setup.c ++++ b/arch/i386/kernel/setup.c +@@ -362,8 +362,10 @@ void __init zone_sizes_init(void) + { + unsigned long max_zone_pfns[MAX_NR_ZONES]; + memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); ++#ifdef CONFIG_ZONE_DMA + max_zone_pfns[ZONE_DMA] = + virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; ++#endif + max_zone_pfns[ZONE_NORMAL] = max_low_pfn; + #ifdef CONFIG_HIGHMEM + max_zone_pfns[ZONE_HIGHMEM] = highend_pfn; +@@ -428,6 +430,9 @@ void __init setup_bootmem_allocator(void) + */ + acpi_reserve_bootmem(); + #endif ++#ifdef CONFIG_OLPC_PM ++ reserve_bootmem(0xf0000, PAGE_SIZE); ++#endif + #ifdef CONFIG_X86_FIND_SMP_CONFIG + /* + * Find and reserve possible boot-time SMP configuration: +diff --git a/arch/i386/pci/Makefile b/arch/i386/pci/Makefile +index 44650e0..1250a7b 100644 +--- a/arch/i386/pci/Makefile ++++ b/arch/i386/pci/Makefile +@@ -3,6 +3,7 @@ obj-y := i386.o init.o + obj-$(CONFIG_PCI_BIOS) += pcbios.o + obj-$(CONFIG_PCI_MMCONFIG) += mmconfig.o direct.o mmconfig-shared.o + obj-$(CONFIG_PCI_DIRECT) += direct.o ++obj-$(CONFIG_PCI_OLPC) += olpc.o + + pci-y := fixup.o + pci-$(CONFIG_ACPI) += acpi.o +diff --git a/arch/i386/pci/init.c b/arch/i386/pci/init.c +index 3de9f9b..0f5f7dd 100644 +--- a/arch/i386/pci/init.c ++++ b/arch/i386/pci/init.c +@@ -14,6 +14,9 @@ static __init int pci_access_init(void) + #ifdef CONFIG_PCI_MMCONFIG + pci_mmcfg_init(type); + #endif ++#ifdef CONFIG_PCI_OLPC ++ pci_olpc_init(); ++#endif + if (raw_pci_ops) + return 0; + #ifdef CONFIG_PCI_BIOS +diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h +index 8c66f27..a67e617 100644 +--- a/arch/i386/pci/pci.h ++++ b/arch/i386/pci/pci.h +@@ -93,6 +93,7 @@ extern void pci_direct_init(int type); + extern void pci_pcbios_init(void); + extern void pci_mmcfg_init(int type); + extern void pcibios_sort(void); ++extern void pci_olpc_init(void); + + /* pci-mmconfig.c */ + +diff --git a/drivers/Makefile b/drivers/Makefile +index f0878b2..c033d30 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -23,6 +23,8 @@ obj-y += char/ + + obj-$(CONFIG_CONNECTOR) += connector/ + ++obj-$(CONFIG_SYSPROF) += sysprof/ + -+/* We are using the 32Khz input clock - its the only one that has the -+ * ranges we find desirable. The following table lists the suitable -+ * divisors and the associated hz, minimum interval -+ * and the maximum interval: -+ -+ Divisor Hz Min Delta (S) Max Delta (S) -+ 1 32000 .0005 2.048 -+ 2 16000 .001 4.096 -+ 4 8000 .002 8.192 -+ 8 4000 .004 16.384 -+ 16 2000 .008 32.768 -+ 32 1000 .016 65.536 -+ 64 500 .032 131.072 -+ 128 250 .064 262.144 -+ 256 125 .128 524.288 -+*/ + # i810fb and intelfb depend on char/agp/ + obj-$(CONFIG_FB_I810) += video/i810/ + obj-$(CONFIG_FB_INTEL) += video/intelfb/ +diff --git a/drivers/char/vt_ioctl.c b/drivers/char/vt_ioctl.c +index c6f6f42..55ae42c 100644 +--- a/drivers/char/vt_ioctl.c ++++ b/drivers/char/vt_ioctl.c +@@ -37,6 +37,9 @@ + char vt_dont_switch; + extern struct tty_driver *console_driver; + ++/* Add a notifier chain to inform drivers of a VT_TEXT/VT_GRAPHICS switch */ ++RAW_NOTIFIER_HEAD(console_notifier_list); + -+#include -+#include -+#include -+#include -+#include -+#include + #define VT_IS_IN_USE(i) (console_driver->ttys[i] && console_driver->ttys[i]->count) + #define VT_BUSY(i) (VT_IS_IN_USE(i) || i == fg_console || vc_cons[i].d == sel_cons) + +@@ -491,6 +494,14 @@ int vt_ioctl(struct tty_struct *tty, struct file * file, + vc->vc_mode = (unsigned char) arg; + if (console != fg_console) + return 0; + -+#include "do_timer.h" ++ /* Notify listeners if the current fg_console has switched */ + -+#define MFGPT_MAX_TIMERS 8 ++ raw_notifier_call_chain(&console_notifier_list, ++ (arg == KD_TEXT) ? ++ CONSOLE_EVENT_SWITCH_TEXT : ++ CONSOLE_EVENT_SWITCH_GRAPHICS, 0); + -+#define F_AVAIL 0x01 + /* + * explicitly blank/unblank the screen if switching modes + */ +diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c +index e6c4a2b..874d623 100644 +--- a/drivers/i2c/busses/scx200_acb.c ++++ b/drivers/i2c/busses/scx200_acb.c +@@ -46,6 +46,10 @@ static int base[MAX_DEVICES] = { 0x820, 0x840 }; + module_param_array(base, int, NULL, 0); + MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); + ++static unsigned int smbclk = 0x70; ++module_param(smbclk, uint, 0); ++MODULE_PARM_DESC(smbclk, "Specify the SMB_CLK value"); + -+static struct mfgpt_timer_t { -+ int flags; -+ struct module *owner; -+} mfgpt_timers[MFGPT_MAX_TIMERS]; + #define POLL_TIMEOUT (HZ/5) + + enum scx200_acb_state { +@@ -108,6 +112,7 @@ struct scx200_acb_iface { + #define ACBADDR (iface->base + 4) + #define ACBCTL2 (iface->base + 5) + #define ACBCTL2_ENABLE 0x01 ++#define ACBCTL3 (iface->base + 6) + + /************************************************************************/ + +@@ -392,11 +397,13 @@ static __init int scx200_acb_probe(struct scx200_acb_iface *iface) + { + u8 val; + +- /* Disable the ACCESS.bus device and Configure the SCL +- frequency: 16 clock cycles */ +- outb(0x70, ACBCTL2); ++ /* Disable the ACCESS.bus device and Configure the SCL */ + -+/* Selected from the table above */ ++ outb((smbclk & 0x7F) << 1, ACBCTL2); + -+#define MFGPT_DIVISOR 16 -+#define MFGPT_SCALE 4 /* divisor = 2^(scale) */ -+#define MFGPT_HZ (32000 / MFGPT_DIVISOR) -+#define MFGPT_PERIODIC (MFGPT_HZ / HZ) ++ outb((smbclk >> 7) & 0xFF, ACBCTL3); + +- if (inb(ACBCTL2) != 0x70) { ++ if (inb(ACBCTL2) != ((smbclk & 0x7F) << 1)) { + pr_debug(NAME ": ACBCTL2 readback failed\n"); + return -ENXIO; + } +diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c +index 41fc3d0..a15e7a9 100644 +--- a/drivers/input/keyboard/atkbd.c ++++ b/drivers/input/keyboard/atkbd.c +@@ -63,12 +63,25 @@ static int atkbd_extra; + module_param_named(extra, atkbd_extra, bool, 0); + MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and similar keyboards"); + ++#define ATKBD_KEY_UNKNOWN 0 ++#define ATKBD_KEY_NULL 0xFF0000FF + -+#ifdef CONFIG_GEODE_MFGPT_TIMER -+static int __init mfgpt_timer_setup(void); -+#else -+#define mfgpt_timer_setup() (0) -+#endif ++#define ATKBD_SCR_1 0xFF0000FE ++#define ATKBD_SCR_2 0xFF0000FD ++#define ATKBD_SCR_4 0xFF0000FC ++#define ATKBD_SCR_8 0xFF0000FB ++#define ATKBD_SCR_CLICK 0xFF0000FA ++#define ATKBD_SCR_LEFT 0xFF0000F9 ++#define ATKBD_SCR_RIGHT 0xFF0000F8 + -+/* Allow for disabling of MFGPTs */ -+static int disable = 0; -+static int __init mfgpt_disable(char *s) -+{ -+ disable = 1; -+ return 1; -+} -+__setup("nomfgpt", mfgpt_disable); ++#define ATKBD_SPECIAL 0xFF0000F8 + -+/* -+ * Check whether any MFGPTs are available for the kernel to use. In most -+ * cases, firmware that uses AMD's VSA code will claim all timers during -+ * bootup; we certainly don't want to take them if they're already in use. -+ * In other cases (such as with VSAless OpenFirmware), the system firmware -+ * leaves timers available for us to use. -+ */ -+int __init geode_mfgpt_detect(void) -+{ -+ int count = 0, i; -+ u16 val; + /* + * Scancode to keycode tables. These are just the default setting, and + * are loadable via an userland utility. + */ + +-static unsigned char atkbd_set2_keycode[512] = { ++static unsigned int atkbd_set2_keycode[512] = { + + #ifdef CONFIG_KEYBOARD_ATKBD_HP_KEYCODES + +@@ -87,11 +100,17 @@ static unsigned char atkbd_set2_keycode[512] = { + 82, 83, 80, 76, 77, 72, 1, 69, 87, 78, 81, 74, 55, 73, 70, 99, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 217,100,255, 0, 97,165, 0, 0,156, 0, 0, 0, 0, 0, 0,125, + -+ if (disable) { -+ printk(KERN_INFO "geode-mfgpt: Skipping MFGPT setup\n"); -+ return 0; -+ } -+ -+ for (i = 0; i < MFGPT_MAX_TIMERS; i++) { -+ val = geode_mfgpt_read(i, MFGPT_REG_SETUP); -+ if (!(val & MFGPT_SETUP_SETUP)) { -+ mfgpt_timers[i].flags = F_AVAIL; -+ count++; -+ } -+ } -+ -+ /* set up clock event device, if desired */ -+ i = mfgpt_timer_setup(); ++ 217,100,ATKBD_KEY_NULL, 0, 97,165, 0, 0, ++ 156, 0, 0, 0, 0, 0, 0,125, + -+ return count; -+} + 173,114, 0,113, 0, 0, 0,126,128, 0, 0,140, 0, 0, 0,127, + 159, 0,115, 0,164, 0, 0,116,158, 0,172,166, 0, 0, 0,142, + 157, 0, 0, 0, 0, 0, 0, 0,155, 0, 98, 0, 0,163, 0, 0, +- 226, 0, 0, 0, 0, 0, 0, 0, 0,255, 96, 0, 0, 0,143, 0, + -+int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable) -+{ -+ u32 msr, mask, value, dummy; -+ int shift = (cmp == MFGPT_CMP1) ? 0 : 8; ++ 226, 0, 0, 0, 0, 0, 0, 0, ++ 0,ATKBD_KEY_NULL, 96, 0, 0, 0,143, 0, + -+ if (timer < 0 || timer >= MFGPT_MAX_TIMERS) -+ return -EIO; + 0, 0, 0, 0, 0, 0, 0, 0, 0,107, 0,105,102, 0, 0,112, + 110,111,108,112,106,103, 0,119, 0,118,109, 0, 99,104,119, 0, + +@@ -150,19 +169,6 @@ static unsigned char atkbd_unxlate_table[128] = { + #define ATKBD_RET_HANGEUL 0xf2 + #define ATKBD_RET_ERR 0xff + +-#define ATKBD_KEY_UNKNOWN 0 +-#define ATKBD_KEY_NULL 255 +- +-#define ATKBD_SCR_1 254 +-#define ATKBD_SCR_2 253 +-#define ATKBD_SCR_4 252 +-#define ATKBD_SCR_8 251 +-#define ATKBD_SCR_CLICK 250 +-#define ATKBD_SCR_LEFT 249 +-#define ATKBD_SCR_RIGHT 248 +- +-#define ATKBD_SPECIAL 248 +- + #define ATKBD_LED_EVENT_BIT 0 + #define ATKBD_REP_EVENT_BIT 1 + +@@ -174,7 +180,7 @@ static unsigned char atkbd_unxlate_table[128] = { + #define ATKBD_XL_HANJA 0x20 + + static struct { +- unsigned char keycode; ++ unsigned int keycode; + unsigned char set2; + } atkbd_scroll_keys[] = { + { ATKBD_SCR_1, 0xc5 }, +@@ -200,7 +206,7 @@ struct atkbd { + char phys[32]; + + unsigned short id; +- unsigned char keycode[512]; ++ unsigned int keycode[512]; + unsigned char set; + unsigned char translated; + unsigned char extra; +@@ -351,7 +357,7 @@ static irqreturn_t atkbd_interrupt(struct serio *serio, unsigned char data, + unsigned int code = data; + int scroll = 0, hscroll = 0, click = -1, add_release_event = 0; + int value; +- unsigned char keycode; ++ unsigned int keycode; + + #ifdef ATKBD_DEBUG + printk(KERN_DEBUG "atkbd.c: Received %02x flags %02x\n", data, flags); +@@ -856,9 +862,11 @@ static void atkbd_set_keycode_table(struct atkbd *atkbd) + atkbd->keycode[i | 0x80] = atkbd_scroll_keys[j].keycode; + } + } else if (atkbd->set == 3) { +- memcpy(atkbd->keycode, atkbd_set3_keycode, sizeof(atkbd->keycode)); ++ for (i = 0; i < ARRAY_SIZE(atkbd_set3_keycode); i++) ++ atkbd->keycode[i] = atkbd_set3_keycode[i]; + } else { +- memcpy(atkbd->keycode, atkbd_set2_keycode, sizeof(atkbd->keycode)); ++ for (i = 0; i < ARRAY_SIZE(atkbd_set2_keycode); i++) ++ atkbd->keycode[i] = atkbd_set2_keycode[i]; + + if (atkbd->scroll) + for (i = 0; i < ARRAY_SIZE(atkbd_scroll_keys); i++) +@@ -925,8 +933,8 @@ static void atkbd_set_device_attrs(struct atkbd *atkbd) + } + + input_dev->keycode = atkbd->keycode; +- input_dev->keycodesize = sizeof(unsigned char); +- input_dev->keycodemax = ARRAY_SIZE(atkbd_set2_keycode); ++ input_dev->keycodesize = sizeof(unsigned int); ++ input_dev->keycodemax = ARRAY_SIZE(atkbd->keycode); + + for (i = 0; i < 512; i++) + if (atkbd->keycode[i] && atkbd->keycode[i] < ATKBD_SPECIAL) +@@ -1017,6 +1025,10 @@ static int atkbd_connect(struct serio *serio, struct serio_driver *drv) + return err; + } + ++#ifdef CONFIG_OLPC ++#include ++#endif + -+ /* -+ * The register maps for these are described in sections 6.17.1.x of -+ * the AMD Geode CS5536 Companion Device Data Book. -+ */ -+ switch(event) { -+ case MFGPT_EVENT_RESET: -+ /* XXX: According to the docs, we cannot reset timers above -+ * 6; that is, resets for 7 and 8 will be ignored. Is this -+ * a problem? */ -+ msr = MFGPT_NR_MSR; -+ mask = 1 << (timer + 24); -+ break; + /* + * atkbd_reconnect() tries to restore keyboard into a sane state and is + * most likely called on resume. +@@ -1027,6 +1039,12 @@ static int atkbd_reconnect(struct serio *serio) + struct atkbd *atkbd = serio_get_drvdata(serio); + struct serio_driver *drv = serio->drv; + ++#ifdef CONFIG_OLPC ++ if (olpc_rev_after(OLPC_REV_B2)) ++ if (serio->dev.power.power_state.event != PM_EVENT_ON) ++ return 0; ++#endif + -+ case MFGPT_EVENT_NMI: -+ msr = MFGPT_NR_MSR; -+ mask = 1 << (timer + shift); -+ break; + if (!atkbd || !drv) { + printk(KERN_DEBUG "atkbd: reconnect request, but serio is disconnected, ignoring...\n"); + return -1; +diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig +index 7bbea09..6febbc5 100644 +--- a/drivers/input/mouse/Kconfig ++++ b/drivers/input/mouse/Kconfig +@@ -96,6 +96,16 @@ config MOUSE_PS2_TOUCHKIT + + If unsure, say N. + ++config MOUSE_PS2_OLPC ++ bool "OLPC PS/2 mouse protocol extension" if EMBEDDED ++ default n ++ depends on MOUSE_PS2 && OLPC ++ ---help--- ++ Say Y here if you have an OLPC PS/2 touchpad connected to ++ your system. + -+ case MFGPT_EVENT_IRQ: -+ msr = MFGPT_IRQ_MSR; -+ mask = 1 << (timer + shift); -+ break; ++ If unsure, say N. + -+ default: -+ return -EIO; + config MOUSE_SERIAL + tristate "Serial mouse" + select SERIO +diff --git a/drivers/input/mouse/Makefile b/drivers/input/mouse/Makefile +index 9e6e363..f4654ce 100644 +--- a/drivers/input/mouse/Makefile ++++ b/drivers/input/mouse/Makefile +@@ -24,3 +24,4 @@ psmouse-$(CONFIG_MOUSE_PS2_LOGIPS2PP) += logips2pp.o + psmouse-$(CONFIG_MOUSE_PS2_LIFEBOOK) += lifebook.o + psmouse-$(CONFIG_MOUSE_PS2_TRACKPOINT) += trackpoint.o + psmouse-$(CONFIG_MOUSE_PS2_TOUCHKIT) += touchkit_ps2.o ++psmouse-$(CONFIG_MOUSE_PS2_OLPC) += olpc.o +diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c +index b9f0fb2..edcdb68 100644 +--- a/drivers/input/mouse/psmouse-base.c ++++ b/drivers/input/mouse/psmouse-base.c +@@ -26,6 +26,7 @@ + #include "synaptics.h" + #include "logips2pp.h" + #include "alps.h" ++#include "olpc.h" + #include "lifebook.h" + #include "trackpoint.h" + #include "touchkit_ps2.h" +@@ -103,7 +104,7 @@ static struct attribute_group psmouse_attribute_group = { + */ + static DEFINE_MUTEX(psmouse_mutex); + +-static struct workqueue_struct *kpsmoused_wq; ++struct workqueue_struct *kpsmoused_wq; + + struct psmouse_protocol { + enum psmouse_type type; +@@ -320,7 +321,7 @@ static irqreturn_t psmouse_interrupt(struct serio *serio, + goto out; + } + +- if (psmouse->packet[1] == PSMOUSE_RET_ID) { ++ if (psmouse->packet[1] == PSMOUSE_RET_ID || psmouse->packet[1] == PSMOUSE_RET_BAT) { + __psmouse_set_state(psmouse, PSMOUSE_IGNORE); + serio_reconnect(serio); + goto out; +@@ -631,8 +632,21 @@ static int psmouse_extensions(struct psmouse *psmouse, + } + } + ++/* ++ * Try OLPC touchpad. ++ */ + if (max_proto > PSMOUSE_IMEX) { ++ if (olpc_detect(psmouse, set_properties) == 0) { ++ if (!set_properties || olpc_init(psmouse) == 0) ++ return PSMOUSE_OLPC; ++/* ++ * Init failed, try basic relative protocols ++ */ ++ max_proto = PSMOUSE_IMEX; ++ } + } + ++ if (max_proto > PSMOUSE_IMEX) { + if (genius_detect(psmouse, set_properties) == 0) + return PSMOUSE_GENPS; + +@@ -762,6 +776,14 @@ static const struct psmouse_protocol psmouse_protocols[] = { + .detect = touchkit_ps2_detect, + }, + #endif ++#ifdef CONFIG_MOUSE_PS2_OLPC ++ { ++ .type = PSMOUSE_OLPC, ++ .name = "OLPC", ++ .alias = "olpc", ++ .detect = olpc_detect, ++ }, ++#endif + { + .type = PSMOUSE_CORTRON, + .name = "CortronPS/2", +diff --git a/drivers/input/mouse/psmouse.h b/drivers/input/mouse/psmouse.h +index 1317bdd..c4857df 100644 +--- a/drivers/input/mouse/psmouse.h ++++ b/drivers/input/mouse/psmouse.h +@@ -89,6 +89,7 @@ enum psmouse_type { + PSMOUSE_TRACKPOINT, + PSMOUSE_TOUCHKIT_PS2, + PSMOUSE_CORTRON, ++ PSMOUSE_OLPC, + PSMOUSE_AUTO /* This one should always be last */ + }; + +@@ -96,6 +97,7 @@ int psmouse_sliced_command(struct psmouse *psmouse, unsigned char command); + int psmouse_reset(struct psmouse *psmouse); + void psmouse_set_resolution(struct psmouse *psmouse, unsigned int resolution); + ++extern struct workqueue_struct *kpsmoused_wq; + + struct psmouse_attribute { + struct device_attribute dattr; +diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c +index c2eea27..3510726 100644 +--- a/drivers/input/serio/i8042.c ++++ b/drivers/input/serio/i8042.c +@@ -868,6 +868,11 @@ static long i8042_panic_blink(long count) + #undef DELAY + + #ifdef CONFIG_PM + -+ rdmsr(msr, value, dummy); -+ -+ if (enable) -+ value |= mask; -+ else -+ value &= ~mask; -+ -+ wrmsr(msr, value, dummy); -+ return 0; -+} -+EXPORT_SYMBOL(geode_mfgpt_toggle_event); -+ -+int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable) -+{ -+ u32 val, dummy; -+ int offset; -+ -+ if (timer < 0 || timer >= MFGPT_MAX_TIMERS) -+ return -EIO; ++#ifdef CONFIG_OLPC ++#include ++#endif + -+ if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) -+ return -EIO; -+ -+ rdmsr(0x51400022, val, dummy); -+ -+ offset = (timer % 4) * 4; -+ -+ val &= ~((0xF << offset) | (0xF << (offset + 16))); -+ -+ if (enable) { -+ val |= (irq & 0x0F) << (offset); -+ val |= (irq & 0x0F) << (offset + 16); -+ } -+ -+ wrmsr(0x51400022, val, dummy); -+ return 0; -+} -+EXPORT_SYMBOL(geode_mfgpt_set_irq); -+ -+static int mfgpt_get(int timer, struct module *owner) -+{ -+ mfgpt_timers[timer].flags &= ~F_AVAIL; -+ mfgpt_timers[timer].owner = owner; -+ printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer); -+ return timer; -+} -+ -+int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner) -+{ -+ int i; -+ -+ if (!geode_get_dev_base(GEODE_DEV_MFGPT)) -+ return -ENODEV; -+ if (timer >= MFGPT_MAX_TIMERS) -+ return -EIO; -+ -+ if (timer < 0) { -+ /* Try to find an available timer */ -+ for (i = 0; i < MFGPT_MAX_TIMERS; i++) { -+ if (mfgpt_timers[i].flags & F_AVAIL) -+ return mfgpt_get(i, owner); -+ -+ if (i == 5 && domain == MFGPT_DOMAIN_WORKING) -+ break; + /* + * Here we try to restore the original BIOS settings. We only want to + * do that once, when we really suspend, not when we taking memory +@@ -878,8 +883,15 @@ static long i8042_panic_blink(long count) + static int i8042_suspend(struct platform_device *dev, pm_message_t state) + { + if (dev->dev.power.power_state.event != state.event) { ++#ifdef CONFIG_OLPC ++ /* Anything newer than B2 remains powered; no reset needed */ ++ if (olpc_rev_before(OLPC_REV_PRE_B3)) { ++#endif + if (state.event == PM_EVENT_SUSPEND) + i8042_controller_reset(); ++#ifdef CONFIG_OLPC + } ++#endif + + dev->dev.power.power_state = state; + } +@@ -902,9 +914,15 @@ static int i8042_resume(struct platform_device *dev) + if (dev->dev.power.power_state.event == PM_EVENT_ON) + return 0; + ++#ifdef CONFIG_OLPC ++ if (olpc_rev_before(OLPC_REV_PRE_B3)) { ++#endif + error = i8042_controller_check(); + if (error) + return error; ++#ifdef CONFIG_OLPC + } -+ else { -+ /* If they requested a specific timer, try to honor that */ -+ if (mfgpt_timers[timer].flags & F_AVAIL) -+ return mfgpt_get(timer, owner); -+ } -+ -+ /* No timers available - too bad */ -+ return -1; -+} -+EXPORT_SYMBOL(geode_mfgpt_alloc_timer); -+ -+#ifdef CONFIG_GEODE_MFGPT_TIMER -+ -+static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN; -+static u16 mfgpt_event_clock; -+ -+static int irq = 7; -+static int __init mfgpt_setup(char *str) -+{ -+ get_option(&str, &irq); -+ return 1; -+} -+__setup("mfgpt_irq=", mfgpt_setup); -+ -+static inline void mfgpt_disable_timer(u16 clock) -+{ -+ u16 val = geode_mfgpt_read(clock, MFGPT_REG_SETUP); -+ geode_mfgpt_write(clock, MFGPT_REG_SETUP, val & ~MFGPT_SETUP_CNTEN); -+} -+ -+static int mfgpt_next_event(unsigned long, struct clock_event_device *); -+static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *); -+ -+static struct clock_event_device mfgpt_clockevent = { -+ .name = "mfgpt-timer", -+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = mfgpt_set_mode, -+ .set_next_event = mfgpt_next_event, -+ .rating = 250, -+ .cpumask = CPU_MASK_ALL, -+ .shift = 32 -+}; -+ -+static inline void mfgpt_start_timer(u16 clock, u16 delta) -+{ -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta); -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); -+ -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, -+ MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); -+} -+ -+static void mfgpt_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *evt) -+{ -+ mfgpt_disable_timer(mfgpt_event_clock); -+ -+ if (mode == CLOCK_EVT_MODE_PERIODIC) -+ mfgpt_start_timer(mfgpt_event_clock, MFGPT_PERIODIC); -+ -+ mfgpt_tick_mode = mode; -+} -+ -+static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) -+{ -+ mfgpt_start_timer(mfgpt_event_clock, delta); -+ return 0; -+} -+ -+/* Assume (foolishly?), that this interrupt was due to our tick */ ++#endif + + error = i8042_controller_selftest(); + if (error) +diff --git a/drivers/input/serio/serio.c b/drivers/input/serio/serio.c +index 372ca49..c9e5308 100644 +--- a/drivers/input/serio/serio.c ++++ b/drivers/input/serio/serio.c +@@ -916,11 +916,22 @@ static int serio_uevent(struct device *dev, char **envp, int num_envp, char *buf + #endif /* CONFIG_HOTPLUG */ + + #ifdef CONFIG_PM + -+static irqreturn_t mfgpt_tick(int irq, void *dev_id) -+{ -+ if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN) -+ return IRQ_HANDLED; ++#ifdef CONFIG_OLPC ++#include ++#endif + -+ /* Turn off the clock */ -+ mfgpt_disable_timer(mfgpt_event_clock); + static int serio_suspend(struct device *dev, pm_message_t state) + { + if (dev->power.power_state.event != state.event) { ++#ifdef CONFIG_OLPC ++ if (olpc_rev_before(OLPC_REV_PRE_B3)) { ++#endif + if (state.event == PM_EVENT_SUSPEND) + serio_cleanup(to_serio_port(dev)); ++#ifdef CONFIG_OLPC ++ } ++#endif + + dev->power.power_state = state; + } +diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c +index ef53618..47881d2 100644 +--- a/drivers/media/video/cafe_ccic.c ++++ b/drivers/media/video/cafe_ccic.c +@@ -63,13 +63,13 @@ MODULE_SUPPORTED_DEVICE("Video"); + */ + + #define MAX_DMA_BUFS 3 +-static int alloc_bufs_at_load = 0; +-module_param(alloc_bufs_at_load, bool, 0444); +-MODULE_PARM_DESC(alloc_bufs_at_load, +- "Non-zero value causes DMA buffers to be allocated at module " +- "load time. This increases the chances of successfully getting " +- "those buffers, but at the cost of nailing down the memory from " +- "the outset."); ++static int alloc_bufs_at_read = 0; ++module_param(alloc_bufs_at_read, bool, 0444); ++MODULE_PARM_DESC(alloc_bufs_at_read, ++ "Non-zero value causes DMA buffers to be allocated when the " ++ "video capture device is read, rather than at module load " ++ "time. This saves memory, but decreases the chances of " ++ "successfully getting those buffers."); + + static int n_dma_bufs = 3; + module_param(n_dma_bufs, uint, 0644); +@@ -370,6 +370,10 @@ static int cafe_smbus_write_data(struct cafe_camera *cam, + rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR); + cafe_reg_write(cam, REG_TWSIC1, rval); + spin_unlock_irqrestore(&cam->dev_lock, flags); ++ mdelay(2); /* It'll probably take about 900µs anyway, and the ++ CAFÉ is apparently quite sensitive to being poked ++ at this point. If we can work out precisely what's ++ going on and reduce this delay, it would be nice. */ + + /* + * Time to wait for the write to complete. THIS IS A RACY +@@ -1503,7 +1507,7 @@ static int cafe_v4l_release(struct inode *inode, struct file *filp) + } + if (cam->users == 0) { + cafe_ctlr_power_down(cam); +- if (! alloc_bufs_at_load) ++ if (alloc_bufs_at_read) + cafe_free_dma_bufs(cam); + } + mutex_unlock(&cam->s_mutex); +@@ -2162,7 +2166,7 @@ static int cafe_pci_probe(struct pci_dev *pdev, + /* + * If so requested, try to get our DMA buffers now. + */ +- if (alloc_bufs_at_load) { ++ if (!alloc_bufs_at_read) { + if (cafe_alloc_dma_bufs(cam, 1)) + cam_warn(cam, "Unable to alloc DMA buffers at load" + " will try again later."); +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index 73e248f..f7afde3 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -202,5 +202,10 @@ config THINKPAD_ACPI_BAY + + If you are not sure, say Y here. + ++config EEPROM_93CX6 ++ tristate "EEPROM 93CX6 support" ++ ---help--- ++ This is a driver for the EEPROM chipsets 93c46 and 93c66. ++ The driver supports both read as well as write commands. + + endif # MISC_DEVICES +diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c +index 93fe2e5..e17eb8e 100644 +--- a/drivers/mmc/card/block.c ++++ b/drivers/mmc/card/block.c +@@ -229,6 +229,11 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) + if (brq.data.blocks > card->host->max_blk_count) + brq.data.blocks = card->host->max_blk_count; + ++ if (mmc_card_sd(card) && !card->host->ios.clock) { ++ printk(KERN_ERR "%s: I/O to stopped card\n", ++ req->rq_disk->disk_name); ++ goto cmd_err; ++ } + mmc_set_data_timeout(&brq.data, card, rq_data_dir(req) != READ); + + /* +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 20a7d89..9abbb58 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -411,6 +411,12 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) + break; + } + ++ /* ++ * There's an off-by-one error in the hw that we need to ++ * compensate for. ++ */ ++ count++; + -+ /* Clear the counter */ -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); + if (count >= 0xF) { + printk(KERN_WARNING "%s: Too large timeout requested!\n", + mmc_hostname(host->mmc)); +@@ -676,19 +682,17 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) + if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) + writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); + +- pwr = SDHCI_POWER_ON; +- + switch (1 << power) { + case MMC_VDD_165_195: +- pwr |= SDHCI_POWER_180; ++ pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: +- pwr |= SDHCI_POWER_300; ++ pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: +- pwr |= SDHCI_POWER_330; ++ pwr = SDHCI_POWER_330; + break; + default: + BUG(); +@@ -696,6 +700,10 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) + + writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); + ++ pwr |= SDHCI_POWER_ON; + -+ /* Restart the clock in periodic mode */ ++ writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); + -+ if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) { -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, -+ MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); -+ } + out: + host->power = power; + } +diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig +index fbec8cd..8848e8a 100644 +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -278,6 +278,14 @@ config SSFDC + This enables read only access to SmartMedia formatted NAND + flash. You can mount it with FAT file system. + ++config MTD_OOPS ++ tristate "Log panic/oops to an MTD buffer" ++ depends on MTD ++ help ++ This enables panic and oops messages to be logged to a circular ++ buffer in a flash partition where it can be read back at some ++ later point. + -+ mfgpt_clockevent.event_handler(&mfgpt_clockevent); -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction mfgptirq = { -+ .handler = mfgpt_tick, -+ .flags = IRQF_DISABLED | IRQF_NOBALANCING, -+ .mask = CPU_MASK_NONE, -+ .name = "mfgpt-timer" -+}; -+ -+static int __init mfgpt_timer_setup(void) -+{ -+ int timer, ret; -+ u16 val; -+ -+ timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING, THIS_MODULE); -+ if (timer < 0) { -+ printk(KERN_ERR "mfgpt-timer: Could not allocate a MFPGT timer\n"); -+ return -ENODEV; -+ } -+ -+ mfgpt_event_clock = timer; -+ /* Set the clock scale and enable the event mode for CMP2 */ -+ val = MFGPT_SCALE | (3 << 8); -+ -+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val); -+ -+ /* Set up the IRQ on the MFGPT side */ -+ if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) { -+ printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq); -+ return -EIO; -+ } -+ -+ /* And register it with the kernel */ -+ ret = setup_irq(irq, &mfgptirq); -+ -+ if (ret) { -+ printk(KERN_ERR "mfgpt-timer: Unable to set up the interrupt.\n"); -+ goto err; -+ } -+ -+ /* Set up the clock event */ -+ mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, 32); -+ mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mfgpt_clockevent); -+ mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, &mfgpt_clockevent); -+ -+ printk("mfgpt-timer: registering the MFGT timer as a clock event.\n"); -+ clockevents_register_device(&mfgpt_clockevent); -+ -+ return 0; -+ -+err: -+ geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq); -+ printk(KERN_ERR "mfgpt-timer: Unable to set up the MFGPT clock source\n"); -+ return -EIO; -+} -+ -+#endif -diff --git a/arch/i386/kernel/ofw.c b/arch/i386/kernel/ofw.c -new file mode 100644 -index 0000000..fdcd936 ---- /dev/null -+++ b/arch/i386/kernel/ofw.c -@@ -0,0 +1,100 @@ -+/* -+ * ofw.c - Open Firmware client interface for 32-bit systems. -+ * This code is intended to be portable to any 32-bit Open Firmware -+ * implementation with a standard client interface that can be -+ * called when Linux is running. -+ * -+ * Copyright (C) 2007 Mitch Bradley -+ * Copyright (C) 2007 Andres Salomon -+ */ -+ -+#include -+#include -+#include -+#include -+ -+ -+int (*call_firmware)(int *); -+ -+static DEFINE_SPINLOCK(prom_lock); -+ -+#define MAXARGS 20 -+ -+/* -+ * The return value from ofw() in all cases is 0 if the attempt to call the -+ * function succeeded, <0 otherwise. That return value is from the -+ * gateway function only. Any results from the called function are returned -+ * via output argument pointers. -+ * -+ * Here are call templates for all the standard OFW client services: -+ * -+ * ofw("test", 1, 1, namestr, &missing); -+ * ofw("peer", 1, 1, phandle, &sibling_phandle); -+ * ofw("child", 1, 1, phandle, &child_phandle); -+ * ofw("parent", 1, 1, phandle, &parent_phandle); -+ * ofw("instance_to_package", 1, 1, ihandle, &phandle); -+ * ofw("getproplen", 2, 1, phandle, namestr, &proplen); -+ * ofw("getprop", 4, 1, phandle, namestr, bufaddr, buflen, &size); -+ * ofw("nextprop", 3, 1, phandle, previousstr, bufaddr, &flag); -+ * ofw("setprop", 4, 1, phandle, namestr, bufaddr, len, &size); -+ * ofw("canon", 3, 1, devspecstr, bufaddr, buflen, &length); -+ * ofw("finddevice", 1, 1, devspecstr, &phandle); -+ * ofw("instance-to-path", 3, 1, ihandle, bufaddr, buflen, &length); -+ * ofw("package-to-path", 3, 1, phandle, bufaddr, buflen, &length); -+ * ofw("call_method", numin, numout, in0, in1, ..., &out0, &out1, ...); -+ * ofw("open", 1, 1, devspecstr, &ihandle); -+ * ofw("close", 1, 0, ihandle); -+ * ofw("read", 3, 1, ihandle, addr, len, &actual); -+ * ofw("write", 3, 1, ihandle, addr, len, &actual); -+ * ofw("seek", 3, 1, ihandle, pos_hi, pos_lo, &status); -+ * ofw("claim", 3, 1, virtaddr, size, align, &baseaddr); -+ * ofw("release", 2, 0, virtaddr, size); -+ * ofw("boot", 1, 0, bootspecstr); -+ * ofw("enter", 0, 0); -+ * ofw("exit", 0, 0); -+ * ofw("chain", 5, 0, virtaddr, size, entryaddr, argsaddr, len); -+ * ofw("interpret", numin+1, numout+1, cmdstr, in0, ..., &catchres, &out0, ...); -+ * ofw("set-callback", 1, 1, newfuncaddr, &oldfuncaddr); -+ * ofw("set-symbol-lookup", 2, 0, symtovaladdr, valtosymaddr); -+ * ofw("milliseconds", 0, 1, &ms); -+ */ -+ -+int ofw(char *name, int numargs, int numres, ...) -+{ -+ va_list ap; -+ int argarray[MAXARGS+3]; -+ int argnum = 3; -+ int retval; -+ int *intp; -+ unsigned long flags; -+ -+ if (!call_firmware) -+ return -1; -+ if ((numargs + numres) > MAXARGS) -+ return -1; /* spit out an error? */ -+ -+ argarray[0] = (int) name; -+ argarray[1] = numargs; -+ argarray[2] = numres; + source "drivers/mtd/chips/Kconfig" + + source "drivers/mtd/maps/Kconfig" +diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile +index 6d958a4..7f0b04b 100644 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_NFTL) += nftl.o + obj-$(CONFIG_INFTL) += inftl.o + obj-$(CONFIG_RFD_FTL) += rfd_ftl.o + obj-$(CONFIG_SSFDC) += ssfdc.o ++obj-$(CONFIG_MTD_OOPS) += mtdoops.o + + nftl-objs := nftlcore.o nftlmount.o + inftl-objs := inftlcore.o inftlmount.o +diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c +index 2f19fa7..39eff9f 100644 +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -526,7 +526,7 @@ static int cfi_intelext_partition_fixup(struct mtd_info *mtd, + struct cfi_pri_intelext *extp = cfi->cmdset_priv; + + /* +- * Probing of multi-partition flash ships. ++ * Probing of multi-partition flash chips. + * + * To support multiple partitions when available, we simply arrange + * for each of them to have their own flchip structure even if they +@@ -1780,7 +1780,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, + return ret; + } + +-int cfi_intelext_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) ++static int cfi_intelext_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) + { + unsigned long ofs, len; + int ret; +@@ -1930,7 +1930,7 @@ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, size_t len) + printk(KERN_DEBUG "%s: lock status before, ofs=0x%08llx, len=0x%08X\n", + __FUNCTION__, ofs, len); + cfi_varsize_frob(mtd, do_printlockstatus_oneblock, +- ofs, len, 0); ++ ofs, len, NULL); + #endif + + ret = cfi_varsize_frob(mtd, do_xxlock_oneblock, +@@ -1940,7 +1940,7 @@ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, size_t len) + printk(KERN_DEBUG "%s: lock status after, ret=%d\n", + __FUNCTION__, ret); + cfi_varsize_frob(mtd, do_printlockstatus_oneblock, +- ofs, len, 0); ++ ofs, len, NULL); + #endif + + return ret; +@@ -1954,7 +1954,7 @@ static int cfi_intelext_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) + printk(KERN_DEBUG "%s: lock status before, ofs=0x%08llx, len=0x%08X\n", + __FUNCTION__, ofs, len); + cfi_varsize_frob(mtd, do_printlockstatus_oneblock, +- ofs, len, 0); ++ ofs, len, NULL); + #endif + + ret = cfi_varsize_frob(mtd, do_xxlock_oneblock, +@@ -1964,7 +1964,7 @@ static int cfi_intelext_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) + printk(KERN_DEBUG "%s: lock status after, ret=%d\n", + __FUNCTION__, ret); + cfi_varsize_frob(mtd, do_printlockstatus_oneblock, +- ofs, len, 0); ++ ofs, len, NULL); + #endif + + return ret; +@@ -2255,7 +2255,7 @@ static void cfi_intelext_save_locks(struct mtd_info *mtd) + adr = region->offset + block * len; + + status = cfi_varsize_frob(mtd, +- do_getlockstatus_oneblock, adr, len, 0); ++ do_getlockstatus_oneblock, adr, len, NULL); + if (status) + set_bit(block, region->lockmap); + else +diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c +index 1f64458..389acc6 100644 +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1609,7 +1609,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, + } + + +-int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) ++static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) + { + unsigned long ofs, len; + int ret; +diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c +index 58e561e..593e9d6 100644 +--- a/drivers/mtd/chips/jedec_probe.c ++++ b/drivers/mtd/chips/jedec_probe.c +@@ -70,6 +70,7 @@ + + /* Fujitsu */ + #define MBM29F040C 0x00A4 ++#define MBM29F800BA 0x2258 + #define MBM29LV650UE 0x22D7 + #define MBM29LV320TE 0x22F6 + #define MBM29LV320BE 0x22F9 +@@ -129,6 +130,7 @@ + #define LH28F640BF 0x00b0 + + /* ST - www.st.com */ ++#define M29F800AB 0x0058 + #define M29W800DT 0x00D7 + #define M29W800DB 0x005B + #define M29W160DT 0x22C4 +@@ -646,6 +648,23 @@ static const struct amd_flash_info jedec_table[] = { + } + }, { + .mfr_id = MANUFACTURER_FUJITSU, ++ .dev_id = MBM29F800BA, ++ .name = "Fujitsu MBM29F800BA", ++ .uaddr = { ++ [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ ++ [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ ++ }, ++ .DevSize = SIZE_1MiB, ++ .CmdSet = P_ID_AMD_STD, ++ .NumEraseRegions= 4, ++ .regions = { ++ ERASEINFO(0x04000,1), ++ ERASEINFO(0x02000,2), ++ ERASEINFO(0x08000,1), ++ ERASEINFO(0x10000,15), ++ } ++ }, { ++ .mfr_id = MANUFACTURER_FUJITSU, + .dev_id = MBM29LV650UE, + .name = "Fujitsu MBM29LV650UE", + .uaddr = { +@@ -1510,6 +1529,23 @@ static const struct amd_flash_info jedec_table[] = { + ERASEINFO(0x1000,256) + } + ++ }, { ++ .mfr_id = MANUFACTURER_ST, ++ .dev_id = M29F800AB, ++ .name = "ST M29F800AB", ++ .uaddr = { ++ [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ ++ [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ ++ }, ++ .DevSize = SIZE_1MiB, ++ .CmdSet = P_ID_AMD_STD, ++ .NumEraseRegions= 4, ++ .regions = { ++ ERASEINFO(0x04000,1), ++ ERASEINFO(0x02000,2), ++ ERASEINFO(0x08000,1), ++ ERASEINFO(0x10000,15), ++ } + }, { + .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ + .dev_id = M29W800DT, +diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig +index ff642f8..b4ea64d 100644 +--- a/drivers/mtd/devices/Kconfig ++++ b/drivers/mtd/devices/Kconfig +@@ -69,12 +69,21 @@ config MTD_DATAFLASH26 + If you have such a board and such a DataFlash, say 'Y'. + + config MTD_M25P80 +- tristate "Support for M25 SPI Flash" ++ tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" + depends on SPI_MASTER && EXPERIMENTAL + help +- This enables access to ST M25P80 and similar SPI flash chips, +- used for program and data storage. Set up your spi devices +- with the right board-specific platform data. ++ This enables access to most modern SPI flash chips, used for ++ program and data storage. Series supported include Atmel AT26DF, ++ Spansion S25SL, SST 25VF, ST M25P, and Winbond W25X. Other chips ++ are supported as well. See the driver source for the current list, ++ or to add other chips. + -+ va_start(ap, numres); -+ while (numargs) { -+ argarray[argnum++] = va_arg(ap, int); -+ numargs--; -+ } ++ Note that the original DataFlash chips (AT45 series, not AT26DF), ++ need an entirely different driver. + -+ spin_lock_irqsave(&prom_lock, flags); -+ retval = call_firmware(argarray); -+ spin_unlock_irqrestore(&prom_lock, flags); ++ Set up your spi devices with the right board-specific platform data, ++ if you want to specify device partitioning or to use a device which ++ doesn't support the JEDEC ID instruction. + + config MTD_SLRAM + tristate "Uncached system RAM" +diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c +index 78c2511..98df5bc 100644 +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -1,5 +1,5 @@ + /* +- * MTD SPI driver for ST M25Pxx flash chips ++ * MTD SPI driver for ST M25Pxx (and similar) serial flash chips + * + * Author: Mike Lavender, mike@steroidmicros.com + * +@@ -19,33 +19,32 @@ + #include + #include + #include +-#include ++#include + -+ if (retval == 0) { -+ while (numres) { -+ intp = va_arg(ap, int *); -+ *intp = argarray[argnum++]; -+ numres--; -+ } -+ } -+ va_end(ap); -+ return retval; -+} -+EXPORT_SYMBOL(ofw); -diff --git a/arch/i386/kernel/olpc-pm.c b/arch/i386/kernel/olpc-pm.c -new file mode 100644 -index 0000000..93149f1 ---- /dev/null -+++ b/arch/i386/kernel/olpc-pm.c -@@ -0,0 +1,785 @@ -+/* olpc-pm.c -+ * © 2006 Red Hat, Inc. -+ * Portions also copyright 2006 Advanced Micro Devices, Inc. -+ * GPLv2 -+ */ + #include + #include + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* A few words about accessing the ACPI and PM registers. Long story short, -+ byte and word accesses of the ACPI and PM registers is broken. The only -+ way to do it really correctly is to use dword accesses, which we do -+ throughout this code. For more details, please consult Eratta 17 and 18 -+ here: -+ -+ http://www.amd.com/files/connectivitysolutions/geode/geode_gx/34472D_CS5536_B1_specupdate.pdf -+*/ -+ -+#define PM_IRQ 3 -+ -+#define CS5536_PM_PWRBTN (1 << 8) -+#define CS5536_PM_RTC (1 << 10) + #include + #include + +-#include +- +- +-/* NOTE: AT 25F and SST 25LF series are very similar, +- * but commands for sector erase and chip id differ... +- */ + + #define FLASH_PAGESIZE 256 + + /* Flash opcodes. */ +-#define OPCODE_WREN 6 /* Write enable */ +-#define OPCODE_RDSR 5 /* Read status register */ +-#define OPCODE_READ 3 /* Read data bytes */ +-#define OPCODE_PP 2 /* Page program */ +-#define OPCODE_SE 0xd8 /* Sector erase */ +-#define OPCODE_RES 0xab /* Read Electronic Signature */ ++#define OPCODE_WREN 0x06 /* Write enable */ ++#define OPCODE_RDSR 0x05 /* Read status register */ ++#define OPCODE_READ 0x03 /* Read data bytes (low frequency) */ ++#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ ++#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ ++#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ ++#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ ++#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ + #define OPCODE_RDID 0x9f /* Read JEDEC ID */ + + /* Status Register bits. */ + #define SR_WIP 1 /* Write in progress */ + #define SR_WEL 2 /* Write enable latch */ ++/* meaning of other SR_* bits may differ between vendors */ + #define SR_BP0 4 /* Block protect 0 */ + #define SR_BP1 8 /* Block protect 1 */ + #define SR_BP2 0x10 /* Block protect 2 */ +@@ -65,9 +64,10 @@ + + struct m25p { + struct spi_device *spi; +- struct semaphore lock; ++ struct mutex lock; + struct mtd_info mtd; +- unsigned partitioned; ++ unsigned partitioned:1; ++ u8 erase_opcode; + u8 command[4]; + }; + +@@ -150,8 +150,9 @@ static int wait_till_ready(struct m25p *flash) + */ + static int erase_sector(struct m25p *flash, u32 offset) + { +- DEBUG(MTD_DEBUG_LEVEL3, "%s: %s at 0x%08x\n", flash->spi->dev.bus_id, +- __FUNCTION__, offset); ++ DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", ++ flash->spi->dev.bus_id, __FUNCTION__, ++ flash->mtd.erasesize / 1024, offset); + + /* Wait until finished previous write command. */ + if (wait_till_ready(flash)) +@@ -161,7 +162,7 @@ static int erase_sector(struct m25p *flash, u32 offset) + write_enable(flash); + + /* Set up command buffer. */ +- flash->command[0] = OPCODE_SE; ++ flash->command[0] = flash->erase_opcode; + flash->command[1] = offset >> 16; + flash->command[2] = offset >> 8; + flash->command[3] = offset; +@@ -201,13 +202,17 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) + addr = instr->addr; + len = instr->len; + +- down(&flash->lock); ++ mutex_lock(&flash->lock); + -+#define GPIO_WAKEUP_EC (1 << 31) -+#define GPIO_WAKEUP_LID (1 << 30) ++ /* REVISIT in some cases we could speed up erasing large regions ++ * by using OPCODE_SE instead of OPCODE_BE_4K ++ */ + + /* now erase those sectors */ + while (len) { + if (erase_sector(flash, addr)) { + instr->state = MTD_ERASE_FAILED; +- up(&flash->lock); ++ mutex_unlock(&flash->lock); + return -EIO; + } + +@@ -215,7 +220,7 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) + len -= mtd->erasesize; + } + +- up(&flash->lock); ++ mutex_unlock(&flash->lock); + + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); +@@ -260,16 +265,19 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, + if (retlen) + *retlen = 0; + +- down(&flash->lock); ++ mutex_lock(&flash->lock); + + /* Wait till previous write/erase is done. */ + if (wait_till_ready(flash)) { + /* REVISIT status return?? */ +- up(&flash->lock); ++ mutex_unlock(&flash->lock); + return 1; + } + +- /* NOTE: OPCODE_FAST_READ (if available) is faster... */ ++ /* FIXME switch to OPCODE_FAST_READ. It's required for higher ++ * clocks; and at this writing, every chip this driver handles ++ * supports that opcode. ++ */ + + /* Set up the write data buffer. */ + flash->command[0] = OPCODE_READ; +@@ -281,7 +289,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, + + *retlen = m.actual_length - sizeof(flash->command); + +- up(&flash->lock); ++ mutex_unlock(&flash->lock); + + return 0; + } +@@ -323,7 +331,7 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, + t[1].tx_buf = buf; + spi_message_add_tail(&t[1], &m); + +- down(&flash->lock); ++ mutex_lock(&flash->lock); + + /* Wait until finished previous write command. */ + if (wait_till_ready(flash)) +@@ -381,10 +389,10 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, + if (retlen) + *retlen += m.actual_length + - sizeof(flash->command); +- } +- } ++ } ++ } + +- up(&flash->lock); ++ mutex_unlock(&flash->lock); + + return 0; + } +@@ -398,24 +406,118 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, + + struct flash_info { + char *name; +- u8 id; +- u16 jedec_id; + -+#define PM_MODE_NORMAL 0 -+#define PM_MODE_TEST 1 -+#define PM_MODE_MAX 2 ++ /* JEDEC id zero means "no ID" (most older chips); otherwise it has ++ * a high byte of zero plus three data bytes: the manufacturer id, ++ * then a two byte device id. ++ */ ++ u32 jedec_id; + -+/* These, and the battery EC commands, should be in an olpc.h. */ -+#define EC_WRITE_SCI_MASK 0x1b -+#define EC_READ_SCI_MASK 0x1c ++ /* The size listed here is what works with OPCODE_SE, which isn't ++ * necessarily called a "sector" by the vendor. ++ */ + unsigned sector_size; +- unsigned n_sectors; ++ u16 n_sectors; + -+extern void do_olpc_suspend_lowlevel(void); ++ u16 flags; ++#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ + }; + + -+static struct { -+ unsigned long address; -+ unsigned short segment; -+} ofw_bios_entry = { 0, __KERNEL_CS }; ++/* NOTE: double check command sets and memory organization when you add ++ * more flash chips. This current list focusses on newer chips, which ++ * have been converging on command sets which including JEDEC ID. ++ */ + static struct flash_info __devinitdata m25p_data [] = { +- /* REVISIT: fill in JEDEC ids, for parts that have them */ +- { "m25p05", 0x05, 0x2010, 32 * 1024, 2 }, +- { "m25p10", 0x10, 0x2011, 32 * 1024, 4 }, +- { "m25p20", 0x11, 0x2012, 64 * 1024, 4 }, +- { "m25p40", 0x12, 0x2013, 64 * 1024, 8 }, +- { "m25p80", 0x13, 0x0000, 64 * 1024, 16 }, +- { "m25p16", 0x14, 0x2015, 64 * 1024, 32 }, +- { "m25p32", 0x15, 0x2016, 64 * 1024, 64 }, +- { "m25p64", 0x16, 0x2017, 64 * 1024, 128 }, + -+static int olpc_pm_mode = PM_MODE_NORMAL; -+static unsigned long acpi_base; -+static unsigned long pms_base; -+static int sci_irq; -+static int olpc_lid_flag; ++ /* Atmel -- some are (confusingly) marketed as "DataFlash" */ ++ { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K, }, ++ { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K, }, + -+static struct input_dev *pm_inputdev; -+static struct input_dev *lid_inputdev; -+static struct input_dev *ebook_inputdev; -+static struct pm_ops olpc_pm_ops; ++ { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K, }, + -+static int gpio_wake_events = 0; -+static int ebook_state = -1; -+static u16 olpc_wakeup_mask = 0; ++ { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K, }, ++ { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K, }, ++ { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, }, ++ { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, }, + -+struct platform_device olpc_powerbutton_dev = { -+ .name = "powerbutton", -+ .id = -1, -+}; ++ /* Spansion -- single (large) sector size only, at least ++ * for the chips listed here (without boot sectors). ++ */ ++ { "s25sl004a", 0x010212, 64 * 1024, 8, }, ++ { "s25sl008a", 0x010213, 64 * 1024, 16, }, ++ { "s25sl016a", 0x010214, 64 * 1024, 32, }, ++ { "s25sl032a", 0x010215, 64 * 1024, 64, }, ++ { "s25sl064a", 0x010216, 64 * 1024, 128, }, + -+struct platform_device olpc_lid_dev = { -+ .name = "lid", -+ .id = -1, -+}; ++ /* SST -- large erase sizes are "overlays", "sectors" are 4K */ ++ { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K, }, ++ { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K, }, ++ { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K, }, ++ { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K, }, + -+static void __init init_ebook_state(void) -+{ -+ if (olpc_ec_cmd(0x2a, NULL, 0, (unsigned char *) &ebook_state, 1)) { -+ printk(KERN_WARNING "olpc-pm: failed to get EBOOK state!\n"); -+ ebook_state = 0; -+ } -+ ebook_state &= 1; ++ /* ST Microelectronics -- newer production may have feature updates */ ++ { "m25p05", 0x202010, 32 * 1024, 2, }, ++ { "m25p10", 0x202011, 32 * 1024, 4, }, ++ { "m25p20", 0x202012, 64 * 1024, 4, }, ++ { "m25p40", 0x202013, 64 * 1024, 8, }, ++ { "m25p80", 0, 64 * 1024, 16, }, ++ { "m25p16", 0x202015, 64 * 1024, 32, }, ++ { "m25p32", 0x202016, 64 * 1024, 64, }, ++ { "m25p64", 0x202017, 64 * 1024, 128, }, ++ { "m25p128", 0x202018, 256 * 1024, 64, }, + -+ /* the input layer needs to know what value to default to as well */ -+ input_report_switch(ebook_inputdev, SW_TABLET_MODE, ebook_state); -+ input_sync(ebook_inputdev); -+} ++ { "m45pe80", 0x204014, 64 * 1024, 16, }, ++ { "m45pe16", 0x204015, 64 * 1024, 32, }, + -+static void (*battery_callback)(unsigned long); -+static DEFINE_SPINLOCK(battery_callback_lock); ++ { "m25pe80", 0x208014, 64 * 1024, 16, }, ++ { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K, }, + -+/* propagate_events is non-NULL if run from workqueue, -+ NULL when called at init time to flush SCI queue */ -+static void process_sci_queue(struct work_struct *propagate_events) ++ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ ++ { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K, }, ++ { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K, }, ++ { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K, }, ++ { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K, }, ++ { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K, }, ++ { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K, }, ++ { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K, }, + }; + ++static struct flash_info *__devinit jedec_probe(struct spi_device *spi) +{ -+ unsigned char data = 0; -+ unsigned char battery_events = 0; -+ int ret; ++ int tmp; ++ u8 code = OPCODE_RDID; ++ u8 id[3]; ++ u32 jedec; ++ struct flash_info *info; + -+ do { -+ ret = olpc_ec_cmd(0x84, NULL, 0, &data, 1); -+ if (!ret) { -+ printk(KERN_DEBUG "olpc-pm: SCI 0x%x received\n", -+ data); -+ -+ switch (data) { -+ case EC_SCI_SRC_EMPTY: -+ case EC_SCI_SRC_GAME: -+ case EC_SCI_SRC_WLAN: -+ /* we ignore these for now */ -+ break; -+ case EC_SCI_SRC_BATERR: -+ printk(KERN_ERR "olpc-pm: Battery Management System detected an error! Remove turnip from battery slot.\n"); -+ case EC_SCI_SRC_BATSOC: -+ case EC_SCI_SRC_BATTERY: -+ case EC_SCI_SRC_ACPWR: -+ battery_events |= data; -+ break; -+ case EC_SCI_SRC_EBOOK: -+ ebook_state = !ebook_state; -+ if (propagate_events) { -+ input_report_switch(ebook_inputdev, -+ SW_TABLET_MODE, ebook_state); -+ input_sync(ebook_inputdev); -+ } -+ break; -+ default: -+ printk(KERN_ERR "olpc-pm: Unknown SCI event 0x%x occurred!\n", data); -+ } -+ } -+ } while (data && !ret); -+ -+ if (battery_events && battery_callback && propagate_events) { -+ void (*cbk)(unsigned long); -+ -+ /* Older EC versions didn't distinguish between AC and battery -+ events */ -+ if (olpc_platform_info.ecver < 0x45) -+ battery_events = EC_SCI_SRC_BATTERY | EC_SCI_SRC_ACPWR; -+ -+ spin_lock(&battery_callback_lock); -+ cbk = battery_callback; -+ spin_unlock(&battery_callback_lock); -+ -+ cbk(battery_events); -+ } -+ -+ if (ret) -+ printk(KERN_WARNING "Failed to clear SCI queue!\n"); -+} -+ -+static DECLARE_WORK(sci_work, process_sci_queue); -+ -+void olpc_register_battery_callback(void (*f)(unsigned long)) -+{ -+ spin_lock(&battery_callback_lock); -+ battery_callback = f; -+ spin_unlock(&battery_callback_lock); -+} -+EXPORT_SYMBOL_GPL(olpc_register_battery_callback); -+ -+void olpc_deregister_battery_callback(void) -+{ -+ spin_lock(&battery_callback_lock); -+ battery_callback = NULL; -+ spin_unlock(&battery_callback_lock); -+ cancel_work_sync(&sci_work); -+} -+EXPORT_SYMBOL_GPL(olpc_deregister_battery_callback); -+ -+ -+static int olpc_pm_interrupt(int irq, void *id) -+{ -+ uint32_t sts, gpe = 0; -+ -+ sts = inl(acpi_base + PM1_STS); -+ outl(sts | 0xFFFF, acpi_base + PM1_STS); -+ -+ if (olpc_get_rev() >= OLPC_REV_B2) { -+ gpe = inl(acpi_base + PM_GPE0_STS); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ } -+ -+ if (sts & CS5536_PM_PWRBTN) { -+ input_report_key(pm_inputdev, KEY_POWER, 1); -+ input_sync(pm_inputdev); -+ printk(KERN_DEBUG "olpm-pm: PM_PWRBTN event received\n"); -+ /* Do we need to delay this (and hence schedule_work)? */ -+ input_report_key(pm_inputdev, KEY_POWER, 0); -+ input_sync(pm_inputdev); -+ } -+ -+ if (gpe & GPIO_WAKEUP_EC) { -+ geode_gpio_clear(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS); -+ schedule_work(&sci_work); -+ } -+ -+ if (gpe & GPIO_WAKEUP_LID) { -+ /* Disable events */ -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ -+ /* Clear the edge */ -+ -+ if (olpc_lid_flag) -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* Clear the status too */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS); -+ -+ /* The line is high when the LID is open, but SW_LID -+ * should be high when the LID is closed, so we pass the old -+ * value of olpc_lid_flag -+ */ -+ -+ input_report_switch(lid_inputdev, SW_LID, olpc_lid_flag); -+ input_sync(lid_inputdev); -+ -+ /* Swap the status */ -+ olpc_lid_flag = !olpc_lid_flag; -+ -+ if (olpc_lid_flag) -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* re-enable the event */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * For now, only support STR. We also don't support suspending on -+ * B1s, due to difficulties with the cafe FPGA. -+ */ -+static int olpc_pm_state_valid(suspend_state_t pm_state) -+{ -+ if (pm_state == PM_SUSPEND_MEM && olpc_rev_after(OLPC_REV_B1)) -+ return 1; -+ -+ return 0; -+} -+ -+/* This is a catchall function for operations that just don't belong -+ * anywhere else. Later we will evaluate if these belong in the -+ * individual device drivers or the firmware. -+ * If you add something to this function, please explain yourself with -+ * a comment. -+ */ -+ -+extern void gxfb_flatpanel_control(int state); -+ -+static u32 gpio_wakeup[2]; -+static u64 irq_sources[4]; -+static u64 mfgpt_irq_msr, mfgpt_nr_msr; -+ -+void olpc_fixup_wakeup(void) -+{ -+ u32 base = geode_gpio_base(); -+ int i; -+ -+ /* This clears any pending events from the status register - -+ * the firmware also does this, but its possible that it tries -+ * it too early before the key has a chance to debounce ++ /* JEDEC also defines an optional "extended device information" ++ * string for after vendor-specific data, after the three bytes ++ * we use here. Supporting some chips might require using it. + */ ++ tmp = spi_write_then_read(spi, &code, 1, id, 3); ++ if (tmp < 0) { ++ DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", ++ spi->dev.bus_id, tmp); ++ return NULL; ++ } ++ jedec = id[0]; ++ jedec = jedec << 8; ++ jedec |= id[1]; ++ jedec = jedec << 8; ++ jedec |= id[2]; + -+ outl((CS5536_PM_PWRBTN << 16) | 0xFFFF, acpi_base + PM1_STS); -+ -+ /* Enable the flatpanel sequencing as early as possible, because -+ it takes ~64ms to resume. This probably belongs in the firmware */ -+ -+ //gxfb_flatpanel_control(1); -+ -+ /* Restore the interrupt sources */ -+ wrmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]); -+ wrmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]); -+ wrmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]); -+ wrmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]); -+ -+ /* Restore the X and Y sources for GPIO */ -+ outl(gpio_wakeup[0], base + GPIO_MAP_X); -+ outl(gpio_wakeup[1], base + GPIO_MAP_Y); -+ -+ /* Resture the MFGPT MSRs */ -+ wrmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr); -+ wrmsrl(MFGPT_NR_MSR, mfgpt_nr_msr); -+ -+ for (i=0;i<2;i++) { -+ /* tell the wireless module to restart USB communication */ -+ olpc_ec_cmd(0x24, NULL, 0, NULL, 0); ++ for (tmp = 0, info = m25p_data; ++ tmp < ARRAY_SIZE(m25p_data); ++ tmp++, info++) { ++ if (info->jedec_id == jedec) ++ return info; + } ++ dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); ++ return NULL; +} + -+void olpc_fixup_sleep(void) -+{ -+ u32 base = geode_gpio_base(); -+ int i; -+ -+ /* Save the X and Y sources for GPIO */ -+ gpio_wakeup[0] = inl(base + GPIO_MAP_X); -+ gpio_wakeup[1] = inl(base + GPIO_MAP_Y); -+ -+ /* Save the Y and Z unrestricted sources */ -+ -+ rdmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]); -+ rdmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]); -+ rdmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]); -+ rdmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]); -+ -+ /* Turn off the MFGPT timers on the way down */ -+ -+ for(i = 0; i < 8; i++) { -+ u32 val = geode_mfgpt_read(i, MFGPT_REG_SETUP); + -+ if (val & MFGPT_SETUP_SETUP) { -+ val &= ~MFGPT_SETUP_CNTEN; -+ geode_mfgpt_write(i, MFGPT_REG_SETUP, val); + /* + * board specific setup should have ensured the SPI clock used here + * matches what the READ command supports, at least until this driver +@@ -429,37 +531,51 @@ static int __devinit m25p_probe(struct spi_device *spi) + unsigned i; + + /* Platform data helps sort out which chip type we have, as +- * well as how this board partitions it. ++ * well as how this board partitions it. If we don't have ++ * a chip ID, try the JEDEC id commands; they'll work for most ++ * newer chips, even if we don't recognize the particular chip. + */ + data = spi->dev.platform_data; +- if (!data || !data->type) { +- /* FIXME some chips can identify themselves with RES +- * or JEDEC get-id commands. Try them ... +- */ +- DEBUG(MTD_DEBUG_LEVEL1, "%s: no chip id\n", +- spi->dev.bus_id); +- return -ENODEV; +- } ++ if (data && data->type) { ++ for (i = 0, info = m25p_data; ++ i < ARRAY_SIZE(m25p_data); ++ i++, info++) { ++ if (strcmp(data->type, info->name) == 0) ++ break; + } -+ } + +- for (i = 0, info = m25p_data; i < ARRAY_SIZE(m25p_data); i++, info++) { +- if (strcmp(data->type, info->name) == 0) +- break; +- } +- if (i == ARRAY_SIZE(m25p_data)) { +- DEBUG(MTD_DEBUG_LEVEL1, "%s: unrecognized id %s\n", +- spi->dev.bus_id, data->type); ++ /* unrecognized chip? */ ++ if (i == ARRAY_SIZE(m25p_data)) { ++ DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", ++ spi->dev.bus_id, data->type); ++ info = NULL; + -+ /* Save the MFGPT MSRs */ -+ rdmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr); -+ rdmsrl(MFGPT_NR_MSR, mfgpt_nr_msr); ++ /* recognized; is that chip really what's there? */ ++ } else if (info->jedec_id) { ++ struct flash_info *chip = jedec_probe(spi); + -+ if (device_may_wakeup(&olpc_powerbutton_dev.dev)) -+ olpc_wakeup_mask |= CS5536_PM_PWRBTN; -+ else -+ olpc_wakeup_mask &= ~(CS5536_PM_PWRBTN); ++ if (!chip || chip != info) { ++ dev_warn(&spi->dev, "found %s, expected %s\n", ++ chip ? chip->name : "UNKNOWN", ++ info->name); ++ info = NULL; ++ } ++ } ++ } else ++ info = jedec_probe(spi); + -+ if (device_may_wakeup(&olpc_lid_dev.dev)) { -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ gpio_wake_events |= GPIO_WAKEUP_LID; ++ if (!info) + return -ENODEV; +- } + + flash = kzalloc(sizeof *flash, GFP_KERNEL); + if (!flash) + return -ENOMEM; + + flash->spi = spi; +- init_MUTEX(&flash->lock); ++ mutex_init(&flash->lock); + dev_set_drvdata(&spi->dev, flash); + +- if (data->name) ++ if (data && data->name) + flash->mtd.name = data->name; + else + flash->mtd.name = spi->dev.bus_id; +@@ -468,17 +584,25 @@ static int __devinit m25p_probe(struct spi_device *spi) + flash->mtd.writesize = 1; + flash->mtd.flags = MTD_CAP_NORFLASH; + flash->mtd.size = info->sector_size * info->n_sectors; +- flash->mtd.erasesize = info->sector_size; + flash->mtd.erase = m25p80_erase; + flash->mtd.read = m25p80_read; + flash->mtd.write = m25p80_write; + ++ /* prefer "small sector" erase if possible */ ++ if (info->flags & SECT_4K) { ++ flash->erase_opcode = OPCODE_BE_4K; ++ flash->mtd.erasesize = 4096; + } else { -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ gpio_wake_events &= ~(GPIO_WAKEUP_LID); -+ } -+} -+ -+static int olpc_pm_enter(suspend_state_t pm_state) -+{ -+ /* Only STR is supported */ -+ if (pm_state != PM_SUSPEND_MEM) -+ return -EINVAL; -+ -+ olpc_fixup_sleep(); -+ -+ /* Set the GPIO wakeup bits */ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ -+ /* Save CPU state */ -+ do_olpc_suspend_lowlevel(); -+ -+ olpc_fixup_wakeup(); -+ -+ /* Restore the SCI wakeup events */ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ -+ return 0; -+} -+ -+int asmlinkage olpc_do_sleep(u8 sleep_state) -+{ -+ void *pgd_addr = __va(read_cr3()); -+ printk(KERN_ERR "olpc_do_sleep!\n"); /* this needs to remain here so -+ * that gcc doesn't optimize -+ * away our __va! */ -+ /* FIXME: Set the SCI bits we want to wake up on here */ -+ -+ /* FIXME: Set any other SCI events that we might want here */ -+ -+ outl((olpc_wakeup_mask << 16) | 0xFFFF, acpi_base + PM1_STS); -+ -+ /* If we are in test mode, then just return (simulate a successful -+ suspend/resume). Otherwise, if we are doing the real thing, -+ then go for the gusto */ -+ -+ if (olpc_pm_mode != PM_MODE_TEST) { -+ __asm__ __volatile__("movl %0,%%eax" : : "r" (pgd_addr)); -+ __asm__("call *(%%edi); cld" -+ : : "D" (&ofw_bios_entry)); -+ } -+ -+ return 0; -+} -+ -+/* This code will slowly disappear as we fixup the issues in the BIOS */ -+ -+static void __init olpc_fixup_bios(void) -+{ -+ unsigned long hi, lo; -+ -+ if (olpc_has_vsa()) { -+ /* The VSA aggressively sets up the ACPI and PM register for -+ * trapping - its not enough to force these values in the BIOS - -+ * they seem to be changed during PCI init as well. -+ */ -+ -+ /* Change the PM registers to decode to the DD */ -+ -+ rdmsr(0x510100e2, lo, hi); -+ hi |= 0x80000000; -+ wrmsr(0x510100e2, lo, hi); -+ -+ /* Change the ACPI registers to decode to the DD */ -+ -+ rdmsr(0x510100e3, lo, hi); -+ hi |= 0x80000000; -+ wrmsr(0x510100e3, lo, hi); ++ flash->erase_opcode = OPCODE_SE; ++ flash->mtd.erasesize = info->sector_size; + } + -+ /* GPIO24 controls WORK_AUX */ -+ -+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_ENABLE); -+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_AUX1); -+ -+ if (olpc_get_rev() >= OLPC_REV_B2) { -+ /* GPIO10 is connected to the thermal alarm */ -+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_ENABLE); -+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_AUX1); -+ -+ /* Set up to get LID events */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_INPUT_ENABLE); -+ -+ /* Clear edge detection and event enable for now */ -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS); -+ -+ /* Set the LID to cause an PME event on group 6 */ -+ geode_gpio_event_pme(OLPC_GPIO_LID, 6); + dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, + flash->mtd.size / 1024); + + DEBUG(MTD_DEBUG_LEVEL2, +- "mtd .name = %s, .size = 0x%.8x (%uM) " +- ".erasesize = 0x%.8x (%uK) .numeraseregions = %d\n", ++ "mtd .name = %s, .size = 0x%.8x (%uMiB) " ++ ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", + flash->mtd.name, + flash->mtd.size, flash->mtd.size / (1024*1024), + flash->mtd.erasesize, flash->mtd.erasesize / 1024, +@@ -488,7 +612,7 @@ static int __devinit m25p_probe(struct spi_device *spi) + for (i = 0; i < flash->mtd.numeraseregions; i++) + DEBUG(MTD_DEBUG_LEVEL2, + "mtd.eraseregions[%d] = { .offset = 0x%.8x, " +- ".erasesize = 0x%.8x (%uK), " ++ ".erasesize = 0x%.8x (%uKiB), " + ".numblocks = %d }\n", + i, flash->mtd.eraseregions[i].offset, + flash->mtd.eraseregions[i].erasesize, +@@ -516,14 +640,14 @@ static int __devinit m25p_probe(struct spi_device *spi) + } + + if (nr_parts > 0) { +- for (i = 0; i < data->nr_parts; i++) { ++ for (i = 0; i < nr_parts; i++) { + DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " + "{.name = %s, .offset = 0x%.8x, " +- ".size = 0x%.8x (%uK) }\n", +- i, data->parts[i].name, +- data->parts[i].offset, +- data->parts[i].size, +- data->parts[i].size / 1024); ++ ".size = 0x%.8x (%uKiB) }\n", ++ i, parts[i].name, ++ parts[i].offset, ++ parts[i].size, ++ parts[i].size / 1024); + } + flash->partitioned = 1; + return add_mtd_partitions(&flash->mtd, parts, nr_parts); +@@ -560,6 +684,11 @@ static struct spi_driver m25p80_driver = { + }, + .probe = m25p_probe, + .remove = __devexit_p(m25p_remove), + -+ /* Set PME group 6 to fire the SCI interrupt */ -+ geode_gpio_set_irq(6, sci_irq); -+ } -+ -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_INPUT_ENABLE); -+ -+ /* Clear pending events */ -+ -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS); -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_POSITIVE_EDGE_STS); -+ -+ //geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_EN); -+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_EVENTS_ENABLE); -+ -+ /* Set the SCI to cause a PME event on group 7 */ -+ geode_gpio_event_pme(OLPC_GPIO_ECSCI, 7); -+ -+ /* And have group 6 also fire the SCI interrupt */ -+ geode_gpio_set_irq(7, sci_irq); -+} -+ -+/* This provides a control file for setting up testing of the -+ power management system. For now, there is just one setting: -+ "test" which means that we don't actually enter the power -+ off routine. -+*/ -+ -+static const char * const pm_states[] = { -+ [PM_MODE_NORMAL] = "normal", -+ [PM_MODE_TEST] = "test", -+}; -+ -+extern struct mutex pm_mutex; -+extern struct kset power_subsys; -+ -+static ssize_t control_show(struct kset *s, char *buf) -+{ -+ return sprintf(buf, "%s\n", pm_states[olpc_pm_mode]); -+} -+ -+static ssize_t control_store(struct kset *s, const char *buf, size_t n) -+{ -+ int i, len; -+ char *p; -+ -+ p = memchr(buf, '\n', n); -+ len = p ? p - buf : n; -+ -+ /* Grab the mutex */ -+ mutex_lock(&pm_mutex); -+ -+ for(i = 0; i < PM_MODE_MAX; i++) { -+ if (!strncmp(buf, pm_states[i], len)) { -+ olpc_pm_mode = i; -+ break; -+ } -+ } -+ -+ mutex_unlock(&pm_mutex); -+ -+ return (i == PM_MODE_MAX) ? -EINVAL : n; -+} -+ -+static struct subsys_attribute control_attr = { -+ .attr = { -+ .name = "olpc-pm", -+ .mode = 0644, -+ }, -+ .show = control_show, -+ .store = control_store, -+}; -+ -+static struct attribute * olpc_attributes[] = { -+ &control_attr.attr, -+ NULL -+}; -+ -+static struct attribute_group olpc_attrs = { -+ .attrs = olpc_attributes, -+}; -+ -+static int __init alloc_inputdevs(void) -+{ -+ int ret = -ENOMEM; -+ -+ pm_inputdev = input_allocate_device(); -+ if (!pm_inputdev) -+ goto err; -+ -+ pm_inputdev->name = "OLPC PM"; -+ pm_inputdev->phys = "olpc_pm/input0"; -+ set_bit(EV_KEY, pm_inputdev->evbit); -+ set_bit(KEY_POWER, pm_inputdev->keybit); -+ -+ ret = input_register_device(pm_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register PM input device: %d\n", ret); -+ goto err; -+ } -+ -+ lid_inputdev = input_allocate_device(); -+ if (!lid_inputdev) -+ goto err; -+ -+ lid_inputdev->name = "OLPC lid switch"; -+ lid_inputdev->phys = "olpc_pm/input1"; -+ set_bit(EV_SW, lid_inputdev->evbit); -+ set_bit(SW_LID, lid_inputdev->swbit); -+ -+ ret = input_register_device(lid_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register lid input device: %d\n", ret); -+ goto err; -+ } -+ -+ ebook_inputdev = input_allocate_device(); -+ if (!ebook_inputdev) -+ goto err; -+ -+ ebook_inputdev->name = "OLPC ebook switch"; -+ ebook_inputdev->phys = "olpc_pm/input2"; -+ set_bit(EV_SW, ebook_inputdev->evbit); -+ set_bit(SW_TABLET_MODE, ebook_inputdev->swbit); -+ -+ ret = input_register_device(ebook_inputdev); -+ if (ret) { -+ printk(KERN_ERR "olpc-pm: failed to register ebook input device: %d\n", ret); -+ goto err; -+ } -+ -+ return ret; -+err: -+ if (ebook_inputdev) { -+ input_unregister_device(ebook_inputdev); -+ ebook_inputdev = NULL; -+ } -+ if (lid_inputdev) { -+ input_unregister_device(lid_inputdev); -+ lid_inputdev = NULL; -+ } -+ if (pm_inputdev) { -+ input_unregister_device(pm_inputdev); -+ pm_inputdev = NULL; -+ } -+ -+ return ret; -+} -+ -+static int __init olpc_pm_init(void) -+{ -+ uint32_t lo, hi; -+ int ret; -+ uint8_t ec_byte; -+ -+ if (!machine_is_olpc()) -+ return -ENODEV; -+ -+ acpi_base = geode_acpi_base(); -+ pms_base = geode_pms_base(); -+ -+ if (!acpi_base || !pms_base) -+ return -ENODEV; -+ -+ ret = alloc_inputdevs(); -+ if (ret) -+ return ret; -+ -+ rdmsr(0x51400020, lo, hi); -+ sci_irq = (lo >> 20) & 15; -+ -+ if (sci_irq) { -+ printk(KERN_INFO "SCI is mapped to IRQ %d\n", sci_irq); -+ } else { -+ /* Zero doesn't mean zero -- it means masked */ -+ printk(KERN_INFO "SCI unmapped. Mapping to IRQ 3\n"); -+ sci_irq = 3; -+ lo |= 0x00300000; -+ wrmsrl(0x51400020, lo); -+ } -+ -+ olpc_fixup_bios(); -+ -+ lo = inl(pms_base + PM_FSD); -+ -+ /* Lock, enable failsafe, 4 seconds */ -+ outl(0xc001f400, pms_base + PM_FSD); -+ -+ /* Here we set up the SCI events we're interested in during -+ * real-time. We have no sleep button, and the RTC doesn't make -+ * sense, so set up the power button -+ */ -+ -+ outl(inl(acpi_base) | ((CS5536_PM_PWRBTN) << 16), acpi_base); -+ -+ if (olpc_get_rev() >= OLPC_REV_B2) { -+ gpio_wake_events |= GPIO_WAKEUP_LID; -+ -+ /* Get the current value of the GPIO, and set up the edges */ -+ olpc_lid_flag = geode_gpio_isset(OLPC_GPIO_LID, GPIO_READ_BACK); -+ -+ /* Watch for the opposite edge */ -+ -+ if (olpc_lid_flag) -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN); -+ else -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN); -+ -+ /* Enable the event */ -+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE); -+ } -+ -+ /* Set up the mask for wakeups the EC will generate SCIs on */ -+ -+ ret = olpc_ec_cmd(EC_READ_SCI_MASK, NULL, 0, &ec_byte, 1); -+ if (ret) -+ printk(KERN_ERR "Error getting the EC SCI mask: %d\n", ret); -+ -+ /* Disable battery 1% charge wakeups */ -+ ec_byte &= ~EC_SCI_SRC_BATSOC; -+ -+ ret = olpc_ec_cmd(EC_WRITE_SCI_MASK, &ec_byte, 1, NULL, 0); -+ if (ret) -+ printk(KERN_ERR "Error setting the EC SCI mask: %d\n", ret); -+ -+ /* Set up the EC SCI */ -+ -+ gpio_wake_events |= GPIO_WAKEUP_EC; -+ -+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN); -+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS); -+ -+ /* Select level triggered in PIC */ -+ -+ if (sci_irq < 8) { -+ lo = inb(0x4d0); -+ lo |= 1 << sci_irq; -+ outb(lo, 0x4d0); -+ } else { -+ lo = inb(0x4d1); -+ lo |= 1 << (sci_irq - 8); -+ outb(lo, 0x4d1); -+ } -+ /* Clear pending interrupt */ -+ outl(inl(acpi_base) | 0xFFFF, acpi_base); -+ process_sci_queue(0); /* we just want to flush the queue here */ -+ init_ebook_state(); -+ -+ /* Enable the interrupt */ -+ -+ ret = request_irq(sci_irq, &olpc_pm_interrupt, 0, "SCI", &acpi_base); -+ -+ if (ret) { -+ printk(KERN_ERR "Error registering SCI: %d\n", ret); -+ return ret; -+ } -+ -+ ofw_bios_entry.address = 0xF0000 + PAGE_OFFSET; -+ pm_set_ops(&olpc_pm_ops); -+ -+ sysfs_create_group(&power_subsys.kobj, &olpc_attrs); -+ -+ return 0; -+} -+ -+ -+#if defined (CONFIG_RTC_DRV_CMOS) || defined (CONFIG_RTC_DRV_CMOS_MODULE) -+struct resource rtc_platform_resource[2] = { -+ { -+ .flags = IORESOURCE_IO, -+ .start = RTC_PORT(0), -+ .end = RTC_PORT(0) + RTC_IO_EXTENT -+ }, -+ { -+ .flags = IORESOURCE_IRQ, -+ .start = 8, -+ .end = 8, -+ }, -+}; -+ -+ -+static void rtc_wake_on(struct device *dev) -+{ -+ olpc_wakeup_mask |= CS5536_PM_RTC; -+} -+ -+static void rtc_wake_off(struct device *dev) -+{ -+ olpc_wakeup_mask &= ~(CS5536_PM_RTC); -+} -+ -+static struct cmos_rtc_board_info rtc_info = { -+ .rtc_day_alarm = 0, -+ .rtc_mon_alarm = 0, -+ .rtc_century = 0, -+ .wake_on = rtc_wake_on, -+ .wake_off = rtc_wake_off, -+}; -+ -+struct platform_device olpc_rtc_device = { -+ .name = "rtc_cmos", -+ .id = -1, -+ .num_resources = ARRAY_SIZE(rtc_platform_resource), -+ .dev.platform_data = &rtc_info, -+ .resource = rtc_platform_resource, -+}; -+ -+static int __init olpc_platform_init(void) -+{ -+ (void)platform_device_register(&olpc_rtc_device); -+ device_init_wakeup(&olpc_rtc_device.dev, 1); -+ -+ (void)platform_device_register(&olpc_powerbutton_dev); -+ device_init_wakeup(&olpc_powerbutton_dev.dev, 1); -+ -+ (void)platform_device_register(&olpc_lid_dev); -+ device_init_wakeup(&olpc_lid_dev.dev, 1); -+ -+ return 0; -+} -+arch_initcall(olpc_platform_init); -+#endif /* CONFIG_RTC_DRV_CMOS */ -+ -+static void olpc_pm_exit(void) -+{ -+ /* Clear any pending events, and disable them */ -+ outl(0xFFFF, acpi_base+2); -+ -+ free_irq(sci_irq, &acpi_base); -+ input_unregister_device(pm_inputdev); -+ input_unregister_device(lid_inputdev); -+ input_unregister_device(ebook_inputdev); -+} -+ -+static struct pm_ops olpc_pm_ops = { -+ .valid = olpc_pm_state_valid, -+ .enter = olpc_pm_enter, -+}; -+ -+module_init(olpc_pm_init); -+module_exit(olpc_pm_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("David Woodhouse "); -+MODULE_DESCRIPTION("AMD Geode power management for OLPC CL1"); -diff --git a/arch/i386/kernel/olpc-sleep.S b/arch/i386/kernel/olpc-sleep.S -new file mode 100644 -index 0000000..9535c9a ---- /dev/null -+++ b/arch/i386/kernel/olpc-sleep.S -@@ -0,0 +1,39 @@ -+.text -+ -+ENTRY(olpc_sleep_asm) -+olpc_sleep: -+ ;; Get the value of PM1_CNT and store it off -+ -+ add 08h, ax -+ mov bx,dx -+ in dx,eax -+ or 2000h, ax -+ mov ax,di -+ -+ ;; flush the cache -+ wbinvd -+ -+ ;; GX2 must disable refresh before going into self-refresh -+ mov 2000000180xh, ecx -+ rdmsr -+ mov eax, esi -+ and 0FF0000FFh, eax -+ wrmsr -+ -+ ;; Now, put the memory into self refresh -+ mov 2004, cx -+ xor edx, edx -+ xor eax, eax -+ mov 04h, al -+ wrmsr -+ -+ ;; Thats all she wrote - time to go to sleep -+ -+ mov bx, dx -+ movzx di, eax -+ out eax, dx -+ -+ ;; -+ -+ -+ -diff --git a/arch/i386/kernel/olpc-wakeup.S b/arch/i386/kernel/olpc-wakeup.S -new file mode 100644 -index 0000000..a92cc61 ---- /dev/null -+++ b/arch/i386/kernel/olpc-wakeup.S -@@ -0,0 +1,122 @@ -+.text -+#include -+#include -+#include -+ -+ALIGN -+ .align 4096 -+ -+wakeup_start: -+# jmp wakeup_start -+ -+ cli -+ cld -+ -+ # Clear any dangerous flags -+ -+ pushl $0 -+ popfl -+ -+ # Set up %cr3 -+ movl $swsusp_pg_dir - __PAGE_OFFSET, %eax -+ movl %eax, %cr3 -+ -+ movl saved_cr4, %eax -+ movl %eax, %cr4 -+ -+ movl saved_cr0, %eax -+ movl %eax, %cr0 -+ -+ jmp 1f -+1: -+ ljmpl $__KERNEL_CS,$wakeup_return -+ -+ -+.org 0x1000 -+ -+wakeup_return: -+ movw $__KERNEL_DS, %ax -+ movw %ax, %ss -+ movw %ax, %ds -+ movw %ax, %es -+ movw %ax, %fs -+ movw %ax, %gs -+ -+ lgdt saved_gdt -+ lidt saved_idt -+ lldt saved_ldt -+ ljmp $(__KERNEL_CS),$1f -+1: -+ movl %cr3, %eax -+ movl %eax, %cr3 -+ wbinvd -+ -+ # Go back to the return point -+ jmp ret_point -+ -+save_registers: -+ sgdt saved_gdt -+ sidt saved_idt -+ sldt saved_ldt -+ -+ pushl %edx -+ movl %cr4, %edx -+ movl %edx, saved_cr4 -+ -+ movl %cr0, %edx -+ movl %edx, saved_cr0 -+ -+ popl %edx -+ -+ -+ movl %ebx, saved_context_ebx -+ movl %ebp, saved_context_ebp -+ movl %esi, saved_context_esi -+ movl %edi, saved_context_edi -+ -+ pushfl -+ popl saved_context_eflags -+ -+ ret -+ -+ -+restore_registers: -+ movl saved_context_ebp, %ebp -+ movl saved_context_ebx, %ebx -+ movl saved_context_esi, %esi -+ movl saved_context_edi, %edi -+ -+ pushl saved_context_eflags -+ popfl -+ -+ ret -+ -+ -+ENTRY(do_olpc_suspend_lowlevel) -+ call save_processor_state -+ call save_registers -+ -+ # This is the stack context we want to remember -+ movl %esp, saved_context_esp -+ -+ pushl $3 -+ call olpc_do_sleep -+ -+ jmp wakeup_start -+ .p2align 4,,7 -+ret_point: -+ movl saved_context_esp, %esp -+ -+ call restore_registers -+ call restore_processor_state -+ ret -+ -+.data -+ALIGN -+ -+saved_gdt: .long 0,0 -+saved_idt: .long 0,0 -+saved_ldt: .long 0 -+saved_cr4: .long 0 -+saved_cr0: .long 0 -+ -diff --git a/arch/i386/kernel/olpc.c b/arch/i386/kernel/olpc.c -new file mode 100644 -index 0000000..d540cb0 ---- /dev/null -+++ b/arch/i386/kernel/olpc.c -@@ -0,0 +1,320 @@ -+/* Support for the OLPC DCON and OLPC EC access -+ * Copyright (C) 2006, Advanced Micro Devices, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* This is our new multi-purpose structure used to contain the -+ * information about the platform that we detect -+ */ -+ -+struct olpc_platform_t olpc_platform_info; -+EXPORT_SYMBOL_GPL(olpc_platform_info); -+ -+/********************************************************************* -+ * EC locking and access -+ *********************************************************************/ -+ -+static DEFINE_SPINLOCK(ec_lock); -+ -+/* what the timeout *should* be (in ms) */ -+#define EC_BASE_TIMEOUT 20 -+ -+/* the timeout that bugs in the EC might force us to actually use */ -+static int ec_timeout = EC_BASE_TIMEOUT; -+ -+static int __init olpc_ec_timeout_set(char *str) -+{ -+ if (get_option(&str, &ec_timeout) != 1) { -+ ec_timeout = EC_BASE_TIMEOUT; -+ printk(KERN_ERR "olpc-ec: invalid argument to " -+ "'olpc_ec_timeout=', ignoring!\n"); -+ } -+ printk(KERN_DEBUG "olpc-ec: using %d ms delay for EC commands.\n", -+ ec_timeout); -+ return 1; -+} -+__setup("olpc_ec_timeout=", olpc_ec_timeout_set); -+ -+/* -+ * These *bf_status functions return whether the buffers are full or not. -+ */ -+ -+static inline unsigned int ibf_status(unsigned int port) -+{ -+ return inb(port) & 0x02; -+} -+ -+static inline unsigned int obf_status(unsigned int port) -+{ -+ return inb(port) & 0x01; -+} -+ -+#define wait_on_ibf(p, d) __wait_on_ibf(__LINE__, (p), (d)) -+static int __wait_on_ibf(unsigned int line, unsigned int port, int desired) -+{ -+ unsigned int timeo; -+ int state = ibf_status(port); -+ -+ for (timeo = ec_timeout; state != desired && timeo; timeo--) { -+ mdelay(1); -+ state = ibf_status(port); -+ } -+ -+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) && -+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) { -+ printk(KERN_WARNING "olpc-ec: waited %u ms for IBF (%d)!\n", -+ EC_BASE_TIMEOUT-timeo, line); -+ } -+ -+ return !(state == desired); -+} -+ -+#define wait_on_obf(p, d) __wait_on_obf(__LINE__, (p), (d)) -+static int __wait_on_obf(unsigned int line, unsigned int port, int desired) -+{ -+ unsigned int timeo; -+ int state = obf_status(port); -+ -+ for (timeo = ec_timeout; state != desired && timeo; timeo--) { -+ mdelay(1); -+ state = obf_status(port); -+ } -+ -+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) && -+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) { -+ printk(KERN_WARNING "olpc-ec: waited %u ms for OBF (%d)!\n", -+ EC_BASE_TIMEOUT-timeo, line); -+ } -+ -+ return !(state == desired); -+} -+ -+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, -+ unsigned char *outbuf, size_t outlen) -+{ -+ unsigned long flags; -+ int ret = -EIO; -+ int i; -+ -+ spin_lock_irqsave(&ec_lock, flags); -+ -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to " -+ "quiesce!\n"); -+ goto err; -+ } -+ -+restart: -+ /* -+ * Note that if we time out during any IBF checks, that's a failure; -+ * we have to return. There's no way for the kernel to clear that. -+ * -+ * If we time out during an OBF check, we can restart the command; -+ * reissuing it will clear the OBF flag, and we should be alright. -+ * The OBF flag will sometimes misbehave due to what we believe -+ * is a hardware quirk.. -+ */ -+ printk(KERN_DEBUG "olpc-ec: running cmd 0x%x\n", cmd); -+ outb(cmd, 0x6c); -+ -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to read " -+ "command!\n"); -+ goto err; -+ } -+ -+ if (inbuf && inlen) { -+ /* write data to EC */ -+ for (i = 0; i < inlen; i++) { -+ if (wait_on_ibf(0x6c, 0)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for" -+ " EC accept data!\n"); -+ goto err; -+ } -+ printk(KERN_DEBUG "olpc-ec: sending cmd arg 0x%x\n", -+ inbuf[i]); -+ outb(inbuf[i], 0x68); -+ } -+ } -+ if (outbuf && outlen) { -+ /* read data from EC */ -+ for (i = 0; i < outlen; i++) { -+ if (wait_on_obf(0x6c, 1)) { -+ printk(KERN_ERR "olpc-ec: timeout waiting for" -+ " EC to provide data!\n"); -+ goto restart; -+ } -+ outbuf[i] = inb(0x68); -+ printk(KERN_DEBUG "olpc-ec: received 0x%x\n", -+ outbuf[i]); -+ } -+ } -+ -+ ret = 0; -+err: -+ spin_unlock_irqrestore(&ec_lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(olpc_ec_cmd); -+ -+/********************************************************************* -+ * DCON stuff -+ *********************************************************************/ -+ -+static void olpc_power_off(void) -+{ -+ printk(KERN_INFO "OLPC power off sequence...\n"); -+ outb(0xff, 0x381); -+ outb(0x14, 0x382); -+ outb(0x01, 0x383); -+ outb(0xff, 0x381); -+ outb(0x14, 0x382); -+ outb(0x00, 0x383); -+} -+ -+static void __init -+ec_detect(void) -+{ -+ olpc_ec_cmd(0x08, NULL, 0, (unsigned char *) &olpc_platform_info.ecver, 1); -+} -+ -+/* Check to see if this version of the OLPC board has VSA built -+ * in, and set a flag -+ */ -+ -+static void __init vsa_detect(void) -+{ -+ u16 rev; -+ -+ outw(0xFC53, 0xAC1C); -+ outw(0x0003, 0xAC1C); -+ -+ rev = inw(0xAC1E); -+ -+ if (rev == 0x4132) -+ olpc_platform_info.flags |= OLPC_F_VSA; -+} -+ -+/* Map OFW revisions to what OLPC_REV_* */ -+static const char __initdata *olpc_boardrev_str[] = { -+ "A1", -+ "preB1", -+ "B1", -+ "preB2", -+ "B2", -+ "preB3", -+ "B3", -+ "B4", -+ "C1", -+ "R1", -+}; -+ -+static void __init platform_detect(char *revision, size_t len) -+{ -+ size_t propsize; -+ int i; -+ -+ BUG_ON(ARRAY_SIZE(olpc_boardrev_str) != OLPC_REV_UNKNOWN); -+ -+ if (ofw("getprop", 4, 1, NULL, "model", revision, len, &propsize)) { -+ printk(KERN_ERR "ofw: getprop call failed!\n"); -+ goto failed; -+ } -+ if (len < propsize) { -+ printk(KERN_ERR "ofw: revision string is too long!\n"); -+ goto failed; -+ } -+ -+ for (i=0; i < ARRAY_SIZE(olpc_boardrev_str); i++) { -+ if (strcmp(revision, olpc_boardrev_str[i]) == 0) { -+ olpc_platform_info.boardrev = i; -+ return; -+ } -+ } -+ -+failed: -+ strncpy(revision, "Unknown", len); -+ olpc_platform_info.boardrev = OLPC_REV_UNKNOWN; -+} -+ -+static int olpc_dcon_present = -1; -+module_param(olpc_dcon_present, int, 0444); -+ -+/* REV_A CMOS map: -+ * bit 440; DCON present bit -+ */ -+ -+#define OLPC_CMOS_DCON_OFFSET (440 / 8) -+#define OLPC_CMOS_DCON_MASK 0x01 -+ -+static int __init olpc_init(void) -+{ -+ unsigned char *romsig; -+ char revision[10]; -+ -+ spin_lock_init(&ec_lock); -+ -+ romsig = ioremap(0xffffffc0, 16); -+ -+ if (!romsig) -+ return 0; -+ -+ if (strncmp(romsig, "CL1 Q", 7)) -+ goto unmap; -+ if (strncmp(romsig+6, romsig+13, 3)) { -+ printk(KERN_INFO "OLPC BIOS signature looks invalid. Assuming not OLPC\n"); -+ goto unmap; -+ } -+ printk(KERN_INFO "OLPC board with OpenFirmware: %.16s\n", romsig); -+ -+ olpc_platform_info.flags |= OLPC_F_PRESENT; -+ -+ pm_power_off = olpc_power_off; -+ -+ /* Get the platform revision */ -+ platform_detect(revision, sizeof(revision)); -+ -+ /* If olpc_dcon_present isn't set by the command line, then -+ * "detect" it -+ */ -+ -+ if (olpc_dcon_present == -1) { -+ /* B1 and greater always has a DCON */ -+ if (olpc_platform_info.boardrev >= OLPC_REV_B1 && -+ olpc_platform_info.boardrev < OLPC_REV_UNKNOWN) -+ olpc_dcon_present = 1; -+ } -+ -+ if (olpc_dcon_present) -+ olpc_platform_info.flags |= OLPC_F_DCON; -+ -+ /* Get the EC revision */ -+ ec_detect(); -+ -+ /* Check to see if the VSA exists */ -+ vsa_detect(); -+ -+ printk(KERN_INFO "OLPC board revision: %s (EC=%x)\n", revision, -+ olpc_platform_info.ecver); -+ -+ unmap: -+ iounmap(romsig); -+ -+ return 0; -+} -+ -+postcore_initcall(olpc_init); -diff --git a/arch/i386/kernel/prom.c b/arch/i386/kernel/prom.c -new file mode 100644 -index 0000000..d64bb27 ---- /dev/null -+++ b/arch/i386/kernel/prom.c -@@ -0,0 +1,478 @@ -+/* -+ * Procedures for creating, accessing and interpreting the device tree. -+ * -+ * Paul Mackerras August 1996. -+ * Copyright (C) 1996-2005 Paul Mackerras. -+ * -+ * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner. -+ * {engebret|bergner}@us.ibm.com -+ * -+ * Adapted for sparc64 by David S. Miller davem@davemloft.net -+ * -+ * Adapter for i386/OLPC by Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * XXX: This is very much a stub; right now we're keeping 2 device trees -+ * in memory (one for promfs, and one here). That will not remain -+ * for long! -+ */ -+ -+static struct device_node *allnodes; -+ -+/* use when traversing tree through the allnext, child, sibling, -+ * or parent members of struct device_node. -+ */ -+static DEFINE_RWLOCK(devtree_lock); -+ -+int of_device_is_compatible(const struct device_node *device, -+ const char *compat) -+{ -+ const char* cp; -+ int cplen, l; -+ -+ cp = of_get_property(device, "compatible", &cplen); -+ if (cp == NULL) -+ return 0; -+ while (cplen > 0) { -+ if (strncmp(cp, compat, strlen(compat)) == 0) -+ return 1; -+ l = strlen(cp) + 1; -+ cp += l; -+ cplen -= l; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(of_device_is_compatible); -+ -+struct device_node *of_get_parent(const struct device_node *node) -+{ -+ struct device_node *np; -+ -+ if (!node) -+ return NULL; -+ -+ np = node->parent; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_get_parent); -+ -+struct device_node *of_get_next_child(const struct device_node *node, -+ struct device_node *prev) -+{ -+ struct device_node *next; -+ -+ next = prev ? prev->sibling : node->child; -+ for (; next != 0; next = next->sibling) { -+ break; -+ } -+ -+ return next; -+} -+EXPORT_SYMBOL(of_get_next_child); -+ -+struct device_node *of_find_node_by_path(const char *path) -+{ -+ struct device_node *np = allnodes; -+ -+ for (; np != 0; np = np->allnext) { -+ if (np->full_name != 0 && strcmp(np->full_name, path) == 0) -+ break; -+ } -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_path); -+ -+struct device_node *of_find_node_by_phandle(phandle handle) -+{ -+ struct device_node *np; -+ -+ for (np = allnodes; np != 0; np = np->allnext) -+ if (np->node == handle) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_phandle); -+ -+struct device_node *of_find_node_by_name(struct device_node *from, -+ const char *name) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != NULL; np = np->allnext) -+ if (np->name != NULL && strcmp(np->name, name) == 0) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_name); -+ -+struct device_node *of_find_node_by_type(struct device_node *from, -+ const char *type) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != 0; np = np->allnext) -+ if (np->type != 0 && strcmp(np->type, type) == 0) -+ break; -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_node_by_type); -+ -+struct device_node *of_find_compatible_node(struct device_node *from, -+ const char *type, const char *compatible) -+{ -+ struct device_node *np; -+ -+ np = from ? from->allnext : allnodes; -+ for (; np != 0; np = np->allnext) { -+ if (type != NULL -+ && !(np->type != 0 && strcmp(np->type, type) == 0)) -+ continue; -+ if (of_device_is_compatible(np, compatible)) -+ break; -+ } -+ -+ return np; -+} -+EXPORT_SYMBOL(of_find_compatible_node); -+ -+struct property *of_find_property(const struct device_node *np, -+ const char *name, -+ int *lenp) -+{ -+ struct property *pp; -+ -+ for (pp = np->properties; pp != 0; pp = pp->next) { -+ if (strcasecmp(pp->name, name) == 0) { -+ if (lenp != 0) -+ *lenp = pp->length; -+ break; -+ } -+ } -+ return pp; -+} -+EXPORT_SYMBOL(of_find_property); -+ -+/* -+ * Find a property with a given name for a given node -+ * and return the value. -+ */ -+const void *of_get_property(const struct device_node *np, const char *name, -+ int *lenp) -+{ -+ struct property *pp = of_find_property(np,name,lenp); -+ return pp ? pp->value : NULL; -+} -+EXPORT_SYMBOL(of_get_property); -+ -+int of_getintprop_default(struct device_node *np, const char *name, int def) -+{ -+ struct property *prop; -+ int len; -+ -+ prop = of_find_property(np, name, &len); -+ if (!prop || len != 4) -+ return def; -+ -+ return *(int *) prop->value; -+} -+EXPORT_SYMBOL(of_getintprop_default); -+ -+int of_n_addr_cells(struct device_node *np) -+{ -+ const int* ip; -+ do { -+ if (np->parent) -+ np = np->parent; -+ ip = of_get_property(np, "#address-cells", NULL); -+ if (ip != NULL) -+ return *ip; -+ } while (np->parent); -+ /* No #address-cells property for the root node, default to 2 */ -+ return 2; -+} -+EXPORT_SYMBOL(of_n_addr_cells); -+ -+int of_n_size_cells(struct device_node *np) -+{ -+ const int* ip; -+ do { -+ if (np->parent) -+ np = np->parent; -+ ip = of_get_property(np, "#size-cells", NULL); -+ if (ip != NULL) -+ return *ip; -+ } while (np->parent); -+ /* No #size-cells property for the root node, default to 1 */ -+ return 1; -+} -+EXPORT_SYMBOL(of_n_size_cells); -+ -+int of_set_property(struct device_node *dp, const char *name, void *val, int len) -+{ -+ return -EIO; -+} -+EXPORT_SYMBOL(of_set_property); -+ -+static unsigned int prom_early_allocated; -+ -+static void * __init prom_early_alloc(unsigned long size) -+{ -+ void *ret; -+ -+ ret = kmalloc(size, GFP_KERNEL); -+ if (ret != NULL) -+ memset(ret, 0, size); -+ else -+ printk(KERN_ERR "ACK! couldn't allocate prom memory!\n"); -+ -+ prom_early_allocated += size; -+ -+ return ret; -+} -+ -+static int is_root_node(const struct device_node *dp) -+{ -+ if (!dp) -+ return 0; -+ -+ return (dp->parent == NULL); -+} -+ -+static char * __init build_path_component(struct device_node *dp) -+{ -+ int pathlen; -+ char *n, *i; -+ -+ if (ofw("package-to-path", 3, 1, dp->node, NULL, 0, &pathlen)) { -+ printk(KERN_ERR "PROM: unable to get path name from OFW!\n"); -+ return "ERROR"; -+ } -+ n = prom_early_alloc(pathlen + 1); -+ if (ofw("package-to-path", 3, 1, dp->node, n, pathlen+1, &pathlen)) -+ printk(KERN_ERR "PROM: unable to get path name from OFW\n"); -+ -+ if ((i = strrchr(n, '/'))) -+ n = ++i; /* we only want the file name */ -+ return n; -+} -+ -+static char * __init build_full_name(struct device_node *dp) -+{ -+ int len, ourlen, plen; -+ char *n; -+ -+ plen = strlen(dp->parent->full_name); -+ ourlen = strlen(dp->path_component_name); -+ len = ourlen + plen + 2; -+ -+ n = prom_early_alloc(len); -+ strcpy(n, dp->parent->full_name); -+ if (!is_root_node(dp->parent)) { -+ strcpy(n + plen, "/"); -+ plen++; -+ } -+ strcpy(n + plen, dp->path_component_name); -+ -+ return n; -+} -+ -+static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len) -+{ -+ static struct property *tmp = NULL; -+ struct property *p; -+ -+ if (tmp) { -+ p = tmp; -+ memset(p, 0, sizeof(*p) + 32); -+ tmp = NULL; -+ } else { -+ p = prom_early_alloc(sizeof(struct property) + 32); -+ } -+ -+ p->name = (char *) (p + 1); -+ if (special_name) { -+ strcpy(p->name, special_name); -+ p->length = special_len; -+ p->value = prom_early_alloc(special_len); -+ memcpy(p->value, special_val, special_len); -+ } else { -+ int fl; -+ if (prev == NULL) { -+ if (ofw("nextprop", 3, 1, node, "", p->name, &fl)) { -+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__); -+ return NULL; -+ } -+ } else { -+ if (ofw("nextprop", 3, 1, node, prev, p->name, &fl)) { -+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__); -+ return NULL; -+ } -+ } -+ if (strlen(p->name) == 0 || fl != 1) { -+ tmp = p; -+ return NULL; -+ } -+ if (ofw("getproplen", 2, 1, node, p->name, &p->length)) { -+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__); -+ return NULL; -+ } -+ if (p->length <= 0) { -+ p->length = 0; -+ } else { -+ p->value = prom_early_alloc(p->length + 1); -+ if (ofw("getprop", 4, 1, node, p->name, p->value, p->length, &p->length)) { -+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__); -+ return NULL; -+ } -+ ((unsigned char *)p->value)[p->length] = '\0'; -+ } -+ } -+ return p; -+} -+ -+static struct property * __init build_prop_list(phandle node) -+{ -+ struct property *head, *tail; -+ -+ head = tail = build_one_prop(node, NULL, -+ ".node", &node, sizeof(node)); -+ -+ tail->next = build_one_prop(node, NULL, NULL, NULL, 0); -+ tail = tail->next; -+ while(tail) { -+ tail->next = build_one_prop(node, tail->name, -+ NULL, NULL, 0); -+ tail = tail->next; -+ } -+ -+ return head; -+} -+ -+static char * __init get_one_property(phandle node, const char *name) -+{ -+ char *buf = ""; -+ int len; -+ -+ if (ofw("getproplen", 2, 1, node, name, &len)) { -+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__); -+ return NULL; -+ } -+ if (len > 0) { -+ buf = prom_early_alloc(len); -+ if (ofw("getprop", 4, 1, node, name, buf, len, &len)) { -+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__); -+ return NULL; -+ } -+ } -+ -+ return buf; -+} -+ -+static struct device_node * __init create_node(phandle node, struct device_node *parent) -+{ -+ struct device_node *dp; -+ -+ if (!node) -+ return NULL; -+ -+ dp = prom_early_alloc(sizeof(*dp)); -+ dp->parent = parent; -+ -+ kref_init(&dp->kref); -+ -+ dp->name = get_one_property(node, "name"); -+ dp->type = get_one_property(node, "device_type"); -+ dp->node = node; -+ -+ dp->properties = build_prop_list(node); -+ -+ return dp; -+} -+ -+static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp) -+{ -+ struct device_node *ret = NULL, *prev_sibling = NULL; -+ struct device_node *dp; -+ u32 child; -+ -+ while (1) { -+ dp = create_node(node, parent); -+ if (!dp) -+ break; -+ -+ if (prev_sibling) -+ prev_sibling->sibling = dp; -+ -+ if (!ret) -+ ret = dp; -+ prev_sibling = dp; -+ -+ *(*nextp) = dp; -+ *nextp = &dp->allnext; -+ -+ dp->path_component_name = build_path_component(dp); -+ dp->full_name = build_full_name(dp); -+ -+ if (ofw("child", 1, 1, node, &child)) { -+ printk(KERN_ERR "PROM: %s: fetching child failed!\n", __func__); -+ return NULL; -+ } -+ dp->child = build_tree(dp, child, nextp); -+ -+ if (ofw("peer", 1, 1, node, &node)) { -+ printk(KERN_ERR "PROM: %s: fetching peer failed!\n", __func__); -+ return NULL; -+ } -+ } -+ -+ return ret; -+} -+ -+static phandle root_node; -+ -+void __init prom_build_devicetree(void) -+{ -+ struct device_node **nextp; -+ u32 child; -+ -+ if (ofw("peer", 1, 1, 0, &root_node)) { -+ printk(KERN_ERR "PROM: unable to get root node from OFW!\n"); -+ return; -+ } -+ -+ allnodes = create_node(root_node, NULL); -+ allnodes->path_component_name = ""; -+ allnodes->full_name = "/"; -+ -+ nextp = &allnodes->allnext; -+ if (ofw("child", 1, 1, allnodes->node, &child)) { -+ printk(KERN_ERR "PROM: unable to get child node from OFW!\n"); -+ return; -+ } -+ allnodes->child = build_tree(allnodes, child, &nextp); -+ printk("PROM: Built device tree with %u bytes of memory.\n", -+ prom_early_allocated); -+} -diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c -index d474cd6..c4b26ba 100644 ---- a/arch/i386/kernel/setup.c -+++ b/arch/i386/kernel/setup.c -@@ -362,8 +362,10 @@ void __init zone_sizes_init(void) - { - unsigned long max_zone_pfns[MAX_NR_ZONES]; - memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); -+#ifdef CONFIG_ZONE_DMA - max_zone_pfns[ZONE_DMA] = - virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; -+#endif - max_zone_pfns[ZONE_NORMAL] = max_low_pfn; - #ifdef CONFIG_HIGHMEM - max_zone_pfns[ZONE_HIGHMEM] = highend_pfn; -@@ -428,6 +430,9 @@ void __init setup_bootmem_allocator(void) - */ - acpi_reserve_bootmem(); - #endif -+#ifdef CONFIG_OLPC_PM -+ reserve_bootmem(0xf0000, PAGE_SIZE); -+#endif - #ifdef CONFIG_X86_FIND_SMP_CONFIG - /* - * Find and reserve possible boot-time SMP configuration: -diff --git a/arch/i386/pci/Makefile b/arch/i386/pci/Makefile -index 44650e0..1250a7b 100644 ---- a/arch/i386/pci/Makefile -+++ b/arch/i386/pci/Makefile -@@ -3,6 +3,7 @@ obj-y := i386.o init.o - obj-$(CONFIG_PCI_BIOS) += pcbios.o - obj-$(CONFIG_PCI_MMCONFIG) += mmconfig.o direct.o mmconfig-shared.o - obj-$(CONFIG_PCI_DIRECT) += direct.o -+obj-$(CONFIG_PCI_OLPC) += olpc.o - - pci-y := fixup.o - pci-$(CONFIG_ACPI) += acpi.o -diff --git a/arch/i386/pci/init.c b/arch/i386/pci/init.c -index 3de9f9b..0f5f7dd 100644 ---- a/arch/i386/pci/init.c -+++ b/arch/i386/pci/init.c -@@ -14,6 +14,9 @@ static __init int pci_access_init(void) - #ifdef CONFIG_PCI_MMCONFIG - pci_mmcfg_init(type); - #endif -+#ifdef CONFIG_PCI_OLPC -+ pci_olpc_init(); -+#endif - if (raw_pci_ops) - return 0; - #ifdef CONFIG_PCI_BIOS -diff --git a/arch/i386/pci/olpc.c b/arch/i386/pci/olpc.c -new file mode 100644 -index 0000000..1518d25 ---- /dev/null -+++ b/arch/i386/pci/olpc.c -@@ -0,0 +1,298 @@ -+/* -+ * olpcpci.c - Low-level PCI config space access for OLPC systems -+ * without the VSA PCI virtualization software. -+ * -+ * The AMD Geode chipset (GX2 processor, cs5536 I/O companion device) -+ * has some I/O functions (display, southbridge, sound, USB HCIs, etc) -+ * that more or less behave like PCI devices, but the hardware doesn't -+ * directly implement the PCI configuration space headers. AMD provides -+ * "VSA" (Virtual System Architecture) software that emulates PCI config -+ * space for these devices, by trapping I/O accesses to PCI config register -+ * (CF8/CFC) and running some code in System Management Mode interrupt state. -+ * On the OLPC platform, we don't want to use that VSA code because -+ * (a) it slows down suspend/resume, and (b) recompiling it requires special -+ * compilers that are hard to get. So instead of letting the complex VSA -+ * code simulate the PCI config registers for the on-chip devices, we -+ * just simulate them the easy way, by inserting the code into the -+ * pci_write_config and pci_read_config path. Most of the config registers -+ * are read-only anyway, so the bulk of the simulation is just table lookup. -+ */ -+ -+#include -+#include -+#include -+#include -+#include "pci.h" -+ -+static int is_lx; -+ -+/* -+ * In the tables below, the first two line (8 longwords) are the -+ * size masks that are used when the higher level PCI code determines -+ * the size of the region by writing ~0 to a base address register -+ * and reading back the result. -+ * -+ * The following lines are the values that are read during normal -+ * PCI config access cycles, i.e. not after just having written -+ * ~0 to a base address register. -+ */ -+ -+static const u32 lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x281022 , 0x2200005 , 0x6000021 , 0x80f808 , /* AMD Vendor ID */ -+ 0x0 , 0x0 , 0x0 , 0x0 , /* No virtual registers, hence no BAR for them */ -+ 0x0 , 0x0 , 0x0 , 0x28100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ -+ 0xfffffffd , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x28100b , 0x2200005 , 0x6000021 , 0x80f808 , /* NSC Vendor ID */ -+ 0xac1d , 0x0 , 0x0 , 0x0 , /* I/O BAR - base of virtual registers */ -+ 0x0 , 0x0 , 0x0 , 0x28100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ -+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20811022 , 0x2200003 , 0x3000000 , 0x0 , /* AMD Vendor ID */ -+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */ -+ 0xfe00c000 , 0x0 , 0x0 , 0x30100b , /* VIP */ -+ 0x0 , 0x0 , 0x0 , 0x10e , /* INTA, IRQ14 for graphics accel */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ -+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x30100b , 0x2200003 , 0x3000000 , 0x0 , /* NSC Vendor ID */ -+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */ -+ 0x0 , 0x0 , 0x0 , 0x30100b , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */ -+ 0xffffc000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20821022 , 0x2a00006 , 0x10100000 , 0x8 , /* NSC Vendor ID */ -+ 0xfe010000 , 0x0 , 0x0 , 0x0 , /* AES registers */ -+ 0x0 , 0x0 , 0x0 , 0x20821022 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+ -+static const u32 isa_hdr[] = { /* dev f function 0 - devfn = 78 */ -+ 0xfffffff9 , 0xffffff01 , 0xffffffc1 , 0xffffffe1 , -+ 0xffffff81 , 0xffffffc1 , 0x0 , 0x0 , -+ -+ 0x20901022 , 0x2a00049 , 0x6010003 , 0x802000 , -+ 0x18b1 , 0x1001 , 0x1801 , 0x1881 , /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */ -+ 0x1401 , 0x1841 , 0x0 , 0x20901022 , /* PMS-128 ACPI-64 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0xaa5b , /* interrupt steering */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ac97_hdr[] = { /* dev f function 3 - devfn = 7b */ -+ 0xffffff81 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20931022 , 0x2a00041 , 0x4010001 , 0x0 , -+ 0x1481 , 0x0 , 0x0 , 0x0 , /* I/O BAR-128 */ -+ 0x0 , 0x0 , 0x0 , 0x20931022 , -+ 0x0 , 0x0 , 0x0 , 0x205 , /* IntB , IRQ5 */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ohci_hdr[] = { /* dev f function 4 - devfn = 7c */ -+ 0xfffff000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20941022 , 0x2300006 , 0xc031002 , 0x0 , -+ 0xfe01a000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */ -+ 0x0 , 0x0 , 0x0 , 0x20941022 , -+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */ -+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */ -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+}; -+ -+static const u32 ehci_hdr[] = { /* dev f function 4 - devfn = 7d */ -+ 0xfffff000 , 0x0 , 0x0 , 0x0 , -+ 0x0 , 0x0 , 0x0 , 0x0 , -+ -+ 0x20951022 , 0x2300006 , 0xc032002 , 0x0 , -+ 0xfe01b000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */ -+ 0x0 , 0x0 , 0x0 , 0x20951022 , -+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */ -+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */ -+#if 0 -+ 0x1 , 0x40080000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */ -+#endif -+ 0x01000001 , 0x00000000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */ -+ 0x2020 , 0x0 , 0x0 , 0x0 , /* (EHCI page 8) 60 SBRN (R/O), 61 FLADJ (R/W), PORTWAKECAP */ -+}; -+ -+static u32 ff_loc = ~0; -+static u32 zero_loc = 0; -+ -+static int bar_probing = 0; /* Set after a write of ~0 to a BAR */ -+ -+#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */ -+#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */ -+#define SIMULATED(bus, devfn) (((bus) == 0) && ((PCI_SLOT(devfn) == NB_SLOT) || (PCI_SLOT(devfn) == SB_SLOT))) -+ -+static u32 *hdr_addr(const u32 *hdr, int reg) -+{ -+ u32 addr; -+ -+ /* -+ * This is a little bit tricky. The header maps consist of -+ * 0x20 bytes of size masks, followed by 0x70 bytes of header data. -+ * In the normal case, when not probing a BAR's size, we want -+ * to access the header data, so we add 0x20 to the reg offset, -+ * thus skipping the size mask area. -+ * In the BAR probing case, we want to access the size mask for -+ * the BAR, so we subtract 0x10 (the config header offset for -+ * BAR0), and don't skip the size mask area. -+ */ -+ -+ addr = (u32)hdr + reg + (bar_probing ? -0x10 : 0x20); -+ -+ bar_probing = 0; -+ return (u32 *)addr; -+} -+ -+static int pci_olpc_read(unsigned int seg, unsigned int bus, -+ unsigned int devfn, int reg, int len, u32 *value) -+{ -+ u32 *addr; -+ -+ /* Use the hardware mechanism for non-simulated devices */ -+ if (!SIMULATED(bus, devfn)) -+ return pci_conf1_read(seg, bus, devfn, reg, len, value); -+ -+ /* -+ * No device has config registers past 0x70, so we save table space -+ * by not storing entries for the nonexistent registers -+ */ -+ if (reg >= 0x70) -+ addr = &zero_loc; -+ else { -+ switch (devfn) { -+ case 0x8: -+ addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); -+ break; -+ case 0x9: -+ addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); -+ break; -+ case 0xa: -+ addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; -+ break; -+ case 0x78: -+ addr = hdr_addr(isa_hdr, reg); -+ break; -+ case 0x7b: -+ addr = hdr_addr(ac97_hdr, reg); -+ break; -+ case 0x7c: -+ addr = hdr_addr(ohci_hdr, reg); -+ break; -+ case 0x7d: -+ addr = hdr_addr(ehci_hdr, reg); -+ break; -+ default: -+ addr = &ff_loc; -+ break; -+ } -+ } -+ switch (len) { -+ case 1: -+ *value = *(u8 *) addr; -+ break; -+ case 2: -+ *value = *(u16 *) addr; -+ break; -+ case 4: -+ *value = *addr; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return 0; -+} -+ -+static int pci_olpc_write(unsigned int seg, unsigned int bus, -+ unsigned int devfn, int reg, int len, u32 value) -+{ -+ /* Use the hardware mechanism for non-simulated devices */ -+ if (!SIMULATED(bus, devfn)) -+ return pci_conf1_write(seg, bus, devfn, reg, len, value); -+ -+ /* XXX we may want to extend this to simulate EHCI power management */ -+ -+ /* -+ * Mostly we just discard writes, but if the write is a size probe -+ * (i.e. writing ~0 to a BAR), we remember it and arrange to return -+ * the appropriate size mask on the next read. This is cheating -+ * to some extent, because it depends on the fact that the next -+ * access after such a write will always be a read to the same BAR. -+ */ -+ -+ if ((reg >= 0x10) && (reg < 0x2c)) { -+ /* Write is to a BAR */ -+ if (value == ~0) -+ bar_probing = 1; -+ } else { -+ /* -+ * No warning on writes to ROM BAR, CMD, LATENCY_TIMER, -+ * CACHE_LINE_SIZE, or PM registers. -+ */ -+ if ((reg != 0x30) && (reg != 0x04) && (reg != 0x0d) && -+ (reg != 0x0c) && (reg != 0x44)) -+ printk(KERN_WARNING "OLPC PCI: Config write to devfn %x reg %x value %x\n", devfn, reg, value); -+ } -+ -+ return 0; -+} -+ -+static struct pci_raw_ops pci_olpc_conf = { -+ .read = pci_olpc_read, -+ .write = pci_olpc_write, -+}; -+ -+void __init pci_olpc_init(void) -+{ -+ if (!machine_is_olpc() || olpc_has_vsa()) -+ return; -+ -+ printk(KERN_INFO "PCI: Using configuration type OLPC\n"); -+ raw_pci_ops = &pci_olpc_conf; -+ is_lx = is_geode_lx(); -+} -diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h -index 8c66f27..a67e617 100644 ---- a/arch/i386/pci/pci.h -+++ b/arch/i386/pci/pci.h -@@ -93,6 +93,7 @@ extern void pci_direct_init(int type); - extern void pci_pcbios_init(void); - extern void pci_mmcfg_init(int type); - extern void pcibios_sort(void); -+extern void pci_olpc_init(void); - - /* pci-mmconfig.c */ - -diff --git a/drivers/Makefile b/drivers/Makefile -index f0878b2..c033d30 100644 ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -23,6 +23,8 @@ obj-y += char/ - - obj-$(CONFIG_CONNECTOR) += connector/ - -+obj-$(CONFIG_SYSPROF) += sysprof/ -+ - # i810fb and intelfb depend on char/agp/ - obj-$(CONFIG_FB_I810) += video/i810/ - obj-$(CONFIG_FB_INTEL) += video/intelfb/ -diff --git a/drivers/char/vt_ioctl.c b/drivers/char/vt_ioctl.c -index c6f6f42..55ae42c 100644 ---- a/drivers/char/vt_ioctl.c -+++ b/drivers/char/vt_ioctl.c -@@ -37,6 +37,9 @@ - char vt_dont_switch; - extern struct tty_driver *console_driver; - -+/* Add a notifier chain to inform drivers of a VT_TEXT/VT_GRAPHICS switch */ -+RAW_NOTIFIER_HEAD(console_notifier_list); -+ - #define VT_IS_IN_USE(i) (console_driver->ttys[i] && console_driver->ttys[i]->count) - #define VT_BUSY(i) (VT_IS_IN_USE(i) || i == fg_console || vc_cons[i].d == sel_cons) - -@@ -491,6 +494,14 @@ int vt_ioctl(struct tty_struct *tty, struct file * file, - vc->vc_mode = (unsigned char) arg; - if (console != fg_console) - return 0; -+ -+ /* Notify listeners if the current fg_console has switched */ -+ -+ raw_notifier_call_chain(&console_notifier_list, -+ (arg == KD_TEXT) ? -+ CONSOLE_EVENT_SWITCH_TEXT : -+ CONSOLE_EVENT_SWITCH_GRAPHICS, 0); -+ - /* - * explicitly blank/unblank the screen if switching modes - */ -diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c -index e6c4a2b..874d623 100644 ---- a/drivers/i2c/busses/scx200_acb.c -+++ b/drivers/i2c/busses/scx200_acb.c -@@ -46,6 +46,10 @@ static int base[MAX_DEVICES] = { 0x820, 0x840 }; - module_param_array(base, int, NULL, 0); - MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); - -+static unsigned int smbclk = 0x70; -+module_param(smbclk, uint, 0); -+MODULE_PARM_DESC(smbclk, "Specify the SMB_CLK value"); -+ - #define POLL_TIMEOUT (HZ/5) - - enum scx200_acb_state { -@@ -108,6 +112,7 @@ struct scx200_acb_iface { - #define ACBADDR (iface->base + 4) - #define ACBCTL2 (iface->base + 5) - #define ACBCTL2_ENABLE 0x01 -+#define ACBCTL3 (iface->base + 6) - - /************************************************************************/ - -@@ -392,11 +397,13 @@ static __init int scx200_acb_probe(struct scx200_acb_iface *iface) - { - u8 val; - -- /* Disable the ACCESS.bus device and Configure the SCL -- frequency: 16 clock cycles */ -- outb(0x70, ACBCTL2); -+ /* Disable the ACCESS.bus device and Configure the SCL */ -+ -+ outb((smbclk & 0x7F) << 1, ACBCTL2); -+ -+ outb((smbclk >> 7) & 0xFF, ACBCTL3); - -- if (inb(ACBCTL2) != 0x70) { -+ if (inb(ACBCTL2) != ((smbclk & 0x7F) << 1)) { - pr_debug(NAME ": ACBCTL2 readback failed\n"); - return -ENXIO; - } -diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c -index 41fc3d0..a15e7a9 100644 ---- a/drivers/input/keyboard/atkbd.c -+++ b/drivers/input/keyboard/atkbd.c -@@ -63,12 +63,25 @@ static int atkbd_extra; - module_param_named(extra, atkbd_extra, bool, 0); - MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and similar keyboards"); - -+#define ATKBD_KEY_UNKNOWN 0 -+#define ATKBD_KEY_NULL 0xFF0000FF -+ -+#define ATKBD_SCR_1 0xFF0000FE -+#define ATKBD_SCR_2 0xFF0000FD -+#define ATKBD_SCR_4 0xFF0000FC -+#define ATKBD_SCR_8 0xFF0000FB -+#define ATKBD_SCR_CLICK 0xFF0000FA -+#define ATKBD_SCR_LEFT 0xFF0000F9 -+#define ATKBD_SCR_RIGHT 0xFF0000F8 -+ -+#define ATKBD_SPECIAL 0xFF0000F8 -+ - /* - * Scancode to keycode tables. These are just the default setting, and - * are loadable via an userland utility. - */ - --static unsigned char atkbd_set2_keycode[512] = { -+static unsigned int atkbd_set2_keycode[512] = { - - #ifdef CONFIG_KEYBOARD_ATKBD_HP_KEYCODES - -@@ -87,11 +100,17 @@ static unsigned char atkbd_set2_keycode[512] = { - 82, 83, 80, 76, 77, 72, 1, 69, 87, 78, 81, 74, 55, 73, 70, 99, - - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 217,100,255, 0, 97,165, 0, 0,156, 0, 0, 0, 0, 0, 0,125, -+ -+ 217,100,ATKBD_KEY_NULL, 0, 97,165, 0, 0, -+ 156, 0, 0, 0, 0, 0, 0,125, -+ - 173,114, 0,113, 0, 0, 0,126,128, 0, 0,140, 0, 0, 0,127, - 159, 0,115, 0,164, 0, 0,116,158, 0,172,166, 0, 0, 0,142, - 157, 0, 0, 0, 0, 0, 0, 0,155, 0, 98, 0, 0,163, 0, 0, -- 226, 0, 0, 0, 0, 0, 0, 0, 0,255, 96, 0, 0, 0,143, 0, -+ -+ 226, 0, 0, 0, 0, 0, 0, 0, -+ 0,ATKBD_KEY_NULL, 96, 0, 0, 0,143, 0, -+ - 0, 0, 0, 0, 0, 0, 0, 0, 0,107, 0,105,102, 0, 0,112, - 110,111,108,112,106,103, 0,119, 0,118,109, 0, 99,104,119, 0, - -@@ -150,19 +169,6 @@ static unsigned char atkbd_unxlate_table[128] = { - #define ATKBD_RET_HANGEUL 0xf2 - #define ATKBD_RET_ERR 0xff - --#define ATKBD_KEY_UNKNOWN 0 --#define ATKBD_KEY_NULL 255 -- --#define ATKBD_SCR_1 254 --#define ATKBD_SCR_2 253 --#define ATKBD_SCR_4 252 --#define ATKBD_SCR_8 251 --#define ATKBD_SCR_CLICK 250 --#define ATKBD_SCR_LEFT 249 --#define ATKBD_SCR_RIGHT 248 -- --#define ATKBD_SPECIAL 248 -- - #define ATKBD_LED_EVENT_BIT 0 - #define ATKBD_REP_EVENT_BIT 1 - -@@ -174,7 +180,7 @@ static unsigned char atkbd_unxlate_table[128] = { - #define ATKBD_XL_HANJA 0x20 - - static struct { -- unsigned char keycode; -+ unsigned int keycode; - unsigned char set2; - } atkbd_scroll_keys[] = { - { ATKBD_SCR_1, 0xc5 }, -@@ -200,7 +206,7 @@ struct atkbd { - char phys[32]; - - unsigned short id; -- unsigned char keycode[512]; -+ unsigned int keycode[512]; - unsigned char set; - unsigned char translated; - unsigned char extra; -@@ -351,7 +357,7 @@ static irqreturn_t atkbd_interrupt(struct serio *serio, unsigned char data, - unsigned int code = data; - int scroll = 0, hscroll = 0, click = -1, add_release_event = 0; - int value; -- unsigned char keycode; -+ unsigned int keycode; - - #ifdef ATKBD_DEBUG - printk(KERN_DEBUG "atkbd.c: Received %02x flags %02x\n", data, flags); -@@ -856,9 +862,11 @@ static void atkbd_set_keycode_table(struct atkbd *atkbd) - atkbd->keycode[i | 0x80] = atkbd_scroll_keys[j].keycode; - } - } else if (atkbd->set == 3) { -- memcpy(atkbd->keycode, atkbd_set3_keycode, sizeof(atkbd->keycode)); -+ for (i = 0; i < ARRAY_SIZE(atkbd_set3_keycode); i++) -+ atkbd->keycode[i] = atkbd_set3_keycode[i]; - } else { -- memcpy(atkbd->keycode, atkbd_set2_keycode, sizeof(atkbd->keycode)); -+ for (i = 0; i < ARRAY_SIZE(atkbd_set2_keycode); i++) -+ atkbd->keycode[i] = atkbd_set2_keycode[i]; - - if (atkbd->scroll) - for (i = 0; i < ARRAY_SIZE(atkbd_scroll_keys); i++) -@@ -925,8 +933,8 @@ static void atkbd_set_device_attrs(struct atkbd *atkbd) - } - - input_dev->keycode = atkbd->keycode; -- input_dev->keycodesize = sizeof(unsigned char); -- input_dev->keycodemax = ARRAY_SIZE(atkbd_set2_keycode); -+ input_dev->keycodesize = sizeof(unsigned int); -+ input_dev->keycodemax = ARRAY_SIZE(atkbd->keycode); - - for (i = 0; i < 512; i++) - if (atkbd->keycode[i] && atkbd->keycode[i] < ATKBD_SPECIAL) -@@ -1017,6 +1025,10 @@ static int atkbd_connect(struct serio *serio, struct serio_driver *drv) - return err; - } - -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - /* - * atkbd_reconnect() tries to restore keyboard into a sane state and is - * most likely called on resume. -@@ -1027,6 +1039,12 @@ static int atkbd_reconnect(struct serio *serio) - struct atkbd *atkbd = serio_get_drvdata(serio); - struct serio_driver *drv = serio->drv; - -+#ifdef CONFIG_OLPC -+ if (olpc_rev_after(OLPC_REV_B2)) -+ if (serio->dev.power.power_state.event != PM_EVENT_ON) -+ return 0; -+#endif -+ - if (!atkbd || !drv) { - printk(KERN_DEBUG "atkbd: reconnect request, but serio is disconnected, ignoring...\n"); - return -1; -diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig -index 7bbea09..6febbc5 100644 ---- a/drivers/input/mouse/Kconfig -+++ b/drivers/input/mouse/Kconfig -@@ -96,6 +96,16 @@ config MOUSE_PS2_TOUCHKIT - - If unsure, say N. - -+config MOUSE_PS2_OLPC -+ bool "OLPC PS/2 mouse protocol extension" if EMBEDDED -+ default n -+ depends on MOUSE_PS2 && OLPC -+ ---help--- -+ Say Y here if you have an OLPC PS/2 touchpad connected to -+ your system. -+ -+ If unsure, say N. -+ - config MOUSE_SERIAL - tristate "Serial mouse" - select SERIO -diff --git a/drivers/input/mouse/Makefile b/drivers/input/mouse/Makefile -index 9e6e363..f4654ce 100644 ---- a/drivers/input/mouse/Makefile -+++ b/drivers/input/mouse/Makefile -@@ -24,3 +24,4 @@ psmouse-$(CONFIG_MOUSE_PS2_LOGIPS2PP) += logips2pp.o - psmouse-$(CONFIG_MOUSE_PS2_LIFEBOOK) += lifebook.o - psmouse-$(CONFIG_MOUSE_PS2_TRACKPOINT) += trackpoint.o - psmouse-$(CONFIG_MOUSE_PS2_TOUCHKIT) += touchkit_ps2.o -+psmouse-$(CONFIG_MOUSE_PS2_OLPC) += olpc.o -diff --git a/drivers/input/mouse/olpc.c b/drivers/input/mouse/olpc.c -new file mode 100644 -index 0000000..dc575ac ---- /dev/null -+++ b/drivers/input/mouse/olpc.c -@@ -0,0 +1,554 @@ -+/* -+ * OLPC touchpad PS/2 mouse driver -+ * -+ * Copyright (c) 2006 One Laptop Per Child, inc. -+ * Authors Zephaniah E. Hull and Andres Salomon -+ * -+ * This driver is partly based on the ALPS driver, which is: -+ * -+ * Copyright (c) 2003 Neil Brown -+ * Copyright (c) 2003-2005 Peter Osterlund -+ * Copyright (c) 2004 Dmitry Torokhov -+ * Copyright (c) 2005 Vojtech Pavlik -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * The touchpad on the OLPC is fairly wide, with the entire area usable -+ * as a tablet ("PT mode"), and the center 1/3rd also usable as a touchpad -+ * ("GS mode"). -+ * -+ * Earlier version of the device had simultaneous reporting; however, that -+ * was removed. Instead, the device now reports packets in one mode, and -+ * tells the driver when a mode switch needs to happen. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "psmouse.h" -+#include "olpc.h" -+ -+static int tpdebug; -+module_param(tpdebug, int, 0644); -+ -+#define OLPC_GS 1 /* The GS sensor. */ -+#define OLPC_PT 2 /* The PT sensor. */ -+ -+static struct olpc_model_info olpc_model_data[] = { -+ { { 0x67, 0x00, 0x00 }, OLPC_GS | OLPC_PT }, /* unknown ID */ -+ { { 0x67, 0x00, 0x0a }, OLPC_GS | OLPC_PT }, /* pre-B1 */ -+ { { 0x67, 0x00, 0x14 }, OLPC_GS }, /* B1.*/ -+ { { 0x67, 0x00, 0x28 }, OLPC_GS | OLPC_PT }, /* B2 */ -+ { { 0x67, 0x00, 0x3c }, OLPC_GS | OLPC_PT }, /* B2-2 */ -+ { { 0x67, 0x00, 0x50 }, OLPC_GS | OLPC_PT }, /* C1 */ -+}; -+ -+#define OLPC_PKT_PT 0xcf -+#define OLPC_PKT_GS 0xff -+ -+static int olpc_absolute_mode(struct psmouse *psmouse, int mode); -+ -+/* -+ * OLPC absolute Mode - single-mode format -+ * -+ * byte 0: 1 1 0 0 1 1 1 1 -+ * byte 1: 0 x6 x5 x4 x3 x2 x1 x0 -+ * byte 2(PT): 0 0 x9 x8 x7 ? pt-dsw gs-dsw -+ * byte 2(GS): 0 x10 x9 x8 x7 ? gs-dsw pt-dsw -+ * byte 3: 0 y9 y8 y7 1 0 swr swl -+ * byte 4: 0 y6 y5 y4 y3 y2 y1 y0 -+ * byte 5: 0 z6 z5 z4 z3 z2 z1 z0 -+ * -+ * ?'s are not defined in the protocol spec, may vary between models. -+ * -+ * swr/swl are the left/right buttons. -+ * -+ * pt-dsw/gs-dsw indicate that the pt/gs sensor is detecting a -+ * pen/finger -+ */ -+ -+static void olpc_process_packet_gspt(struct psmouse *psmouse) -+{ -+ struct olpc_data *priv = psmouse->private; -+ unsigned char *packet = psmouse->packet; -+ struct input_dev *dev = psmouse->dev; -+ struct input_dev *dev2 = priv->dev2; -+ int x, y, z, gs_down = 0, pt_down = 0, left, right; -+ struct timeval now_tv; -+ s64 now_ns; -+ -+ left = packet[3] & 1; -+ right = packet[3] & 2; -+ x = packet[1] | ((packet[2] & 0x78) << 4); -+ y = packet[4] | ((packet[3] & 0x70) << 3); -+ z = packet[5]; -+ -+ if (psmouse->packet[0] == OLPC_PKT_GS) { -+ pt_down = !!(packet[2] & 1); -+ gs_down = !!(packet[2] & 2); -+ } else if (psmouse->packet[0] == OLPC_PKT_PT) { -+ gs_down = !!(packet[2] & 1); -+ pt_down = !!(packet[2] & 2); -+ } -+ -+ /* -+ * XXX: Kludge. -+ * If it's been more than 30ms since the last packet, -+ * assume that there was a lift we were never told about. -+ */ -+ do_gettimeofday(&now_tv); -+ now_ns = timeval_to_ns (&now_tv); -+ if (now_ns >= priv->late) { -+ input_report_key(dev, BTN_TOUCH, 0); -+ input_report_key(dev, BTN_TOOL_PEN, 0); -+ input_report_key(dev2, BTN_TOUCH, 0); -+ input_report_key(dev2, BTN_TOOL_FINGER, 0); -+ -+ input_sync(dev); -+ input_sync(dev2); -+ } -+ -+ priv->late = now_ns + (30 * NSEC_PER_MSEC); -+ -+ -+ if (tpdebug) { -+ printk(KERN_DEBUG "%s %02x %02x %02x %02x %02x %02x\n", -+ __FUNCTION__, psmouse->packet[0], psmouse->packet[1], -+ psmouse->packet[2], psmouse->packet[3], psmouse->packet[4], -+ psmouse->packet[5]); -+ printk(KERN_DEBUG "l=%d r=%d p=%d g=%d x=%d y=%d z=%d\n", -+ left, right, pt_down, gs_down, x, y, z); -+ } -+ -+ if (psmouse->packet[0] == OLPC_PKT_PT) { -+ input_report_key(dev, BTN_LEFT, left); -+ input_report_key(dev, BTN_RIGHT, right); -+ } else if (psmouse->packet[0] == OLPC_PKT_GS) { -+ input_report_key(dev, BTN_LEFT, left); -+ input_report_key(dev, BTN_RIGHT, right); -+ input_report_key(dev2, BTN_LEFT, left); -+ input_report_key(dev2, BTN_RIGHT, right); -+ } -+ -+ input_report_key(dev, BTN_TOUCH, pt_down); -+ input_report_key(dev, BTN_TOOL_PEN, pt_down); -+ input_report_key(dev2, BTN_TOUCH, gs_down); -+ input_report_key(dev2, BTN_TOOL_FINGER, gs_down); -+ -+ input_report_abs(dev2, ABS_PRESSURE, z); -+ -+ if (psmouse->packet[0] == OLPC_PKT_PT && pt_down) { -+ input_report_abs(dev, ABS_X, x); -+ input_report_abs(dev, ABS_Y, y); -+ } else if (psmouse->packet[0] == OLPC_PKT_GS && gs_down) { -+ input_report_abs(dev2, ABS_X, x); -+ input_report_abs(dev2, ABS_Y, y); -+ } -+ -+ input_sync(dev); -+ input_sync(dev2); -+ -+ if (priv->pending_mode == OLPC_GS && -+ psmouse->packet[0] == OLPC_PKT_PT && pt_down) { -+ priv->pending_mode = 0; -+ cancel_delayed_work(&priv->mode_switch); -+ } -+ -+ if (priv->i->flags & (OLPC_PT|OLPC_GS)) { -+ int pending = 0; -+ if (psmouse->packet[0] == OLPC_PKT_PT && !pt_down) -+ pending = OLPC_GS; -+ else if (psmouse->packet[0] == OLPC_PKT_GS && pt_down) -+ pending = OLPC_PT; -+ -+ if (priv->current_mode == pending) { -+ priv->pending_mode = 0; -+ pending = priv->current_mode; -+ } -+ else if (priv->pending_mode != pending) { -+ priv->pending_mode = pending; -+ if (tpdebug) -+ printk(KERN_WARNING "Scheduling mode switch to %s.\n", -+ pending == OLPC_GS ? "GS" : "PT"); -+ -+ /* -+ * Apply a de-bounce when switching from PT to GS, to allow for -+ * spurious PT-up packets. -+ */ -+ if (priv->pending_mode == OLPC_GS) -+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50)); -+ else -+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, 0); -+ } -+ } -+} -+ -+static psmouse_ret_t olpc_process_byte(struct psmouse *psmouse) -+{ -+ psmouse_ret_t ret = PSMOUSE_BAD_DATA; -+ -+ if (psmouse->packet[0] != OLPC_PKT_PT && -+ psmouse->packet[0] != OLPC_PKT_GS) -+ goto out; -+ -+ /* Bytes 2 - 6 should have 0 in the highest bit */ -+ if (psmouse->pktcnt >= 2 && psmouse->pktcnt <= 6 && -+ (psmouse->packet[psmouse->pktcnt - 1] & 0x80)) -+ goto out; -+ -+ if (psmouse->pktcnt == 6) { -+ olpc_process_packet_gspt(psmouse); -+ ret = PSMOUSE_FULL_PACKET; -+ goto out; -+ } -+ -+ ret = PSMOUSE_GOOD_DATA; -+out: -+ if (ret != PSMOUSE_GOOD_DATA && ret != PSMOUSE_FULL_PACKET) -+ printk(KERN_DEBUG "%s: (%d) %02x %02x %02x %02x %02x %02x\n", -+ __FUNCTION__, psmouse->pktcnt, psmouse->packet[0], -+ psmouse->packet[1], psmouse->packet[2], -+ psmouse->packet[3], psmouse->packet[4], -+ psmouse->packet[5]); -+ return ret; -+} -+ -+static struct olpc_model_info *olpc_get_model(struct psmouse *psmouse) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ unsigned char param[4]; -+ int i; -+ -+ /* -+ * Now try "E7 report". Allowed responses are in -+ * olpc_model_data[].signature -+ */ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21)) -+ return NULL; -+ -+ param[0] = param[1] = param[2] = 0xff; -+ if (ps2_command(ps2dev, param, PSMOUSE_CMD_GETINFO)) -+ return NULL; -+ -+ pr_debug("olpc.c(%d): E7 report: %2.2x %2.2x %2.2x", -+ __LINE__, param[0], param[1], param[2]); -+ -+ for (i = 0; i < ARRAY_SIZE(olpc_model_data); i++) { -+ if (!memcmp(param, olpc_model_data[i].signature, -+ sizeof(olpc_model_data[i].signature))) { -+ printk(KERN_INFO __FILE__ ": OLPC touchpad revision 0x%x.\n", param[2]); -+ return olpc_model_data + i; -+ } -+ } -+ -+ /* -+ * ALPS creates new IDs pretty frequently; rather than listing them -+ * all, just assume they support the defaults. We've set aside the -+ * first entry of olpc_model_data as the catch-all. -+ */ -+ if (!memcmp(param, olpc_model_data[0].signature, 2)) { -+ printk(KERN_INFO __FILE__ ": unknown ALPS revision %x, assuming default flags.\n", param[2]); -+ return &olpc_model_data[0]; -+ } -+ -+ return NULL; -+} -+ -+static int olpc_find_mode(struct psmouse *psmouse) -+{ -+ struct olpc_data *priv = psmouse->private; -+ int mode = priv->i->flags; -+ -+ if (mode & OLPC_GS) -+ mode = OLPC_GS; -+ else if (mode & OLPC_PT) -+ mode = OLPC_PT; -+ else -+ mode = -1; -+ -+ return mode; -+} -+ -+/* -+ * Touchpad should be disabled before calling this! -+ */ -+static int olpc_new_mode(struct psmouse *psmouse, int mode) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ struct olpc_data *priv = psmouse->private; -+ unsigned char param; -+ int ret; -+ -+ if (tpdebug) -+ printk(KERN_WARNING __FILE__ ": Switching to %d. [%lu]\n", mode, jiffies); -+ -+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2))) -+ goto failed; -+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2))) -+ goto failed; -+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2))) -+ goto failed; -+ -+ switch (mode) { -+ default: -+ printk(KERN_WARNING __FILE__ ": Invalid mode %d. Defaulting to OLPC_GS.\n", mode); -+ case OLPC_GS: -+ ret = ps2_command(ps2dev, NULL, 0xE6); -+ break; -+ case OLPC_PT: -+ ret = ps2_command(ps2dev, NULL, 0xE7); -+ break; -+ } -+ if (ret) -+ goto failed; -+ -+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */ -+ psmouse->pktcnt = psmouse->out_of_sync = 0; -+ psmouse->last = jiffies; -+ psmouse->state = PSMOUSE_ACTIVATED; -+ -+ if ((ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_ENABLE))) -+ goto failed; -+ -+ priv->current_mode = mode; -+ priv->pending_mode = 0; -+ if (tpdebug) -+ printk(KERN_WARNING __FILE__ ": Switched to mode %d successful.\n", mode); -+ -+failed: -+ if (ret) -+ printk(KERN_WARNING __FILE__ ": Mode switch to %d failed! (%d) [%lu]\n", mode, ret, jiffies); -+ return ret; -+} -+ -+static int olpc_absolute_mode(struct psmouse *psmouse, int mode) -+{ -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ -+ /* Switch to 'Advanced mode.', four disables in a row. */ -+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) || -+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE)) -+ return -1; -+ -+ return olpc_new_mode(psmouse, mode); -+} -+ -+/* -+ * olpc_poll() - poll the touchpad for current motion packet. -+ * Used in resync. -+ * Note: We can't poll, so always return failure. -+ */ -+static int olpc_poll(struct psmouse *psmouse) -+{ -+ return -1; -+} -+ -+static int olpc_reconnect(struct psmouse *psmouse) -+{ -+ struct olpc_data *priv = psmouse->private; -+ int mode; -+ -+ if (olpc_rev_after(OLPC_REV_B2)) -+ if (psmouse->ps2dev.serio->dev.power.power_state.event != PM_EVENT_ON) -+ return 0; -+ -+ psmouse_reset(psmouse); -+ -+ if (!(priv->i = olpc_get_model(psmouse))) -+ return -1; -+ -+ mode = olpc_find_mode(psmouse); -+ if (mode < 0) -+ return -1; -+ -+ if (olpc_absolute_mode(psmouse, mode)) { -+ printk(KERN_ERR __FILE__ ": Failed to reenable absolute mode.\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static void olpc_disconnect(struct psmouse *psmouse) -+{ -+ struct olpc_data *priv = psmouse->private; -+ -+ psmouse_reset(psmouse); -+ input_unregister_device(priv->dev2); -+ kfree(priv); -+} -+ -+static void olpc_mode_switch(struct work_struct *w) -+{ -+ struct delayed_work *work = container_of(w, struct delayed_work, work); -+ struct olpc_data *priv = container_of(work, struct olpc_data, mode_switch); -+ struct psmouse *psmouse = priv->psmouse; -+ struct ps2dev *ps2dev = &psmouse->ps2dev; -+ int pending_mode, ret; -+ -+ if (priv->pending_mode == priv->current_mode) { -+ priv->pending_mode = 0; -+ printk (KERN_DEBUG __FILE__ ": In switch_mode, no target mode.\n"); -+ return; -+ } -+ -+ if (tpdebug) -+ printk(KERN_WARNING __FILE__ ": Disable for switch to %d. [%lu]\n", priv->pending_mode, jiffies); -+ -+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */ -+ psmouse->state = PSMOUSE_INITIALIZING; -+ -+ ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE); -+ if (ret) { -+ /* XXX: if this ever fails, we need to do a full reset! */ -+ printk(KERN_WARNING __FILE__ ": Disable failed for switch to %d. (%d) [%lu]\n", priv->pending_mode, ret, jiffies); -+ return; -+ } -+ -+ /* -+ * ALPS tells us that it may take up to 20msec for the disable to -+ * take effect; however, ps2_command() will wait up to 200msec for -+ * the ACK to come back (and I'm assuming that by the time the -+ * hardware sends back its ACK, it has stopped sending bytes). -+ */ -+ pending_mode = priv->pending_mode; -+ -+ if (olpc_new_mode(psmouse, priv->pending_mode)) -+ goto bad; -+ -+ /* -+ * Deal with a potential race condition. -+ * -+ * If there is a brief tap of a stylus or a fingernail that -+ * triggers a mode switch to PT mode, and the stylus/fingernail is -+ * lifted after the DISABLE above, but before we reenable in the new mode, -+ * then we can get stuck in PT mode. -+ */ -+ if (pending_mode == OLPC_PT) { -+ priv->pending_mode = OLPC_GS; -+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50)); -+ } -+ -+ return; -+ -+bad: -+ printk(KERN_WARNING __FILE__ ": Failure to switch modes, resetting device...\n"); -+ olpc_reconnect(psmouse); -+} -+ -+int olpc_init(struct psmouse *psmouse) -+{ -+ struct olpc_data *priv; -+ struct input_dev *dev = psmouse->dev; -+ struct input_dev *dev2; -+ int mode; -+ -+ priv = kzalloc(sizeof(struct olpc_data), GFP_KERNEL); -+ dev2 = input_allocate_device(); -+ if (!priv || !dev2) -+ goto init_fail; -+ -+ psmouse->private = priv; -+ priv->dev2 = dev2; -+ priv->psmouse = psmouse; -+ -+ psmouse_reset(psmouse); -+ if (!(priv->i = olpc_get_model(psmouse))) -+ goto init_fail; -+ -+ mode = olpc_find_mode(psmouse); -+ if (mode < 0) { -+ printk(KERN_ERR __FILE__ ": Failed to identify proper mode\n"); -+ goto init_fail; -+ } -+ -+ if (olpc_absolute_mode(psmouse, mode)) { -+ printk(KERN_ERR __FILE__ ": Failed to enable absolute mode\n"); -+ goto init_fail; -+ } -+ -+ /* -+ * Unset some of the default bits for things we don't have. -+ */ -+ dev->evbit[LONG(EV_REL)] &= ~BIT(EV_REL); -+ dev->relbit[LONG(REL_X)] &= ~(BIT(REL_X) | BIT(REL_Y)); -+ dev->keybit[LONG(BTN_MIDDLE)] &= ~BIT(BTN_MIDDLE); -+ -+ dev->evbit[LONG(EV_KEY)] |= BIT(EV_KEY); -+ dev->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH); -+ dev->keybit[LONG(BTN_TOOL_PEN)] |= BIT(BTN_TOOL_PEN); -+ dev->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT); -+ -+ dev->evbit[LONG(EV_ABS)] |= BIT(EV_ABS); -+ input_set_abs_params(dev, ABS_X, 2, 1000, 0, 0); -+ input_set_abs_params(dev, ABS_Y, 0, 717, 0, 0); -+ -+ snprintf(priv->phys, sizeof(priv->phys), -+ "%s/input1", psmouse->ps2dev.serio->phys); -+ dev2->phys = priv->phys; -+ dev2->name = "OLPC ALPS GlideSensor"; -+ dev2->id.bustype = BUS_I8042; -+ dev2->id.vendor = 0x0002; -+ dev2->id.product = PSMOUSE_OLPC; -+ dev2->id.version = 0x0000; -+ -+ dev2->evbit[LONG(EV_KEY)] |= BIT(EV_KEY); -+ dev2->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH); -+ dev2->keybit[LONG(BTN_TOOL_FINGER)] |= BIT(BTN_TOOL_FINGER); -+ dev2->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT); -+ -+ dev2->evbit[LONG(EV_ABS)] |= BIT(EV_ABS); -+ input_set_abs_params(dev2, ABS_X, 350, 512, 0, 0); -+ input_set_abs_params(dev2, ABS_Y, 70, 325, 0, 0); -+ input_set_abs_params(dev2, ABS_PRESSURE, 0, 63, 0, 0); -+ -+ if (input_register_device(dev2)) { -+ printk(KERN_ERR __FILE__ ": Failed to register GlideSensor\n"); -+ goto init_fail; -+ } -+ -+ psmouse->protocol_handler = olpc_process_byte; -+ psmouse->poll = olpc_poll; -+ psmouse->disconnect = olpc_disconnect; -+ psmouse->reconnect = olpc_reconnect; -+ psmouse->pktsize = 6; -+ -+ /* Disable the idle resync. */ -+ psmouse->resync_time = 0; -+ /* Reset after a lot of bad bytes. */ -+ psmouse->resetafter = 1024; -+ -+ INIT_DELAYED_WORK(&priv->mode_switch, olpc_mode_switch); -+ -+ return 0; -+ -+init_fail: -+ input_free_device(dev2); -+ kfree(priv); -+ return -1; -+} -+ -+int olpc_detect(struct psmouse *psmouse, int set_properties) -+{ -+ if (!olpc_get_model(psmouse)) -+ return -1; -+ -+ if (set_properties) { -+ psmouse->vendor = "ALPS"; -+ psmouse->name = "PenTablet"; -+ psmouse->model = 0; -+ } -+ return 0; -+} -+ -diff --git a/drivers/input/mouse/olpc.h b/drivers/input/mouse/olpc.h -new file mode 100644 -index 0000000..426f8b4 ---- /dev/null -+++ b/drivers/input/mouse/olpc.h -@@ -0,0 +1,49 @@ -+/* -+ * OLPC touchpad PS/2 mouse driver -+ * -+ * Copyright (c) 2006 One Laptop Per Child, inc. -+ * -+ * This driver is partly based on the ALPS driver. -+ * Copyright (c) 2003 Peter Osterlund -+ * Copyright (c) 2005 Vojtech Pavlik -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ */ -+ -+#ifndef _OLPC_H -+#define _OLPC_H -+ -+struct olpc_model_info { -+ unsigned char signature[3]; -+ unsigned char flags; -+}; -+ -+struct olpc_data { -+ struct input_dev *dev2; /* Relative device */ -+ struct psmouse *psmouse; -+ char name[32]; /* Name */ -+ char phys[32]; /* Phys */ -+ struct olpc_model_info *i; /* Info */ -+ int pending_mode; -+ int current_mode; -+ s64 late; -+ struct delayed_work mode_switch; -+}; -+ -+#ifdef CONFIG_MOUSE_PS2_OLPC -+int olpc_detect(struct psmouse *psmouse, int set_properties); -+int olpc_init(struct psmouse *psmouse); -+#else -+inline int olpc_detect(struct psmouse *psmouse, int set_properties) -+{ -+ return -ENOSYS; -+} -+inline int olpc_init(struct psmouse *psmouse) -+{ -+ return -ENOSYS; -+} -+#endif -+ -+#endif -diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c -index b9f0fb2..edcdb68 100644 ---- a/drivers/input/mouse/psmouse-base.c -+++ b/drivers/input/mouse/psmouse-base.c -@@ -26,6 +26,7 @@ - #include "synaptics.h" - #include "logips2pp.h" - #include "alps.h" -+#include "olpc.h" - #include "lifebook.h" - #include "trackpoint.h" - #include "touchkit_ps2.h" -@@ -103,7 +104,7 @@ static struct attribute_group psmouse_attribute_group = { - */ - static DEFINE_MUTEX(psmouse_mutex); - --static struct workqueue_struct *kpsmoused_wq; -+struct workqueue_struct *kpsmoused_wq; - - struct psmouse_protocol { - enum psmouse_type type; -@@ -320,7 +321,7 @@ static irqreturn_t psmouse_interrupt(struct serio *serio, - goto out; - } - -- if (psmouse->packet[1] == PSMOUSE_RET_ID) { -+ if (psmouse->packet[1] == PSMOUSE_RET_ID || psmouse->packet[1] == PSMOUSE_RET_BAT) { - __psmouse_set_state(psmouse, PSMOUSE_IGNORE); - serio_reconnect(serio); - goto out; -@@ -631,8 +632,21 @@ static int psmouse_extensions(struct psmouse *psmouse, - } - } - -+/* -+ * Try OLPC touchpad. -+ */ - if (max_proto > PSMOUSE_IMEX) { -+ if (olpc_detect(psmouse, set_properties) == 0) { -+ if (!set_properties || olpc_init(psmouse) == 0) -+ return PSMOUSE_OLPC; -+/* -+ * Init failed, try basic relative protocols -+ */ -+ max_proto = PSMOUSE_IMEX; -+ } -+ } - -+ if (max_proto > PSMOUSE_IMEX) { - if (genius_detect(psmouse, set_properties) == 0) - return PSMOUSE_GENPS; - -@@ -762,6 +776,14 @@ static const struct psmouse_protocol psmouse_protocols[] = { - .detect = touchkit_ps2_detect, - }, - #endif -+#ifdef CONFIG_MOUSE_PS2_OLPC -+ { -+ .type = PSMOUSE_OLPC, -+ .name = "OLPC", -+ .alias = "olpc", -+ .detect = olpc_detect, -+ }, -+#endif - { - .type = PSMOUSE_CORTRON, - .name = "CortronPS/2", -diff --git a/drivers/input/mouse/psmouse.h b/drivers/input/mouse/psmouse.h -index 1317bdd..c4857df 100644 ---- a/drivers/input/mouse/psmouse.h -+++ b/drivers/input/mouse/psmouse.h -@@ -89,6 +89,7 @@ enum psmouse_type { - PSMOUSE_TRACKPOINT, - PSMOUSE_TOUCHKIT_PS2, - PSMOUSE_CORTRON, -+ PSMOUSE_OLPC, - PSMOUSE_AUTO /* This one should always be last */ - }; - -@@ -96,6 +97,7 @@ int psmouse_sliced_command(struct psmouse *psmouse, unsigned char command); - int psmouse_reset(struct psmouse *psmouse); - void psmouse_set_resolution(struct psmouse *psmouse, unsigned int resolution); - -+extern struct workqueue_struct *kpsmoused_wq; - - struct psmouse_attribute { - struct device_attribute dattr; -diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c -index c2eea27..3510726 100644 ---- a/drivers/input/serio/i8042.c -+++ b/drivers/input/serio/i8042.c -@@ -868,6 +868,11 @@ static long i8042_panic_blink(long count) - #undef DELAY - - #ifdef CONFIG_PM -+ -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - /* - * Here we try to restore the original BIOS settings. We only want to - * do that once, when we really suspend, not when we taking memory -@@ -878,8 +883,15 @@ static long i8042_panic_blink(long count) - static int i8042_suspend(struct platform_device *dev, pm_message_t state) - { - if (dev->dev.power.power_state.event != state.event) { -+#ifdef CONFIG_OLPC -+ /* Anything newer than B2 remains powered; no reset needed */ -+ if (olpc_rev_before(OLPC_REV_PRE_B3)) { -+#endif - if (state.event == PM_EVENT_SUSPEND) - i8042_controller_reset(); -+#ifdef CONFIG_OLPC -+ } -+#endif - - dev->dev.power.power_state = state; - } -@@ -902,9 +914,15 @@ static int i8042_resume(struct platform_device *dev) - if (dev->dev.power.power_state.event == PM_EVENT_ON) - return 0; - -+#ifdef CONFIG_OLPC -+ if (olpc_rev_before(OLPC_REV_PRE_B3)) { -+#endif - error = i8042_controller_check(); - if (error) - return error; -+#ifdef CONFIG_OLPC -+ } -+#endif - - error = i8042_controller_selftest(); - if (error) -diff --git a/drivers/input/serio/serio.c b/drivers/input/serio/serio.c -index 372ca49..c9e5308 100644 ---- a/drivers/input/serio/serio.c -+++ b/drivers/input/serio/serio.c -@@ -916,11 +916,22 @@ static int serio_uevent(struct device *dev, char **envp, int num_envp, char *buf - #endif /* CONFIG_HOTPLUG */ - - #ifdef CONFIG_PM -+ -+#ifdef CONFIG_OLPC -+#include -+#endif -+ - static int serio_suspend(struct device *dev, pm_message_t state) - { - if (dev->power.power_state.event != state.event) { -+#ifdef CONFIG_OLPC -+ if (olpc_rev_before(OLPC_REV_PRE_B3)) { -+#endif - if (state.event == PM_EVENT_SUSPEND) - serio_cleanup(to_serio_port(dev)); -+#ifdef CONFIG_OLPC -+ } -+#endif - - dev->power.power_state = state; - } -diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c -index ef53618..47881d2 100644 ---- a/drivers/media/video/cafe_ccic.c -+++ b/drivers/media/video/cafe_ccic.c -@@ -63,13 +63,13 @@ MODULE_SUPPORTED_DEVICE("Video"); - */ - - #define MAX_DMA_BUFS 3 --static int alloc_bufs_at_load = 0; --module_param(alloc_bufs_at_load, bool, 0444); --MODULE_PARM_DESC(alloc_bufs_at_load, -- "Non-zero value causes DMA buffers to be allocated at module " -- "load time. This increases the chances of successfully getting " -- "those buffers, but at the cost of nailing down the memory from " -- "the outset."); -+static int alloc_bufs_at_read = 0; -+module_param(alloc_bufs_at_read, bool, 0444); -+MODULE_PARM_DESC(alloc_bufs_at_read, -+ "Non-zero value causes DMA buffers to be allocated when the " -+ "video capture device is read, rather than at module load " -+ "time. This saves memory, but decreases the chances of " -+ "successfully getting those buffers."); - - static int n_dma_bufs = 3; - module_param(n_dma_bufs, uint, 0644); -@@ -370,6 +370,10 @@ static int cafe_smbus_write_data(struct cafe_camera *cam, - rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR); - cafe_reg_write(cam, REG_TWSIC1, rval); - spin_unlock_irqrestore(&cam->dev_lock, flags); -+ mdelay(2); /* It'll probably take about 900µs anyway, and the -+ CAFÉ is apparently quite sensitive to being poked -+ at this point. If we can work out precisely what's -+ going on and reduce this delay, it would be nice. */ - - /* - * Time to wait for the write to complete. THIS IS A RACY -@@ -1503,7 +1507,7 @@ static int cafe_v4l_release(struct inode *inode, struct file *filp) - } - if (cam->users == 0) { - cafe_ctlr_power_down(cam); -- if (! alloc_bufs_at_load) -+ if (alloc_bufs_at_read) - cafe_free_dma_bufs(cam); - } - mutex_unlock(&cam->s_mutex); -@@ -2162,7 +2166,7 @@ static int cafe_pci_probe(struct pci_dev *pdev, - /* - * If so requested, try to get our DMA buffers now. - */ -- if (alloc_bufs_at_load) { -+ if (!alloc_bufs_at_read) { - if (cafe_alloc_dma_bufs(cam, 1)) - cam_warn(cam, "Unable to alloc DMA buffers at load" - " will try again later."); -diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index 73e248f..f7afde3 100644 ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -202,5 +202,10 @@ config THINKPAD_ACPI_BAY - - If you are not sure, say Y here. - -+config EEPROM_93CX6 -+ tristate "EEPROM 93CX6 support" -+ ---help--- -+ This is a driver for the EEPROM chipsets 93c46 and 93c66. -+ The driver supports both read as well as write commands. - - endif # MISC_DEVICES -diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c -index 93fe2e5..e17eb8e 100644 ---- a/drivers/mmc/card/block.c -+++ b/drivers/mmc/card/block.c -@@ -229,6 +229,11 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) - if (brq.data.blocks > card->host->max_blk_count) - brq.data.blocks = card->host->max_blk_count; - -+ if (mmc_card_sd(card) && !card->host->ios.clock) { -+ printk(KERN_ERR "%s: I/O to stopped card\n", -+ req->rq_disk->disk_name); -+ goto cmd_err; -+ } - mmc_set_data_timeout(&brq.data, card, rq_data_dir(req) != READ); - - /* -diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c -index 20a7d89..9abbb58 100644 ---- a/drivers/mmc/host/sdhci.c -+++ b/drivers/mmc/host/sdhci.c -@@ -411,6 +411,12 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) - break; - } - -+ /* -+ * There's an off-by-one error in the hw that we need to -+ * compensate for. -+ */ -+ count++; -+ - if (count >= 0xF) { - printk(KERN_WARNING "%s: Too large timeout requested!\n", - mmc_hostname(host->mmc)); -@@ -676,19 +682,17 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) - if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) - writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); - -- pwr = SDHCI_POWER_ON; -- - switch (1 << power) { - case MMC_VDD_165_195: -- pwr |= SDHCI_POWER_180; -+ pwr = SDHCI_POWER_180; - break; - case MMC_VDD_29_30: - case MMC_VDD_30_31: -- pwr |= SDHCI_POWER_300; -+ pwr = SDHCI_POWER_300; - break; - case MMC_VDD_32_33: - case MMC_VDD_33_34: -- pwr |= SDHCI_POWER_330; -+ pwr = SDHCI_POWER_330; - break; - default: - BUG(); -@@ -696,6 +700,10 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) - - writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); - -+ pwr |= SDHCI_POWER_ON; -+ -+ writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); -+ - out: - host->power = power; - } -diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig -index fbec8cd..8848e8a 100644 ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -278,6 +278,14 @@ config SSFDC - This enables read only access to SmartMedia formatted NAND - flash. You can mount it with FAT file system. - -+config MTD_OOPS -+ tristate "Log panic/oops to an MTD buffer" -+ depends on MTD -+ help -+ This enables panic and oops messages to be logged to a circular -+ buffer in a flash partition where it can be read back at some -+ later point. -+ - source "drivers/mtd/chips/Kconfig" - - source "drivers/mtd/maps/Kconfig" -diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile -index 6d958a4..7f0b04b 100644 ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -22,6 +22,7 @@ obj-$(CONFIG_NFTL) += nftl.o - obj-$(CONFIG_INFTL) += inftl.o - obj-$(CONFIG_RFD_FTL) += rfd_ftl.o - obj-$(CONFIG_SSFDC) += ssfdc.o -+obj-$(CONFIG_MTD_OOPS) += mtdoops.o - - nftl-objs := nftlcore.o nftlmount.o - inftl-objs := inftlcore.o inftlmount.o -diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c -index 2f19fa7..39eff9f 100644 ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -526,7 +526,7 @@ static int cfi_intelext_partition_fixup(struct mtd_info *mtd, - struct cfi_pri_intelext *extp = cfi->cmdset_priv; - - /* -- * Probing of multi-partition flash ships. -+ * Probing of multi-partition flash chips. - * - * To support multiple partitions when available, we simply arrange - * for each of them to have their own flchip structure even if they -@@ -1780,7 +1780,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, - return ret; - } - --int cfi_intelext_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) -+static int cfi_intelext_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) - { - unsigned long ofs, len; - int ret; -@@ -1930,7 +1930,7 @@ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, size_t len) - printk(KERN_DEBUG "%s: lock status before, ofs=0x%08llx, len=0x%08X\n", - __FUNCTION__, ofs, len); - cfi_varsize_frob(mtd, do_printlockstatus_oneblock, -- ofs, len, 0); -+ ofs, len, NULL); - #endif - - ret = cfi_varsize_frob(mtd, do_xxlock_oneblock, -@@ -1940,7 +1940,7 @@ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, size_t len) - printk(KERN_DEBUG "%s: lock status after, ret=%d\n", - __FUNCTION__, ret); - cfi_varsize_frob(mtd, do_printlockstatus_oneblock, -- ofs, len, 0); -+ ofs, len, NULL); - #endif - - return ret; -@@ -1954,7 +1954,7 @@ static int cfi_intelext_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) - printk(KERN_DEBUG "%s: lock status before, ofs=0x%08llx, len=0x%08X\n", - __FUNCTION__, ofs, len); - cfi_varsize_frob(mtd, do_printlockstatus_oneblock, -- ofs, len, 0); -+ ofs, len, NULL); - #endif - - ret = cfi_varsize_frob(mtd, do_xxlock_oneblock, -@@ -1964,7 +1964,7 @@ static int cfi_intelext_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) - printk(KERN_DEBUG "%s: lock status after, ret=%d\n", - __FUNCTION__, ret); - cfi_varsize_frob(mtd, do_printlockstatus_oneblock, -- ofs, len, 0); -+ ofs, len, NULL); - #endif - - return ret; -@@ -2255,7 +2255,7 @@ static void cfi_intelext_save_locks(struct mtd_info *mtd) - adr = region->offset + block * len; - - status = cfi_varsize_frob(mtd, -- do_getlockstatus_oneblock, adr, len, 0); -+ do_getlockstatus_oneblock, adr, len, NULL); - if (status) - set_bit(block, region->lockmap); - else -diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c -index 1f64458..389acc6 100644 ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1609,7 +1609,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, - } - - --int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) -+static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) - { - unsigned long ofs, len; - int ret; -diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c -index 58e561e..593e9d6 100644 ---- a/drivers/mtd/chips/jedec_probe.c -+++ b/drivers/mtd/chips/jedec_probe.c -@@ -70,6 +70,7 @@ - - /* Fujitsu */ - #define MBM29F040C 0x00A4 -+#define MBM29F800BA 0x2258 - #define MBM29LV650UE 0x22D7 - #define MBM29LV320TE 0x22F6 - #define MBM29LV320BE 0x22F9 -@@ -129,6 +130,7 @@ - #define LH28F640BF 0x00b0 - - /* ST - www.st.com */ -+#define M29F800AB 0x0058 - #define M29W800DT 0x00D7 - #define M29W800DB 0x005B - #define M29W160DT 0x22C4 -@@ -646,6 +648,23 @@ static const struct amd_flash_info jedec_table[] = { - } - }, { - .mfr_id = MANUFACTURER_FUJITSU, -+ .dev_id = MBM29F800BA, -+ .name = "Fujitsu MBM29F800BA", -+ .uaddr = { -+ [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ -+ [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ -+ }, -+ .DevSize = SIZE_1MiB, -+ .CmdSet = P_ID_AMD_STD, -+ .NumEraseRegions= 4, -+ .regions = { -+ ERASEINFO(0x04000,1), -+ ERASEINFO(0x02000,2), -+ ERASEINFO(0x08000,1), -+ ERASEINFO(0x10000,15), -+ } -+ }, { -+ .mfr_id = MANUFACTURER_FUJITSU, - .dev_id = MBM29LV650UE, - .name = "Fujitsu MBM29LV650UE", - .uaddr = { -@@ -1510,6 +1529,23 @@ static const struct amd_flash_info jedec_table[] = { - ERASEINFO(0x1000,256) - } - -+ }, { -+ .mfr_id = MANUFACTURER_ST, -+ .dev_id = M29F800AB, -+ .name = "ST M29F800AB", -+ .uaddr = { -+ [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ -+ [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ -+ }, -+ .DevSize = SIZE_1MiB, -+ .CmdSet = P_ID_AMD_STD, -+ .NumEraseRegions= 4, -+ .regions = { -+ ERASEINFO(0x04000,1), -+ ERASEINFO(0x02000,2), -+ ERASEINFO(0x08000,1), -+ ERASEINFO(0x10000,15), -+ } - }, { - .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ - .dev_id = M29W800DT, -diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig -index ff642f8..b4ea64d 100644 ---- a/drivers/mtd/devices/Kconfig -+++ b/drivers/mtd/devices/Kconfig -@@ -69,12 +69,21 @@ config MTD_DATAFLASH26 - If you have such a board and such a DataFlash, say 'Y'. - - config MTD_M25P80 -- tristate "Support for M25 SPI Flash" -+ tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" - depends on SPI_MASTER && EXPERIMENTAL - help -- This enables access to ST M25P80 and similar SPI flash chips, -- used for program and data storage. Set up your spi devices -- with the right board-specific platform data. -+ This enables access to most modern SPI flash chips, used for -+ program and data storage. Series supported include Atmel AT26DF, -+ Spansion S25SL, SST 25VF, ST M25P, and Winbond W25X. Other chips -+ are supported as well. See the driver source for the current list, -+ or to add other chips. -+ -+ Note that the original DataFlash chips (AT45 series, not AT26DF), -+ need an entirely different driver. -+ -+ Set up your spi devices with the right board-specific platform data, -+ if you want to specify device partitioning or to use a device which -+ doesn't support the JEDEC ID instruction. - - config MTD_SLRAM - tristate "Uncached system RAM" -diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c -index 78c2511..98df5bc 100644 ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -1,5 +1,5 @@ - /* -- * MTD SPI driver for ST M25Pxx flash chips -+ * MTD SPI driver for ST M25Pxx (and similar) serial flash chips - * - * Author: Mike Lavender, mike@steroidmicros.com - * -@@ -19,33 +19,32 @@ - #include - #include - #include --#include -+#include -+ - #include - #include -+ - #include - #include - --#include -- -- --/* NOTE: AT 25F and SST 25LF series are very similar, -- * but commands for sector erase and chip id differ... -- */ - - #define FLASH_PAGESIZE 256 - - /* Flash opcodes. */ --#define OPCODE_WREN 6 /* Write enable */ --#define OPCODE_RDSR 5 /* Read status register */ --#define OPCODE_READ 3 /* Read data bytes */ --#define OPCODE_PP 2 /* Page program */ --#define OPCODE_SE 0xd8 /* Sector erase */ --#define OPCODE_RES 0xab /* Read Electronic Signature */ -+#define OPCODE_WREN 0x06 /* Write enable */ -+#define OPCODE_RDSR 0x05 /* Read status register */ -+#define OPCODE_READ 0x03 /* Read data bytes (low frequency) */ -+#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -+#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -+#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -+#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -+#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ - #define OPCODE_RDID 0x9f /* Read JEDEC ID */ - - /* Status Register bits. */ - #define SR_WIP 1 /* Write in progress */ - #define SR_WEL 2 /* Write enable latch */ -+/* meaning of other SR_* bits may differ between vendors */ - #define SR_BP0 4 /* Block protect 0 */ - #define SR_BP1 8 /* Block protect 1 */ - #define SR_BP2 0x10 /* Block protect 2 */ -@@ -65,9 +64,10 @@ - - struct m25p { - struct spi_device *spi; -- struct semaphore lock; -+ struct mutex lock; - struct mtd_info mtd; -- unsigned partitioned; -+ unsigned partitioned:1; -+ u8 erase_opcode; - u8 command[4]; - }; - -@@ -150,8 +150,9 @@ static int wait_till_ready(struct m25p *flash) - */ - static int erase_sector(struct m25p *flash, u32 offset) - { -- DEBUG(MTD_DEBUG_LEVEL3, "%s: %s at 0x%08x\n", flash->spi->dev.bus_id, -- __FUNCTION__, offset); -+ DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", -+ flash->spi->dev.bus_id, __FUNCTION__, -+ flash->mtd.erasesize / 1024, offset); - - /* Wait until finished previous write command. */ - if (wait_till_ready(flash)) -@@ -161,7 +162,7 @@ static int erase_sector(struct m25p *flash, u32 offset) - write_enable(flash); - - /* Set up command buffer. */ -- flash->command[0] = OPCODE_SE; -+ flash->command[0] = flash->erase_opcode; - flash->command[1] = offset >> 16; - flash->command[2] = offset >> 8; - flash->command[3] = offset; -@@ -201,13 +202,17 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) - addr = instr->addr; - len = instr->len; - -- down(&flash->lock); -+ mutex_lock(&flash->lock); -+ -+ /* REVISIT in some cases we could speed up erasing large regions -+ * by using OPCODE_SE instead of OPCODE_BE_4K -+ */ - - /* now erase those sectors */ - while (len) { - if (erase_sector(flash, addr)) { - instr->state = MTD_ERASE_FAILED; -- up(&flash->lock); -+ mutex_unlock(&flash->lock); - return -EIO; - } - -@@ -215,7 +220,7 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) - len -= mtd->erasesize; - } - -- up(&flash->lock); -+ mutex_unlock(&flash->lock); - - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); -@@ -260,16 +265,19 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, - if (retlen) - *retlen = 0; - -- down(&flash->lock); -+ mutex_lock(&flash->lock); - - /* Wait till previous write/erase is done. */ - if (wait_till_ready(flash)) { - /* REVISIT status return?? */ -- up(&flash->lock); -+ mutex_unlock(&flash->lock); - return 1; - } - -- /* NOTE: OPCODE_FAST_READ (if available) is faster... */ -+ /* FIXME switch to OPCODE_FAST_READ. It's required for higher -+ * clocks; and at this writing, every chip this driver handles -+ * supports that opcode. -+ */ - - /* Set up the write data buffer. */ - flash->command[0] = OPCODE_READ; -@@ -281,7 +289,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, - - *retlen = m.actual_length - sizeof(flash->command); - -- up(&flash->lock); -+ mutex_unlock(&flash->lock); - - return 0; - } -@@ -323,7 +331,7 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, - t[1].tx_buf = buf; - spi_message_add_tail(&t[1], &m); - -- down(&flash->lock); -+ mutex_lock(&flash->lock); - - /* Wait until finished previous write command. */ - if (wait_till_ready(flash)) -@@ -381,10 +389,10 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, - if (retlen) - *retlen += m.actual_length - - sizeof(flash->command); -- } -- } -+ } -+ } - -- up(&flash->lock); -+ mutex_unlock(&flash->lock); - - return 0; - } -@@ -398,24 +406,118 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, - - struct flash_info { - char *name; -- u8 id; -- u16 jedec_id; -+ -+ /* JEDEC id zero means "no ID" (most older chips); otherwise it has -+ * a high byte of zero plus three data bytes: the manufacturer id, -+ * then a two byte device id. -+ */ -+ u32 jedec_id; -+ -+ /* The size listed here is what works with OPCODE_SE, which isn't -+ * necessarily called a "sector" by the vendor. -+ */ - unsigned sector_size; -- unsigned n_sectors; -+ u16 n_sectors; -+ -+ u16 flags; -+#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ - }; - -+ -+/* NOTE: double check command sets and memory organization when you add -+ * more flash chips. This current list focusses on newer chips, which -+ * have been converging on command sets which including JEDEC ID. -+ */ - static struct flash_info __devinitdata m25p_data [] = { -- /* REVISIT: fill in JEDEC ids, for parts that have them */ -- { "m25p05", 0x05, 0x2010, 32 * 1024, 2 }, -- { "m25p10", 0x10, 0x2011, 32 * 1024, 4 }, -- { "m25p20", 0x11, 0x2012, 64 * 1024, 4 }, -- { "m25p40", 0x12, 0x2013, 64 * 1024, 8 }, -- { "m25p80", 0x13, 0x0000, 64 * 1024, 16 }, -- { "m25p16", 0x14, 0x2015, 64 * 1024, 32 }, -- { "m25p32", 0x15, 0x2016, 64 * 1024, 64 }, -- { "m25p64", 0x16, 0x2017, 64 * 1024, 128 }, -+ -+ /* Atmel -- some are (confusingly) marketed as "DataFlash" */ -+ { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K, }, -+ { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K, }, -+ -+ { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K, }, -+ -+ { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K, }, -+ { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K, }, -+ { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, }, -+ { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, }, -+ -+ /* Spansion -- single (large) sector size only, at least -+ * for the chips listed here (without boot sectors). -+ */ -+ { "s25sl004a", 0x010212, 64 * 1024, 8, }, -+ { "s25sl008a", 0x010213, 64 * 1024, 16, }, -+ { "s25sl016a", 0x010214, 64 * 1024, 32, }, -+ { "s25sl032a", 0x010215, 64 * 1024, 64, }, -+ { "s25sl064a", 0x010216, 64 * 1024, 128, }, -+ -+ /* SST -- large erase sizes are "overlays", "sectors" are 4K */ -+ { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K, }, -+ { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K, }, -+ { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K, }, -+ { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K, }, -+ -+ /* ST Microelectronics -- newer production may have feature updates */ -+ { "m25p05", 0x202010, 32 * 1024, 2, }, -+ { "m25p10", 0x202011, 32 * 1024, 4, }, -+ { "m25p20", 0x202012, 64 * 1024, 4, }, -+ { "m25p40", 0x202013, 64 * 1024, 8, }, -+ { "m25p80", 0, 64 * 1024, 16, }, -+ { "m25p16", 0x202015, 64 * 1024, 32, }, -+ { "m25p32", 0x202016, 64 * 1024, 64, }, -+ { "m25p64", 0x202017, 64 * 1024, 128, }, -+ { "m25p128", 0x202018, 256 * 1024, 64, }, -+ -+ { "m45pe80", 0x204014, 64 * 1024, 16, }, -+ { "m45pe16", 0x204015, 64 * 1024, 32, }, -+ -+ { "m25pe80", 0x208014, 64 * 1024, 16, }, -+ { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K, }, -+ -+ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ -+ { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K, }, -+ { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K, }, -+ { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K, }, -+ { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K, }, -+ { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K, }, -+ { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K, }, -+ { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K, }, - }; - -+static struct flash_info *__devinit jedec_probe(struct spi_device *spi) -+{ -+ int tmp; -+ u8 code = OPCODE_RDID; -+ u8 id[3]; -+ u32 jedec; -+ struct flash_info *info; -+ -+ /* JEDEC also defines an optional "extended device information" -+ * string for after vendor-specific data, after the three bytes -+ * we use here. Supporting some chips might require using it. -+ */ -+ tmp = spi_write_then_read(spi, &code, 1, id, 3); -+ if (tmp < 0) { -+ DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", -+ spi->dev.bus_id, tmp); -+ return NULL; -+ } -+ jedec = id[0]; -+ jedec = jedec << 8; -+ jedec |= id[1]; -+ jedec = jedec << 8; -+ jedec |= id[2]; -+ -+ for (tmp = 0, info = m25p_data; -+ tmp < ARRAY_SIZE(m25p_data); -+ tmp++, info++) { -+ if (info->jedec_id == jedec) -+ return info; -+ } -+ dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); -+ return NULL; -+} -+ -+ - /* - * board specific setup should have ensured the SPI clock used here - * matches what the READ command supports, at least until this driver -@@ -429,37 +531,51 @@ static int __devinit m25p_probe(struct spi_device *spi) - unsigned i; - - /* Platform data helps sort out which chip type we have, as -- * well as how this board partitions it. -+ * well as how this board partitions it. If we don't have -+ * a chip ID, try the JEDEC id commands; they'll work for most -+ * newer chips, even if we don't recognize the particular chip. - */ - data = spi->dev.platform_data; -- if (!data || !data->type) { -- /* FIXME some chips can identify themselves with RES -- * or JEDEC get-id commands. Try them ... -- */ -- DEBUG(MTD_DEBUG_LEVEL1, "%s: no chip id\n", -- spi->dev.bus_id); -- return -ENODEV; -- } -+ if (data && data->type) { -+ for (i = 0, info = m25p_data; -+ i < ARRAY_SIZE(m25p_data); -+ i++, info++) { -+ if (strcmp(data->type, info->name) == 0) -+ break; -+ } - -- for (i = 0, info = m25p_data; i < ARRAY_SIZE(m25p_data); i++, info++) { -- if (strcmp(data->type, info->name) == 0) -- break; -- } -- if (i == ARRAY_SIZE(m25p_data)) { -- DEBUG(MTD_DEBUG_LEVEL1, "%s: unrecognized id %s\n", -- spi->dev.bus_id, data->type); -+ /* unrecognized chip? */ -+ if (i == ARRAY_SIZE(m25p_data)) { -+ DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", -+ spi->dev.bus_id, data->type); -+ info = NULL; -+ -+ /* recognized; is that chip really what's there? */ -+ } else if (info->jedec_id) { -+ struct flash_info *chip = jedec_probe(spi); -+ -+ if (!chip || chip != info) { -+ dev_warn(&spi->dev, "found %s, expected %s\n", -+ chip ? chip->name : "UNKNOWN", -+ info->name); -+ info = NULL; -+ } -+ } -+ } else -+ info = jedec_probe(spi); -+ -+ if (!info) - return -ENODEV; -- } - - flash = kzalloc(sizeof *flash, GFP_KERNEL); - if (!flash) - return -ENOMEM; - - flash->spi = spi; -- init_MUTEX(&flash->lock); -+ mutex_init(&flash->lock); - dev_set_drvdata(&spi->dev, flash); - -- if (data->name) -+ if (data && data->name) - flash->mtd.name = data->name; - else - flash->mtd.name = spi->dev.bus_id; -@@ -468,17 +584,25 @@ static int __devinit m25p_probe(struct spi_device *spi) - flash->mtd.writesize = 1; - flash->mtd.flags = MTD_CAP_NORFLASH; - flash->mtd.size = info->sector_size * info->n_sectors; -- flash->mtd.erasesize = info->sector_size; - flash->mtd.erase = m25p80_erase; - flash->mtd.read = m25p80_read; - flash->mtd.write = m25p80_write; - -+ /* prefer "small sector" erase if possible */ -+ if (info->flags & SECT_4K) { -+ flash->erase_opcode = OPCODE_BE_4K; -+ flash->mtd.erasesize = 4096; -+ } else { -+ flash->erase_opcode = OPCODE_SE; -+ flash->mtd.erasesize = info->sector_size; -+ } -+ - dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, - flash->mtd.size / 1024); - - DEBUG(MTD_DEBUG_LEVEL2, -- "mtd .name = %s, .size = 0x%.8x (%uM) " -- ".erasesize = 0x%.8x (%uK) .numeraseregions = %d\n", -+ "mtd .name = %s, .size = 0x%.8x (%uMiB) " -+ ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", - flash->mtd.name, - flash->mtd.size, flash->mtd.size / (1024*1024), - flash->mtd.erasesize, flash->mtd.erasesize / 1024, -@@ -488,7 +612,7 @@ static int __devinit m25p_probe(struct spi_device *spi) - for (i = 0; i < flash->mtd.numeraseregions; i++) - DEBUG(MTD_DEBUG_LEVEL2, - "mtd.eraseregions[%d] = { .offset = 0x%.8x, " -- ".erasesize = 0x%.8x (%uK), " -+ ".erasesize = 0x%.8x (%uKiB), " - ".numblocks = %d }\n", - i, flash->mtd.eraseregions[i].offset, - flash->mtd.eraseregions[i].erasesize, -@@ -516,14 +640,14 @@ static int __devinit m25p_probe(struct spi_device *spi) - } - - if (nr_parts > 0) { -- for (i = 0; i < data->nr_parts; i++) { -+ for (i = 0; i < nr_parts; i++) { - DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " - "{.name = %s, .offset = 0x%.8x, " -- ".size = 0x%.8x (%uK) }\n", -- i, data->parts[i].name, -- data->parts[i].offset, -- data->parts[i].size, -- data->parts[i].size / 1024); -+ ".size = 0x%.8x (%uKiB) }\n", -+ i, parts[i].name, -+ parts[i].offset, -+ parts[i].size, -+ parts[i].size / 1024); - } - flash->partitioned = 1; - return add_mtd_partitions(&flash->mtd, parts, nr_parts); -@@ -560,6 +684,11 @@ static struct spi_driver m25p80_driver = { - }, - .probe = m25p_probe, - .remove = __devexit_p(m25p_remove), -+ -+ /* REVISIT: many of these chips have deep power-down modes, which -+ * should clearly be entered on suspend() to minimize power use. -+ * And also when they're otherwise idle... -+ */ - }; - - -diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c -index a987e91..a5ed6d2 100644 ---- a/drivers/mtd/devices/mtd_dataflash.c -+++ b/drivers/mtd/devices/mtd_dataflash.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -89,7 +90,7 @@ struct dataflash { - unsigned short page_offset; /* offset in flash address */ - unsigned int page_size; /* of bytes per page */ - -- struct semaphore lock; -+ struct mutex lock; - struct spi_device *spi; - - struct mtd_info mtd; -@@ -167,7 +168,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) - x.len = 4; - spi_message_add_tail(&x, &msg); - -- down(&priv->lock); -+ mutex_lock(&priv->lock); - while (instr->len > 0) { - unsigned int pageaddr; - int status; -@@ -210,7 +211,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) - instr->len -= priv->page_size; - } - } -- up(&priv->lock); -+ mutex_unlock(&priv->lock); - - /* Inform MTD subsystem that erase is complete */ - instr->state = MTD_ERASE_DONE; -@@ -266,7 +267,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, - x[1].len = len; - spi_message_add_tail(&x[1], &msg); - -- down(&priv->lock); -+ mutex_lock(&priv->lock); - - /* Continuous read, max clock = f(car) which may be less than - * the peak rate available. Some chips support commands with -@@ -279,7 +280,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, - /* plus 4 "don't care" bytes */ - - status = spi_sync(priv->spi, &msg); -- up(&priv->lock); -+ mutex_unlock(&priv->lock); - - if (status >= 0) { - *retlen = msg.actual_length - 8; -@@ -336,7 +337,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, - else - writelen = len; - -- down(&priv->lock); -+ mutex_lock(&priv->lock); - while (remaining > 0) { - DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n", - pageaddr, offset, writelen); -@@ -441,7 +442,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, - else - writelen = remaining; - } -- up(&priv->lock); -+ mutex_unlock(&priv->lock); - - return status; - } -@@ -463,7 +464,7 @@ add_dataflash(struct spi_device *spi, char *name, - if (!priv) - return -ENOMEM; - -- init_MUTEX(&priv->lock); -+ mutex_init(&priv->lock); - priv->spi = spi; - priv->page_size = pagesize; - priv->page_offset = pageoffset; -diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c -index e8f686f..7060a08 100644 ---- a/drivers/mtd/devices/pmc551.c -+++ b/drivers/mtd/devices/pmc551.c -@@ -30,8 +30,8 @@ - * - * Notes: - * Due to what I assume is more buggy SROM, the 64M PMC551 I -- * have available claims that all 4 of it's DRAM banks have 64M -- * of ram configured (making a grand total of 256M onboard). -+ * have available claims that all 4 of its DRAM banks have 64MiB -+ * of ram configured (making a grand total of 256MiB onboard). - * This is slightly annoying since the BAR0 size reflects the - * aperture size, not the dram size, and the V370PDC supplies no - * other method for memory size discovery. This problem is -@@ -70,7 +70,7 @@ - * made the memory unusable, added a fix to code to touch up - * the DRAM some. - * -- * Bugs/FIXME's: -+ * Bugs/FIXMEs: - * * MUST fix the init function to not spin on a register - * waiting for it to set .. this does not safely handle busted - * devices that never reset the register correctly which will -@@ -562,10 +562,10 @@ static u32 fixup_pmc551(struct pci_dev *dev) - /* - * Some screen fun - */ -- printk(KERN_DEBUG "pmc551: %d%c (0x%x) of %sprefetchable memory at " -+ printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at " - "0x%llx\n", (size < 1024) ? size : (size < 1048576) ? - size >> 10 : size >> 20, -- (size < 1024) ? 'B' : (size < 1048576) ? 'K' : 'M', size, -+ (size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size, - ((dcmd & (0x1 << 3)) == 0) ? "non-" : "", - (unsigned long long)pci_resource_start(dev, 0)); - -@@ -649,14 +649,10 @@ MODULE_DESCRIPTION(PMC551_VERSION); - * Stuff these outside the ifdef so as to not bust compiled in driver support - */ - static int msize = 0; --#if defined(CONFIG_MTD_PMC551_APERTURE_SIZE) --static int asize = CONFIG_MTD_PMC551_APERTURE_SIZE; --#else - static int asize = 0; --#endif - - module_param(msize, int, 0); --MODULE_PARM_DESC(msize, "memory size in Megabytes [1 - 1024]"); -+MODULE_PARM_DESC(msize, "memory size in MiB [1 - 1024]"); - module_param(asize, int, 0); - MODULE_PARM_DESC(asize, "aperture size, must be <= memsize [1-1024]"); - -@@ -799,8 +795,7 @@ static int __init init_pmc551(void) - mtd->owner = THIS_MODULE; - - if (add_mtd_device(mtd)) { -- printk(KERN_NOTICE "pmc551: Failed to register new " -- "device\n"); -+ printk(KERN_NOTICE "pmc551: Failed to register new device\n"); - pci_iounmap(PCI_Device, priv->start); - kfree(mtd->priv); - kfree(mtd); -@@ -811,13 +806,13 @@ static int __init init_pmc551(void) - pci_dev_get(PCI_Device); - - printk(KERN_NOTICE "Registered pmc551 memory device.\n"); -- printk(KERN_NOTICE "Mapped %dM of memory from 0x%p to 0x%p\n", -+ printk(KERN_NOTICE "Mapped %dMiB of memory from 0x%p to 0x%p\n", - priv->asize >> 20, - priv->start, priv->start + priv->asize); -- printk(KERN_NOTICE "Total memory is %d%c\n", -+ printk(KERN_NOTICE "Total memory is %d%sB\n", - (length < 1024) ? length : - (length < 1048576) ? length >> 10 : length >> 20, -- (length < 1024) ? 'B' : (length < 1048576) ? 'K' : 'M'); -+ (length < 1024) ? "" : (length < 1048576) ? "Ki" : "Mi"); - priv->nextpmc551 = pmc551list; - pmc551list = mtd; - found++; -@@ -850,7 +845,7 @@ static void __exit cleanup_pmc551(void) - pmc551list = priv->nextpmc551; - - if (priv->start) { -- printk(KERN_DEBUG "pmc551: unmapping %dM starting at " -+ printk(KERN_DEBUG "pmc551: unmapping %dMiB starting at " - "0x%p\n", priv->asize >> 20, priv->start); - pci_iounmap(priv->dev, priv->start); - } -diff --git a/drivers/mtd/maps/nettel.c b/drivers/mtd/maps/nettel.c -index 7b96cd0..0c9b305 100644 ---- a/drivers/mtd/maps/nettel.c -+++ b/drivers/mtd/maps/nettel.c -@@ -158,68 +158,11 @@ static struct notifier_block nettel_notifier_block = { - nettel_reboot_notifier, NULL, 0 - }; - --/* -- * Erase the configuration file system. -- * Used to support the software reset button. -- */ --static void nettel_erasecallback(struct erase_info *done) --{ -- wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; -- wake_up(wait_q); --} -- --static struct erase_info nettel_erase; -- --int nettel_eraseconfig(void) --{ -- struct mtd_info *mtd; -- DECLARE_WAITQUEUE(wait, current); -- wait_queue_head_t wait_q; -- int ret; -- -- init_waitqueue_head(&wait_q); -- mtd = get_mtd_device(NULL, 2); -- if (!IS_ERR(mtd)) { -- nettel_erase.mtd = mtd; -- nettel_erase.callback = nettel_erasecallback; -- nettel_erase.callback = NULL; -- nettel_erase.addr = 0; -- nettel_erase.len = mtd->size; -- nettel_erase.priv = (u_long) &wait_q; -- nettel_erase.priv = 0; -- -- set_current_state(TASK_INTERRUPTIBLE); -- add_wait_queue(&wait_q, &wait); -- -- ret = mtd->erase(mtd, &nettel_erase); -- if (ret) { -- set_current_state(TASK_RUNNING); -- remove_wait_queue(&wait_q, &wait); -- put_mtd_device(mtd); -- return(ret); -- } -- -- schedule(); /* Wait for erase to finish. */ -- remove_wait_queue(&wait_q, &wait); -- -- put_mtd_device(mtd); -- } -- -- return(0); --} -- --#else -- --int nettel_eraseconfig(void) --{ -- return(0); --} -- - #endif - - /****************************************************************************/ - --int __init nettel_init(void) -+static int __init nettel_init(void) - { - volatile unsigned long *amdpar; - unsigned long amdaddr, maxsize; -@@ -421,10 +364,6 @@ int __init nettel_init(void) - - intel_mtd->owner = THIS_MODULE; - --#ifndef CONFIG_BLK_DEV_INITRD -- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1); --#endif -- - num_intel_partitions = sizeof(nettel_intel_partitions) / - sizeof(nettel_intel_partitions[0]); - -@@ -477,7 +416,7 @@ out_unmap2: - - /****************************************************************************/ - --void __exit nettel_cleanup(void) -+static void __exit nettel_cleanup(void) - { - #ifdef CONFIG_MTD_CFI_INTELEXT - unregister_reboot_notifier(&nettel_notifier_block); -diff --git a/drivers/mtd/maps/pmcmsp-ramroot.c b/drivers/mtd/maps/pmcmsp-ramroot.c -index 18049bc..30de5c0 100644 ---- a/drivers/mtd/maps/pmcmsp-ramroot.c -+++ b/drivers/mtd/maps/pmcmsp-ramroot.c -@@ -79,7 +79,6 @@ static int __init init_rrmap(void) - rr_mtd->owner = THIS_MODULE; - - add_mtd_device(rr_mtd); -- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, rr_mtd->index); - - return 0; - } -diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c -index ef89780..74d9d30 100644 ---- a/drivers/mtd/mtd_blkdevs.c -+++ b/drivers/mtd/mtd_blkdevs.c -@@ -24,10 +24,9 @@ - #include - #include - --static LIST_HEAD(blktrans_majors); -+#include "mtdcore.h" - --extern struct mutex mtd_table_mutex; --extern struct mtd_info *mtd_table[]; -+static LIST_HEAD(blktrans_majors); - - struct mtd_blkcore_priv { - struct task_struct *thread; -@@ -202,7 +201,7 @@ static int blktrans_ioctl(struct inode *inode, struct file *file, - } - } - --struct block_device_operations mtd_blktrans_ops = { -+static struct block_device_operations mtd_blktrans_ops = { - .owner = THIS_MODULE, - .open = blktrans_open, - .release = blktrans_release, -diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c -index d091b24..22ed96c 100644 ---- a/drivers/mtd/mtdchar.c -+++ b/drivers/mtd/mtdchar.c -@@ -136,7 +136,8 @@ static int mtd_close(struct inode *inode, struct file *file) - - DEBUG(MTD_DEBUG_LEVEL0, "MTD_close\n"); - -- if (mtd->sync) -+ /* Only sync if opened RW */ -+ if ((file->f_mode & 2) && mtd->sync) - mtd->sync(mtd); - - put_mtd_device(mtd); -diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c -index c153b64..6c2645e 100644 ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -22,6 +22,8 @@ - - #include - -+#include "mtdcore.h" -+ - /* These are exported solely for the purpose of mtd_blkdevs.c. You - should not use them for _anything_ else */ - DEFINE_MUTEX(mtd_table_mutex); -diff --git a/drivers/mtd/mtdcore.h b/drivers/mtd/mtdcore.h -new file mode 100644 -index 0000000..a33251f ---- /dev/null -+++ b/drivers/mtd/mtdcore.h -@@ -0,0 +1,11 @@ -+/* linux/drivers/mtd/mtdcore.h -+ * -+ * Header file for driver private mtdcore exports -+ * -+ */ -+ -+/* These are exported solely for the purpose of mtd_blkdevs.c. You -+ should not use them for _anything_ else */ -+ -+extern struct mutex mtd_table_mutex; -+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES]; -diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c -new file mode 100644 -index 0000000..cfc28ab ---- /dev/null -+++ b/drivers/mtd/mtdoops.c -@@ -0,0 +1,365 @@ -+/* -+ * MTD Oops/Panic logger -+ * -+ * Copyright (C) 2007 Nokia Corporation. All rights reserved. -+ * -+ * Author: Richard Purdie -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define OOPS_PAGE_SIZE 4096 -+ -+static struct mtdoops_context { -+ int mtd_index; -+ struct work_struct work; -+ struct mtd_info *mtd; -+ int oops_pages; -+ int nextpage; -+ int nextcount; -+ -+ void *oops_buf; -+ int ready; -+ int writecount; -+} oops_cxt; -+ -+static void mtdoops_erase_callback(struct erase_info *done) -+{ -+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; -+ wake_up(wait_q); -+} -+ -+static int mtdoops_erase_block(struct mtd_info *mtd, int offset) -+{ -+ struct erase_info erase; -+ DECLARE_WAITQUEUE(wait, current); -+ wait_queue_head_t wait_q; -+ int ret; -+ -+ init_waitqueue_head(&wait_q); -+ erase.mtd = mtd; -+ erase.callback = mtdoops_erase_callback; -+ erase.addr = offset; -+ if (mtd->erasesize < OOPS_PAGE_SIZE) -+ erase.len = OOPS_PAGE_SIZE; -+ else -+ erase.len = mtd->erasesize; -+ erase.priv = (u_long)&wait_q; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ add_wait_queue(&wait_q, &wait); -+ -+ ret = mtd->erase(mtd, &erase); -+ if (ret) { -+ set_current_state(TASK_RUNNING); -+ remove_wait_queue(&wait_q, &wait); -+ printk (KERN_WARNING "mtdoops: erase of region [0x%x, 0x%x] " -+ "on \"%s\" failed\n", -+ erase.addr, erase.len, mtd->name); -+ return ret; -+ } -+ -+ schedule(); /* Wait for erase to finish. */ -+ remove_wait_queue(&wait_q, &wait); -+ -+ return 0; -+} -+ -+static int mtdoops_inc_counter(struct mtdoops_context *cxt) -+{ -+ struct mtd_info *mtd = cxt->mtd; -+ size_t retlen; -+ u32 count; -+ int ret; -+ -+ cxt->nextpage++; -+ if (cxt->nextpage > cxt->oops_pages) -+ cxt->nextpage = 0; -+ cxt->nextcount++; -+ if (cxt->nextcount == 0xffffffff) -+ cxt->nextcount = 0; -+ -+ ret = mtd->read(mtd, cxt->nextpage * OOPS_PAGE_SIZE, 4, -+ &retlen, (u_char *) &count); -+ if ((retlen != 4) || (ret < 0)) { -+ printk(KERN_ERR "mtdoops: Read failure at %d (%d of 4 read)" -+ ", err %d.\n", cxt->nextpage * OOPS_PAGE_SIZE, -+ retlen, ret); -+ return 1; -+ } -+ -+ /* See if we need to erase the next block */ -+ if (count != 0xffffffff) -+ return 1; -+ -+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (no erase)\n", -+ cxt->nextpage, cxt->nextcount); -+ cxt->ready = 1; -+ return 0; -+} -+ -+static void mtdoops_prepare(struct mtdoops_context *cxt) -+{ -+ struct mtd_info *mtd = cxt->mtd; -+ int i = 0, j, ret, mod; -+ -+ /* We were unregistered */ -+ if (!mtd) -+ return; -+ -+ mod = (cxt->nextpage * OOPS_PAGE_SIZE) % mtd->erasesize; -+ if (mod != 0) { -+ cxt->nextpage = cxt->nextpage + ((mtd->erasesize - mod) / OOPS_PAGE_SIZE); -+ if (cxt->nextpage > cxt->oops_pages) -+ cxt->nextpage = 0; -+ } -+ -+ while (mtd->block_isbad && -+ mtd->block_isbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE)) { -+badblock: -+ printk(KERN_WARNING "mtdoops: Bad block at %08x\n", -+ cxt->nextpage * OOPS_PAGE_SIZE); -+ i++; -+ cxt->nextpage = cxt->nextpage + (mtd->erasesize / OOPS_PAGE_SIZE); -+ if (cxt->nextpage > cxt->oops_pages) -+ cxt->nextpage = 0; -+ if (i == (cxt->oops_pages / (mtd->erasesize / OOPS_PAGE_SIZE))) { -+ printk(KERN_ERR "mtdoops: All blocks bad!\n"); -+ return; -+ } -+ } -+ -+ for (j = 0, ret = -1; (j < 3) && (ret < 0); j++) -+ ret = mtdoops_erase_block(mtd, cxt->nextpage * OOPS_PAGE_SIZE); -+ -+ if (ret < 0) { -+ if (mtd->block_markbad) -+ mtd->block_markbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE); -+ goto badblock; -+ } -+ -+ printk(KERN_DEBUG "mtdoops: Ready %d, %d \n", cxt->nextpage, cxt->nextcount); -+ -+ cxt->ready = 1; -+} -+ -+static void mtdoops_workfunc(struct work_struct *work) -+{ -+ struct mtdoops_context *cxt = -+ container_of(work, struct mtdoops_context, work); -+ -+ mtdoops_prepare(cxt); -+} -+ -+static int find_next_position(struct mtdoops_context *cxt) -+{ -+ struct mtd_info *mtd = cxt->mtd; -+ int page, maxpos = 0; -+ u32 count, maxcount = 0xffffffff; -+ size_t retlen; -+ -+ for (page = 0; page < cxt->oops_pages; page++) { -+ mtd->read(mtd, page * OOPS_PAGE_SIZE, 4, &retlen, (u_char *) &count); -+ if (count == 0xffffffff) -+ continue; -+ if (maxcount == 0xffffffff) { -+ maxcount = count; -+ maxpos = page; -+ } else if ((count < 0x40000000) && (maxcount > 0xc0000000)) { -+ maxcount = count; -+ maxpos = page; -+ } else if ((count > maxcount) && (count < 0xc0000000)) { -+ maxcount = count; -+ maxpos = page; -+ } else if ((count > maxcount) && (count > 0xc0000000) -+ && (maxcount > 0x80000000)) { -+ maxcount = count; -+ maxpos = page; -+ } -+ } -+ if (maxcount == 0xffffffff) { -+ cxt->nextpage = 0; -+ cxt->nextcount = 1; -+ cxt->ready = 1; -+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (first init)\n", -+ cxt->nextpage, cxt->nextcount); -+ return 0; -+ } -+ -+ cxt->nextpage = maxpos; -+ cxt->nextcount = maxcount; -+ -+ return mtdoops_inc_counter(cxt); -+} -+ -+ -+static void mtdoops_notify_add(struct mtd_info *mtd) -+{ -+ struct mtdoops_context *cxt = &oops_cxt; -+ int ret; -+ -+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0) -+ return; -+ -+ if (mtd->size < (mtd->erasesize * 2)) { -+ printk(KERN_ERR "MTD partition %d not big enough for mtdoops\n", -+ mtd->index); -+ return; -+ } -+ -+ cxt->mtd = mtd; -+ cxt->oops_pages = mtd->size / OOPS_PAGE_SIZE; -+ -+ ret = find_next_position(cxt); -+ if (ret == 1) -+ mtdoops_prepare(cxt); -+ -+ printk(KERN_DEBUG "mtdoops: Attached to MTD device %d\n", mtd->index); -+} -+ -+static void mtdoops_notify_remove(struct mtd_info *mtd) -+{ -+ struct mtdoops_context *cxt = &oops_cxt; -+ -+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0) -+ return; -+ -+ cxt->mtd = NULL; -+ flush_scheduled_work(); -+} -+ -+ -+static void -+mtdoops_console_write(struct console *co, const char *s, unsigned int count) -+{ -+ struct mtdoops_context *cxt = co->data; -+ struct mtd_info *mtd = cxt->mtd; -+ int i, ret; -+ -+ if (!cxt->ready || !mtd) -+ return; -+ -+ if (!oops_in_progress && cxt->writecount != 0) { -+ size_t retlen; -+ if (cxt->writecount < OOPS_PAGE_SIZE) -+ memset(cxt->oops_buf + cxt->writecount, 0xff, -+ OOPS_PAGE_SIZE - cxt->writecount); -+ -+ ret = mtd->write(mtd, cxt->nextpage * OOPS_PAGE_SIZE, -+ OOPS_PAGE_SIZE, &retlen, cxt->oops_buf); -+ cxt->ready = 0; -+ cxt->writecount = 0; -+ -+ if ((retlen != OOPS_PAGE_SIZE) || (ret < 0)) -+ printk(KERN_ERR "mtdoops: Write failure at %d (%d of %d" -+ " written), err %d.\n", -+ cxt->nextpage * OOPS_PAGE_SIZE, retlen, -+ OOPS_PAGE_SIZE, ret); -+ -+ ret = mtdoops_inc_counter(cxt); -+ if (ret == 1) -+ schedule_work(&cxt->work); -+ } -+ -+ if (!oops_in_progress) -+ return; -+ -+ if (cxt->writecount == 0) { -+ u32 *stamp = cxt->oops_buf; -+ *stamp = cxt->nextcount; -+ cxt->writecount = 4; -+ } -+ -+ if ((count + cxt->writecount) > OOPS_PAGE_SIZE) -+ count = OOPS_PAGE_SIZE - cxt->writecount; -+ -+ for (i = 0; i < count; i++, s++) -+ *((char *)(cxt->oops_buf) + cxt->writecount + i) = *s; -+ -+ cxt->writecount = cxt->writecount + count; -+} -+ -+static int __init mtdoops_console_setup(struct console *co, char *options) -+{ -+ struct mtdoops_context *cxt = co->data; -+ -+ if (cxt->mtd_index != -1) -+ return -EBUSY; -+ if (co->index == -1) -+ return -EINVAL; -+ -+ cxt->mtd_index = co->index; -+ return 0; -+} -+ -+static struct mtd_notifier mtdoops_notifier = { -+ .add = mtdoops_notify_add, -+ .remove = mtdoops_notify_remove, -+}; -+ -+static struct console mtdoops_console = { -+ .name = "ttyMTD", -+ .write = mtdoops_console_write, -+ .setup = mtdoops_console_setup, -+ .flags = CON_PRINTBUFFER, -+ .index = -1, -+ .data = &oops_cxt, -+}; -+ -+static int __init mtdoops_console_init(void) -+{ -+ struct mtdoops_context *cxt = &oops_cxt; -+ -+ cxt->mtd_index = -1; -+ cxt->oops_buf = vmalloc(OOPS_PAGE_SIZE); -+ -+ if (!cxt->oops_buf) { -+ printk(KERN_ERR "Failed to allocate oops buffer workspace\n"); -+ return -ENOMEM; -+ } -+ -+ INIT_WORK(&cxt->work, mtdoops_workfunc); -+ -+ register_console(&mtdoops_console); -+ register_mtd_user(&mtdoops_notifier); -+ return 0; -+} -+ -+static void __exit mtdoops_console_exit(void) -+{ -+ struct mtdoops_context *cxt = &oops_cxt; -+ -+ unregister_mtd_user(&mtdoops_notifier); -+ unregister_console(&mtdoops_console); -+ vfree(cxt->oops_buf); -+} -+ -+ -+subsys_initcall(mtdoops_console_init); -+module_exit(mtdoops_console_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Richard Purdie "); -+MODULE_DESCRIPTION("MTD Oops/Panic console logger/driver"); -diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig -index f1d60b6..df25cab 100644 ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -134,10 +134,10 @@ config MTD_NAND_S3C2410_HWECC - - config MTD_NAND_NDFC - tristate "NDFC NanD Flash Controller" -- depends on 44x -+ depends on 4xx - select MTD_NAND_ECC_SMC - help -- NDFC Nand Flash Controllers are integrated in EP44x SoCs -+ NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs - - config MTD_NAND_S3C2410_CLKSTOP - bool "S3C2410 NAND IDLE clock stop" -@@ -237,7 +237,7 @@ config MTD_NAND_CAFE - select REED_SOLOMON - select REED_SOLOMON_DEC16 - help -- Use NAND flash attached to the CAFÉ chip designed for the $100 -+ Use NAND flash attached to the CAFÉ chip designed for the OLPC - laptop. - - config MTD_NAND_CS553X -diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c -index cff969d..cca69b3 100644 ---- a/drivers/mtd/nand/cafe_nand.c -+++ b/drivers/mtd/nand/cafe_nand.c -@@ -821,14 +821,53 @@ static struct pci_device_id cafe_nand_tbl[] = { - - MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); - -+static int cafe_nand_resume(struct pci_dev *pdev) -+{ -+ uint32_t timing1, timing2, timing3; -+ uint32_t ctrl; -+ struct mtd_info *mtd = pci_get_drvdata(pdev); -+ struct cafe_priv *cafe = mtd->priv; -+ -+ timing1 = timing2 = timing3 = 0xffffffff; -+ /* Start off by resetting the NAND controller completely */ -+ cafe_writel(cafe, 1, NAND_RESET); -+ cafe_writel(cafe, 0, NAND_RESET); -+ cafe_writel(cafe, timing1, NAND_TIMING1); -+ cafe_writel(cafe, timing2, NAND_TIMING2); -+ cafe_writel(cafe, timing3, NAND_TIMING3); -+ cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); -+ -+ /* Disable master reset, enable NAND clock */ -+ ctrl = cafe_readl(cafe, GLOBAL_CTRL); -+ ctrl &= 0xffffeff0; -+ ctrl |= 0x00007000; -+ cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); -+ cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); -+ cafe_writel(cafe, 0, NAND_DMA_CTRL); -+ cafe_writel(cafe, 0x7006, GLOBAL_CTRL); -+ cafe_writel(cafe, 0x700a, GLOBAL_CTRL); -+ -+ /* Set up DMA address */ -+ cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); -+ if (sizeof(cafe->dmaaddr) > 4) -+ /* Shift in two parts to shut the compiler up */ -+ cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); -+ else -+ cafe_writel(cafe, 0, NAND_DMA_ADDR1); -+ -+ /* Enable NAND IRQ in global IRQ mask register */ -+ cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); -+ return 0; -+} -+ - static struct pci_driver cafe_nand_pci_driver = { - .name = "CAFÉ NAND", - .id_table = cafe_nand_tbl, - .probe = cafe_nand_probe, - .remove = __devexit_p(cafe_nand_remove), -+ .resume = cafe_nand_resume, - #ifdef CONFIG_PMx - .suspend = cafe_nand_suspend, -- .resume = cafe_nand_resume, - #endif - }; - -diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c -index fd7a8d5..1c0e89f 100644 ---- a/drivers/mtd/nand/ndfc.c -+++ b/drivers/mtd/nand/ndfc.c -@@ -24,7 +24,11 @@ - #include - - #include -+#ifdef CONFIG_40x -+#include -+#else - #include -+#endif - - struct ndfc_nand_mtd { - struct mtd_info mtd; -@@ -230,7 +234,11 @@ static int ndfc_nand_probe(struct platform_device *pdev) - struct ndfc_controller *ndfc = &ndfc_ctrl; - unsigned long long phys = settings->ndfc_erpn | res->start; - -+#ifndef CONFIG_PHYS_64BIT -+ ndfc->ndfcbase = ioremap((phys_addr_t)phys, res->end - res->start + 1); -+#else - ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1); -+#endif - if (!ndfc->ndfcbase) { - printk(KERN_ERR "NDFC: ioremap failed\n"); - return -EIO; -diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig -index c257d39..cb41cbc 100644 ---- a/drivers/mtd/onenand/Kconfig -+++ b/drivers/mtd/onenand/Kconfig -@@ -40,4 +40,27 @@ config MTD_ONENAND_OTP - - OTP block is fully-guaranteed to be a valid block. - -+config MTD_ONENAND_2X_PROGRAM -+ bool "OneNAND 2X program support" -+ help -+ The 2X Program is an extension of Program Operation. -+ Since the device is equipped with two DataRAMs, and two-plane NAND -+ Flash memory array, these two component enables simultaneous program -+ of 4KiB. Plane1 has only even blocks such as block0, block2, block4 -+ while Plane2 has only odd blocks such as block1, block3, block5. -+ So MTD regards it as 4KiB page size and 256KiB block size -+ -+ Now the following chips support it. (KFXXX16Q2M) -+ Demux: KFG2G16Q2M, KFH4G16Q2M, KFW8G16Q2M, -+ Mux: KFM2G16Q2M, KFN4G16Q2M, -+ -+ And more recent chips -+ -+config MTD_ONENAND_SIM -+ tristate "OneNAND simulator support" -+ depends on MTD_PARTITIONS -+ help -+ The simulator may simulate various OneNAND flash chips for the -+ OneNAND MTD layer. -+ - endif # MTD_ONENAND -diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile -index 269cfe4..4d2eacf 100644 ---- a/drivers/mtd/onenand/Makefile -+++ b/drivers/mtd/onenand/Makefile -@@ -8,4 +8,7 @@ obj-$(CONFIG_MTD_ONENAND) += onenand.o - # Board specific. - obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o - -+# Simulator -+obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o -+ - onenand-objs = onenand_base.o onenand_bbt.o -diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c -index 0537fac..7d194cf 100644 ---- a/drivers/mtd/onenand/onenand_base.c -+++ b/drivers/mtd/onenand/onenand_base.c -@@ -206,6 +206,15 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le - default: - block = (int) (addr >> this->erase_shift); - page = (int) (addr >> this->page_shift); -+ -+ if (ONENAND_IS_2PLANE(this)) { -+ /* Make the even block number */ -+ block &= ~1; -+ /* Is it the odd plane? */ -+ if (addr & this->writesize) -+ block++; -+ page >>= 1; -+ } - page &= this->page_mask; - break; - } -@@ -216,8 +225,12 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le - value = onenand_bufferram_address(this, block); - this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); - -- /* Switch to the next data buffer */ -- ONENAND_SET_NEXT_BUFFERRAM(this); -+ if (ONENAND_IS_2PLANE(this)) -+ /* It is always BufferRAM0 */ -+ ONENAND_SET_BUFFERRAM0(this); -+ else -+ /* Switch to the next data buffer */ -+ ONENAND_SET_NEXT_BUFFERRAM(this); - - return 0; - } -@@ -247,6 +260,8 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le - break; - - default: -+ if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG) -+ cmd = ONENAND_CMD_2X_PROG; - dataram = ONENAND_CURRENT_BUFFERRAM(this); - break; - } -@@ -445,8 +460,9 @@ static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) - struct onenand_chip *this = mtd->priv; - - if (ONENAND_CURRENT_BUFFERRAM(this)) { -+ /* Note: the 'this->writesize' is a real page size */ - if (area == ONENAND_DATARAM) -- return mtd->writesize; -+ return this->writesize; - if (area == ONENAND_SPARERAM) - return mtd->oobsize; - } -@@ -572,6 +588,30 @@ static int onenand_write_bufferram(struct mtd_info *mtd, int area, - } - - /** -+ * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode -+ * @param mtd MTD data structure -+ * @param addr address to check -+ * @return blockpage address -+ * -+ * Get blockpage address at 2x program mode -+ */ -+static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr) -+{ -+ struct onenand_chip *this = mtd->priv; -+ int blockpage, block, page; -+ -+ /* Calculate the even block number */ -+ block = (int) (addr >> this->erase_shift) & ~1; -+ /* Is it the odd plane? */ -+ if (addr & this->writesize) -+ block++; -+ page = (int) (addr >> (this->page_shift + 1)) & this->page_mask; -+ blockpage = (block << 7) | page; -+ -+ return blockpage; -+} -+ -+/** - * onenand_check_bufferram - [GENERIC] Check BufferRAM information - * @param mtd MTD data structure - * @param addr address to check -@@ -585,7 +625,10 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) - int blockpage, found = 0; - unsigned int i; - -- blockpage = (int) (addr >> this->page_shift); -+ if (ONENAND_IS_2PLANE(this)) -+ blockpage = onenand_get_2x_blockpage(mtd, addr); -+ else -+ blockpage = (int) (addr >> this->page_shift); - - /* Is there valid data? */ - i = ONENAND_CURRENT_BUFFERRAM(this); -@@ -625,7 +668,10 @@ static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, - int blockpage; - unsigned int i; - -- blockpage = (int) (addr >> this->page_shift); -+ if (ONENAND_IS_2PLANE(this)) -+ blockpage = onenand_get_2x_blockpage(mtd, addr); -+ else -+ blockpage = (int) (addr >> this->page_shift); - - /* Invalidate another BufferRAM */ - i = ONENAND_NEXT_BUFFERRAM(this); -@@ -734,6 +780,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, - int read = 0, column; - int thislen; - int ret = 0, boundary = 0; -+ int writesize = this->writesize; - - DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); - -@@ -754,22 +801,22 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, - /* Do first load to bufferRAM */ - if (read < len) { - if (!onenand_check_bufferram(mtd, from)) { -- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); -+ this->command(mtd, ONENAND_CMD_READ, from, writesize); - ret = this->wait(mtd, FL_READING); - onenand_update_bufferram(mtd, from, !ret); - } - } - -- thislen = min_t(int, mtd->writesize, len - read); -- column = from & (mtd->writesize - 1); -- if (column + thislen > mtd->writesize) -- thislen = mtd->writesize - column; -+ thislen = min_t(int, writesize, len - read); -+ column = from & (writesize - 1); -+ if (column + thislen > writesize) -+ thislen = writesize - column; - - while (!ret) { - /* If there is more to load then start next load */ - from += thislen; - if (read + thislen < len) { -- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); -+ this->command(mtd, ONENAND_CMD_READ, from, writesize); - /* - * Chip boundary handling in DDP - * Now we issued chip 1 read and pointed chip 1 -@@ -794,7 +841,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, - this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); - ONENAND_SET_NEXT_BUFFERRAM(this); - buf += thislen; -- thislen = min_t(int, mtd->writesize, len - read); -+ thislen = min_t(int, writesize, len - read); - column = 0; - cond_resched(); - /* Now wait for load */ -@@ -1079,7 +1126,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, - /* Read more? */ - if (read < len) { - /* Update Page size */ -- from += mtd->writesize; -+ from += this->writesize; - column = 0; - } - } -@@ -1135,12 +1182,12 @@ static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, - int thislen, column; - - while (len != 0) { -- thislen = min_t(int, mtd->writesize, len); -- column = addr & (mtd->writesize - 1); -- if (column + thislen > mtd->writesize) -- thislen = mtd->writesize - column; -+ thislen = min_t(int, this->writesize, len); -+ column = addr & (this->writesize - 1); -+ if (column + thislen > this->writesize) -+ thislen = this->writesize - column; - -- this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); -+ this->command(mtd, ONENAND_CMD_READ, addr, this->writesize); - - onenand_update_bufferram(mtd, addr, 0); - -@@ -1236,6 +1283,10 @@ static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, - - /* In partial page write we don't update bufferram */ - onenand_update_bufferram(mtd, to, !ret && !subpage); -+ if (ONENAND_IS_2PLANE(this)) { -+ ONENAND_SET_BUFFERRAM1(this); -+ onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage); -+ } - - if (ret) { - printk(KERN_ERR "onenand_write: write filaed %d\n", ret); -@@ -1384,6 +1435,10 @@ static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, - this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); - - onenand_update_bufferram(mtd, to, 0); -+ if (ONENAND_IS_2PLANE(this)) { -+ ONENAND_SET_BUFFERRAM1(this); -+ onenand_update_bufferram(mtd, to + this->writesize, 0); -+ } - - ret = this->wait(mtd, FL_WRITING); - if (ret) { -@@ -2107,6 +2162,7 @@ static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, - * - * Check and set OneNAND features - * - lock scheme -+ * - two plane - */ - static void onenand_check_features(struct mtd_info *mtd) - { -@@ -2118,19 +2174,35 @@ static void onenand_check_features(struct mtd_info *mtd) - process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; - - /* Lock scheme */ -- if (density >= ONENAND_DEVICE_DENSITY_1Gb) { -+ switch (density) { -+ case ONENAND_DEVICE_DENSITY_4Gb: -+ this->options |= ONENAND_HAS_2PLANE; -+ -+ case ONENAND_DEVICE_DENSITY_2Gb: -+ /* 2Gb DDP don't have 2 plane */ -+ if (!ONENAND_IS_DDP(this)) -+ this->options |= ONENAND_HAS_2PLANE; -+ this->options |= ONENAND_HAS_UNLOCK_ALL; -+ -+ case ONENAND_DEVICE_DENSITY_1Gb: - /* A-Die has all block unlock */ -- if (process) { -- printk(KERN_DEBUG "Chip support all block unlock\n"); -+ if (process) - this->options |= ONENAND_HAS_UNLOCK_ALL; -- } -- } else { -- /* Some OneNAND has continues lock scheme */ -- if (!process) { -- printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); -+ break; -+ -+ default: -+ /* Some OneNAND has continuous lock scheme */ -+ if (!process) - this->options |= ONENAND_HAS_CONT_LOCK; -- } -+ break; - } -+ -+ if (this->options & ONENAND_HAS_CONT_LOCK) -+ printk(KERN_DEBUG "Lock scheme is Continuous Lock\n"); -+ if (this->options & ONENAND_HAS_UNLOCK_ALL) -+ printk(KERN_DEBUG "Chip support all block unlock\n"); -+ if (this->options & ONENAND_HAS_2PLANE) -+ printk(KERN_DEBUG "Chip has 2 plane\n"); - } - - /** -@@ -2257,6 +2329,8 @@ static int onenand_probe(struct mtd_info *mtd) - this->erase_shift = ffs(mtd->erasesize) - 1; - this->page_shift = ffs(mtd->writesize) - 1; - this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1; -+ /* It's real page size */ -+ this->writesize = mtd->writesize; - - /* REVIST: Multichip handling */ - -@@ -2265,6 +2339,17 @@ static int onenand_probe(struct mtd_info *mtd) - /* Check OneNAND features */ - onenand_check_features(mtd); - -+ /* -+ * We emulate the 4KiB page and 256KiB erase block size -+ * But oobsize is still 64 bytes. -+ * It is only valid if you turn on 2X program support, -+ * Otherwise it will be ignored by compiler. -+ */ -+ if (ONENAND_IS_2PLANE(this)) { -+ mtd->writesize <<= 1; -+ mtd->erasesize <<= 1; -+ } -+ - return 0; - } - -diff --git a/drivers/mtd/onenand/onenand_sim.c b/drivers/mtd/onenand/onenand_sim.c -new file mode 100644 -index 0000000..b806673 ---- /dev/null -+++ b/drivers/mtd/onenand/onenand_sim.c -@@ -0,0 +1,495 @@ -+/* -+ * linux/drivers/mtd/onenand/onenand_sim.c -+ * -+ * The OneNAND simulator -+ * -+ * Copyright © 2005-2007 Samsung Electronics -+ * Kyungmin Park -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#ifndef CONFIG_ONENAND_SIM_MANUFACTURER -+#define CONFIG_ONENAND_SIM_MANUFACTURER 0xec -+#endif -+#ifndef CONFIG_ONENAND_SIM_DEVICE_ID -+#define CONFIG_ONENAND_SIM_DEVICE_ID 0x04 -+#endif -+#ifndef CONFIG_ONENAND_SIM_VERSION_ID -+#define CONFIG_ONENAND_SIM_VERSION_ID 0x1e -+#endif -+ -+static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER; -+static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID; -+static int version_id = CONFIG_ONENAND_SIM_VERSION_ID; -+ -+struct onenand_flash { -+ void __iomem *base; -+ void __iomem *data; -+}; -+ -+#define ONENAND_CORE(flash) (flash->data) -+#define ONENAND_CORE_SPARE(flash, this, offset) \ -+ ((flash->data) + (this->chipsize) + (offset >> 5)) -+ -+#define ONENAND_MAIN_AREA(this, offset) \ -+ (this->base + ONENAND_DATARAM + offset) -+ -+#define ONENAND_SPARE_AREA(this, offset) \ -+ (this->base + ONENAND_SPARERAM + offset) -+ -+#define ONENAND_GET_WP_STATUS(this) \ -+ (readw(this->base + ONENAND_REG_WP_STATUS)) -+ -+#define ONENAND_SET_WP_STATUS(v, this) \ -+ (writew(v, this->base + ONENAND_REG_WP_STATUS)) -+ -+/* It has all 0xff chars */ -+#define MAX_ONENAND_PAGESIZE (2048 + 64) -+static unsigned char *ffchars; -+ -+static struct mtd_partition os_partitions[] = { -+ { -+ .name = "OneNAND simulator partition", -+ .offset = 0, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+/* -+ * OneNAND simulator mtd -+ */ -+struct onenand_info { -+ struct mtd_info mtd; -+ struct mtd_partition *parts; -+ struct onenand_chip onenand; -+ struct onenand_flash flash; -+}; -+ -+struct onenand_info *info; -+ -+#define DPRINTK(format, args...) \ -+do { \ -+ printk(KERN_DEBUG "%s[%d]: " format "\n", __func__, \ -+ __LINE__, ##args); \ -+} while (0) -+ -+/** -+ * onenand_lock_handle - Handle Lock scheme -+ * @param this OneNAND device structure -+ * @param cmd The command to be sent -+ * -+ * Send lock command to OneNAND device. -+ * The lock scheme is depends on chip type. -+ */ -+static void onenand_lock_handle(struct onenand_chip *this, int cmd) -+{ -+ int block_lock_scheme; -+ int status; -+ -+ status = ONENAND_GET_WP_STATUS(this); -+ block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK); -+ -+ switch (cmd) { -+ case ONENAND_CMD_UNLOCK: -+ if (block_lock_scheme) -+ ONENAND_SET_WP_STATUS(ONENAND_WP_US, this); -+ else -+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this); -+ break; -+ -+ case ONENAND_CMD_LOCK: -+ if (block_lock_scheme) -+ ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this); -+ else -+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this); -+ break; -+ -+ case ONENAND_CMD_LOCK_TIGHT: -+ if (block_lock_scheme) -+ ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this); -+ else -+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS, this); -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+/** -+ * onenand_bootram_handle - Handle BootRAM area -+ * @param this OneNAND device structure -+ * @param cmd The command to be sent -+ * -+ * Emulate BootRAM area. It is possible to do basic operation using BootRAM. -+ */ -+static void onenand_bootram_handle(struct onenand_chip *this, int cmd) -+{ -+ switch (cmd) { -+ case ONENAND_CMD_READID: -+ writew(manuf_id, this->base); -+ writew(device_id, this->base + 2); -+ writew(version_id, this->base + 4); -+ break; -+ -+ default: -+ /* REVIST: Handle other commands */ -+ break; -+ } -+} -+ -+/** -+ * onenand_update_interrupt - Set interrupt register -+ * @param this OneNAND device structure -+ * @param cmd The command to be sent -+ * -+ * Update interrupt register. The status is depends on command. -+ */ -+static void onenand_update_interrupt(struct onenand_chip *this, int cmd) -+{ -+ int interrupt = ONENAND_INT_MASTER; -+ -+ switch (cmd) { -+ case ONENAND_CMD_READ: -+ case ONENAND_CMD_READOOB: -+ interrupt |= ONENAND_INT_READ; -+ break; -+ -+ case ONENAND_CMD_PROG: -+ case ONENAND_CMD_PROGOOB: -+ interrupt |= ONENAND_INT_WRITE; -+ break; -+ -+ case ONENAND_CMD_ERASE: -+ interrupt |= ONENAND_INT_ERASE; -+ break; -+ -+ case ONENAND_CMD_RESET: -+ interrupt |= ONENAND_INT_RESET; -+ break; -+ -+ default: -+ break; -+ } -+ -+ writew(interrupt, this->base + ONENAND_REG_INTERRUPT); -+} -+ -+/** -+ * onenand_check_overwrite - Check over-write if happend -+ * @param dest The destination pointer -+ * @param src The source pointer -+ * @param count The length to be check -+ * @return 0 on same, otherwise 1 -+ * -+ * Compare the source with destination -+ */ -+static int onenand_check_overwrite(void *dest, void *src, size_t count) -+{ -+ unsigned int *s = (unsigned int *) src; -+ unsigned int *d = (unsigned int *) dest; -+ int i; -+ -+ count >>= 2; -+ for (i = 0; i < count; i++) -+ if ((*s++ ^ *d++) != 0) -+ return 1; -+ -+ return 0; -+} -+ -+/** -+ * onenand_data_handle - Handle OneNAND Core and DataRAM -+ * @param this OneNAND device structure -+ * @param cmd The command to be sent -+ * @param dataram Which dataram used -+ * @param offset The offset to OneNAND Core -+ * -+ * Copy data from OneNAND Core to DataRAM (read) -+ * Copy data from DataRAM to OneNAND Core (write) -+ * Erase the OneNAND Core (erase) -+ */ -+static void onenand_data_handle(struct onenand_chip *this, int cmd, -+ int dataram, unsigned int offset) -+{ -+ struct mtd_info *mtd = &info->mtd; -+ struct onenand_flash *flash = this->priv; -+ int main_offset, spare_offset; -+ void __iomem *src; -+ void __iomem *dest; -+ unsigned int i; -+ -+ if (dataram) { -+ main_offset = mtd->writesize; -+ spare_offset = mtd->oobsize; -+ } else { -+ main_offset = 0; -+ spare_offset = 0; -+ } -+ -+ switch (cmd) { -+ case ONENAND_CMD_READ: -+ src = ONENAND_CORE(flash) + offset; -+ dest = ONENAND_MAIN_AREA(this, main_offset); -+ memcpy(dest, src, mtd->writesize); -+ /* Fall through */ -+ -+ case ONENAND_CMD_READOOB: -+ src = ONENAND_CORE_SPARE(flash, this, offset); -+ dest = ONENAND_SPARE_AREA(this, spare_offset); -+ memcpy(dest, src, mtd->oobsize); -+ break; -+ -+ case ONENAND_CMD_PROG: -+ src = ONENAND_MAIN_AREA(this, main_offset); -+ dest = ONENAND_CORE(flash) + offset; -+ /* To handle partial write */ -+ for (i = 0; i < (1 << mtd->subpage_sft); i++) { -+ int off = i * this->subpagesize; -+ if (!memcmp(src + off, ffchars, this->subpagesize)) -+ continue; -+ if (memcmp(dest + off, ffchars, this->subpagesize) && -+ onenand_check_overwrite(dest + off, src + off, this->subpagesize)) -+ printk(KERN_ERR "over-write happend at 0x%08x\n", offset); -+ memcpy(dest + off, src + off, this->subpagesize); -+ } -+ /* Fall through */ -+ -+ case ONENAND_CMD_PROGOOB: -+ src = ONENAND_SPARE_AREA(this, spare_offset); -+ /* Check all data is 0xff chars */ -+ if (!memcmp(src, ffchars, mtd->oobsize)) -+ break; -+ -+ dest = ONENAND_CORE_SPARE(flash, this, offset); -+ if (memcmp(dest, ffchars, mtd->oobsize) && -+ onenand_check_overwrite(dest, src, mtd->oobsize)) -+ printk(KERN_ERR "OOB: over-write happend at 0x%08x\n", -+ offset); -+ memcpy(dest, src, mtd->oobsize); -+ break; -+ -+ case ONENAND_CMD_ERASE: -+ memset(ONENAND_CORE(flash) + offset, 0xff, mtd->erasesize); -+ memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff, -+ (mtd->erasesize >> 5)); -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+/** -+ * onenand_command_handle - Handle command -+ * @param this OneNAND device structure -+ * @param cmd The command to be sent -+ * -+ * Emulate OneNAND command. -+ */ -+static void onenand_command_handle(struct onenand_chip *this, int cmd) -+{ -+ unsigned long offset = 0; -+ int block = -1, page = -1, bufferram = -1; -+ int dataram = 0; -+ -+ switch (cmd) { -+ case ONENAND_CMD_UNLOCK: -+ case ONENAND_CMD_LOCK: -+ case ONENAND_CMD_LOCK_TIGHT: -+ case ONENAND_CMD_UNLOCK_ALL: -+ onenand_lock_handle(this, cmd); -+ break; -+ -+ case ONENAND_CMD_BUFFERRAM: -+ /* Do nothing */ -+ return; -+ -+ default: -+ block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1); -+ if (block & (1 << ONENAND_DDP_SHIFT)) { -+ block &= ~(1 << ONENAND_DDP_SHIFT); -+ /* The half of chip block */ -+ block += this->chipsize >> (this->erase_shift + 1); -+ } -+ if (cmd == ONENAND_CMD_ERASE) -+ break; -+ -+ page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8); -+ page = (page >> ONENAND_FPA_SHIFT); -+ bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER); -+ bufferram >>= ONENAND_BSA_SHIFT; -+ bufferram &= ONENAND_BSA_DATARAM1; -+ dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0; -+ break; -+ } -+ -+ if (block != -1) -+ offset += block << this->erase_shift; -+ -+ if (page != -1) -+ offset += page << this->page_shift; -+ -+ onenand_data_handle(this, cmd, dataram, offset); -+ -+ onenand_update_interrupt(this, cmd); -+} -+ -+/** -+ * onenand_writew - [OneNAND Interface] Emulate write operation -+ * @param value value to write -+ * @param addr address to write -+ * -+ * Write OneNAND register with value -+ */ -+static void onenand_writew(unsigned short value, void __iomem * addr) -+{ -+ struct onenand_chip *this = info->mtd.priv; -+ -+ /* BootRAM handling */ -+ if (addr < this->base + ONENAND_DATARAM) { -+ onenand_bootram_handle(this, value); -+ return; -+ } -+ /* Command handling */ -+ if (addr == this->base + ONENAND_REG_COMMAND) -+ onenand_command_handle(this, value); -+ -+ writew(value, addr); -+} -+ -+/** -+ * flash_init - Initialize OneNAND simulator -+ * @param flash OneNAND simulaotr data strucutres -+ * -+ * Initialize OneNAND simulator. -+ */ -+static int __init flash_init(struct onenand_flash *flash) -+{ -+ int density, size; -+ int buffer_size; -+ -+ flash->base = kzalloc(131072, GFP_KERNEL); -+ if (!flash->base) { -+ printk(KERN_ERR "Unable to allocate base address.\n"); -+ return -ENOMEM; -+ } -+ -+ density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT; -+ size = ((16 << 20) << density); -+ -+ ONENAND_CORE(flash) = vmalloc(size + (size >> 5)); -+ if (!ONENAND_CORE(flash)) { -+ printk(KERN_ERR "Unable to allocate nand core address.\n"); -+ kfree(flash->base); -+ return -ENOMEM; -+ } -+ -+ memset(ONENAND_CORE(flash), 0xff, size + (size >> 5)); -+ -+ /* Setup registers */ -+ writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID); -+ writew(device_id, flash->base + ONENAND_REG_DEVICE_ID); -+ writew(version_id, flash->base + ONENAND_REG_VERSION_ID); -+ -+ if (density < 2) -+ buffer_size = 0x0400; /* 1KiB page */ -+ else -+ buffer_size = 0x0800; /* 2KiB page */ -+ writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE); -+ -+ return 0; -+} -+ -+/** -+ * flash_exit - Clean up OneNAND simulator -+ * @param flash OneNAND simulaotr data strucutres -+ * -+ * Clean up OneNAND simulator. -+ */ -+static void flash_exit(struct onenand_flash *flash) -+{ -+ vfree(ONENAND_CORE(flash)); -+ kfree(flash->base); -+ kfree(flash); -+} -+ -+static int __init onenand_sim_init(void) -+{ -+ /* Allocate all 0xff chars pointer */ -+ ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL); -+ if (!ffchars) { -+ printk(KERN_ERR "Unable to allocate ff chars.\n"); -+ return -ENOMEM; -+ } -+ memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE); -+ -+ /* Allocate OneNAND simulator mtd pointer */ -+ info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL); -+ if (!info) { -+ printk(KERN_ERR "Unable to allocate core structures.\n"); -+ kfree(ffchars); -+ return -ENOMEM; -+ } -+ -+ /* Override write_word function */ -+ info->onenand.write_word = onenand_writew; -+ -+ if (flash_init(&info->flash)) { -+ printk(KERN_ERR "Unable to allocat flash.\n"); -+ kfree(ffchars); -+ kfree(info); -+ return -ENOMEM; -+ } -+ -+ info->parts = os_partitions; -+ -+ info->onenand.base = info->flash.base; -+ info->onenand.priv = &info->flash; -+ -+ info->mtd.name = "OneNAND simulator"; -+ info->mtd.priv = &info->onenand; -+ info->mtd.owner = THIS_MODULE; -+ -+ if (onenand_scan(&info->mtd, 1)) { -+ flash_exit(&info->flash); -+ kfree(ffchars); -+ kfree(info); -+ return -ENXIO; -+ } -+ -+ add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions)); -+ -+ return 0; -+} -+ -+static void __exit onenand_sim_exit(void) -+{ -+ struct onenand_chip *this = info->mtd.priv; -+ struct onenand_flash *flash = this->priv; -+ -+ onenand_release(&info->mtd); -+ flash_exit(flash); -+ kfree(ffchars); -+ kfree(info); -+} -+ -+module_init(onenand_sim_init); -+module_exit(onenand_sim_exit); -+ -+MODULE_AUTHOR("Kyungmin Park "); -+MODULE_DESCRIPTION("The OneNAND flash simulator"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c -index 1938d6d..cc01dbd 100644 ---- a/drivers/net/forcedeth.c -+++ b/drivers/net/forcedeth.c -@@ -3556,10 +3556,12 @@ static int nv_request_irq(struct net_device *dev, int intr_test) - } - if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { - if ((ret = pci_enable_msi(np->pci_dev)) == 0) { -+ pci_intx(np->pci_dev, 0); - np->msi_flags |= NV_MSI_ENABLED; - if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { - printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); - pci_disable_msi(np->pci_dev); -+ pci_intx(np->pci_dev, 1); - np->msi_flags &= ~NV_MSI_ENABLED; - goto out_err; - } -@@ -3601,6 +3603,7 @@ static void nv_free_irq(struct net_device *dev) - free_irq(np->pci_dev->irq, dev); - if (np->msi_flags & NV_MSI_ENABLED) { - pci_disable_msi(np->pci_dev); -+ pci_intx(np->pci_dev, 1); - np->msi_flags &= ~NV_MSI_ENABLED; - } - } -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 7dcaa09..eb69d4d 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -1390,6 +1390,17 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); - - /* -+ * According to Tom Sylla, the Geode does not support PCI power management -+ * transition, so we shouldn't need the D3hot delay. -+ */ -+static void __init quirk_geode_pci_pm(struct pci_dev *dev) -+{ -+ pci_pm_d3_delay = 0; -+} -+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, quirk_geode_pci_pm); -+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_geode_pci_pm); -+ -+/* - * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size - * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. - * Re-allocate the region if needed... -diff --git a/drivers/sysprof/Kconfig b/drivers/sysprof/Kconfig -new file mode 100644 -index 0000000..b99c13a ---- /dev/null -+++ b/drivers/sysprof/Kconfig -@@ -0,0 +1,12 @@ -+ -+menu "Sysprof" -+ -+config SYSPROF -+ tristate "Sysprof support" -+ help -+ Say M here to include the sysprof-module. -+ -+ Sysprof is a sampling profiler that uses a kernel module, -+ sysprof-module, to generate stacktraces which are then interpreted by -+ the userspace program "sysprof". -+endmenu -diff --git a/drivers/sysprof/Makefile b/drivers/sysprof/Makefile -new file mode 100644 -index 0000000..cd465e9 ---- /dev/null -+++ b/drivers/sysprof/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_SYSPROF) += sysprof-module.o -diff --git a/drivers/sysprof/config.h b/drivers/sysprof/config.h -new file mode 100644 -index 0000000..bb62689 ---- /dev/null -+++ b/drivers/sysprof/config.h -@@ -0,0 +1,23 @@ -+/* config.h. Generated by configure. */ -+/* config.h.in. Generated from configure.ac by autoheader. */ -+ -+/* Look for global separate debug info in this path */ -+#define DEBUGDIR "/usr/local/lib/debug" -+ -+/* Define to 1 if you have the `iberty' library (-liberty). */ -+/* #undef HAVE_LIBIBERTY */ -+ -+/* Define to the address where bug reports for this package should be sent. */ -+#define PACKAGE_BUGREPORT "" -+ -+/* Define to the full name of this package. */ -+#define PACKAGE_NAME "sysprof" -+ -+/* Define to the full name and version of this package. */ -+#define PACKAGE_STRING "sysprof 1.0.8" -+ -+/* Define to the one symbol short name of this package. */ -+#define PACKAGE_TARNAME "sysprof" -+ -+/* Define to the version of this package. */ -+#define PACKAGE_VERSION "1.0.8" -diff --git a/drivers/sysprof/sysprof-module.c b/drivers/sysprof/sysprof-module.c -new file mode 100644 -index 0000000..36e0b51 ---- /dev/null -+++ b/drivers/sysprof/sysprof-module.c -@@ -0,0 +1,271 @@ -+/* -*- c-basic-offset: 8 -*- */ -+ -+/* Sysprof -- Sampling, systemwide CPU profiler -+ * Copyright 2004, Red Hat, Inc. -+ * Copyright 2004, 2005, Soeren Sandmann -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifdef CONFIG_SMP -+# define __SMP__ -+#endif -+#include -+#include /* Needed for KERN_ALERT */ -+#include /* Needed by all modules */ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "sysprof-module.h" -+ -+#include "config.h" -+ -+#include -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#include -+#endif -+ -+#if !CONFIG_PROFILING -+# error Sysprof needs a kernel with profiling support compiled in. -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+# error Sysprof needs a Linux 2.6.11 kernel or later -+#endif -+#include -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Soeren Sandmann (sandmann@daimi.au.dk)"); -+ -+#define SAMPLES_PER_SECOND (200) -+#define INTERVAL ((HZ <= SAMPLES_PER_SECOND)? 1 : (HZ / SAMPLES_PER_SECOND)) -+#define N_TRACES 256 -+ -+static SysprofStackTrace stack_traces[N_TRACES]; -+static SysprofStackTrace * head = &stack_traces[0]; -+static SysprofStackTrace * tail = &stack_traces[0]; -+DECLARE_WAIT_QUEUE_HEAD (wait_for_trace); -+DECLARE_WAIT_QUEUE_HEAD (wait_for_exit); -+ -+/* Macro the names of the registers that are used on each architecture */ -+#if defined(CONFIG_X86_64) -+# define REG_FRAME_PTR rbp -+# define REG_INS_PTR rip -+# define REG_STACK_PTR rsp -+#elif defined(CONFIG_X86) -+# define REG_FRAME_PTR ebp -+# define REG_INS_PTR eip -+# define REG_STACK_PTR esp -+#else -+# error Sysprof only supports the i386 and x86-64 architectures -+#endif -+ -+typedef struct userspace_reader userspace_reader; -+struct userspace_reader -+{ -+ struct task_struct *task; -+ unsigned long cache_address; -+ unsigned long *cache; -+}; -+ -+typedef struct StackFrame StackFrame; -+struct StackFrame { -+ unsigned long next; -+ unsigned long return_address; -+}; -+ -+struct work_struct work; -+ -+static int -+read_frame (void *frame_pointer, StackFrame *frame) -+{ -+#if 0 -+ /* This is commented out because we seem to be called with -+ * (current_thread_info()->addr_limit.seg)) == 0 -+ * which means access_ok() _always_ fails. -+ * -+ * Not sure why (or if) this isn't the case for oprofile -+ */ -+ if (!access_ok(VERIFY_READ, frame_pointer, sizeof(StackFrame))) -+ return 1; -+#endif -+ -+ if (__copy_from_user_inatomic ( -+ frame, frame_pointer, sizeof (StackFrame))) -+ return 1; -+ -+ return 0; -+} -+ -+DEFINE_PER_CPU(int, n_samples); -+ -+static int -+timer_notify (struct pt_regs *regs) -+{ -+ SysprofStackTrace *trace = head; -+ int i; -+ int is_user; -+ static atomic_t in_timer_notify = ATOMIC_INIT(1); -+ int n; -+ -+ n = ++get_cpu_var(n_samples); -+ put_cpu_var(n_samples); -+ -+ if (n % INTERVAL != 0) -+ return 0; -+ -+ /* 0: locked, 1: unlocked */ -+ -+ if (!atomic_dec_and_test(&in_timer_notify)) -+ goto out; -+ -+ is_user = user_mode(regs); -+ -+ if (!current || current->pid == 0) -+ goto out; -+ -+ if (is_user && current->state != TASK_RUNNING) -+ goto out; -+ -+ if (!is_user) -+ { -+ /* kernel */ -+ -+ trace->pid = current->pid; -+ trace->truncated = 0; -+ trace->n_addresses = 1; -+ -+ /* 0x1 is taken by sysprof to mean "in kernel" */ -+ trace->addresses[0] = (void *)0x1; -+ } -+ else -+ { -+ StackFrame *frame_pointer; -+ StackFrame frame; -+ memset(trace, 0, sizeof (SysprofStackTrace)); -+ -+ trace->pid = current->pid; -+ trace->truncated = 0; -+ -+ i = 0; -+ -+ trace->addresses[i++] = (void *)regs->REG_INS_PTR; -+ -+ frame_pointer = (void *)regs->REG_FRAME_PTR; -+ -+ while (read_frame (frame_pointer, &frame) == 0 && -+ i < SYSPROF_MAX_ADDRESSES && -+ (unsigned long)frame_pointer >= regs->REG_STACK_PTR) -+ { -+ trace->addresses[i++] = (void *)frame.return_address; -+ frame_pointer = (StackFrame *)frame.next; -+ } -+ -+ trace->n_addresses = i; -+ -+ if (i == SYSPROF_MAX_ADDRESSES) -+ trace->truncated = 1; -+ else -+ trace->truncated = 0; -+ } -+ -+ if (head++ == &stack_traces[N_TRACES - 1]) -+ head = &stack_traces[0]; -+ -+ wake_up (&wait_for_trace); -+ -+out: -+ atomic_inc(&in_timer_notify); -+ return 0; -+} -+ -+static int -+procfile_read(char *buffer, -+ char **buffer_location, -+ off_t offset, -+ int buffer_len, -+ int *eof, -+ void *data) -+{ -+ if (head == tail) -+ return -EWOULDBLOCK; -+ -+ *buffer_location = (char *)tail; -+ -+ BUG_ON(tail->pid == 0); -+ -+ if (tail++ == &stack_traces[N_TRACES - 1]) -+ tail = &stack_traces[0]; -+ -+ return sizeof (SysprofStackTrace); -+} -+ -+struct proc_dir_entry *trace_proc_file; -+static unsigned int -+procfile_poll(struct file *filp, poll_table *poll_table) -+{ -+ if (head != tail) -+ return POLLIN | POLLRDNORM; -+ -+ poll_wait(filp, &wait_for_trace, poll_table); -+ -+ if (head != tail) -+ return POLLIN | POLLRDNORM; -+ -+ return 0; -+} -+ -+int -+init_module(void) -+{ -+ static struct file_operations fops; -+ -+ trace_proc_file = -+ create_proc_entry ("sysprof-trace", S_IFREG | S_IRUGO, &proc_root); -+ -+ if (!trace_proc_file) -+ return 1; -+ -+ fops = *trace_proc_file->proc_fops; -+ fops.poll = procfile_poll; -+ -+ trace_proc_file->read_proc = procfile_read; -+ trace_proc_file->proc_fops = &fops; -+ trace_proc_file->size = sizeof (SysprofStackTrace); -+ -+ register_timer_hook (timer_notify); -+ -+ printk(KERN_ALERT "sysprof: loaded (%s)\n", PACKAGE_VERSION); -+ -+ return 0; -+} -+ -+void -+cleanup_module(void) -+{ -+ unregister_timer_hook (timer_notify); -+ -+ remove_proc_entry("sysprof-trace", &proc_root); -+ -+ printk(KERN_ALERT "sysprof: unloaded\n"); -+} -+ -diff --git a/drivers/sysprof/sysprof-module.h b/drivers/sysprof/sysprof-module.h -new file mode 100644 -index 0000000..66a11ae ---- /dev/null -+++ b/drivers/sysprof/sysprof-module.h -@@ -0,0 +1,37 @@ -+/* Sysprof -- Sampling, systemwide CPU profiler -+ * Copyright 2004, Red Hat, Inc. -+ * Copyright 2004, 2005, Soeren Sandmann -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef SYSPROF_MODULE_H -+#define SYSPROF_MODULE_H -+ -+typedef struct SysprofStackTrace SysprofStackTrace; -+ -+#define SYSPROF_MAX_ADDRESSES 512 -+ -+struct SysprofStackTrace -+{ -+ int pid; /* -1 if in kernel */ -+ int truncated; -+ int n_addresses; /* note: this can be 1 if the process was compiled -+ * with -fomit-frame-pointer or is otherwise weird -+ */ -+ void *addresses[SYSPROF_MAX_ADDRESSES]; -+}; -+ -+#endif -diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig -index 5216c11..3e3df7e 100644 ---- a/drivers/video/Kconfig -+++ b/drivers/video/Kconfig -@@ -594,7 +594,7 @@ config FB_TGA - - config FB_VESA - bool "VESA VGA graphics support" -- depends on (FB = y) && X86 -+ depends on (FB = y) && X86 && !VGA_NOPROBE - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -@@ -1028,7 +1028,7 @@ config FB_CARILLO_RANCH - - config FB_INTEL - tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)" -- depends on FB && EXPERIMENTAL && PCI && X86 -+ depends on FB && EXPERIMENTAL && PCI && X86 && !VGA_NOPROBE - select AGP - select AGP_INTEL - select FB_MODE_HELPERS -@@ -1383,7 +1383,7 @@ config FB_SAVAGE_ACCEL - - config FB_SIS - tristate "SiS/XGI display support" -- depends on FB && PCI -+ depends on FB && PCI && !VGA_NOPROBE - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -@@ -1822,6 +1822,15 @@ config FB_PS3_DEFAULT_SIZE_M - The default value can be overridden on the kernel command line - using the "ps3fb" option (e.g. "ps3fb=9M"); - -+config FB_OLPC_DCON -+ tristate "One Laptop Per Child Display CONtroller support" -+ depends on OLPC -+ select I2C -+ ---help--- -+ Add support for the OLPC DCON controller. This controller is only -+ available on OLPC platforms. Unless you have one of these -+ platforms, you will want to say 'N'. -+ - config FB_XILINX - tristate "Xilinx frame buffer support" - depends on FB && XILINX_VIRTEX -diff --git a/drivers/video/Makefile b/drivers/video/Makefile -index 06eec7b..fc535fb 100644 ---- a/drivers/video/Makefile -+++ b/drivers/video/Makefile -@@ -111,6 +111,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ - obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o - obj-$(CONFIG_FB_PS3) += ps3fb.o - obj-$(CONFIG_FB_SM501) += sm501fb.o -+obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon.o - obj-$(CONFIG_FB_XILINX) += xilinxfb.o - obj-$(CONFIG_FB_OMAP) += omap/ - -diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c -index 0740272..4ac6a95 100644 ---- a/drivers/video/fbmem.c -+++ b/drivers/video/fbmem.c -@@ -820,6 +820,53 @@ static void try_to_load(int fb) - #endif /* CONFIG_KMOD */ - - int -+fb_powerup(struct fb_info *info) -+{ -+ int ret = 0; -+ -+ if (!info || info->state == FBINFO_STATE_RUNNING) -+ return 0; -+ -+ if (info->fbops->fb_powerup) -+ ret = info->fbops->fb_powerup(info); -+ -+ if (!ret) { -+ acquire_console_sem(); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ } -+ -+ return ret; -+} -+ -+int -+fb_powerdown(struct fb_info *info) -+{ -+ int ret = 0; -+ -+ if (!info || info->state == FBINFO_STATE_SUSPENDED) -+ return 0; -+ -+ /* Tell everybody that the fbdev is going down */ -+ acquire_console_sem(); -+ fb_set_suspend(info, 1); -+ release_console_sem(); -+ -+ if (info->fbops->fb_powerdown) -+ ret = info->fbops->fb_powerdown(info); -+ -+ /* If the power down failed, then un-notify */ -+ -+ if (ret) { -+ acquire_console_sem(); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ } -+ -+ return ret; -+} -+ -+int - fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) - { - struct fb_fix_screeninfo *fix = &info->fix; -diff --git a/drivers/video/geode/Makefile b/drivers/video/geode/Makefile -index 957304b..5c98da1 100644 ---- a/drivers/video/geode/Makefile -+++ b/drivers/video/geode/Makefile -@@ -5,5 +5,5 @@ obj-$(CONFIG_FB_GEODE_GX) += gxfb.o - obj-$(CONFIG_FB_GEODE_LX) += lxfb.o - - gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o --gxfb-objs := gxfb_core.o display_gx.o video_gx.o -+gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o - lxfb-objs := lxfb_core.o lxfb_ops.o -diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c -index 0f16e4b..a432b99 100644 ---- a/drivers/video/geode/display_gx.c -+++ b/drivers/video/geode/display_gx.c -@@ -11,26 +11,44 @@ - * Free Software Foundation; either version 2 of the License, or * (at your - * option) any later version. - */ -+ -+#include - #include - #include - #include - #include - #include - #include -+#include - - #include "geodefb.h" - #include "display_gx.h" - --#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE --unsigned int gx_frame_buffer_size(void) -+static inline void rmwl(u32 val, u32 *reg) - { -- return CONFIG_FB_GEODE_GX_FBSIZE; -+ u32 in = readl(reg); -+ if (in != val) -+ writel(val, reg); - } --#else -+ - unsigned int gx_frame_buffer_size(void) - { - unsigned int val; - -+#ifdef CONFIG_OLPC -+ if (machine_is_olpc() && !olpc_has_vsa()) { -+ u32 hi,lo; -+ rdmsr(GLIU0_P2D_RO0, lo, hi); -+ -+ /* Top page number */ -+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); -+ -+ val -= (lo & 0x000fffff); /* Subtract bottom page number */ -+ val += 1; /* Adjust page count */ -+ return (val << 12); -+ } -+#endif -+ - /* FB size is reported by a virtual register */ - /* Virtual register class = 0x02 */ - /* VG_MEM_SIZE(512Kb units) = 0x00 */ -@@ -41,7 +59,6 @@ unsigned int gx_frame_buffer_size(void) - val = (unsigned int)(inw(0xAC1E)) & 0xFFl; - return (val << 19); - } --#endif - - int gx_line_delta(int xres, int bpp) - { -@@ -63,23 +80,23 @@ static void gx_set_mode(struct fb_info *info) - gcfg = readl(par->dc_regs + DC_GENERAL_CFG); - dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); - -- /* Disable the timing generator. */ -- dcfg &= ~(DC_DCFG_TGEN); -- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); -+ /* Programming the clock is costly and ugly, so avoid if if we can */ - -- /* Wait for pending memory requests before disabling the FIFO load. */ -- udelay(100); -+ if (par->curdclk != info->var.pixclock) { -+ /* Disable the timing generator. */ -+ dcfg &= ~(DC_DCFG_TGEN); -+ writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); - -- /* Disable FIFO load and compression. */ -- gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); -- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -+ /* Wait for pending memory requests before disabling the FIFO load. */ -+ udelay(100); - -- /* Setup DCLK and its divisor. */ -- par->vid_ops->set_dclk(info); -+ /* Disable FIFO load and compression. */ -+ gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); -+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG); - -- /* -- * Setup new mode. -- */ -+ /* Setup DCLK and its divisor. */ -+ par->vid_ops->set_dclk(info); -+ } - - /* Clear all unused feature bits. */ - gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; -@@ -90,12 +107,13 @@ static void gx_set_mode(struct fb_info *info) - gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; - - /* Framebuffer start offset. */ -- writel(0, par->dc_regs + DC_FB_ST_OFFSET); -+ rmwl(0, par->dc_regs + DC_FB_ST_OFFSET); - - /* Line delta and line buffer length. */ -- writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); -- writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, -- par->dc_regs + DC_LINE_SIZE); -+ rmwl(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); -+ -+ rmwl(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, -+ par->dc_regs + DC_LINE_SIZE); - - - /* Enable graphics and video data and unmask address lines. */ -@@ -134,17 +152,16 @@ static void gx_set_mode(struct fb_info *info) - vblankend = vsyncend + info->var.upper_margin; - vtotal = vblankend; - -- writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); -- writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); -- writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); -- -- writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); -- writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); -- writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); -+ rmwl((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); -+ rmwl((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); -+ rmwl((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); -+ rmwl((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); -+ rmwl((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); -+ rmwl((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); - - /* Write final register values. */ -- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); -- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -+ rmwl(dcfg, par->dc_regs + DC_DISPLAY_CFG); -+ rmwl(gcfg, par->dc_regs + DC_GENERAL_CFG); - - par->vid_ops->configure_display(info); - -diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h -index 0af33f3..d20b877 100644 ---- a/drivers/video/geode/display_gx.h -+++ b/drivers/video/geode/display_gx.h -@@ -20,6 +20,9 @@ extern struct geode_dc_ops gx_dc_ops; - #define GLD_MSR_CONFIG 0xC0002001 - #define GLD_MSR_CONFIG_DM_FP 0x40 - -+/* Used for memory dection on the OLPC */ -+#define GLIU0_P2D_RO0 0x10000029 -+ - /* Display controller registers */ - - #define DC_UNLOCK 0x00 -diff --git a/drivers/video/geode/geode_regs.h b/drivers/video/geode/geode_regs.h -new file mode 100644 -index 0000000..9e75505 ---- /dev/null -+++ b/drivers/video/geode/geode_regs.h -@@ -0,0 +1,242 @@ -+/* This header file defines the registers and suspend/resume -+ structures for the Geode GX and LX. The lxfb driver defines -+ _GEODELX_ before including this file, which will unlock the -+ extra registers that are only valid for LX. -+*/ -+ -+#ifndef _GEODE_REGS_H_ -+#define _GEODE_REGS_H_ -+ -+/* MSRs */ -+ -+#define GX_VP_MSR_PAD_SELECT 0xC0002011 -+#define LX_VP_MSR_PAD_SELECT 0x48000011 -+ -+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015 -+ -+#define GLCP_DOTPLL_RESET (1 << 0) -+#define GLCP_DOTPLL_BYPASS (1 << 15) -+#define GLCP_DOTPLL_HALFPIX (1 << 24) -+#define GLCP_DOTPLL_LOCK (1 << 25) -+ -+/* Registers */ -+#define VP_FP_START 0x400 -+ -+ -+#ifdef _GEODELX_ -+ -+#define GP_REG_SIZE 0x7C -+#define DC_REG_SIZE 0xF0 -+#define VP_REG_SIZE 0x158 -+#define FP_REG_SIZE 0x70 -+ -+#else -+ -+#define GP_REG_SIZE 0x50 -+#define DC_REG_SIZE 0x90 -+#define VP_REG_SIZE 0x138 -+#define FP_REG_SIZE 0x70 -+ -+#endif -+ -+#define DC_PAL_SIZE 0x105 -+ -+struct geoderegs { -+ -+ struct { -+ u64 padsel; -+ u64 dotpll; -+ -+#ifdef _GEODELX_ -+ u64 dfglcfg; -+ u64 dcspare; -+#else -+ u64 rstpll; -+#endif -+ } msr; -+ -+ union { -+ unsigned char b[GP_REG_SIZE]; -+ struct { -+ u32 dst_offset; /* 0x00 */ -+ u32 src_offset; /* 0x04 */ -+ u32 stride; /* 0x08 */ -+ u32 wid_height; /* 0x0C */ -+ u32 src_color_fg; /* 0x10 */ -+ u32 src_color_bg; /* 0x14 */ -+ u32 pat_color_0; /* 0x18 */ -+ u32 pat_color_1; /* 0x1C */ -+ u32 pat_color_2; /* 0x20 */ -+ u32 pat_color_3; /* 0x24 */ -+ u32 pat_color_4; /* 0x28 */ -+ u32 pat_color_5; /* 0x2C */ -+ u32 pat_data_0; /* 0x30 */ -+ u32 pat_data_1; /* 0x34 */ -+ u32 raster_mode; /* 0x38 */ -+ u32 vector_mode; /* 0x3C */ -+ u32 blt_mode; /* 0x40 */ -+ u32 blit_status; /* 0x4C */ -+ u32 hst_src; /* 0x48 */ -+ u32 base_offset; /* 0x4C */ -+ -+#ifdef _GEODELX_ -+ u32 cmd_top; /* 0x50 */ -+ u32 cmd_bot; /* 0x54 */ -+ u32 cmd_read; /* 0x58 */ -+ u32 cmd_write; /* 0x5C */ -+ u32 ch3_offset; /* 0x60 */ -+ u32 ch3_mode_str; /* 0x64 */ -+ u32 ch3_width; /* 0x68 */ -+ u32 ch3_hsrc; /* 0x6C */ -+ u32 lut_index; /* 0x70 */ -+ u32 lut_data; /* 0x74 */ -+ u32 int_cntrl; /* 0x78 */ -+#endif -+ } r; -+ } gp; -+ -+ union { -+ unsigned char b[DC_REG_SIZE]; -+ -+ struct { -+ u32 unlock; /* 0x00 */ -+ u32 gcfg; /* 0x04 */ -+ u32 dcfg; /* 0x08 */ -+ u32 arb; /* 0x0C */ -+ u32 fb_st_offset; /* 0x10 */ -+ u32 cb_st_offset; /* 0x14 */ -+ u32 curs_st_offset; /* 0x18 */ -+ u32 icon_st_offset; /* 0x1C */ -+ u32 vid_y_st_offset; /* 0x20 */ -+ u32 vid_u_st_offset; /* 0x24 */ -+ u32 vid_v_st_offset; /* 0x28 */ -+ u32 dctop; /* 0x2c */ -+ u32 line_size; /* 0x30 */ -+ u32 gfx_pitch; /* 0x34 */ -+ u32 vid_yuv_pitch; /* 0x38 */ -+ u32 rsvd2; /* 0x3C */ -+ u32 h_active_timing; /* 0x40 */ -+ u32 h_blank_timing; /* 0x44 */ -+ u32 h_sync_timing; /* 0x48 */ -+ u32 rsvd3; /* 0x4C */ -+ u32 v_active_timing; /* 0x50 */ -+ u32 v_blank_timing; /* 0x54 */ -+ u32 v_sync_timing; /* 0x58 */ -+ u32 fbactive; /* 0x5C */ -+ u32 dc_cursor_x; /* 0x60 */ -+ u32 dc_cursor_y; /* 0x64 */ -+ u32 dc_icon_x; /* 0x68 */ -+ u32 dc_line_cnt; /* 0x6C */ -+ u32 rsvd5; /* 0x70 - palette address */ -+ u32 rsvd6; /* 0x74 - palette data */ -+ u32 dfifo_diag; /* 0x78 */ -+ u32 cfifo_diag; /* 0x7C */ -+ u32 dc_vid_ds_delta; /* 0x80 */ -+ u32 gliu0_mem_offset; /* 0x84 */ -+ u32 dv_ctl; /* 0x88 - added by LX */ -+ u32 dv_acc; /* 0x8C */ -+ -+#ifdef _GEODELX_ -+ u32 gfx_scale; -+ u32 irq_filt_ctl; -+ u32 filt_coeff1; -+ u32 filt_coeff2; -+ u32 vbi_event_ctl; -+ u32 vbi_odd_ctl; -+ u32 vbi_hor; -+ u32 vbi_ln_odd; -+ u32 vbi_ln_event; -+ u32 vbi_pitch; -+ u32 clr_key; -+ u32 clr_key_mask; -+ u32 clr_key_x; -+ u32 clr_key_y; -+ u32 irq; -+ u32 rsvd8; -+ u32 genlk_ctrl; -+ u32 vid_even_y_st_offset; /* 0xD8 */ -+ u32 vid_even_u_st_offset; /* 0xDC */ -+ u32 vid_even_v_st_offset; /* 0xE0 */ -+ u32 v_active_even_timing; /* 0xE4 */ -+ u32 v_blank_even_timing; /* 0xE8 */ -+ u32 v_sync_even_timing; /* 0xEC */ -+#endif -+ } r; -+ } dc; -+ -+ union { -+ unsigned char b[VP_REG_SIZE]; -+ -+ struct { -+ u64 vcfg; /* 0x00 */ -+ u64 dcfg; /* 0x08 */ -+ u64 vx; /* 0x10 */ -+ u64 vy; /* 0x18 */ -+ u64 vs; /* 0x20 */ -+ u64 vck; /* 0x28 */ -+ u64 vcm; /* 0x30 */ -+ u64 rsvd1; /* 0x38 - Gamma address*/ -+ u64 rsvd2; /* 0x40 - Gamma data*/ -+ u64 rsvd3; /* 0x48 */ -+ u64 misc; /* 0x50 */ -+ u64 ccs; /* 0x58 */ -+ u64 rsvd4[3]; /* 0x60-0x70 */ -+ u64 vdc; /* 0x78 */ -+ u64 vco; /* 0x80 */ -+ u64 crc; /* 0x88 */ -+ u64 crc32; /* 0x90 */ -+ u64 vde; /* 0x98 */ -+ u64 cck; /* 0xA0 */ -+ u64 ccm; /* 0xA8 */ -+ u64 cc1; /* 0xB0 */ -+ u64 cc2; /* 0xB8 */ -+ u64 a1x; /* 0xC0 */ -+ u64 a1y; /* 0xC8 */ -+ u64 a1c; /* 0xD0 */ -+ u64 a1t; /* 0xD8 */ -+ u64 a2x; /* 0xE0 */ -+ u64 a2y; /* 0xE8 */ -+ u64 a2c; /* 0xF0 */ -+ u64 a2t; /* 0xF8 */ -+ u64 a3x; /* 0x100 */ -+ u64 a3y; /* 0x108 */ -+ u64 a3c; /* 0x110 */ -+ u64 a3t; /* 0x118 */ -+ u64 vrr; /* 0x120 */ -+ u64 awt; /* 0x128 */ -+ u64 vtm; /* 0x130 */ -+#ifdef _GEODELX_ -+ u64 vye; /* 0x138 */ -+ u64 a1ye; /* 0x140 */ -+ u32 a2ye; /* 0x148 */ -+ u32 a3ye; /* 0x150 */ -+#endif -+ } r; -+ } vp; -+ -+ union { -+ unsigned char b[FP_REG_SIZE]; -+ -+ struct { -+ u64 pt1; /* 0x400 */ -+ u64 pt2; /* 0x408 */ -+ u64 pm; /* 0x410 */ -+ u64 dfc; /* 0x418 */ -+ u64 blfsr; /* 0x420 */ -+ u64 rlfsr; /* 0x428 */ -+ u64 fmi; /* 0x430 */ -+ u64 fmd; /* 0x438 */ -+ u64 rsvd; /* 0x440 */ -+ u64 dca; /* 0x448 */ -+ u64 dmd; /* 0x450 */ -+ u64 crc; /* 0x458 */ -+ u64 fbb; /* 0x460 */ -+ u64 crc32; /* 0x468 */ -+ } r; -+ } fp; -+ -+ u32 pal[DC_PAL_SIZE]; -+ u32 gamma[256]; -+}; -+ -+#endif -diff --git a/drivers/video/geode/geodefb.h b/drivers/video/geode/geodefb.h -index ae04820..0214d11 100644 ---- a/drivers/video/geode/geodefb.h -+++ b/drivers/video/geode/geodefb.h -@@ -12,6 +12,10 @@ - #ifndef __GEODEFB_H__ - #define __GEODEFB_H__ - -+#define FB_POWER_STATE_OFF 0 -+#define FB_POWER_STATE_SUSPEND 1 -+#define FB_POWER_STATE_ON 2 -+ - struct geodefb_info; - - struct geode_dc_ops { -@@ -21,18 +25,24 @@ struct geode_dc_ops { - - struct geode_vid_ops { - void (*set_dclk)(struct fb_info *); -+ unsigned int (*get_dclk)(struct fb_info *); - void (*configure_display)(struct fb_info *); - int (*blank_display)(struct fb_info *, int blank_mode); - }; - - struct geodefb_par { - int enable_crt; -+ int fbactive; /* True if the current console is in KD_GRAPHICS mode */ - int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */ - int panel_y; -+ unsigned int curdclk; /* Used by GX to avoid unnessesary clock switching */ - void __iomem *dc_regs; - void __iomem *vid_regs; -+ void __iomem *gp_regs; - struct geode_dc_ops *dc_ops; - struct geode_vid_ops *vid_ops; -+ -+ int state; - }; - - #endif /* !__GEODEFB_H__ */ -diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c -index cf841ef..3eabc53 100644 ---- a/drivers/video/geode/gxfb_core.c -+++ b/drivers/video/geode/gxfb_core.c -@@ -30,12 +30,31 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include "geodefb.h" - #include "display_gx.h" - #include "video_gx.h" - -+#define FBIOSGAMMA _IOW('F', 0x20, void *) -+#define FBIOGGAMMA _IOW('F', 0x21, void *) -+ -+#ifdef DEBUG -+ -+#define FBIODUMPGP _IOW('F', 0x22, void *) -+#define FBIODUMPDC _IOW('F', 0x23, void *) -+#define FBIODUMPVP _IOW('F', 0x24, void *) -+#define FBIODUMPFP _IOW('F', 0x25, void *) -+ -+#endif -+ - static char *mode_option; -+static int noclear; -+struct fb_info *gxfb_info; - - /* Modes relevant to the GX (taken from modedb.c) */ - static const struct fb_videomode gx_modedb[] __initdata = { -@@ -103,8 +122,20 @@ static const struct fb_videomode gx_modedb[] __initdata = { - { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1200x900-75 - CRT timings for the OLPC mode */ -+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } - }; - -+#ifdef CONFIG_OLPC -+static const struct fb_videomode gx_dcon_modedb[] __initdata = { -+ /* The only mode the DCON has is 1200x900 */ -+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } -+}; -+#endif -+ -+ - static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) - { - if (var->xres > 1600 || var->yres > 1200) -@@ -137,7 +168,7 @@ static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) - return 0; - } - --static int gxfb_set_par(struct fb_info *info) -+int gxfb_set_par(struct fb_info *info) - { - struct geodefb_par *par = info->par; - -@@ -204,16 +235,26 @@ static int gxfb_blank(int blank_mode, struct fb_info *info) - return par->vid_ops->blank_display(info, blank_mode); - } - -+static int fbsize; -+ - static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev) - { - struct geodefb_par *par = info->par; -- int fb_len; - int ret; - - ret = pci_enable_device(dev); - if (ret < 0) - return ret; - -+ ret = pci_request_region(dev, 1, "gxfb (graphics processor)"); -+ if (ret < 0) -+ return ret; -+ -+ par->gp_regs = ioremap(pci_resource_start(dev, 1), -+ pci_resource_len(dev, 1)); -+ if (!par->gp_regs) -+ return -ENOMEM; -+ - ret = pci_request_region(dev, 3, "gxfb (video processor)"); - if (ret < 0) - return ret; -@@ -232,36 +273,118 @@ static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *de - ret = pci_request_region(dev, 0, "gxfb (framebuffer)"); - if (ret < 0) - return ret; -- if ((fb_len = gx_frame_buffer_size()) < 0) -- return -ENOMEM; -+ -+ /* If the fbsize wasn't specified then try to probe it */ -+ -+ if (!fbsize) { -+ fbsize = gx_frame_buffer_size(); -+ if (fbsize == 0) -+ return -ENOMEM; -+ } -+ - info->fix.smem_start = pci_resource_start(dev, 0); -- info->fix.smem_len = fb_len; -+ info->fix.smem_len = fbsize; - info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); - if (!info->screen_base) - return -ENOMEM; - -- /* Set the 16MB aligned base address of the graphics memory region -+ /* Set the 16MiB aligned base address of the graphics memory region - * in the display controller */ - - writel(info->fix.smem_start & 0xFF000000, - par->dc_regs + DC_GLIU0_MEM_OFFSET); - -- dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n", -+ dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n", - info->fix.smem_len / 1024, info->fix.smem_start); - - return 0; - } - -+static int gxfb_ioctl( struct fb_info *info, unsigned int cmd, -+ unsigned long arg) -+{ -+ unsigned int gamma[GXFB_GAMMA_DWORDS]; -+ int ret = -EINVAL; -+ struct geodefb_par *par = info->par; -+ int i; -+ -+ switch(cmd) { -+ case FBIOSGAMMA: -+ /* Read the gamma information from the user - 256 dwords */ -+ -+ if (copy_from_user(gamma, (void * __user) arg, GXFB_GAMMA_SIZE)) -+ return -EFAULT; -+ -+ writel(0, par->vid_regs + GX_GAR); -+ -+ /* Sequential writes to the data register will increment the -+ address automatically */ -+ -+ for(i = 0; i < GXFB_GAMMA_DWORDS; i++) -+ writel(gamma[i] & 0xFFFFFF, par->vid_regs + GX_GDR); -+ -+ writel(readl(par->vid_regs + GX_MISC) & ~GX_MISC_GAM_EN, -+ par->vid_regs + GX_MISC); -+ -+ ret = 0; -+ break; -+ -+ case FBIOGGAMMA: -+ if (readl(par->vid_regs + GX_MISC) & GX_MISC_GAM_EN) -+ return -EINVAL; -+ -+ memset(gamma, 0, GXFB_GAMMA_SIZE); -+ writel(0, par->vid_regs + GX_GAR); -+ -+ for(i = 0; i < GXFB_GAMMA_DWORDS;i++) -+ gamma[i] = readl(par->vid_regs + GX_GDR); -+ -+ if (copy_to_user((void * __user) arg, gamma, GXFB_GAMMA_SIZE)) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ -+ break; -+ -+#ifdef DEBUG -+ case FBIODUMPGP: -+ ret = 0; -+ dump_regs(info, 0); -+ break; -+ -+ case FBIODUMPDC: -+ ret = 0; -+ dump_regs(info, 1); -+ break; -+ -+ case FBIODUMPVP: -+ ret = 0; -+ dump_regs(info, 2); -+ break; -+ -+ case FBIODUMPFP: -+ ret = 0; -+ dump_regs(info, 3); -+ break; -+#endif -+ } -+ -+ return ret; -+} -+ - static struct fb_ops gxfb_ops = { - .owner = THIS_MODULE, - .fb_check_var = gxfb_check_var, - .fb_set_par = gxfb_set_par, - .fb_setcolreg = gxfb_setcolreg, - .fb_blank = gxfb_blank, -+ .fb_ioctl = gxfb_ioctl, - /* No HW acceleration for now. */ - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -+ .fb_powerdown = gxfb_powerdown, -+ .fb_powerup = gxfb_powerup, - }; - - static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) -@@ -303,23 +426,86 @@ static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) - return info; - } - --static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) -+static int gxfb_console_notify(struct notifier_block *self, -+ unsigned long action, void *data) -+{ -+ if (gxfb_info != NULL) { -+ struct geodefb_par *par = gxfb_info->par; -+ par->fbactive = (action == CONSOLE_EVENT_SWITCH_TEXT) ? 0 : 1; -+ } -+ -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block gxfb_console_notifier = { -+ .notifier_call = gxfb_console_notify -+}; -+ -+#ifdef CONFIG_PM -+ -+static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ struct geodefb_par *par = info->par; -+ -+ if (pdev->dev.power.power_state.event == state.event) -+ return 0; -+ -+ if (state.event == PM_EVENT_SUSPEND) { -+ -+ acquire_console_sem(); -+ gxfb_powerdown(info); -+ -+ par->state = FB_POWER_STATE_OFF; -+ fb_set_suspend(info, 1); -+ -+ release_console_sem(); -+ } -+ -+ pdev->dev.power.power_state = state; -+ return 0; -+} -+ -+static int gxfb_resume(struct pci_dev *pdev) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ acquire_console_sem(); -+ -+ /* Turn the engine completely on */ -+ -+ if (gxfb_powerup(info)) -+ printk(KERN_ERR "gxfb: Powerup failed\n"); -+ -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ -+ pdev->dev.power.power_state = PMSG_ON; -+ return 0; -+} -+#endif -+ -+static int __init gxfb_probe(struct pci_dev *pdev, -+ const struct pci_device_id *id) - { - struct geodefb_par *par; -- struct fb_info *info; - int ret; - unsigned long val; - -- info = gxfb_init_fbinfo(&pdev->dev); -- if (!info) -+ struct fb_videomode *modedb_ptr; -+ int modedb_size; -+ -+ gxfb_info = gxfb_init_fbinfo(&pdev->dev); -+ if (gxfb_info == NULL) - return -ENOMEM; -- par = info->par; -+ -+ par = gxfb_info->par; - - /* GX display controller and GX video device. */ - par->dc_ops = &gx_dc_ops; - par->vid_ops = &gx_vid_ops; - -- if ((ret = gxfb_map_video_memory(info, pdev)) < 0) { -+ if ((ret = gxfb_map_video_memory(gxfb_info, pdev)) < 0) { - dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n"); - goto err; - } -@@ -333,32 +519,60 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i - else - par->enable_crt = 1; - -- ret = fb_find_mode(&info->var, info, mode_option, -- gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16); -+ /* Get the current dotclock */ -+ -+ par->curdclk = (par->vid_ops->get_dclk) ? par->vid_ops->get_dclk(gxfb_info) : 0; -+ -+ /* We need to determine a display mode right now, so we will -+ * check to see if the DCON was previously detected by the BIOS -+ * and use that to make our mode database decision. -+ */ -+ -+ modedb_ptr = (struct fb_videomode *) gx_modedb; -+ modedb_size = ARRAY_SIZE(gx_modedb); -+ -+#ifdef CONFIG_OLPC -+ if (olpc_has_dcon()) { -+ modedb_ptr = (struct fb_videomode *) gx_dcon_modedb; -+ modedb_size = ARRAY_SIZE(gx_dcon_modedb); -+ } -+#endif -+ -+ ret = fb_find_mode(&gxfb_info->var, gxfb_info, mode_option, -+ modedb_ptr, modedb_size, NULL, 16); -+ - if (ret == 0 || ret == 4) { - dev_err(&pdev->dev, "could not find valid video mode\n"); - ret = -EINVAL; - goto err; - } - -+ /* Clear the screen of garbage, unless noclear was specified, -+ * in which case we assume the user knows what he is doing */ -+ -+ if (!noclear) -+ memset_io(gxfb_info->screen_base, 0, gxfb_info->fix.smem_len); -+ -+ gxfb_check_var(&gxfb_info->var, gxfb_info); -+ gxfb_set_par(gxfb_info); -+ -+ /* We are powered up */ -+ par->state = FB_POWER_STATE_ON; - -- /* Clear the frame buffer of garbage. */ -- memset_io(info->screen_base, 0, info->fix.smem_len); - -- gxfb_check_var(&info->var, info); -- gxfb_set_par(info); -+ console_event_register(&gxfb_console_notifier); - -- if (register_framebuffer(info) < 0) { -+ if (register_framebuffer(gxfb_info) < 0) { - ret = -EINVAL; - goto err; - } -- pci_set_drvdata(pdev, info); -- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); -+ pci_set_drvdata(pdev, gxfb_info); -+ printk(KERN_INFO "fb%d: %s frame buffer device\n", gxfb_info->node, gxfb_info->fix.id); - return 0; - - err: -- if (info->screen_base) { -- iounmap(info->screen_base); -+ if (gxfb_info->screen_base) { -+ iounmap(gxfb_info->screen_base); - pci_release_region(pdev, 0); - } - if (par->vid_regs) { -@@ -370,8 +584,9 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i - pci_release_region(pdev, 2); - } - -- if (info) -- framebuffer_release(info); -+ if (gxfb_info) -+ framebuffer_release(gxfb_info); -+ - return ret; - } - -@@ -397,9 +612,7 @@ static void gxfb_remove(struct pci_dev *pdev) - } - - static struct pci_device_id gxfb_id_table[] = { -- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO, -- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, -- 0xff0000, 0 }, -+ { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) }, - { 0, } - }; - -@@ -410,22 +623,30 @@ static struct pci_driver gxfb_driver = { - .id_table = gxfb_id_table, - .probe = gxfb_probe, - .remove = gxfb_remove, -+#ifdef CONFIG_PM -+ .suspend = gxfb_suspend, -+ .resume = gxfb_resume -+#endif - }; - - #ifndef MODULE --static int __init gxfb_setup(char *options) --{ -+static int __init gxfb_setup(char *options) { - - char *opt; - - if (!options || !*options) - return 0; - -- while ((opt = strsep(&options, ",")) != NULL) { -+ while((opt = strsep(&options, ",")) != NULL) { - if (!*opt) - continue; - -- mode_option = opt; -+ if (!strncmp(opt, "fbsize:", 7)) -+ fbsize = simple_strtoul(opt+7, NULL, 0); -+ else if (!strcmp(opt, "noclear")) -+ noclear = 1; -+ else -+ mode_option = opt; - } - - return 0; -@@ -444,7 +665,6 @@ static int __init gxfb_init(void) - #endif - return pci_register_driver(&gxfb_driver); - } -- - static void __exit gxfb_cleanup(void) - { - pci_unregister_driver(&gxfb_driver); -@@ -456,5 +676,8 @@ module_exit(gxfb_cleanup); - module_param(mode_option, charp, 0); - MODULE_PARM_DESC(mode_option, "video mode (x[-][@])"); - -+module_param(fbsize, int, 0); -+MODULE_PARM_DESC(fbsize, "video memory size"); -+ - MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX"); - MODULE_LICENSE("GPL"); -diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h -index 6c227f9..5be8a4d 100644 ---- a/drivers/video/geode/lxfb.h -+++ b/drivers/video/geode/lxfb.h -@@ -25,10 +25,23 @@ void lx_set_mode(struct fb_info *); - void lx_get_gamma(struct fb_info *, unsigned int *, int); - void lx_set_gamma(struct fb_info *, unsigned int *, int); - unsigned int lx_framebuffer_size(void); -+int lx_shutdown(struct fb_info *); -+int lx_powerup(struct fb_info *); - int lx_blank_display(struct fb_info *, int); - void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, - unsigned int, unsigned int); - -+ -+ -+/* ioctl() defines */ -+ -+#define FBIOSGAMMA _IOW('F', 0x20, void *) -+#define FBIOGGAMMA _IOW('F', 0x21, void *) -+ -+/* General definitions */ -+#define LXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ -+#define LXFB_GAMMA_SIZE (LXFB_GAMMA_DWORDS * sizeof(unsigned int)) -+ - /* MSRS */ - - #define MSR_LX_GLD_CONFIG 0x48002001 -diff --git a/drivers/video/geode/lxfb_core.c b/drivers/video/geode/lxfb_core.c -index 5e30b40..c9060ed 100644 ---- a/drivers/video/geode/lxfb_core.c -+++ b/drivers/video/geode/lxfb_core.c -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include "lxfb.h" - -@@ -35,186 +36,84 @@ static int fbsize; - */ - - const struct fb_videomode geode_modedb[] __initdata = { -- /* 640x480-60 */ -- { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2, -+ /* 640x480-60 VESA */ -+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 640x480-75 VESA */ -+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 640x480-85 VESA */ -+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-60 VESA */ -+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x400-70 */ -- { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2, -- FB_SYNC_HOR_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-70 */ -- { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-72 */ -- { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-75 VESA */ -+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-75 */ -- { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 800x600-85 VESA */ -+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-85 */ -- { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-60 VESA */ -+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, -+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-75 VESA */ -+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-90 */ -- { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-100 */ -- { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 640x480-60 */ -- { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1024x768-85 VESA */ -+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-56 */ -- { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-60 */ -- { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-70 */ -- { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-72 */ -- { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-75 */ -- { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-85 */ -- { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-90 */ -- { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-100 */ -- { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 800x600-60 */ -- { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x960-60 VESA */ -+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-60 */ -- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x960-85 VESA */ -+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-70 */ -- { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-60 VESA */ -+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-72 */ -- { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-75 */ -- { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-85 */ -- { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-90 */ -- { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-100 */ -- { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1024x768-60 */ -- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-75 VESA */ -+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-60 */ -- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-70 */ -- { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-72 */ -- { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-75 */ -- { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-85 */ -- { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-90 */ -- { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-100 */ -- { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1152x864-60 */ -- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1280x1024-85 VESA */ -+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-60 */ -- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-70 */ -- { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-72 */ -- { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-75 */ -- { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-85 */ -- { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-90 */ -- { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-100 */ -- { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1280x1024-60 */ -- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, -- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-60 */ -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-60 VESA */ - { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-70 */ -- { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-72 */ -- { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-75 */ -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-75 VESA */ - { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-85 */ -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1600x1200-85 VESA */ - { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-90 */ -- { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-100 */ -- { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1600x1200-60 */ -- { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, - FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-60 */ -- { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-70 */ -- { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-72 */ -- { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-75 */ -- { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -- /* 1920x1440-85 */ -- { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3, -- 0, FB_VMODE_NONINTERLACED, 0 }, -+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, -+ /* 1200x900-75 - CRT timings for the OLPC mode */ -+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, -+ 0, FB_VMODE_NONINTERLACED, 0 } ++ /* REVISIT: many of these chips have deep power-down modes, which ++ * should clearly be entered on suspend() to minimize power use. ++ * And also when they're otherwise idle... ++ */ }; -+#ifdef CONFIG_OLPC -+const struct fb_videomode olpc_dcon_modedb[] __initdata = { -+ /* The only mode the DCON has is 1200x900 */ -+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, -+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -+ FB_VMODE_NONINTERLACED, 0 } -+}; -+#endif -+ - static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) - { - if (var->xres > 1920 || var->yres > 1440) -@@ -379,16 +278,55 @@ static int __init lxfb_map_video_memory(struct fb_info *info, - return 0; - } -+static int lxfb_set_gamma(struct fb_info *info, void * __user data) -+{ -+ unsigned int gamma[LXFB_GAMMA_DWORDS]; -+ -+ if (copy_from_user(gamma, data, LXFB_GAMMA_SIZE)) -+ return -EFAULT; -+ -+ lx_set_gamma(info, gamma, LXFB_GAMMA_SIZE); -+ return 0; -+} -+ -+static int lxfb_get_gamma(struct fb_info *info, void * __user data) -+{ -+ unsigned int gamma[LXFB_GAMMA_DWORDS]; -+ memset(gamma, 0, sizeof(gamma)); -+ -+ lx_get_gamma(info, gamma, LXFB_GAMMA_DWORDS); -+ -+ return copy_to_user(data, gamma, LXFB_GAMMA_SIZE) ? -+ -EFAULT : 0; -+} -+ -+static int lxfb_ioctl( struct fb_info *info, unsigned int cmd, -+ unsigned long arg) -+{ -+ switch(cmd) { -+ case FBIOSGAMMA: -+ return lxfb_set_gamma(info, (void * __user) arg); -+ -+ case FBIOGGAMMA: -+ return lxfb_get_gamma(info, (void * __user) arg); -+ } -+ -+ return -ENOTTY; -+} -+ - static struct fb_ops lxfb_ops = { - .owner = THIS_MODULE, - .fb_check_var = lxfb_check_var, - .fb_set_par = lxfb_set_par, - .fb_setcolreg = lxfb_setcolreg, - .fb_blank = lxfb_blank, -+ .fb_ioctl = lxfb_ioctl, - /* No HW acceleration for now. */ - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, -+ .fb_powerdown = lx_shutdown, -+ .fb_powerup = lx_powerup, - }; +diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c +index a987e91..a5ed6d2 100644 +--- a/drivers/mtd/devices/mtd_dataflash.c ++++ b/drivers/mtd/devices/mtd_dataflash.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -89,7 +90,7 @@ struct dataflash { + unsigned short page_offset; /* offset in flash address */ + unsigned int page_size; /* of bytes per page */ + +- struct semaphore lock; ++ struct mutex lock; + struct spi_device *spi; + + struct mtd_info mtd; +@@ -167,7 +168,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) + x.len = 4; + spi_message_add_tail(&x, &msg); - static struct fb_info * __init lxfb_init_fbinfo(struct device *dev) -@@ -431,6 +369,45 @@ static struct fb_info * __init lxfb_init_fbinfo(struct device *dev) - return info; - } +- down(&priv->lock); ++ mutex_lock(&priv->lock); + while (instr->len > 0) { + unsigned int pageaddr; + int status; +@@ -210,7 +211,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) + instr->len -= priv->page_size; + } + } +- up(&priv->lock); ++ mutex_unlock(&priv->lock); -+#ifdef CONFIG_PM -+ -+static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ if (pdev->dev.power.power_state.event == state.event) -+ return 0; -+ -+ if (state.event == PM_EVENT_SUSPEND) { -+ -+ acquire_console_sem(); -+ lx_shutdown(info); -+ fb_set_suspend(info, 1); -+ release_console_sem(); -+ } -+ -+ pdev->dev.power.power_state = state; -+ return 0; -+} -+ -+static int lxfb_resume(struct pci_dev *pdev) -+{ -+ struct fb_info *info = pci_get_drvdata(pdev); -+ -+ acquire_console_sem(); -+ -+ /* Turn the engine completely on */ -+ -+ lx_powerup(info); -+ fb_set_suspend(info, 0); -+ release_console_sem(); -+ -+ pdev->dev.power.power_state = PMSG_ON; -+ return 0; -+} -+ -+#endif -+ - static int __init lxfb_probe(struct pci_dev *pdev, - const struct pci_device_id *id) - { -@@ -467,6 +444,13 @@ static int __init lxfb_probe(struct pci_dev *pdev, - modedb_ptr = (struct fb_videomode *) geode_modedb; - modedb_size = ARRAY_SIZE(geode_modedb); + /* Inform MTD subsystem that erase is complete */ + instr->state = MTD_ERASE_DONE; +@@ -266,7 +267,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, + x[1].len = len; + spi_message_add_tail(&x[1], &msg); -+#ifdef CONFIG_OLPC -+ if (olpc_has_dcon()) { -+ modedb_ptr = (struct fb_videomode *) olpc_dcon_modedb; -+ modedb_size = ARRAY_SIZE(olpc_dcon_modedb); -+ } -+#endif -+ - ret = fb_find_mode(&info->var, info, mode_option, - modedb_ptr, modedb_size, NULL, 16); +- down(&priv->lock); ++ mutex_lock(&priv->lock); -@@ -556,6 +540,10 @@ static struct pci_driver lxfb_driver = { - .id_table = lxfb_id_table, - .probe = lxfb_probe, - .remove = lxfb_remove, -+#ifdef CONFIG_PM -+ .suspend = lxfb_suspend, -+ .resume = lxfb_resume -+#endif - }; + /* Continuous read, max clock = f(car) which may be less than + * the peak rate available. Some chips support commands with +@@ -279,7 +280,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, + /* plus 4 "don't care" bytes */ - #ifndef MODULE -diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c -index 4fbc99b..47ed9de 100644 ---- a/drivers/video/geode/lxfb_ops.c -+++ b/drivers/video/geode/lxfb_ops.c -@@ -13,9 +13,13 @@ - #include - #include - #include -+#include + status = spi_sync(priv->spi, &msg); +- up(&priv->lock); ++ mutex_unlock(&priv->lock); - #include "lxfb.h" + if (status >= 0) { + *retlen = msg.actual_length - 8; +@@ -336,7 +337,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, + else + writelen = len; -+#define _GEODELX_ -+#include "geode_regs.h" -+ - /* TODO - * Support panel scaling - * Add acceleration -@@ -290,6 +294,19 @@ unsigned int lx_framebuffer_size(void) - { - unsigned int val; +- down(&priv->lock); ++ mutex_lock(&priv->lock); + while (remaining > 0) { + DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n", + pageaddr, offset, writelen); +@@ -441,7 +442,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, + else + writelen = remaining; + } +- up(&priv->lock); ++ mutex_unlock(&priv->lock); -+#ifdef CONFIG_OLPC -+ if (machine_is_olpc() && !olpc_has_vsa()) { -+ u32 hi,lo; -+ rdmsr(MSR_LX_GLIU0_P2D_RO0, lo, hi); -+ -+ /* Top page number */ -+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); -+ val -= (lo & 0x000fffff); /* Subtract bottom page number */ -+ val += 1; /* Adjust page count */ -+ return (val << 12); -+ } -+#endif -+ - /* The frame buffer size is reported by a VSM in VSA II */ - /* Virtual Register Class = 0x02 */ - /* VG_MEM_SIZE (1MB units) = 0x00 */ -@@ -301,6 +318,34 @@ unsigned int lx_framebuffer_size(void) - return (val << 20); + return status; } +@@ -463,7 +464,7 @@ add_dataflash(struct spi_device *spi, char *name, + if (!priv) + return -ENOMEM; -+void lx_set_gamma(struct fb_info *info, unsigned int *gamma, int len) -+{ -+ int i; -+ struct lxfb_par *par = info->par; -+ -+ writel(0, par->df_regs + DF_PAR); -+ -+ /* Sequential writes to the data register will increment the -+ address automatically */ -+ -+ for(i = 0; i < len; i++) -+ writel(gamma[i] & 0xFFFFFF, par->df_regs + DF_PDR); -+ -+ writel(readl(par->df_regs + DF_MISC) & ~DF_MISC_GAM_BYPASS, -+ par->df_regs + DF_MISC); -+} -+ -+void lx_get_gamma(struct fb_info *info, unsigned int *gamma, int len) -+{ -+ int i; -+ struct lxfb_par *par = info->par; -+ -+ writel(0, par->df_regs + DF_PAR); -+ -+ for(i = 0; i < len;i++) -+ gamma[i] = readl(par->df_regs + DF_PDR); -+} -+ - void lx_set_mode(struct fb_info *info) - { - struct lxfb_par *par = info->par; -@@ -313,6 +358,7 @@ void lx_set_mode(struct fb_info *info) - int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; +- init_MUTEX(&priv->lock); ++ mutex_init(&priv->lock); + priv->spi = spi; + priv->page_size = pagesize; + priv->page_offset = pageoffset; +diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c +index e8f686f..7060a08 100644 +--- a/drivers/mtd/devices/pmc551.c ++++ b/drivers/mtd/devices/pmc551.c +@@ -30,8 +30,8 @@ + * + * Notes: + * Due to what I assume is more buggy SROM, the 64M PMC551 I +- * have available claims that all 4 of it's DRAM banks have 64M +- * of ram configured (making a grand total of 256M onboard). ++ * have available claims that all 4 of its DRAM banks have 64MiB ++ * of ram configured (making a grand total of 256MiB onboard). + * This is slightly annoying since the BAR0 size reflects the + * aperture size, not the dram size, and the V370PDC supplies no + * other method for memory size discovery. This problem is +@@ -70,7 +70,7 @@ + * made the memory unusable, added a fix to code to touch up + * the DRAM some. + * +- * Bugs/FIXME's: ++ * Bugs/FIXMEs: + * * MUST fix the init function to not spin on a register + * waiting for it to set .. this does not safely handle busted + * devices that never reset the register correctly which will +@@ -562,10 +562,10 @@ static u32 fixup_pmc551(struct pci_dev *dev) + /* + * Some screen fun + */ +- printk(KERN_DEBUG "pmc551: %d%c (0x%x) of %sprefetchable memory at " ++ printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at " + "0x%llx\n", (size < 1024) ? size : (size < 1048576) ? + size >> 10 : size >> 20, +- (size < 1024) ? 'B' : (size < 1048576) ? 'K' : 'M', size, ++ (size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size, + ((dcmd & (0x1 << 3)) == 0) ? "non-" : "", + (unsigned long long)pci_resource_start(dev, 0)); - /* Unlock the DC registers */ -+ readl(par->dc_regs + DC_UNLOCK); - writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); +@@ -649,14 +649,10 @@ MODULE_DESCRIPTION(PMC551_VERSION); + * Stuff these outside the ifdef so as to not bust compiled in driver support + */ + static int msize = 0; +-#if defined(CONFIG_MTD_PMC551_APERTURE_SIZE) +-static int asize = CONFIG_MTD_PMC551_APERTURE_SIZE; +-#else + static int asize = 0; +-#endif + + module_param(msize, int, 0); +-MODULE_PARM_DESC(msize, "memory size in Megabytes [1 - 1024]"); ++MODULE_PARM_DESC(msize, "memory size in MiB [1 - 1024]"); + module_param(asize, int, 0); + MODULE_PARM_DESC(asize, "aperture size, must be <= memsize [1-1024]"); + +@@ -799,8 +795,7 @@ static int __init init_pmc551(void) + mtd->owner = THIS_MODULE; + + if (add_mtd_device(mtd)) { +- printk(KERN_NOTICE "pmc551: Failed to register new " +- "device\n"); ++ printk(KERN_NOTICE "pmc551: Failed to register new device\n"); + pci_iounmap(PCI_Device, priv->start); + kfree(mtd->priv); + kfree(mtd); +@@ -811,13 +806,13 @@ static int __init init_pmc551(void) + pci_dev_get(PCI_Device); - lx_graphics_disable(info); -@@ -534,3 +580,285 @@ int lx_blank_display(struct fb_info *info, int blank_mode) + printk(KERN_NOTICE "Registered pmc551 memory device.\n"); +- printk(KERN_NOTICE "Mapped %dM of memory from 0x%p to 0x%p\n", ++ printk(KERN_NOTICE "Mapped %dMiB of memory from 0x%p to 0x%p\n", + priv->asize >> 20, + priv->start, priv->start + priv->asize); +- printk(KERN_NOTICE "Total memory is %d%c\n", ++ printk(KERN_NOTICE "Total memory is %d%sB\n", + (length < 1024) ? length : + (length < 1048576) ? length >> 10 : length >> 20, +- (length < 1024) ? 'B' : (length < 1048576) ? 'K' : 'M'); ++ (length < 1024) ? "" : (length < 1048576) ? "Ki" : "Mi"); + priv->nextpmc551 = pmc551list; + pmc551list = mtd; + found++; +@@ -850,7 +845,7 @@ static void __exit cleanup_pmc551(void) + pmc551list = priv->nextpmc551; - return 0; - } -+ -+static struct geoderegs saved_regs; -+ -+static void lx_save_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct lxfb_par *par = info->par; -+ int i; -+ -+ /* Wait for the command buffer to empty */ -+ while(!(readl(par->gp_regs + 0x44) & (1 << 4))); -+ -+ rdmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); -+ rdmsrl(MSR_LX_GLCP_DOTPLL, regs->msr.dotpll); -+ rdmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); -+ rdmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); -+ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE); -+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE); -+ memcpy(regs->vp.b, par->df_regs, VP_REG_SIZE); -+ memcpy(regs->fp.b, par->df_regs + VP_FP_START, FP_REG_SIZE); -+ -+ /* Save the palettes */ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ regs->pal[i] = readl(par->dc_regs + 0x74); -+ -+ writel(0, par->df_regs + 0x38); -+ -+ for(i = 0; i <= 0xFF; i++) -+ regs->gamma[i] = readl(par->df_regs + 0x40); -+} -+ -+static void lx_restore_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct lxfb_par *par = info->par; -+ u32 val, i; -+ -+ /* == DOTPLL == */ -+ -+ lx_set_dotpll((u32) (regs->msr.dotpll >> 32)); -+ -+ /* MSRs */ -+ -+ wrmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); -+ -+ /* == GP == */ -+ -+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00); -+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04); -+ writel(regs->gp.r.stride, par->gp_regs + 0x08); -+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C); -+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10); -+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14); -+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18); -+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C); -+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20); -+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24); -+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28); -+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C); -+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30); -+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34); -+ -+ /* Writing to these registers would cause a blt to happen */ -+ /* 0x38, 0x3c, 0x40 */ -+ -+ /* Status register (0x44) is read only */ -+ -+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48); -+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c); -+ writel(regs->gp.r.cmd_top, par->gp_regs + 0x50); -+ writel(regs->gp.r.cmd_bot, par->gp_regs + 0x54); -+ writel(regs->gp.r.cmd_read, par->gp_regs + 0x58); -+ writel(regs->gp.r.cmd_write, par->gp_regs + 0x5C); -+ writel(regs->gp.r.ch3_offset, par->gp_regs + 0x60); -+ writel(regs->gp.r.ch3_mode_str, par->gp_regs + 0x64); -+ writel(regs->gp.r.ch3_width, par->gp_regs + 0x6C); -+ writel(regs->gp.r.ch3_hsrc, par->gp_regs + 0x70); -+ -+ /* FIXME: Restore the LUT data here */ -+ -+ writel(regs->gp.r.int_cntrl, par->gp_regs + 0x70); -+ -+ /* == DC == */ -+ -+ /* Write the unlock value */ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ /* Write the palette data first */ -+ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ writel(regs->pal[i], par->dc_regs + 0x74); -+ -+ /* MSRs */ -+ wrmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); -+ -+ /* Write the gcfg register without the enables */ -+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04); -+ -+ /* Write the vcfg register without the enables */ -+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08); -+ -+ /* Write the rest of the active registers */ -+ writel(regs->dc.r.arb, par->dc_regs + 0x0C); -+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10); -+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14); -+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18); -+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C); -+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20); -+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24); -+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28); -+ writel(regs->dc.r.dctop, par->dc_regs + 0x2c); -+ writel(regs->dc.r.line_size, par->dc_regs + 0x30); -+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34); -+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38); -+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40); -+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44); -+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48); -+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50); -+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54); -+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58); -+ writel(regs->dc.r.fbactive, par->dc_regs + 0x5c); -+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60); -+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64); -+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68); -+ -+ /* Skip register 0x6C (line_cnt), 0x70/0x74 (palette), -+ 0x78 (diagnostic), and 0x7c (diagnostic) -+ */ -+ -+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80); -+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84); -+ writel(regs->dc.r.dv_ctl, par->dc_regs + 0x88); -+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C); -+ -+ writel(regs->dc.r.gfx_scale, par->dc_regs + 0x90); -+ writel(regs->dc.r.irq_filt_ctl, par->dc_regs + 0x94); -+ writel(regs->dc.r.filt_coeff1, par->dc_regs + 0x98); -+ writel(regs->dc.r.filt_coeff2, par->dc_regs + 0x9C); -+ writel(regs->dc.r.vbi_event_ctl, par->dc_regs + 0xA0); -+ -+ writel(regs->dc.r.vbi_odd_ctl, par->dc_regs + 0xA4); -+ writel(regs->dc.r.vbi_hor, par->dc_regs + 0xA8); -+ writel(regs->dc.r.vbi_ln_odd, par->dc_regs + 0xAC); -+ writel(regs->dc.r.vbi_ln_event, par->dc_regs + 0xB0); -+ writel(regs->dc.r.vbi_pitch, par->dc_regs + 0xB4); -+ writel(regs->dc.r.clr_key, par->dc_regs + 0xB8); -+ writel(regs->dc.r.clr_key_mask, par->dc_regs + 0xBC); -+ -+ writel(regs->dc.r.clr_key_x, par->dc_regs + 0xC0); -+ writel(regs->dc.r.clr_key_y, par->dc_regs + 0xC4); -+ writel(regs->dc.r.irq, par->dc_regs + 0xC8); -+ writel(regs->dc.r.genlk_ctrl, par->dc_regs + 0xD4); -+ -+ writel(regs->dc.r.vid_even_y_st_offset, par->dc_regs + 0xD8); -+ writel(regs->dc.r.vid_even_u_st_offset, par->dc_regs + 0xDC); -+ writel(regs->dc.r.vid_even_v_st_offset, par->dc_regs + 0xE0); -+ -+ writel(regs->dc.r.v_active_even_timing, par->dc_regs + 0xE4); -+ writel(regs->dc.r.v_blank_even_timing, par->dc_regs + 0xE8); -+ writel(regs->dc.r.v_sync_even_timing, par->dc_regs + 0xEC); -+ -+ /* == VP == */ -+ -+ /* MSR */ -+ wrmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); -+ -+ /* Write gamma information first */ -+ -+ writel(0, par->df_regs + 0x38); -+ -+ for(i = 0; i <= 0xFF; i++) -+ writel((u32) regs->gamma[i], par->df_regs + 0x40); -+ -+ /* Don't enable video yet */ -+ writel((u32) regs->vp.r.vcfg & ~0x01, par->df_regs + 0x00); -+ -+ /* Don't enable the CRT yet */ -+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->df_regs + 0x08); -+ -+ /* Write the rest of the VP registers */ -+ -+ writel((u32) regs->vp.r.vx, par->df_regs + 0x10); -+ writel((u32) regs->vp.r.vy, par->df_regs + 0x18); -+ writel((u32) regs->vp.r.vs, par->df_regs + 0x20); -+ writel((u32) regs->vp.r.vck, par->df_regs + 0x28); -+ writel((u32) regs->vp.r.vcm, par->df_regs + 0x30); -+ writel((u32) regs->vp.r.misc, par->df_regs + 0x50); -+ writel((u32) regs->vp.r.ccs, par->df_regs + 0x58); -+ writel((u32) regs->vp.r.vdc, par->df_regs + 0x78); -+ writel((u32) regs->vp.r.vco, par->df_regs + 0x80); -+ writel((u32) regs->vp.r.crc, par->df_regs + 0x88); -+ writel((u32) regs->vp.r.vde, par->df_regs + 0x98); -+ writel((u32) regs->vp.r.cck, par->df_regs + 0xA0); -+ writel((u32) regs->vp.r.ccm, par->df_regs + 0xA8); -+ writel((u32) regs->vp.r.cc1, par->df_regs + 0xB0); -+ writel((u32) regs->vp.r.cc2, par->df_regs + 0xB8); -+ writel((u32) regs->vp.r.a1x, par->df_regs + 0xC0); -+ writel((u32) regs->vp.r.a1y, par->df_regs + 0xC8); -+ writel((u32) regs->vp.r.a1c, par->df_regs + 0xD0); -+ writel((u32) regs->vp.r.a1t, par->df_regs + 0xD8); -+ writel((u32) regs->vp.r.a2x, par->df_regs + 0xE0); -+ writel((u32) regs->vp.r.a2y, par->df_regs + 0xE8); -+ writel((u32) regs->vp.r.a2c, par->df_regs + 0xF0); -+ writel((u32) regs->vp.r.a2t, par->df_regs + 0xF8); -+ writel((u32) regs->vp.r.a3x, par->df_regs + 0x100); -+ writel((u32) regs->vp.r.a3y, par->df_regs + 0x108); -+ writel((u32) regs->vp.r.a3c, par->df_regs + 0x110); -+ writel((u32) regs->vp.r.a3t, par->df_regs + 0x118); -+ writel((u32) regs->vp.r.vrr, par->df_regs + 0x120); -+ -+ writel((u32) regs->vp.r.vye, par->df_regs + 0x138); -+ writel((u32) regs->vp.r.a1ye, par->df_regs + 0x140); -+ writel((u32) regs->vp.r.a2ye, par->df_regs + 0x148); -+ writel((u32) regs->vp.r.a3ye, par->df_regs + 0x150); -+ -+ /* == FP == */ -+ -+ writel((u32) regs->fp.r.pt1, par->df_regs + 0x400); -+ writel((u32) regs->fp.r.pt2, par->df_regs + 0x408); -+ writel((u32) regs->fp.r.dfc, par->df_regs + 0x418); -+ writel(regs->fp.r.dca, par->df_regs + 0x448); -+ writel(regs->fp.r.dmd, par->df_regs + 0x450); -+ writel(regs->fp.r.crc, par->df_regs + 0x458); -+ -+ /* Final enables */ + if (priv->start) { +- printk(KERN_DEBUG "pmc551: unmapping %dM starting at " ++ printk(KERN_DEBUG "pmc551: unmapping %dMiB starting at " + "0x%p\n", priv->asize >> 20, priv->start); + pci_iounmap(priv->dev, priv->start); + } +diff --git a/drivers/mtd/maps/nettel.c b/drivers/mtd/maps/nettel.c +index 7b96cd0..0c9b305 100644 +--- a/drivers/mtd/maps/nettel.c ++++ b/drivers/mtd/maps/nettel.c +@@ -158,68 +158,11 @@ static struct notifier_block nettel_notifier_block = { + nettel_reboot_notifier, NULL, 0 + }; + +-/* +- * Erase the configuration file system. +- * Used to support the software reset button. +- */ +-static void nettel_erasecallback(struct erase_info *done) +-{ +- wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; +- wake_up(wait_q); +-} +- +-static struct erase_info nettel_erase; +- +-int nettel_eraseconfig(void) +-{ +- struct mtd_info *mtd; +- DECLARE_WAITQUEUE(wait, current); +- wait_queue_head_t wait_q; +- int ret; +- +- init_waitqueue_head(&wait_q); +- mtd = get_mtd_device(NULL, 2); +- if (!IS_ERR(mtd)) { +- nettel_erase.mtd = mtd; +- nettel_erase.callback = nettel_erasecallback; +- nettel_erase.callback = NULL; +- nettel_erase.addr = 0; +- nettel_erase.len = mtd->size; +- nettel_erase.priv = (u_long) &wait_q; +- nettel_erase.priv = 0; +- +- set_current_state(TASK_INTERRUPTIBLE); +- add_wait_queue(&wait_q, &wait); +- +- ret = mtd->erase(mtd, &nettel_erase); +- if (ret) { +- set_current_state(TASK_RUNNING); +- remove_wait_queue(&wait_q, &wait); +- put_mtd_device(mtd); +- return(ret); +- } +- +- schedule(); /* Wait for erase to finish. */ +- remove_wait_queue(&wait_q, &wait); +- +- put_mtd_device(mtd); +- } +- +- return(0); +-} +- +-#else +- +-int nettel_eraseconfig(void) +-{ +- return(0); +-} +- + #endif + + /****************************************************************************/ + +-int __init nettel_init(void) ++static int __init nettel_init(void) + { + volatile unsigned long *amdpar; + unsigned long amdaddr, maxsize; +@@ -421,10 +364,6 @@ int __init nettel_init(void) + + intel_mtd->owner = THIS_MODULE; + +-#ifndef CONFIG_BLK_DEV_INITRD +- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1); +-#endif +- + num_intel_partitions = sizeof(nettel_intel_partitions) / + sizeof(nettel_intel_partitions[0]); + +@@ -477,7 +416,7 @@ out_unmap2: + + /****************************************************************************/ + +-void __exit nettel_cleanup(void) ++static void __exit nettel_cleanup(void) + { + #ifdef CONFIG_MTD_CFI_INTELEXT + unregister_reboot_notifier(&nettel_notifier_block); +diff --git a/drivers/mtd/maps/pmcmsp-ramroot.c b/drivers/mtd/maps/pmcmsp-ramroot.c +index 18049bc..30de5c0 100644 +--- a/drivers/mtd/maps/pmcmsp-ramroot.c ++++ b/drivers/mtd/maps/pmcmsp-ramroot.c +@@ -79,7 +79,6 @@ static int __init init_rrmap(void) + rr_mtd->owner = THIS_MODULE; + + add_mtd_device(rr_mtd); +- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, rr_mtd->index); + + return 0; + } +diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c +index ef89780..74d9d30 100644 +--- a/drivers/mtd/mtd_blkdevs.c ++++ b/drivers/mtd/mtd_blkdevs.c +@@ -24,10 +24,9 @@ + #include + #include + +-static LIST_HEAD(blktrans_majors); ++#include "mtdcore.h" + +-extern struct mutex mtd_table_mutex; +-extern struct mtd_info *mtd_table[]; ++static LIST_HEAD(blktrans_majors); + + struct mtd_blkcore_priv { + struct task_struct *thread; +@@ -202,7 +201,7 @@ static int blktrans_ioctl(struct inode *inode, struct file *file, + } + } + +-struct block_device_operations mtd_blktrans_ops = { ++static struct block_device_operations mtd_blktrans_ops = { + .owner = THIS_MODULE, + .open = blktrans_open, + .release = blktrans_release, +diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c +index d091b24..22ed96c 100644 +--- a/drivers/mtd/mtdchar.c ++++ b/drivers/mtd/mtdchar.c +@@ -136,7 +136,8 @@ static int mtd_close(struct inode *inode, struct file *file) + + DEBUG(MTD_DEBUG_LEVEL0, "MTD_close\n"); + +- if (mtd->sync) ++ /* Only sync if opened RW */ ++ if ((file->f_mode & 2) && mtd->sync) + mtd->sync(mtd); + + put_mtd_device(mtd); +diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c +index c153b64..6c2645e 100644 +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -22,6 +22,8 @@ + + #include + ++#include "mtdcore.h" + -+ val = readl(par->df_regs + 0x410); + /* These are exported solely for the purpose of mtd_blkdevs.c. You + should not use them for _anything_ else */ + DEFINE_MUTEX(mtd_table_mutex); +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index f1d60b6..df25cab 100644 +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -134,10 +134,10 @@ config MTD_NAND_S3C2410_HWECC + + config MTD_NAND_NDFC + tristate "NDFC NanD Flash Controller" +- depends on 44x ++ depends on 4xx + select MTD_NAND_ECC_SMC + help +- NDFC Nand Flash Controllers are integrated in EP44x SoCs ++ NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs + + config MTD_NAND_S3C2410_CLKSTOP + bool "S3C2410 NAND IDLE clock stop" +@@ -237,7 +237,7 @@ config MTD_NAND_CAFE + select REED_SOLOMON + select REED_SOLOMON_DEC16 + help +- Use NAND flash attached to the CAFÉ chip designed for the $100 ++ Use NAND flash attached to the CAFÉ chip designed for the OLPC + laptop. + + config MTD_NAND_CS553X +diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c +index cff969d..cca69b3 100644 +--- a/drivers/mtd/nand/cafe_nand.c ++++ b/drivers/mtd/nand/cafe_nand.c +@@ -821,14 +821,53 @@ static struct pci_device_id cafe_nand_tbl[] = { + + MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); + ++static int cafe_nand_resume(struct pci_dev *pdev) ++{ ++ uint32_t timing1, timing2, timing3; ++ uint32_t ctrl; ++ struct mtd_info *mtd = pci_get_drvdata(pdev); ++ struct cafe_priv *cafe = mtd->priv; + -+ /* Control the panel */ -+ if (regs->fp.r.pm & (1 << 24)) { ++ timing1 = timing2 = timing3 = 0xffffffff; ++ /* Start off by resetting the NAND controller completely */ ++ cafe_writel(cafe, 1, NAND_RESET); ++ cafe_writel(cafe, 0, NAND_RESET); ++ cafe_writel(cafe, timing1, NAND_TIMING1); ++ cafe_writel(cafe, timing2, NAND_TIMING2); ++ cafe_writel(cafe, timing3, NAND_TIMING3); ++ cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); + -+ if (!(val & 0x09)) -+ writel(regs->fp.r.pm, par->df_regs + 0x410); -+ } -+ else { -+ if (!(val & 0x05)) -+ writel(regs->fp.r.pm, par->df_regs + 0x410); -+ } ++ /* Disable master reset, enable NAND clock */ ++ ctrl = cafe_readl(cafe, GLOBAL_CTRL); ++ ctrl &= 0xffffeff0; ++ ctrl |= 0x00007000; ++ cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); ++ cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); ++ cafe_writel(cafe, 0, NAND_DMA_CTRL); ++ cafe_writel(cafe, 0x7006, GLOBAL_CTRL); ++ cafe_writel(cafe, 0x700a, GLOBAL_CTRL); + -+ /* Turn everything on */ ++ /* Set up DMA address */ ++ cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); ++ if (sizeof(cafe->dmaaddr) > 4) ++ /* Shift in two parts to shut the compiler up */ ++ cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); ++ else ++ cafe_writel(cafe, 0, NAND_DMA_ADDR1); + -+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04); -+ writel((u32) regs->vp.r.vcfg, par->df_regs + 0x00); -+ writel((u32) regs->vp.r.dcfg, par->df_regs + 0x08); -+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08); ++ /* Enable NAND IRQ in global IRQ mask register */ ++ cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); ++ return 0; +} + -+static int lx_power_on = 1; + static struct pci_driver cafe_nand_pci_driver = { + .name = "CAFÉ NAND", + .id_table = cafe_nand_tbl, + .probe = cafe_nand_probe, + .remove = __devexit_p(cafe_nand_remove), ++ .resume = cafe_nand_resume, + #ifdef CONFIG_PMx + .suspend = cafe_nand_suspend, +- .resume = cafe_nand_resume, + #endif + }; + +diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c +index fd7a8d5..1c0e89f 100644 +--- a/drivers/mtd/nand/ndfc.c ++++ b/drivers/mtd/nand/ndfc.c +@@ -24,7 +24,11 @@ + #include + + #include ++#ifdef CONFIG_40x ++#include ++#else + #include ++#endif + + struct ndfc_nand_mtd { + struct mtd_info mtd; +@@ -230,7 +234,11 @@ static int ndfc_nand_probe(struct platform_device *pdev) + struct ndfc_controller *ndfc = &ndfc_ctrl; + unsigned long long phys = settings->ndfc_erpn | res->start; + ++#ifndef CONFIG_PHYS_64BIT ++ ndfc->ndfcbase = ioremap((phys_addr_t)phys, res->end - res->start + 1); ++#else + ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1); ++#endif + if (!ndfc->ndfcbase) { + printk(KERN_ERR "NDFC: ioremap failed\n"); + return -EIO; +diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig +index c257d39..cb41cbc 100644 +--- a/drivers/mtd/onenand/Kconfig ++++ b/drivers/mtd/onenand/Kconfig +@@ -40,4 +40,27 @@ config MTD_ONENAND_OTP + + OTP block is fully-guaranteed to be a valid block. + ++config MTD_ONENAND_2X_PROGRAM ++ bool "OneNAND 2X program support" ++ help ++ The 2X Program is an extension of Program Operation. ++ Since the device is equipped with two DataRAMs, and two-plane NAND ++ Flash memory array, these two component enables simultaneous program ++ of 4KiB. Plane1 has only even blocks such as block0, block2, block4 ++ while Plane2 has only odd blocks such as block1, block3, block5. ++ So MTD regards it as 4KiB page size and 256KiB block size ++ ++ Now the following chips support it. (KFXXX16Q2M) ++ Demux: KFG2G16Q2M, KFH4G16Q2M, KFW8G16Q2M, ++ Mux: KFM2G16Q2M, KFN4G16Q2M, + -+int lx_shutdown(struct fb_info *info) -+{ -+ struct lxfb_par *par = info->par; ++ And more recent chips + -+ if (lx_power_on == 0) -+ return 0; ++config MTD_ONENAND_SIM ++ tristate "OneNAND simulator support" ++ depends on MTD_PARTITIONS ++ help ++ The simulator may simulate various OneNAND flash chips for the ++ OneNAND MTD layer. + -+ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); -+ lx_save_regs(info, &saved_regs); -+ lx_graphics_disable(info); + endif # MTD_ONENAND +diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile +index 269cfe4..4d2eacf 100644 +--- a/drivers/mtd/onenand/Makefile ++++ b/drivers/mtd/onenand/Makefile +@@ -8,4 +8,7 @@ obj-$(CONFIG_MTD_ONENAND) += onenand.o + # Board specific. + obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o + ++# Simulator ++obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o + -+ lx_power_on = 0; -+ return 0; -+} + onenand-objs = onenand_base.o onenand_bbt.o +diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c +index 0537fac..7d194cf 100644 +--- a/drivers/mtd/onenand/onenand_base.c ++++ b/drivers/mtd/onenand/onenand_base.c +@@ -206,6 +206,15 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le + default: + block = (int) (addr >> this->erase_shift); + page = (int) (addr >> this->page_shift); + -+int lx_powerup(struct fb_info *info) ++ if (ONENAND_IS_2PLANE(this)) { ++ /* Make the even block number */ ++ block &= ~1; ++ /* Is it the odd plane? */ ++ if (addr & this->writesize) ++ block++; ++ page >>= 1; ++ } + page &= this->page_mask; + break; + } +@@ -216,8 +225,12 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le + value = onenand_bufferram_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + +- /* Switch to the next data buffer */ +- ONENAND_SET_NEXT_BUFFERRAM(this); ++ if (ONENAND_IS_2PLANE(this)) ++ /* It is always BufferRAM0 */ ++ ONENAND_SET_BUFFERRAM0(this); ++ else ++ /* Switch to the next data buffer */ ++ ONENAND_SET_NEXT_BUFFERRAM(this); + + return 0; + } +@@ -247,6 +260,8 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le + break; + + default: ++ if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG) ++ cmd = ONENAND_CMD_2X_PROG; + dataram = ONENAND_CURRENT_BUFFERRAM(this); + break; + } +@@ -445,8 +460,9 @@ static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { ++ /* Note: the 'this->writesize' is a real page size */ + if (area == ONENAND_DATARAM) +- return mtd->writesize; ++ return this->writesize; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } +@@ -572,6 +588,30 @@ static int onenand_write_bufferram(struct mtd_info *mtd, int area, + } + + /** ++ * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode ++ * @param mtd MTD data structure ++ * @param addr address to check ++ * @return blockpage address ++ * ++ * Get blockpage address at 2x program mode ++ */ ++static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr) +{ -+ struct lxfb_par *par = info->par; -+ -+ if (lx_power_on == 1) -+ return 0; ++ struct onenand_chip *this = mtd->priv; ++ int blockpage, block, page; + -+ lx_restore_regs(info, &saved_regs); -+ writel(0, par->dc_regs + DC_UNLOCK); ++ /* Calculate the even block number */ ++ block = (int) (addr >> this->erase_shift) & ~1; ++ /* Is it the odd plane? */ ++ if (addr & this->writesize) ++ block++; ++ page = (int) (addr >> (this->page_shift + 1)) & this->page_mask; ++ blockpage = (block << 7) | page; + -+ lx_power_on = 1; -+ return 0; ++ return blockpage; +} -diff --git a/drivers/video/geode/suspend_gx.c b/drivers/video/geode/suspend_gx.c -new file mode 100644 -index 0000000..43c25be ---- /dev/null -+++ b/drivers/video/geode/suspend_gx.c -@@ -0,0 +1,272 @@ -+#include -+#include -+#include -+ -+#include "geodefb.h" -+#include "video_gx.h" -+ -+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs) -+{ -+ int timeout = 1000; + -+ u64 rstpll, dotpll; -+ -+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll); -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); ++/** + * onenand_check_bufferram - [GENERIC] Check BufferRAM information + * @param mtd MTD data structure + * @param addr address to check +@@ -585,7 +625,10 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) + int blockpage, found = 0; + unsigned int i; + +- blockpage = (int) (addr >> this->page_shift); ++ if (ONENAND_IS_2PLANE(this)) ++ blockpage = onenand_get_2x_blockpage(mtd, addr); ++ else ++ blockpage = (int) (addr >> this->page_shift); + + /* Is there valid data? */ + i = ONENAND_CURRENT_BUFFERRAM(this); +@@ -625,7 +668,10 @@ static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, + int blockpage; + unsigned int i; + +- blockpage = (int) (addr >> this->page_shift); ++ if (ONENAND_IS_2PLANE(this)) ++ blockpage = onenand_get_2x_blockpage(mtd, addr); ++ else ++ blockpage = (int) (addr >> this->page_shift); + + /* Invalidate another BufferRAM */ + i = ONENAND_NEXT_BUFFERRAM(this); +@@ -734,6 +780,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, + int read = 0, column; + int thislen; + int ret = 0, boundary = 0; ++ int writesize = this->writesize; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + +@@ -754,22 +801,22 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, + /* Do first load to bufferRAM */ + if (read < len) { + if (!onenand_check_bufferram(mtd, from)) { +- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); ++ this->command(mtd, ONENAND_CMD_READ, from, writesize); + ret = this->wait(mtd, FL_READING); + onenand_update_bufferram(mtd, from, !ret); + } + } + +- thislen = min_t(int, mtd->writesize, len - read); +- column = from & (mtd->writesize - 1); +- if (column + thislen > mtd->writesize) +- thislen = mtd->writesize - column; ++ thislen = min_t(int, writesize, len - read); ++ column = from & (writesize - 1); ++ if (column + thislen > writesize) ++ thislen = writesize - column; + + while (!ret) { + /* If there is more to load then start next load */ + from += thislen; + if (read + thislen < len) { +- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); ++ this->command(mtd, ONENAND_CMD_READ, from, writesize); + /* + * Chip boundary handling in DDP + * Now we issued chip 1 read and pointed chip 1 +@@ -794,7 +841,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, + this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); + ONENAND_SET_NEXT_BUFFERRAM(this); + buf += thislen; +- thislen = min_t(int, mtd->writesize, len - read); ++ thislen = min_t(int, writesize, len - read); + column = 0; + cond_resched(); + /* Now wait for load */ +@@ -1079,7 +1126,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, + /* Read more? */ + if (read < len) { + /* Update Page size */ +- from += mtd->writesize; ++ from += this->writesize; + column = 0; + } + } +@@ -1135,12 +1182,12 @@ static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, + int thislen, column; + + while (len != 0) { +- thislen = min_t(int, mtd->writesize, len); +- column = addr & (mtd->writesize - 1); +- if (column + thislen > mtd->writesize) +- thislen = mtd->writesize - column; ++ thislen = min_t(int, this->writesize, len); ++ column = addr & (this->writesize - 1); ++ if (column + thislen > this->writesize) ++ thislen = this->writesize - column; + +- this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); ++ this->command(mtd, ONENAND_CMD_READ, addr, this->writesize); + + onenand_update_bufferram(mtd, addr, 0); + +@@ -1236,6 +1283,10 @@ static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, + + /* In partial page write we don't update bufferram */ + onenand_update_bufferram(mtd, to, !ret && !subpage); ++ if (ONENAND_IS_2PLANE(this)) { ++ ONENAND_SET_BUFFERRAM1(this); ++ onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage); ++ } + + if (ret) { + printk(KERN_ERR "onenand_write: write filaed %d\n", ret); +@@ -1384,6 +1435,10 @@ static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, + this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); + + onenand_update_bufferram(mtd, to, 0); ++ if (ONENAND_IS_2PLANE(this)) { ++ ONENAND_SET_BUFFERRAM1(this); ++ onenand_update_bufferram(mtd, to + this->writesize, 0); ++ } + + ret = this->wait(mtd, FL_WRITING); + if (ret) { +@@ -2107,6 +2162,7 @@ static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, + * + * Check and set OneNAND features + * - lock scheme ++ * - two plane + */ + static void onenand_check_features(struct mtd_info *mtd) + { +@@ -2118,19 +2174,35 @@ static void onenand_check_features(struct mtd_info *mtd) + process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; + + /* Lock scheme */ +- if (density >= ONENAND_DEVICE_DENSITY_1Gb) { ++ switch (density) { ++ case ONENAND_DEVICE_DENSITY_4Gb: ++ this->options |= ONENAND_HAS_2PLANE; + -+ dotpll &= 0x00000000ffffffffull; -+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull; -+ -+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET; -+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS; -+ -+ wrmsrl(MSR_GLCP_DOTPLL, dotpll); ++ case ONENAND_DEVICE_DENSITY_2Gb: ++ /* 2Gb DDP don't have 2 plane */ ++ if (!ONENAND_IS_DDP(this)) ++ this->options |= ONENAND_HAS_2PLANE; ++ this->options |= ONENAND_HAS_UNLOCK_ALL; + -+ rstpll |= (regs->msr.rstpll & -+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 | -+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 | -+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)); -+ -+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll); -+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET); -+ wrmsrl(MSR_GLCP_DOTPLL, dotpll); ++ case ONENAND_DEVICE_DENSITY_1Gb: + /* A-Die has all block unlock */ +- if (process) { +- printk(KERN_DEBUG "Chip support all block unlock\n"); ++ if (process) + this->options |= ONENAND_HAS_UNLOCK_ALL; +- } +- } else { +- /* Some OneNAND has continues lock scheme */ +- if (!process) { +- printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); ++ break; + -+ do { -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); -+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); -+} ++ default: ++ /* Some OneNAND has continuous lock scheme */ ++ if (!process) + this->options |= ONENAND_HAS_CONT_LOCK; +- } ++ break; + } + -+/* FIXME: Make sure nothing is read to clear */ ++ if (this->options & ONENAND_HAS_CONT_LOCK) ++ printk(KERN_DEBUG "Lock scheme is Continuous Lock\n"); ++ if (this->options & ONENAND_HAS_UNLOCK_ALL) ++ printk(KERN_DEBUG "Chip support all block unlock\n"); ++ if (this->options & ONENAND_HAS_2PLANE) ++ printk(KERN_DEBUG "Chip has 2 plane\n"); + } + + /** +@@ -2257,6 +2329,8 @@ static int onenand_probe(struct mtd_info *mtd) + this->erase_shift = ffs(mtd->erasesize) - 1; + this->page_shift = ffs(mtd->writesize) - 1; + this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1; ++ /* It's real page size */ ++ this->writesize = mtd->writesize; + + /* REVIST: Multichip handling */ + +@@ -2265,6 +2339,17 @@ static int onenand_probe(struct mtd_info *mtd) + /* Check OneNAND features */ + onenand_check_features(mtd); + ++ /* ++ * We emulate the 4KiB page and 256KiB erase block size ++ * But oobsize is still 64 bytes. ++ * It is only valid if you turn on 2X program support, ++ * Otherwise it will be ignored by compiler. ++ */ ++ if (ONENAND_IS_2PLANE(this)) { ++ mtd->writesize <<= 1; ++ mtd->erasesize <<= 1; ++ } + -+void gx_save_regs(struct fb_info *info, struct geoderegs *regs) + return 0; + } + +diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c +index 1938d6d..cc01dbd 100644 +--- a/drivers/net/forcedeth.c ++++ b/drivers/net/forcedeth.c +@@ -3556,10 +3556,12 @@ static int nv_request_irq(struct net_device *dev, int intr_test) + } + if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { + if ((ret = pci_enable_msi(np->pci_dev)) == 0) { ++ pci_intx(np->pci_dev, 0); + np->msi_flags |= NV_MSI_ENABLED; + if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { + printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); + pci_disable_msi(np->pci_dev); ++ pci_intx(np->pci_dev, 1); + np->msi_flags &= ~NV_MSI_ENABLED; + goto out_err; + } +@@ -3601,6 +3603,7 @@ static void nv_free_irq(struct net_device *dev) + free_irq(np->pci_dev->irq, dev); + if (np->msi_flags & NV_MSI_ENABLED) { + pci_disable_msi(np->pci_dev); ++ pci_intx(np->pci_dev, 1); + np->msi_flags &= ~NV_MSI_ENABLED; + } + } +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 7dcaa09..eb69d4d 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -1390,6 +1390,17 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); + + /* ++ * According to Tom Sylla, the Geode does not support PCI power management ++ * transition, so we shouldn't need the D3hot delay. ++ */ ++static void __init quirk_geode_pci_pm(struct pci_dev *dev) +{ -+ struct geodefb_par *par = info->par; -+ int i; -+ -+ /* Wait for the BLT engine to stop being busy */ -+ while(readl(par->gp_regs + 0x44) & 0x05); -+ -+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel); -+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll); -+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll); -+ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE); -+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE); -+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE); -+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE); -+ -+ /* Save the palettes */ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ regs->pal[i] = readl(par->dc_regs + 0x74); -+ -+ writel(0, par->vid_regs + 0x38); -+ -+ for(i = 0; i < 0xFF; i++) -+ regs->gamma[i] = readl(par->vid_regs + 0x40); ++ pci_pm_d3_delay = 0; +} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, quirk_geode_pci_pm); ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_geode_pci_pm); + -+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs) -+{ -+ struct geodefb_par *par = info->par; -+ u32 val, i; -+ -+ /* DOTPLL */ -+ gx_set_dotpll(info, regs); -+ -+ /* GP */ -+ -+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00); -+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04); -+ writel(regs->gp.r.stride, par->gp_regs + 0x08); -+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C); -+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10); -+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14); -+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18); -+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C); -+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20); -+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24); -+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28); -+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C); -+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30); -+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34); -+ -+ /* Don't write the raster / vector / blt mode regs */ -+ /* status register is read only */ -+ -+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48); -+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c); -+ -+ /* DC */ -+ -+ /* Write the unlock value */ -+ writel(0x4758, par->dc_regs + 0x00); -+ -+ writel(0, par->dc_regs + 0x70); -+ -+ for(i = 0; i < DC_PAL_SIZE; i++) -+ writel(regs->pal[i], par->dc_regs + 0x74); -+ -+ /* Write the gcfg register without the enables */ -+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04); -+ -+ /* Write the vcfg register without the enables */ -+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08); -+ -+ /* Write the rest of the active registers */ -+ -+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10); -+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14); -+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18); -+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C); -+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20); -+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24); -+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28); -+ writel(regs->dc.r.line_size, par->dc_regs + 0x30); -+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34); -+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38); -+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40); -+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44); -+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48); -+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50); -+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54); -+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58); -+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60); -+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64); -+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68); -+ -+ /* Don't write the line_cnt or diag registers */ -+ -+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80); -+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84); -+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C); -+ -+ /* VP */ -+ -+ /* MSR */ -+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel); -+ -+ writel(0, par->vid_regs + 0x38); -+ -+ for(i = 0; i < 0xFF; i++) -+ writel((u32) regs->gamma[i], par->vid_regs + 0x40); -+ -+ /* Don't enable video yet */ -+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00); -+ -+ /* Don't enable the CRT yet */ -+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08); -+ -+ /* Write the rest of the VP registers */ ++/* + * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size + * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. + * Re-allocate the region if needed... +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index 5216c11..3e3df7e 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -594,7 +594,7 @@ config FB_TGA + + config FB_VESA + bool "VESA VGA graphics support" +- depends on (FB = y) && X86 ++ depends on (FB = y) && X86 && !VGA_NOPROBE + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT +@@ -1028,7 +1028,7 @@ config FB_CARILLO_RANCH + + config FB_INTEL + tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)" +- depends on FB && EXPERIMENTAL && PCI && X86 ++ depends on FB && EXPERIMENTAL && PCI && X86 && !VGA_NOPROBE + select AGP + select AGP_INTEL + select FB_MODE_HELPERS +@@ -1383,7 +1383,7 @@ config FB_SAVAGE_ACCEL + + config FB_SIS + tristate "SiS/XGI display support" +- depends on FB && PCI ++ depends on FB && PCI && !VGA_NOPROBE + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT +@@ -1822,6 +1822,15 @@ config FB_PS3_DEFAULT_SIZE_M + The default value can be overridden on the kernel command line + using the "ps3fb" option (e.g. "ps3fb=9M"); + ++config FB_OLPC_DCON ++ tristate "One Laptop Per Child Display CONtroller support" ++ depends on OLPC ++ select I2C ++ ---help--- ++ Add support for the OLPC DCON controller. This controller is only ++ available on OLPC platforms. Unless you have one of these ++ platforms, you will want to say 'N'. + -+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10); -+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18); -+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20); -+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28); -+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30); -+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50); -+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58); -+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78); -+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80); -+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88); -+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98); -+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0); -+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8); -+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0); -+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8); -+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0); -+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8); -+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0); -+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8); -+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0); -+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8); -+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0); -+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8); -+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100); -+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108); -+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110); -+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118); -+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120); -+ -+ -+ /* FP registers */ -+ -+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400); -+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408); -+ -+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418); -+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420); -+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428); -+ writel(regs->fp.r.fmi, par->vid_regs + 0x430); -+ writel(regs->fp.r.fmd, par->vid_regs + 0x438); -+ writel(regs->fp.r.dca, par->vid_regs + 0x448); -+ writel(regs->fp.r.dmd, par->vid_regs + 0x450); -+ writel(regs->fp.r.crc, par->vid_regs + 0x458); -+ writel(regs->fp.r.fbb, par->vid_regs + 0x460); -+ -+ /* Final enables */ + config FB_XILINX + tristate "Xilinx frame buffer support" + depends on FB && XILINX_VIRTEX +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 06eec7b..fc535fb 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -111,6 +111,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ + obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o + obj-$(CONFIG_FB_PS3) += ps3fb.o + obj-$(CONFIG_FB_SM501) += sm501fb.o ++obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon.o + obj-$(CONFIG_FB_XILINX) += xilinxfb.o + obj-$(CONFIG_FB_OMAP) += omap/ + +diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c +index 0740272..4ac6a95 100644 +--- a/drivers/video/fbmem.c ++++ b/drivers/video/fbmem.c +@@ -820,6 +820,53 @@ static void try_to_load(int fb) + #endif /* CONFIG_KMOD */ + + int ++fb_powerup(struct fb_info *info) ++{ ++ int ret = 0; + -+ val = readl(par->vid_regs + 0x410); ++ if (!info || info->state == FBINFO_STATE_RUNNING) ++ return 0; + -+ /* Control the panel */ -+ if (regs->fp.r.pm & (1 << 24)) { ++ if (info->fbops->fb_powerup) ++ ret = info->fbops->fb_powerup(info); + -+ if (!(val & 0x09)) -+ writel(regs->fp.r.pm, par->vid_regs + 0x410); -+ } -+ else { -+ if (!(val & 0x05)) -+ writel(regs->fp.r.pm, par->vid_regs + 0x410); ++ if (!ret) { ++ acquire_console_sem(); ++ fb_set_suspend(info, 0); ++ release_console_sem(); + } -+ -+ /* Turn everything on */ + -+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04); -+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00); -+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08); -+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08); ++ return ret; +} + ++int ++fb_powerdown(struct fb_info *info) ++{ ++ int ret = 0; + -+#ifdef DEBUG -+ -+void dump_regs(struct fb_info *info, int mode) { -+ -+ struct geodefb_par *par = info->par; -+ u32 val; -+ int i; ++ if (!info || info->state == FBINFO_STATE_SUSPENDED) ++ return 0; + -+ if (mode == 0) { -+ for(i = 0; i < GP_REG_SIZE; i += 4) { -+ val = readl(par->gp_regs + i); -+ } -+ } ++ /* Tell everybody that the fbdev is going down */ ++ acquire_console_sem(); ++ fb_set_suspend(info, 1); ++ release_console_sem(); + -+ if (mode == 1) { -+ writel(0x4758, par->dc_regs + 0x00); ++ if (info->fbops->fb_powerdown) ++ ret = info->fbops->fb_powerdown(info); + -+ for(i = 0; i < DC_REG_SIZE; i += 4) { -+ val = readl(par->dc_regs + i); -+ printk("DC%x: %x\n", i, val); -+ } -+ } ++ /* If the power down failed, then un-notify */ + -+ if (mode == 2) { -+ for(i = 0; i < VP_REG_SIZE; i += 8) { -+ val = readl(par->vid_regs + i); -+ printk("VP%x: %x\n", i, val); -+ } ++ if (ret) { ++ acquire_console_sem(); ++ fb_set_suspend(info, 0); ++ release_console_sem(); + } + -+ if (mode == 3) { -+ for(i = 0; i < FP_REG_SIZE; i += 8) { -+ val = readl(par->vid_regs + 0x400 + i); -+ printk("FP%x: %x\n", i, val); -+ } -+ } ++ return ret; +} + -+#endif -diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c -index 7f3f18d..e282e74 100644 ---- a/drivers/video/geode/video_gx.c -+++ b/drivers/video/geode/video_gx.c -@@ -16,10 +16,14 @@ ++int + fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) + { + struct fb_fix_screeninfo *fix = &info->fix; +diff --git a/drivers/video/geode/Makefile b/drivers/video/geode/Makefile +index 957304b..5c98da1 100644 +--- a/drivers/video/geode/Makefile ++++ b/drivers/video/geode/Makefile +@@ -5,5 +5,5 @@ obj-$(CONFIG_FB_GEODE_GX) += gxfb.o + obj-$(CONFIG_FB_GEODE_LX) += lxfb.o + + gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o +-gxfb-objs := gxfb_core.o display_gx.o video_gx.o ++gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o + lxfb-objs := lxfb_core.o lxfb_ops.o +diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c +index 0f16e4b..a432b99 100644 +--- a/drivers/video/geode/display_gx.c ++++ b/drivers/video/geode/display_gx.c +@@ -11,26 +11,44 @@ + * Free Software Foundation; either version 2 of the License, or * (at your + * option) any later version. + */ ++ ++#include + #include + #include + #include #include + #include #include - #include +#include #include "geodefb.h" - #include "video_gx.h" -+#include "display_gx.h" - -+/* This structure is used to store the saved registers during suspend */ -+static struct geoderegs gx_saved_regs; - - /* - * Tables of register settings for various DOTCLKs. -@@ -58,7 +62,7 @@ static const struct gx_pll_entry gx_pll_table_48MHz[] = { - { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */ - { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */ - { 13333, 0, 0x00000052 }, /* 75.0000 */ -- { 12698, 0, 0x00000056 }, /* 78.7500 */ -+ { 12698, 0, 0x00000056 }, /* 78.7500 */ - { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */ - { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */ - { 10582, 0, 0x000002D2 }, /* 94.5000 */ -@@ -117,8 +121,9 @@ static const struct gx_pll_entry gx_pll_table_14MHz[] = { - { 4357, 0, 0x0000057D }, /* 229.5000 */ - }; + #include "display_gx.h" --static void gx_set_dclk_frequency(struct fb_info *info) -+void gx_set_dclk_frequency(struct fb_info *info) +-#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE +-unsigned int gx_frame_buffer_size(void) ++static inline void rmwl(u32 val, u32 *reg) { -+ struct geodefb_par *par = info->par; - const struct gx_pll_entry *pll_table; - int pll_table_len; - int i, best_i; -@@ -173,115 +178,169 @@ static void gx_set_dclk_frequency(struct fb_info *info) - do { - rdmsrl(MSR_GLCP_DOTPLL, dotpll); - } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); -+ -+ par->curdclk = pll_table[best_i].dotpll_value; +- return CONFIG_FB_GEODE_GX_FBSIZE; ++ u32 in = readl(reg); ++ if (in != val) ++ writel(val, reg); } +-#else ++ + unsigned int gx_frame_buffer_size(void) + { + unsigned int val; --static void --gx_configure_tft(struct fb_info *info) -+/* Find out the current clock - we will use this information to avoid -+ re-programming it if we don't need to */ ++#ifdef CONFIG_OLPC ++ if (machine_is_olpc() && !olpc_has_vsa()) { ++ u32 hi,lo; ++ rdmsr(GLIU0_P2D_RO0, lo, hi); + -+unsigned int gx_get_dclk(struct fb_info *info) ++ /* Top page number */ ++ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); ++ ++ val -= (lo & 0x000fffff); /* Subtract bottom page number */ ++ val += 1; /* Adjust page count */ ++ return (val << 12); ++ } ++#endif ++ + /* FB size is reported by a virtual register */ + /* Virtual register class = 0x02 */ + /* VG_MEM_SIZE(512Kb units) = 0x00 */ +@@ -41,7 +59,6 @@ unsigned int gx_frame_buffer_size(void) + val = (unsigned int)(inw(0xAC1E)) & 0xFFl; + return (val << 19); + } +-#endif + + int gx_line_delta(int xres, int bpp) { -- struct geodefb_par *par = info->par; -- unsigned long val; -- unsigned long fp; -+ const struct gx_pll_entry *pll_table; -+ int pll_table_len; -+ u64 dotpll; -+ int i; +@@ -63,23 +80,23 @@ static void gx_set_mode(struct fb_info *info) + gcfg = readl(par->dc_regs + DC_GENERAL_CFG); + dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); + +- /* Disable the timing generator. */ +- dcfg &= ~(DC_DCFG_TGEN); +- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); ++ /* Programming the clock is costly and ugly, so avoid if if we can */ + +- /* Wait for pending memory requests before disabling the FIFO load. */ +- udelay(100); ++ if (par->curdclk != info->var.pixclock) { ++ /* Disable the timing generator. */ ++ dcfg &= ~(DC_DCFG_TGEN); ++ writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); + +- /* Disable FIFO load and compression. */ +- gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); +- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); ++ /* Wait for pending memory requests before disabling the FIFO load. */ ++ udelay(100); + +- /* Setup DCLK and its divisor. */ +- par->vid_ops->set_dclk(info); ++ /* Disable FIFO load and compression. */ ++ gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); ++ writel(gcfg, par->dc_regs + DC_GENERAL_CFG); -- /* Set up the DF pad select MSR */ -+ if (cpu_data->x86_mask == 1) { -+ pll_table = gx_pll_table_14MHz; -+ pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz); -+ } else { -+ pll_table = gx_pll_table_48MHz; -+ pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz); +- /* +- * Setup new mode. +- */ ++ /* Setup DCLK and its divisor. */ ++ par->vid_ops->set_dclk(info); + } -- rdmsrl(GX_VP_MSR_PAD_SELECT, val); -- val &= ~GX_VP_PAD_SELECT_MASK; -- val |= GX_VP_PAD_SELECT_TFT; -- wrmsrl(GX_VP_MSR_PAD_SELECT, val); -+ rdmsrl(MSR_GLCP_DOTPLL, dotpll); + /* Clear all unused feature bits. */ + gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; +@@ -90,12 +107,13 @@ static void gx_set_mode(struct fb_info *info) + gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; -- /* Turn off the panel */ -+ for(i = 0; i < pll_table_len; i++) { -+ if (pll_table[i].dotpll_value == (u32) (dotpll >> 32)) -+ break; -+ } + /* Framebuffer start offset. */ +- writel(0, par->dc_regs + DC_FB_ST_OFFSET); ++ rmwl(0, par->dc_regs + DC_FB_ST_OFFSET); -- fp = readl(par->vid_regs + GX_FP_PM); -- fp &= ~GX_FP_PM_P; -- writel(fp, par->vid_regs + GX_FP_PM); -+ return (i == pll_table_len) ? 0 : pll_table[i].pixclock; -+} -+ + /* Line delta and line buffer length. */ +- writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); +- writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, +- par->dc_regs + DC_LINE_SIZE); ++ rmwl(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); + -+#define CMP(val, mask, res) (((val) & (mask)) == (res)) ++ rmwl(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, ++ par->dc_regs + DC_LINE_SIZE); -- /* Set timing 1 */ -+static void -+gx_configure_tft(struct fb_info *info) { -- fp = readl(par->vid_regs + GX_FP_PT1); -- fp &= GX_FP_PT1_VSIZE_MASK; -- fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; -- writel(fp, par->vid_regs + GX_FP_PT1); -+ struct geodefb_par *par = info->par; -+ u32 val, fp = 0, fp1, fp2, sync = 0; + /* Enable graphics and video data and unmask address lines. */ +@@ -134,17 +152,16 @@ static void gx_set_mode(struct fb_info *info) + vblankend = vsyncend + info->var.upper_margin; + vtotal = vblankend; -- /* Timing 2 */ -- /* Set bits that are always on for TFT */ -+ /* Set up the DF pad select MSR */ +- writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); +- writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); +- writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); +- +- writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); +- writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); +- writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); ++ rmwl((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); ++ rmwl((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); ++ rmwl((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); ++ rmwl((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); ++ rmwl((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); ++ rmwl((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); -- fp = 0x0F100000; -+ rdmsrl(GX_VP_MSR_PAD_SELECT, val); + /* Write final register values. */ +- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); +- writel(gcfg, par->dc_regs + DC_GENERAL_CFG); ++ rmwl(dcfg, par->dc_regs + DC_DISPLAY_CFG); ++ rmwl(gcfg, par->dc_regs + DC_GENERAL_CFG); -- /* Add sync polarity */ -+ if ((val & GX_VP_PAD_SELECT_MASK) != GX_VP_PAD_SELECT_TFT) { -+ val &= ~GX_VP_PAD_SELECT_MASK; -+ val |= GX_VP_PAD_SELECT_TFT; -+ wrmsrl(GX_VP_MSR_PAD_SELECT, val); -+ } + par->vid_ops->configure_display(info); - if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) -- fp |= GX_FP_PT2_VSP; -+ sync |= GX_FP_PT2_VSP; +diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h +index 0af33f3..d20b877 100644 +--- a/drivers/video/geode/display_gx.h ++++ b/drivers/video/geode/display_gx.h +@@ -20,6 +20,9 @@ extern struct geode_dc_ops gx_dc_ops; + #define GLD_MSR_CONFIG 0xC0002001 + #define GLD_MSR_CONFIG_DM_FP 0x40 - if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) -- fp |= GX_FP_PT2_HSP; -+ sync |= GX_FP_PT2_HSP; ++/* Used for memory dection on the OLPC */ ++#define GLIU0_P2D_RO0 0x10000029 ++ + /* Display controller registers */ -- writel(fp, par->vid_regs + GX_FP_PT2); -+ /* We only need to turn off the panel if something changed */ + #define DC_UNLOCK 0x00 +diff --git a/drivers/video/geode/geodefb.h b/drivers/video/geode/geodefb.h +index ae04820..0214d11 100644 +--- a/drivers/video/geode/geodefb.h ++++ b/drivers/video/geode/geodefb.h +@@ -12,6 +12,10 @@ + #ifndef __GEODEFB_H__ + #define __GEODEFB_H__ -- /* Set the dither control */ -- writel(0x70, par->vid_regs + GX_FP_DFC); -+ fp1 = readl(par->vid_regs + GX_FP_PT1); -+ fp2 = readl(par->vid_regs + GX_FP_PT2); ++#define FB_POWER_STATE_OFF 0 ++#define FB_POWER_STATE_SUSPEND 1 ++#define FB_POWER_STATE_ON 2 + -+ if (!CMP(fp1, GX_FP_PT1_VSIZE_MASK, info->var.yres << GX_FP_PT1_VSIZE_SHIFT) || -+ (fp2 != (0x0F100000 | sync))) { + struct geodefb_info; -- /* Enable the FP data and power (in case the BIOS didn't) */ -+ /* Turn off the panel */ + struct geode_dc_ops { +@@ -21,18 +25,24 @@ struct geode_dc_ops { -- fp = readl(par->vid_regs + GX_DCFG); -- fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN; -- writel(fp, par->vid_regs + GX_DCFG); -+#ifdef NOTUSED -+ /* Do we really need to turn off the panel? */ -+ /* Possibly - we have a glitch somewhere */ + struct geode_vid_ops { + void (*set_dclk)(struct fb_info *); ++ unsigned int (*get_dclk)(struct fb_info *); + void (*configure_display)(struct fb_info *); + int (*blank_display)(struct fb_info *, int blank_mode); + }; -- /* Unblank the panel */ -+ fp = readl(par->vid_regs + GX_FP_PM); -+ fp &= ~GX_FP_PM_P; -+ writel(fp, par->vid_regs + GX_FP_PM); -+#endif + struct geodefb_par { + int enable_crt; ++ int fbactive; /* True if the current console is in KD_GRAPHICS mode */ + int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */ + int panel_y; ++ unsigned int curdclk; /* Used by GX to avoid unnessesary clock switching */ + void __iomem *dc_regs; + void __iomem *vid_regs; ++ void __iomem *gp_regs; + struct geode_dc_ops *dc_ops; + struct geode_vid_ops *vid_ops; + -+ /* Timing 1 */ -+ fp1 &= GX_FP_PT1_VSIZE_MASK; -+ fp1 |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; -+ writel(fp, par->vid_regs + GX_FP_PT1); ++ int state; + }; + + #endif /* !__GEODEFB_H__ */ +diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c +index cf841ef..3eabc53 100644 +--- a/drivers/video/geode/gxfb_core.c ++++ b/drivers/video/geode/gxfb_core.c +@@ -30,12 +30,31 @@ + #include + #include + #include ++#include ++#include ++#include ++#include ++#include + + #include "geodefb.h" + #include "display_gx.h" + #include "video_gx.h" + ++#define FBIOSGAMMA _IOW('F', 0x20, void *) ++#define FBIOGGAMMA _IOW('F', 0x21, void *) + -+ /* Timing 2 */ -+ writel(0x0F100000 | sync, par->vid_regs + GX_FP_PT2); -+ } ++#ifdef DEBUG + -+ /* Set the dither control */ -+ if (readl(par->vid_regs + GX_FP_DFC) != 0x70) { -+ writel(0x70, par->vid_regs + GX_FP_DFC); -+ } ++#define FBIODUMPGP _IOW('F', 0x22, void *) ++#define FBIODUMPDC _IOW('F', 0x23, void *) ++#define FBIODUMPVP _IOW('F', 0x24, void *) ++#define FBIODUMPFP _IOW('F', 0x25, void *) + -+ /* Turn on the panel */ - - fp = readl(par->vid_regs + GX_FP_PM); -- fp |= GX_FP_PM_P; -- writel(fp, par->vid_regs + GX_FP_PM); ++#endif + -+ if (!(fp & 0x09)) -+ writel(fp | GX_FP_PM_P, par->vid_regs + GX_FP_PM); - } + static char *mode_option; ++static int noclear; ++struct fb_info *gxfb_info; -+#define DCFG_DEFAULT_VAL GX_DCFG_CRT_SYNC_SKW_DFLT | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN | \ -+GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN + /* Modes relevant to the GX (taken from modedb.c) */ + static const struct fb_videomode gx_modedb[] __initdata = { +@@ -103,8 +122,20 @@ static const struct fb_videomode gx_modedb[] __initdata = { + { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1200x900-75 - CRT timings for the OLPC mode */ ++ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, ++ 0, FB_VMODE_NONINTERLACED, 0 } + }; + ++#ifdef CONFIG_OLPC ++static const struct fb_videomode gx_dcon_modedb[] __initdata = { ++ /* The only mode the DCON has is 1200x900 */ ++ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, ++ 0, FB_VMODE_NONINTERLACED, 0 } ++}; ++#endif + - static void gx_configure_display(struct fb_info *info) ++ + static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { - struct geodefb_par *par = info->par; -- u32 dcfg, misc; -+ u32 dcfg, misc, sync = 0; - - /* Set up the MISC register */ -- - misc = readl(par->vid_regs + GX_MISC); - -- /* Power up the DAC */ -- misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ /* We leave gamma enabled if it was already enabled. -+ Although the hardware enables it without setting -+ up the gamma table, the BIOS or bootloader ought -+ to have either disabled it or loaded a table by now */ - -- /* Disable gamma correction */ -- misc |= GX_MISC_GAM_EN; - -- writel(misc, par->vid_regs + GX_MISC); + if (var->xres > 1600 || var->yres > 1200) +@@ -137,7 +168,7 @@ static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) + return 0; + } -- /* Write the display configuration */ -- dcfg = readl(par->vid_regs + GX_DCFG); -+ if (par->enable_crt) { -+ /* Power up the CRT DACs */ -+ if (misc & ( GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN)) { -+ misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ writel(misc, par->vid_regs + GX_MISC); -+ } +-static int gxfb_set_par(struct fb_info *info) ++int gxfb_set_par(struct fb_info *info) + { + struct geodefb_par *par = info->par; -- /* Disable hsync and vsync */ -- dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -- writel(dcfg, par->vid_regs + GX_DCFG); -+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) -+ sync |= GX_DCFG_CRT_HSYNC_POL; +@@ -204,16 +235,26 @@ static int gxfb_blank(int blank_mode, struct fb_info *info) + return par->vid_ops->blank_display(info, blank_mode); + } -- /* Clear bits from existing mode. */ -- dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK -- | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL -- | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) -+ sync |= GX_DCFG_CRT_VSYNC_POL; -+ } -+ else { -+ /* Turn off the CRT DACs in FP mode - we don't need them */ -+ if ((misc & (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN))) { -+ misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); -+ writel(misc, par->vid_regs + GX_MISC); -+ } -+ } ++static int fbsize; ++ + static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev) + { + struct geodefb_par *par = info->par; +- int fb_len; + int ret; -- /* Set default sync skew. */ -- dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; -+ /* Write the display configuration */ -+ dcfg = readl(par->vid_regs + GX_DCFG); + ret = pci_enable_device(dev); + if (ret < 0) + return ret; -- /* Enable hsync and vsync. */ -- dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; -+ if (!CMP(dcfg, DCFG_DEFAULT_VAL | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL, -+ DCFG_DEFAULT_VAL | sync)) { ++ ret = pci_request_region(dev, 1, "gxfb (graphics processor)"); ++ if (ret < 0) ++ return ret; ++ ++ par->gp_regs = ioremap(pci_resource_start(dev, 1), ++ pci_resource_len(dev, 1)); ++ if (!par->gp_regs) ++ return -ENOMEM; ++ + ret = pci_request_region(dev, 3, "gxfb (video processor)"); + if (ret < 0) + return ret; +@@ -232,36 +273,118 @@ static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *de + ret = pci_request_region(dev, 0, "gxfb (framebuffer)"); + if (ret < 0) + return ret; +- if ((fb_len = gx_frame_buffer_size()) < 0) +- return -ENOMEM; ++ ++ /* If the fbsize wasn't specified then try to probe it */ ++ ++ if (!fbsize) { ++ fbsize = gx_frame_buffer_size(); ++ if (fbsize == 0) ++ return -ENOMEM; ++ } ++ + info->fix.smem_start = pci_resource_start(dev, 0); +- info->fix.smem_len = fb_len; ++ info->fix.smem_len = fbsize; + info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); + if (!info->screen_base) + return -ENOMEM; -- /* Sync polarities. */ -- if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) -- dcfg |= GX_DCFG_CRT_HSYNC_POL; -- if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) -- dcfg |= GX_DCFG_CRT_VSYNC_POL; -+ /* Disable hsync and vsync */ -+ dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); -+ writel(dcfg, par->vid_regs + GX_DCFG); +- /* Set the 16MB aligned base address of the graphics memory region ++ /* Set the 16MiB aligned base address of the graphics memory region + * in the display controller */ -- /* Enable the display logic */ -- /* Set up the DACS to blank normally */ -+ /* Clear bits from existing mode. */ -+ dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK -+ | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL -+ | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); + writel(info->fix.smem_start & 0xFF000000, + par->dc_regs + DC_GLIU0_MEM_OFFSET); -- dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; -+ /* Set default sync skew. */ -+ dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; +- dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n", ++ dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n", + info->fix.smem_len / 1024, info->fix.smem_start); -- /* Enable the external DAC VREF? */ -+ /* Enable hsync and vsync. */ -+ dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; + return 0; + } -- writel(dcfg, par->vid_regs + GX_DCFG); -+ /* Enable the display logic */ -+ dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; ++static int gxfb_ioctl( struct fb_info *info, unsigned int cmd, ++ unsigned long arg) ++{ ++ unsigned int gamma[GXFB_GAMMA_DWORDS]; ++ int ret = -EINVAL; ++ struct geodefb_par *par = info->par; ++ int i; + -+ writel(dcfg, par->vid_regs + GX_DCFG); ++ switch(cmd) { ++ case FBIOSGAMMA: ++ /* Read the gamma information from the user - 256 dwords */ ++ ++ if (copy_from_user(gamma, (void * __user) arg, GXFB_GAMMA_SIZE)) ++ return -EFAULT; ++ ++ writel(0, par->vid_regs + GX_GAR); ++ ++ /* Sequential writes to the data register will increment the ++ address automatically */ ++ ++ for(i = 0; i < GXFB_GAMMA_DWORDS; i++) ++ writel(gamma[i] & 0xFFFFFF, par->vid_regs + GX_GDR); ++ ++ writel(readl(par->vid_regs + GX_MISC) & ~GX_MISC_GAM_EN, ++ par->vid_regs + GX_MISC); ++ ++ ret = 0; ++ break; ++ ++ case FBIOGGAMMA: ++ if (readl(par->vid_regs + GX_MISC) & GX_MISC_GAM_EN) ++ return -EINVAL; ++ ++ memset(gamma, 0, GXFB_GAMMA_SIZE); ++ writel(0, par->vid_regs + GX_GAR); ++ ++ for(i = 0; i < GXFB_GAMMA_DWORDS;i++) ++ gamma[i] = readl(par->vid_regs + GX_GDR); ++ ++ if (copy_to_user((void * __user) arg, gamma, GXFB_GAMMA_SIZE)) ++ ret = -EFAULT; ++ else ++ ret = 0; ++ ++ break; ++ ++#ifdef DEBUG ++ case FBIODUMPGP: ++ ret = 0; ++ dump_regs(info, 0); ++ break; ++ ++ case FBIODUMPDC: ++ ret = 0; ++ dump_regs(info, 1); ++ break; ++ ++ case FBIODUMPVP: ++ ret = 0; ++ dump_regs(info, 2); ++ break; ++ ++ case FBIODUMPFP: ++ ret = 0; ++ dump_regs(info, 3); ++ break; ++#endif + } ++ ++ return ret; ++} ++ + static struct fb_ops gxfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = gxfb_check_var, + .fb_set_par = gxfb_set_par, + .fb_setcolreg = gxfb_setcolreg, + .fb_blank = gxfb_blank, ++ .fb_ioctl = gxfb_ioctl, + /* No HW acceleration for now. */ + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, ++ .fb_powerdown = gxfb_powerdown, ++ .fb_powerup = gxfb_powerup, + }; - /* Set up the flat panel (if it is enabled) */ - -@@ -289,6 +348,100 @@ static void gx_configure_display(struct fb_info *info) - gx_configure_tft(info); + static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) +@@ -303,23 +426,86 @@ static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) + return info; } -+int gxfb_powerdown(struct fb_info *info) +-static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) ++static int gxfb_console_notify(struct notifier_block *self, ++ unsigned long action, void *data) ++{ ++ if (gxfb_info != NULL) { ++ struct geodefb_par *par = gxfb_info->par; ++ par->fbactive = (action == CONSOLE_EVENT_SWITCH_TEXT) ? 0 : 1; ++ } ++ ++ return NOTIFY_OK; ++} ++ ++static struct notifier_block gxfb_console_notifier = { ++ .notifier_call = gxfb_console_notify ++}; ++ ++#ifdef CONFIG_PM ++ ++static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state) +{ ++ struct fb_info *info = pci_get_drvdata(pdev); + struct geodefb_par *par = info->par; + -+ /* We're already suspended */ ++ if (pdev->dev.power.power_state.event == state.event) ++ return 0; ++ ++ if (state.event == PM_EVENT_SUSPEND) { ++ ++ acquire_console_sem(); ++ gxfb_powerdown(info); ++ ++ par->state = FB_POWER_STATE_OFF; ++ fb_set_suspend(info, 1); ++ ++ release_console_sem(); ++ } ++ ++ pdev->dev.power.power_state = state; ++ return 0; ++} ++ ++static int gxfb_resume(struct pci_dev *pdev) ++{ ++ struct fb_info *info = pci_get_drvdata(pdev); ++ ++ acquire_console_sem(); ++ ++ /* Turn the engine completely on */ ++ ++ if (gxfb_powerup(info)) ++ printk(KERN_ERR "gxfb: Powerup failed\n"); + -+ if (par->state != FB_POWER_STATE_ON) -+ return 0; ++ fb_set_suspend(info, 0); ++ release_console_sem(); + -+ /* Save the registers */ -+ gx_save_regs(info, &gx_saved_regs); ++ pdev->dev.power.power_state = PMSG_ON; ++ return 0; ++} ++#endif + -+ /* Shut down the engine */ ++static int __init gxfb_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id) + { + struct geodefb_par *par; +- struct fb_info *info; + int ret; + unsigned long val; + +- info = gxfb_init_fbinfo(&pdev->dev); +- if (!info) ++ struct fb_videomode *modedb_ptr; ++ int modedb_size; + -+ writel(gx_saved_regs.vp.r.vcfg & ~0x01, par->vid_regs + GX_VCFG); -+ writel(gx_saved_regs.vp.r.dcfg & ~0x0F, par->vid_regs + GX_DCFG); ++ gxfb_info = gxfb_init_fbinfo(&pdev->dev); ++ if (gxfb_info == NULL) + return -ENOMEM; +- par = info->par; + -+ /* Turn off the flat panel unless we are attached to a DCON */ -+ if (!olpc_has_dcon()) -+ writel(gx_saved_regs.fp.r.pm & ~GX_FP_PM_P, par->vid_regs + GX_FP_PM); ++ par = gxfb_info->par; + + /* GX display controller and GX video device. */ + par->dc_ops = &gx_dc_ops; + par->vid_ops = &gx_vid_ops; + +- if ((ret = gxfb_map_video_memory(info, pdev)) < 0) { ++ if ((ret = gxfb_map_video_memory(gxfb_info, pdev)) < 0) { + dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n"); + goto err; + } +@@ -333,32 +519,60 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i + else + par->enable_crt = 1; + +- ret = fb_find_mode(&info->var, info, mode_option, +- gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16); ++ /* Get the current dotclock */ + -+ writel(0x4758, par->dc_regs + DC_UNLOCK); ++ par->curdclk = (par->vid_ops->get_dclk) ? par->vid_ops->get_dclk(gxfb_info) : 0; + -+ writel(gx_saved_regs.dc.r.gcfg & ~0x0F, -+ par->dc_regs + DC_GENERAL_CFG); ++ /* We need to determine a display mode right now, so we will ++ * check to see if the DCON was previously detected by the BIOS ++ * and use that to make our mode database decision. ++ */ + -+ writel(gx_saved_regs.dc.r.dcfg & ~0x19, -+ par->dc_regs + DC_DISPLAY_CFG); -+ -+ par->state = FB_POWER_STATE_SUSPEND; ++ modedb_ptr = (struct fb_videomode *) gx_modedb; ++ modedb_size = ARRAY_SIZE(gx_modedb); + -+ return 0; -+} ++#ifdef CONFIG_OLPC ++ if (olpc_has_dcon()) { ++ modedb_ptr = (struct fb_videomode *) gx_dcon_modedb; ++ modedb_size = ARRAY_SIZE(gx_dcon_modedb); ++ } ++#endif + -+int gxfb_powerup(struct fb_info *info) -+{ -+ struct geodefb_par *par = info->par; -+ u32 val; ++ ret = fb_find_mode(&gxfb_info->var, gxfb_info, mode_option, ++ modedb_ptr, modedb_size, NULL, 16); + -+ if (par->state == FB_POWER_STATE_SUSPEND) { + if (ret == 0 || ret == 4) { + dev_err(&pdev->dev, "could not find valid video mode\n"); + ret = -EINVAL; + goto err; + } + ++ /* Clear the screen of garbage, unless noclear was specified, ++ * in which case we assume the user knows what he is doing */ + -+ writel(gx_saved_regs.dc.r.dcfg, -+ par->dc_regs + DC_DISPLAY_CFG); ++ if (!noclear) ++ memset_io(gxfb_info->screen_base, 0, gxfb_info->fix.smem_len); + -+ writel(gx_saved_regs.vp.r.vcfg, par->vid_regs + GX_VCFG); -+ writel(gx_saved_regs.vp.r.dcfg, par->vid_regs + GX_DCFG); ++ gxfb_check_var(&gxfb_info->var, gxfb_info); ++ gxfb_set_par(gxfb_info); + -+ val = readl(par->vid_regs + GX_FP_PM); ++ /* We are powered up */ ++ par->state = FB_POWER_STATE_ON; + +- /* Clear the frame buffer of garbage. */ +- memset_io(info->screen_base, 0, info->fix.smem_len); + +- gxfb_check_var(&info->var, info); +- gxfb_set_par(info); ++ console_event_register(&gxfb_console_notifier); + +- if (register_framebuffer(info) < 0) { ++ if (register_framebuffer(gxfb_info) < 0) { + ret = -EINVAL; + goto err; + } +- pci_set_drvdata(pdev, info); +- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); ++ pci_set_drvdata(pdev, gxfb_info); ++ printk(KERN_INFO "fb%d: %s frame buffer device\n", gxfb_info->node, gxfb_info->fix.id); + return 0; + + err: +- if (info->screen_base) { +- iounmap(info->screen_base); ++ if (gxfb_info->screen_base) { ++ iounmap(gxfb_info->screen_base); + pci_release_region(pdev, 0); + } + if (par->vid_regs) { +@@ -370,8 +584,9 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i + pci_release_region(pdev, 2); + } + +- if (info) +- framebuffer_release(info); ++ if (gxfb_info) ++ framebuffer_release(gxfb_info); + -+ /* power up the panel if it needs it; we don't always power it down */ -+ if (!(val & 0x09)) { -+ writel(gx_saved_regs.fp.r.pm, par->vid_regs + GX_FP_PM); -+ mdelay(64); -+ } -+ } + return ret; + } + +@@ -397,9 +612,7 @@ static void gxfb_remove(struct pci_dev *pdev) + } + + static struct pci_device_id gxfb_id_table[] = { +- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO, +- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, +- 0xff0000, 0 }, ++ { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) }, + { 0, } + }; + +@@ -410,22 +623,30 @@ static struct pci_driver gxfb_driver = { + .id_table = gxfb_id_table, + .probe = gxfb_probe, + .remove = gxfb_remove, ++#ifdef CONFIG_PM ++ .suspend = gxfb_suspend, ++ .resume = gxfb_resume ++#endif + }; + + #ifndef MODULE +-static int __init gxfb_setup(char *options) +-{ ++static int __init gxfb_setup(char *options) { + + char *opt; + + if (!options || !*options) + return 0; + +- while ((opt = strsep(&options, ",")) != NULL) { ++ while((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + +- mode_option = opt; ++ if (!strncmp(opt, "fbsize:", 7)) ++ fbsize = simple_strtoul(opt+7, NULL, 0); ++ else if (!strcmp(opt, "noclear")) ++ noclear = 1; ++ else ++ mode_option = opt; + } + + return 0; +@@ -444,7 +665,6 @@ static int __init gxfb_init(void) + #endif + return pci_register_driver(&gxfb_driver); + } +- + static void __exit gxfb_cleanup(void) + { + pci_unregister_driver(&gxfb_driver); +@@ -456,5 +676,8 @@ module_exit(gxfb_cleanup); + module_param(mode_option, charp, 0); + MODULE_PARM_DESC(mode_option, "video mode (x[-][@])"); + ++module_param(fbsize, int, 0); ++MODULE_PARM_DESC(fbsize, "video memory size"); + -+ /* If the panel is currently on its way up, then wait up to 100ms -+ for it */ -+ -+ if (readl(par->vid_regs + GX_FP_PM) & 0x08) { -+ int i; -+ -+ for(i = 0; i < 10; i++) { -+ if (readl(par->vid_regs + GX_FP_PM) & 0x01) -+ break; + MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX"); + MODULE_LICENSE("GPL"); +diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h +index 6c227f9..5be8a4d 100644 +--- a/drivers/video/geode/lxfb.h ++++ b/drivers/video/geode/lxfb.h +@@ -25,10 +25,23 @@ void lx_set_mode(struct fb_info *); + void lx_get_gamma(struct fb_info *, unsigned int *, int); + void lx_set_gamma(struct fb_info *, unsigned int *, int); + unsigned int lx_framebuffer_size(void); ++int lx_shutdown(struct fb_info *); ++int lx_powerup(struct fb_info *); + int lx_blank_display(struct fb_info *, int); + void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, + unsigned int, unsigned int); + + -+ mdelay(10); -+ } + -+ if (i == 10) -+ printk(KERN_ERR "gxfb: Panel power up timed out\n"); -+ } ++/* ioctl() defines */ + -+ if (par->state == FB_POWER_STATE_ON) -+ return 0; -+ -+ switch(par->state) { -+ case FB_POWER_STATE_OFF: -+ gx_restore_regs(info, &gx_saved_regs); -+ break; ++#define FBIOSGAMMA _IOW('F', 0x20, void *) ++#define FBIOGGAMMA _IOW('F', 0x21, void *) + -+ case FB_POWER_STATE_SUSPEND: -+ /* Do this because it will turn on the FIFO which will -+ start the line count */ -+ writel(gx_saved_regs.dc.r.gcfg, -+ par->dc_regs + DC_GENERAL_CFG); -+ writel(0x0, par->dc_regs + DC_UNLOCK); -+ break; -+ } ++/* General definitions */ ++#define LXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ ++#define LXFB_GAMMA_SIZE (LXFB_GAMMA_DWORDS * sizeof(unsigned int)) + -+ par->state = FB_POWER_STATE_ON; -+ return 0; -+} + /* MSRS */ + + #define MSR_LX_GLD_CONFIG 0x48002001 +diff --git a/drivers/video/geode/lxfb_core.c b/drivers/video/geode/lxfb_core.c +index 5e30b40..c9060ed 100644 +--- a/drivers/video/geode/lxfb_core.c ++++ b/drivers/video/geode/lxfb_core.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + + #include "lxfb.h" + +@@ -35,186 +36,84 @@ static int fbsize; + */ + + const struct fb_videomode geode_modedb[] __initdata = { +- /* 640x480-60 */ +- { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2, ++ /* 640x480-60 VESA */ ++ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, ++ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 640x480-75 VESA */ ++ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, ++ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 640x480-85 VESA */ ++ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, ++ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 800x600-60 VESA */ ++ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 640x400-70 */ +- { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2, +- FB_SYNC_HOR_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-70 */ +- { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-72 */ +- { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 800x600-75 VESA */ ++ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-75 */ +- { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 800x600-85 VESA */ ++ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-85 */ +- { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1024x768-60 VESA */ ++ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, ++ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1024x768-75 VESA */ ++ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-90 */ +- { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-100 */ +- { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 640x480-60 */ +- { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1024x768-85 VESA */ ++ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-56 */ +- { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-60 */ +- { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-70 */ +- { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-72 */ +- { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-75 */ +- { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-85 */ +- { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-90 */ +- { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-100 */ +- { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 800x600-60 */ +- { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1280x960-60 VESA */ ++ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-60 */ +- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1280x960-85 VESA */ ++ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-70 */ +- { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1280x1024-60 VESA */ ++ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-72 */ +- { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-75 */ +- { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-85 */ +- { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-90 */ +- { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-100 */ +- { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1024x768-60 */ +- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1280x1024-75 VESA */ ++ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-60 */ +- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-70 */ +- { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-72 */ +- { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-75 */ +- { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-85 */ +- { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-90 */ +- { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-100 */ +- { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1152x864-60 */ +- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1280x1024-85 VESA */ ++ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-60 */ +- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-70 */ +- { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-72 */ +- { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-75 */ +- { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-85 */ +- { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-90 */ +- { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-100 */ +- { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1280x1024-60 */ +- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, +- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-60 */ ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1600x1200-60 VESA */ + { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-70 */ +- { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-72 */ +- { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-75 */ ++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1600x1200-75 VESA */ + { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-85 */ ++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1600x1200-85 VESA */ + { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-90 */ +- { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-100 */ +- { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1600x1200-60 */ +- { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +- FB_VMODE_NONINTERLACED, 0 }, +- /* 1920x1440-60 */ +- { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1920x1440-70 */ +- { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1920x1440-72 */ +- { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1920x1440-75 */ +- { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, +- /* 1920x1440-85 */ +- { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3, +- 0, FB_VMODE_NONINTERLACED, 0 }, ++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, ++ /* 1200x900-75 - CRT timings for the OLPC mode */ ++ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3, ++ 0, FB_VMODE_NONINTERLACED, 0 } + }; + ++#ifdef CONFIG_OLPC ++const struct fb_videomode olpc_dcon_modedb[] __initdata = { ++ /* The only mode the DCON has is 1200x900 */ ++ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, ++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ FB_VMODE_NONINTERLACED, 0 } ++}; ++#endif + - static int gx_blank_display(struct fb_info *info, int blank_mode) + static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { - struct geodefb_par *par = info->par; -@@ -315,6 +468,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) - default: - return -EINVAL; - } -+ - dcfg = readl(par->vid_regs + GX_DCFG); - dcfg &= ~(GX_DCFG_DAC_BL_EN - | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); -@@ -326,7 +480,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) - dcfg |= GX_DCFG_VSYNC_EN; - writel(dcfg, par->vid_regs + GX_DCFG); - -- /* Power on/off flat panel. */ -+ /* Power on/off flat panel */ - - if (par->enable_crt == 0) { - fp_pm = readl(par->vid_regs + GX_FP_PM); -@@ -340,8 +494,37 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) + if (var->xres > 1920 || var->yres > 1440) +@@ -379,16 +278,55 @@ static int __init lxfb_map_video_memory(struct fb_info *info, return 0; } -+extern struct fb_info *gxfb_info; -+ -+/* This function controls the flatpanel power sequencing - this is used -+ by the OLPC power management engine to enable the FP sequencing much -+ earlier in the resume process -+*/ -+ -+void gxfb_flatpanel_control(int state) -+{ -+ struct geodefb_par *par = gxfb_info->par; -+ u32 val, fp = readl(par->vid_regs + GX_FP_PM); -+ val = fp; -+ -+ /* Turn on the panel if it isn't aleady */ -+ -+ if (state) { -+ if (!(val & 0x01)) -+ val |= GX_FP_PM_P; -+ } -+ else { -+ if (!(val & 0x02)) -+ val &= ~GX_FP_PM_P; -+ } -+ -+ if (val != fp) -+ writel(val, par->vid_regs + GX_FP_PM); -+} -+ - struct geode_vid_ops gx_vid_ops = { - .set_dclk = gx_set_dclk_frequency, -+ .get_dclk = gx_get_dclk, - .configure_display = gx_configure_display, - .blank_display = gx_blank_display, - }; -diff --git a/drivers/video/geode/video_gx.h b/drivers/video/geode/video_gx.h -index ce28d8f..c57b36b 100644 ---- a/drivers/video/geode/video_gx.h -+++ b/drivers/video/geode/video_gx.h -@@ -11,6 +11,8 @@ - #ifndef __VIDEO_GX_H__ - #define __VIDEO_GX_H__ - -+#include "geode_regs.h" -+ - extern struct geode_vid_ops gx_vid_ops; - - /* GX Flatpanel control MSR */ -@@ -20,6 +22,8 @@ extern struct geode_vid_ops gx_vid_ops; - - /* Geode GX video processor registers */ - -+#define GX_VCFG 0x0000 -+ - #define GX_DCFG 0x0008 - # define GX_DCFG_CRT_EN 0x00000001 - # define GX_DCFG_HSYNC_EN 0x00000002 -@@ -42,6 +46,14 @@ extern struct geode_vid_ops gx_vid_ops; - #define GX_MISC_DAC_PWRDN 0x00000400 - #define GX_MISC_A_PWRDN 0x00000800 - -+/* Gamma correction RAM - address and data registers */ -+ -+#define GX_GAR 0x038 -+#define GX_GDR 0x040 -+ -+#define GXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ -+#define GXFB_GAMMA_SIZE (GXFB_GAMMA_DWORDS * sizeof(unsigned int)) -+ - /* Geode GX flat panel display control registers */ - - #define GX_FP_PT1 0x0400 -@@ -69,4 +81,13 @@ extern struct geode_vid_ops gx_vid_ops; - # define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull) - # define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull) - -+int gxfb_powerdown(struct fb_info *info); -+int gxfb_powerup(struct fb_info *info); -+ -+void gx_set_dclk_frequency(struct fb_info *info); -+unsigned int gx_get_dclk(struct fb_info *info); -+ -+void gx_save_regs(struct fb_info *info, struct geoderegs *regs); -+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs); -+ - #endif /* !__VIDEO_GX_H__ */ -diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c -index 3741ad7..49f6db5 100644 ---- a/drivers/video/modedb.c -+++ b/drivers/video/modedb.c -@@ -33,6 +33,8 @@ const char *global_mode_option; - * Standard video mode definitions (taken from XFree86) - */ - -+#define DEFAULT_MODEDB_INDEX 0 -+ - static const struct fb_videomode modedb[] = { - { - /* 640x400 @ 70 Hz, 31.5 kHz hsync */ -@@ -504,7 +506,8 @@ int fb_find_mode(struct fb_var_screeninfo *var, - } - - if (!default_mode) -- default_mode = &db[0]; -+ default_mode = (db == modedb) ? -+ &modedb[DEFAULT_MODEDB_INDEX] : &db[0]; - - if (!default_bpp) - default_bpp = 8; -diff --git a/drivers/video/olpc_dcon.c b/drivers/video/olpc_dcon.c -new file mode 100644 -index 0000000..d4ef138 ---- /dev/null -+++ b/drivers/video/olpc_dcon.c -@@ -0,0 +1,824 @@ -+/* -+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse -+ * -+ * Copyright © 2006-2007 Red Hat, Inc. -+ * Copyright © 2006-2007 Advanced Micro Devices, Inc. -+ * -+ * This program is free software. You can redistribute it and/or -+ * modify it under the terms of version 2 of the GNU General Public -+ * License as published by the Free Software Foundation. -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "olpc_dcon.h" -+ -+/* Module definitions */ -+ -+static int resumeline = 898; -+module_param(resumeline, int, 0444); -+ -+static int noinit; -+module_param(noinit, int, 0444); -+ -+/* Default off since it doesn't work on DCON ASIC in B-test OLPC board */ -+static int useaa = 1; -+module_param(useaa, int, 0444); -+ -+/* I2C structures */ -+ -+static struct i2c_driver dcon_driver; -+static struct i2c_client *dcon_client; -+ -+/* Platform devices */ -+static struct platform_device *dcon_device; -+ -+/* Backlight device */ -+static struct backlight_device *dcon_bl_dev; -+ -+/* Base address of the GPIO registers */ -+static unsigned long gpio_base; -+ -+static struct fb_info *fbinfo; -+ -+/* Current source, initialized at probe time */ -+static int dcon_source; -+ -+/* Desired source */ -+static int dcon_pending; -+ -+/* Current output type */ -+static int dcon_output = DCON_OUTPUT_COLOR; -+ -+/* Current sleep status (not yet implemented) */ -+static int dcon_sleep_val = DCON_ACTIVE; -+ -+/* Shadow register for the DCON_REG_MODE register */ -+static unsigned short dcon_disp_mode; -+ -+/* Variables used during switches */ -+static int dcon_switched; -+ -+static DECLARE_WAIT_QUEUE_HEAD(dcon_wait_queue); -+ -+static unsigned short normal_i2c[] = { 0x0D, I2C_CLIENT_END }; -+I2C_CLIENT_INSMOD; -+ -+#define dcon_write(reg,val) i2c_smbus_write_word_data(dcon_client,reg,val) -+#define dcon_read(reg) i2c_smbus_read_word_data(dcon_client,reg) -+ -+/* The current backlight value - this saves us some smbus traffic */ -+static int bl_val = -1; -+ -+/* ===== API functions - these are called by a variety of users ==== */ -+ -+/* Backlight notes - turning off the backlight enable bit in the DCON -+ * doesn't save us any power over just pushing the BL to zero, so we -+ * don't use that bit in this code. -+ */ -+ -+static int dcon_get_backlight(void) -+{ -+ if (dcon_client == NULL) -+ return 0; -+ -+ if (bl_val == -1) -+ bl_val = dcon_read(DCON_REG_BRIGHT) & 0x0F; -+ -+ return bl_val; -+} -+ -+static void dcon_set_backlight(int level) ++static int lxfb_set_gamma(struct fb_info *info, void * __user data) +{ -+ if (dcon_client == NULL) -+ return; -+ -+ if (bl_val == (level & 0x0F)) -+ return; -+ -+ bl_val = level & 0x0F; -+ dcon_write(DCON_REG_BRIGHT, bl_val); ++ unsigned int gamma[LXFB_GAMMA_DWORDS]; + -+ /* Purposely turn off the backlight when we go to level 0 */ ++ if (copy_from_user(gamma, data, LXFB_GAMMA_SIZE)) ++ return -EFAULT; + -+ if (bl_val == 0) { -+ dcon_disp_mode &= ~MODE_BL_ENABLE; -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ } -+ else if (!(dcon_disp_mode & MODE_BL_ENABLE)) { -+ dcon_disp_mode |= MODE_BL_ENABLE; -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ } ++ lx_set_gamma(info, gamma, LXFB_GAMMA_SIZE); ++ return 0; +} + -+/* Set the output type to either color or mono */ -+ -+static int dcon_set_output(int arg) ++static int lxfb_get_gamma(struct fb_info *info, void * __user data) +{ -+ if (dcon_output == arg) -+ return 0; -+ -+ dcon_output = arg; ++ unsigned int gamma[LXFB_GAMMA_DWORDS]; ++ memset(gamma, 0, sizeof(gamma)); + -+ if (arg == DCON_OUTPUT_MONO) { -+ dcon_disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA); -+ dcon_disp_mode |= MODE_MONO_LUMA; -+ } -+ else { -+ dcon_disp_mode &= ~(MODE_MONO_LUMA); -+ dcon_disp_mode |= MODE_CSWIZZLE; -+ if (useaa) -+ dcon_disp_mode |= MODE_COL_AA; -+ } ++ lx_get_gamma(info, gamma, LXFB_GAMMA_DWORDS); + -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ return 0; ++ return copy_to_user(data, gamma, LXFB_GAMMA_SIZE) ? ++ -EFAULT : 0; +} + -+/* For now, this will be really stupid - we need to address how -+ * DCONLOAD works in a sleep and account for it accordingly -+ */ -+ -+static void dcon_sleep(int state) ++static int lxfb_ioctl( struct fb_info *info, unsigned int cmd, ++ unsigned long arg) +{ -+ /* Turn off the backlight and put the DCON to sleep */ -+ -+ if (state == dcon_sleep_val) -+ return; -+ -+ if (state == DCON_SLEEP) { -+ dcon_disp_mode &= ~MODE_BL_ENABLE; -+ dcon_disp_mode |= MODE_SLEEP; -+ } -+ else { -+ /* Only re-enable the backlight if the backlight value is set */ -+ -+ if (bl_val != 0) -+ dcon_disp_mode |= MODE_BL_ENABLE; ++ switch(cmd) { ++ case FBIOSGAMMA: ++ return lxfb_set_gamma(info, (void * __user) arg); + -+ dcon_disp_mode &= ~MODE_SLEEP; ++ case FBIOGGAMMA: ++ return lxfb_get_gamma(info, (void * __user) arg); + } + -+ dcon_sleep_val = state; -+ dcon_write(DCON_REG_MODE, dcon_disp_mode); -+ -+ /* We should turn off some stuff in the framebuffer - but what? */ ++ return -ENOTTY; +} + -+/* Set the source of the display (CPU or DCON) */ + static struct fb_ops lxfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = lxfb_check_var, + .fb_set_par = lxfb_set_par, + .fb_setcolreg = lxfb_setcolreg, + .fb_blank = lxfb_blank, ++ .fb_ioctl = lxfb_ioctl, + /* No HW acceleration for now. */ + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, ++ .fb_powerdown = lx_shutdown, ++ .fb_powerup = lx_powerup, + }; + + static struct fb_info * __init lxfb_init_fbinfo(struct device *dev) +@@ -431,6 +369,45 @@ static struct fb_info * __init lxfb_init_fbinfo(struct device *dev) + return info; + } + ++#ifdef CONFIG_PM + -+static void dcon_source_switch(struct work_struct *work) ++static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state) +{ -+ DECLARE_WAITQUEUE(wait, current); -+ int source = dcon_pending; -+ -+ if (dcon_source == source) -+ return; -+ -+ dcon_switched = 0; -+ -+ switch (source) { -+ case DCON_SOURCE_CPU: -+ -+ /* Enable the scanline interrupt bit */ -+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode | MODE_SCAN_INT)) -+ printk(KERN_ERR "olpc-dcon: couldn't enable scanline interrupt!\n"); -+ else { -+ /* Wait up to one second for the scanline interrupt */ -+ wait_event_timeout(dcon_wait_queue, dcon_switched == 1, HZ); -+ } -+ -+ if (!dcon_switched) -+ printk(KERN_ERR "olpc-dcon: Timeout entering CPU mode; expect a screen glitch.\n"); -+ -+ /* -+ * Ideally we'd like to disable interrupts here so that the -+ * fb_powerup and DCON turn on happen at a known time value; -+ * however, we can't do that right now with fb_set_suspend -+ * messing with semaphores. -+ * -+ * For now, we just hope.. -+ */ -+ if (fb_powerup(fbinfo)) { -+ printk(KERN_ERR "olpc-dcon: Failed to enter CPU mode\n"); -+ dcon_pending = DCON_SOURCE_DCON; -+ return; -+ } -+ -+ /* And turn off the DCON */ -+ outl(1<<11, gpio_base + GPIOx_OUT_VAL); -+ -+ /* Turn off the scanline interrupt */ -+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode)) -+ printk(KERN_ERR "olpc-dcon: couldn't disable scanline interrupt!\n"); ++ struct fb_info *info = pci_get_drvdata(pdev); + -+ printk(KERN_INFO "olpc-dcon: The CPU has control\n"); -+ break; -+ case DCON_SOURCE_DCON: -+ { -+ int t; ++ if (pdev->dev.power.power_state.event == state.event) ++ return 0; + -+ add_wait_queue(&dcon_wait_queue, &wait); -+ set_current_state(TASK_UNINTERRUPTIBLE); ++ if (state.event == PM_EVENT_SUSPEND) { + -+ /* Clear GPIO11 (DCONLOAD) - this implies that the DCON is in -+ control */ ++ acquire_console_sem(); ++ lx_shutdown(info); ++ fb_set_suspend(info, 1); ++ release_console_sem(); ++ } + -+ outl(1 << (11 + 16), gpio_base + GPIOx_OUT_VAL); ++ pdev->dev.power.power_state = state; ++ return 0; ++} + -+ t = schedule_timeout(HZ/2); -+ remove_wait_queue(&dcon_wait_queue, &wait); -+ set_current_state(TASK_RUNNING); ++static int lxfb_resume(struct pci_dev *pdev) ++{ ++ struct fb_info *info = pci_get_drvdata(pdev); + -+ if (!dcon_switched) -+ printk(KERN_ERR "olpc-dcon: Timeout entering DCON mode; expect a screen glitch.\n"); ++ acquire_console_sem(); + -+ /* Turn off the graphics engine completely */ -+ fb_powerdown(fbinfo); ++ /* Turn the engine completely on */ + -+ printk(KERN_INFO "olpc-dcon: The DCON has control\n"); -+ break; -+ } -+ default: -+ BUG(); -+ } ++ lx_powerup(info); ++ fb_set_suspend(info, 0); ++ release_console_sem(); + -+ dcon_source = source; ++ pdev->dev.power.power_state = PMSG_ON; ++ return 0; +} + -+static DECLARE_WORK(dcon_work, dcon_source_switch); ++#endif + -+static int dcon_set_source(int arg) -+{ -+ if (arg != DCON_SOURCE_CPU && arg != DCON_SOURCE_DCON) -+ return -EINVAL; + static int __init lxfb_probe(struct pci_dev *pdev, + const struct pci_device_id *id) + { +@@ -467,6 +444,13 @@ static int __init lxfb_probe(struct pci_dev *pdev, + modedb_ptr = (struct fb_videomode *) geode_modedb; + modedb_size = ARRAY_SIZE(geode_modedb); + ++#ifdef CONFIG_OLPC ++ if (olpc_has_dcon()) { ++ modedb_ptr = (struct fb_videomode *) olpc_dcon_modedb; ++ modedb_size = ARRAY_SIZE(olpc_dcon_modedb); ++ } ++#endif + -+ if (dcon_pending == arg) -+ return 0; + ret = fb_find_mode(&info->var, info, mode_option, + modedb_ptr, modedb_size, NULL, 16); + +@@ -556,6 +540,10 @@ static struct pci_driver lxfb_driver = { + .id_table = lxfb_id_table, + .probe = lxfb_probe, + .remove = lxfb_remove, ++#ifdef CONFIG_PM ++ .suspend = lxfb_suspend, ++ .resume = lxfb_resume ++#endif + }; + + #ifndef MODULE +diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c +index 4fbc99b..47ed9de 100644 +--- a/drivers/video/geode/lxfb_ops.c ++++ b/drivers/video/geode/lxfb_ops.c +@@ -13,9 +13,13 @@ + #include + #include + #include ++#include + + #include "lxfb.h" + ++#define _GEODELX_ ++#include "geode_regs.h" + -+ dcon_pending = arg; -+ if ((dcon_source != arg) && !work_pending(&dcon_work)) -+ schedule_work(&dcon_work); + /* TODO + * Support panel scaling + * Add acceleration +@@ -290,6 +294,19 @@ unsigned int lx_framebuffer_size(void) + { + unsigned int val; + ++#ifdef CONFIG_OLPC ++ if (machine_is_olpc() && !olpc_has_vsa()) { ++ u32 hi,lo; ++ rdmsr(MSR_LX_GLIU0_P2D_RO0, lo, hi); + -+ return 0; -+} ++ /* Top page number */ ++ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); ++ val -= (lo & 0x000fffff); /* Subtract bottom page number */ ++ val += 1; /* Adjust page count */ ++ return (val << 12); ++ } ++#endif + -+static int dcon_set_source_sync(int arg) + /* The frame buffer size is reported by a VSM in VSA II */ + /* Virtual Register Class = 0x02 */ + /* VG_MEM_SIZE (1MB units) = 0x00 */ +@@ -301,6 +318,34 @@ unsigned int lx_framebuffer_size(void) + return (val << 20); + } + ++void lx_set_gamma(struct fb_info *info, unsigned int *gamma, int len) +{ -+ int ret = dcon_set_source(arg); -+ if (!ret) -+ flush_scheduled_work(); -+ return ret; -+} -+ -+static int dconbl_set(struct backlight_device *dev) { ++ int i; ++ struct lxfb_par *par = info->par; + -+ int level = dev->props.brightness; ++ writel(0, par->df_regs + DF_PAR); + -+ if (dev->props.power != FB_BLANK_UNBLANK) -+ level = 0; ++ /* Sequential writes to the data register will increment the ++ address automatically */ + -+ dcon_set_backlight(level); -+ return 0; -+} ++ for(i = 0; i < len; i++) ++ writel(gamma[i] & 0xFFFFFF, par->df_regs + DF_PDR); + -+static int dconbl_get(struct backlight_device *dev) { -+ return dcon_get_backlight(); ++ writel(readl(par->df_regs + DF_MISC) & ~DF_MISC_GAM_BYPASS, ++ par->df_regs + DF_MISC); +} + -+static ssize_t dcon_mode_show(struct device *dev, -+ struct device_attribute *attr, char *buf) ++void lx_get_gamma(struct fb_info *info, unsigned int *gamma, int len) +{ -+ return sprintf(buf, "%4.4X\n", dcon_disp_mode); -+} ++ int i; ++ struct lxfb_par *par = info->par; + -+static ssize_t dcon_sleep_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_sleep_val); -+} ++ writel(0, par->df_regs + DF_PAR); + -+static ssize_t /* __deprecated */ dcon_source_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n"); -+ return sprintf(buf, "%d\n", dcon_source); ++ for(i = 0; i < len;i++) ++ gamma[i] = readl(par->df_regs + DF_PDR); +} + -+static ssize_t dcon_freeze_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_source == DCON_SOURCE_DCON ? 1 : 0); -+} + void lx_set_mode(struct fb_info *info) + { + struct lxfb_par *par = info->par; +@@ -313,6 +358,7 @@ void lx_set_mode(struct fb_info *info) + int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; + + /* Unlock the DC registers */ ++ readl(par->dc_regs + DC_UNLOCK); + writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); + + lx_graphics_disable(info); +@@ -534,3 +580,285 @@ int lx_blank_display(struct fb_info *info, int blank_mode) + + return 0; + } + -+static ssize_t dcon_output_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", dcon_output); -+} ++static struct geoderegs saved_regs; + -+static ssize_t dcon_resumeline_show(struct device *dev, -+ struct device_attribute *attr, char *buf) ++static void lx_save_regs(struct fb_info *info, struct geoderegs *regs) +{ -+ return sprintf(buf, "%d\n", resumeline); -+} ++ struct lxfb_par *par = info->par; ++ int i; + -+static int _strtoul(const char *buf, int len, unsigned int *val) -+{ ++ /* Wait for the command buffer to empty */ ++ while(!(readl(par->gp_regs + 0x44) & (1 << 4))); ++ ++ rdmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); ++ rdmsrl(MSR_LX_GLCP_DOTPLL, regs->msr.dotpll); ++ rdmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); ++ rdmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); + -+ char *endp; -+ unsigned int output = simple_strtoul(buf, &endp, 0); -+ int size = endp - buf; ++ writel(0x4758, par->dc_regs + 0x00); + -+ if (*endp && isspace(*endp)) -+ size++; ++ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE); ++ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE); ++ memcpy(regs->vp.b, par->df_regs, VP_REG_SIZE); ++ memcpy(regs->fp.b, par->df_regs + VP_FP_START, FP_REG_SIZE); + -+ if (size != len) -+ return -EINVAL; ++ /* Save the palettes */ ++ writel(0, par->dc_regs + 0x70); + -+ *val = output; -+ return 0; ++ for(i = 0; i < DC_PAL_SIZE; i++) ++ regs->pal[i] = readl(par->dc_regs + 0x74); ++ ++ writel(0, par->df_regs + 0x38); ++ ++ for(i = 0; i <= 0xFF; i++) ++ regs->gamma[i] = readl(par->df_regs + 0x40); +} + -+static ssize_t dcon_output_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) ++static void lx_restore_regs(struct fb_info *info, struct geoderegs *regs) +{ -+ int output; -+ int rc = -EINVAL; ++ struct lxfb_par *par = info->par; ++ u32 val, i; + -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; ++ /* == DOTPLL == */ + -+ if (output == DCON_OUTPUT_COLOR || output == DCON_OUTPUT_MONO) { -+ dcon_set_output(output); -+ rc = count; -+ } ++ lx_set_dotpll((u32) (regs->msr.dotpll >> 32)); + -+ return rc; -+} ++ /* MSRs */ + -+static ssize_t /* __deprecated */ dcon_source_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ int rc = -EINVAL; ++ wrmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg); ++ ++ /* == GP == */ + -+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n"); -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; ++ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00); ++ writel(regs->gp.r.src_offset, par->gp_regs + 0x04); ++ writel(regs->gp.r.stride, par->gp_regs + 0x08); ++ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C); ++ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10); ++ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14); ++ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18); ++ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C); ++ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20); ++ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24); ++ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28); ++ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C); ++ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30); ++ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34); + -+ dcon_set_source(output); -+ rc = count; ++ /* Writing to these registers would cause a blt to happen */ ++ /* 0x38, 0x3c, 0x40 */ + -+ return rc; -+} ++ /* Status register (0x44) is read only */ + -+static ssize_t dcon_freeze_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; -+ int rc = -EINVAL; ++ writel(regs->gp.r.hst_src, par->gp_regs + 0x48); ++ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c); ++ writel(regs->gp.r.cmd_top, par->gp_regs + 0x50); ++ writel(regs->gp.r.cmd_bot, par->gp_regs + 0x54); ++ writel(regs->gp.r.cmd_read, par->gp_regs + 0x58); ++ writel(regs->gp.r.cmd_write, par->gp_regs + 0x5C); ++ writel(regs->gp.r.ch3_offset, par->gp_regs + 0x60); ++ writel(regs->gp.r.ch3_mode_str, par->gp_regs + 0x64); ++ writel(regs->gp.r.ch3_width, par->gp_regs + 0x6C); ++ writel(regs->gp.r.ch3_hsrc, par->gp_regs + 0x70); + -+ if (_strtoul(buf, count, &output)) -+ return rc; ++ /* FIXME: Restore the LUT data here */ + -+ dcon_set_source(output ? DCON_SOURCE_DCON : DCON_SOURCE_CPU); -+ rc = count; ++ writel(regs->gp.r.int_cntrl, par->gp_regs + 0x70); + -+ return rc; -+} ++ /* == DC == */ + -+static ssize_t dcon_resumeline_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int rl; -+ int rc = -EINVAL; ++ /* Write the unlock value */ ++ writel(0x4758, par->dc_regs + 0x00); + -+ if (_strtoul(buf, count, &rl)) -+ return rc; ++ /* Write the palette data first */ + -+ resumeline = rl; -+ dcon_write(DCON_REG_SCAN_INT, resumeline); -+ rc = count; ++ writel(0, par->dc_regs + 0x70); + -+ return rc; -+} ++ for(i = 0; i < DC_PAL_SIZE; i++) ++ writel(regs->pal[i], par->dc_regs + 0x74); + -+static ssize_t dcon_sleep_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int output; ++ /* MSRs */ ++ wrmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare); + -+ if (_strtoul(buf, count, &output)) -+ return -EINVAL; ++ /* Write the gcfg register without the enables */ ++ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04); + -+ dcon_sleep(output ? DCON_SLEEP : DCON_ACTIVE); -+ return count; -+} ++ /* Write the vcfg register without the enables */ ++ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08); + -+static struct device_attribute dcon_device_files[] = { -+ __ATTR(mode, 0444, dcon_mode_show, NULL), -+ __ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store), -+ __ATTR(source, 0644, dcon_source_show, dcon_source_store), -+ __ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store), -+ __ATTR(output, 0644, dcon_output_show, dcon_output_store), -+ __ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store), -+}; ++ /* Write the rest of the active registers */ ++ writel(regs->dc.r.arb, par->dc_regs + 0x0C); ++ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10); ++ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14); ++ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18); ++ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C); ++ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20); ++ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24); ++ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28); ++ writel(regs->dc.r.dctop, par->dc_regs + 0x2c); ++ writel(regs->dc.r.line_size, par->dc_regs + 0x30); ++ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34); ++ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38); ++ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40); ++ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44); ++ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48); ++ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50); ++ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54); ++ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58); ++ writel(regs->dc.r.fbactive, par->dc_regs + 0x5c); ++ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60); ++ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64); ++ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68); + -+static struct backlight_ops dcon_bl_ops = { -+ .get_brightness = dconbl_get, -+ .update_status = dconbl_set -+}; ++ /* Skip register 0x6C (line_cnt), 0x70/0x74 (palette), ++ 0x78 (diagnostic), and 0x7c (diagnostic) ++ */ + -+/* List of GPIOs that we care about: -+ (in) GPIO12 -- DCONBLNK -+ (in) GPIO[56] -- DCONSTAT[01] -+ (out) GPIO11 -- DCONLOAD -+*/ ++ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80); ++ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84); ++ writel(regs->dc.r.dv_ctl, par->dc_regs + 0x88); ++ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C); + -+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12)) -+#define OUT_GPIOS (1<<11) ++ writel(regs->dc.r.gfx_scale, par->dc_regs + 0x90); ++ writel(regs->dc.r.irq_filt_ctl, par->dc_regs + 0x94); ++ writel(regs->dc.r.filt_coeff1, par->dc_regs + 0x98); ++ writel(regs->dc.r.filt_coeff2, par->dc_regs + 0x9C); ++ writel(regs->dc.r.vbi_event_ctl, par->dc_regs + 0xA0); + -+static irqreturn_t dcon_interrupt(int, void *); ++ writel(regs->dc.r.vbi_odd_ctl, par->dc_regs + 0xA4); ++ writel(regs->dc.r.vbi_hor, par->dc_regs + 0xA8); ++ writel(regs->dc.r.vbi_ln_odd, par->dc_regs + 0xAC); ++ writel(regs->dc.r.vbi_ln_event, par->dc_regs + 0xB0); ++ writel(regs->dc.r.vbi_pitch, par->dc_regs + 0xB4); ++ writel(regs->dc.r.clr_key, par->dc_regs + 0xB8); ++ writel(regs->dc.r.clr_key_mask, par->dc_regs + 0xBC); + -+static int dcon_request_irq(void) -+{ -+ unsigned long lo, hi; -+ unsigned char lob; ++ writel(regs->dc.r.clr_key_x, par->dc_regs + 0xC0); ++ writel(regs->dc.r.clr_key_y, par->dc_regs + 0xC4); ++ writel(regs->dc.r.irq, par->dc_regs + 0xC8); ++ writel(regs->dc.r.genlk_ctrl, par->dc_regs + 0xD4); + -+ rdmsr(MSR_LBAR_GPIO, lo, hi); ++ writel(regs->dc.r.vid_even_y_st_offset, par->dc_regs + 0xD8); ++ writel(regs->dc.r.vid_even_u_st_offset, par->dc_regs + 0xDC); ++ writel(regs->dc.r.vid_even_v_st_offset, par->dc_regs + 0xE0); + -+ /* Check the mask and whether GPIO is enabled (sanity check) */ -+ if (hi != 0x0000f001) { -+ printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n"); -+ return -ENODEV; -+ } ++ writel(regs->dc.r.v_active_even_timing, par->dc_regs + 0xE4); ++ writel(regs->dc.r.v_blank_even_timing, par->dc_regs + 0xE8); ++ writel(regs->dc.r.v_sync_even_timing, par->dc_regs + 0xEC); + -+ /* Mask off the IO base address */ -+ gpio_base = lo & 0x0000ff00; ++ /* == VP == */ + -+ /* Turn off the event enable for GPIO7 just to be safe */ -+ outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN); ++ /* MSR */ ++ wrmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel); + -+ /* Set the directions for the GPIO pins */ -+ outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN); -+ outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN); ++ /* Write gamma information first */ + -+ /* Set up the interrupt mappings */ ++ writel(0, par->df_regs + 0x38); + -+ /* Set the IRQ to pair 2 */ -+ geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2); ++ for(i = 0; i <= 0xFF; i++) ++ writel((u32) regs->gamma[i], par->df_regs + 0x40); + -+ /* Enable group 2 to trigger the DCON interrupt */ -+ geode_gpio_set_irq(2, DCON_IRQ); ++ /* Don't enable video yet */ ++ writel((u32) regs->vp.r.vcfg & ~0x01, par->df_regs + 0x00); + -+ /* Select edge level for interrupt (in PIC) */ ++ /* Don't enable the CRT yet */ ++ writel((u32) regs->vp.r.dcfg & ~0x0F, par->df_regs + 0x08); + -+ lob = inb(0x4d0); -+ lob &= ~(1 << DCON_IRQ); -+ outb(lob, 0x4d0); ++ /* Write the rest of the VP registers */ + -+ /* Register the interupt handler */ -+ if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver)) -+ return -EIO; ++ writel((u32) regs->vp.r.vx, par->df_regs + 0x10); ++ writel((u32) regs->vp.r.vy, par->df_regs + 0x18); ++ writel((u32) regs->vp.r.vs, par->df_regs + 0x20); ++ writel((u32) regs->vp.r.vck, par->df_regs + 0x28); ++ writel((u32) regs->vp.r.vcm, par->df_regs + 0x30); ++ writel((u32) regs->vp.r.misc, par->df_regs + 0x50); ++ writel((u32) regs->vp.r.ccs, par->df_regs + 0x58); ++ writel((u32) regs->vp.r.vdc, par->df_regs + 0x78); ++ writel((u32) regs->vp.r.vco, par->df_regs + 0x80); ++ writel((u32) regs->vp.r.crc, par->df_regs + 0x88); ++ writel((u32) regs->vp.r.vde, par->df_regs + 0x98); ++ writel((u32) regs->vp.r.cck, par->df_regs + 0xA0); ++ writel((u32) regs->vp.r.ccm, par->df_regs + 0xA8); ++ writel((u32) regs->vp.r.cc1, par->df_regs + 0xB0); ++ writel((u32) regs->vp.r.cc2, par->df_regs + 0xB8); ++ writel((u32) regs->vp.r.a1x, par->df_regs + 0xC0); ++ writel((u32) regs->vp.r.a1y, par->df_regs + 0xC8); ++ writel((u32) regs->vp.r.a1c, par->df_regs + 0xD0); ++ writel((u32) regs->vp.r.a1t, par->df_regs + 0xD8); ++ writel((u32) regs->vp.r.a2x, par->df_regs + 0xE0); ++ writel((u32) regs->vp.r.a2y, par->df_regs + 0xE8); ++ writel((u32) regs->vp.r.a2c, par->df_regs + 0xF0); ++ writel((u32) regs->vp.r.a2t, par->df_regs + 0xF8); ++ writel((u32) regs->vp.r.a3x, par->df_regs + 0x100); ++ writel((u32) regs->vp.r.a3y, par->df_regs + 0x108); ++ writel((u32) regs->vp.r.a3c, par->df_regs + 0x110); ++ writel((u32) regs->vp.r.a3t, par->df_regs + 0x118); ++ writel((u32) regs->vp.r.vrr, par->df_regs + 0x120); + -+ /* Clear INV_EN for GPIO7 (DCONIRQ) */ -+ outl((1<<(16+7)), gpio_base + GPIOx_INV_EN); ++ writel((u32) regs->vp.r.vye, par->df_regs + 0x138); ++ writel((u32) regs->vp.r.a1ye, par->df_regs + 0x140); ++ writel((u32) regs->vp.r.a2ye, par->df_regs + 0x148); ++ writel((u32) regs->vp.r.a3ye, par->df_regs + 0x150); + -+ /* Enable filter for GPIO12 (DCONBLANK) */ -+ outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN); ++ /* == FP == */ + -+ /* Disable filter for GPIO7 */ -+ outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN); ++ writel((u32) regs->fp.r.pt1, par->df_regs + 0x400); ++ writel((u32) regs->fp.r.pt2, par->df_regs + 0x408); ++ writel((u32) regs->fp.r.dfc, par->df_regs + 0x418); ++ writel(regs->fp.r.dca, par->df_regs + 0x448); ++ writel(regs->fp.r.dmd, par->df_regs + 0x450); ++ writel(regs->fp.r.crc, par->df_regs + 0x458); + -+ /* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */ ++ /* Final enables */ + -+ outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN); -+ outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN); ++ val = readl(par->df_regs + 0x410); + -+ /* Add GPIO12 to the Filter Event Pair #7 */ -+ outb(12, gpio_base + GPIO_FE7_SEL); ++ /* Control the panel */ ++ if (regs->fp.r.pm & (1 << 24)) { + -+ /* Turn off negative Edge Enable for GPIO12 */ -+ outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN); ++ if (!(val & 0x09)) ++ writel(regs->fp.r.pm, par->df_regs + 0x410); ++ } ++ else { ++ if (!(val & 0x05)) ++ writel(regs->fp.r.pm, par->df_regs + 0x410); ++ } + -+ /* Enable negative Edge Enable for GPIO7 */ -+ outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN); ++ /* Turn everything on */ + -+ /* Zero the filter amount for Filter Event Pair #7 */ -+ outw(0, gpio_base + GPIO_FLT7_AMNT); ++ writel(regs->dc.r.gcfg, par->dc_regs + 0x04); ++ writel((u32) regs->vp.r.vcfg, par->df_regs + 0x00); ++ writel((u32) regs->vp.r.dcfg, par->df_regs + 0x08); ++ writel(regs->dc.r.dcfg, par->dc_regs + 0x08); ++} + -+ /* Clear the negative edge status for GPIO7 and GPIO12 */ -+ outl((1<<7) | (1<<12), gpio_base+0x4c); ++static int lx_power_on = 1; + -+ /* FIXME: Clear the posiitive status as well, just to be sure */ -+ outl((1<<7) | (1<<12), gpio_base+0x48); ++int lx_shutdown(struct fb_info *info) ++{ ++ struct lxfb_par *par = info->par; + -+ /* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */ -+ outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN); ++ if (lx_power_on == 0) ++ return 0; + -+ /* Determine the current state by reading the GPIO bit */ -+ /* Earlier stages of the boot process have established the state */ -+ dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11) -+ ? DCON_SOURCE_CPU -+ : DCON_SOURCE_DCON; -+ dcon_pending = dcon_source; ++ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); ++ lx_save_regs(info, &saved_regs); ++ lx_graphics_disable(info); + ++ lx_power_on = 0; + return 0; +} + -+static int dcon_reboot_notify(struct notifier_block *nb, unsigned long foo, void *bar) ++int lx_powerup(struct fb_info *info) +{ -+ if (dcon_client == NULL) -+ return 0; ++ struct lxfb_par *par = info->par; + -+ /* Turn off the DCON. Entirely. */ -+ dcon_write(DCON_REG_MODE, 0x39); -+ dcon_write(DCON_REG_MODE, 0x32); -+ return 0; -+} ++ if (lx_power_on == 1) ++ return 0; + -+static int dcon_conswitch_notify(struct notifier_block *nb, -+ unsigned long mode, void *dummy) -+{ -+ if (mode == CONSOLE_EVENT_SWITCH_TEXT) -+ dcon_sleep(DCON_ACTIVE); ++ lx_restore_regs(info, &saved_regs); ++ writel(0, par->dc_regs + DC_UNLOCK); + ++ lx_power_on = 1; + return 0; +} +diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c +index 7f3f18d..e282e74 100644 +--- a/drivers/video/geode/video_gx.c ++++ b/drivers/video/geode/video_gx.c +@@ -16,10 +16,14 @@ + #include + #include + #include ++#include + + #include "geodefb.h" + #include "video_gx.h" ++#include "display_gx.h" + ++/* This structure is used to store the saved registers during suspend */ ++static struct geoderegs gx_saved_regs; + + /* + * Tables of register settings for various DOTCLKs. +@@ -58,7 +62,7 @@ static const struct gx_pll_entry gx_pll_table_48MHz[] = { + { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */ + { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */ + { 13333, 0, 0x00000052 }, /* 75.0000 */ +- { 12698, 0, 0x00000056 }, /* 78.7500 */ ++ { 12698, 0, 0x00000056 }, /* 78.7500 */ + { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */ + { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */ + { 10582, 0, 0x000002D2 }, /* 94.5000 */ +@@ -117,8 +121,9 @@ static const struct gx_pll_entry gx_pll_table_14MHz[] = { + { 4357, 0, 0x0000057D }, /* 229.5000 */ + }; + +-static void gx_set_dclk_frequency(struct fb_info *info) ++void gx_set_dclk_frequency(struct fb_info *info) + { ++ struct geodefb_par *par = info->par; + const struct gx_pll_entry *pll_table; + int pll_table_len; + int i, best_i; +@@ -173,115 +178,169 @@ static void gx_set_dclk_frequency(struct fb_info *info) + do { + rdmsrl(MSR_GLCP_DOTPLL, dotpll); + } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); + -+static struct notifier_block dcon_nb = { -+ .notifier_call = dcon_reboot_notify, -+ .priority = -1, -+}; -+ -+static struct notifier_block dcon_console_nb = { -+ .notifier_call = dcon_conswitch_notify, -+ .priority = -1, -+}; -+ -+static int dcon_probe(struct i2c_adapter *adap, int addr, int kind) -+{ -+ struct i2c_client *client; -+ uint16_t ver; -+ int rc, i; ++ par->curdclk = pll_table[best_i].dotpll_value; + } + +-static void +-gx_configure_tft(struct fb_info *info) ++/* Find out the current clock - we will use this information to avoid ++ re-programming it if we don't need to */ + -+ if (!olpc_has_dcon()) { -+ printk("olpc-dcon: No DCON is attached.\n"); -+ return -ENODEV; ++unsigned int gx_get_dclk(struct fb_info *info) + { +- struct geodefb_par *par = info->par; +- unsigned long val; +- unsigned long fp; ++ const struct gx_pll_entry *pll_table; ++ int pll_table_len; ++ u64 dotpll; ++ int i; + +- /* Set up the DF pad select MSR */ ++ if (cpu_data->x86_mask == 1) { ++ pll_table = gx_pll_table_14MHz; ++ pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz); ++ } else { ++ pll_table = gx_pll_table_48MHz; ++ pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz); + } -+ -+ if (num_registered_fb >= 1) -+ fbinfo = registered_fb[0]; -+ -+ if (adap->id != I2C_HW_SMBUS_SCX200) { -+ printk(KERN_ERR "olpc-dcon: Invalid I2C bus (%d not %d)\n", -+ adap->id, I2C_HW_SMBUS_SCX200); -+ return -ENXIO; + +- rdmsrl(GX_VP_MSR_PAD_SELECT, val); +- val &= ~GX_VP_PAD_SELECT_MASK; +- val |= GX_VP_PAD_SELECT_TFT; +- wrmsrl(GX_VP_MSR_PAD_SELECT, val); ++ rdmsrl(MSR_GLCP_DOTPLL, dotpll); + +- /* Turn off the panel */ ++ for(i = 0; i < pll_table_len; i++) { ++ if (pll_table[i].dotpll_value == (u32) (dotpll >> 32)) ++ break; + } + +- fp = readl(par->vid_regs + GX_FP_PM); +- fp &= ~GX_FP_PM_P; +- writel(fp, par->vid_regs + GX_FP_PM); ++ return (i == pll_table_len) ? 0 : pll_table[i].pixclock; ++} + -+ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL); -+ if (client == NULL) -+ return -ENOMEM; + -+ strncpy(client->name, "OLPC-DCON", I2C_NAME_SIZE); -+ client->addr = addr; -+ client->adapter = adap; -+ client->driver = &dcon_driver; ++#define CMP(val, mask, res) (((val) & (mask)) == (res)) + +- /* Set timing 1 */ ++static void ++gx_configure_tft(struct fb_info *info) { + +- fp = readl(par->vid_regs + GX_FP_PT1); +- fp &= GX_FP_PT1_VSIZE_MASK; +- fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; +- writel(fp, par->vid_regs + GX_FP_PT1); ++ struct geodefb_par *par = info->par; ++ u32 val, fp = 0, fp1, fp2, sync = 0; + +- /* Timing 2 */ +- /* Set bits that are always on for TFT */ ++ /* Set up the DF pad select MSR */ + +- fp = 0x0F100000; ++ rdmsrl(GX_VP_MSR_PAD_SELECT, val); + +- /* Add sync polarity */ ++ if ((val & GX_VP_PAD_SELECT_MASK) != GX_VP_PAD_SELECT_TFT) { ++ val &= ~GX_VP_PAD_SELECT_MASK; ++ val |= GX_VP_PAD_SELECT_TFT; ++ wrmsrl(GX_VP_MSR_PAD_SELECT, val); ++ } + + if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) +- fp |= GX_FP_PT2_VSP; ++ sync |= GX_FP_PT2_VSP; + + if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) +- fp |= GX_FP_PT2_HSP; ++ sync |= GX_FP_PT2_HSP; + +- writel(fp, par->vid_regs + GX_FP_PT2); ++ /* We only need to turn off the panel if something changed */ + +- /* Set the dither control */ +- writel(0x70, par->vid_regs + GX_FP_DFC); ++ fp1 = readl(par->vid_regs + GX_FP_PT1); ++ fp2 = readl(par->vid_regs + GX_FP_PT2); + -+ if ((rc = i2c_attach_client(client)) != 0) { -+ printk(KERN_ERR "olpc-dcon: Unable to attach the I2C client.\n"); -+ goto eclient; -+ } ++ if (!CMP(fp1, GX_FP_PT1_VSIZE_MASK, info->var.yres << GX_FP_PT1_VSIZE_SHIFT) || ++ (fp2 != (0x0F100000 | sync))) { + +- /* Enable the FP data and power (in case the BIOS didn't) */ ++ /* Turn off the panel */ + +- fp = readl(par->vid_regs + GX_DCFG); +- fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN; +- writel(fp, par->vid_regs + GX_DCFG); ++#ifdef NOTUSED ++ /* Do we really need to turn off the panel? */ ++ /* Possibly - we have a glitch somewhere */ + +- /* Unblank the panel */ ++ fp = readl(par->vid_regs + GX_FP_PM); ++ fp &= ~GX_FP_PM_P; ++ writel(fp, par->vid_regs + GX_FP_PM); ++#endif + -+ ver = i2c_smbus_read_word_data(client, DCON_REG_ID); ++ /* Timing 1 */ ++ fp1 &= GX_FP_PT1_VSIZE_MASK; ++ fp1 |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT; ++ writel(fp, par->vid_regs + GX_FP_PT1); + -+ if ((ver >> 8) != 0xDC) { -+ printk(KERN_ERR "olpc-dcon: DCON ID not 0xDCxx: 0x%04x instead.\n", ver); -+ rc = -ENXIO; -+ goto ei2c; ++ /* Timing 2 */ ++ writel(0x0F100000 | sync, par->vid_regs + GX_FP_PT2); + } + -+ if ((rc = dcon_request_irq())) { -+ printk(KERN_ERR "olpc-dcon: Unable to grab IRQ.\n"); -+ goto ei2c; ++ /* Set the dither control */ ++ if (readl(par->vid_regs + GX_FP_DFC) != 0x70) { ++ writel(0x70, par->vid_regs + GX_FP_DFC); + } + -+ if (ver < 0xdc02 && !noinit) { -+ /* Initialize the DCON registers */ ++ /* Turn on the panel */ + + fp = readl(par->vid_regs + GX_FP_PM); +- fp |= GX_FP_PM_P; +- writel(fp, par->vid_regs + GX_FP_PM); + -+ /* Start with work-arounds for DCON ASIC */ -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc); -+ i2c_smbus_write_word_data(client, 0x0b, 0x007a); -+ i2c_smbus_write_word_data(client, 0x36, 0x025c); -+ i2c_smbus_write_word_data(client, 0x37, 0x025e); -+ -+ /* Initialise SDRAM */ ++ if (!(fp & 0x09)) ++ writel(fp | GX_FP_PM_P, par->vid_regs + GX_FP_PM); + } + ++#define DCFG_DEFAULT_VAL GX_DCFG_CRT_SYNC_SKW_DFLT | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN | \ ++GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN + -+ i2c_smbus_write_word_data(client, 0x3b, 0x002b); -+ i2c_smbus_write_word_data(client, 0x41, 0x0101); -+ i2c_smbus_write_word_data(client, 0x42, 0x0101); + static void gx_configure_display(struct fb_info *info) + { + struct geodefb_par *par = info->par; +- u32 dcfg, misc; ++ u32 dcfg, misc, sync = 0; + + /* Set up the MISC register */ +- + misc = readl(par->vid_regs + GX_MISC); + +- /* Power up the DAC */ +- misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); ++ /* We leave gamma enabled if it was already enabled. ++ Although the hardware enables it without setting ++ up the gamma table, the BIOS or bootloader ought ++ to have either disabled it or loaded a table by now */ + +- /* Disable gamma correction */ +- misc |= GX_MISC_GAM_EN; + +- writel(misc, par->vid_regs + GX_MISC); + +- /* Write the display configuration */ +- dcfg = readl(par->vid_regs + GX_DCFG); ++ if (par->enable_crt) { ++ /* Power up the CRT DACs */ ++ if (misc & ( GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN)) { ++ misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); ++ writel(misc, par->vid_regs + GX_MISC); ++ } + +- /* Disable hsync and vsync */ +- dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); +- writel(dcfg, par->vid_regs + GX_DCFG); ++ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) ++ sync |= GX_DCFG_CRT_HSYNC_POL; + +- /* Clear bits from existing mode. */ +- dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK +- | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL +- | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); ++ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) ++ sync |= GX_DCFG_CRT_VSYNC_POL; + } -+ -+ /* Colour swizzle, AA, no passthrough, backlight */ -+ -+ dcon_disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE | MODE_CSWIZZLE; -+ if (useaa) -+ dcon_disp_mode |= MODE_COL_AA; -+ i2c_smbus_write_word_data(client, DCON_REG_MODE, dcon_disp_mode); -+ -+ -+ /* Set the scanline to interrupt on during resume */ -+ -+ i2c_smbus_write_word_data(client, DCON_REG_SCAN_INT, resumeline); -+ -+ /* Add the DCON device */ -+ -+ dcon_device = platform_device_alloc("dcon", -1); -+ -+ if (dcon_device == NULL) { -+ printk(KERN_ERR "dcon: Unable to create the DCON device\n"); -+ rc = -ENOMEM; -+ goto eirq; ++ else { ++ /* Turn off the CRT DACs in FP mode - we don't need them */ ++ if ((misc & (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN))) { ++ misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN); ++ writel(misc, par->vid_regs + GX_MISC); ++ } + } + +- /* Set default sync skew. */ +- dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; ++ /* Write the display configuration */ ++ dcfg = readl(par->vid_regs + GX_DCFG); + +- /* Enable hsync and vsync. */ +- dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; ++ if (!CMP(dcfg, DCFG_DEFAULT_VAL | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL, ++ DCFG_DEFAULT_VAL | sync)) { + +- /* Sync polarities. */ +- if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) +- dcfg |= GX_DCFG_CRT_HSYNC_POL; +- if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) +- dcfg |= GX_DCFG_CRT_VSYNC_POL; ++ /* Disable hsync and vsync */ ++ dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); ++ writel(dcfg, par->vid_regs + GX_DCFG); + +- /* Enable the display logic */ +- /* Set up the DACS to blank normally */ ++ /* Clear bits from existing mode. */ ++ dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK ++ | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL ++ | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); + +- dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; ++ /* Set default sync skew. */ ++ dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; + +- /* Enable the external DAC VREF? */ ++ /* Enable hsync and vsync. */ ++ dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; + +- writel(dcfg, par->vid_regs + GX_DCFG); ++ /* Enable the display logic */ ++ dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN; + -+ if ((rc = platform_device_add(dcon_device))) { -+ printk(KERN_ERR "dcon: Unable to add the DCON device\n"); -+ goto edev; ++ writel(dcfg, par->vid_regs + GX_DCFG); + } + + /* Set up the flat panel (if it is enabled) */ + +@@ -289,6 +348,100 @@ static void gx_configure_display(struct fb_info *info) + gx_configure_tft(info); + } + ++int gxfb_powerdown(struct fb_info *info) ++{ ++ struct geodefb_par *par = info->par; + -+ for(i = 0; i < ARRAY_SIZE(dcon_device_files); i++) -+ device_create_file(&dcon_device->dev, &dcon_device_files[i]); -+ -+ /* Add the backlight device for the DCON */ ++ /* We're already suspended */ + -+ dcon_client = client; ++ if (par->state != FB_POWER_STATE_ON) ++ return 0; + -+ dcon_bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev, -+ NULL, &dcon_bl_ops); ++ /* Save the registers */ ++ gx_save_regs(info, &gx_saved_regs); + -+ if (IS_ERR(dcon_bl_dev)) { -+ printk(KERN_INFO "Could not register the backlight device for the DCON (%ld)\n", PTR_ERR(dcon_bl_dev)); -+ dcon_bl_dev = NULL; -+ } -+ else { -+ dcon_bl_dev->props.max_brightness = 15; -+ dcon_bl_dev->props.power = FB_BLANK_UNBLANK; -+ dcon_bl_dev->props.brightness = dcon_get_backlight(); ++ /* Shut down the engine */ + -+ backlight_update_status(dcon_bl_dev); -+ } ++ writel(gx_saved_regs.vp.r.vcfg & ~0x01, par->vid_regs + GX_VCFG); ++ writel(gx_saved_regs.vp.r.dcfg & ~0x0F, par->vid_regs + GX_DCFG); + -+ register_reboot_notifier(&dcon_nb); -+ console_event_register(&dcon_console_nb); ++ /* Turn off the flat panel unless we are attached to a DCON */ ++ if (!olpc_has_dcon()) ++ writel(gx_saved_regs.fp.r.pm & ~GX_FP_PM_P, par->vid_regs + GX_FP_PM); + -+ printk(KERN_INFO "olpc-dcon: Discovered DCON version %x\n", ver & 0xFF); ++ writel(0x4758, par->dc_regs + DC_UNLOCK); + -+ return 0; ++ writel(gx_saved_regs.dc.r.gcfg & ~0x0F, ++ par->dc_regs + DC_GENERAL_CFG); + -+ edev: -+ platform_device_unregister(dcon_device); -+ dcon_device = NULL; -+ eirq: -+ free_irq(DCON_IRQ, &dcon_driver); -+ ei2c: -+ i2c_detach_client(client); -+ eclient: -+ kfree(client); ++ writel(gx_saved_regs.dc.r.dcfg & ~0x19, ++ par->dc_regs + DC_DISPLAY_CFG); ++ ++ par->state = FB_POWER_STATE_SUSPEND; + -+ return rc; ++ return 0; +} + -+static int dcon_attach(struct i2c_adapter *adap) ++int gxfb_powerup(struct fb_info *info) +{ -+ int ret; ++ struct geodefb_par *par = info->par; ++ u32 val; ++ ++ if (par->state == FB_POWER_STATE_SUSPEND) { + -+ ret = i2c_probe(adap, &addr_data, dcon_probe); ++ writel(gx_saved_regs.dc.r.dcfg, ++ par->dc_regs + DC_DISPLAY_CFG); + -+ if (dcon_client == NULL) -+ printk(KERN_ERR "olpc-dcon: No DCON found on SMBus\n"); ++ writel(gx_saved_regs.vp.r.vcfg, par->vid_regs + GX_VCFG); ++ writel(gx_saved_regs.vp.r.dcfg, par->vid_regs + GX_DCFG); + -+ return ret; -+} ++ val = readl(par->vid_regs + GX_FP_PM); + -+static int dcon_detach(struct i2c_client *client) -+{ -+ int rc; -+ dcon_client = NULL; ++ /* power up the panel if it needs it; we don't always power it down */ ++ if (!(val & 0x09)) { ++ writel(gx_saved_regs.fp.r.pm, par->vid_regs + GX_FP_PM); ++ mdelay(64); ++ } ++ } + -+ unregister_reboot_notifier(&dcon_nb); -+ console_event_unregister(&dcon_console_nb); ++ /* If the panel is currently on its way up, then wait up to 100ms ++ for it */ ++ ++ if (readl(par->vid_regs + GX_FP_PM) & 0x08) { ++ int i; ++ ++ for(i = 0; i < 10; i++) { ++ if (readl(par->vid_regs + GX_FP_PM) & 0x01) ++ break; + -+ free_irq(DCON_IRQ, &dcon_driver); ++ mdelay(10); ++ } + -+ if ((rc = i2c_detach_client(client)) == 0) -+ kfree(i2c_get_clientdata(client)); ++ if (i == 10) ++ printk(KERN_ERR "gxfb: Panel power up timed out\n"); ++ } + -+ if (dcon_bl_dev != NULL) -+ backlight_device_unregister(dcon_bl_dev); ++ if (par->state == FB_POWER_STATE_ON) ++ return 0; ++ ++ switch(par->state) { ++ case FB_POWER_STATE_OFF: ++ gx_restore_regs(info, &gx_saved_regs); ++ break; + -+ if (dcon_device != NULL) -+ platform_device_unregister(dcon_device); -+ cancel_work_sync(&dcon_work); ++ case FB_POWER_STATE_SUSPEND: ++ /* Do this because it will turn on the FIFO which will ++ start the line count */ ++ writel(gx_saved_regs.dc.r.gcfg, ++ par->dc_regs + DC_GENERAL_CFG); ++ writel(0x0, par->dc_regs + DC_UNLOCK); ++ break; ++ } + -+ return rc; ++ par->state = FB_POWER_STATE_ON; ++ return 0; +} + + static int gx_blank_display(struct fb_info *info, int blank_mode) + { + struct geodefb_par *par = info->par; +@@ -315,6 +468,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) + default: + return -EINVAL; + } + -+#ifdef CONFIG_PM -+static int dcon_suspend(struct i2c_client *client, pm_message_t state) -+{ -+ if (dcon_sleep_val != DCON_ACTIVE) -+ return 0; + dcfg = readl(par->vid_regs + GX_DCFG); + dcfg &= ~(GX_DCFG_DAC_BL_EN + | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); +@@ -326,7 +480,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) + dcfg |= GX_DCFG_VSYNC_EN; + writel(dcfg, par->vid_regs + GX_DCFG); + +- /* Power on/off flat panel. */ ++ /* Power on/off flat panel */ + + if (par->enable_crt == 0) { + fp_pm = readl(par->vid_regs + GX_FP_PM); +@@ -340,8 +494,37 @@ static int gx_blank_display(struct fb_info *info, int blank_mode) + return 0; + } + ++extern struct fb_info *gxfb_info; + -+ /* Set up the DCON to have the source */ -+ return dcon_set_source_sync(DCON_SOURCE_DCON); -+} ++/* This function controls the flatpanel power sequencing - this is used ++ by the OLPC power management engine to enable the FP sequencing much ++ earlier in the resume process ++*/ + -+static int dcon_resume(struct i2c_client *client) ++void gxfb_flatpanel_control(int state) +{ -+ int x; -+ if (dcon_sleep_val != DCON_ACTIVE) -+ return 0; ++ struct geodefb_par *par = gxfb_info->par; ++ u32 val, fp = readl(par->vid_regs + GX_FP_PM); ++ val = fp; + -+ /* HACK: ensure the bus is stable */ -+ do { -+ x = dcon_read(DCON_REG_ID); -+ } while (x < 0); ++ /* Turn on the panel if it isn't aleady */ + -+ return dcon_set_source(DCON_SOURCE_CPU); -+} ++ if (state) { ++ if (!(val & 0x01)) ++ val |= GX_FP_PM_P; ++ } ++ else { ++ if (!(val & 0x02)) ++ val &= ~GX_FP_PM_P; ++ } + -+#endif ++ if (val != fp) ++ writel(val, par->vid_regs + GX_FP_PM); ++} + -+static irqreturn_t dcon_interrupt(int irq, void *id) -+{ -+ int status = inl(gpio_base + GPIOx_READ_BACK) >> 5; + struct geode_vid_ops gx_vid_ops = { + .set_dclk = gx_set_dclk_frequency, ++ .get_dclk = gx_get_dclk, + .configure_display = gx_configure_display, + .blank_display = gx_blank_display, + }; +diff --git a/drivers/video/geode/video_gx.h b/drivers/video/geode/video_gx.h +index ce28d8f..c57b36b 100644 +--- a/drivers/video/geode/video_gx.h ++++ b/drivers/video/geode/video_gx.h +@@ -11,6 +11,8 @@ + #ifndef __VIDEO_GX_H__ + #define __VIDEO_GX_H__ + ++#include "geode_regs.h" + -+ /* Clear the negative edge status for GPIO7 */ -+ outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS); + extern struct geode_vid_ops gx_vid_ops; + + /* GX Flatpanel control MSR */ +@@ -20,6 +22,8 @@ extern struct geode_vid_ops gx_vid_ops; + + /* Geode GX video processor registers */ + ++#define GX_VCFG 0x0000 + -+ switch (status & 3) { -+ case 3: -+ printk(KERN_DEBUG "olpc-dcon: DCONLOAD_MISSED interrupt\n"); -+ break; -+ case 2: /* switch to DCON mode */ -+ case 1: /* switch to CPU mode */ -+ dcon_switched = 1; -+ wake_up(&dcon_wait_queue); -+ break; -+ case 0: -+ printk(KERN_DEBUG "olpc-dcon: scanline interrupt w/CPU\n"); -+ } + #define GX_DCFG 0x0008 + # define GX_DCFG_CRT_EN 0x00000001 + # define GX_DCFG_HSYNC_EN 0x00000002 +@@ -42,6 +46,14 @@ extern struct geode_vid_ops gx_vid_ops; + #define GX_MISC_DAC_PWRDN 0x00000400 + #define GX_MISC_A_PWRDN 0x00000800 + ++/* Gamma correction RAM - address and data registers */ + -+ return IRQ_HANDLED; -+} ++#define GX_GAR 0x038 ++#define GX_GDR 0x040 + -+static struct i2c_driver dcon_driver = { -+ .driver = { -+ .name = "OLPC-DCON", -+ }, -+ .id = I2C_DRIVERID_DCON, -+ .attach_adapter = dcon_attach, -+ .detach_client = dcon_detach, -+#ifdef CONFIG_PM -+ .suspend = dcon_suspend, -+ .resume = dcon_resume, -+#endif -+}; ++#define GXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */ ++#define GXFB_GAMMA_SIZE (GXFB_GAMMA_DWORDS * sizeof(unsigned int)) + + /* Geode GX flat panel display control registers */ + + #define GX_FP_PT1 0x0400 +@@ -69,4 +81,13 @@ extern struct geode_vid_ops gx_vid_ops; + # define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull) + # define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull) + ++int gxfb_powerdown(struct fb_info *info); ++int gxfb_powerup(struct fb_info *info); + -+static int __init olpc_dcon_init(void) -+{ -+ i2c_add_driver(&dcon_driver); -+ return 0; -+} ++void gx_set_dclk_frequency(struct fb_info *info); ++unsigned int gx_get_dclk(struct fb_info *info); + -+static void __exit olpc_dcon_exit(void) -+{ -+ i2c_del_driver(&dcon_driver); -+} ++void gx_save_regs(struct fb_info *info, struct geoderegs *regs); ++void gx_restore_regs(struct fb_info *info, struct geoderegs *regs); + -+module_init(olpc_dcon_init); -+module_exit(olpc_dcon_exit); -+ -+MODULE_LICENSE("GPL"); -diff --git a/drivers/video/olpc_dcon.h b/drivers/video/olpc_dcon.h -new file mode 100644 -index 0000000..6453ca4 ---- /dev/null -+++ b/drivers/video/olpc_dcon.h -@@ -0,0 +1,75 @@ -+#ifndef OLPC_DCON_H_ -+#define OLPC_DCON_H_ -+ -+/* DCON registers */ -+ -+#define DCON_REG_ID 0 -+#define DCON_REG_MODE 1 -+ -+#define MODE_PASSTHRU (1<<0) -+#define MODE_SLEEP (1<<1) -+#define MODE_SLEEP_AUTO (1<<2) -+#define MODE_BL_ENABLE (1<<3) -+#define MODE_BLANK (1<<4) -+#define MODE_CSWIZZLE (1<<5) -+#define MODE_COL_AA (1<<6) -+#define MODE_MONO_LUMA (1<<7) -+#define MODE_SCAN_INT (1<<8) -+#define MODE_CLOCKDIV (1<<9) -+#define MODE_DEBUG (1<<14) -+#define MODE_SELFTEST (1<<15) -+ -+#define DCON_REG_HRES 2 -+#define DCON_REG_HTOTAL 3 -+#define DCON_REG_HSYNC_WIDTH 4 -+#define DCON_REG_VRES 5 -+#define DCON_REG_VTOTAL 6 -+#define DCON_REG_VSYNC_WIDTH 7 -+#define DCON_REG_TIMEOUT 8 -+#define DCON_REG_SCAN_INT 9 -+#define DCON_REG_BRIGHT 10 -+ -+/* GPIO registers (CS5536) */ -+ -+#define MSR_LBAR_GPIO 0x5140000C -+ -+#define GPIOx_OUT_VAL 0x00 -+#define GPIOx_OUT_EN 0x04 -+#define GPIOx_IN_EN 0x20 -+#define GPIOx_INV_EN 0x24 -+#define GPIOx_IN_FLTR_EN 0x28 -+#define GPIOx_EVNTCNT_EN 0x2C -+#define GPIOx_READ_BACK 0x30 -+#define GPIOx_EVNT_EN 0x38 -+#define GPIOx_NEGEDGE_EN 0x44 -+#define GPIOx_NEGEDGE_STS 0x4C -+#define GPIO_FLT7_AMNT 0xD8 -+#define GPIO_MAP_X 0xE0 -+#define GPIO_MAP_Y 0xE4 -+#define GPIO_FE7_SEL 0xF7 -+ -+ -+/* Status values */ -+ -+#define DCONSTAT_SCANINT 0 -+#define DCONSTAT_SCANINT_DCON 1 -+#define DCONSTAT_DISPLAYLOAD 2 -+#define DCONSTAT_MISSED 3 -+ -+/* Source values */ -+ -+#define DCON_SOURCE_DCON 0 -+#define DCON_SOURCE_CPU 1 -+ -+/* Output values */ -+#define DCON_OUTPUT_COLOR 0 -+#define DCON_OUTPUT_MONO 1 -+ -+/* Sleep values */ -+#define DCON_ACTIVE 0 -+#define DCON_SLEEP 1 -+ -+/* Interrupt */ -+#define DCON_IRQ 6 + #endif /* !__VIDEO_GX_H__ */ +diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c +index 3741ad7..49f6db5 100644 +--- a/drivers/video/modedb.c ++++ b/drivers/video/modedb.c +@@ -33,6 +33,8 @@ const char *global_mode_option; + * Standard video mode definitions (taken from XFree86) + */ + ++#define DEFAULT_MODEDB_INDEX 0 + -+#endif + static const struct fb_videomode modedb[] = { + { + /* 640x400 @ 70 Hz, 31.5 kHz hsync */ +@@ -504,7 +506,8 @@ int fb_find_mode(struct fb_var_screeninfo *var, + } + + if (!default_mode) +- default_mode = &db[0]; ++ default_mode = (db == modedb) ? ++ &modedb[DEFAULT_MODEDB_INDEX] : &db[0]; + + if (!default_bpp) + default_bpp = 8; diff --git a/fs/Kconfig b/fs/Kconfig index f9eed6d..6fa3ea2 100644 --- a/fs/Kconfig @@ -16997,363 +5620,55 @@ index 91d1d0f..d1d4f27 100644 + if (!c->wbuf_verify) { + kfree(c->oobbuf); + kfree(c->wbuf); -+ return -ENOMEM; -+ } -+#endif - return 0; - } - - void jffs2_nand_flash_cleanup(struct jffs2_sb_info *c) - { -+#ifdef CONFIG_JFFS2_FS_WBUF_VERIFY -+ kfree(c->wbuf_verify); -+#endif - kfree(c->wbuf); - kfree(c->oobbuf); - } -diff --git a/fs/jffs2/xattr.h b/fs/jffs2/xattr.h -index 3b0ff29..6e3b5dd 100644 ---- a/fs/jffs2/xattr.h -+++ b/fs/jffs2/xattr.h -@@ -75,7 +75,7 @@ extern void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); - extern void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c); - - extern struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, -- uint32_t xid, uint32_t version); -+ uint32_t xid, uint32_t version); - - extern void jffs2_xattr_delete_inode(struct jffs2_sb_info *c, struct jffs2_inode_cache *ic); - extern void jffs2_xattr_free_inode(struct jffs2_sb_info *c, struct jffs2_inode_cache *ic); -diff --git a/fs/jffs2/xattr_user.c b/fs/jffs2/xattr_user.c -index 40942bc..8bbeab9 100644 ---- a/fs/jffs2/xattr_user.c -+++ b/fs/jffs2/xattr_user.c -@@ -17,7 +17,7 @@ - #include "nodelist.h" - - static int jffs2_user_getxattr(struct inode *inode, const char *name, -- void *buffer, size_t size) -+ void *buffer, size_t size) - { - if (!strcmp(name, "")) - return -EINVAL; -@@ -25,7 +25,7 @@ static int jffs2_user_getxattr(struct inode *inode, const char *name, - } - - static int jffs2_user_setxattr(struct inode *inode, const char *name, const void *buffer, -- size_t size, int flags) -+ size_t size, int flags) - { - if (!strcmp(name, "")) - return -EINVAL; -diff --git a/fs/promfs/Makefile b/fs/promfs/Makefile -new file mode 100644 -index 0000000..940a51b ---- /dev/null -+++ b/fs/promfs/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_PROMFS_FS) += promfs.o -diff --git a/fs/promfs/promfs.c b/fs/promfs/promfs.c -new file mode 100644 -index 0000000..9fb2bfa ---- /dev/null -+++ b/fs/promfs/promfs.c -@@ -0,0 +1,295 @@ -+/* -+ * promfs.c - generic inode/dentry functions for IEEE 1275-based filesystems. -+ * -+ * This is based heavily upon prior ieee1275 and other virtual filesystems -+ * implementations; openpromfs, proc_devtree.c, oprofilefs, procfs, ... -+ * -+ * Copyright (C) 2007 Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+//#include -+#include -+ -+#define PROMFS_MAGIC 0x1f2f3fff -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Andres Salomon"); -+ -+struct promfs_inode -+{ -+ struct inode ino; -+ struct property *prop; -+}; -+ -+static inline struct promfs_inode *to_promfs_inode(struct inode *inode) -+{ -+ return container_of(inode, struct promfs_inode, ino); -+} -+ -+#if 0 -+static DEFINE_SPINLOCK(promfs_lock); -+ -+static struct of_node *of_tree = NULL; -+static DEFINE_RWLOCK(of_tree_lock); -+ -+void __init of_build_tree(void) -+{ -+ -+ -+} -+#endif -+ -+static int promfs_open_file(struct inode *inode, struct file *file) -+{ -+ struct promfs_inode *ino; -+ -+ ino = to_promfs_inode(inode); -+ if (!ino->prop) -+ return -EIO; -+ file->private_data = ino->prop; -+ -+ return 0; -+} -+ -+static ssize_t promfs_read_file(struct file *file, char __user *data, -+ size_t len, loff_t *ppos) -+{ -+ struct property *prop = (struct property *) file->private_data; -+ return simple_read_from_buffer(data, len, ppos, prop->value, -+ prop->length); -+} -+ -+static ssize_t promfs_write_file(struct file *file, char const __user *buf, -+ size_t count, loff_t * offset) -+{ -+ /* TODO.... 'cause, y'know, it would be nice. */ -+ return -EIO; -+} -+ -+static struct file_operations promfs_file_ops = { -+ .open = promfs_open_file, -+ .read = promfs_read_file, -+ .write = promfs_write_file, -+}; -+ -+static struct kmem_cache *promfs_inode_cachep; -+ -+static struct inode *promfs_alloc_inode(struct super_block *sb) -+{ -+ struct promfs_inode *pr_ino; -+ -+ pr_ino = kmem_cache_alloc(promfs_inode_cachep, GFP_KERNEL); -+ if (!pr_ino) -+ return NULL; -+ pr_ino->prop = NULL; -+ -+ return &pr_ino->ino; -+} -+ -+static void promfs_destroy_inode(struct inode *inode) -+{ -+ kmem_cache_free(promfs_inode_cachep, to_promfs_inode(inode)); -+} -+ -+static void promfs_read_inode(struct inode *inode) -+{ -+ inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME; -+} -+ -+static int promfs_remount(struct super_block *sb, int *flags, char *data) -+{ -+ *flags |= MS_NOATIME; -+ return 0; -+} -+ -+static struct super_operations promfs_s_ops = { -+ .alloc_inode = promfs_alloc_inode, -+ .destroy_inode = promfs_destroy_inode, -+ .read_inode = promfs_read_inode, -+ .statfs = simple_statfs, -+ .drop_inode = generic_delete_inode, -+ .remount_fs = promfs_remount, -+}; -+ -+static struct inode *promfs_get_inode(struct super_block *sb, int mode) -+{ -+ struct inode *inode = new_inode(sb); -+ -+ if (inode) { -+ inode->i_mode = mode; -+ inode->i_uid = 0; -+ inode->i_gid = 0; -+ inode->i_blocks = 0; -+ inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME; -+ } -+ -+ return inode; -+} -+ -+static int promfs_create_file(struct super_block *sb, struct dentry *root, -+ struct property *prop, const struct file_operations *fops) -+{ -+ struct dentry *dentry; -+ struct inode *inode; -+ struct promfs_inode *ino; -+ -+ dentry = d_alloc_name(root, prop->name); -+ if (!dentry) -+ goto err; -+ -+ inode = promfs_get_inode(sb, S_IFREG | 0644); -+ if (!inode) -+ goto err_dput; -+ inode->i_fop = fops; -+ ino = to_promfs_inode(inode); -+ ino->prop = prop; -+ d_add(dentry, inode); -+ -+ return 0; -+ -+err_dput: -+ dput(dentry); -+err: -+ return -EFAULT; -+} -+ -+struct dentry *promfs_create_dir(struct super_block *sb, struct dentry *root, -+ char const *name) -+{ -+ struct dentry *dentry; -+ struct inode *inode; -+ -+ dentry = d_alloc_name(root, name); -+ if (!dentry) -+ goto err; -+ -+ inode = promfs_get_inode(sb, S_IFDIR | 0755); -+ if (!inode) -+ goto err_dput; -+ inode->i_op = &simple_dir_inode_operations; -+ inode->i_fop = &simple_dir_operations; -+ d_add(dentry, inode); -+ return dentry; -+ -+err_dput: -+ dput(dentry); -+err: -+ return NULL; -+} -+ -+void promfs_populate(struct super_block *sb, struct dentry *root, -+ struct device_node *node) -+{ -+ struct dentry *dentry; -+ struct device_node *child; -+ struct property *prop; -+ -+ if (!node) -+ return; -+ -+ for (child = node->child; child; child = child->sibling) { -+ dentry = promfs_create_dir(sb, root, child->path_component_name); -+ promfs_populate(sb, dentry, child); -+ } -+ for (prop = node->properties; prop; prop = prop->next) -+ promfs_create_file(sb, root, prop, &promfs_file_ops); -+} -+ -+static int promfs_fill_super(struct super_block *sb, void *data, int silent) -+{ -+ struct inode *root_inode; -+ struct dentry *root_dentry; -+ struct promfs_inode *inode; -+ -+ sb->s_blocksize = PAGE_CACHE_SIZE; -+ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; -+ sb->s_magic = PROMFS_MAGIC; -+ sb->s_op = &promfs_s_ops; -+ sb->s_time_gran = 1; -+ sb->s_flags |= MS_NOATIME; -+ -+ root_inode = promfs_get_inode(sb, S_IFDIR | 0755); -+ if (!root_inode) -+ goto err; -+ root_inode->i_op = &simple_dir_inode_operations; -+ root_inode->i_fop = &simple_dir_operations; -+ -+ inode = to_promfs_inode(root_inode); -+ -+ root_dentry = d_alloc_root(root_inode); -+ if (!root_dentry) -+ goto err_iput; -+ sb->s_root = root_dentry; -+ -+ promfs_populate(sb, root_dentry, of_find_node_by_path("/")); -+ return 0; -+ -+err_iput: -+ iput(root_inode); -+err: -+ return -ENOMEM; -+} -+ -+static int promfs_get_sb(struct file_system_type *fs_type, int flags, -+ const char *dev_name, void *data, struct vfsmount *mnt) -+{ -+ return get_sb_single(fs_type, flags, data, promfs_fill_super, mnt); -+} -+ -+static struct file_system_type promfs_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "promfs", -+ .get_sb = promfs_get_sb, -+ .kill_sb = kill_litter_super, -+}; -+ -+static void init_once(void *i, struct kmem_cache *cachep, unsigned long fl) -+{ -+ struct promfs_inode *inode = (struct promfs_inode *) i; -+ inode_init_once(&inode->ino); -+} -+ -+static int __init init_promfs(void) -+{ -+ int err; -+ -+ prom_build_devicetree(); -+ promfs_inode_cachep = kmem_cache_create("promfs_inode_cache", -+ sizeof(struct promfs_inode), 0, -+ SLAB_RECLAIM_ACCOUNT|SLAB_MEM_SPREAD, init_once, NULL); -+ if (!promfs_inode_cachep) -+ return -ENOMEM; -+ -+ err = register_filesystem(&promfs_fs_type); -+ if (err) -+ kmem_cache_destroy(promfs_inode_cachep); -+ -+ return err; -+} -+ -+static void __exit exit_promfs(void) -+{ -+ unregister_filesystem(&promfs_fs_type); -+ kmem_cache_destroy(promfs_inode_cachep); -+} -+ -+module_init(init_promfs); -+module_exit(exit_promfs); ++ return -ENOMEM; ++ } ++#endif + return 0; + } + + void jffs2_nand_flash_cleanup(struct jffs2_sb_info *c) + { ++#ifdef CONFIG_JFFS2_FS_WBUF_VERIFY ++ kfree(c->wbuf_verify); ++#endif + kfree(c->wbuf); + kfree(c->oobbuf); + } +diff --git a/fs/jffs2/xattr.h b/fs/jffs2/xattr.h +index 3b0ff29..6e3b5dd 100644 +--- a/fs/jffs2/xattr.h ++++ b/fs/jffs2/xattr.h +@@ -75,7 +75,7 @@ extern void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); + extern void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c); + + extern struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, +- uint32_t xid, uint32_t version); ++ uint32_t xid, uint32_t version); + + extern void jffs2_xattr_delete_inode(struct jffs2_sb_info *c, struct jffs2_inode_cache *ic); + extern void jffs2_xattr_free_inode(struct jffs2_sb_info *c, struct jffs2_inode_cache *ic); +diff --git a/fs/jffs2/xattr_user.c b/fs/jffs2/xattr_user.c +index 40942bc..8bbeab9 100644 +--- a/fs/jffs2/xattr_user.c ++++ b/fs/jffs2/xattr_user.c +@@ -17,7 +17,7 @@ + #include "nodelist.h" + + static int jffs2_user_getxattr(struct inode *inode, const char *name, +- void *buffer, size_t size) ++ void *buffer, size_t size) + { + if (!strcmp(name, "")) + return -EINVAL; +@@ -25,7 +25,7 @@ static int jffs2_user_getxattr(struct inode *inode, const char *name, + } + + static int jffs2_user_setxattr(struct inode *inode, const char *name, const void *buffer, +- size_t size, int flags) ++ size_t size, int flags) + { + if (!strcmp(name, "")) + return -EINVAL; diff --git a/include/asm-i386/geode.h b/include/asm-i386/geode.h index 6da4bbb..f18ebe2 100644 --- a/include/asm-i386/geode.h @@ -17414,264 +5729,7 @@ index 6da4bbb..f18ebe2 100644 /* Specific geode tests */ static inline int is_geode_gx(void) -diff --git a/include/asm-i386/ofw.h b/include/asm-i386/ofw.h -new file mode 100644 -index 0000000..79b08b1 ---- /dev/null -+++ b/include/asm-i386/ofw.h -@@ -0,0 +1,16 @@ -+/* -+ * Definitions for Open Firmware client interface on 32-bit system. -+ * OF Cell size is 4. Integer properties are encoded big endian, -+ * as with all OF implementations. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+#ifndef _OFW_H -+#define _OFW_H -+ -+extern int ofw(char *, int, int, ...); -+ -+#endif -diff --git a/include/asm-i386/olpc.h b/include/asm-i386/olpc.h -new file mode 100644 -index 0000000..26bc1a8 ---- /dev/null -+++ b/include/asm-i386/olpc.h -@@ -0,0 +1,116 @@ -+/* OLPC machine specific definitions */ -+ -+#ifndef ASM_OLPC_H_ -+#define ASM_OLPC_H_ -+ -+#include -+ -+struct olpc_platform_t { -+ int flags; -+ int boardrev; -+ int ecver; -+}; -+ -+#define OLPC_F_PRESENT 0x01 -+#define OLPC_F_DCON 0x02 -+#define OLPC_F_VSA 0x04 -+ -+enum -+{ -+ OLPC_REV_A = 0, -+ -+ OLPC_REV_PRE_B1, -+ OLPC_REV_B1, -+ OLPC_REV_PRE_B2, -+ OLPC_REV_B2, -+ OLPC_REV_PRE_B3, -+ OLPC_REV_B3, -+ OLPC_REV_B4, -+ OLPC_REV_C1, -+ OLPC_REV_R1, -+ OLPC_REV_UNKNOWN /* this should always come last */ -+}; -+ -+#ifndef CONFIG_OLPC -+ -+static inline int machine_is_olpc(void) { return 0; } -+static inline int olpc_has_dcon(void) { return 0; } -+static inline int olpc_has_vsa(void) { return 0; } -+static inline int olpc_get_rev(void) { return OLPC_REV_UNKNOWN; } -+ -+#else -+ -+extern struct olpc_platform_t olpc_platform_info; -+ -+static inline int -+machine_is_olpc(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0; -+} -+ -+static inline int -+olpc_has_dcon(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0; -+} -+ -+static inline int -+olpc_has_vsa(void) -+{ -+ return (olpc_platform_info.flags & OLPC_F_VSA) ? 1 : 0; -+} -+ -+static inline int -+olpc_get_rev(void) -+{ -+ return olpc_platform_info.boardrev; -+} -+ -+static inline int -+olpc_rev_after(int rev) -+{ -+ return olpc_platform_info.boardrev > rev && -+ olpc_platform_info.boardrev != OLPC_REV_UNKNOWN; -+} -+ -+static inline int -+olpc_rev_before(int rev) -+{ -+ return olpc_platform_info.boardrev < rev || -+ olpc_platform_info.boardrev == OLPC_REV_UNKNOWN; -+} -+ -+#endif -+ -+/* EC functions */ -+ -+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, -+ unsigned char *outbuf, size_t outlen); -+ -+void olpc_register_battery_callback(void (*f)(unsigned long)); -+void olpc_deregister_battery_callback(void); -+ -+/* EC commands and responses */ -+ -+/* SCI source values */ -+ -+#define EC_SCI_SRC_EMPTY 0x00 -+#define EC_SCI_SRC_GAME 0x01 -+#define EC_SCI_SRC_BATTERY 0x02 -+#define EC_SCI_SRC_BATSOC 0x04 -+#define EC_SCI_SRC_BATERR 0x08 -+#define EC_SCI_SRC_EBOOK 0x10 -+#define EC_SCI_SRC_WLAN 0x20 -+#define EC_SCI_SRC_ACPWR 0x40 -+ -+/* GPIO assignments */ -+ -+#define OLPC_GPIO_MIC_AC 1 -+#define OLPC_GPIO_DCON_IRQ 7 -+#define OLPC_GPIO_THRM_ALRM 10 -+#define OLPC_GPIO_WORKAUX 24 -+#define OLPC_GPIO_LID 26 -+#define OLPC_GPIO_ECSCI 27 -+ -+#endif -+ -diff --git a/include/asm-i386/prom.h b/include/asm-i386/prom.h -new file mode 100644 -index 0000000..59d3bdd ---- /dev/null -+++ b/include/asm-i386/prom.h -@@ -0,0 +1,108 @@ -+#ifndef _I386_PROM_H -+#define _I386_PROM_H -+#ifdef __KERNEL__ -+ -+ -+/* -+ * Definitions for talking to the Open Firmware PROM on -+ * Power Macintosh computers. -+ * -+ * Copyright (C) 1996-2005 Paul Mackerras. -+ * -+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp. -+ * Updates for SPARC64 by David S. Miller -+ * Updates for i386/OLPC by Andres Salomon -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+ -+typedef u32 phandle; -+typedef u32 ihandle; -+ -+struct property { -+ char *name; -+ int length; -+ void *value; -+ struct property *next; -+}; -+ -+struct device_node { -+ const char *name; -+ const char *type; -+ phandle node; -+// phandle linux_phandle; -+ char *path_component_name; -+ char *full_name; -+ -+ struct property *properties; -+ struct property *deadprops; /* removed properties */ -+ struct device_node *parent; -+ struct device_node *child; -+ struct device_node *sibling; -+ struct device_node *next; /* next device of same type */ -+ struct device_node *allnext; /* next in list of all nodes */ -+ struct proc_dir_entry *pde; /* this node's proc directory */ -+ struct kref kref; -+ unsigned long _flags; -+ void *data; -+}; -+ -+/* flag descriptions */ -+#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ -+ -+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) -+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) -+ -+#define OF_BAD_ADDR ((u64)-1) -+ -+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de) -+{ -+ dn->pde = de; -+} -+ -+extern struct device_node *of_find_node_by_name(struct device_node *from, -+ const char *name); -+#define for_each_node_by_name(dn, name) \ -+ for (dn = of_find_node_by_name(NULL, name); dn; \ -+ dn = of_find_node_by_name(dn, name)) -+extern struct device_node *of_find_node_by_type(struct device_node *from, -+ const char *type); -+#define for_each_node_by_type(dn, type) \ -+ for (dn = of_find_node_by_type(NULL, type); dn; \ -+ dn = of_find_node_by_type(dn, type)) -+extern struct device_node *of_find_compatible_node(struct device_node *from, -+ const char *type, const char *compat); -+extern struct device_node *of_find_node_by_path(const char *path); -+extern struct device_node *of_find_node_by_phandle(phandle handle); -+extern struct device_node *of_get_parent(const struct device_node *node); -+extern struct device_node *of_get_next_child(const struct device_node *node, -+ struct device_node *prev); -+extern struct property *of_find_property(const struct device_node *np, -+ const char *name, -+ int *lenp); -+//extern struct device_node *of_node_get(struct device_node *node); -+//extern void of_node_put(struct device_node *node); -+extern int of_device_is_compatible(const struct device_node *device, -+ const char *); -+extern const void *of_get_property(const struct device_node *node, -+ const char *name, -+ int *lenp); -+#define get_property(node,name,lenp) of_get_property(node,name,lenp) -+extern int of_set_property(struct device_node *node, const char *name, void *val, int len); -+extern int of_getintprop_default(struct device_node *np, -+ const char *name, -+ int def); -+extern int of_n_addr_cells(struct device_node *np); -+extern int of_n_size_cells(struct device_node *np); -+ -+extern void prom_build_devicetree(void); -+ -+#endif /* __KERNEL__ */ -+#endif + diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h index 7862fe8..d7146c0 100644 --- a/include/asm-i386/setup.h @@ -17684,113 +5742,6 @@ index 7862fe8..d7146c0 100644 #ifndef __ASSEMBLY__ -diff --git a/include/linux/battery.h b/include/linux/battery.h -new file mode 100644 -index 0000000..2f856a0 ---- /dev/null -+++ b/include/linux/battery.h -@@ -0,0 +1,101 @@ -+/* -+ * Driver model for batteries -+ * -+ * © 2006 David Woodhouse -+ * -+ * Based on LED Class support, by John Lenz and Richard Purdie: -+ * -+ * © 2005 John Lenz -+ * © 2005-2006 Richard Purdie -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __LINUX_BATTERY_H__ -+#define __LINUX_BATTERY_H__ -+ -+struct device; -+struct class_device; -+ -+/* -+ * Battery Core -+ */ -+#define PWRDEV_TYPE_BATTERY 0 -+#define PWRDEV_TYPE_AC 1 -+ -+#define BAT_STAT_PRESENT (1<<0) -+#define BAT_STAT_LOW (1<<1) -+#define BAT_STAT_FULL (1<<2) -+#define BAT_STAT_CHARGING (1<<3) -+#define BAT_STAT_DISCHARGING (1<<4) -+#define BAT_STAT_OVERTEMP (1<<5) -+#define BAT_STAT_CRITICAL (1<<6) -+#define BAT_STAT_FIRE (1<<7) -+#define BAT_STAT_CHARGE_DONE (1<<8) -+ -+/* Thou shalt not export any attributes in sysfs except these, and -+ with these units: */ -+#define BAT_INFO_STATUS "status" /* Not free-form. Use -+ provided function */ -+#define BAT_INFO_TEMP1 "temp1" /* °C/1000 */ -+#define BAT_INFO_TEMP1_NAME "temp1_name" /* string */ -+ -+#define BAT_INFO_TEMP2 "temp2" /* °C/1000 */ -+#define BAT_INFO_TEMP2_NAME "temp2_name" /* string */ -+ -+#define BAT_INFO_VOLTAGE "voltage" /* mV */ -+#define BAT_INFO_VOLTAGE_DESIGN "voltage_design" /* mV */ -+ -+#define BAT_INFO_CURRENT "current" /* mA */ -+#define BAT_INFO_CURRENT_NOW "current_now" /* mA */ -+ -+#define BAT_INFO_POWER "power" /* mW */ -+#define BAT_INFO_POWER_NOW "power_now" /* mW */ -+ -+/* The following capacity/charge properties are represented in either -+ mA or mW. The CAP_UNITS property MUST be provided if any of these are. */ -+#define BAT_INFO_RATE "rate" /* CAP_UNITS */ -+#define BAT_INFO_CAP_LEFT "capacity_left" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_DESIGN "capacity_design" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_LAST_FULL "capacity_last_full" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_LOW "capacity_low_thresh" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_WARN "capacity_warn_thresh" /* CAP_UNITS*h */ -+#define BAT_INFO_CAP_UNITS "capacity_units" /* string: must be -+ either mA or mW */ -+ -+#define BAT_INFO_CAP_PCT "capacity_percentage" /* integer */ -+ -+#define BAT_INFO_TIME_EMPTY "time_to_empty" /* seconds */ -+#define BAT_INFO_TIME_EMPTY_NOW "time_to_empty_now" /* seconds */ -+#define BAT_INFO_TIME_FULL "time_to_full" /* seconds */ -+#define BAT_INFO_TIME_FULL_NOW "time_to_full_now" /* seconds */ -+ -+#define BAT_INFO_MANUFACTURER "manufacturer" /* string */ -+#define BAT_INFO_TECHNOLOGY "technology" /* string */ -+#define BAT_INFO_MODEL "model" /* string */ -+#define BAT_INFO_SERIAL "serial" /* string */ -+#define BAT_INFO_OEM_INFO "oem_info" /* string */ -+ -+#define BAT_INFO_CYCLE_COUNT "cycle_count" /* integer */ -+#define BAT_INFO_DATE_MFR "date_manufactured" /* YYYY[-MM[-DD]] */ -+#define BAT_INFO_DATE_FIRST_USE "date_first_use" /* YYYY[-MM[-DD]] */ -+ -+struct battery_dev { -+ int status_cap; -+ int id; -+ int type; -+ const char *name; -+ -+ struct device *dev; -+}; -+ -+int battery_device_register(struct device *parent, -+ struct battery_dev *battery_cdev); -+void battery_device_unregister(struct battery_dev *battery_cdev); -+ -+ -+ssize_t battery_attribute_show_status(char *buf, unsigned long status); -+ssize_t battery_attribute_show_ac_status(char *buf, unsigned long status); -+#endif /* __LINUX_BATTERY_H__ */ diff --git a/include/linux/console.h b/include/linux/console.h index 56a7bcd..1a8b034 100644 --- a/include/linux/console.h @@ -17839,139 +5790,6 @@ index cec5410..6b59db5 100644 extern struct fb_info *registered_fb[FB_MAX]; extern int num_registered_fb; extern struct class *fb_class; -diff --git a/include/linux/isl_38xx.h b/include/linux/isl_38xx.h -new file mode 100644 -index 0000000..c7e98f2 ---- /dev/null -+++ b/include/linux/isl_38xx.h -@@ -0,0 +1,127 @@ -+/* -+ * Copyright (C) 2002 Intersil Americas Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _LINUX_ISL_38XX_H -+#define _LINUX_ISL_38XX_H -+ -+#include -+ -+#define ISL38XX_CB_RX_QSIZE 8 -+#define ISL38XX_CB_TX_QSIZE 32 -+ -+/* ISL38XX Access Point Specific definitions */ -+#define ISL38XX_MAX_WDS_LINKS 8 -+ -+/* ISL38xx Client Specific definitions */ -+#define ISL38XX_PSM_ACTIVE_STATE 0 -+#define ISL38XX_PSM_POWERSAVE_STATE 1 -+ -+/* ISL38XX Host Interface Definitions */ -+#define ISL38XX_PCI_MEM_SIZE 0x02000 -+#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000 -+#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000 -+#define ISL38XX_WRITEIO_DELAY 10 /* in us */ -+#define ISL38XX_RESET_DELAY 50 /* in ms */ -+#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */ -+#define ISL38XX_MAX_WAIT_CYCLES 10 -+ -+/* PCI Memory Area */ -+#define ISL38XX_HARDWARE_REG 0x0000 -+#define ISL38XX_CARDBUS_CIS 0x0800 -+#define ISL38XX_DIRECT_MEM_WIN 0x1000 -+ -+/* Hardware registers */ -+#define ISL38XX_DEV_INT_REG 0x0000 -+#define ISL38XX_INT_IDENT_REG 0x0010 -+#define ISL38XX_INT_ACK_REG 0x0014 -+#define ISL38XX_INT_EN_REG 0x0018 -+#define ISL38XX_GEN_PURP_COM_REG_1 0x0020 -+#define ISL38XX_GEN_PURP_COM_REG_2 0x0024 -+#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1 -+#define ISL38XX_DIR_MEM_BASE_REG 0x0030 -+#define ISL38XX_CTRL_STAT_REG 0x0078 -+ -+/* High end mobos queue up pci writes, the following -+ * is used to "read" from after a write to force flush */ -+#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG -+ -+/** -+ * isl38xx_w32_flush - PCI iomem write helper -+ * @base: (host) memory base address of the device -+ * @val: 32bit value (host order) to write -+ * @offset: byte offset into @base to write value to -+ * -+ * This helper takes care of writing a 32bit datum to the -+ * specified offset into the device's pci memory space, and making sure -+ * the pci memory buffers get flushed by performing one harmless read -+ * from the %ISL38XX_PCI_POSTING_FLUSH offset. -+ */ -+static inline void -+isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset) -+{ -+ writel(val, base + offset); -+ (void) readl(base + ISL38XX_PCI_POSTING_FLUSH); -+} -+ -+/* Device Interrupt register bits */ -+#define ISL38XX_DEV_INT_RESET 0x0001 -+#define ISL38XX_DEV_INT_UPDATE 0x0002 -+#define ISL38XX_DEV_INT_WAKEUP 0x0008 -+#define ISL38XX_DEV_INT_SLEEP 0x0010 -+#define ISL38XX_DEV_INT_ABORT 0x0020 -+/* thos two only used in USB */ -+#define ISL38XX_DEV_INT_DATA 0x0040 -+#define ISL38XX_DEV_INT_MGMT 0x0080 -+ -+#define ISL38XX_DEV_INT_PCIUART_CTS 0x4000 -+#define ISL38XX_DEV_INT_PCIUART_DR 0x8000 -+ -+/* Interrupt Identification/Acknowledge/Enable register bits */ -+#define ISL38XX_INT_IDENT_UPDATE 0x0002 -+#define ISL38XX_INT_IDENT_INIT 0x0004 -+#define ISL38XX_INT_IDENT_WAKEUP 0x0008 -+#define ISL38XX_INT_IDENT_SLEEP 0x0010 -+#define ISL38XX_INT_IDENT_PCIUART_CTS 0x4000 -+#define ISL38XX_INT_IDENT_PCIUART_DR 0x8000 -+ -+#define ISL38XX_INT_SOURCES (ISL38XX_INT_IDENT_UPDATE | \ -+ ISL38XX_INT_IDENT_INIT | \ -+ ISL38XX_INT_IDENT_WAKEUP | \ -+ ISL38XX_INT_IDENT_SLEEP | \ -+ ISL38XX_INT_IDENT_PCIUART_CTS | \ -+ ISL38XX_INT_IDENT_PCIUART_DR) -+ -+/* Control/Status register bits */ -+/* Looks like there are other meaningful bits -+ 0x20004400 seen in normal operation, -+ 0x200044db at 'timeout waiting for mgmt response' -+*/ -+#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200 -+#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000 -+#define ISL38XX_CTRL_STAT_RESET 0x10000000 -+#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000 -+#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000 -+#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000 -+ -+/* Some flags for the isl hardware registers controlling DMA inside the -+ * chip */ -+#define ISL38XX_DMA_STATUS_DONE 0x00000001 -+#define ISL38XX_DMA_STATUS_READY 0x00000002 -+#define NET2280_EPA_FIFO_PCI_ADDR 0x20000000 -+#define ISL38XX_DMA_MASTER_CONTROL_TRIGGER 0x00000004 -+ -+#endif /* _LINUX_ISL_38XX_H */ diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index a56d24a..fd0a260 100644 --- a/include/linux/mtd/onenand.h @@ -18073,23 +5891,6 @@ index 699b7e9..b44facf 100644 +} + #endif /* _VT_KERN_H */ -diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h -index 246ac23..874a2c8 100644 ---- a/include/sound/ac97_codec.h -+++ b/include/sound/ac97_codec.h -@@ -281,10 +281,12 @@ - /* specific - Analog Devices */ - #define AC97_AD_TEST 0x5a /* test register */ - #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */ -+#define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */ - #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ - #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ - #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ - #define AC97_AD_MISC 0x76 /* Misc Control Bits */ -+#define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */ - - /* specific - Cirrus Logic */ - #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ diff --git a/kernel/power/console.c b/kernel/power/console.c index 89bcf49..dca98f5 100644 --- a/kernel/power/console.c @@ -18103,516 +5904,3 @@ index 89bcf49..dca98f5 100644 #define SUSPEND_CONSOLE (MAX_NR_CONSOLES-1) static int orig_fgconsole, orig_kmsg; -diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c -index bbed644..090e852 100644 ---- a/sound/pci/ac97/ac97_codec.c -+++ b/sound/pci/ac97/ac97_codec.c -@@ -49,7 +49,7 @@ module_param(enable_loopback, bool, 0444); - MODULE_PARM_DESC(enable_loopback, "Enable AC97 ADC/DAC Loopback Control"); - - #ifdef CONFIG_SND_AC97_POWER_SAVE --static int power_save; -+static int power_save = 1; - module_param(power_save, bool, 0644); - MODULE_PARM_DESC(power_save, "Enable AC97 power-saving control"); - #endif -diff --git a/sound/pci/ac97/ac97_patch.c b/sound/pci/ac97/ac97_patch.c -index 581ebba..06637f7 100644 ---- a/sound/pci/ac97/ac97_patch.c -+++ b/sound/pci/ac97/ac97_patch.c -@@ -1973,8 +1973,9 @@ static const struct snd_kcontrol_new snd_ac97_ad1888_controls[] = { - .get = snd_ac97_ad1888_lohpsel_get, - .put = snd_ac97_ad1888_lohpsel_put - }, -- AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, 2, 1, 1), -- AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, 12, 1, 1), -+ AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, AC97_AD_VREFD_SHIFT, 1, 1), -+ AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, -+ AC97_AD_HPFD_SHIFT, 1, 1), - AC97_SINGLE("Spread Front to Surround and Center/LFE", AC97_AD_MISC, 7, 1, 0), - { - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -diff --git a/sound/pci/cs5535audio/Makefile b/sound/pci/cs5535audio/Makefile -index ad947b4..3866c4d 100644 ---- a/sound/pci/cs5535audio/Makefile -+++ b/sound/pci/cs5535audio/Makefile -@@ -8,5 +8,9 @@ ifeq ($(CONFIG_PM),y) - snd-cs5535audio-objs += cs5535audio_pm.o - endif - -+ifdef CONFIG_OLPC -+snd-cs5535audio-objs += cs5535audio_olpc.o -+endif -+ - # Toplevel Module Dependency - obj-$(CONFIG_SND_CS5535AUDIO) += snd-cs5535audio.o -diff --git a/sound/pci/cs5535audio/cs5535audio.c b/sound/pci/cs5535audio/cs5535audio.c -index b8e75ef..389d9da 100644 ---- a/sound/pci/cs5535audio/cs5535audio.c -+++ b/sound/pci/cs5535audio/cs5535audio.c -@@ -145,7 +145,7 @@ static unsigned short snd_cs5535audio_ac97_codec_read(struct snd_ac97 *ac97, - return snd_cs5535audio_codec_read(cs5535au, reg); - } - --static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) -+static int __devinit snd_cs5535audio_mixer(struct cs5535audio *cs5535au) - { - struct snd_card *card = cs5535au->card; - struct snd_ac97_bus *pbus; -@@ -160,10 +160,14 @@ static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) - return err; - - memset(&ac97, 0, sizeof(ac97)); -- ac97.scaps = AC97_SCAP_AUDIO|AC97_SCAP_SKIP_MODEM; -+ ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM -+ | AC97_SCAP_POWER_SAVE; - ac97.private_data = cs5535au; - ac97.pci = cs5535au->pci; - -+ /* olpc_prequirks is dummied out if not olpc */ -+ olpc_prequirks(card, &ac97); -+ - if ((err = snd_ac97_mixer(pbus, &ac97, &cs5535au->ac97)) < 0) { - snd_printk(KERN_ERR "mixer failed\n"); - return err; -@@ -171,6 +175,12 @@ static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) - - snd_ac97_tune_hardware(cs5535au->ac97, ac97_quirks, ac97_quirk); - -+ /* olpc_quirks is dummied out if not olpc */ -+ if (( err = olpc_quirks(card, cs5535au->ac97)) < 0) { -+ snd_printk(KERN_ERR "olpc quirks failed\n"); -+ return err; -+ } -+ - return 0; - } - -@@ -206,7 +216,6 @@ static void process_bm1_irq(struct cs5535audio *cs5535au) - static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) - { - u16 acc_irq_stat; -- u8 bm_stat; - unsigned char count; - struct cs5535audio *cs5535au = dev_id; - -@@ -217,7 +226,7 @@ static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) - - if (!acc_irq_stat) - return IRQ_NONE; -- for (count = 0; count < 10; count++) { -+ for (count = 0; count < 4; count++) { - if (acc_irq_stat & (1 << count)) { - switch (count) { - case IRQ_STS: -@@ -232,26 +241,9 @@ static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) - case BM1_IRQ_STS: - process_bm1_irq(cs5535au); - break; -- case BM2_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM2_STATUS); -- break; -- case BM3_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM3_STATUS); -- break; -- case BM4_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM4_STATUS); -- break; -- case BM5_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM5_STATUS); -- break; -- case BM6_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM6_STATUS); -- break; -- case BM7_IRQ_STS: -- bm_stat = cs_readb(cs5535au, ACC_BM7_STATUS); -- break; - default: -- snd_printk(KERN_ERR "Unexpected irq src\n"); -+ snd_printk(KERN_ERR "Unexpected irq src: " -+ "0x%x\n", acc_irq_stat); - break; - } - } -diff --git a/sound/pci/cs5535audio/cs5535audio.h b/sound/pci/cs5535audio/cs5535audio.h -index 4fd1f31..ff82f10 100644 ---- a/sound/pci/cs5535audio/cs5535audio.h -+++ b/sound/pci/cs5535audio/cs5535audio.h -@@ -16,57 +16,28 @@ - #define ACC_IRQ_STATUS 0x12 - #define ACC_BM0_CMD 0x20 - #define ACC_BM1_CMD 0x28 --#define ACC_BM2_CMD 0x30 --#define ACC_BM3_CMD 0x38 --#define ACC_BM4_CMD 0x40 --#define ACC_BM5_CMD 0x48 --#define ACC_BM6_CMD 0x50 --#define ACC_BM7_CMD 0x58 - #define ACC_BM0_PRD 0x24 - #define ACC_BM1_PRD 0x2C --#define ACC_BM2_PRD 0x34 --#define ACC_BM3_PRD 0x3C --#define ACC_BM4_PRD 0x44 --#define ACC_BM5_PRD 0x4C --#define ACC_BM6_PRD 0x54 --#define ACC_BM7_PRD 0x5C - #define ACC_BM0_STATUS 0x21 - #define ACC_BM1_STATUS 0x29 --#define ACC_BM2_STATUS 0x31 --#define ACC_BM3_STATUS 0x39 --#define ACC_BM4_STATUS 0x41 --#define ACC_BM5_STATUS 0x49 --#define ACC_BM6_STATUS 0x51 --#define ACC_BM7_STATUS 0x59 - #define ACC_BM0_PNTR 0x60 - #define ACC_BM1_PNTR 0x64 --#define ACC_BM2_PNTR 0x68 --#define ACC_BM3_PNTR 0x6C --#define ACC_BM4_PNTR 0x70 --#define ACC_BM5_PNTR 0x74 --#define ACC_BM6_PNTR 0x78 --#define ACC_BM7_PNTR 0x7C -+ - /* acc_codec bar0 reg bits */ - /* ACC_IRQ_STATUS */ - #define IRQ_STS 0 - #define WU_IRQ_STS 1 - #define BM0_IRQ_STS 2 - #define BM1_IRQ_STS 3 --#define BM2_IRQ_STS 4 --#define BM3_IRQ_STS 5 --#define BM4_IRQ_STS 6 --#define BM5_IRQ_STS 7 --#define BM6_IRQ_STS 8 --#define BM7_IRQ_STS 9 - /* ACC_BMX_STATUS */ - #define EOP (1<<0) - #define BM_EOP_ERR (1<<1) - /* ACC_BMX_CTL */ --#define BM_CTL_EN 0x00000001 --#define BM_CTL_PAUSE 0x00000011 --#define BM_CTL_DIS 0x00000000 --#define BM_CTL_BYTE_ORD_LE 0x00000000 --#define BM_CTL_BYTE_ORD_BE 0x00000100 -+#define BM_CTL_EN 0x01 -+#define BM_CTL_PAUSE 0x03 -+#define BM_CTL_DIS 0x00 -+#define BM_CTL_BYTE_ORD_LE 0x00 -+#define BM_CTL_BYTE_ORD_BE 0x04 - /* cs5535 specific ac97 codec register defines */ - #define CMD_MASK 0xFF00FFFF - #define CMD_NEW 0x00010000 -@@ -106,8 +77,8 @@ struct cs5535audio_dma { - struct snd_pcm_substream *substream; - unsigned int buf_addr, buf_bytes; - unsigned int period_bytes, periods; -- int suspended; - u32 saved_prd; -+ int pcm_open_flag; - }; - - struct cs5535audio { -@@ -123,8 +94,21 @@ struct cs5535audio { - struct cs5535audio_dma dmas[NUM_CS5535AUDIO_DMAS]; - }; - -+#ifdef CONFIG_PM - int snd_cs5535audio_suspend(struct pci_dev *pci, pm_message_t state); - int snd_cs5535audio_resume(struct pci_dev *pci); -+#endif -+ -+#ifdef CONFIG_OLPC -+void olpc_prequirks(struct snd_card *card, struct snd_ac97_template *ac97) __devinit; -+int olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97) __devinit; -+int olpc_ai_enable(struct snd_ac97 *ac97, u8 val); -+#else -+#define olpc_prequirks(arg,arg2) do {} while (0) -+#define olpc_quirks(arg,arg2) (0) -+#define olpc_ai_enable(a, v) (0) -+#endif -+ - int __devinit snd_cs5535audio_pcm(struct cs5535audio *cs5535audio); - - #endif /* __SOUND_CS5535AUDIO_H */ -diff --git a/sound/pci/cs5535audio/cs5535audio_olpc.c b/sound/pci/cs5535audio/cs5535audio_olpc.c -new file mode 100644 -index 0000000..791be73 ---- /dev/null -+++ b/sound/pci/cs5535audio/cs5535audio_olpc.c -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "cs5535audio.h" -+ -+/* -+ * OLPC has an additional feature on top of the regular AD1888 codec features. -+ * It has an Analog Input mode that is switched into (after disabling the -+ * High Pass Filter) via GPIO. It is only supported on B2 and later models. -+ */ -+ -+int olpc_ai_enable(struct snd_ac97 *ac97, u8 val) -+{ -+ int err; -+ -+ /* -+ * update the High Pass Filter (via AC97_AD_TEST2), and then set -+ * Analog Input mode through a GPIO. -+ */ -+ -+ if (val) { -+ err = snd_ac97_update_bits(ac97, AC97_AD_TEST2, -+ 1<type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; -+ uinfo->count = 1; -+ uinfo->value.integer.min = 0; -+ uinfo->value.integer.max = 1; -+ return 0; -+} -+ -+static int snd_cs5535audio_ai_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ ucontrol->value.integer.value[0] = geode_gpio_isset(OLPC_GPIO_MIC_AC, -+ GPIO_OUTPUT_VAL); -+ return 0; -+} -+ -+static int snd_cs5535audio_ai_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct cs5535audio *cs5535au = snd_kcontrol_chip(kcontrol); -+ struct snd_ac97 *ac97 = cs5535au->ac97; -+ -+ olpc_ai_enable(ac97, ucontrol->value.integer.value[0]); -+ -+ return 1; -+} -+ -+static struct snd_kcontrol_new snd_cs5535audio_controls __devinitdata = -+{ -+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -+ .name = "DC Mode Enable", -+ .info = snd_cs5535audio_ai_info, -+ .get = snd_cs5535audio_ai_get, -+ .put = snd_cs5535audio_ai_put, -+ .private_value = 0 -+}; -+ -+void __devinit olpc_prequirks(struct snd_card *card, -+ struct snd_ac97_template *ac97) -+{ -+ /* Bail if this isn't an OLPC platform */ -+ if (!machine_is_olpc()) -+ return; -+ -+ /* If on an OLPC B3 or higher, invert EAPD. */ -+ if (olpc_rev_after(OLPC_REV_B2)) -+ ac97->scaps |= AC97_SCAP_INV_EAPD; -+} -+ -+int __devinit olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97) -+{ -+ struct snd_ctl_elem_id elem; -+ -+ /* Bail if this isn't an OLPC platform */ -+ if (!machine_is_olpc()) -+ return 0; -+ -+ /* drop the original ad1888 HPF control */ -+ memset(&elem, 0, sizeof(elem)); -+ elem.iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ strcpy(elem.name, "High Pass Filter Enable"); -+ snd_ctl_remove_id(card, &elem); -+ -+ /* add the override for OLPC's HPF */ -+ return snd_ctl_add(card, snd_ctl_new1(&snd_cs5535audio_controls, -+ ac97->private_data)); -+} -diff --git a/sound/pci/cs5535audio/cs5535audio_pcm.c b/sound/pci/cs5535audio/cs5535audio_pcm.c -index 5450a9e..d23f8ea 100644 ---- a/sound/pci/cs5535audio/cs5535audio_pcm.c -+++ b/sound/pci/cs5535audio/cs5535audio_pcm.c -@@ -164,6 +164,7 @@ static int cs5535audio_build_dma_packets(struct cs5535audio *cs5535au, - jmpprd_addr = cpu_to_le32(lastdesc->addr + - (sizeof(struct cs5535audio_dma_desc)*periods)); - -+ dma->substream = substream; - dma->period_bytes = period_bytes; - dma->periods = periods; - spin_lock_irq(&cs5535au->reg_lock); -@@ -241,6 +242,7 @@ static void cs5535audio_clear_dma_packets(struct cs5535audio *cs5535au, - { - snd_dma_free_pages(&dma->desc_buf); - dma->desc_buf.area = NULL; -+ dma->substream = NULL; - } - - static int snd_cs5535audio_hw_params(struct snd_pcm_substream *substream, -@@ -260,6 +262,9 @@ static int snd_cs5535audio_hw_params(struct snd_pcm_substream *substream, - err = cs5535audio_build_dma_packets(cs5535au, dma, substream, - params_periods(hw_params), - params_period_bytes(hw_params)); -+ if (!err) -+ dma->pcm_open_flag = 1; -+ - return err; - } - -@@ -268,6 +273,15 @@ static int snd_cs5535audio_hw_free(struct snd_pcm_substream *substream) - struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); - struct cs5535audio_dma *dma = substream->runtime->private_data; - -+ if (dma->pcm_open_flag) { -+ if (substream == cs5535au->playback_substream) -+ snd_ac97_update_power(cs5535au->ac97, -+ AC97_PCM_FRONT_DAC_RATE, 0); -+ else -+ snd_ac97_update_power(cs5535au->ac97, -+ AC97_PCM_LR_ADC_RATE, 0); -+ dma->pcm_open_flag = 0; -+ } - cs5535audio_clear_dma_packets(cs5535au, dma, substream); - return snd_pcm_lib_free_pages(substream); - } -@@ -298,14 +312,12 @@ static int snd_cs5535audio_trigger(struct snd_pcm_substream *substream, int cmd) - break; - case SNDRV_PCM_TRIGGER_RESUME: - dma->ops->enable_dma(cs5535au); -- dma->suspended = 0; - break; - case SNDRV_PCM_TRIGGER_STOP: - dma->ops->disable_dma(cs5535au); - break; - case SNDRV_PCM_TRIGGER_SUSPEND: - dma->ops->disable_dma(cs5535au); -- dma->suspended = 1; - break; - default: - snd_printk(KERN_ERR "unhandled trigger\n"); -@@ -344,6 +356,7 @@ static int snd_cs5535audio_capture_open(struct snd_pcm_substream *substream) - int err; - struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); - struct snd_pcm_runtime *runtime = substream->runtime; -+ struct snd_ac97 *ac97 = cs5535au->ac97; - - runtime->hw = snd_cs5535audio_capture; - cs5535au->capture_substream = substream; -@@ -352,11 +365,29 @@ static int snd_cs5535audio_capture_open(struct snd_pcm_substream *substream) - if ((err = snd_pcm_hw_constraint_integer(runtime, - SNDRV_PCM_HW_PARAM_PERIODS)) < 0) - return err; -- return 0; -+ -+#ifdef CONFIG_OLPC -+ /* Disable Analog Input */ -+ olpc_ai_enable(ac97, 0); -+ /* Enable V_ref bias while recording. */ -+ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1<ac97; -+ -+ /* Disable Analog Input */ -+ olpc_ai_enable(ac97, 0); -+ /* Disable V_ref bias. */ -+ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1<pcm); -+ snd_ac97_suspend(cs5535au->ac97); - for (i = 0; i < NUM_CS5535AUDIO_DMAS; i++) { - struct cs5535audio_dma *dma = &cs5535au->dmas[i]; -- if (dma && dma->substream && !dma->suspended) -+ if (dma && dma->substream) - dma->saved_prd = dma->ops->read_prd(cs5535au); - } -- snd_pcm_suspend_all(cs5535au->pcm); -- snd_ac97_suspend(cs5535au->ac97); - /* save important regs, then disable aclink in hw */ - snd_cs5535audio_stop_hardware(cs5535au); - -+ if (pci_save_state(pci)) { -+ printk(KERN_ERR "cs5535audio: pci_save_state failed!\n"); -+ return -EIO; -+ } - pci_disable_device(pci); -- pci_save_state(pci); - pci_set_power_state(pci, pci_choose_state(pci, state)); - return 0; - } -@@ -89,7 +92,12 @@ int snd_cs5535audio_resume(struct pci_dev *pci) - int i; - - pci_set_power_state(pci, PCI_D0); -- pci_restore_state(pci); -+ if (pci_restore_state(pci) < 0) { -+ printk(KERN_ERR "cs5535audio: pci_restore_state failed, " -+ "disabling device\n"); -+ snd_card_disconnect(card); -+ return -EIO; -+ } - if (pci_enable_device(pci) < 0) { - printk(KERN_ERR "cs5535audio: pci_enable_device failed, " - "disabling device\n"); -@@ -112,17 +120,17 @@ int snd_cs5535audio_resume(struct pci_dev *pci) - if (!timeout) - snd_printk(KERN_ERR "Failure getting AC Link ready\n"); - -- /* we depend on ac97 to perform the codec power up */ -- snd_ac97_resume(cs5535au->ac97); - /* set up rate regs, dma. actual initiation is done in trig */ - for (i = 0; i < NUM_CS5535AUDIO_DMAS; i++) { - struct cs5535audio_dma *dma = &cs5535au->dmas[i]; -- if (dma && dma->substream && dma->suspended) { -+ if (dma && dma->substream) { - dma->substream->ops->prepare(dma->substream); - dma->ops->setup_prd(cs5535au, dma->saved_prd); - } - } -- -+ -+ /* we depend on ac97 to perform the codec power up */ -+ snd_ac97_resume(cs5535au->ac97); - snd_power_change_state(card, SNDRV_CTL_POWER_D0); - - return 0; diff --git a/target/linux/olpc/patches/110-olpc_sound.patch b/target/linux/olpc/patches/110-olpc_sound.patch new file mode 100644 index 000000000000..421ab283bc72 --- /dev/null +++ b/target/linux/olpc/patches/110-olpc_sound.patch @@ -0,0 +1,414 @@ +diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h +index 246ac23..874a2c8 100644 +--- a/include/sound/ac97_codec.h ++++ b/include/sound/ac97_codec.h +@@ -281,10 +281,12 @@ + /* specific - Analog Devices */ + #define AC97_AD_TEST 0x5a /* test register */ + #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */ ++#define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */ + #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ + #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ + #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ + #define AC97_AD_MISC 0x76 /* Misc Control Bits */ ++#define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */ + + /* specific - Cirrus Logic */ + #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ +diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c +index bbed644..090e852 100644 +--- a/sound/pci/ac97/ac97_codec.c ++++ b/sound/pci/ac97/ac97_codec.c +@@ -49,7 +49,7 @@ module_param(enable_loopback, bool, 0444); + MODULE_PARM_DESC(enable_loopback, "Enable AC97 ADC/DAC Loopback Control"); + + #ifdef CONFIG_SND_AC97_POWER_SAVE +-static int power_save; ++static int power_save = 1; + module_param(power_save, bool, 0644); + MODULE_PARM_DESC(power_save, "Enable AC97 power-saving control"); + #endif +diff --git a/sound/pci/ac97/ac97_patch.c b/sound/pci/ac97/ac97_patch.c +index 581ebba..06637f7 100644 +--- a/sound/pci/ac97/ac97_patch.c ++++ b/sound/pci/ac97/ac97_patch.c +@@ -1973,8 +1973,9 @@ static const struct snd_kcontrol_new snd_ac97_ad1888_controls[] = { + .get = snd_ac97_ad1888_lohpsel_get, + .put = snd_ac97_ad1888_lohpsel_put + }, +- AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, 2, 1, 1), +- AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, 12, 1, 1), ++ AC97_SINGLE("V_REFOUT Enable", AC97_AD_MISC, AC97_AD_VREFD_SHIFT, 1, 1), ++ AC97_SINGLE("High Pass Filter Enable", AC97_AD_TEST2, ++ AC97_AD_HPFD_SHIFT, 1, 1), + AC97_SINGLE("Spread Front to Surround and Center/LFE", AC97_AD_MISC, 7, 1, 0), + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, +diff --git a/sound/pci/cs5535audio/Makefile b/sound/pci/cs5535audio/Makefile +index ad947b4..3866c4d 100644 +--- a/sound/pci/cs5535audio/Makefile ++++ b/sound/pci/cs5535audio/Makefile +@@ -8,5 +8,9 @@ ifeq ($(CONFIG_PM),y) + snd-cs5535audio-objs += cs5535audio_pm.o + endif + ++ifdef CONFIG_OLPC ++snd-cs5535audio-objs += cs5535audio_olpc.o ++endif ++ + # Toplevel Module Dependency + obj-$(CONFIG_SND_CS5535AUDIO) += snd-cs5535audio.o +diff --git a/sound/pci/cs5535audio/cs5535audio.c b/sound/pci/cs5535audio/cs5535audio.c +index b8e75ef..389d9da 100644 +--- a/sound/pci/cs5535audio/cs5535audio.c ++++ b/sound/pci/cs5535audio/cs5535audio.c +@@ -145,7 +145,7 @@ static unsigned short snd_cs5535audio_ac97_codec_read(struct snd_ac97 *ac97, + return snd_cs5535audio_codec_read(cs5535au, reg); + } + +-static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) ++static int __devinit snd_cs5535audio_mixer(struct cs5535audio *cs5535au) + { + struct snd_card *card = cs5535au->card; + struct snd_ac97_bus *pbus; +@@ -160,10 +160,14 @@ static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) + return err; + + memset(&ac97, 0, sizeof(ac97)); +- ac97.scaps = AC97_SCAP_AUDIO|AC97_SCAP_SKIP_MODEM; ++ ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM ++ | AC97_SCAP_POWER_SAVE; + ac97.private_data = cs5535au; + ac97.pci = cs5535au->pci; + ++ /* olpc_prequirks is dummied out if not olpc */ ++ olpc_prequirks(card, &ac97); ++ + if ((err = snd_ac97_mixer(pbus, &ac97, &cs5535au->ac97)) < 0) { + snd_printk(KERN_ERR "mixer failed\n"); + return err; +@@ -171,6 +175,12 @@ static int snd_cs5535audio_mixer(struct cs5535audio *cs5535au) + + snd_ac97_tune_hardware(cs5535au->ac97, ac97_quirks, ac97_quirk); + ++ /* olpc_quirks is dummied out if not olpc */ ++ if (( err = olpc_quirks(card, cs5535au->ac97)) < 0) { ++ snd_printk(KERN_ERR "olpc quirks failed\n"); ++ return err; ++ } ++ + return 0; + } + +@@ -206,7 +216,6 @@ static void process_bm1_irq(struct cs5535audio *cs5535au) + static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) + { + u16 acc_irq_stat; +- u8 bm_stat; + unsigned char count; + struct cs5535audio *cs5535au = dev_id; + +@@ -217,7 +226,7 @@ static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) + + if (!acc_irq_stat) + return IRQ_NONE; +- for (count = 0; count < 10; count++) { ++ for (count = 0; count < 4; count++) { + if (acc_irq_stat & (1 << count)) { + switch (count) { + case IRQ_STS: +@@ -232,26 +241,9 @@ static irqreturn_t snd_cs5535audio_interrupt(int irq, void *dev_id) + case BM1_IRQ_STS: + process_bm1_irq(cs5535au); + break; +- case BM2_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM2_STATUS); +- break; +- case BM3_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM3_STATUS); +- break; +- case BM4_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM4_STATUS); +- break; +- case BM5_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM5_STATUS); +- break; +- case BM6_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM6_STATUS); +- break; +- case BM7_IRQ_STS: +- bm_stat = cs_readb(cs5535au, ACC_BM7_STATUS); +- break; + default: +- snd_printk(KERN_ERR "Unexpected irq src\n"); ++ snd_printk(KERN_ERR "Unexpected irq src: " ++ "0x%x\n", acc_irq_stat); + break; + } + } +diff --git a/sound/pci/cs5535audio/cs5535audio.h b/sound/pci/cs5535audio/cs5535audio.h +index 4fd1f31..ff82f10 100644 +--- a/sound/pci/cs5535audio/cs5535audio.h ++++ b/sound/pci/cs5535audio/cs5535audio.h +@@ -16,57 +16,28 @@ + #define ACC_IRQ_STATUS 0x12 + #define ACC_BM0_CMD 0x20 + #define ACC_BM1_CMD 0x28 +-#define ACC_BM2_CMD 0x30 +-#define ACC_BM3_CMD 0x38 +-#define ACC_BM4_CMD 0x40 +-#define ACC_BM5_CMD 0x48 +-#define ACC_BM6_CMD 0x50 +-#define ACC_BM7_CMD 0x58 + #define ACC_BM0_PRD 0x24 + #define ACC_BM1_PRD 0x2C +-#define ACC_BM2_PRD 0x34 +-#define ACC_BM3_PRD 0x3C +-#define ACC_BM4_PRD 0x44 +-#define ACC_BM5_PRD 0x4C +-#define ACC_BM6_PRD 0x54 +-#define ACC_BM7_PRD 0x5C + #define ACC_BM0_STATUS 0x21 + #define ACC_BM1_STATUS 0x29 +-#define ACC_BM2_STATUS 0x31 +-#define ACC_BM3_STATUS 0x39 +-#define ACC_BM4_STATUS 0x41 +-#define ACC_BM5_STATUS 0x49 +-#define ACC_BM6_STATUS 0x51 +-#define ACC_BM7_STATUS 0x59 + #define ACC_BM0_PNTR 0x60 + #define ACC_BM1_PNTR 0x64 +-#define ACC_BM2_PNTR 0x68 +-#define ACC_BM3_PNTR 0x6C +-#define ACC_BM4_PNTR 0x70 +-#define ACC_BM5_PNTR 0x74 +-#define ACC_BM6_PNTR 0x78 +-#define ACC_BM7_PNTR 0x7C ++ + /* acc_codec bar0 reg bits */ + /* ACC_IRQ_STATUS */ + #define IRQ_STS 0 + #define WU_IRQ_STS 1 + #define BM0_IRQ_STS 2 + #define BM1_IRQ_STS 3 +-#define BM2_IRQ_STS 4 +-#define BM3_IRQ_STS 5 +-#define BM4_IRQ_STS 6 +-#define BM5_IRQ_STS 7 +-#define BM6_IRQ_STS 8 +-#define BM7_IRQ_STS 9 + /* ACC_BMX_STATUS */ + #define EOP (1<<0) + #define BM_EOP_ERR (1<<1) + /* ACC_BMX_CTL */ +-#define BM_CTL_EN 0x00000001 +-#define BM_CTL_PAUSE 0x00000011 +-#define BM_CTL_DIS 0x00000000 +-#define BM_CTL_BYTE_ORD_LE 0x00000000 +-#define BM_CTL_BYTE_ORD_BE 0x00000100 ++#define BM_CTL_EN 0x01 ++#define BM_CTL_PAUSE 0x03 ++#define BM_CTL_DIS 0x00 ++#define BM_CTL_BYTE_ORD_LE 0x00 ++#define BM_CTL_BYTE_ORD_BE 0x04 + /* cs5535 specific ac97 codec register defines */ + #define CMD_MASK 0xFF00FFFF + #define CMD_NEW 0x00010000 +@@ -106,8 +77,8 @@ struct cs5535audio_dma { + struct snd_pcm_substream *substream; + unsigned int buf_addr, buf_bytes; + unsigned int period_bytes, periods; +- int suspended; + u32 saved_prd; ++ int pcm_open_flag; + }; + + struct cs5535audio { +@@ -123,8 +94,21 @@ struct cs5535audio { + struct cs5535audio_dma dmas[NUM_CS5535AUDIO_DMAS]; + }; + ++#ifdef CONFIG_PM + int snd_cs5535audio_suspend(struct pci_dev *pci, pm_message_t state); + int snd_cs5535audio_resume(struct pci_dev *pci); ++#endif ++ ++#ifdef CONFIG_OLPC ++void olpc_prequirks(struct snd_card *card, struct snd_ac97_template *ac97) __devinit; ++int olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97) __devinit; ++int olpc_ai_enable(struct snd_ac97 *ac97, u8 val); ++#else ++#define olpc_prequirks(arg,arg2) do {} while (0) ++#define olpc_quirks(arg,arg2) (0) ++#define olpc_ai_enable(a, v) (0) ++#endif ++ + int __devinit snd_cs5535audio_pcm(struct cs5535audio *cs5535audio); + + #endif /* __SOUND_CS5535AUDIO_H */ +diff --git a/sound/pci/cs5535audio/cs5535audio_pcm.c b/sound/pci/cs5535audio/cs5535audio_pcm.c +index 5450a9e..d23f8ea 100644 +--- a/sound/pci/cs5535audio/cs5535audio_pcm.c ++++ b/sound/pci/cs5535audio/cs5535audio_pcm.c +@@ -164,6 +164,7 @@ static int cs5535audio_build_dma_packets(struct cs5535audio *cs5535au, + jmpprd_addr = cpu_to_le32(lastdesc->addr + + (sizeof(struct cs5535audio_dma_desc)*periods)); + ++ dma->substream = substream; + dma->period_bytes = period_bytes; + dma->periods = periods; + spin_lock_irq(&cs5535au->reg_lock); +@@ -241,6 +242,7 @@ static void cs5535audio_clear_dma_packets(struct cs5535audio *cs5535au, + { + snd_dma_free_pages(&dma->desc_buf); + dma->desc_buf.area = NULL; ++ dma->substream = NULL; + } + + static int snd_cs5535audio_hw_params(struct snd_pcm_substream *substream, +@@ -260,6 +262,9 @@ static int snd_cs5535audio_hw_params(struct snd_pcm_substream *substream, + err = cs5535audio_build_dma_packets(cs5535au, dma, substream, + params_periods(hw_params), + params_period_bytes(hw_params)); ++ if (!err) ++ dma->pcm_open_flag = 1; ++ + return err; + } + +@@ -268,6 +273,15 @@ static int snd_cs5535audio_hw_free(struct snd_pcm_substream *substream) + struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); + struct cs5535audio_dma *dma = substream->runtime->private_data; + ++ if (dma->pcm_open_flag) { ++ if (substream == cs5535au->playback_substream) ++ snd_ac97_update_power(cs5535au->ac97, ++ AC97_PCM_FRONT_DAC_RATE, 0); ++ else ++ snd_ac97_update_power(cs5535au->ac97, ++ AC97_PCM_LR_ADC_RATE, 0); ++ dma->pcm_open_flag = 0; ++ } + cs5535audio_clear_dma_packets(cs5535au, dma, substream); + return snd_pcm_lib_free_pages(substream); + } +@@ -298,14 +312,12 @@ static int snd_cs5535audio_trigger(struct snd_pcm_substream *substream, int cmd) + break; + case SNDRV_PCM_TRIGGER_RESUME: + dma->ops->enable_dma(cs5535au); +- dma->suspended = 0; + break; + case SNDRV_PCM_TRIGGER_STOP: + dma->ops->disable_dma(cs5535au); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + dma->ops->disable_dma(cs5535au); +- dma->suspended = 1; + break; + default: + snd_printk(KERN_ERR "unhandled trigger\n"); +@@ -344,6 +356,7 @@ static int snd_cs5535audio_capture_open(struct snd_pcm_substream *substream) + int err; + struct cs5535audio *cs5535au = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_ac97 *ac97 = cs5535au->ac97; + + runtime->hw = snd_cs5535audio_capture; + cs5535au->capture_substream = substream; +@@ -352,11 +365,29 @@ static int snd_cs5535audio_capture_open(struct snd_pcm_substream *substream) + if ((err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS)) < 0) + return err; +- return 0; ++ ++#ifdef CONFIG_OLPC ++ /* Disable Analog Input */ ++ olpc_ai_enable(ac97, 0); ++ /* Enable V_ref bias while recording. */ ++ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1<ac97; ++ ++ /* Disable Analog Input */ ++ olpc_ai_enable(ac97, 0); ++ /* Disable V_ref bias. */ ++ snd_ac97_update_bits(ac97, AC97_AD_MISC, 1<pcm); ++ snd_ac97_suspend(cs5535au->ac97); + for (i = 0; i < NUM_CS5535AUDIO_DMAS; i++) { + struct cs5535audio_dma *dma = &cs5535au->dmas[i]; +- if (dma && dma->substream && !dma->suspended) ++ if (dma && dma->substream) + dma->saved_prd = dma->ops->read_prd(cs5535au); + } +- snd_pcm_suspend_all(cs5535au->pcm); +- snd_ac97_suspend(cs5535au->ac97); + /* save important regs, then disable aclink in hw */ + snd_cs5535audio_stop_hardware(cs5535au); + ++ if (pci_save_state(pci)) { ++ printk(KERN_ERR "cs5535audio: pci_save_state failed!\n"); ++ return -EIO; ++ } + pci_disable_device(pci); +- pci_save_state(pci); + pci_set_power_state(pci, pci_choose_state(pci, state)); + return 0; + } +@@ -89,7 +92,12 @@ int snd_cs5535audio_resume(struct pci_dev *pci) + int i; + + pci_set_power_state(pci, PCI_D0); +- pci_restore_state(pci); ++ if (pci_restore_state(pci) < 0) { ++ printk(KERN_ERR "cs5535audio: pci_restore_state failed, " ++ "disabling device\n"); ++ snd_card_disconnect(card); ++ return -EIO; ++ } + if (pci_enable_device(pci) < 0) { + printk(KERN_ERR "cs5535audio: pci_enable_device failed, " + "disabling device\n"); +@@ -112,17 +120,17 @@ int snd_cs5535audio_resume(struct pci_dev *pci) + if (!timeout) + snd_printk(KERN_ERR "Failure getting AC Link ready\n"); + +- /* we depend on ac97 to perform the codec power up */ +- snd_ac97_resume(cs5535au->ac97); + /* set up rate regs, dma. actual initiation is done in trig */ + for (i = 0; i < NUM_CS5535AUDIO_DMAS; i++) { + struct cs5535audio_dma *dma = &cs5535au->dmas[i]; +- if (dma && dma->substream && dma->suspended) { ++ if (dma && dma->substream) { + dma->substream->ops->prepare(dma->substream); + dma->ops->setup_prd(cs5535au, dma->saved_prd); + } + } +- ++ ++ /* we depend on ac97 to perform the codec power up */ ++ snd_ac97_resume(cs5535au->ac97); + snd_power_change_state(card, SNDRV_CTL_POWER_D0); + + return 0; -- 2.30.2