From 5ab134ad09988ca8225e759a052df7a1bbd26145 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Mon, 29 Oct 2012 18:25:45 +0800 Subject: [PATCH] ARM: tegra: dt: add L2 cache controller Add L2 cache controller binding into DT for Tegra. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 9 +++++++++ arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f3a09d0d45bc..f40cfbaa7c7e 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b1497c7d7d68..148371b432a0 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 -- 2.30.2