From 51cc9adef064c8cf3df6d24e8662e9151529decf Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 8 Feb 2018 19:41:02 +0200 Subject: [PATCH] drm/i915: Don't query PCODE RC6VIDS on platforms not supporting it On BXT/GLK GEN6_PCODE_READ_RC6VIDS fails with MAILBOX_P24C_CC_ILLEGAL_CMD, so don't try to do the query on these platforms. Do it only on SNB, IVB and HSW, where we use this command anyway for RC6 enabling. Based on my tests the command also succeeds on all LLC platforms, but it's not clear if it's really supported on those (it returns 0 aka 245mv for all RC6 states everywhere except on SNB). BSpec lists the command as supported on SKL+ (see P24C_PCODE_MAILBOX_INTERFACE) but that's clearly incorrect, since on SKL/KBL the same command ID is used for SKL_PCODE_LOAD_HDCP_KEYS. Since the command fails on BXT/GLK, the BSpec command list is also incorrect for those platforms (see P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR). I filed a request to update that info in Bspec, but for now let's assume a minimal set of platforms where the command is supported. References: https://bugs.freedesktop.org/show_bug.cgi?id=103337 Signed-off-by: Imre Deak Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180208174102.10240-1-imre.deak@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index eff5548ec093..960302668649 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1471,9 +1471,12 @@ static int gen6_drpc_info(struct seq_file *m) gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); } - mutex_lock(&dev_priv->pcu_lock); - sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); - mutex_unlock(&dev_priv->pcu_lock); + if (INTEL_GEN(dev_priv) <= 7) { + mutex_lock(&dev_priv->pcu_lock); + sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, + &rc6vids); + mutex_unlock(&dev_priv->pcu_lock); + } seq_printf(m, "RC1e Enabled: %s\n", yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); @@ -1529,12 +1532,15 @@ static int gen6_drpc_info(struct seq_file *m) print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); - seq_printf(m, "RC6 voltage: %dmV\n", - GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); - seq_printf(m, "RC6+ voltage: %dmV\n", - GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); - seq_printf(m, "RC6++ voltage: %dmV\n", - GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); + if (INTEL_GEN(dev_priv) <= 7) { + seq_printf(m, "RC6 voltage: %dmV\n", + GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); + seq_printf(m, "RC6+ voltage: %dmV\n", + GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); + seq_printf(m, "RC6++ voltage: %dmV\n", + GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); + } + return i915_forcewake_domains(m, NULL); } -- 2.30.2