From 4f43673e5ac54c3c2486eee6f1c9cf5e51744f23 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 21 Jan 2016 19:43:40 -0700 Subject: [PATCH] rockchip: clk: Add a function to get a peripheral clock rate It is useful to be able to read the rate of a peripheral clock. Add a handler for that. Signed-off-by: Simon Glass --- drivers/clk/clk_rk3288.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 49c2bdf2b2..df5c38cf72 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -508,6 +508,42 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } +static ulong rk3288_get_periph_rate(struct udevice *dev, int periph) +{ + struct rk3288_clk_priv *priv = dev_get_priv(dev); + struct udevice *gclk; + ulong new_rate, gclk_rate; + int ret; + + ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk); + if (ret) + return ret; + gclk_rate = clk_get_rate(gclk); + switch (periph) { + case HCLK_EMMC: + case HCLK_SDIO0: + case HCLK_SDIO1: + new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph); + break; + case SCLK_SPI0: + case SCLK_SPI1: + case SCLK_SPI2: + new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + case PCLK_I2C5: + return gclk_rate; + default: + return -ENOENT; + } + + return new_rate; +} + static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate) { struct rk3288_clk_priv *priv = dev_get_priv(dev); @@ -543,6 +579,7 @@ static struct clk_ops rk3288_clk_ops = { .get_rate = rk3288_clk_get_rate, .set_rate = rk3288_clk_set_rate, .set_periph_rate = rk3288_set_periph_rate, + .get_periph_rate = rk3288_get_periph_rate, }; static int rk3288_clk_probe(struct udevice *dev) -- 2.30.2