From 49a7581c6ced35379ec3c450bb60fe736db9d733 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 25 Sep 2005 18:41:04 +0200 Subject: [PATCH] OMAP242x H4 board update - fix for ES2 differences. - switch to using the cfi_flash driver. - fix SRAM build address. - fix for GP device operation. - unlock SRAM for GP devices. - display more device information. - fix potential deadlock in omap24xx_i2c driver. - fix DLL load values to match dpllout*1 operation. - fix 2nd chip select init for combo DDR device. - add support for CFI Intel 28F256L18 on H4 board. Patch by Richard Woodruff, 03 Mar 2005 --- CHANGELOG | 13 ++ board/omap2420h4/Makefile | 2 +- board/omap2420h4/config.mk | 8 +- board/omap2420h4/mem.c | 102 ++++++++---- board/omap2420h4/omap2420h4.c | 36 +++- board/omap2420h4/sys_info.c | 116 +++++++++++-- drivers/omap24xx_i2c.c | 17 +- include/asm-arm/arch-arm1136/clocks.h | 8 +- include/asm-arm/arch-arm1136/i2c.h | 1 + include/asm-arm/arch-arm1136/mem.h | 199 ++++++++++------------- include/asm-arm/arch-arm1136/omap2420.h | 13 ++ include/asm-arm/arch-arm1136/rev.h | 58 ------- include/asm-arm/arch-arm1136/sys_info.h | 8 +- include/asm-arm/arch-arm1136/sys_proto.h | 3 +- include/configs/omap2420h4.h | 35 ++-- 15 files changed, 365 insertions(+), 254 deletions(-) delete mode 100644 include/asm-arm/arch-arm1136/rev.h diff --git a/CHANGELOG b/CHANGELOG index 21944f8361..a82a9a6fce 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,19 @@ Changes for U-Boot 1.1.4: ====================================================================== +* OMAP242x H4 board update + - fix for ES2 differences. + - switch to using the cfi_flash driver. + - fix SRAM build address. + - fix for GP device operation. + - unlock SRAM for GP devices. + - display more device information. + - fix potential deadlock in omap24xx_i2c driver. + - fix DLL load values to match dpllout*1 operation. + - fix 2nd chip select init for combo DDR device. + - add support for CFI Intel 28F256L18 on H4 board. + Patch by Richard Woodruff, 03 Mar 2005 + * Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h Patch by Steven Scholz, 02 Mar 2005 diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile index deab6b6d1c..38dec00d36 100644 --- a/board/omap2420h4/Makefile +++ b/board/omap2420h4/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := omap2420h4.o flash.o mem.o sys_info.o +OBJS := omap2420h4.o mem.o sys_info.o SOBJS := platform.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk index e6aa75678d..3edcde0188 100644 --- a/board/omap2420h4/config.mk +++ b/board/omap2420h4/config.mk @@ -19,4 +19,10 @@ TEXT_BASE = 0x80e80000 # Used with full SRAM boot. # This is either with a GP system or a signed boot image. # easiest, and safest way to go if you can. -#TEXT_BASE = 0x40280000 +#TEXT_BASE = 0x40270000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index 9ae595b3ca..62eb6e38a3 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -48,7 +48,7 @@ void sdelay (unsigned long loops) *********************************************************************************/ void prcm_init(void) { - u32 rev,div; + u32 div; void (*f_lock_pll) (u32, u32, u32, u32); extern void *_end_vect, *_start; @@ -64,11 +64,7 @@ void prcm_init(void) __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - rev = get_cpu_rev(); - if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1) - div = BUS_DIV_ES1; - else - div = BUS_DIV; + div = BUS_DIV; __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */ sdelay(1000); @@ -99,6 +95,23 @@ void prcm_init(void) sdelay(1000); } +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG); + +} /******************************************************** * mem_ok() - test used to see if timings are correct @@ -122,6 +135,7 @@ u32 mem_ok(void) return(1); } + /******************************************************** * sdrc_init() - init the sdrc chip selects CS0 and CS1 * - early init routines, called from flash or @@ -148,28 +162,29 @@ void sdrc_init(void) **************************************************************************/ void do_sdrc_init(u32 offset, u32 early) { - u32 cpu, bug=0, rev, common=0, cs0=0, pmask=0, pass_type; + u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; sdrc_data_t *sdata; /* do not change type */ u32 a, b, r; static const sdrc_data_t sdrc_2422 = { H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0, - H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0_DDR, - 0, H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL + H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR, + 0, H4_2422_SDRC_DLLAB_CTRL }; static const sdrc_data_t sdrc_2420 = { H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR, H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, - H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, - H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL + H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, + H4_2420_SDRC_DLLAB_CTRL }; if (offset == SDRC_CS0_OSET) cs0 = common = 1; /* int regs shared between both chip select */ cpu = get_cpu_type(); + rev = get_cpu_rev(); /* warning generated, though code generation is correct. this may bite later, * but is ok for now. there is only so much C code you can do on stack only @@ -197,9 +212,15 @@ void do_sdrc_init(u32 offset, u32 early) if(running_from_internal_boot()) sdata = (sdrc_data_t *)((u32)sdata + 0x4000); } - if (!early && (get_mem_type() == DDR_COMBO)) {/* combo part has a shared CKE signal, can't use feature */ - pmask = BIT2; - pass_type = COMBO_DDR; /* CS1 config */ + + if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { + if(mtype == DDR_COMBO){ + pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ + pass_type = COMBO_DDR; /* CS1 config */ + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); + } + if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */ + make_cs1_contiguous(); } next_mem_type: @@ -208,11 +229,10 @@ next_mem_type: wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); #ifdef POWER_SAVE __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER)|BIT6) & ~pmask, SDRC_POWER); + __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER); #endif } @@ -224,15 +244,16 @@ next_mem_type: __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); } - if(pass_type == IP_SDR){ /* SDRAM can run full speed only rated for 105MHz*/ - a = H4_242X_SDRC_ACTIM_CTRLA_0_100MHz; - b = H4_242X_SDRC_ACTIM_CTRLB_0_100MHz; - r = H4_2420_SDRC_RFR_CTRL; - } else { - a = sdata->sdrc_actim_ctrla_0; - b = sdata->sdrc_actim_ctrlb_0; - r = sdata->sdrc_rfr_ctrl; - } + a = sdata->sdrc_actim_ctrla_0; + b = sdata->sdrc_actim_ctrlb_0; + r = sdata->sdrc_dllab_ctrl; + + /* work around ES1 DDR issues */ + if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){ + a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1; + b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1; + r = H4_242x_SDRC_RFR_CTRL_ES1; + } if (cs0) { __raw_writel(a, SDRC_ACTIM_CTRLA_0); @@ -241,7 +262,6 @@ next_mem_type: __raw_writel(a, SDRC_ACTIM_CTRLA_1); __raw_writel(b, SDRC_ACTIM_CTRLB_1); } - __raw_writel(r, SDRC_RFR_CTRL+offset); /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ @@ -263,18 +283,22 @@ next_mem_type: __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ - rev = get_cpu_rev(); - if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1){ - bug = BIT0; + if (rev == CPU_2420_2422_ES1){ + dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ } - /* enable & load up DLL with good value for 75MHz, and set phase to 90% */ + else + dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */ + + /* enable & load up DLL with good value for 75MHz, and set phase to 90 + * ES1 recommends 90 phase, ES2 recommends 72 phase. + */ if (common && (pass_type != IP_SDR)) { - __raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL); - __raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL); } sdelay(90000); @@ -291,12 +315,18 @@ next_mem_type: *****************************************************/ void gpmc_init(void) { - u32 mux=0, mtype, mwidth; + u32 mux=0, mtype, mwidth, rev, tval; + + rev = get_cpu_rev(); + if (rev == CPU_2420_2422_ES1) + tval = 1; + else + tval = 0; /* disable bit switched meaning */ /* global settings */ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */ + __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ #ifdef CFG_NAND_BOOT __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ #else diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 219bcf43be..c729eca015 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -36,7 +36,7 @@ extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif -static void wait_for_command_complete(unsigned int wd_base); + void wait_for_command_complete(unsigned int wd_base); /******************************************************* * Routine: delay @@ -82,6 +82,21 @@ void try_unlock_sram(void) } } +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_sram(void) +{ + /* if GP device unlock device SRAM for general use */ + if (get_device_type() == GP_DEVICE) { + __raw_writel(0xFF, A_REQINFOPERM0); + __raw_writel(0xCFDE, A_READPERM0); + __raw_writel(0xCFDE, A_WRITEPERM0); + } +} + /********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. @@ -144,7 +159,7 @@ void watchdog_init(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) +void wait_for_command_complete(unsigned int wd_base) { int pending = 1; do { @@ -200,7 +215,7 @@ int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; unsigned int size0=0,size1=0; - u32 mtype, btype; + u32 mtype, btype, rev, cpu; u8 chg_on = 0x5; /* enable charge of back up battery */ u8 vmode_on = 0x8C; #define NOT_EARLY 0 @@ -209,6 +224,8 @@ int dram_init (void) btype = get_board_type(); mtype = get_mem_type(); + rev = get_cpu_rev(); + cpu = get_cpu_type(); display_board_info(btype); if (btype == BOARD_H4_MENELAUS){ @@ -219,15 +236,16 @@ int dram_init (void) if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ - size0 = size1 = SZ_32M; - } else if (mtype == SDR_DISCRETE) - size0 = SZ_128M; - else - size0 = SZ_64M; + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + else /* ES2 and above can remap at 32MB granularity */ + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; gd->bd->bi_dram[1].size = size1; return 0; diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c index 121d67916d..9864d3e489 100644 --- a/board/omap2420h4/sys_info.c +++ b/board/omap2420h4/sys_info.c @@ -28,6 +28,16 @@ #include #include +/************************************************************************** + * get_prod_id() - get id info from chips + ***************************************************************************/ +static u32 get_prod_id(void) +{ + u32 p; + p = __raw_readl(PRODUCTION_ID); /* get production ID */ + return((p & CPU_242X_PID_MASK) >> 16); +} + /************************************************************************** * get_cpu_type() - low level get cpu type * - no C globals yet. @@ -40,6 +50,14 @@ u32 get_cpu_type(void) { u32 v; + switch(get_prod_id()){ + case 1:;/* 2420 */ + case 2: return(CPU_2420); break; /* 2420 pop */ + case 4: return(CPU_2422); break; + case 8: return(CPU_2423); break; + default: break; /* early 2420/2422's unmarked */ + } + v = __raw_readl(TAP_IDCODE_REG); v &= CPU_24XX_ID_MASK; if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */ @@ -61,6 +79,16 @@ u32 get_cpu_rev(void) v = v >> 28; return(v+1); /* currently 2422 and 2420 match up */ } +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); + if(*burst == H4_2420_SDRC_MR_0_SDR) + return(1); + return(0); +} /*********************************************************** * get_mem_type() - identify type of mDDR part used. @@ -70,23 +98,39 @@ u32 get_cpu_rev(void) *************************************************************/ u32 get_mem_type(void) { - volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); + u32 cpu, sdr = is_mem_sdr(); - if (get_cpu_type() == CPU_2422) + cpu = get_cpu_type(); + if (cpu == CPU_2422 || cpu == CPU_2423) return(DDR_STACKED); + if(get_prod_id() == 0x2) + return(XDR_POP); + if (get_board_type() == BOARD_H4_MENELAUS) - if(*burst == H4_2420_SDRC_MR_0_SDR) + if(sdr) return(SDR_DISCRETE); else return(DDR_COMBO); else - if(*burst == H4_2420_SDRC_MR_0_SDR) /* SDP + SDR kit */ + if(sdr) /* SDP + SDR kit */ return(SDR_DISCRETE); else return(DDR_DISCRETE); /* origional SDP */ } +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */ + size &= 0x2FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return(size); +} + /*********************************************************************** * get_board_type() - get board type based on current production stats. * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. @@ -104,7 +148,7 @@ u32 get_board_type(void) /****************************************************************** * get_sysboot_value() - get init word settings (dip switch on h4) ******************************************************************/ -u32 get_sysboot_value(void) +inline u32 get_sysboot_value(void) { return(0x00000FFF & __raw_readl(CONTROL_STATUS)); } @@ -193,22 +237,53 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) *********************************************************************/ void display_board_info(u32 btype) { - char cpu_2420[] = "2420"; + char cpu_2420[] = "2420"; /* cpu type */ char cpu_2422[] = "2422"; - char db_men[] = "Menelaus"; - char db_ip[]= "IP"; - char *cpu_s, *db_s; - u32 cpu = get_cpu_type(); + char cpu_2423[] = "2423"; + char db_men[] = "Menelaus"; /* board type */ + char db_ip[] = "IP"; + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; - if(cpu == CPU_2420) - cpu_s = cpu_2420; + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if(is_mem_sdr()) + mem_s = mem_sdr; else + mem_s = mem_ddr; + + if(cpu == CPU_2423) + cpu_s = cpu_2423; + else if (cpu == CPU_2422) cpu_s = cpu_2422; + else + cpu_s = cpu_2420; + if(btype == BOARD_H4_MENELAUS) db_s = db_men; else db_s = db_ip; - printf("TI H4 SDP Base Board with OMAP%s %s Daughter Board\n",cpu_s, db_s); + + switch(sec){ + case TST_DEVICE: sec_s = t_tst; break; + case EMU_DEVICE: sec_s = t_emu; break; + case HS_DEVICE: sec_s = t_hs; break; + case GP_DEVICE: sec_s = t_gp; break; + default: sec_s = unk; + } + + printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1); + printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s); } /************************************************************************* @@ -230,7 +305,7 @@ u32 get_board_rev(void) /******************************************************** * get_base(); get upper addr of current execution *******************************************************/ -static u32 get_base(void) +u32 get_base(void) { u32 val; __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); @@ -242,7 +317,7 @@ static u32 get_base(void) /******************************************************** * get_base2(); get 2upper addr of current execution *******************************************************/ -static u32 get_base2(void) +u32 get_base2(void) { u32 val; __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); @@ -300,3 +375,14 @@ u32 running_from_internal_boot(void) else return(0); } + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); + return(mode >>= 8); +} + diff --git a/drivers/omap24xx_i2c.c b/drivers/omap24xx_i2c.c index 383dfcbb64..7dab78685d 100644 --- a/drivers/omap24xx_i2c.c +++ b/drivers/omap24xx_i2c.c @@ -32,12 +32,16 @@ static void wait_for_bb (void); static u16 wait_for_pin (void); -void flush_fifo(void); +static void flush_fifo(void); void i2c_init (int speed, int slaveadd) { u16 scl; + outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ + udelay(1000); + outw(0x0, I2C_SYSC); /* will probably self clear but */ + if (inw (I2C_CON) & I2C_CON_EN) { outw (0, I2C_CON); udelay (50000); @@ -52,11 +56,14 @@ void i2c_init (int speed, int slaveadd) /* own address */ outw (slaveadd, I2C_OA); outw (I2C_CON_EN, I2C_CON); - outw (0, I2C_CNT); + /* have to enable intrrupts or OMAP i2c module doesn't work */ outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); udelay (1000); + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -160,11 +167,15 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) } if (!i2c_error) { + int eout = 200; + outw (I2C_CON_EN, I2C_CON); while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ outw (0xFFFF, I2C_STAT); + if(--eout == 0) /* better leave with error than hang */ + break; } } flush_fifo(); @@ -173,7 +184,7 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) return i2c_error; } -void flush_fifo(void) +static void flush_fifo(void) { u16 stat; /* note: if you try and read data when its not there or ready diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h index bd1b088326..2a95af1810 100644 --- a/include/asm-arm/arch-arm1136/clocks.h +++ b/include/asm-arm/arch-arm1136/clocks.h @@ -57,8 +57,7 @@ #define II_MPU_DIV 0x2 /* mpu = core/2 */ #define II_DSP_DIV 0x343 /* dsp & iva divider */ #define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04600C26 -#define II_BUS_DIV_ES1 0x04601026 +#define II_BUS_DIV 0x04601026 #define II_DPLL_300 0x01832100 /****************************************************************************; @@ -87,8 +86,7 @@ #define III_MPU_DIV 0x2 /* mpu = core/2 */ #define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ #define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08300c44 -#define III_BUS_DIV_ES1 0x08301044 +#define III_BUS_DIV 0x08301044 #define III_DPLL_266 0x01885500 /* set defaults for boot up */ @@ -98,7 +96,6 @@ # define DSP_DIV II_DSP_DIV # define GFX_DIV II_GFX_DIV # define BUS_DIV II_BUS_DIV -# define BUS_DIV_ES1 II_BUS_DIV_ES1 # define DPLL_VAL II_DPLL_300 #elif PRCM_CONFIG_III # define DPLL_OUT III_DPLL_OUT_X2 @@ -106,7 +103,6 @@ # define DSP_DIV III_DSP_DIV # define GFX_DIV III_GFX_DIV # define BUS_DIV III_BUS_DIV -# define BUS_DIV_ES1 III_BUS_DIV_ES1 # define DPLL_VAL III_DPLL_266 #endif diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h index 3e37f4dab0..7248950e52 100644 --- a/include/asm-arm/arch-arm1136/i2c.h +++ b/include/asm-arm/arch-arm1136/i2c.h @@ -33,6 +33,7 @@ #define I2C_BUF (I2C_BASE + 0x14) #define I2C_CNT (I2C_BASE + 0x18) #define I2C_DATA (I2C_BASE + 0x1c) +#define I2C_SYSC (I2C_BASE + 0x20) #define I2C_CON (I2C_BASE + 0x24) #define I2C_OA (I2C_BASE + 0x28) #define I2C_SA (I2C_BASE + 0x2c) diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h index dfaf568769..c81f1c4370 100644 --- a/include/asm-arm/arch-arm1136/mem.h +++ b/include/asm-arm/arch-arm1136/mem.h @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -25,8 +25,8 @@ #ifndef _OMAP24XX_MEM_H_ #define _OMAP24XX_MEM_H_ -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ #ifndef __ASSEMBLY__ /* struct's for holding data tables for current boards, they are getting used @@ -40,8 +40,7 @@ struct sdrc_data_s { u32 sdrc_rfr_ctrl; u32 sdrc_mr_0_ddr; u32 sdrc_mr_0_sdr; - u32 sdrc_dlla_ctrl; - u32 sdrc_dllb_ctrl; + u32 sdrc_dllab_ctrl; } /*__attribute__ ((packed))*/; typedef struct sdrc_data_s sdrc_data_t; @@ -49,129 +48,109 @@ typedef enum { STACKED = 0, IP_DDR = 1, COMBO_DDR = 2, - IP_SDR = 3, + IP_SDR = 3, } mem_t; #endif /* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_SHARING 0x00000100 #define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ #define H4_2420_SDRC_MR_0_SDR 0x00000031 #define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ #define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ #define H4_2420_SDRC_MR_0_DDR 0x00000032 -#ifndef CONFIG_OPTIMIZE_DDR -# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909 -# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014 -# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401 -# define H4_2420_SDRC_RFR_CTRL 0x0002da01 -#endif -#define H4_2420_SDRC_DLLA_CTRL 0x0000E307 /* DLL value used for 50MHz */ -#define H4_2420_SDRC_DLLB_CTRL 0x0000E307 /* allow DPLLout*1 to work */ - #define H4_2422_SDRC_SHARING 0x00004b00 #define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ -#ifndef CONFIG_OPTIMIZE_DDR -# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909 -# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020 -# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401 -# define H4_2422_SDRC_RFR_CTRL 0x0002da01 -#endif #define H4_2422_SDRC_MR_0_DDR 0x00000032 -#define H4_2422_SDRC_DLLA_CTRL 0x00007307 -#define H4_2422_SDRC_DLLB_CTRL 0x00007307 -/* optimized timings */ +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ #define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 #define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */ -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 - -#ifdef CONFIG_OPTIMIZE_DDR -# ifdef PRCM_CONFIG_II -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# elif PRCM_CONFIG_III -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# endif -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0 -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0 -# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1 -# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 +#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ +#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ + +#ifdef PRCM_CONFIG_II +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#elif PRCM_CONFIG_III +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz #endif /* GPMC settings */ -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -#ifdef CFG_NAND_BOOT -#define H4_24XX_GPMC_CONFIG1_0 0x0 -#define H4_24XX_GPMC_CONFIG2_0 0x00141400 -#define H4_24XX_GPMC_CONFIG3_0 0x00141400 -#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -#define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -#define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -#else -#define H4_24XX_GPMC_CONFIG1_0 0x3 -#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 -#define H4_24XX_GPMC_CONFIG3_0 0x00050502 -#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 -#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -#endif -#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) - -#define H4_24XX_GPMC_CONFIG1_1 0x00011000 -#define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 -#define H4_24XX_GPMC_CONFIG3_1 0x00080802 -#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -#define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F -#define H4_24XX_GPMC_CONFIG6_1 0x000003C2 -#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -#ifdef CFG_NAND_BOOT -#define H4_24XX_GPMC_CONFIG1_0 0x0 -#define H4_24XX_GPMC_CONFIG2_0 0x00141400 -#define H4_24XX_GPMC_CONFIG3_0 0x00141400 -#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -#define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -#define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -#else -#define H4_24XX_GPMC_CONFIG1_0 0x3 -#define H4_24XX_GPMC_CONFIG2_0 0x00151501 -#define H4_24XX_GPMC_CONFIG3_0 0x00060602 -#define H4_24XX_GPMC_CONFIG4_0 0x10081008 -#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -#define H4_24XX_GPMC_CONFIG6_0 0x000004c4 -#endif -#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) - -#define H4_24XX_GPMC_CONFIG1_1 0x00011000 -#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 -#define H4_24XX_GPMC_CONFIG3_1 0x00080803 -#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F -#define H4_24XX_GPMC_CONFIG6_1 0x000004C4 -#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif - -#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */ -#define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */ -#define VAL_H4_SDRC_SHARING 0x00000100 -#define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */ -#define VAL_H4_SDRC_MCFG_0 0x01702011 -#define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/ -#define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */ -#define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485 -#endif - -#endif +#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* else NOR */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 +# define H4_24XX_GPMC_CONFIG3_0 0x00050502 +# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 +# define H4_24XX_GPMC_CONFIG3_1 0x00080802 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif PRCM_CONFIG_II */ + +#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* NOR boot */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x00151501 +# define H4_24XX_GPMC_CONFIG3_0 0x00060602 +# define H4_24XX_GPMC_CONFIG4_0 0x10081008 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 +# define H4_24XX_GPMC_CONFIG3_1 0x00080803 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif CFG_PRCM_III */ + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index eba385cea3..7a7aae6b0e 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -37,13 +37,25 @@ #define A_WRITEPERM0 0x68005058 #define GP_DEVICE (BIT8|BIT9) +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + /* CONTROL */ #define OMAP2420_CTRL_BASE (0x48000000) #define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + /* TAP information */ #define OMAP2420_TAP_BASE (0x48014000) #define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) /* GPMC */ #define OMAP2420_GPMC_BASE (0x6800A000) @@ -76,6 +88,7 @@ #define OMAP2420_SDRC_BASE 0x68009000 #define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) #define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) #define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) #define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) #define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) diff --git a/include/asm-arm/arch-arm1136/rev.h b/include/asm-arm/arch-arm1136/rev.h deleted file mode 100644 index 6fceb092d5..0000000000 --- a/include/asm-arm/arch-arm1136/rev.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_REV_H_ -#define _OMAP24XX_REV_H_ - -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 - -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 - -#endif diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h index ef301ba61a..53c231a5e4 100644 --- a/include/asm-arm/arch-arm1136/sys_info.h +++ b/include/asm-arm/arch-arm1136/sys_info.h @@ -39,7 +39,8 @@ typedef struct h4_system_data { u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ } h4_sys_data; -#define SDR_DISCRETE 4 +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ #define DDR_STACKED 3 /* stacked part on 2422 */ #define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ @@ -50,16 +51,19 @@ typedef struct h4_system_data { #define DDR_165 165 /* future parts */ #define CPU_2420 0x2420 -#define CPU_2422 0x2422 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ #define CPU_2422_ES1 1 #define CPU_2422_ES2 2 #define CPU_2420_ES1 1 #define CPU_2420_ES2 2 +#define CPU_2420_2422_ES1 1 #define CPU_2420_CHIPID 0x0B5D9000 #define CPU_24XX_ID_MASK 0x0FFFF000 #define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 #define BOARD_H4_MENELAUS 1 #define BOARD_H4_SDP 2 diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h index 2cd8455dec..9d8e5b2622 100644 --- a/include/asm-arm/arch-arm1136/sys_proto.h +++ b/include/asm-arm/arch-arm1136/sys_proto.h @@ -44,10 +44,11 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); u32 get_board_type(void); void display_board_info(u32); void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); u32 running_in_sdram(void); u32 running_in_sram(void); u32 running_in_flash(void); u32 running_from_internal_boot(void); - +u32 get_device_type(void); #endif diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index c7916036ff..5674e20fc8 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -39,11 +39,8 @@ /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ /* Clock config to target*/ -#define PRCM_CONFIG_II 1 -/*#define PRCM_CONFIG_III 1 */ - -/* Memory configuration on board */ -/*#define CONFIG_OPTIMIZE_DDR 1 */ +#define PRCM_CONFIG_II 1 +//#define PRCM_CONFIG_III 1 #include /* get chip and board defs */ @@ -125,11 +122,8 @@ #ifdef CFG_NAND_BOOT #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) #else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) #endif -/* I'd like to get to these. Snap kernel loads if we make MMC go */ - /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */ - #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -241,17 +235,21 @@ #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_FLASH_SECT_SIZE SZ_128K #define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ #define PHYS_FLASH_SIZE_1 SZ_32M #define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ #define PHYS_FLASH_SIZE_2 SZ_32M -#define CFG_FLASH_BASE PHYS_FLASH_1 /*----------------------------------------------------------------------- * FLASH and environment organization */ +#define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } #ifdef CFG_NAND_BOOT #define CFG_ENV_IS_IN_NAND 1 @@ -259,11 +257,24 @@ #else #define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) #define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ #endif + + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ #define CFG_JFFS2_MEM_NAND -- 2.30.2