From 4745acaa1a603b67f6b9b7970365ebadd7d6586f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 20 Feb 2007 10:57:08 +0100 Subject: [PATCH] [PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 18 +- Makefile | 3 + board/amcc/katmai/Makefile | 51 ++++ board/amcc/katmai/cmd_katmai.c | 267 +++++++++++++++++ board/amcc/katmai/config.mk | 38 +++ board/amcc/katmai/init.S | 108 +++++++ board/amcc/katmai/katmai.c | 514 +++++++++++++++++++++++++++++++++ board/amcc/katmai/katmai.h | 65 +++++ board/amcc/katmai/u-boot.lds | 157 ++++++++++ cpu/ppc4xx/cpu_init.c | 2 +- cpu/ppc4xx/speed.c | 13 +- cpu/ppc4xx/start.S | 57 ++++ include/configs/katmai.h | 415 ++++++++++++++++++++++++++ include/ppc405.h | 1 + include/ppc440.h | 9 +- 16 files changed, 1700 insertions(+), 19 deletions(-) create mode 100644 board/amcc/katmai/Makefile create mode 100644 board/amcc/katmai/cmd_katmai.c create mode 100644 board/amcc/katmai/config.mk create mode 100644 board/amcc/katmai/init.S create mode 100644 board/amcc/katmai/katmai.c create mode 100644 board/amcc/katmai/katmai.h create mode 100644 board/amcc/katmai/u-boot.lds create mode 100644 include/configs/katmai.h diff --git a/MAINTAINERS b/MAINTAINERS index f90c5a65ff..1d0a8dfdb3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -288,6 +288,7 @@ Stefan Roese bamboo PPC440EP bunbinga PPC405EP ebony PPC440GP + katmai PPC440SPe ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP diff --git a/MAKEALL b/MAKEALL index d943cee45f..c9f5958269 100755 --- a/MAKEALL +++ b/MAKEALL @@ -81,15 +81,15 @@ LIST_4xx=" \ CRAYL1 csb272 csb472 DASA_SIM \ DP405 DU405 ebony ERIC \ EXBITGEN G2000 HH405 HUB405 \ - JSE KAREF luan METROBOX \ - MIP405 MIP405T ML2 ml300 \ - ocotea OCRTC ORSG p3p440 \ - PCI405 pcs440ep PIP405 PLU405 \ - PMC405 PPChameleonEVB sbc405 sc3 \ - sequoia sequoia_nand taishan VOH405 \ - VOM405 W7OLMC W7OLMG walnut \ - WUH405 XPEDITE1K yellowstone yosemite \ - yucca \ + JSE KAREF katmai luan \ + METROBOX MIP405 MIP405T ML2 \ + ml300 ocotea OCRTC ORSG \ + p3p440 PCI405 pcs440ep PIP405 \ + PLU405 PMC405 PPChameleonEVB sbc405 \ + sc3 sequoia sequoia_nand taishan \ + VOH405 VOM405 W7OLMC W7OLMG \ + walnut WUH405 XPEDITE1K yellowstone \ + yosemite yucca \ " ######################################################################### diff --git a/Makefile b/Makefile index f39ff652f5..546a808157 100644 --- a/Makefile +++ b/Makefile @@ -1092,6 +1092,9 @@ JSE_config: unconfig KAREF_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx karef sandburst +katmai_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc + luan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile new file mode 100644 index 0000000000..d06a402d17 --- /dev/null +++ b/board/amcc/katmai/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o cmd_katmai.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c new file mode 100644 index 0000000000..684f6a5863 --- /dev/null +++ b/board/amcc/katmai/cmd_katmai.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include + +static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar chip; + ulong data; + int nbytes; + extern char console_buffer[]; + + char sysClock[4]; + char cpuClock[4]; + char plbClock[4]; + char pcixClock[4]; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "prom0") == 0) + chip = IIC0_BOOTPROM_ADDR; + else + chip = IIC0_ALT_BOOTPROM_ADDR; + + do { + printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if ((strcmp(console_buffer, "33") != 0) & + (strcmp(console_buffer, "66") != 0)) + nbytes=0; + + strcpy(sysClock, console_buffer); + + } while (nbytes == 0); + + do { + if (strcmp(sysClock, "66") == 0) { + printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); + } else { +#ifdef CONFIG_STRESS + printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); +#else + printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); +#endif + } + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if (strcmp(sysClock, "66") == 0) { + if ((strcmp(console_buffer, "400") != 0) & + (strcmp(console_buffer, "533") != 0) +#ifdef CONFIG_STRESS + & (strcmp(console_buffer, "667") != 0) +#endif + ) { + nbytes = 0; + } + } else { + if ((strcmp(console_buffer, "400") != 0) & + (strcmp(console_buffer, "500") != 0) & + (strcmp(console_buffer, "533") != 0) +#ifdef CONFIG_STRESS + & (strcmp(console_buffer, "667") != 0) +#endif + ) { + nbytes = 0; + } + } + + strcpy(cpuClock, console_buffer); + + } while (nbytes == 0); + + if (strcmp(cpuClock, "500") == 0) + strcpy(plbClock, "166"); + else if (strcmp(cpuClock, "533") == 0) + strcpy(plbClock, "133"); + else { + do { + if (strcmp(cpuClock, "400") == 0) + printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + +#ifdef CONFIG_STRESS + if (strcmp(cpuClock, "667") == 0) + printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + +#endif + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if (strcmp(cpuClock, "400") == 0) { + if ((strcmp(console_buffer, "100") != 0) & + (strcmp(console_buffer, "133") != 0)) + nbytes = 0; + } +#ifdef CONFIG_STRESS + if (strcmp(cpuClock, "667") == 0) { + if ((strcmp(console_buffer, "133") != 0) & + (strcmp(console_buffer, "166") != 0)) + nbytes = 0; + } +#endif + strcpy(plbClock, console_buffer); + + } while (nbytes == 0); + } + + do { + printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if ((strcmp(console_buffer, "33") != 0) & + (strcmp(console_buffer, "66") != 0) & + (strcmp(console_buffer, "100") != 0) & + (strcmp(console_buffer, "133") != 0)) { + nbytes = 0; + } + strcpy(pcixClock, console_buffer); + + } while (nbytes == 0); + + printf("\nsys clk = %sMhz\n", sysClock); + printf("cpu clk = %sMhz\n", cpuClock); + printf("plb clk = %sMhz\n", plbClock); + printf("Pci-X clk = %sMhz\n", pcixClock); + + do { + printf("\npress [y] to write I2C bootstrap \n"); + printf("or [n] to abort. \n"); + printf("Don't forget to set board switches \n"); + printf("according to your choice before re-starting \n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + + nbytes = readline (" ? "); + if (strcmp(console_buffer, "n") == 0) + return 0; + + } while (nbytes == 0); + + if (strcmp(sysClock, "33") == 0) { + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "100") == 0)) + data = 0x8678c206; + + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x8678c2c6; + + if ((strcmp(cpuClock, "500") == 0)) + data = 0x8778f2c6; + + if ((strcmp(cpuClock, "533") == 0)) + data = 0x87790252; + +#ifdef CONFIG_STRESS + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x87794256; + + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "166") == 0)) + data = 0x87794206; + +#endif + } + if (strcmp(sysClock, "66") == 0) { + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "100") == 0)) + data = 0x84706206; + + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x847062c6; + + if ((strcmp(cpuClock, "533") == 0)) + data = 0x85708206; + +#ifdef CONFIG_STRESS + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x8570a256; + + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "166") == 0)) + data = 0x8570a206; + +#endif + } + +#ifdef DEBUG + printf(" pin strap0 to write in i2c = %x\n", data); +#endif /* DEBUG */ + + if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) + printf("Error writing strap0 in %s\n", argv[2]); + + if (strcmp(pcixClock, "33") == 0) + data = 0x00000701; + + if (strcmp(pcixClock, "66") == 0) + data = 0x00000601; + + if (strcmp(pcixClock, "100") == 0) + data = 0x00000501; + + if (strcmp(pcixClock, "133") == 0) + data = 0x00000401; + + if (strcmp(plbClock, "166") == 0) + data |= 0x05950000; + else + data |= 0x05A50000; + +#ifdef DEBUG + printf(" pin strap1 to write in i2c = %x\n", data); +#endif /* DEBUG */ + + udelay(1000); + if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) + printf("Error writing strap1 in %s\n", argv[2]); + + return 0; +} + +U_BOOT_CMD( + bootstrap, 3, 1, do_bootstrap, + "bootstrap - program the serial device strap\n", + "wrclk [prom0|prom1] - program the serial device strap\n" + ); diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk new file mode 100644 index 0000000000..115c1aed05 --- /dev/null +++ b/board/amcc/katmai/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 440SPe Evaluation (Katmai) board +# + +TEXT_BASE = 0xfffc0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S new file mode 100644 index 0000000000..f5900bcb7b --- /dev/null +++ b/board/amcc/katmai/init.S @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + +/************************************************************************** + * TLB table for revA + *************************************************************************/ + .globl tlbtabA +tlbtabA: + tlbtab_start + tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbtab_end + +/************************************************************************** + * TLB table for revB + * + * Notice: revB of the 440SPe chip is very strict about PLB real addresses + * and ranges to be mapped for config space: it seems to only work with + * d_nnnn_nnnn range (hangs the core upon config transaction attempts when + * set otherwise) while revA uses c_nnnn_nnnn. + *************************************************************************/ + .globl tlbtabB +tlbtabB: + tlbtab_start + tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbtab_end diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c new file mode 100644 index 0000000000..8704925a9c --- /dev/null +++ b/board/amcc/katmai/katmai.c @@ -0,0 +1,514 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#include "katmai.h" +#include "../cpu/ppc4xx/440spe_pcie.h" + +#undef PCIE_ENDPOINT +/* #define PCIE_ENDPOINT 1 */ + +int ppc440spe_init_pcie_rootport(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); + +int board_early_init_f (void) +{ + unsigned long mfr; + unsigned long pfc; + + /*----------------------------------------------------------------------+ + * Interrupt controller setup for the Katmai 440SPe Evaluation board. + *-----------------------------------------------------------------------+ + *-----------------------------------------------------------------------+ + * Interrupt | Source | Pol. | Sensi.| Crit. | + *-----------+-----------------------------------+-------+-------+-------+ + * IRQ 00 | UART0 | High | Level | Non | + * IRQ 01 | UART1 | High | Level | Non | + * IRQ 02 | IIC0 | High | Level | Non | + * IRQ 03 | IIC1 | High | Level | Non | + * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | + * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | + * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | + * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | + * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | + * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | + * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | + * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | + * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | + * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | + * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | + * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | + * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | + * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | + * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | + * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | + * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | + * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | + * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | + * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | + * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | + * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | + * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | + * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | + * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | + * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | + * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | + * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | + *------------------------------------------------------------------------ + * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | + * IRQ 33 | MAL Serr | High | Level | Non | + * IRQ 34 | MAL Txde | High | Level | Non | + * IRQ 35 | MAL Rxde | High | Level | Non | + * IRQ 36 | DMC CE or DMC UE | High | Level | Non | + * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | + * IRQ 38 | MAL TX EOB | High | Level | Non | + * IRQ 39 | MAL RX EOB | High | Level | Non | + * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | + * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | + * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | + * IRQ 43 | L2 Cache | Risin | Edge | Non | + * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | + * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | + * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | + * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | + * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | + * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | + * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | + * IRQ 54 | DMA Error | High | Level | Non | + * IRQ 55 | DMA I2O Error | High | Level | Non | + * IRQ 56 | Serial ROM | High | Level | Non | + * IRQ 57 | PCIX0 Error | High | Edge | Non | + * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | + * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | + * IRQ 60 | EMAC0 Interrupt | High | Level | Non | + * IRQ 61 | EMAC0 Wake-up | High | Level | Non | + * IRQ 62 | Reserved | High | Level | Non | + * IRQ 63 | XOR | High | Level | Non | + *----------------------------------------------------------------------- + * IRQ 64 | PE0 AL | High | Level | Non | + * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + * IRQ 68 | PE0 TCR | High | Level | Non | + * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + * IRQ 70 | PE0 DCR Error | High | Level | Non | + * IRQ 71 | Reserved | N/A | N/A | Non | + * IRQ 72 | PE1 AL | High | Level | Non | + * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + * IRQ 76 | PE1 TCR | High | Level | Non | + * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + * IRQ 78 | PE1 DCR Error | High | Level | Non | + * IRQ 79 | Reserved | N/A | N/A | Non | + * IRQ 80 | PE2 AL | High | Level | Non | + * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + * IRQ 84 | PE2 TCR | High | Level | Non | + * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + * IRQ 86 | PE2 DCR Error | High | Level | Non | + * IRQ 87 | Reserved | N/A | N/A | Non | + * IRQ 88 | External IRQ(5) | Progr | Progr | Non | + * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + * IRQ 94 | Reserved | N/A | N/A | Non | + * IRQ 95 | Reserved | N/A | N/A | Non | + *----------------------------------------------------------------------- + * IRQ 96 | PE0 INTA | High | Level | Non | + * IRQ 97 | PE0 INTB | High | Level | Non | + * IRQ 98 | PE0 INTC | High | Level | Non | + * IRQ 99 | PE0 INTD | High | Level | Non | + * IRQ 100 | PE1 INTA | High | Level | Non | + * IRQ 101 | PE1 INTB | High | Level | Non | + * IRQ 102 | PE1 INTC | High | Level | Non | + * IRQ 103 | PE1 INTD | High | Level | Non | + * IRQ 104 | PE2 INTA | High | Level | Non | + * IRQ 105 | PE2 INTB | High | Level | Non | + * IRQ 106 | PE2 INTC | High | Level | Non | + * IRQ 107 | PE2 INTD | Risin | Edge | Non | + * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | + * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | + * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | + * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | + * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | + * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | + * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | + * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | + * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | + * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | + * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | + * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | + * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | + * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | + * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | + * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | + * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | + * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | + * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | + * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | + *-----------+-----------------------------------+-------+-------+-------+ */ + /*-------------------------------------------------------------------------+ + * Put UICs in PowerPC440SPemode. + * Initialise UIC registers. Clear all interrupts. Disable all interrupts. + * Set critical interrupt values. Set interrupt polarities. Set interrupt + * trigger levels. Make bit 0 High priority. Clear all interrupts again. + *------------------------------------------------------------------------*/ + mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic3er, 0x00000000); /* disable all interrupts */ + mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */ + mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/ + mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/ + + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts*/ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/ + mtdcr (uic1er, 0x00000000); /* disable all interrupts*/ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */ + mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/ + mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ + +/* SDR0_MFR should be part of Ethernet init */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; +/* mtsdr(sdr_mfr, mfr); */ + + /* + * Setup GPIO signalling per defines in katmai.h + */ + pfc = PFC0_KATMAI; + mtsdr(SDR0_PFC0, pfc); + + out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI); + out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI); + out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI); + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + + printf("Board: Katmai - AMCC 440SPe Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*-------------------------------------------------------------------+ + * The katmai board is always configured as the host & requires the + * PCI arbiter to be enabled. + *-------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*-------------------------------------------------------------------+ + * Disable everything + *-------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*-------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 + * strapping options to not support sizes such as 128/256 MB. + *-------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIX0_BAR0, 0 ); + + /*-------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *-------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +#if defined(CONFIG_PCI) +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +int is_pci_host(struct pci_controller *hose) +{ + /* The katmai board is always configured as host. */ + return 1; +} + +static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; + +void pcie_setup_hoses(void) +{ + struct pci_controller *hose; + int i, bus; + + /* + * assume we're called after the PCIX hose is initialized, which takes + * bus ID 0 and therefore start numbering PCIe's from 1. + */ + bus = 1; + for (i = 0; i <= 2; i++) { +#ifdef PCIE_ENDPOINT + if (ppc440spe_init_pcie_endport(i)) { +#else + if (ppc440spe_init_pcie_rootport(i)) { +#endif + printf("PCIE%d: initialization failed\n", i); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + bus++; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM + ); + hose->region_count = 1; + pci_register_hose(hose); + +#ifdef PCIE_ENDPOINT + ppc440spe_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ +#else + ppc440spe_setup_pcie_rootpoint(hose, i); + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); +#endif + } +} +#endif /* defined(CONFIG_PCI) */ + +int misc_init_f (void) +{ + uint reg; +#if defined(CONFIG_STRESS) + uint i ; + uint disp; +#endif + + /* minimal init for PCIe */ +#if 0 /* test-only: test endpoint at some time, for now rootpoint only */ + /* pci express 0 Endpoint Mode */ + mfsdr(SDR0_PE0DLPSET, reg); + reg &= (~0x00400000); + mtsdr(SDR0_PE0DLPSET, reg); +#else + /* pci express 0 Rootpoint Mode */ + mfsdr(SDR0_PE0DLPSET, reg); + reg |= 0x00400000; + mtsdr(SDR0_PE0DLPSET, reg); +#endif + /* pci express 1 Rootpoint Mode */ + mfsdr(SDR0_PE1DLPSET, reg); + reg |= 0x00400000; + mtsdr(SDR0_PE1DLPSET, reg); + /* pci express 2 Rootpoint Mode */ + mfsdr(SDR0_PE2DLPSET, reg); + reg |= 0x00400000; + mtsdr(SDR0_PE2DLPSET, reg); + +#if defined(CONFIG_STRESS) + /* + * All this setting done by linux only needed by stress an charac. test + * procedure + * PCIe 1 Rootpoint PCIe2 Endpoint + * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level + */ + for (i=0,disp=0; i<8; i++,disp+=3) { + mfsdr(SDR0_PE0HSSSET1L0+disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE0HSSSET1L0+disp, reg); + } + + /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ + for (i=0,disp=0; i<4; i++,disp+=3) { + mfsdr(SDR0_PE1HSSSET1L0+disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE1HSSSET1L0+disp, reg); + } + + /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ + for (i=0,disp=0; i<4; i++,disp+=3) { + mfsdr(SDR0_PE2HSSSET1L0+disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE2HSSSET1L0+disp, reg); + } + + reg = 0x21242222; + mtsdr(SDR0_PE2UTLSET1, reg); + reg = 0x11000000; + mtsdr(SDR0_PE2UTLSET2, reg); + /* pci express 1 Endpoint Mode */ + reg = 0x00004000; + mtsdr(SDR0_PE2DLPSET, reg); + + mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ +#endif + + return 0; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return (ctrlc()); +} +#endif diff --git a/board/amcc/katmai/katmai.h b/board/amcc/katmai/katmai.h new file mode 100644 index 0000000000..9d5b793f13 --- /dev/null +++ b/board/amcc/katmai/katmai.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KATMAI_H_ +#define __KATMAI_H_ + +/*---------------------------------------------------------------------------- + * XX + * XXXX XX XXX XXX XXXX + * XX XX XX XX XX XX + * XX XXX XX XX XX XX XX + * XX XX XXXXX XX XX XX + * XXXX XX XXXX XXXX + * XXXX + * + * The 440SPe provices 32 bits of GPIO. By default all GPIO pins + * are disabled, and must be explicitly enabled by setting a + * bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the + * corresponding bit in the SDR0_PFC0 register (note that bit numbers + * reflect the PowerPC convention where bit 0 is the most-significant + * bit). + * + * Katmai specific: + * RS232_RX_EN# is held HIGH during reset by hardware, keeping the + * RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in + * Hi-Z condition. This prevents contention between the MAX3411 (U26) + * and 74CBTLV3125PG (U2) during reset. + * + * RS232_RX_EN# is connected as GPIO pin 30. Once the processor + * is released from reset, this pin must be configured as an output and + * then driven high to enable the receive signals from the UART transciever. + *----------------------------------------------------------------------------*/ +#define GPIO_ENABLE(gpio) (0x80000000 >> (gpio)) + +#define PFC0_KATMAI GPIO_ENABLE(30) +#define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */ +#define GPIO_TCR_KATMAI GPIO_ENABLE(30) +#define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */ + +#define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700) +#define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704) +#define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718) +#define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C) + +#endif /* __KATMAI_H_ */ diff --git a/board/amcc/katmai/u-boot.lds b/board/amcc/katmai/u-boot.lds new file mode 100644 index 0000000000..9fe661e246 --- /dev/null +++ b/board/amcc/katmai/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/katmai/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index ae24591087..82ae4434b0 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -314,7 +314,7 @@ cpu_init_f (void) #endif #if defined (CFG_EBC_CFG) - mtebc(epcr, CFG_EBC_CFG); + mtebc(EBC0_CFG, CFG_EBC_CFG); #endif #if defined(CONFIG_WATCHDOG) diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 2d16a83420..06220c3439 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -331,7 +331,7 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; unsigned long prbdv0; -#if defined(CONFIG_440SPE) +#if defined(CONFIG_YUCCA) unsigned long sys_freq; unsigned long sys_per=0; unsigned long msr; @@ -348,7 +348,7 @@ void get_sys_info (sys_info_t * sysInfo) /*-------------------------------------------------------------------------+ | Calculate the system clock speed from the period. +-------------------------------------------------------------------------*/ - sys_freq=(ONE_BILLION/sys_per)*1000; + sys_freq = (ONE_BILLION / sys_per) * 1000; #endif /* Extract configured divisors */ @@ -385,17 +385,17 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; /* Now calculate the individual clocks */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_YUCCA) sysInfo->freqVCOMhz = (m * sys_freq) ; #else - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1); #endif sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; -#if defined(CONFIG_440SPE) +#if defined(CONFIG_YUCCA) /* Determine PCI Clock Period */ pci_clock_per = determine_pci_clock_per(); sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; @@ -408,7 +408,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif -#if defined(CONFIG_440SPE) +#if defined(CONFIG_YUCCA) unsigned long determine_sysper(void) { unsigned int fpga_clocking_reg; @@ -583,7 +583,6 @@ unsigned long determine_sysper(void) } return(sys_per); - } /*-------------------------------------------------------------------------+ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8e000d3092..a3db93ffbb 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1856,3 +1856,60 @@ pll_wait: /* execution will continue from the poweron */ /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ + +#if defined(CONFIG_440) +#define function_prolog(func_name) .text; \ + .align 2; \ + .globl func_name; \ + func_name: +#define function_epilog(func_name) .type func_name,@function; \ + .size func_name,.-func_name + +/*----------------------------------------------------------------------------+ +| mttlb3. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb3) + TLBWE(4,3,2) + blr + function_epilog(mttlb3) + +/*----------------------------------------------------------------------------+ +| mftlb3. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb3) + TLBRE(3,3,2) + blr + function_epilog(mftlb3) + +/*----------------------------------------------------------------------------+ +| mttlb2. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb2) + TLBWE(4,3,1) + blr + function_epilog(mttlb2) + +/*----------------------------------------------------------------------------+ +| mftlb2. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb2) + TLBRE(3,3,1) + blr + function_epilog(mftlb2) + +/*----------------------------------------------------------------------------+ +| mttlb1. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb1) + TLBWE(4,3,0) + blr + function_epilog(mttlb1) + +/*----------------------------------------------------------------------------+ +| mftlb1. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb1) + TLBRE(3,3,0) + blr + function_epilog(mftlb1) +#endif /* CONFIG_440 */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h new file mode 100644 index 0000000000..c750e14656 --- /dev/null +++ b/include/configs/katmai.h @@ -0,0 +1,415 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2004 Paul Reynolds + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * katmai.h - configuration for AMCC Katmai (440SPe) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KATMAI 1 /* Board is Katmai */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ +#undef CONFIG_SHOW_BOOT_PROGRESS + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE0_XCFGBASE 0xc0000400 +#define CFG_PCIE1_CFGBASE 0xc0001000 +#define CFG_PCIE1_XCFGBASE 0xc0001400 +#define CFG_PCIE2_CFGBASE 0xc0002000 +#define CFG_PCIE2_XCFGBASE 0xc0002400 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses */ +#define IIC0_DIMM0_ADDR 0x51 +#define IIC0_DIMM1_ADDR 0x52 +#undef CONFIG_STRESS +#undef ENABLE_ECC + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0x50) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* I2C DTT */ +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ +#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */ +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the ADM1021, the rest determines index into + * CFG_DTT_ADM1021 array below. + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). + * there will be one entry in this array for each two (dummy) sensors in + * CONFIG_DTT_SENSORS. + * + * For Katmai board: + * - only one ADM1021 + * - i2c addr 0x18 + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg + */ +#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=katmai\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=katmai/uImage\0" \ + "kernel_addr=fff10000\0" \ + "ramdisk_addr=fff20000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 katmai/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "kozio=bootm ffc60000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DTT | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#undef CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ + +/* + * NETWORK Support (PCI): + */ +/* Support for Intel 82557/82559/82559ER chips. */ +#define CONFIG_EEPRO100 + +/*----------------------------------------------------------------------- + * Xilinx System ACE support + *----------------------------------------------------------------------*/ +#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ +#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CFG_SYSTEMACE_BASE CFG_ACE_BASE +#define CONFIG_DOS_PARTITION 1 + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* Memory Bank 0 (Flash) initialization */ +#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CFG_EBC_PB1AP 0x7F8FFE80 +#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/*------------------------------------------------------------------------- + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + *-------------------------------------------------------------------------*/ +#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/ppc405.h b/include/ppc405.h index e475fa54cd..a49912cabb 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -240,6 +240,7 @@ #define pbesr0 0x21 /* periph bus error status reg 0 */ #define pbesr1 0x22 /* periph bus error status reg 1 */ #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP /****************************************************************************** diff --git a/include/ppc440.h b/include/ppc440.h index 91cff414af..c24f5b7ab1 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -533,9 +533,12 @@ #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ +#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ /*-----------------------------------------------------------------------------+ | Memory Controller Options 1 @@ -730,6 +733,7 @@ #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 #define SDRAM_WRDTR_WTR_MASK 0x0E000000 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 @@ -847,6 +851,7 @@ #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ -- 2.30.2