From 44cace4dabe186a486d6713de6196bc7cea2228b Mon Sep 17 00:00:00 2001 From: blogic Date: Mon, 2 May 2016 18:50:31 +0000 Subject: [PATCH] lantiq: add device tree binding for the phy clock source Signed-off-by: Mathias Kresin SVN-Revision: 49283 --- ...add-gphy-clk-src-device-tree-binding.patch | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch diff --git a/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..227d1cf25a --- /dev/null +++ b/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -423,6 +423,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -608,4 +622,6 @@ void __init ltq_soc_init(void) + + if (of_machine_is_compatible("lantiq,vr9")) + xbar_fpi_burst_disable(); ++ ++ set_phy_clock_source(np_cgu); + } -- 2.30.2