From 39bca3599aab8edbc4a6c6d10fc76b1a932e5dfa Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 2 Jul 2019 14:04:35 -0400 Subject: [PATCH] drm/amd/display: add a option to force the clock at every mode change. [Description] This is for HW negative stress testing use. force reset the dispclk and dppclk even the same clock already set in HW. Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++++++++- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 9a873e2b3736..3cff4f0518d3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -151,7 +151,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, bool enter_display_off = false; bool dpp_clock_lowered = false; struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; + bool force_reset = false; + if (clk_mgr_base->clks.dispclk_khz == 0 || + dc->debug.force_clock_mode & 0x1) { + //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. + force_reset = true; + //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. + } display_count = clk_mgr_helper_get_active_display_cnt(dc, context); if (dc->res_pool->pp_smu) pp_smu = &dc->res_pool->pp_smu->nv_funcs; @@ -223,7 +230,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, update_dispclk = true; } - if (dc->config.forced_clocks == false) { + if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { if (dpp_clock_lowered) { // if clock is being lowered, increase DTO before lowering refclk dcn20_update_clocks_update_dpp_dto(clk_mgr, context); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a5b5afd48a7b..584fabf5a9a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -385,6 +385,7 @@ struct dc_debug_options { #if defined(CONFIG_DRM_AMD_DC_DCN2_0) bool cm_in_bypass; #endif + int force_clock_mode;/*every mode change.*/ }; struct dc_debug_data { -- 2.30.2