From 38b2df95c53be4bd5421d933ca0dabbcb82741d0 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller Date: Mon, 13 Aug 2012 21:18:02 -0300 Subject: [PATCH] [media] drx-j: add a driver for Trident drx-j frontend Add support for the Trident DRX-J driver, including a card profile for the PCTV 80e which uses the chip. Thanks to Trident for allowing the release of this code under a BSD license, and of course Hauppauge/PCTV for pushing for its release to the community. [pdickeybeta@gmail.com: modified to fix compilation errors and also to move the driver files from the drx39xy subdirectory to the frontends directory] [m.chehab@samsung.com: fix merge conflicts, commented drx-j compilation and added EM28XX_R06_I2C_CLK setup also to the board setup] Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.em28xx | 1 + drivers/media/dvb-frontends/Kconfig | 2 + drivers/media/dvb-frontends/Makefile | 1 + drivers/media/dvb-frontends/drx39xyj/Kconfig | 8 + drivers/media/dvb-frontends/drx39xyj/Makefile | 3 + .../media/dvb-frontends/drx39xyj/bsp_host.h | 82 + .../media/dvb-frontends/drx39xyj/bsp_i2c.h | 219 + .../media/dvb-frontends/drx39xyj/bsp_tuner.h | 218 + .../media/dvb-frontends/drx39xyj/bsp_types.h | 230 + .../media/dvb-frontends/drx39xyj/drx39xxj.c | 456 + .../media/dvb-frontends/drx39xyj/drx39xxj.h | 40 + .../dvb-frontends/drx39xyj/drx39xxj_dummy.c | 134 + .../dvb-frontends/drx39xyj/drx_dap_fasi.c | 674 + .../dvb-frontends/drx39xyj/drx_dap_fasi.h | 267 + .../media/dvb-frontends/drx39xyj/drx_driver.c | 1600 ++ .../media/dvb-frontends/drx39xyj/drx_driver.h | 2588 +++ .../drx39xyj/drx_driver_version.h | 83 + drivers/media/dvb-frontends/drx39xyj/drxj.c | 16680 ++++++++++++++++ drivers/media/dvb-frontends/drx39xyj/drxj.h | 732 + .../media/dvb-frontends/drx39xyj/drxj_map.h | 15350 ++++++++++++++ .../media/dvb-frontends/drx39xyj/drxj_mc.h | 3947 ++++ .../dvb-frontends/drx39xyj/drxj_mc_vsb.h | 752 + .../dvb-frontends/drx39xyj/drxj_mc_vsbqam.h | 1444 ++ .../dvb-frontends/drx39xyj/drxj_options.h | 68 + drivers/media/usb/em28xx/em28xx-cards.c | 20 + drivers/media/usb/em28xx/em28xx-dvb.c | 27 + drivers/media/usb/em28xx/em28xx.h | 1 + 27 files changed, 45627 insertions(+) create mode 100644 drivers/media/dvb-frontends/drx39xyj/Kconfig create mode 100644 drivers/media/dvb-frontends/drx39xyj/Makefile create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_host.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/bsp_types.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj.c create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_map.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h create mode 100644 drivers/media/dvb-frontends/drx39xyj/drxj_options.h diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index e81864405102..404ac9b5f440 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -57,6 +57,7 @@ 56 -> Pinnacle Hybrid Pro (330e) (em2882) [2304:0226] 57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316] 58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041] + 59 -> Pinnacle PCTV HD Mini (em2874) [2304:023f] 60 -> Hauppauge WinTV HVR 850 (em2883) [2040:651f] 61 -> Pixelview PlayTV Box 4 USB 2.0 (em2820/em2840) 62 -> Gadmei TVR200 (em2820/em2840) diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 44330718a25e..611c794856a9 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -650,6 +650,8 @@ config DVB_TUNER_DIB0090 comment "SEC control devices for DVB-S" depends on DVB_CORE +source "drivers/media/dvb-frontends/drx39xyj/Kconfig" + config DVB_LNBP21 tristate "LNBP21/LNBH24 SEC controllers" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index b5815c803d19..282aba2fe8db 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_DVB_HD29L2) += hd29l2.o obj-$(CONFIG_DVB_DS3000) += ds3000.o obj-$(CONFIG_DVB_TS2020) += ts2020.o obj-$(CONFIG_DVB_MB86A16) += mb86a16.o +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj/ obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o obj-$(CONFIG_DVB_IX2505V) += ix2505v.o obj-$(CONFIG_DVB_STV0367) += stv0367.o diff --git a/drivers/media/dvb-frontends/drx39xyj/Kconfig b/drivers/media/dvb-frontends/drx39xyj/Kconfig new file mode 100644 index 000000000000..5bcf6b4cb74a --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Kconfig @@ -0,0 +1,8 @@ +config DVB_DRX39XYJ + tristate "Micronas DRX-J demodulator" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + depends on BROKEN + help + An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want + to support this frontend. diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile new file mode 100644 index 000000000000..b44dc3710229 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -0,0 +1,3 @@ +drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o + +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_host.h b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h new file mode 100644 index 000000000000..30f711d5cd21 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_host.h @@ -0,0 +1,82 @@ +/** +* \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $ +* +* \brief Host and OS dependent type definitions, macro's and functions +* +*/ + +/* +* $(c) 2004-2005,2007-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXBSP_HOST_H__ +#define __DRXBSP_HOST_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ +#include "bsp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ +DRXStatus_t DRXBSP_HST_Init( void ); + +DRXStatus_t DRXBSP_HST_Term( void ); + +void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n); + +int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n); + +u32_t DRXBSP_HST_Clock( void ); + +DRXStatus_t DRXBSP_HST_Sleep( u32_t n ); + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif + +#endif /* __DRXBSP_HOST_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h new file mode 100644 index 000000000000..6f4e69fb96af --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h @@ -0,0 +1,219 @@ +/** +* \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $ +* +* \brief I2C API, implementation depends on board specifics +* +* This module encapsulates I2C access.In some applications several devices +* share one I2C bus. If these devices have the same I2C address some kind +* off "switch" must be implemented to ensure error free communication with +* one device. In case such a "switch" is used, the device ID can be used +* to implement control over this "switch". +* +* +*/ + +/* +* $(c) 2004-2005,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +#ifndef __BSPI2C_H__ +#define __BSPI2C_H__ +/*------------------------------------------------------------------------------ +INCLUDES +------------------------------------------------------------------------------*/ +#include "bsp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------------ +TYPEDEFS +------------------------------------------------------------------------------*/ +/** +* \typedef I2Caddr_t +* \brief I2C device address (7-bit or 10-bit) +*/ +typedef u16_t I2Caddr_t; + +/** +* \typedef I2CdevId_t +* \brief Device identifier. +* +* The device ID can be useful if several devices share an I2C address, +* or if multiple I2C busses are used. +* It can be used to control a "switch" selecting the correct device and/or +* I2C bus. +* +*/ +typedef u16_t I2CdevId_t; + +/** +* \struct _I2CDeviceAddr_t +* \brief I2C device parameters. +* +* This structure contains the I2C address, the device ID and a userData pointer. +* The userData pointer can be used for application specific purposes. +* +*/ +struct _I2CDeviceAddr_t { + I2Caddr_t i2cAddr; /**< The I2C address of the device. */ + I2CdevId_t i2cDevId; /**< The device identifier. */ + void *userData; /**< User data pointer */ +}; + +/** +* \typedef I2CDeviceAddr_t +* \brief I2C device parameters. +* +* This structure contains the I2C address and the device ID. +* +*/ +typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t; + +/** +* \typedef pI2CDeviceAddr_t +* \brief Pointer to I2C device parameters. +*/ +typedef I2CDeviceAddr_t *pI2CDeviceAddr_t; + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +MACROS +------------------------------------------------------------------------------*/ + +/** +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +ENUM +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTS +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + + +/** +* \fn DRXBSP_I2C_Init() +* \brief Initialize I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Initialization successful. +* \retval DRX_STS_ERROR Initialization failed. +*/ +DRXStatus_t DRXBSP_I2C_Init( void ); + + +/** +* \fn DRXBSP_I2C_Term() +* \brief Terminate I2C communication module. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Termination successful. +* \retval DRX_STS_ERROR Termination failed. +*/ +DRXStatus_t DRXBSP_I2C_Term( void ); + +/** +* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, +* u16_t wCount, +* pu8_t wData, +* pI2CDeviceAddr_t rDevAddr, +* u16_t rCount, +* pu8_t rData) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param wDevAddr The device i2c address and the device ID to write to +* \param wCount The number of bytes to write +* \param wData The array to write the data to +* \param rDevAddr The device i2c address and the device ID to read from +* \param rCount The number of bytes to read +* \param rData The array to read the data from +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Succes. +* \retval DRX_STS_ERROR Failure. +* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both wDevAddr and rDevAddr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ +DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData); + + +/** +* \fn DRXBSP_I2C_ErrorText() +* \brief Returns a human readable error. +* Counter part of numerical DRX_I2C_Error_g. +* +* \return char* Pointer to human readable error text. +*/ +char* DRXBSP_I2C_ErrorText( void ); + +/** +* \var DRX_I2C_Error_g; +* \brief I2C specific error codes, platform dependent. +*/ +extern int DRX_I2C_Error_g; + + +/*------------------------------------------------------------------------------ +THE END +------------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __BSPI2C_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h new file mode 100644 index 000000000000..e5693d0d5e9b --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h @@ -0,0 +1,218 @@ +/** +* \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $ +* +* \brief Tuner dependable type definitions, macro's and functions +* +*/ + +/* +* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +#ifndef __DRXBSP_TUNER_H__ +#define __DRXBSP_TUNER_H__ +/*------------------------------------------------------------------------------ +INCLUDES +------------------------------------------------------------------------------*/ +#include "bsp_types.h" +#include "bsp_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + + + /* Sub-mode bits should be adjacent and incremental */ +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + +#define TUNER_MODE_SUB_MAX 8 +#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ + TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ + TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ + TUNER_MODE_SUB6 | TUNER_MODE_SUB7 ) + +/*------------------------------------------------------------------------------ +TYPEDEFS +------------------------------------------------------------------------------*/ + +typedef u32_t TUNERMode_t; +typedef pu32_t pTUNERMode_t; + +typedef char* TUNERSubMode_t; /* description of submode */ +typedef TUNERSubMode_t *pTUNERSubMode_t; + + +typedef enum { + + TUNER_LOCKED, + TUNER_NOT_LOCKED + +} TUNERLockStatus_t, *pTUNERLockStatus_t; + + +typedef struct { + + char *name; /* Tuner brand & type name */ + DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */ + DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */ + + u8_t subMode; /* Index to sub-mode in use */ + pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/ + u8_t subModes; /* Number of available sub-modes */ + + /* The following fields will be either 0, NULL or FALSE and do not need + initialisation */ + void *selfCheck; /* gives proof of initialization */ + Bool_t programmed; /* only valid if selfCheck is OK */ + DRXFrequency_t RFfrequency; /* only valid if programmed */ + DRXFrequency_t IFfrequency; /* only valid if programmed */ + + void* myUserData; /* pointer to associated demod instance */ + u16_t myCapabilities; /* value for storing application flags */ + +} TUNERCommonAttr_t, *pTUNERCommonAttr_t; + + +/* +* Generic functions for DRX devices. +*/ +typedef struct TUNERInstance_s *pTUNERInstance_t; + +typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner ); +typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner ); + +typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t frequency ); + +typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ); + +typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat ); + +typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData ); + +typedef struct +{ + TUNEROpenFunc_t openFunc; + TUNERCloseFunc_t closeFunc; + TUNERSetFrequencyFunc_t setFrequencyFunc; + TUNERGetFrequencyFunc_t getFrequencyFunc; + TUNERLockStatusFunc_t lockStatusFunc; + TUNERi2cWriteReadFunc_t i2cWriteReadFunc; + +} TUNERFunc_t, *pTUNERFunc_t; + +typedef struct TUNERInstance_s { + + I2CDeviceAddr_t myI2CDevAddr; + pTUNERCommonAttr_t myCommonAttr; + void* myExtAttr; + pTUNERFunc_t myFunct; + +} TUNERInstance_t; + + +/*------------------------------------------------------------------------------ +ENUM +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTS +------------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ); + +DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ); + +DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t frequency ); + +DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ); + +DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner, + pTUNERLockStatus_t lockStat ); + +DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData); + +/*------------------------------------------------------------------------------ +THE END +------------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXBSP_TUNER_H__ */ + +/* End of file */ diff --git a/drivers/media/dvb-frontends/drx39xyj/bsp_types.h b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h new file mode 100644 index 000000000000..4a0dc0ba83bd --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/bsp_types.h @@ -0,0 +1,230 @@ +/** +* \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $ +* +* \brief General type definitions for board support packages +* +* This file contains type definitions that are needed for almost any +* board support package. +* The definitions are host and project independent. +* +*/ + +/* +* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __BSP_TYPES_H__ +#define __BSP_TYPES_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + +/** +* \typedef unsigned char u8_t +* \brief type definition of an unsigned 8 bits integer +*/ +typedef unsigned char u8_t; +/** +* \typedef char s8_t +* \brief type definition of a signed 8 bits integer +*/ +typedef char s8_t; +/** +* \typedef unsigned short u16_t *pu16_t +* \brief type definition of an unsigned 16 bits integer +*/ +typedef unsigned short u16_t; +/** +* \typedef short s16_t +* \brief type definition of a signed 16 bits integer +*/ +typedef short s16_t; +/** +* \typedef unsigned long u32_t +* \brief type definition of an unsigned 32 bits integer +*/ +typedef unsigned long u32_t; +/** +* \typedef long s32_t +* \brief type definition of a signed 32 bits integer +*/ +typedef long s32_t; +/* +* \typedef struct ... u64_t +* \brief type definition of an usigned 64 bits integer +*/ +typedef struct { + u32_t MSLW; + u32_t LSLW; +} u64_t; +/* +* \typedef struct ... i64_t +* \brief type definition of a signed 64 bits integer +*/ +typedef struct { + s32_t MSLW; + u32_t LSLW; +} s64_t; + +/** +* \typedef u8_t *pu8_t +* \brief type definition of pointer to an unsigned 8 bits integer +*/ +typedef u8_t *pu8_t; +/** +* \typedef s8_t *ps8_t +* \brief type definition of pointer to a signed 8 bits integer +*/ +typedef s8_t *ps8_t; +/** +* \typedef u16_t *pu16_t +* \brief type definition of pointer to an unsigned 16 bits integer +*/ +typedef u16_t *pu16_t; +/** +* \typedef s16_t *ps16_t +* \brief type definition of pointer to a signed 16 bits integer +*/ +typedef s16_t *ps16_t; +/** +* \typedef u32_t *pu32_t +* \brief type definition of pointer to an unsigned 32 bits integer +*/ +typedef u32_t *pu32_t; +/** +* \typedef s32_t *ps32_t +* \brief type definition of pointer to a signed 32 bits integer +*/ +typedef s32_t *ps32_t; +/** +* \typedef u64_t *pu64_t +* \brief type definition of pointer to an usigned 64 bits integer +*/ +typedef u64_t *pu64_t; +/** +* \typedef s64_t *ps64_t +* \brief type definition of pointer to a signed 64 bits integer +*/ +typedef s64_t *ps64_t; + + +/** +* \typedef s32_t DRXFrequency_t +* \brief type definition of frequency +*/ +typedef s32_t DRXFrequency_t; + +/** +* \typedef DRXFrequency_t *pDRXFrequency_t +* \brief type definition of a pointer to a frequency +*/ +typedef DRXFrequency_t *pDRXFrequency_t; + +/** +* \typedef u32_t DRXSymbolrate_t +* \brief type definition of symbol rate +*/ +typedef u32_t DRXSymbolrate_t; + +/** +* \typedef DRXSymbolrate_t *pDRXSymbolrate_t +* \brief type definition of a pointer to a symbol rate +*/ +typedef DRXSymbolrate_t *pDRXSymbolrate_t; + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ +/** +* \def NULL +* \brief Define NULL for target. +*/ +#ifndef NULL +#define NULL (0) +#endif + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/* +* Boolean datatype. Only define if not already defined TRUE or FALSE. +*/ +#if defined (TRUE) || defined (FALSE) +typedef int Bool_t; +#else +/** +* \enum Bool_t +* \brief Boolean type +*/ +typedef enum { + FALSE = 0, + TRUE +} Bool_t; +#endif +typedef Bool_t *pBool_t; + +/** +* \enum DRXStatus_t +* \brief Various return statusses +*/ +typedef enum { + DRX_STS_READY = 3, /**< device/service is ready */ + DRX_STS_BUSY = 2, /**< device/service is busy */ + DRX_STS_OK = 1, /**< everything is OK */ + DRX_STS_INVALID_ARG = -1, /**< invalid arguments */ + DRX_STS_ERROR = -2, /**< general error */ + DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */ +} DRXStatus_t, *pDRXStatus_t; + + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/** +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __BSP_TYPES_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c new file mode 100644 index 000000000000..524c07d9d451 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.c @@ -0,0 +1,456 @@ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drx39xxj.h" +#include "drx_driver.h" +#include "bsp_types.h" +#include "bsp_tuner.h" +#include "drxj_mc.h" +#include "drxj.h" + +static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXPowerMode_t powerMode; + + if (enable) + powerMode = DRX_POWER_UP; + else + powerMode = DRX_POWER_DOWN; + + result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode); + if (result != DRX_STS_OK) { + printk("Power state change failed\n"); + return 0; + } + + state->powered_up = enable; + return 0; +} + +static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXLockStatus_t lock_status; + + *status = 0; + + result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get lock status!\n"); + *status = 0; + } + + switch (lock_status) { + case DRX_NEVER_LOCK: + *status = 0; + printk("drx says NEVER_LOCK\n"); + break; + case DRX_NOT_LOCKED: + *status = 0; + break; + case DRX_LOCK_STATE_1: + case DRX_LOCK_STATE_2: + case DRX_LOCK_STATE_3: + case DRX_LOCK_STATE_4: + case DRX_LOCK_STATE_5: + case DRX_LOCK_STATE_6: + case DRX_LOCK_STATE_7: + case DRX_LOCK_STATE_8: + case DRX_LOCK_STATE_9: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI + | FE_HAS_SYNC; + break; + case DRX_LOCKED: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI + | FE_HAS_SYNC + | FE_HAS_LOCK; + break; + default: + printk("Lock state unknown %d\n", lock_status); + } + + return 0; +} + +static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get ber!\n"); + *ber = 0; + return 0; + } + + *ber = sig_quality.postReedSolomonBER; + return 0; +} + +static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get signal strength!\n"); + *strength = 0; + return 0; + } + + /* 1-100% scaled to 0-65535 */ + *strength = (sig_quality.indicator * 65535 / 100); + return 0; +} + +static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not read snr!\n"); + *snr = 0; + return 0; + } + + *snr = sig_quality.MER; + return 0; +} + +static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStatus_t result; + DRXSigQuality_t sig_quality; + + result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not get uc blocks!\n"); + *ucblocks = 0; + return 0; + } + + *ucblocks = sig_quality.packetError; + return 0; +} + +static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +{ + return 0; +} + +static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) +{ +#ifdef DJH_DEBUG + int i; +#endif + struct drx39xxj_state* state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + DRXStandard_t standard = DRX_STANDARD_8VSB; + DRXChannel_t channel; + DRXStatus_t result; + DRXUIOData_t uioData; + DRXChannel_t defChannel = {/* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; + + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + /* Now make the tuner do it's thing... */ + if (fe->ops.tuner_ops.set_params) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.set_params(fe, p); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + if (standard != state->current_standard || state->powered_up == 0) { + /* Set the standard (will be powered up if necessary */ + result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); + if (result != DRX_STS_OK) { + printk("Failed to set standard! result=%02x\n", result); + return -EINVAL; + } + state->powered_up = 1; + state->current_standard = standard; + } + + /* set channel parameters */ + channel = defChannel; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = DRX_CONSTELLATION_AUTO; + + /* program channel */ + result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); + if (result != DRX_STS_OK) { + printk("Failed to set channel!\n"); + return -EINVAL; + } + + // Just for giggles, let's shut off the LNA again.... + uioData.uio = DRX_UIO1; + uioData.value = FALSE; + result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + if (result != DRX_STS_OK) { + printk("Failed to disable LNA!\n"); + return 0; + } + +#ifdef DJH_DEBUG + for(i = 0; i < 2000; i++) { + fe_status_t status; + drx39xxj_read_status(fe, &status); + printk("i=%d status=%d\n", i, status); + msleep(100); + i += 100; + } +#endif + + return 0; +} + + +static int drx39xxj_sleep(struct dvb_frontend* fe) +{ + /* power-down the demodulator */ + return drx39xxj_set_powerstate(fe, 0); +} + +static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + DRXDemodInstance_t *demod = state->demod; + Bool_t i2c_gate_state; + DRXStatus_t result; + +#ifdef DJH_DEBUG + printk("i2c gate call: enable=%d state=%d\n", enable, + state->i2c_gate_open); +#endif + + if (enable) + i2c_gate_state = TRUE; + else + i2c_gate_state = FALSE; + + if (state->i2c_gate_open == enable) { + /* We're already in the desired state */ + return 0; + } + + result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); + if (result != DRX_STS_OK) { + printk("drx39xxj: could not open i2c gate [%d]\n", result); + dump_stack(); + } else { + state->i2c_gate_open = enable; + } + return 0; +} + + +static int drx39xxj_init(struct dvb_frontend* fe) +{ + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + return 0; +} + +static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + return 0; +} + +static void drx39xxj_release(struct dvb_frontend* fe) +{ + struct drx39xxj_state* state = fe->demodulator_priv; + kfree(state); +} + +static struct dvb_frontend_ops drx39xxj_ops; + +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) +{ + struct drx39xxj_state* state = NULL; + + I2CDeviceAddr_t *demodAddr = NULL; + DRXCommonAttr_t *demodCommAttr = NULL; + DRXJData_t *demodExtAttr = NULL; + DRXDemodInstance_t *demod = NULL; + DRXUIOCfg_t uioCfg; + DRXUIOData_t uioData; + DRXStatus_t result; + + /* allocate memory for the internal state */ + state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + if (state == NULL) goto error; + + demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL); + if (demod == NULL) goto error; + + demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL); + if (demodAddr == NULL) goto error; + + demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL); + if (demodCommAttr == NULL) goto error; + + demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL); + if (demodExtAttr == NULL) goto error; + + /* setup the state */ + state->i2c = i2c; + state->demod = demod; + + memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t)); + + demod->myI2CDevAddr = demodAddr; + memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g, + sizeof(I2CDeviceAddr_t)); + demod->myI2CDevAddr->userData = state; + demod->myCommonAttr = demodCommAttr; + memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, + sizeof(DRXCommonAttr_t)); + demod->myCommonAttr->microcode = DRXJ_MC_MAIN; + // demod->myCommonAttr->verifyMicrocode = FALSE; + demod->myCommonAttr->verifyMicrocode = TRUE; + demod->myCommonAttr->intermediateFreq = 5000; + + demod->myExtAttr = demodExtAttr; + memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t)); + ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE; + + demod->myTuner = NULL; + + result = DRX_Open(demod); + if (result != DRX_STS_OK) { + printk("DRX open failed! Aborting\n"); + kfree(state); + return NULL; + } + + /* Turn off the LNA */ + uioCfg.uio = DRX_UIO1; + uioCfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); + if (result != DRX_STS_OK) { + printk("Failed to setup LNA GPIO!\n"); + return NULL; + } + + uioData.uio = DRX_UIO1; + uioData.value = FALSE; + result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); + if (result != DRX_STS_OK) { + printk("Failed to disable LNA!\n"); + return NULL; + } + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &drx39xxj_ops, + sizeof(struct dvb_frontend_ops)); + + state->frontend.demodulator_priv = state; + return &state->frontend; + +error: + if (state != NULL) + kfree(state); + if (demod != NULL) + kfree(demod); + return NULL; +} + +static struct dvb_frontend_ops drx39xxj_ops = { + + .info = { + .name = "Micronas DRX39xxj family Frontend", + .type = FE_ATSC | FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 51000000, + .frequency_max = 858000000, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, + + .init = drx39xxj_init, + .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, + .sleep = drx39xxj_sleep, + .set_frontend = drx39xxj_set_frontend, + .get_frontend = drx39xxj_get_frontend, + .get_tune_settings = drx39xxj_get_tune_settings, + .read_status = drx39xxj_read_status, + .read_ber = drx39xxj_read_ber, + .read_signal_strength = drx39xxj_read_signal_strength, + .read_snr = drx39xxj_read_snr, + .read_ucblocks = drx39xxj_read_ucblocks, + .release = drx39xxj_release, +}; + +MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); +MODULE_AUTHOR("Devin Heitmueller"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drx39xxj_attach); diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h new file mode 100644 index 000000000000..eea6a01afa78 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -0,0 +1,40 @@ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#ifndef DRX39XXJ_H +#define DRX39XXJ_H + +#include +#include "dvb_frontend.h" +#include "drx_driver.h" + +struct drx39xxj_state { + struct i2c_adapter *i2c; + DRXDemodInstance_t *demod; + DRXStandard_t current_standard; + struct dvb_frontend frontend; + int powered_up:1; + unsigned int i2c_gate_open:1; +}; + +extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c); + +#endif // DVB_DUMMY_FE_H diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c new file mode 100644 index 000000000000..2b9344f92449 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "drx_driver.h" +#include "bsp_types.h" +#include "bsp_tuner.h" +#include "drx39xxj.h" + +/* Dummy function to satisfy drxj.c */ +DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + DRXFrequency_t centerFrequency ) +{ + return DRX_STS_OK; +} + +DRXStatus_t +DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner, + TUNERMode_t mode, + pDRXFrequency_t RFfrequency, + pDRXFrequency_t IFfrequency ) +{ + return DRX_STS_OK; +} + +DRXStatus_t DRXBSP_HST_Sleep( u32_t n ) +{ + msleep(n); + return DRX_STS_OK; +} + +u32_t DRXBSP_HST_Clock( void ) +{ + return jiffies_to_msecs(jiffies); +} + +int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n) +{ + return ( memcmp( s1, s2, (size_t) n) ); +} + +void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n) +{ + return ( memcpy( to, from, (size_t) n) ); +} + +DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData ) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (wDevAddr == NULL) { + /* Read only */ + state = rDevAddr->userData; + msg[0].addr = rDevAddr->i2cAddr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = rData; + msg[0].len = rCount; + num_msgs = 1; + } else if (rDevAddr == NULL) { + /* Write only */ + state = wDevAddr->userData; + msg[0].addr = wDevAddr->i2cAddr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = wCount; + num_msgs = 1; + } else { + /* Both write and read */ + state = wDevAddr->userData; + msg[0].addr = wDevAddr->i2cAddr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = wCount; + msg[1].addr = rDevAddr->i2cAddr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = rData; + msg[1].len = rCount; + num_msgs = 2; + } + + if (state->i2c == NULL) { + printk("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + + return DRX_STS_OK; + +#ifdef DJH_DEBUG + struct drx39xxj_state *state = wDevAddr->userData; + + struct i2c_msg msg[2] = { + { .addr = wDevAddr->i2cAddr, + .flags = 0, .buf = wData, .len = wCount }, + { .addr = rDevAddr->i2cAddr, + .flags = I2C_M_RD, .buf = rData, .len = rCount }, + }; + + printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + wDevAddr->i2cAddr, state->i2c, wCount, rCount); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + printk(KERN_WARNING "drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c new file mode 100644 index 000000000000..cc10daec3770 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c @@ -0,0 +1,674 @@ +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* These functions know how the chip's memory and registers are to be accessed, +* but nothing more. +* +* These functions should not need adapting to a new platform. +* +* USAGE: +* - +* +* NOTES: +* $(c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +* +*******************************************************************************/ + +#include "drx_dap_fasi.h" +#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */ + +/*============================================================================*/ + +/* Function prototypes */ +static DRXStatus_t DRXDAP_FASI_WriteBlock ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadBlock ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data */ + pu8_t data, /* data to send */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_WriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u16_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu16_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u16_t datain, /* data to send */ + pu16_t dataout); /* data to receive back */ + +static DRXStatus_t DRXDAP_FASI_WriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u32_t data, /* data to write */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu32_t data, /* buffer to receive data */ + DRXflags_t flags); /* special device flags */ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout); /* data to receive back */ + +/* The version structure of this protocol implementation */ +char drxDapFASIModuleName[] = "FASI Data Access Protocol"; +char drxDapFASIVersionText[] = ""; + +DRXVersion_t drxDapFASIVersion = +{ + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapFASIModuleName, /**< name or description of module */ + + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapFASIVersionText /**< version as text string */ +}; + +/* The structure containing the protocol interface */ +DRXAccessFunc_t drxDapFASIFunct_g = +{ + &drxDapFASIVersion, + DRXDAP_FASI_WriteBlock, /* Supported */ + DRXDAP_FASI_ReadBlock, /* Supported */ + DRXDAP_FASI_WriteReg8, /* Not supported */ + DRXDAP_FASI_ReadReg8, /* Not supported */ + DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ + DRXDAP_FASI_WriteReg16, /* Supported */ + DRXDAP_FASI_ReadReg16, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ + DRXDAP_FASI_WriteReg32, /* Supported */ + DRXDAP_FASI_ReadReg32, /* Supported */ + DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ +}; + +/*============================================================================*/ + +/* Functions not supported by protocol*/ + +static DRXStatus_t DRXDAP_FASI_WriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + u8_t data, /* data to write */ + DRXflags_t flags) /* special device flags */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register */ + pu8_t data, /* buffer to receive data */ + DRXflags_t flags) /* special device flags */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u8_t datain, /* data to send */ + pu8_t dataout) /* data to receive back */ +{ + return DRX_STS_ERROR; +} + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* address of register */ + DRXaddr_t raddr, /* address to read back from */ + u32_t datain, /* data to send */ + pu32_t dataout) /* data to receive back */ +{ + return DRX_STS_ERROR; +} + +/*============================================================================*/ + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadBlock ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t datasize, -- number of bytes to read +* pu8_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read block data from chip address. Because the chip is word oriented, +* the number of bytes to read must be even. +* +* Make sure that the buffer to receive the data is large enough. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data read back is NOT translated to the endianness of +* the target platform. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: data read is in *data. +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags ) +{ + u8_t buf[4]; + u16_t bufx; + DRXStatus_t rc; + u16_t overheadSize = 0; + + /* Check parameters ********************************************************/ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); + + if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || + ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && + DRXDAP_FASI_LONG_FORMAT( addr ) ) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize!=0) && (data==NULL)) || + ((datasize & 1)==1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Read block from I2C *****************************************************/ + do { + u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); + + bufx = 0; + + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; + +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + /* short format address preferred but long format otherwise */ + if ( DRXDAP_FASI_LONG_FORMAT(addr) ) + { +#endif +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); +#endif +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + } else { +#endif +#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); +#endif +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) ) + } +#endif + + + + +#if DRXDAP_SINGLE_MASTER + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0); + if (rc == DRX_STS_OK) + { + rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data); + } +#else + /* In multi master mode, do everything in one RW action */ + rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data); +#endif + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == DRX_STS_OK); + + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t waddr, -- address of chip register/memory +* DRXaddr_t raddr, -- chip address to read back from +* u16_t wdata, -- data to send +* pu16_t rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read back data is at *rdata +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata ) +{ + DRXStatus_t rc=DRX_STS_ERROR; + +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + if (rdata == NULL) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == DRX_STS_OK) + { + rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0); + } +#endif + + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* pu16_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read one 16-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read data is at *data +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); + *data = buf[0] + (((u16_t) buf[1]) << 8); + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_ReadReg32 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* pu32_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Read one 32-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - DRX_STS_OK if reading was successful +* in that case: read data is at *data +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags); + *data = (((u32_t) buf[0]) << 0) + + (((u32_t) buf[1]) << 8) + + (((u32_t) buf[2]) << 16) + + (((u32_t) buf[3]) << 24); + return rc; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteBlock ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t datasize, -- number of bytes to read +* pu8_t data, -- data to receive +* DRXflags_t flags) -- special device flags +* +* Write block data to chip address. Because the chip is word oriented, +* the number of bytes to write must be even. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data being written is NOT translated from the endianness of +* the target platform. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags ) +{ + u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ]; + DRXStatus_t st = DRX_STS_ERROR; + DRXStatus_t firstErr = DRX_STS_OK; + u16_t overheadSize = 0; + u16_t blockSize = 0; + + /* Check parameters ********************************************************/ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 ); + + if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) || + ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) && + DRXDAP_FASI_LONG_FORMAT( addr ) ) || + (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize!=0) && (data==NULL)) || + ((datasize & 1)==1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Write block to I2C ******************************************************/ + blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; + do + { + u16_t todo = 0; + u16_t bufx = 0; + + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + /* short format address preferred but long format otherwise */ + if ( DRXDAP_FASI_LONG_FORMAT(addr) ) + { +#endif +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) + buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01); + buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF); +#endif +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + } else { +#endif +#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) + buf[bufx++] = (u8_t) ((addr << 1) & 0xFF); + buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) ); +#endif +#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \ + ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) ) + } +#endif + + /* + In single master mode blockSize can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Addres must be rewriten because HI is reset after data transport and + expects an address. + */ + todo = (blockSize < datasize ? blockSize : datasize); + if (todo==0) + { + u16_t overheadSizeI2cAddr = 0; + u16_t dataBlockSize = 0; + + overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1); + dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; + + /* write device address */ + st = DRXBSP_I2C_WriteRead( devAddr, + (u16_t) (bufx), + buf, + (pI2CDeviceAddr_t)(NULL), + 0, + (pu8_t)(NULL) ); + + if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) + { + /* at the end, return the first error encountered */ + firstErr = st; + } + bufx = 0; + todo = (dataBlockSize < datasize ? dataBlockSize : datasize); + } + DRXBSP_HST_Memcpy (&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = DRXBSP_I2C_WriteRead( devAddr, + (u16_t)(bufx + todo), + buf, + (pI2CDeviceAddr_t)(NULL), + 0, + (pu8_t)(NULL) ); + + if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) ) + { + /* at the end, return the first error encountered */ + firstErr = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return firstErr; +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteReg16 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u16_t data, -- data to send +* DRXflags_t flags) -- special device flags +* +* Write one 16-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (data)]; + + buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); + buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); + + return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); +} + + + + +/****************************** +* +* DRXStatus_t DRXDAP_FASI_WriteReg32 ( +* pI2CDeviceAddr_t devAddr, -- address of I2C device +* DRXaddr_t addr, -- address of chip register/memory +* u32_t data, -- data to send +* DRXflags_t flags) -- special device flags +* +* Write one 32-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - DRX_STS_OK if writing was successful +* - DRX_STS_ERROR if anything went wrong +* +******************************/ + +static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags ) +{ + u8_t buf[sizeof (data)]; + + buf[0] = (u8_t) ( (data >> 0 ) & 0xFF ); + buf[1] = (u8_t) ( (data >> 8 ) & 0xFF ); + buf[2] = (u8_t) ( (data >> 16) & 0xFF ); + buf[3] = (u8_t) ( (data >> 24) & 0xFF ); + + return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags); +} diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h new file mode 100644 index 000000000000..77ff3717c514 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -0,0 +1,267 @@ +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* +* USAGE: +* Include. +* +* NOTES: +* $(c) 2008-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +* +*******************************************************************************/ + +/*-------- compilation control switches --------------------------------------*/ + +#ifndef __DRX_DAP_FASI_H__ +#define __DRX_DAP_FASI_H__ + +/*-------- Required includes -------------------------------------------------*/ + +#include "drx_driver.h" + +/*-------- Defines, configuring the API --------------------------------------*/ + +/******************************************** +* Allowed address formats +********************************************/ + +/* +* Comments about short/long addressing format: +* +* The DAP FASI offers long address format (4 bytes) and short address format +* (2 bytes). The DAP can operate in 3 modes: +* (1) only short +* (2) only long +* (3) both long and short but short preferred and long only when necesarry +* +* These modes must be selected compile time via compile switches. +* Compile switch settings for the diffrent modes: +* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0 +* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* +* The default setting will be (3) both long and short. +* The default setting will need no compile switches. +* The default setting must be overridden if compile switches are already +* defined. +* +*/ + +/* set default */ +#if !defined( DRXDAPFASI_LONG_ADDR_ALLOWED ) +#define DRXDAPFASI_LONG_ADDR_ALLOWED 1 +#endif + +/* set default */ +#if !defined( DRXDAPFASI_SHORT_ADDR_ALLOWED ) +#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1 +#endif + +/* check */ +#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \ + ( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) ) +#error At least one of short- or long-addressing format must be allowed. +*; /* illegal statement to force compiler error */ +#endif + + +/******************************************** +* Single/master multi master setting +********************************************/ +/* +* Comments about SINGLE MASTER/MULTI MASTER modes: +* +* Consider the two sides:1) the master and 2)the slave. +* +* Master: +* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch +* + single master mode means no use of repeated starts +* + multi master mode means use of repeated starts +* Default is single master. +* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER. +* +* Slave: +* Single/multi master selected via the flags in the FASI protocol. +* + single master means remember memory address between i2c packets +* + multimaster means flush memory address between i2c packets +* Default is single master, DAP FASI changes multi-master setting silently +* into single master setting. This cannot be overrriden. +* +*/ +/* set default */ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/******************************************** +* Chunk/mode checking +********************************************/ +/* +* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and +* in combination with short and long addressing format. All text below +* assumes long addressing format. The table also includes information +* for short ADDRessing format. +* +* In single master mode, data can be written by sending the register address +* first, then two or four bytes of data in the next packet. +* Because the device address plus a register address equals five bytes, +* the mimimum chunk size must be five. +* If ten-bit I2C device addresses are used, the minimum chunk size must be six, +* because the I2C device address will then occupy two bytes when writing. +* +* Data in single master mode is transferred as follows: +* a0 a1 a2 a3

+* d0 d1 [d2 d3]

+* .. +* or +* .. +* a0 a1 a2 a3

+* ---

+* +* In multi-master mode, the data must immediately follow the address (an I2C +* stop resets the internal address), and hence the minimum chunk size is +* 1 + 4 (register address) + 2 (data to send) = 7 bytes (8 if +* 10-bit I2C device addresses are used). +* +* The 7-bit or 10-bit i2c address parameters is a runtime parameter. +* The other parameters can be limited via compile time switches. +* +*------------------------------------------------------------------------------- +* +* Minimum chunk size table (in bytes): +* +* +----------------+----------------+ +* | 7b i2c addr | 10b i2c addr | +* +----------------+----------------+ +* | single | multi | single | multi | +* ------+--------+-------+--------+-------+ +* short | 3 | 5 | 4 | 6 | +* long | 5 | 7 | 6 | 8 | +* ------+--------+-------+--------+-------+ +* +*/ + +/* set default */ +#if !defined( DRXDAP_MAX_WCHUNKSIZE) +#define DRXDAP_MAX_WCHUNKSIZE 254 +#endif + +/* check */ +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 3 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#endif +#else +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 7 +#endif +#endif + +#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN +#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) ) +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#else +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#endif +#endif + +/* set default */ +#if !defined( DRXDAP_MAX_RCHUNKSIZE) +#define DRXDAP_MAX_RCHUNKSIZE 254 +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE < 2 +#error DRXDAP_MAX_RCHUNKSIZE must be at least 2 +*; /* illegal statement to force compiler error */ +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE & 1 +#error DRXDAP_MAX_RCHUNKSIZE must be even +*; /* illegal statement to force compiler error */ +#endif + +/*-------- Public API functions ----------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +extern DRXAccessFunc_t drxDapFASIFunct_g; + +#define DRXDAP_FASI_RMW 0x10000000 +#define DRXDAP_FASI_BROADCAST 0x20000000 +#define DRXDAP_FASI_CLEARCRC 0x80000000 +#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000 +#define DRXDAP_FASI_MULTI_MASTER 0x40000000 +#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ +#define DRXDAP_FASI_MODEFLAGS 0xC0000000 +#define DRXDAP_FASI_FLAGS 0xF0000000 + +#define DRXDAP_FASI_ADDR2BLOCK( addr ) (((addr)>>22)&0x3F) +#define DRXDAP_FASI_ADDR2BANK( addr ) (((addr)>>16)&0x3F) +#define DRXDAP_FASI_ADDR2OFFSET( addr ) ((addr)&0x7FFF) + +#define DRXDAP_FASI_SHORT_FORMAT( addr ) (((addr)& 0xFC30FF80)==0) +#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0) +#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0) + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.c b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c new file mode 100644 index 000000000000..7b0284195948 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.c @@ -0,0 +1,1600 @@ +/** +* \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $ +* +* \brief Generic DRX functionality, DRX driver core. +* +* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/*------------------------------------------------------------------------------ +INCLUDE FILES +------------------------------------------------------------------------------*/ +#include "drx_driver.h" +#include "bsp_host.h" + +#define VERSION_FIXED 0 +#if VERSION_FIXED +#define VERSION_MAJOR 0 +#define VERSION_MINOR 0 +#define VERSION_PATCH 0 +#else +#include "drx_driver_version.h" +#endif + +/*------------------------------------------------------------------------------ +DEFINES +------------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*=== MICROCODE RELATED DEFINES ==============================================*/ +/*============================================================================*/ + +/** \brief Magic word for checking correct Endianess of microcode data. */ +#ifndef DRX_UCODE_MAGIC_WORD +#define DRX_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#endif + +/** \brief CRC flag in ucode header, flags field. */ +#ifndef DRX_UCODE_CRC_FLAG +#define DRX_UCODE_CRC_FLAG (0x0001) +#endif + +/** \brief Compression flag in ucode header, flags field. */ +#ifndef DRX_UCODE_COMPRESSION_FLAG +#define DRX_UCODE_COMPRESSION_FLAG (0x0002) +#endif + +/** \brief Maximum size of buffer used to verify the microcode. + Must be an even number. */ +#ifndef DRX_UCODE_MAX_BUF_SIZE +#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) +#endif +#if DRX_UCODE_MAX_BUF_SIZE & 1 +#error DRX_UCODE_MAX_BUF_SIZE must be an even number +#endif + +/*============================================================================*/ +/*=== CHANNEL SCAN RELATED DEFINES ===========================================*/ +/*============================================================================*/ + +/** +* \brief Maximum progress indication. +* +* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. +* +*/ +#ifndef DRX_SCAN_MAX_PROGRESS +#define DRX_SCAN_MAX_PROGRESS 1000 +#endif + +/*============================================================================*/ +/*=== MACROS =================================================================*/ +/*============================================================================*/ + +#define DRX_ISPOWERDOWNMODE( mode ) ( ( mode == DRX_POWER_MODE_9 ) || \ + ( mode == DRX_POWER_MODE_10 ) || \ + ( mode == DRX_POWER_MODE_11 ) || \ + ( mode == DRX_POWER_MODE_12 ) || \ + ( mode == DRX_POWER_MODE_13 ) || \ + ( mode == DRX_POWER_MODE_14 ) || \ + ( mode == DRX_POWER_MODE_15 ) || \ + ( mode == DRX_POWER_MODE_16 ) || \ + ( mode == DRX_POWER_DOWN ) ) + +/*------------------------------------------------------------------------------ +GLOBAL VARIABLES +------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +STRUCTURES +------------------------------------------------------------------------------*/ +/** \brief Structure of the microcode block headers */ +typedef struct { + u32_t addr; /**< Destination address of the data in this block */ + u16_t size; /**< Size of the block data following this header counted in + 16 bits words */ + u16_t flags; /**< Flags for this data block: + - bit[0]= CRC on/off + - bit[1]= compression on/off + - bit[15..2]=reserved */ + u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is + set. */ +} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; + +/*------------------------------------------------------------------------------ +FUNCTIONS +------------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== Channel Scan Functions ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +#ifndef DRX_EXCLUDE_SCAN + +/* Prototype of default scanning function */ +static DRXStatus_t +ScanFunctionDefault( void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ); + +/** +* \brief Get pointer to scanning function. +* \param demod: Pointer to demodulator instance. +* \return DRXScanFunc_t. +*/ +static DRXScanFunc_t +GetScanFunction( pDRXDemodInstance_t demod ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL); + + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + scanFunc = commonAttr->scanFunction; + + if ( scanFunc != NULL ) + { + /* return device-specific scan function if it's not NULL */ + return scanFunc; + } + /* otherwise return default scan function in core driver */ + return &ScanFunctionDefault; +} + +/** +* \brief Get Context pointer. +* \param demod: Pointer to demodulator instance. +* \param scanContext: Context Pointer. +* \return DRXScanFunc_t. +*/ +void *GetScanContext( pDRXDemodInstance_t demod, + void *scanContext) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + + /* get scan function from common attributes */ + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + scanContext = commonAttr->scanContext; + + if ( scanContext == NULL ) + { + scanContext = (void *) demod; + } + + return scanContext; +} + +/** +* \brief Wait for lock while scanning. +* \param demod: Pointer to demodulator instance. +* \param lockStat: Pointer to bool indicating if end result is lock or not. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Success +* \retval DRX_STS_ERROR: I2C failure or bsp function failure. +* +* Wait until timeout, desired lock or NEVER_LOCK. +* Assume: +* - lock function returns : at least DRX_NOT_LOCKED and a lock state +* higher than DRX_NOT_LOCKED. +* - BSP has a clock function to retrieve a millisecond ticker value. +* - BSP has a sleep function to enable sleep of n millisecond. +* +* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted. +* +*/ +static DRXStatus_t +ScanWaitForLock( pDRXDemodInstance_t demod, + pBool_t isLocked ) +{ + Bool_t doneWaiting = FALSE; + DRXLockStatus_t lockState = DRX_NOT_LOCKED; + DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED; + u32_t timeoutValue = 0; + u32_t startTimeLockStage = 0; + u32_t currentTime = 0; + u32_t timerValue = 0; + + *isLocked = FALSE; + timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout; + desiredLockState = demod->myCommonAttr->scanDesiredLock; + startTimeLockStage = DRXBSP_HST_Clock(); + + /* Start polling loop, checking for lock & timeout */ + while ( doneWaiting == FALSE ) + { + + if ( DRX_Ctrl( demod, DRX_CTRL_LOCK_STATUS, &lockState ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + currentTime = DRXBSP_HST_Clock(); + + timerValue = currentTime - startTimeLockStage; + if ( lockState >= desiredLockState ) + { + *isLocked = TRUE; + doneWaiting = TRUE; + } /* if ( lockState >= desiredLockState ) .. */ + else if ( lockState == DRX_NEVER_LOCK ) + { + doneWaiting = TRUE; + } /* if ( lockState == DRX_NEVER_LOCK ) .. */ + else if ( timerValue > timeoutValue ) + { + /* lockState == DRX_NOT_LOCKED and timeout */ + doneWaiting = TRUE; + } + else + { + if ( DRXBSP_HST_Sleep( 10 ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + } /* if ( timerValue > timeoutValue ) .. */ + + } /* while */ + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Determine next frequency to scan. +* \param demod: Pointer to demodulator instance. +* \param skip : Minimum frequency step to take. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Succes. +* \retval DRX_STS_INVALID_ARG: Invalid frequency plan. +* +* Helper function for CtrlScanNext() function. +* Compute next frequency & index in frequency plan. +* Check if scan is ready. +* +*/ +static DRXStatus_t +ScanPrepareNextScan ( pDRXDemodInstance_t demod, + DRXFrequency_t skip ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + u16_t tableIndex = 0; + u16_t frequencyPlanSize = 0; + pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL); + DRXFrequency_t nextFrequency = 0; + DRXFrequency_t tunerMinFrequency = 0; + DRXFrequency_t tunerMaxFrequency = 0; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + tableIndex = commonAttr->scanFreqPlanIndex; + frequencyPlan = commonAttr->scanParam->frequencyPlan; + nextFrequency = commonAttr->scanNextFrequency; + tunerMinFrequency = commonAttr->tunerMinFreqRF; + tunerMaxFrequency = commonAttr->tunerMaxFreqRF; + + do + { + /* Search next frequency to scan */ + + /* always take at least one step */ + (commonAttr->scanChannelsScanned) ++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + + /* and then as many steps necessary to exceed 'skip' + without exceeding end of the band */ + while ( ( skip > 0 ) && + ( nextFrequency <= frequencyPlan[tableIndex].last ) ) + { + (commonAttr->scanChannelsScanned) ++; + nextFrequency += frequencyPlan[tableIndex].step; + skip -= frequencyPlan[tableIndex].step; + } + /* reset skip, in case we move to the next band later */ + skip = 0; + + if ( nextFrequency > frequencyPlan[tableIndex].last ) + { + /* reached end of this band */ + tableIndex++; + frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize; + if ( tableIndex >= frequencyPlanSize ) + { + /* reached end of frequency plan */ + commonAttr->scanReady = TRUE; + } + else + { + nextFrequency = frequencyPlan[tableIndex].first; + } + } + if ( nextFrequency > (tunerMaxFrequency) ) + { + /* reached end of tuner range */ + commonAttr->scanReady = TRUE; + } + } while( ( nextFrequency < tunerMinFrequency ) && + ( commonAttr->scanReady == FALSE ) ); + + /* Store new values */ + commonAttr->scanFreqPlanIndex = tableIndex; + commonAttr->scanNextFrequency = nextFrequency; + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Default DTV scanning function. +* +* \param demod: Pointer to demodulator instance. +* \param scanCommand: Scanning command: INIT, NEXT or STOP. +* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO +* \param getNextChannel: Return TRUE if next frequency is desired at next call +* +* \return DRXStatus_t. +* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* to retrieve channel parameters. +* \retval DRX_STS_BUSY: Channel not found (yet). +* \retval DRX_STS_ERROR: Something went wrong. +* +* scanChannel and getNextChannel will be NULL for INIT and STOP. +*/ +static DRXStatus_t +ScanFunctionDefault ( void *scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ) +{ + pDRXDemodInstance_t demod = NULL; + DRXStatus_t status = DRX_STS_ERROR; + Bool_t isLocked = FALSE; + + demod = (pDRXDemodInstance_t) scanContext; + + if ( scanCommand != DRX_SCAN_COMMAND_NEXT ) + { + /* just return OK if not doing "scan next" */ + return DRX_STS_OK; + } + + *getNextChannel = FALSE; + + status = DRX_Ctrl ( demod, DRX_CTRL_SET_CHANNEL, scanChannel ); + if ( status != DRX_STS_OK ) + { + return (status); + } + + status = ScanWaitForLock ( demod, &isLocked ); + if ( status != DRX_STS_OK ) + { + return status; + } + + /* done with this channel, move to next one */ + *getNextChannel = TRUE; + + if ( isLocked == FALSE ) + { + /* no channel found */ + return DRX_STS_BUSY; + } + /* channel found */ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Initialize for channel scan. +* \param demod: Pointer to demodulator instance. +* \param scanParam: Pointer to scan parameters. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Initialized for scan. +* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner +* range. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +* This function should be called before starting a complete channel scan. +* It will prepare everything for a complete channel scan. +* After calling this function the DRX_CTRL_SCAN_NEXT control function can be +* used to perform the actual scanning. Scanning will start at the first +* center frequency of the frequency plan that is within the tuner range. +* +*/ +static DRXStatus_t +CtrlScanInit( pDRXDemodInstance_t demod, + pDRXScanParam_t scanParam ) +{ + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + DRXFrequency_t maxTunerFreq = 0; + DRXFrequency_t minTunerFreq = 0; + u16_t nrChannelsInPlan = 0; + u16_t i = 0; + void *scanContext = NULL; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + commonAttr->scanActive = TRUE; + + /* invalidate a previous SCAN_INIT */ + commonAttr->scanParam = (pDRXScanParam_t)(NULL); + commonAttr->scanNextFrequency = 0; + + /* Check parameters */ + if ( ( ( demod->myTuner == NULL ) && + ( scanParam->numTries !=1) ) || + + ( scanParam == NULL) || + ( scanParam->numTries == 0) || + ( scanParam->frequencyPlan == NULL) || + ( scanParam->frequencyPlanSize == 0 ) + ) + { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check frequency plan contents */ + maxTunerFreq = commonAttr->tunerMaxFreqRF; + minTunerFreq = commonAttr->tunerMinFreqRF; + for( i = 0; i < (scanParam->frequencyPlanSize); i++ ) + { + DRXFrequency_t width = 0; + DRXFrequency_t step = scanParam->frequencyPlan[i].step; + DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first; + DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last; + DRXFrequency_t minFreq = 0; + DRXFrequency_t maxFreq = 0; + + if ( step <= 0 ) + { + /* Step must be positive and non-zero */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + if ( firstFreq > lastFreq ) + { + /* First center frequency is higher than last center frequency */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + width = lastFreq - firstFreq; + + if ( ( width % step ) != 0 ) + { + /* Difference between last and first center frequency is not + an integer number of steps */ + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + /* Check if frequency plan entry intersects with tuner range */ + if ( lastFreq >= minTunerFreq ) + { + if ( firstFreq <= maxTunerFreq ) + { + if ( firstFreq >= minTunerFreq ) + { + minFreq = firstFreq; + } + else + { + DRXFrequency_t n = 0; + + n = ( minTunerFreq - firstFreq ) / step; + if ( ( ( minTunerFreq - firstFreq ) % step ) != 0 ) + { + n++; + } + minFreq = firstFreq + n*step; + } + + if ( lastFreq <= maxTunerFreq ) + { + maxFreq = lastFreq; + } + else + { + DRXFrequency_t n=0; + + n=( lastFreq - maxTunerFreq )/step; + if ( (( lastFreq - maxTunerFreq )%step) !=0 ) + { + n++; + } + maxFreq = lastFreq - n*step; + } + } + } + + /* Keep track of total number of channels within tuner range + in this frequency plan. */ + if ( (minFreq !=0 ) && ( maxFreq != 0 ) ) + { + nrChannelsInPlan += (u16_t)( ( ( maxFreq-minFreq ) / step ) +1 ); + + /* Determine first frequency (within tuner range) to scan */ + if ( commonAttr->scanNextFrequency == 0 ) + { + commonAttr->scanNextFrequency = minFreq; + commonAttr->scanFreqPlanIndex = i; + } + } + + }/* for ( ... ) */ + + if ( nrChannelsInPlan == 0 ) + { + /* Tuner range and frequency plan ranges do not overlap */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + /* Store parameters */ + commonAttr->scanReady = FALSE; + commonAttr->scanMaxChannels = nrChannelsInPlan; + commonAttr->scanChannelsScanned = 0; + commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */ + + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL ); + + commonAttr->scanActive = FALSE; + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Stop scanning. +* \param demod: Pointer to demodulator instance. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Scan stopped. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +*/ +static DRXStatus_t +CtrlScanStop( pDRXDemodInstance_t demod ) +{ + DRXStatus_t status = DRX_STS_ERROR; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL); + void *scanContext = NULL; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + commonAttr->scanActive = TRUE; + + if ( ( commonAttr->scanParam == NULL ) || + ( commonAttr->scanMaxChannels == 0 ) ) + { + /* Scan was not running, just return OK */ + commonAttr->scanActive = FALSE; + return DRX_STS_OK; + } + + /* Call default or device-specific scanning stop function */ + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL ); + + /* All done, invalidate scan-init */ + commonAttr->scanParam = NULL; + commonAttr->scanMaxChannels = 0; + commonAttr->scanActive = FALSE; + + return status; +} + +/*============================================================================*/ + +/** +* \brief Scan for next channel. +* \param demod: Pointer to demodulator instance. +* \param scanProgress: Pointer to scan progress. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used +* to retrieve channel parameters. +* \retval DRX_STS_BUSY: Tried part of the channels, as specified in +* numTries field of scan parameters. At least one +* more call to DRX_CTRL_SCAN_NEXT is needed to +* complete scanning. +* \retval DRX_STS_READY: Reached end of scan range. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL. +* +* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan. +* +*/ +static DRXStatus_t +CtrlScanNext ( pDRXDemodInstance_t demod, + pu16_t scanProgress ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pBool_t scanReady = (pBool_t)(NULL); + u16_t maxProgress = DRX_SCAN_MAX_PROGRESS; + u32_t numTries = 0; + u32_t i = 0; + + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + + /* Check scan parameters */ + if ( scanProgress == NULL ) + { + commonAttr->scanActive = FALSE; + return DRX_STS_INVALID_ARG; + } + + *scanProgress = 0; + commonAttr->scanActive = TRUE; + if ( ( commonAttr->scanParam == NULL) || + ( commonAttr->scanMaxChannels == 0 ) ) + { + /* CtrlScanInit() was not called succesfully before CtrlScanNext() */ + commonAttr->scanActive = FALSE; + return DRX_STS_ERROR; + } + + *scanProgress = (u16_t)( ( ( commonAttr->scanChannelsScanned)* + ( (u32_t)(maxProgress) ) ) / + ( commonAttr->scanMaxChannels ) ); + + /* Scan */ + numTries = commonAttr->scanParam->numTries; + scanReady = &(commonAttr->scanReady); + + for ( i = 0; ( (i < numTries) && ( (*scanReady) == FALSE) ); i++) + { + DRXChannel_t scanChannel = { 0 }; + DRXStatus_t status = DRX_STS_ERROR; + pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL); + Bool_t nextChannel = FALSE; + void *scanContext = NULL; + + /* Next channel to scan */ + freqPlan = + &(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]); + scanChannel.frequency = commonAttr->scanNextFrequency; + scanChannel.bandwidth = freqPlan->bandwidth; + scanChannel.mirror = DRX_MIRROR_AUTO; + scanChannel.constellation = DRX_CONSTELLATION_AUTO; + scanChannel.hierarchy = DRX_HIERARCHY_AUTO; + scanChannel.priority = DRX_PRIORITY_HIGH; + scanChannel.coderate = DRX_CODERATE_AUTO; + scanChannel.guard = DRX_GUARD_AUTO; + scanChannel.fftmode = DRX_FFTMODE_AUTO; + scanChannel.classification = DRX_CLASSIFICATION_AUTO; + scanChannel.symbolrate = 0; + scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO; + scanChannel.ldpc = DRX_LDPC_AUTO; + scanChannel.carrier = DRX_CARRIER_AUTO; + scanChannel.framemode = DRX_FRAMEMODE_AUTO; + scanChannel.pilot = DRX_PILOT_AUTO; + + /* Call default or device-specific scanning function */ + scanContext = GetScanContext(demod, scanContext); + + status = (*(GetScanFunction( demod ))) + ( scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel ); + + /* Proceed to next channel if requested */ + if ( nextChannel == TRUE ) + { + DRXStatus_t nextStatus = DRX_STS_ERROR; + DRXFrequency_t skip = 0; + + if ( status == DRX_STS_OK ) + { + /* a channel was found, so skip some frequency steps */ + skip = commonAttr->scanParam->skip; + } + nextStatus = ScanPrepareNextScan( demod, skip ); + + /* keep track of progress */ + *scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)* + ((u32_t)(maxProgress)))/ + (commonAttr->scanMaxChannels)); + + if ( nextStatus != DRX_STS_OK ) + { + commonAttr->scanActive = FALSE; + return (nextStatus); + } + } + if ( status != DRX_STS_BUSY ) + { + /* channel found or error */ + commonAttr->scanActive = FALSE; + return status; + } + } /* for ( i = 0; i < ( ... numTries); i++) */ + + if ( (*scanReady) == TRUE ) + { + /* End of scan reached: call stop-scan, ignore any error */ + CtrlScanStop( demod ); + commonAttr->scanActive = FALSE; + return (DRX_STS_READY); + } + + commonAttr->scanActive = FALSE; + + return DRX_STS_BUSY; +} + +#endif /* #ifndef DRX_EXCLUDE_SCAN */ + +/*============================================================================*/ + +/** +* \brief Program tuner. +* \param demod: Pointer to demodulator instance. +* \param tunerChannel: Pointer to tuning parameters. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Tuner programmed successfully. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +* tunerChannel passes parameters to program the tuner, +* but also returns the actual RF and IF frequency from the tuner. +* +*/ +static DRXStatus_t +CtrlProgramTuner( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + DRXStatus_t status = DRX_STS_ERROR; + DRXFrequency_t ifFrequency = 0; + Bool_t tunerSlowMode = FALSE; + + /* can't tune without a tuner */ + if ( demod->myTuner == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + + /* select analog or digital tuner mode based on current standard */ + if ( DRX_Ctrl( demod, DRX_CTRL_GET_STANDARD, &standard ) != DRX_STS_OK ) + { + return DRX_STS_ERROR; + } + + if ( DRX_ISATVSTD( standard ) ) + { + tunerMode |= TUNER_MODE_ANALOG; + } + else /* note: also for unknown standard */ + { + tunerMode |= TUNER_MODE_DIGITAL; + } + + /* select tuner bandwidth */ + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_6MHZ: + tunerMode |= TUNER_MODE_6MHZ; + break; + case DRX_BANDWIDTH_7MHZ: + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_8MHZ: + tunerMode |= TUNER_MODE_8MHZ; + break; + default: /* note: also for unknown bandwidth */ + return DRX_STS_INVALID_ARG; + } + + DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode); + + /* select fast (switch) or slow (lock) tuner mode */ + if ( tunerSlowMode ) + { + tunerMode |= TUNER_MODE_LOCK; + } + else + { + tunerMode |= TUNER_MODE_SWITCH; + } + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); + if ( statusBridge != DRX_STS_OK ) + { + return statusBridge; + } + } + + status = DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + channel->frequency ); + + /* attempt restoring bridge before checking status of SetFrequency */ + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + DRXStatus_t statusBridge = DRX_STS_ERROR; + + statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed ); + if ( statusBridge != DRX_STS_OK ) + { + return statusBridge; + } + } + + /* now check status of DRXBSP_TUNER_SetFrequency */ + if ( status != DRX_STS_OK ) + { + return status; + } + + /* get actual RF and IF frequencies from tuner */ + status = DRXBSP_TUNER_GetFrequency( demod->myTuner, + tunerMode, + &(channel->frequency), + &(ifFrequency) ); + if ( status != DRX_STS_OK ) + { + return status; + } + + /* update common attributes with information available from this function; + TODO: check if this is required and safe */ + DRX_SET_INTERMEDIATEFREQ( demod, ifFrequency ); + + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief function to do a register dump. +* \param demod: Pointer to demodulator instance. +* \param registers: Registers to dump. +* \return DRXStatus_t. +* \retval DRX_STS_OK: Dump executed successfully. +* \retval DRX_STS_ERROR: Something went wrong. +* \retval DRX_STS_INVALID_ARG: Wrong parameters. +* +*/ +DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod, + pDRXRegDump_t registers ) +{ + u16_t i = 0; + + if ( registers == NULL ) + { + /* registers not supplied */ + return DRX_STS_INVALID_ARG; + } + + /* start dumping registers */ + while ( registers[i].address != 0 ) + { + DRXStatus_t status = DRX_STS_ERROR; + u16_t value = 0; + u32_t data = 0; + + status = demod->myAccessFunct->readReg16Func( + demod->myI2CDevAddr, registers[i].address, &value, 0 ); + + data = (u32_t)value; + + if ( status != DRX_STS_OK ) + { + /* no breakouts; + depending on device ID, some HW blocks might not be available */ + data |= ( (u32_t)status ) << 16; + } + registers[i].data = data; + i++; + } + + /* all done, all OK (any errors are saved inside data) */ + return DRX_STS_OK; +} + +/*============================================================================*/ +/*============================================================================*/ +/*===Microcode related functions==============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \brief Read a 16 bits word, expects big endian data. +* \param addr: Pointer to memory from which to read the 16 bits word. +* \return u16_t The data read. +* +* This function takes care of the possible difference in endianness between the +* host and the data contained in the microcode image file. +* +*/ +static u16_t +UCodeRead16( pu8_t addr) +{ + /* Works fo any host processor */ + + u16_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |=((u16_t)addr[1]); + + return word; +} + +/*============================================================================*/ + +/** +* \brief Read a 32 bits word, expects big endian data. +* \param addr: Pointer to memory from which to read the 32 bits word. +* \return u32_t The data read. +* +* This function takes care of the possible difference in endianness between the +* host and the data contained in the microcode image file. +* +*/ +static u32_t +UCodeRead32( pu8_t addr) +{ + /* Works fo any host processor */ + + u32_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |= ((u16_t)addr[1]); + word <<= 8; + word |= ((u16_t)addr[2]); + word <<= 8; + word |= ((u16_t)addr[3]); + + return word ; +} + +/*============================================================================*/ + +/** +* \brief Compute CRC of block of microcode data. +* \param blockData: Pointer to microcode data. +* \param nrWords: Size of microcode block (number of 16 bits words). +* \return u16_t The computed CRC residu. +*/ +static u16_t +UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +{ + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord = 0; + u32_t carry = 0; + + while ( i < nrWords ) + { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) + { + CRCWord <<= 1; + if (carry != 0) + { + CRCWord ^= 0x80050000UL; + } + carry = CRCWord & 0x80000000UL; + } + i++; + blockData+=(sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); +} + +/*============================================================================*/ + +/** +* \brief Handle microcode upload or verify. +* \param devAddr: Address of device. +* \param mcInfo: Pointer to information about microcode data. +* \param action: Either UCODE_UPLOAD or UCODE_VERIFY +* \return DRXStatus_t. +* \retval DRX_STS_OK: +* - In case of UCODE_UPLOAD: code is successfully uploaded. +* - In case of UCODE_VERIFY: image on device is equal to +* image provided to this control function. +* \retval DRX_STS_ERROR: +* - In case of UCODE_UPLOAD: I2C error. +* - In case of UCODE_VERIFY: I2C error or image on device +* is not equal to image provided to this control function. +* \retval DRX_STS_INVALID_ARG: +* - Invalid arguments. +* - Provided image is corrupt +*/ +static DRXStatus_t +CtrlUCode( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action) +{ + DRXStatus_t rc; + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + + /* Check arguments */ + if ( ( mcInfo == NULL ) || + ( mcInfo->mcData == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + mcData = mcInfo->mcData; + + /* Check data */ + mcMagicWord = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + mcNrOfBlks = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + + if ( ( mcMagicWord != DRX_UCODE_MAGIC_WORD ) || + ( mcNrOfBlks == 0 ) ) + { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } + + /* Scan microcode blocks first for version info if uploading */ + if (action == UCODE_UPLOAD) + { + /* Clear version block */ + DRX_SET_MCVERTYPE (demod, 0); + DRX_SET_MCDEV (demod, 0); + DRX_SET_MCVERSION (demod, 0); + DRX_SET_MCPATCH (demod, 0); + for (i = 0; i < mcNrOfBlks; i++) + { + DRXUCodeBlockHdr_t blockHdr; + + /* Process block header */ + blockHdr.addr = UCodeRead32( mcData ); + mcData += sizeof(u32_t); + blockHdr.size = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + blockHdr.flags = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + blockHdr.CRC = UCodeRead16( mcData ); + mcData += sizeof(u16_t); + + if (blockHdr.flags & 0x8) + { + /* Aux block. Check type */ + pu8_t auxblk = mcInfo->mcData + blockHdr.addr; + u16_t auxtype = UCodeRead16 (auxblk); + if (DRX_ISMCVERTYPE (auxtype)) + { + DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk)); + auxblk += sizeof (u16_t); + DRX_SET_MCDEV (demod, UCodeRead32 (auxblk)); + auxblk += sizeof (u32_t); + DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk)); + auxblk += sizeof (u32_t); + DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk)); + } + } + + /* Next block */ + mcData += blockHdr.size * sizeof (u16_t); + } + + /* After scanning, validate the microcode. + It is also valid if no validation control exists. + */ + rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL); + if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) + { + return rc; + } + + /* Restore data pointer */ + mcData = mcInfo->mcData + 2 * sizeof( u16_t ); + } + + /* Process microcode blocks */ + for( i = 0 ; i 0x7FFF ) || + ( ( ( blockHdr.flags & DRX_UCODE_CRC_FLAG ) != 0 ) && + ( blockHdr.CRC != UCodeComputeCRC ( mcData, blockHdr.size) ) ) + ) + { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof( u16_t )); + + if ( blockHdr.size != 0 ) + { + /* Perform the desired action */ + switch ( action ) { + /*================================================================*/ + case UCODE_UPLOAD : + { + /* Upload microcode */ + if ( demod->myAccessFunct->writeBlockFunc( + devAddr, + (DRXaddr_t) blockHdr.addr, + mcBlockNrBytes, + mcData, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } /* if */ + }; + break; + + /*================================================================*/ + case UCODE_VERIFY : + { + int result = 0; + u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare=0; + u32_t bytesLeftToCompare=0; + DRXaddr_t currAddr = (DRXaddr_t)0; + pu8_t currPtr =NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while( bytesLeftToCompare != 0 ) + { + if (bytesLeftToCompare > ( (u32_t)DRX_UCODE_MAX_BUF_SIZE) ) + { + bytesToCompare = ( (u32_t)DRX_UCODE_MAX_BUF_SIZE ); + } + else + { + bytesToCompare = bytesLeftToCompare; + } + + if ( demod->myAccessFunct->readBlockFunc( + devAddr, + currAddr, + (u16_t)bytesToCompare, + (pu8_t)mcDataBuffer, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + + result = DRXBSP_HST_Memcmp( currPtr, + mcDataBuffer, + bytesToCompare); + + if ( result != 0 ) + { + return DRX_STS_ERROR; + } + + currAddr += ((DRXaddr_t)(bytesToCompare/2)); + currPtr = &(currPtr[bytesToCompare]); + bytesLeftToCompare -= ((u32_t)bytesToCompare); + } /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */ + }; + break; + + /*================================================================*/ + default: + return DRX_STS_INVALID_ARG; + break; + + } /* switch ( action ) */ + } /* if (blockHdr.size != 0 ) */ + + /* Next block */ + mcData += mcBlockNrBytes; + + } /* for( i = 0 ; imyDemodFunct->ctrlFunc))( + demod, + DRX_CTRL_VERSION, + (void *) &demodVersionList ); + + /* Always fill in the information of the driver SW . */ + drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE; + drxDriverCoreVersion.moduleName = drxDriverCoreModuleName; + drxDriverCoreVersion.vMajor = VERSION_MAJOR; + drxDriverCoreVersion.vMinor = VERSION_MINOR; + drxDriverCoreVersion.vPatch = VERSION_PATCH; + drxDriverCoreVersion.vString = drxDriverCoreVersionText; + + drxDriverCoreVersionList.version = &drxDriverCoreVersion; + drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL); + + if ( ( returnStatus == DRX_STS_OK ) && ( demodVersionList != NULL ) ) + { + /* Append versioninfo from driver to versioninfo from demod */ + /* Return version info in "bottom-up" order. This way, multiple + devices can be handled without using malloc. */ + pDRXVersionList_t currentListElement = demodVersionList; + while ( currentListElement->next != NULL ) + { + currentListElement = currentListElement->next; + } + currentListElement->next = &drxDriverCoreVersionList; + + *versionList = demodVersionList; + } + else + { + /* Just return versioninfo from driver */ + *versionList = &drxDriverCoreVersionList; + } + + return DRX_STS_OK; +} + +/*============================================================================*/ +/*============================================================================*/ +/*== Exported functions ======================================================*/ +/*============================================================================*/ +/*============================================================================*/ + + + +/** +* \brief This function is obsolete. +* \param demods: Don't care, parameter is ignored. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Initialization completed. +* +* This function is obsolete, prototype available for backward compatability. +* +*/ + +DRXStatus_t +DRX_Init( pDRXDemodInstance_t demods[] ) +{ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief This function is obsolete. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Terminated driver successful. +* +* This function is obsolete, prototype available for backward compatability. +* +*/ + +DRXStatus_t +DRX_Term( void ) +{ + return DRX_STS_OK; +} + +/*============================================================================*/ + +/** +* \brief Open a demodulator instance. +* \param demod: A pointer to a demodulator instance. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Opened demod instance with succes. +* \retval DRX_STS_ERROR: Driver not initialized or unable to initialize +* demod. +* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content. +* +*/ + +DRXStatus_t +DRX_Open(pDRXDemodInstance_t demod) +{ + DRXStatus_t status = DRX_STS_OK; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) || + ( demod->myCommonAttr->isOpened == TRUE )) + { + return (DRX_STS_INVALID_ARG); + } + + status = (*(demod->myDemodFunct->openFunc))( demod ); + + if ( status == DRX_STS_OK ) + { + demod->myCommonAttr->isOpened = TRUE; + } + + return status; +} + +/*============================================================================*/ + +/** +* \brief Close device. +* \param demod: A pointer to a demodulator instance. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Closed demod instance with succes. +* \retval DRX_STS_ERROR: Driver not initialized or error during close +* demod. +* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content. +* +* Free resources occupied by device instance. +* Put device into sleep mode. +*/ + +DRXStatus_t +DRX_Close(pDRXDemodInstance_t demod) +{ + DRXStatus_t status = DRX_STS_OK; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) || + ( demod->myCommonAttr->isOpened == FALSE )) + { + return DRX_STS_INVALID_ARG; + } + + status = (*(demod->myDemodFunct->closeFunc))( demod ); + + DRX_SET_ISOPENED (demod, FALSE); + + return status; +} + +/*============================================================================*/ + +/** +* \brief Control the device. +* \param demod: A pointer to a demodulator instance. +* \param ctrl: Reference to desired control function. +* \param ctrlData: Pointer to data structure for control function. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK: Control function completed successfully. +* \retval DRX_STS_ERROR: Driver not initialized or error during +* control demod. +* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid +* content. +* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not +* available. +* +* Data needed or returned by the control function is stored in ctrlData. +* +*/ + +DRXStatus_t +DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData) +{ + DRXStatus_t status = DRX_STS_ERROR; + + if ( ( demod == NULL ) || + ( demod->myDemodFunct == NULL ) || + ( demod->myCommonAttr == NULL ) || + ( demod->myExtAttr == NULL ) || + ( demod->myI2CDevAddr == NULL ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( ( ( demod->myCommonAttr->isOpened == FALSE ) && + ( ctrl != DRX_CTRL_PROBE_DEVICE ) && + ( ctrl != DRX_CTRL_VERSION) ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( ( DRX_ISPOWERDOWNMODE( demod->myCommonAttr->currentPowerMode ) && + ( ctrl != DRX_CTRL_POWER_MODE ) && + ( ctrl != DRX_CTRL_PROBE_DEVICE ) && + ( ctrl != DRX_CTRL_NOP ) && + ( ctrl != DRX_CTRL_VERSION) + ) + ) + { + return DRX_STS_FUNC_NOT_AVAILABLE; + } + + /* Fixed control functions */ + switch ( ctrl ) { + /*======================================================================*/ + case DRX_CTRL_NOP: + /* No operation */ + return DRX_STS_OK; + break; + + /*======================================================================*/ + case DRX_CTRL_VERSION: + return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); + break; + + /*======================================================================*/ + default : + /* Do nothing */ + break; + } + + /* Virtual functions */ + /* First try calling function from derived class */ + status = (*(demod->myDemodFunct->ctrlFunc))( demod, ctrl, ctrlData ); + if (status == DRX_STS_FUNC_NOT_AVAILABLE) + { + /* Now try calling a the base class function */ + switch ( ctrl ) { + /*===================================================================*/ + case DRX_CTRL_LOAD_UCODE: + return CtrlUCode ( demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_UPLOAD ); + break; + + /*===================================================================*/ + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCode ( demod, + (pDRXUCodeInfo_t) ctrlData, + UCODE_VERIFY); + } + break; + +#ifndef DRX_EXCLUDE_SCAN + /*===================================================================*/ + case DRX_CTRL_SCAN_INIT: + { + return CtrlScanInit( demod, (pDRXScanParam_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_SCAN_NEXT: + { + return CtrlScanNext( demod, (pu16_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_SCAN_STOP: + { + return CtrlScanStop( demod ); + } + break; +#endif /* #ifndef DRX_EXCLUDE_SCAN */ + + /*===================================================================*/ + case DRX_CTRL_PROGRAM_TUNER: + { + return CtrlProgramTuner( demod, (pDRXChannel_t) ctrlData ); + } + break; + + /*===================================================================*/ + case DRX_CTRL_DUMP_REGISTERS: + { + return CtrlDumpRegisters( demod, (pDRXRegDump_t) ctrlData ); + } + break; + + /*===================================================================*/ + default : + return DRX_STS_FUNC_NOT_AVAILABLE; + } + } + else + { + return (status); + } + + return DRX_STS_OK; +} + + +/*============================================================================*/ + +/* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h new file mode 100644 index 000000000000..d3bfe0676581 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -0,0 +1,2588 @@ +/** +* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $ +* +* \brief DRX driver API +* +* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXDRIVER_H__ +#define __DRXDRIVER_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ +#include "bsp_types.h" +#include "bsp_i2c.h" +#include "bsp_tuner.h" +#include "bsp_host.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/************** +* +* This section configures the DRX Data Access Protocols (DAPs). +* +**************/ + +/** +* \def DRXDAP_SINGLE_MASTER +* \brief Enable I2C single or I2C multimaster mode on host. +* +* Set to 1 to enable single master mode +* Set to 0 to enable multi master mode +* +* The actual DAP implementation may be restricted to only one of the modes. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the mode defined below. +* +*/ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/** +* \def DRXDAP_MAX_WCHUNKSIZE +* \brief Defines maximum chunksize of an i2c write action by host. +* +* This indicates the maximum size of data the I2C device driver is able to +* write at a time. This includes I2C device address and register addressing. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data +* buffer. Do not undefine or choose too large, unless your system is able to +* handle a stack buffer of that size. +* +*/ +#ifndef DRXDAP_MAX_WCHUNKSIZE +#define DRXDAP_MAX_WCHUNKSIZE 60 +#endif + +/** +* \def DRXDAP_MAX_RCHUNKSIZE +* \brief Defines maximum chunksize of an i2c read action by host. +* +* This indicates the maximum size of data the I2C device driver is able to read +* at a time. Minimum value is 2. Also, the read chunk size must be even. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overides or cannot handle the chunksize defined below. +* +*/ +#ifndef DRXDAP_MAX_RCHUNKSIZE +#define DRXDAP_MAX_RCHUNKSIZE 60 +#endif + +/************** +* +* This section describes drxdriver defines. +* +**************/ + +/** +* \def DRX_UNKNOWN +* \brief Generic UNKNOWN value for DRX enumerated types. +* +* Used to indicate that the parameter value is unknown or not yet initalized. +*/ +#ifndef DRX_UNKNOWN +#define DRX_UNKNOWN (254) +#endif + +/** +* \def DRX_AUTO +* \brief Generic AUTO value for DRX enumerated types. +* +* Used to instruct the driver to automatically determine the value of the +* parameter. +*/ +#ifndef DRX_AUTO +#define DRX_AUTO (255) +#endif + + +/************** +* +* This section describes flag definitions for the device capbilities. +* +**************/ + +/** +* \brief LNA capability flag +* +* Device has a Low Noise Amplifier +* +*/ +#define DRX_CAPABILITY_HAS_LNA (1UL << 0) +/** +* \brief OOB-RX capability flag +* +* Device has OOB-RX +* +*/ +#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) +/** +* \brief ATV capability flag +* +* Device has ATV +* +*/ +#define DRX_CAPABILITY_HAS_ATV (1UL << 2) +/** +* \brief DVB-T capability flag +* +* Device has DVB-T +* +*/ +#define DRX_CAPABILITY_HAS_DVBT (1UL << 3) +/** +* \brief ITU-B capability flag +* +* Device has ITU-B +* +*/ +#define DRX_CAPABILITY_HAS_ITUB (1UL << 4) +/** +* \brief Audio capability flag +* +* Device has Audio +* +*/ +#define DRX_CAPABILITY_HAS_AUD (1UL << 5) +/** +* \brief SAW switch capability flag +* +* Device has SAW switch +* +*/ +#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) +/** +* \brief GPIO1 capability flag +* +* Device has GPIO1 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) +/** +* \brief GPIO2 capability flag +* +* Device has GPIO2 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) +/** +* \brief IRQN capability flag +* +* Device has IRQN +* +*/ +#define DRX_CAPABILITY_HAS_IRQN (1UL << 9) +/** +* \brief 8VSB capability flag +* +* Device has 8VSB +* +*/ +#define DRX_CAPABILITY_HAS_8VSB (1UL << 10) +/** +* \brief SMA-TX capability flag +* +* Device has SMATX +* +*/ +#define DRX_CAPABILITY_HAS_SMATX (1UL << 11) +/** +* \brief SMA-RX capability flag +* +* Device has SMARX +* +*/ +#define DRX_CAPABILITY_HAS_SMARX (1UL << 12) +/** +* \brief ITU-A/C capability flag +* +* Device has ITU-A/C +* +*/ +#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) + +/*------------------------------------------------------------------------- +MACROS +-------------------------------------------------------------------------*/ +/* Macros to stringify the version number */ +#define DRX_VERSIONSTRING( MAJOR, MINOR, PATCH ) \ + DRX_VERSIONSTRING_HELP(MAJOR)"." \ + DRX_VERSIONSTRING_HELP(MINOR)"." \ + DRX_VERSIONSTRING_HELP(PATCH) +#define DRX_VERSIONSTRING_HELP( NUM ) #NUM + +/** +* \brief Macro to create byte array elements from 16 bit integers. +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x->lowbyte(x), highbyte(x) +*/ +#define DRX_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ + ((u8_t)((((u16_t)x)>>8)&0xFF)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S9TOS16(x) ((((u16_t)x)&0x100 )?((s16_t)((u16_t)(x)|0xFF00)):(x)) + +/** +* \brief Macro to sign extend signed 9 bit value to signed 16 bit value +*/ +#define DRX_S24TODRXFREQ(x) ( ( ( (u32_t) x ) & 0x00800000UL ) ? \ + ( (DRXFrequency_t) \ + ( ( (u32_t) x ) | 0xFF000000 ) ) : \ + ( (DRXFrequency_t) x ) ) + +/** +* \brief Macro to convert 16 bit register value to a DRXFrequency_t +*/ +#define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \ + ( (DRXFrequency_t) \ + ( ( (u32_t) x ) | 0xFFFF0000 ) ) : \ + ( (DRXFrequency_t) x ) ) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/** +* \enum DRXStandard_t +* \brief Modulation standards. +*/ +typedef enum { + DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L + with negative modulation */ + DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L + with positive modulation */ + DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */ +} DRXStandard_t, *pDRXStandard_t; + +/** +* \enum DRXStandard_t +* \brief Modulation sub-standards. +*/ +typedef enum { + DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */ +} DRXSubstandard_t, *pDRXSubstandard_t; + +/** +* \enum DRXBandwidth_t +* \brief Channel bandwidth or channel spacing. +*/ +typedef enum { + DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */ +} DRXBandwidth_t, *pDRXBandwidth_t; + +/** +* \enum DRXMirror_t +* \brief Indicate if channel spectrum is mirrored or not. +*/ +typedef enum { + DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /**< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */ +} DRXMirror_t, *pDRXMirror_t; + +/** +* \enum DRXConstellation_t +* \brief Constellation type of the channel. +*/ +typedef enum { + DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */ +} DRXConstellation_t, *pDRXConstellation_t; + +/** +* \enum DRXHierarchy_t +* \brief Hierarchy of the channel. +*/ +typedef enum { + DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */ +} DRXHierarchy_t, *pDRXHierarchy_t; + +/** +* \enum DRXPriority_t +* \brief Channel priority in case of hierarchical transmission. +*/ +typedef enum { + DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ + DRX_PRIORITY_HIGH, /**< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */ +} DRXPriority_t, *pDRXPriority_t; + +/** +* \enum DRXCoderate_t +* \brief Channel priority in case of hierarchical transmission. +*/ +typedef enum { + DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ + DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */ + DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */ +} DRXCoderate_t, *pDRXCoderate_t; + +/** +* \enum DRXGuard_t +* \brief Guard interval of a channel. +*/ +typedef enum { + DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */ +} DRXGuard_t, *pDRXGuard_t; + +/** +* \enum DRXFftmode_t +* \brief FFT mode. +*/ +typedef enum { + DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ + DRX_FFTMODE_4K, /**< 4K FFT mode. */ + DRX_FFTMODE_8K, /**< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */ +} DRXFftmode_t, *pDRXFftmode_t; + +/** +* \enum DRXClassification_t +* \brief Channel classification. +*/ +typedef enum { + DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /**< Static echo. */ + DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */ +} DRXClassification_t, *pDRXClassification_t; + +/** +* /enum DRXInterleaveModes_t +* /brief Interleave modes +*/ +typedef enum { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */ +} DRXInterleaveModes_t, *pDRXInterleaveModes_t; + +/** +* \enum DRXCarrier_t +* \brief Channel Carrier Mode. +*/ +typedef enum { + DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ + DRX_CARRIER_SINGLE, /**< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ +} DRXCarrier_t, *pDRXCarrier_t; + +/** +* \enum DRXFramemode_t +* \brief Channel Frame Mode. +*/ +typedef enum { + DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ + DRX_FRAMEMODE_595, /**< 595 */ + DRX_FRAMEMODE_945, /**< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */ +} DRXFramemode_t, *pDRXFramemode_t; + +/** +* \enum DRXTPSFrame_t +* \brief Frame number in current super-frame. +*/ +typedef enum { + DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ + DRX_TPS_FRAME2, /**< TPS frame 2. */ + DRX_TPS_FRAME3, /**< TPS frame 3. */ + DRX_TPS_FRAME4, /**< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */ +} DRXTPSFrame_t, *pDRXTPSFrame_t; + +/** +* \enum DRXLDPC_t +* \brief TPS LDPC . +*/ +typedef enum { + DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ + DRX_LDPC_0_6, /**< LDPC 0.6 */ + DRX_LDPC_0_8, /**< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ +} DRXLDPC_t, *pDRXLDPC_t; + +/** +* \enum DRXPilotMode_t +* \brief Pilot modes in DTMB. +*/ +typedef enum { + DRX_PILOT_ON = 0, /**< Pilot On */ + DRX_PILOT_OFF, /**< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ +} DRXPilotMode_t, *pDRXPilotMode_t; + + + +/** +* \enum DRXCtrlIndex_t +* \brief Indices of the control functions. +*/ +typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t; + +#ifndef DRX_CTRL_BASE +#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0) +#endif + +#define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */ +#define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */ + +#define DRX_CTRL_LOAD_UCODE ( DRX_CTRL_BASE + 2)/**< Load microcode */ +#define DRX_CTRL_VERIFY_UCODE ( DRX_CTRL_BASE + 3)/**< Verify microcode */ +#define DRX_CTRL_SET_CHANNEL ( DRX_CTRL_BASE + 4)/**< Set channel */ +#define DRX_CTRL_GET_CHANNEL ( DRX_CTRL_BASE + 5)/**< Get channel */ +#define DRX_CTRL_LOCK_STATUS ( DRX_CTRL_BASE + 6)/**< Get lock status */ +#define DRX_CTRL_SIG_QUALITY ( DRX_CTRL_BASE + 7)/**< Get signal quality */ +#define DRX_CTRL_SIG_STRENGTH ( DRX_CTRL_BASE + 8)/**< Get signal strength*/ +#define DRX_CTRL_RF_POWER ( DRX_CTRL_BASE + 9)/**< Get RF power */ +#define DRX_CTRL_CONSTEL ( DRX_CTRL_BASE + 10)/**< Get constel point */ +#define DRX_CTRL_SCAN_INIT ( DRX_CTRL_BASE + 11)/**< Initialize scan */ +#define DRX_CTRL_SCAN_NEXT ( DRX_CTRL_BASE + 12)/**< Scan for next */ +#define DRX_CTRL_SCAN_STOP ( DRX_CTRL_BASE + 13)/**< Stop scan */ +#define DRX_CTRL_TPS_INFO ( DRX_CTRL_BASE + 14)/**< Get TPS info */ +#define DRX_CTRL_SET_CFG ( DRX_CTRL_BASE + 15)/**< Set configuration */ +#define DRX_CTRL_GET_CFG ( DRX_CTRL_BASE + 16)/**< Get configuration */ +#define DRX_CTRL_VERSION ( DRX_CTRL_BASE + 17)/**< Get version info */ +#define DRX_CTRL_I2C_BRIDGE ( DRX_CTRL_BASE + 18)/**< Open/close bridge */ +#define DRX_CTRL_SET_STANDARD ( DRX_CTRL_BASE + 19)/**< Set demod std */ +#define DRX_CTRL_GET_STANDARD ( DRX_CTRL_BASE + 20)/**< Get demod std */ +#define DRX_CTRL_SET_OOB ( DRX_CTRL_BASE + 21)/**< Set OOB param */ +#define DRX_CTRL_GET_OOB ( DRX_CTRL_BASE + 22)/**< Get OOB param */ +#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */ +#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */ +#define DRX_CTRL_AUD_GET_STATUS ( DRX_CTRL_BASE + 25)/**< Read RDS */ +#define DRX_CTRL_AUD_BEEP ( DRX_CTRL_BASE + 26)/**< Read RDS */ +#define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */ +#define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */ + + /* Professional */ +#define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */ +#define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */ +#define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */ +#define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */ +#define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */ + + /* Misc */ +#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */ +#define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */ +#define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */ +#define DRX_CTRL_UIO_READ ( DRX_CTRL_BASE + 36) /**< Read from UIO */ +#define DRX_CTRL_UIO_WRITE ( DRX_CTRL_BASE + 37) /**< Write to UIO */ +#define DRX_CTRL_READ_EVENTS ( DRX_CTRL_BASE + 38) /**< Read events */ +#define DRX_CTRL_HDL_EVENTS ( DRX_CTRL_BASE + 39) /**< Handle events */ +#define DRX_CTRL_POWER_MODE ( DRX_CTRL_BASE + 40) /**< Set power mode */ +#define DRX_CTRL_LOAD_FILTER ( DRX_CTRL_BASE + 41) /**< Load chan. filter */ +#define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */ +#define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */ + +#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */ + +/** +* \enum DRXUCodeAction_t +* \brief Used to indicate if firmware has to be uploaded or verified. +*/ + +typedef enum { + UCODE_UPLOAD, /**< Upload the microcode image to device */ + UCODE_VERIFY /**< Compare microcode image with code on device */ +} DRXUCodeAction_t, *pDRXUCodeAction_t; + + +/** +* \enum DRXLockStatus_t +* \brief Used to reflect current lock status of demodulator. +* +* The generic lock states have device dependent semantics. +*/ +typedef enum{ + DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */ + DRX_NOT_LOCKED, /**< Device has no lock at all */ + DRX_LOCK_STATE_1, /**< Generic lock state */ + DRX_LOCK_STATE_2, /**< Generic lock state */ + DRX_LOCK_STATE_3, /**< Generic lock state */ + DRX_LOCK_STATE_4, /**< Generic lock state */ + DRX_LOCK_STATE_5, /**< Generic lock state */ + DRX_LOCK_STATE_6, /**< Generic lock state */ + DRX_LOCK_STATE_7, /**< Generic lock state */ + DRX_LOCK_STATE_8, /**< Generic lock state */ + DRX_LOCK_STATE_9, /**< Generic lock state */ + DRX_LOCKED /**< Device is in lock */ +} DRXLockStatus_t, *pDRXLockStatus_t; + +/** +* \enum DRXUIO_t +* \brief Used to address a User IO (UIO). +*/ +typedef enum{ + DRX_UIO1 , + DRX_UIO2 , + DRX_UIO3 , + DRX_UIO4 , + DRX_UIO5 , + DRX_UIO6 , + DRX_UIO7 , + DRX_UIO8 , + DRX_UIO9 , + DRX_UIO10 , + DRX_UIO11 , + DRX_UIO12 , + DRX_UIO13 , + DRX_UIO14 , + DRX_UIO15 , + DRX_UIO16 , + DRX_UIO17 , + DRX_UIO18 , + DRX_UIO19 , + DRX_UIO20 , + DRX_UIO21 , + DRX_UIO22 , + DRX_UIO23 , + DRX_UIO24 , + DRX_UIO25 , + DRX_UIO26 , + DRX_UIO27 , + DRX_UIO28 , + DRX_UIO29 , + DRX_UIO30 , + DRX_UIO31 , + DRX_UIO32 , + DRX_UIO_MAX = DRX_UIO32 +} DRXUIO_t, *pDRXUIO_t; + +/** +* \enum DRXUIOMode_t +* \brief Used to configure the modus oprandi of a UIO. +* +* DRX_UIO_MODE_FIRMWARE is an old uio mode. +* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. +* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to +* DRX_UIO_MODE_FIRMWARE0. +*/ +typedef enum{ + DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */ +} DRXUIOMode_t, *pDRXUIOMode_t; + +/** +* \enum DRXOOBDownstreamStandard_t +* \brief Used to select OOB standard. +* +* Based on ANSI 55-1 and 55-2 +*/ +typedef enum { + DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */ +} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t; + + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \enum DRXCfgType_t +* \brief Generic configuration function identifiers. +*/ +typedef u32_t DRXCfgType_t, *pDRXCfgType_t; + +#ifndef DRX_CFG_BASE +#define DRX_CFG_BASE ((DRXCfgType_t)0) +#endif + +#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */ + +#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \struct DRXUCodeInfo_t +* \brief Parameters for microcode upload and verfiy. +* +* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE +*/ +typedef struct { + pu8_t mcData; /**< Pointer to microcode image. */ + u16_t mcSize; /**< Microcode image size. */ +} DRXUCodeInfo_t, *pDRXUCodeInfo_t; + +/** +* \struct DRXMcVersionRec_t +* \brief Microcode version record +* Version numbers are stored in BCD format, as usual: +* o major number = bits 31-20 (first three nibbles of MSW) +* o minor number = bits 19-16 (fourth nibble of MSW) +* o patch number = bits 15-0 (remaining nibbles in LSW) +* +* The device type indicates for which the device is meant. It is based on the +* JTAG ID, using everything except the bond ID and the metal fix. +* +* Special values: +* - mcDevType == 0 => any device allowed +* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version) +* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version +* (mcVersion is the version) +*/ +#define AUX_VER_RECORD 0x8000 + +typedef struct { + u16_t auxType; /* type of aux data - 0x8000 for version record */ + u32_t mcDevType; /* device type, based on JTAG ID */ + u32_t mcVersion; /* version of microcode */ + u32_t mcBaseVersion; /* in case of patch: the original microcode version */ +} DRXMcVersionRec_t, *pDRXMcVersionRec_t; + +/*========================================*/ + +/** +* \struct DRXFilterInfo_t +* \brief Parameters for loading filter coefficients +* +* Used by DRX_CTRL_LOAD_FILTER +*/ +typedef struct { + pu8_t dataRe; /**< pointer to coefficients for RE */ + pu8_t dataIm; /**< pointer to coefficients for IM */ + u16_t sizeRe; /**< size of coefficients for RE */ + u16_t sizeIm; /**< size of coefficients for IM */ +} DRXFilterInfo_t, *pDRXFilterInfo_t; + + + +/*========================================*/ + +/** +* \struct DRXChannel_t +* \brief The set of parameters describing a single channel. +* +* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. +* Only certain fields need to be used for a specfic standard. +* +*/ +typedef struct { + DRXFrequency_t frequency; /**< frequency in kHz */ + DRXBandwidth_t bandwidth; /**< bandwidth */ + DRXMirror_t mirror; /**< mirrored or not on RF */ + DRXConstellation_t constellation; /**< constellation */ + DRXHierarchy_t hierarchy; /**< hierarchy */ + DRXPriority_t priority; /**< priority */ + DRXCoderate_t coderate; /**< coderate */ + DRXGuard_t guard; /**< guard interval */ + DRXFftmode_t fftmode; /**< fftmode */ + DRXClassification_t classification; /**< classification */ + DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */ + DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */ + DRXLDPC_t ldpc; /**< ldpc */ + DRXCarrier_t carrier; /**< carrier */ + DRXFramemode_t framemode; /**< frame mode */ + DRXPilotMode_t pilot; /**< pilot mode */ +} DRXChannel_t, *pDRXChannel_t; + +/*========================================*/ + +/** +* \struct DRXSigQuality_t +* Signal quality metrics. +* +* Used by DRX_CTRL_SIG_QUALITY. +*/ +typedef struct { + u16_t MER; /**< in steps of 0.1 dB */ + u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */ + u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */ + u32_t scaleFactorBER; /**< scale factor for BER */ + u16_t packetError ; /**< number of packet errors */ + u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */ + u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */ + u32_t averIter; /**< in steps of 0.01 */ + u16_t indicator; /**< indicative signal quality low=0..100=high */ +}DRXSigQuality_t, *pDRXSigQuality_t; + + +typedef enum { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t; + +/*========================================*/ + +/** +* \struct DRXComplex_t +* A complex number. +* +* Used by DRX_CTRL_CONSTEL. +*/ +typedef struct { + s16_t im; /**< Imaginary part. */ + s16_t re; /**< Real part. */ +} DRXComplex_t, *pDRXComplex_t; + + +/*========================================*/ + +/** +* \struct DRXFrequencyPlan_t +* Array element of a frequency plan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +typedef struct { + DRXFrequency_t first; /**< First centre frequency in this band */ + DRXFrequency_t last; /**< Last centre frequency in this band */ + DRXFrequency_t step; /**< Stepping frequency in this band */ + DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */ + u16_t chNumber; /**< First channel number in this band, or first + index in chNames */ + char **chNames; /**< Optional list of channel names in this + band */ +} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t; + +/*========================================*/ + +/** +* \struct DRXFrequencyPlanInfo_t +* Array element of a list of frequency plans. +* +* Used by frequency_plan.h +*/ +typedef struct{ + pDRXFrequencyPlan_t freqPlan; + int freqPlanSize; + char *freqPlanName; +}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t; + +/*========================================*/ + +/** +* /struct DRXScanDataQam_t +* QAM specific scanning variables +*/ +typedef struct { + pu32_t symbolrate; /**< list of symbolrates to scan */ + u16_t symbolrateSize; /**< size of symbolrate array */ + pDRXConstellation_t constellation; /**< list of constellations */ + u16_t constellationSize; /**< size of constellation array */ + u16_t ifAgcThreshold; /**< thresholf for IF-AGC based + scanning filter */ +} DRXScanDataQam_t, *pDRXScanDataQam_t; + +/*========================================*/ + +/** +* /struct DRXScanDataAtv_t +* ATV specific scanning variables +*/ +typedef struct { + s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */ +} DRXScanDataAtv_t, *pDRXScanDataAtv_t; + +/*========================================*/ + +/** +* \struct DRXScanParam_t +* Parameters for channel scan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +typedef struct { + pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/ + u16_t frequencyPlanSize; /**< Number of bands */ + u32_t numTries; /**< Max channels tried */ + DRXFrequency_t skip; /**< Minimum frequency step to take + after a channel is found */ + void *extParams; /**< Standard specific params */ +} DRXScanParam_t, *pDRXScanParam_t; + +/*========================================*/ + +/** +* \brief Scan commands. +* Used by scanning algorithms. +*/ +typedef enum { + DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /**< Next scan */ + DRX_SCAN_COMMAND_STOP /**< Stop scanning */ +}DRXScanCommand_t, *pDRXScanCommand_t; + +/*========================================*/ + +/** +* \brief Inner scan function prototype. +*/ +typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext, + DRXScanCommand_t scanCommand, + pDRXChannel_t scanChannel, + pBool_t getNextChannel ); + +/*========================================*/ + +/** +* \struct DRXTPSInfo_t +* TPS information, DVB-T specific. +* +* Used by DRX_CTRL_TPS_INFO. +*/ +typedef struct { + DRXFftmode_t fftmode; /**< Fft mode */ + DRXGuard_t guard; /**< Guard interval */ + DRXConstellation_t constellation; /**< Constellation */ + DRXHierarchy_t hierarchy; /**< Hierarchy */ + DRXCoderate_t highCoderate; /**< High code rate */ + DRXCoderate_t lowCoderate; /**< Low cod rate */ + DRXTPSFrame_t frame; /**< Tps frame */ + u8_t length; /**< Length */ + u16_t cellId; /**< Cell id */ +}DRXTPSInfo_t, *pDRXTPSInfo_t; + +/*========================================*/ + +/** +* \brief Power mode of device. +* +* Used by DRX_CTRL_SET_POWER_MODE. +*/ +typedef enum { + DRX_POWER_UP = 0, /**< Generic , Power Up Mode */ + DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */ + DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */ + + DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */ + DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */ + DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */ +}DRXPowerMode_t, *pDRXPowerMode_t; + +/*========================================*/ + +/** +* \enum DRXModule_t +* \brief Software module identification. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef enum { + DRX_MODULE_DEVICE, + DRX_MODULE_MICROCODE, + DRX_MODULE_DRIVERCORE, + DRX_MODULE_DEVICEDRIVER, + DRX_MODULE_DAP, + DRX_MODULE_BSP_I2C, + DRX_MODULE_BSP_TUNER, + DRX_MODULE_BSP_HOST, + DRX_MODULE_UNKNOWN +} DRXModule_t, *pDRXModule_t; + + +/** +* \enum DRXVersion_t +* \brief Version information of one software module. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef struct { + DRXModule_t moduleType; /**< Type identifier of the module */ + char *moduleName; /**< Name or description of module */ + u16_t vMajor; /**< Major version number */ + u16_t vMinor; /**< Minor version number */ + u16_t vPatch; /**< Patch version number */ + char *vString; /**< Version as text string */ +} DRXVersion_t, *pDRXVersion_t; + +/** +* \enum DRXVersionList_t +* \brief List element of NULL terminated, linked list for version information. +* +* Used by DRX_CTRL_VERSION. +*/ +typedef struct DRXVersionList_s { + pDRXVersion_t version; /**< Version information */ + struct DRXVersionList_s *next; /**< Next list element */ +} DRXVersionList_t, *pDRXVersionList_t; + +/*========================================*/ + +/** +* \brief Parameters needed to confiugure a UIO. +* +* Used by DRX_CTRL_UIO_CFG. +*/ +typedef struct { + DRXUIO_t uio; /**< UIO identifier */ + DRXUIOMode_t mode; /**< UIO operational mode */ +} DRXUIOCfg_t, *pDRXUIOCfg_t; + +/*========================================*/ + +/** +* \brief Parameters needed to read from or write to a UIO. +* +* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. +*/ +typedef struct { + DRXUIO_t uio; /**< UIO identifier */ + Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */ +} DRXUIOData_t, *pDRXUIOData_t; + +/*========================================*/ + +/** +* \brief Parameters needed to configure OOB. +* +* Used by DRX_CTRL_SET_OOB. +*/ +typedef struct { + DRXFrequency_t frequency; /**< Frequency in kHz */ + DRXOOBDownstreamStandard_t standard; /**< OOB standard */ + Bool_t spectrumInverted; /**< If TRUE, then spectrum + is inverted */ +} DRXOOB_t, *pDRXOOB_t; + + +/*========================================*/ + +/** +* \brief Metrics from OOB. +* +* Used by DRX_CTRL_GET_OOB. +*/ +typedef struct { + DRXFrequency_t frequency; /**< Frequency in Khz */ + DRXLockStatus_t lock; /**< Lock status */ + u32_t mer; /**< MER */ + s32_t symbolRateOffset; /**< Symbolrate offset in ppm */ +} DRXOOBStatus_t, *pDRXOOBStatus_t; + + +/*========================================*/ + +/** +* \brief Device dependent configuration data. +* +* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. +* A sort of nested DRX_Ctrl() functionality for device specific controls. +*/ +typedef struct { + DRXCfgType_t cfgType ; /**< Function identifier */ + void* cfgData ; /**< Function data */ +} DRXCfg_t, *pDRXCfg_t; + +/*========================================*/ + +/** +* /struct DRXMpegStartWidth_t +* MStart width [nr MCLK cycles] for serial MPEG output. +*/ + +typedef enum { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 +} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t; + + +/* CTRL CFG MPEG ouput */ +/** +* \struct DRXCfgMPEGOutput_t +* \brief Configuartion parameters for MPEG output control. +* +* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and +* DRX_CTRL_GET_CFG. +*/ + +typedef struct { + Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */ + Bool_t insertRSByte; /**< If TRUE, insert RS byte */ + Bool_t enableParallel; /**< If TRUE, parallel out otherwise + serial */ + Bool_t invertDATA; /**< If TRUE, invert DATA signals */ + Bool_t invertERR; /**< If TRUE, invert ERR signal */ + Bool_t invertSTR; /**< If TRUE, invert STR signals */ + Bool_t invertVAL; /**< If TRUE, invert VAL signals */ + Bool_t invertCLK; /**< If TRUE, invert CLK signals */ + Bool_t staticCLK; /**< If TRUE, static MPEG clockrate + will be used, otherwise clockrate + will adapt to the bitrate of the + TS */ + u32_t bitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */ +} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t; + +/* CTRL CFG SMA */ +/** +* /struct DRXCfgSMAIO_t +* smart antenna i/o. +*/ +typedef enum DRXCfgSMAIO_t { + DRX_SMA_OUTPUT = 0, + DRX_SMA_INPUT +} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t; + +/** +* /struct DRXCfgSMA_t +* Set smart antenna. +*/ +typedef struct { + DRXCfgSMAIO_t io; + u16_t ctrlData; + Bool_t smartAntInverted; +} DRXCfgSMA_t, *pDRXCfgSMA_t; + +/*========================================*/ + +/** +* \struct DRXI2CData_t +* \brief Data for I2C via 2nd or 3rd or etc I2C port. +* +* Used by DRX_CTRL_I2C_READWRITE. +* If portNr is equal to primairy portNr BSPI2C will be used. +* +*/ +typedef struct { + u16_t portNr; /**< I2C port number */ + pI2CDeviceAddr_t wDevAddr; /**< Write device address */ + u16_t wCount; /**< Size of write data in bytes */ + pu8_t wData; /**< Pointer to write data */ + pI2CDeviceAddr_t rDevAddr; /**< Read device address */ + u16_t rCount; /**< Size of data to read in bytes */ + pu8_t rData; /**< Pointer to read buffer */ +} DRXI2CData_t, *pDRXI2CData_t; + +/*========================================*/ + +/** +* \enum DRXAudStandard_t +* \brief Audio standard identifier. +* +* Used by DRX_CTRL_SET_AUD. +*/ +typedef enum { + DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ + DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */ + DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */ + DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */ + DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */ + DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */ + DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */ +} DRXAudStandard_t, *pDRXAudStandard_t; + +/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */ +/** +* \enum DRXAudNICAMStatus_t +* \brief Status of NICAM carrier. +*/ +typedef enum { + DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */ + DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ +} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t; + +/** +* \struct DRXAudStatus_t +* \brief Audio status characteristics. +*/ +typedef struct { + Bool_t stereo; /**< stereo detection */ + Bool_t carrierA; /**< carrier A detected */ + Bool_t carrierB; /**< carrier B detected */ + Bool_t sap; /**< sap / bilingual detection */ + Bool_t rds; /**< RDS data array present */ + DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */ + s8_t fmIdent; /**< FM Identification value */ +} DRXAudStatus_t, *pDRXAudStatus_t; + +/* CTRL_AUD_READ_RDS - DRXRDSdata_t */ + +/** +* \struct DRXRDSdata_t +* \brief Raw RDS data array. +*/ +typedef struct { + Bool_t valid; /**< RDS data validation */ + u16_t data[18]; /**< data from one RDS data array */ +} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t; + +/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */ +/** +* \enum DRXAudAVCDecayTime_t +* \brief Automatic volume control configuration. +*/ +typedef enum { + DRX_AUD_AVC_OFF, /**< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */ +} DRXAudAVCMode_t, *pDRXAudAVCMode_t; + +/** +* /enum DRXAudMaxAVCGain_t +* /brief Automatic volume control max gain in audio baseband. +*/ +typedef enum { + DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ +} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t; + +/** +* /enum DRXAudMaxAVCAtten_t +* /brief Automatic volume control max attenuation in audio baseband. +*/ +typedef enum { + DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */ + DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */ +} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t; +/** +* \struct DRXCfgAudVolume_t +* \brief Audio volume configuration. +*/ +typedef struct { + Bool_t mute; /**< mute overrides volume setting */ + s16_t volume; /**< volume, range -114 to 12 dB */ + DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */ + u16_t avcRefLevel; /**< AVC reference level */ + DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */ + DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */ + s16_t strengthLeft; /**< quasi-peak, left speaker */ + s16_t strengthRight; /**< quasi-peak, right speaker */ +} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t; + +/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */ +/** +* \enum DRXI2SMode_t +* \brief I2S output mode. +*/ +typedef enum { + DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ +} DRXI2SMode_t, *pDRXI2SMode_t; + +/** +* \enum DRXI2SWordLength_t +* \brief Width of I2S data. +*/ +typedef enum { + DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ +} DRXI2SWordLength_t, *pDRXI2SWordLength_t; + +/** +* \enum DRXI2SFormat_t +* \brief Data wordstrobe alignment for I2S. +*/ +typedef enum { + DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */ + DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */ +} DRXI2SFormat_t, *pDRXI2SFormat_t; + +/** +* \enum DRXI2SPolarity_t +* \brief Polarity of I2S data. +*/ +typedef enum { + DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ +} DRXI2SPolarity_t, *pDRXI2SPolarity_t; + + + +/** +* \struct DRXCfgI2SOutput_t +* \brief I2S output configuration. +*/ +typedef struct { + Bool_t outputEnable; /**< I2S output enable */ + u32_t frequency; /**< range from 8000-48000 Hz */ + DRXI2SMode_t mode; /**< I2S mode, master or slave */ + DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */ + DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */ + DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */ +} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t; + + +/* ------------------------------expert interface-----------------------------*/ +/** +* /enum DRXAudFMDeemphasis_t +* setting for FM-Deemphasis in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_FM_DEEMPH_50US, + DRX_AUD_FM_DEEMPH_75US, + DRX_AUD_FM_DEEMPH_OFF +} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t; + +/** +* /enum DRXAudDeviation_t +* setting for deviation mode in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_DEVIATION_NORMAL, + DRX_AUD_DEVIATION_HIGH +} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t; + +/** +* /enum DRXNoCarrierOption_t +* setting for carrier, mute/noise. +* +*/ +typedef enum { + DRX_NO_CARRIER_MUTE, + DRX_NO_CARRIER_NOISE +} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t; + + +/** +* \enum DRXAudAutoSound_t +* \brief Automatic Sound +*/ +typedef enum { + DRX_AUD_AUTO_SOUND_OFF = 0, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF +} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t; + +/** +* \enum DRXAudASSThres_t +* \brief Automatic Sound Select Thresholds +*/ +typedef struct { + u16_t a2; /* A2 Threshold for ASS configuration */ + u16_t btsc; /* BTSC Threshold for ASS configuration */ + u16_t nicam; /* Nicam Threshold for ASS configuration */ +} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t; + +/** +* \struct DRXAudCarrier_t +* \brief Carrier detection related parameters +*/ +typedef struct { + u16_t thres; /* carrier detetcion threshold for primary carrier (A) */ + DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */ + DRXFrequency_t shift; /* DC level of incoming signal (A) */ + DRXFrequency_t dco; /* frequency adjustment (A) */ +} DRXAudCarrier_t, *pDRXCfgAudCarrier_t; + +/** +* \struct DRXCfgAudCarriers_t +* \brief combining carrier A & B to one struct +*/ +typedef struct { + DRXAudCarrier_t a; + DRXAudCarrier_t b; +} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t; + +/** +* /enum DRXAudI2SSrc_t +* Selection of audio source +*/ +typedef enum { + DRX_AUD_SRC_MONO, + DRX_AUD_SRC_STEREO_OR_AB, + DRX_AUD_SRC_STEREO_OR_A, + DRX_AUD_SRC_STEREO_OR_B +} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t; + + +/** +* \enum DRXAudI2SMatrix_t +* \brief Used for selecting I2S output. +*/ +typedef enum { + DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */ + DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */ +} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t; + + +/** +* /enum DRXAudFMMatrix_t +* setting for FM-Matrix in audio demodulator. +* +*/ +typedef enum { + DRX_AUD_FM_MATRIX_NO_MATRIX, + DRX_AUD_FM_MATRIX_GERMAN, + DRX_AUD_FM_MATRIX_KOREAN, + DRX_AUD_FM_MATRIX_SOUND_A, + DRX_AUD_FM_MATRIX_SOUND_B +} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t; + +/** +* \struct DRXAudMatrices_t +* \brief Mixer settings +*/ +typedef struct { + DRXAudI2SSrc_t sourceI2S; + DRXAudI2SMatrix_t matrixI2S; + DRXAudFMMatrix_t matrixFm; +} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t; + +/** +* \enum DRXI2SVidSync_t +* \brief Audio/video synchronization, interacts with I2S mode. +* AUTO_1 and AUTO_2 are for automatic video standard detection with preference +* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) +*/ +typedef enum { + DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */ + DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */ + DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */ + DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */ +} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t; + +/** +* \struct DRXCfgAudPrescale_t +* \brief Prescalers +*/ +typedef struct { + u16_t fmDeviation; + s16_t nicamGain; +} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t; + +/** +* \struct DRXAudBeep_t +* \brief Beep +*/ +typedef struct { + s16_t volume; /* dB */ + u16_t frequency; /* Hz */ + Bool_t mute; +} DRXAudBeep_t, *pDRXAudBeep_t; + + +/** +* \enum DRXAudBtscDetect_t +* \brief BTSC detetcion mode +*/ +typedef enum { + DRX_BTSC_STEREO, + DRX_BTSC_MONO_AND_SAP +} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t; + +/** +* \struct DRXAudData_t +* \brief Audio data structure +*/ +typedef struct +{ + /* audio storage */ + Bool_t audioIsActive; + DRXAudStandard_t audioStandard; + DRXCfgI2SOutput_t i2sdata; + DRXCfgAudVolume_t volume; + DRXCfgAudAutoSound_t autoSound; + DRXCfgAudASSThres_t assThresholds; + DRXCfgAudCarriers_t carriers; + DRXCfgAudMixer_t mixer; + DRXCfgAudDeviation_t deviation; + DRXCfgAudAVSync_t avSync; + DRXCfgAudPrescale_t prescale; + DRXAudFMDeemphasis_t deemph; + DRXAudBtscDetect_t btscDetect; + /* rds */ + u16_t rdsDataCounter; + Bool_t rdsDataPresent; +} DRXAudData_t, *pDRXAudData_t; + + +/** +* \enum DRXQamLockRange_t +* \brief QAM lock range mode +*/ +typedef enum +{ + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED +}DRXQamLockRange_t, *pDRXQamLockRange_t; + +/*============================================================================*/ +/*============================================================================*/ +/*== Data access structures ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* Address on device */ +typedef u32_t DRXaddr_t, *pDRXaddr_t; + +/* Protocol specific flags */ +typedef u32_t DRXflags_t, *pDRXflags_t; + +/* Write block of data to device */ +typedef DRXStatus_t (*DRXWriteBlockFunc_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* data to send */ + DRXflags_t flags); + +/* Read block of data from device */ +typedef DRXStatus_t (*DRXReadBlockFunc_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t datasize, /* size of data in bytes */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); + +/* Write 8-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u8_t data, /* data to send */ + DRXflags_t flags); + +/* Read 8-bits value to device */ +typedef DRXStatus_t (*DRXReadReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu8_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 8-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u8_t wdata, /* data to write */ + pu8_t rdata); /* data to read */ + +/* Write 16-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u16_t data, /* data to send */ + DRXflags_t flags); + +/* Read 16-bits value to device */ +typedef DRXStatus_t (*DRXReadReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu16_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 16-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u16_t wdata, /* data to write */ + pu16_t rdata); /* data to read */ + +/* Write 32-bits value to device */ +typedef DRXStatus_t (*DRXWriteReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + u32_t data, /* data to send */ + DRXflags_t flags); + +/* Read 32-bits value to device */ +typedef DRXStatus_t (*DRXReadReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t addr, /* address of register/memory */ + pu32_t data, /* receive buffer */ + DRXflags_t flags); + +/* Read modify write 32-bits value to device */ +typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) ( + pI2CDeviceAddr_t devAddr, /* address of I2C device */ + DRXaddr_t waddr, /* write address of register */ + DRXaddr_t raddr, /* read address of register */ + u32_t wdata, /* data to write */ + pu32_t rdata); /* data to read */ + +/** +* \struct DRXAccessFunc_t +* \brief Interface to an access protocol. +*/ +typedef struct { + pDRXVersion_t protocolVersion; + DRXWriteBlockFunc_t writeBlockFunc; + DRXReadBlockFunc_t readBlockFunc; + DRXWriteReg8Func_t writeReg8Func; + DRXReadReg8Func_t readReg8Func; + DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func; + DRXWriteReg16Func_t writeReg16Func; + DRXReadReg16Func_t readReg16Func; + DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func; + DRXWriteReg32Func_t writeReg32Func; + DRXReadReg32Func_t readReg32Func; + DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func; +} DRXAccessFunc_t, *pDRXAccessFunc_t; + +/* Register address and data for register dump function */ +typedef struct { + + DRXaddr_t address; + u32_t data; + +} DRXRegDump_t, *pDRXRegDump_t ; + +/*============================================================================*/ +/*============================================================================*/ +/*== Demod instance data structures ==========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \struct DRXCommonAttr_t +* \brief Set of common attributes, shared by all DRX devices. +*/ +typedef struct { + /* Microcode (firmware) attributes */ + pu8_t microcode; /**< Pointer to microcode image. */ + u16_t microcodeSize; /**< Size of microcode image in bytes. */ + Bool_t verifyMicrocode; /**< Use microcode verify or not. */ + DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */ + + /* Clocks and tuner attributes */ + DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/ + DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */ + DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */ + s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */ + Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/ + + /* Initial MPEG output attributes */ + DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */ + + Bool_t isOpened; /**< if TRUE instance is already opened. */ + + /* Channel scan */ + pDRXScanParam_t scanParam; /**< scan parameters */ + u16_t scanFreqPlanIndex; /**< next index in freq plan */ + DRXFrequency_t scanNextFrequency; /**< next freq to scan */ + Bool_t scanReady; /**< scan ready flag */ + u32_t scanMaxChannels; /**< number of channels in freqplan */ + u32_t scanChannelsScanned; /**< number of channels scanned */ + /* Channel scan - inner loop: demod related */ + DRXScanFunc_t scanFunction; /**< function to check channel */ + /* Channel scan - inner loop: SYSObj related */ + void* scanContext; /**< Context Pointer of SYSObj */ + /* Channel scan - parameters for default DTV scan function in core driver */ + u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */ + DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */ + /* scanActive can be used by SetChannel to decide how to program the tuner, + fast or slow (but stable). Usually fast during scan. */ + Bool_t scanActive; /**< TRUE when scan routines are active */ + + /* Power management */ + DRXPowerMode_t currentPowerMode; /**< current power management mode */ + + /* Tuner */ + u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */ + DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */ + DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */ + Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */ + Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */ + Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */ + + DRXChannel_t currentChannel; /**< current channel parameters */ + DRXStandard_t currentStandard; /**< current standard selection */ + DRXStandard_t prevStandard; /**< previous standard selection */ + DRXStandard_t diCacheStandard; /**< standard in DI cache if available */ + Bool_t useBootloader; /**< use bootloader in open */ + u32_t capabilities; /**< capabilities flags */ + u32_t productId; /**< product ID inc. metal fix number */ + +} DRXCommonAttr_t, *pDRXCommonAttr_t; + + +/* +* Generic functions for DRX devices. +*/ +typedef struct DRXDemodInstance_s *pDRXDemodInstance_t; + +typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod); +typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod); +typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/** +* \struct DRXDemodFunc_t +* \brief A stucture containing all functions of a demodulator. +*/ +typedef struct { + u32_t typeId; /**< Device type identifier. */ + DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */ + DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */ + DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */ +} DRXDemodFunc_t, *pDRXDemodFunc_t; + +/** +* \struct DRXDemodInstance_t +* \brief Top structure of demodulator instance. +*/ +typedef struct DRXDemodInstance_s { + /* type specific demodulator data */ + pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */ + pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */ + pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */ + pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */ + pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */ + void* myExtAttr; /**< device specific attributes */ + /* generic demodulator data */ +} DRXDemodInstance_t; + + + +/*------------------------------------------------------------------------- +MACROS +Conversion from enum values to human readable form. +-------------------------------------------------------------------------*/ + +/* standard */ + +#define DRX_STR_STANDARD(x) ( \ + ( x == DRX_STANDARD_DVBT ) ? "DVB-T" : \ + ( x == DRX_STANDARD_8VSB ) ? "8VSB" : \ + ( x == DRX_STANDARD_NTSC ) ? "NTSC" : \ + ( x == DRX_STANDARD_PAL_SECAM_BG ) ? "PAL/SECAM B/G" : \ + ( x == DRX_STANDARD_PAL_SECAM_DK ) ? "PAL/SECAM D/K" : \ + ( x == DRX_STANDARD_PAL_SECAM_I ) ? "PAL/SECAM I" : \ + ( x == DRX_STANDARD_PAL_SECAM_L ) ? "PAL/SECAM L" : \ + ( x == DRX_STANDARD_PAL_SECAM_LP ) ? "PAL/SECAM LP" : \ + ( x == DRX_STANDARD_ITU_A ) ? "ITU-A" : \ + ( x == DRX_STANDARD_ITU_B ) ? "ITU-B" : \ + ( x == DRX_STANDARD_ITU_C ) ? "ITU-C" : \ + ( x == DRX_STANDARD_ITU_D ) ? "ITU-D" : \ + ( x == DRX_STANDARD_FM ) ? "FM" : \ + ( x == DRX_STANDARD_DTMB ) ? "DTMB" : \ + ( x == DRX_STANDARD_AUTO ) ? "Auto" : \ + ( x == DRX_STANDARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +/* channel */ + +#define DRX_STR_BANDWIDTH(x) ( \ + ( x == DRX_BANDWIDTH_8MHZ ) ? "8 MHz" : \ + ( x == DRX_BANDWIDTH_7MHZ ) ? "7 MHz" : \ + ( x == DRX_BANDWIDTH_6MHZ ) ? "6 MHz" : \ + ( x == DRX_BANDWIDTH_AUTO ) ? "Auto" : \ + ( x == DRX_BANDWIDTH_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_FFTMODE(x) ( \ + ( x == DRX_FFTMODE_2K ) ? "2k" : \ + ( x == DRX_FFTMODE_4K ) ? "4k" : \ + ( x == DRX_FFTMODE_8K ) ? "8k" : \ + ( x == DRX_FFTMODE_AUTO ) ? "Auto" : \ + ( x == DRX_FFTMODE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_GUARD(x) ( \ + ( x == DRX_GUARD_1DIV32 ) ? "1/32nd" : \ + ( x == DRX_GUARD_1DIV16 ) ? "1/16th" : \ + ( x == DRX_GUARD_1DIV8 ) ? "1/8th" : \ + ( x == DRX_GUARD_1DIV4 ) ? "1/4th" : \ + ( x == DRX_GUARD_AUTO ) ? "Auto" : \ + ( x == DRX_GUARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CONSTELLATION(x) ( \ + ( x == DRX_CONSTELLATION_BPSK ) ? "BPSK" : \ + ( x == DRX_CONSTELLATION_QPSK ) ? "QPSK" : \ + ( x == DRX_CONSTELLATION_PSK8 ) ? "PSK8" : \ + ( x == DRX_CONSTELLATION_QAM16 ) ? "QAM16" : \ + ( x == DRX_CONSTELLATION_QAM32 ) ? "QAM32" : \ + ( x == DRX_CONSTELLATION_QAM64 ) ? "QAM64" : \ + ( x == DRX_CONSTELLATION_QAM128 ) ? "QAM128" : \ + ( x == DRX_CONSTELLATION_QAM256 ) ? "QAM256" : \ + ( x == DRX_CONSTELLATION_QAM512 ) ? "QAM512" : \ + ( x == DRX_CONSTELLATION_QAM1024 ) ? "QAM1024" : \ + ( x == DRX_CONSTELLATION_QPSK_NR ) ? "QPSK_NR" : \ + ( x == DRX_CONSTELLATION_AUTO ) ? "Auto" : \ + ( x == DRX_CONSTELLATION_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CODERATE(x) ( \ + ( x == DRX_CODERATE_1DIV2 ) ? "1/2nd" : \ + ( x == DRX_CODERATE_2DIV3 ) ? "2/3rd" : \ + ( x == DRX_CODERATE_3DIV4 ) ? "3/4th" : \ + ( x == DRX_CODERATE_5DIV6 ) ? "5/6th" : \ + ( x == DRX_CODERATE_7DIV8 ) ? "7/8th" : \ + ( x == DRX_CODERATE_AUTO ) ? "Auto" : \ + ( x == DRX_CODERATE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_HIERARCHY(x) ( \ + ( x == DRX_HIERARCHY_NONE ) ? "None" : \ + ( x == DRX_HIERARCHY_ALPHA1 ) ? "Alpha=1" : \ + ( x == DRX_HIERARCHY_ALPHA2 ) ? "Alpha=2" : \ + ( x == DRX_HIERARCHY_ALPHA4 ) ? "Alpha=4" : \ + ( x == DRX_HIERARCHY_AUTO ) ? "Auto" : \ + ( x == DRX_HIERARCHY_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_PRIORITY(x) ( \ + ( x == DRX_PRIORITY_LOW ) ? "Low" : \ + ( x == DRX_PRIORITY_HIGH ) ? "High" : \ + ( x == DRX_PRIORITY_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_MIRROR(x) ( \ + ( x == DRX_MIRROR_NO ) ? "Normal" : \ + ( x == DRX_MIRROR_YES ) ? "Mirrored" : \ + ( x == DRX_MIRROR_AUTO ) ? "Auto" : \ + ( x == DRX_MIRROR_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_CLASSIFICATION(x) ( \ + ( x == DRX_CLASSIFICATION_GAUSS ) ? "Gaussion" : \ + ( x == DRX_CLASSIFICATION_HVY_GAUSS ) ? "Heavy Gaussion" : \ + ( x == DRX_CLASSIFICATION_COCHANNEL ) ? "Co-channel" : \ + ( x == DRX_CLASSIFICATION_STATIC ) ? "Static echo" : \ + ( x == DRX_CLASSIFICATION_MOVING ) ? "Moving echo" : \ + ( x == DRX_CLASSIFICATION_ZERODB ) ? "Zero dB echo" : \ + ( x == DRX_CLASSIFICATION_UNKNOWN ) ? "Unknown" : \ + ( x == DRX_CLASSIFICATION_AUTO ) ? "Auto" : \ + "(Invalid)" ) + +#define DRX_STR_INTERLEAVEMODE(x) ( \ + ( x == DRX_INTERLEAVEMODE_I128_J1 ) ? "I128_J1" : \ + ( x == DRX_INTERLEAVEMODE_I128_J1_V2 ) ? "I128_J1_V2" : \ + ( x == DRX_INTERLEAVEMODE_I128_J2 ) ? "I128_J2" : \ + ( x == DRX_INTERLEAVEMODE_I64_J2 ) ? "I64_J2" : \ + ( x == DRX_INTERLEAVEMODE_I128_J3 ) ? "I128_J3" : \ + ( x == DRX_INTERLEAVEMODE_I32_J4 ) ? "I32_J4" : \ + ( x == DRX_INTERLEAVEMODE_I128_J4 ) ? "I128_J4" : \ + ( x == DRX_INTERLEAVEMODE_I16_J8 ) ? "I16_J8" : \ + ( x == DRX_INTERLEAVEMODE_I128_J5 ) ? "I128_J5" : \ + ( x == DRX_INTERLEAVEMODE_I8_J16 ) ? "I8_J16" : \ + ( x == DRX_INTERLEAVEMODE_I128_J6 ) ? "I128_J6" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_11 ) ? "Reserved 11" : \ + ( x == DRX_INTERLEAVEMODE_I128_J7 ) ? "I128_J7" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_13 ) ? "Reserved 13" : \ + ( x == DRX_INTERLEAVEMODE_I128_J8 ) ? "I128_J8" : \ + ( x == DRX_INTERLEAVEMODE_RESERVED_15 ) ? "Reserved 15" : \ + ( x == DRX_INTERLEAVEMODE_I12_J17 ) ? "I12_J17" : \ + ( x == DRX_INTERLEAVEMODE_I5_J4 ) ? "I5_J4" : \ + ( x == DRX_INTERLEAVEMODE_B52_M240 ) ? "B52_M240" : \ + ( x == DRX_INTERLEAVEMODE_B52_M720 ) ? "B52_M720" : \ + ( x == DRX_INTERLEAVEMODE_B52_M48 ) ? "B52_M48" : \ + ( x == DRX_INTERLEAVEMODE_B52_M0 ) ? "B52_M0" : \ + ( x == DRX_INTERLEAVEMODE_UNKNOWN ) ? "Unknown" : \ + ( x == DRX_INTERLEAVEMODE_AUTO ) ? "Auto" : \ + "(Invalid)" ) + +#define DRX_STR_LDPC(x) ( \ + ( x == DRX_LDPC_0_4 ) ? "0.4" : \ + ( x == DRX_LDPC_0_6 ) ? "0.6" : \ + ( x == DRX_LDPC_0_8 ) ? "0.8" : \ + ( x == DRX_LDPC_AUTO ) ? "Auto" : \ + ( x == DRX_LDPC_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_CARRIER(x) ( \ + ( x == DRX_CARRIER_MULTI ) ? "Multi" : \ + ( x == DRX_CARRIER_SINGLE ) ? "Single" : \ + ( x == DRX_CARRIER_AUTO ) ? "Auto" : \ + ( x == DRX_CARRIER_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_FRAMEMODE(x) ( \ + ( x == DRX_FRAMEMODE_420 ) ? "420" : \ + ( x == DRX_FRAMEMODE_595 ) ? "595" : \ + ( x == DRX_FRAMEMODE_945 ) ? "945" : \ + ( x == DRX_FRAMEMODE_420_FIXED_PN ) ? "420 with fixed PN" : \ + ( x == DRX_FRAMEMODE_945_FIXED_PN ) ? "945 with fixed PN" : \ + ( x == DRX_FRAMEMODE_AUTO ) ? "Auto" : \ + ( x == DRX_FRAMEMODE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_PILOT(x) ( \ + ( x == DRX_PILOT_ON ) ? "On" : \ + ( x == DRX_PILOT_OFF ) ? "Off" : \ + ( x == DRX_PILOT_AUTO ) ? "Auto" : \ + ( x == DRX_PILOT_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +/* TPS */ + +#define DRX_STR_TPS_FRAME(x) ( \ + ( x == DRX_TPS_FRAME1 ) ? "Frame1" : \ + ( x == DRX_TPS_FRAME2 ) ? "Frame2" : \ + ( x == DRX_TPS_FRAME3 ) ? "Frame3" : \ + ( x == DRX_TPS_FRAME4 ) ? "Frame4" : \ + ( x == DRX_TPS_FRAME_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +/* lock status */ + +#define DRX_STR_LOCKSTATUS(x) ( \ + ( x == DRX_NEVER_LOCK ) ? "Never" : \ + ( x == DRX_NOT_LOCKED ) ? "No" : \ + ( x == DRX_LOCKED ) ? "Locked" : \ + ( x == DRX_LOCK_STATE_1 ) ? "Lock state 1" : \ + ( x == DRX_LOCK_STATE_2 ) ? "Lock state 2" : \ + ( x == DRX_LOCK_STATE_3 ) ? "Lock state 3" : \ + ( x == DRX_LOCK_STATE_4 ) ? "Lock state 4" : \ + ( x == DRX_LOCK_STATE_5 ) ? "Lock state 5" : \ + ( x == DRX_LOCK_STATE_6 ) ? "Lock state 6" : \ + ( x == DRX_LOCK_STATE_7 ) ? "Lock state 7" : \ + ( x == DRX_LOCK_STATE_8 ) ? "Lock state 8" : \ + ( x == DRX_LOCK_STATE_9 ) ? "Lock state 9" : \ + "(Invalid)" ) + +/* version information , modules */ +#define DRX_STR_MODULE(x) ( \ + ( x == DRX_MODULE_DEVICE ) ? "Device" : \ + ( x == DRX_MODULE_MICROCODE ) ? "Microcode" : \ + ( x == DRX_MODULE_DRIVERCORE ) ? "CoreDriver" : \ + ( x == DRX_MODULE_DEVICEDRIVER ) ? "DeviceDriver" : \ + ( x == DRX_MODULE_BSP_I2C ) ? "BSP I2C" : \ + ( x == DRX_MODULE_BSP_TUNER ) ? "BSP Tuner" : \ + ( x == DRX_MODULE_BSP_HOST ) ? "BSP Host" : \ + ( x == DRX_MODULE_DAP ) ? "Data Access Protocol" : \ + ( x == DRX_MODULE_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) + +#define DRX_STR_POWER_MODE(x) ( \ + ( x == DRX_POWER_UP ) ? "DRX_POWER_UP " : \ + ( x == DRX_POWER_MODE_1 ) ? "DRX_POWER_MODE_1" : \ + ( x == DRX_POWER_MODE_2 ) ? "DRX_POWER_MODE_2" : \ + ( x == DRX_POWER_MODE_3 ) ? "DRX_POWER_MODE_3" : \ + ( x == DRX_POWER_MODE_4 ) ? "DRX_POWER_MODE_4" : \ + ( x == DRX_POWER_MODE_5 ) ? "DRX_POWER_MODE_5" : \ + ( x == DRX_POWER_MODE_6 ) ? "DRX_POWER_MODE_6" : \ + ( x == DRX_POWER_MODE_7 ) ? "DRX_POWER_MODE_7" : \ + ( x == DRX_POWER_MODE_8 ) ? "DRX_POWER_MODE_8" : \ + ( x == DRX_POWER_MODE_9 ) ? "DRX_POWER_MODE_9" : \ + ( x == DRX_POWER_MODE_10 ) ? "DRX_POWER_MODE_10" : \ + ( x == DRX_POWER_MODE_11 ) ? "DRX_POWER_MODE_11" : \ + ( x == DRX_POWER_MODE_12 ) ? "DRX_POWER_MODE_12" : \ + ( x == DRX_POWER_MODE_13 ) ? "DRX_POWER_MODE_13" : \ + ( x == DRX_POWER_MODE_14 ) ? "DRX_POWER_MODE_14" : \ + ( x == DRX_POWER_MODE_15 ) ? "DRX_POWER_MODE_15" : \ + ( x == DRX_POWER_MODE_16 ) ? "DRX_POWER_MODE_16" : \ + ( x == DRX_POWER_DOWN ) ? "DRX_POWER_DOWN " : \ + "(Invalid)" ) + +#define DRX_STR_OOB_STANDARD(x) ( \ + ( x == DRX_OOB_MODE_A ) ? "ANSI 55-1 " : \ + ( x == DRX_OOB_MODE_B_GRADE_A ) ? "ANSI 55-2 A" : \ + ( x == DRX_OOB_MODE_B_GRADE_B ) ? "ANSI 55-2 B" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_STANDARD(x) ( \ + ( x == DRX_AUD_STANDARD_BTSC ) ? "BTSC" : \ + ( x == DRX_AUD_STANDARD_A2 ) ? "A2" : \ + ( x == DRX_AUD_STANDARD_EIAJ ) ? "EIAJ" : \ + ( x == DRX_AUD_STANDARD_FM_STEREO ) ? "FM Stereo" : \ + ( x == DRX_AUD_STANDARD_AUTO ) ? "Auto" : \ + ( x == DRX_AUD_STANDARD_M_MONO ) ? "M-Standard Mono" : \ + ( x == DRX_AUD_STANDARD_D_K_MONO ) ? "D/K Mono FM" : \ + ( x == DRX_AUD_STANDARD_BG_FM ) ? "B/G-Dual Carrier FM (A2)" : \ + ( x == DRX_AUD_STANDARD_D_K1 ) ? "D/K1-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_D_K2 ) ? "D/K2-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_D_K3 ) ? "D/K3-Dual Carrier FM" : \ + ( x == DRX_AUD_STANDARD_BG_NICAM_FM ) ? "B/G-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_L_NICAM_AM ) ? "L-NICAM-AM" : \ + ( x == DRX_AUD_STANDARD_I_NICAM_FM ) ? "I-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_D_K_NICAM_FM ) ? "D/K-NICAM-FM" : \ + ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \ + "(Invalid)" ) +#define DRX_STR_AUD_STEREO(x) ( \ + ( x == TRUE ) ? "Stereo" : \ + ( x == FALSE ) ? "Mono" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_SAP(x) ( \ + ( x == TRUE ) ? "Present" : \ + ( x == FALSE ) ? "Not present" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_CARRIER(x) ( \ + ( x == TRUE ) ? "Present" : \ + ( x == FALSE ) ? "Not present" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_RDS(x) ( \ + ( x == TRUE ) ? "Available" : \ + ( x == FALSE ) ? "Not Available" : \ + "(Invalid)" ) + +#define DRX_STR_AUD_NICAM_STATUS(x) ( \ + ( x == DRX_AUD_NICAM_DETECTED ) ? "Detected" : \ + ( x == DRX_AUD_NICAM_NOT_DETECTED ) ? "Not detected" : \ + ( x == DRX_AUD_NICAM_BAD ) ? "Bad" : \ + "(Invalid)" ) + +#define DRX_STR_RDS_VALID(x) ( \ + ( x == TRUE ) ? "Valid" : \ + ( x == FALSE ) ? "Not Valid" : \ + "(Invalid)" ) + +/*------------------------------------------------------------------------- +Access macros +-------------------------------------------------------------------------*/ + + +/** +* \brief Create a compilable reference to the microcode attribute +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRX_ATTR_MCRECORD( d ) ((d)->myCommonAttr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT( d ) ((d)->myCommonAttr->mirrorFreqSpect) +#define DRX_ATTR_CURRENTPOWERMODE( d )((d)->myCommonAttr->currentPowerMode) +#define DRX_ATTR_ISOPENED( d ) ((d)->myCommonAttr->isOpened) +#define DRX_ATTR_USEBOOTLOADER( d ) ((d)->myCommonAttr->useBootloader) +#define DRX_ATTR_CURRENTSTANDARD( d ) ((d)->myCommonAttr->currentStandard) +#define DRX_ATTR_PREVSTANDARD( d ) ((d)->myCommonAttr->prevStandard) +#define DRX_ATTR_CACHESTANDARD( d ) ((d)->myCommonAttr->diCacheStandard) +#define DRX_ATTR_CURRENTCHANNEL( d ) ((d)->myCommonAttr->currentChannel) +#define DRX_ATTR_MICROCODE( d ) ((d)->myCommonAttr->microcode) +#define DRX_ATTR_MICROCODESIZE( d ) ((d)->myCommonAttr->microcodeSize) +#define DRX_ATTR_VERIFYMICROCODE( d ) ((d)->myCommonAttr->verifyMicrocode) +#define DRX_ATTR_CAPABILITIES( d ) ((d)->myCommonAttr->capabilities) +#define DRX_ATTR_PRODUCTID( d ) ((d)->myCommonAttr->productId) +#define DRX_ATTR_INTERMEDIATEFREQ( d) ((d)->myCommonAttr->intermediateFreq) +#define DRX_ATTR_SYSCLOCKFREQ( d) ((d)->myCommonAttr->sysClockFreq) +#define DRX_ATTR_TUNERRFAGCPOL( d ) ((d)->myCommonAttr->tunerRfAgcPol) +#define DRX_ATTR_TUNERIFAGCPOL( d) ((d)->myCommonAttr->tunerIfAgcPol) +#define DRX_ATTR_TUNERSLOWMODE( d) ((d)->myCommonAttr->tunerSlowMode) +#define DRX_ATTR_TUNERSPORTNR( d) ((d)->myCommonAttr->tunerPortNr) +#define DRX_ATTR_TUNER( d ) ((d)->myTuner) +#define DRX_ATTR_I2CADDR( d ) ((d)->myI2CDevAddr->i2cAddr) +#define DRX_ATTR_I2CDEVID( d ) ((d)->myI2CDevAddr->i2cDevId) + +/** +* \brief Actual access macro's +* \param d pointer to demod instance +* \param x value to set ar to get +* +* SET macro's must be used to set the value of an attribute. +* GET macro's must be used to retrieve the value of an attribute. +* +*/ + +/**************************/ + +#define DRX_SET_MIRRORFREQSPECT( d, x ) \ + do { \ + DRX_ATTR_MIRRORFREQSPECT( d ) = (x); \ + } while(0) + +#define DRX_GET_MIRRORFREQSPECT( d, x ) \ + do { \ + (x)=DRX_ATTR_MIRRORFREQSPECT( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTPOWERMODE( d, x ) \ + do { \ + DRX_ATTR_CURRENTPOWERMODE( d ) = (x); \ + } while(0) + +#define DRX_GET_CURRENTPOWERMODE( d, x ) \ + do { \ + (x)=DRX_ATTR_CURRENTPOWERMODE( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_MICROCODE( d, x ) \ + do { \ + DRX_ATTR_MICROCODE( d ) = (x); \ + } while(0) + +#define DRX_GET_MICROCODE( d, x ) \ + do { \ + (x)=DRX_ATTR_MICROCODE( d ); \ + } while(0) + +/**************************/ + +#define DRX_SET_MICROCODESIZE( d, x ) \ + do { \ + DRX_ATTR_MICROCODESIZE(d) = (x); \ + } while(0) + +#define DRX_GET_MICROCODESIZE( d, x ) \ + do { \ + (x)=DRX_ATTR_MICROCODESIZE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_VERIFYMICROCODE( d, x ) \ + do { \ + DRX_ATTR_VERIFYMICROCODE(d) = (x); \ + } while(0) + +#define DRX_GET_VERIFYMICROCODE( d, x ) \ + do { \ + (x)=DRX_ATTR_VERIFYMICROCODE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_MCVERTYPE( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).auxType = (x); \ + } while (0) + +#define DRX_GET_MCVERTYPE( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).auxType; \ + } while (0) + +/**************************/ + +#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) + +/**************************/ + +#define DRX_SET_MCDEV( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcDevType = (x); \ + } while (0) + +#define DRX_GET_MCDEV( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcDevType; \ + } while (0) + +/**************************/ + +#define DRX_SET_MCVERSION( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcVersion = (x); \ + } while (0) + +#define DRX_GET_MCVERSION( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcVersion; \ + } while (0) + +/**************************/ +#define DRX_SET_MCPATCH( d, x ) \ + do { \ + DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \ + } while (0) + +#define DRX_GET_MCPATCH( d, x ) \ + do { \ + (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \ + } while (0) + +/**************************/ + +#define DRX_SET_I2CADDR( d, x ) \ + do { \ + DRX_ATTR_I2CADDR(d) = (x); \ + } while(0) + +#define DRX_GET_I2CADDR( d, x ) \ + do { \ + (x)=DRX_ATTR_I2CADDR(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_I2CDEVID( d, x ) \ + do { \ + DRX_ATTR_I2CDEVID(d) = (x); \ + } while(0) + +#define DRX_GET_I2CDEVID( d, x ) \ + do { \ + (x)=DRX_ATTR_I2CDEVID(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_USEBOOTLOADER( d, x ) \ + do { \ + DRX_ATTR_USEBOOTLOADER(d) = (x); \ + } while(0) + +#define DRX_GET_USEBOOTLOADER( d, x) \ + do { \ + (x)=DRX_ATTR_USEBOOTLOADER(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTSTANDARD( d, x ) \ + do { \ + DRX_ATTR_CURRENTSTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_CURRENTSTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_CURRENTSTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_PREVSTANDARD( d, x ) \ + do { \ + DRX_ATTR_PREVSTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_PREVSTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_PREVSTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CACHESTANDARD( d, x ) \ + do { \ + DRX_ATTR_CACHESTANDARD(d) = (x); \ + } while(0) + +#define DRX_GET_CACHESTANDARD( d, x) \ + do { \ + (x)=DRX_ATTR_CACHESTANDARD(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CURRENTCHANNEL( d, x ) \ + do { \ + DRX_ATTR_CURRENTCHANNEL(d) = (x); \ + } while(0) + +#define DRX_GET_CURRENTCHANNEL( d, x) \ + do { \ + (x)=DRX_ATTR_CURRENTCHANNEL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_ISOPENED( d, x ) \ + do { \ + DRX_ATTR_ISOPENED(d) = (x); \ + } while(0) + +#define DRX_GET_ISOPENED( d, x) \ + do { \ + (x) = DRX_ATTR_ISOPENED(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNER( d, x ) \ + do { \ + DRX_ATTR_TUNER(d) = (x); \ + } while(0) + +#define DRX_GET_TUNER( d, x) \ + do { \ + (x) = DRX_ATTR_TUNER(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_CAPABILITIES( d, x ) \ + do { \ + DRX_ATTR_CAPABILITIES(d) = (x); \ + } while(0) + +#define DRX_GET_CAPABILITIES( d, x) \ + do { \ + (x) = DRX_ATTR_CAPABILITIES(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_PRODUCTID( d, x ) \ + do { \ + DRX_ATTR_PRODUCTID(d) |= (x << 4); \ + } while(0) + +#define DRX_GET_PRODUCTID( d, x) \ + do { \ + (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \ + } while(0) + +/**************************/ + +#define DRX_SET_MFX( d, x ) \ + do { \ + DRX_ATTR_PRODUCTID(d) |= (x); \ + } while(0) + +#define DRX_GET_MFX( d, x) \ + do { \ + (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \ + } while(0) + +/**************************/ + +#define DRX_SET_INTERMEDIATEFREQ( d, x ) \ + do { \ + DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \ + } while(0) + +#define DRX_GET_INTERMEDIATEFREQ( d, x) \ + do { \ + (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_SYSCLOCKFREQ( d, x ) \ + do { \ + DRX_ATTR_SYSCLOCKFREQ(d) = (x); \ + } while(0) + +#define DRX_GET_SYSCLOCKFREQ( d, x) \ + do { \ + (x) = DRX_ATTR_SYSCLOCKFREQ(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERRFAGCPOL( d, x ) \ + do { \ + DRX_ATTR_TUNERRFAGCPOL(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERRFAGCPOL( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERRFAGCPOL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERIFAGCPOL( d, x ) \ + do { \ + DRX_ATTR_TUNERIFAGCPOL(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERIFAGCPOL( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERIFAGCPOL(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERSLOWMODE( d, x ) \ + do { \ + DRX_ATTR_TUNERSLOWMODE(d) = (x); \ + } while(0) + +#define DRX_GET_TUNERSLOWMODE( d, x) \ + do { \ + (x) = DRX_ATTR_TUNERSLOWMODE(d); \ + } while(0) + +/**************************/ + +#define DRX_SET_TUNERPORTNR( d, x ) \ + do { \ + DRX_ATTR_TUNERSPORTNR(d) = (x); \ + } while(0) + +/**************************/ + +/* Macros with device-specific handling are converted to CFG functions */ + +#define DRX_ACCESSMACRO_SET( demod, value, cfgName, dataType ) \ + do { \ + DRXCfg_t config; \ + dataType cfgData; \ + config.cfgType = cfgName; \ + config.cfgData = &cfgData; \ + cfgData = value; \ + DRX_Ctrl( demod, DRX_CTRL_SET_CFG, &config ); \ + } while ( 0 ) + +#define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \ + do { \ + DRXStatus_t cfgStatus; \ + DRXCfg_t config; \ + dataType cfgData; \ + config.cfgType = cfgName; \ + config.cfgData = &cfgData; \ + cfgStatus = DRX_Ctrl( demod, DRX_CTRL_GET_CFG, &config ); \ + if ( cfgStatus == DRX_STS_OK ) { \ + value = cfgData; \ + } else { \ + value = (dataType)errorValue; \ + } \ + } while ( 0 ) + + +/* Configuration functions for usage by Access (XS) Macros */ + +#ifndef DRX_XS_CFG_BASE +#define DRX_XS_CFG_BASE (500) +#endif + +#define DRX_XS_CFG_PRESET ( DRX_XS_CFG_BASE + 0 ) +#define DRX_XS_CFG_AUD_BTSC_DETECT ( DRX_XS_CFG_BASE + 1 ) +#define DRX_XS_CFG_QAM_LOCKRANGE ( DRX_XS_CFG_BASE + 2 ) + +/* Access Macros with device-specific handling */ + +#define DRX_SET_PRESET( d, x ) \ + DRX_ACCESSMACRO_SET( (d), (x), DRX_XS_CFG_PRESET, char* ) +#define DRX_GET_PRESET( d, x ) \ + DRX_ACCESSMACRO_GET( (d), (x), DRX_XS_CFG_PRESET, char*, "ERROR" ) + +#define DRX_SET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t ) +#define DRX_GET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN ) + +#define DRX_SET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t ) +#define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN ) + + +/** +* \brief Macro to check if std is an ATV standard +* \retval TRUE std is an ATV standard +* \retval FALSE std is an ATV standard +*/ +#define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_I ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_L ) || \ + ( (std) == DRX_STANDARD_PAL_SECAM_LP ) || \ + ( (std) == DRX_STANDARD_NTSC ) || \ + ( (std) == DRX_STANDARD_FM ) ) + +/** +* \brief Macro to check if std is an QAM standard +* \retval TRUE std is an QAM standards +* \retval FALSE std is an QAM standards +*/ +#define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \ + ( (std) == DRX_STANDARD_ITU_B ) || \ + ( (std) == DRX_STANDARD_ITU_C ) || \ + ( (std) == DRX_STANDARD_ITU_D )) + +/** +* \brief Macro to check if std is VSB standard +* \retval TRUE std is VSB standard +* \retval FALSE std is not VSB standard +*/ +#define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB ) + +/** +* \brief Macro to check if std is DVBT standard +* \retval TRUE std is DVBT standard +* \retval FALSE std is not DVBT standard +*/ +#define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT ) + + + + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +DRXStatus_t DRX_Init( pDRXDemodInstance_t demods[] ); + +DRXStatus_t DRX_Term( void ); + +DRXStatus_t DRX_Open(pDRXDemodInstance_t demod); + +DRXStatus_t DRX_Close(pDRXDemodInstance_t demod); + +DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h new file mode 100644 index 000000000000..e6c777c13cf1 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -0,0 +1,83 @@ +/* + ******************************************************************************* + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drx_driver_version.h + * Generated on: Mon Jan 18 12:09:23 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: ../../../device/drxj/version + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * version.idf Mon Jan 18 11:56:10 2010 - + * + * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. + * + * This software and related documentation (the 'Software') are intellectual + * property owned by Trident and are copyright of Trident, unless specifically + * noted otherwise. + * + * Any use of the Software is permitted only pursuant to the terms of the + * license agreement, if any, which accompanies, is included with or applicable + * to the Software ('License Agreement') or upon express written consent of + * Trident. Any copying, reproduction or redistribution of the Software in + * whole or in part by any means not in accordance with the License Agreement + * or as agreed in writing by Trident is expressly prohibited. + * + * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE + * LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE + * IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND + * CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND + * CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT + * ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL + * PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO + * USE THE SOFTWARE. + * + * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, + * PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, + * DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF + * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF + * OR THE INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING + * FROM TRIDENT'S NEGLIGENCE. $ + * + ******************************************************************************* + */ + +#ifndef __DRX_DRIVER_VERSION__H__ +#define __DRX_DRIVER_VERSION__H__ INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _REGISTERTABLE_ +#include +extern RegisterTable_t drx_driver_version[]; +extern RegisterTableInfo_t drx_driver_version_info[]; +#endif /* _REGISTERTABLE_ */ + + +/* + *============================================================================== + * VERSION + * version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj + *============================================================================== + */ + +#define VERSION__A 0x0 +#define VERSION_MAJOR 1 +#define VERSION_MINOR 0 +#define VERSION_PATCH 56 + +#ifdef __cplusplus +} +#endif + +#endif /* __DRX_DRIVER_VERSION__H__ */ + +/* + * End of file (drx_driver_version.h) + ******************************************************************************* + */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c new file mode 100644 index 000000000000..a83f2ad67e7f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -0,0 +1,16680 @@ +/** +* \file $Id: drxj.c,v 1.637 2010/01/18 17:21:10 dingtao Exp $ +* +* \brief DRXJ specific implementation of DRX driver +* +* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +/* +* $(c) 2006-2010 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/*----------------------------------------------------------------------------- +INCLUDE FILES +----------------------------------------------------------------------------*/ + +#include "drxj.h" +#include "drxj_map.h" + +#ifdef DRXJ_OPTIONS_H +#include "drxj_options.h" +#endif + + +/*============================================================================*/ +/*=== DEFINES ================================================================*/ +/*============================================================================*/ + +/** +* \brief Maximum u32_t value. +*/ +#ifndef MAX_U32 +#define MAX_U32 ((u32_t) (0xFFFFFFFFL)) +#endif + +/* Customer configurable hardware settings, etc */ +#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06 +#endif + +#ifndef OOB_CRX_DRIVE_STRENGTH +#define OOB_CRX_DRIVE_STRENGTH 0x02 +#endif + +#ifndef OOB_DRX_DRIVE_STRENGTH +#define OOB_DRX_DRIVE_STRENGTH 0x02 +#endif +/**** START DJCOMBO patches to DRXJ registermap constants *********************/ +/**** registermap 200706071303 from drxj **************************************/ +#define ATV_TOP_CR_AMP_TH_FM 0x0 +#define ATV_TOP_CR_AMP_TH_L 0xA +#define ATV_TOP_CR_AMP_TH_LP 0xA +#define ATV_TOP_CR_AMP_TH_BG 0x8 +#define ATV_TOP_CR_AMP_TH_DK 0x8 +#define ATV_TOP_CR_AMP_TH_I 0x8 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 +#define ATV_TOP_CR_CONT_CR_D_L 0x20 +#define ATV_TOP_CR_CONT_CR_D_LP 0x20 +#define ATV_TOP_CR_CONT_CR_D_BG 0x18 +#define ATV_TOP_CR_CONT_CR_D_DK 0x18 +#define ATV_TOP_CR_CONT_CR_D_I 0x18 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 +#define ATV_TOP_CR_CONT_CR_I_L 0x80 +#define ATV_TOP_CR_CONT_CR_I_LP 0x80 +#define ATV_TOP_CR_CONT_CR_I_BG 0x80 +#define ATV_TOP_CR_CONT_CR_I_DK 0x80 +#define ATV_TOP_CR_CONT_CR_I_I 0x80 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 +#define ATV_TOP_CR_CONT_CR_P_L 0x4 +#define ATV_TOP_CR_CONT_CR_P_LP 0x4 +#define ATV_TOP_CR_CONT_CR_P_BG 0x4 +#define ATV_TOP_CR_CONT_CR_P_DK 0x4 +#define ATV_TOP_CR_CONT_CR_P_I 0x4 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 +#define ATV_TOP_CR_OVM_TH_L 0xA0 +#define ATV_TOP_CR_OVM_TH_LP 0xA0 +#define ATV_TOP_CR_OVM_TH_BG 0xA0 +#define ATV_TOP_CR_OVM_TH_DK 0xA0 +#define ATV_TOP_CR_OVM_TH_I 0xA0 +#define ATV_TOP_EQU0_EQU_C0_FM 0x0 +#define ATV_TOP_EQU0_EQU_C0_L 0x3 +#define ATV_TOP_EQU0_EQU_C0_LP 0x3 +#define ATV_TOP_EQU0_EQU_C0_BG 0x7 +#define ATV_TOP_EQU0_EQU_C0_DK 0x0 +#define ATV_TOP_EQU0_EQU_C0_I 0x3 +#define ATV_TOP_EQU1_EQU_C1_FM 0x0 +#define ATV_TOP_EQU1_EQU_C1_L 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_BG 0x197 +#define ATV_TOP_EQU1_EQU_C1_DK 0x198 +#define ATV_TOP_EQU1_EQU_C1_I 0x1F6 +#define ATV_TOP_EQU2_EQU_C2_FM 0x0 +#define ATV_TOP_EQU2_EQU_C2_L 0x28 +#define ATV_TOP_EQU2_EQU_C2_LP 0x28 +#define ATV_TOP_EQU2_EQU_C2_BG 0xC5 +#define ATV_TOP_EQU2_EQU_C2_DK 0xB0 +#define ATV_TOP_EQU2_EQU_C2_I 0x28 +#define ATV_TOP_EQU3_EQU_C3_FM 0x0 +#define ATV_TOP_EQU3_EQU_C3_L 0x192 +#define ATV_TOP_EQU3_EQU_C3_LP 0x192 +#define ATV_TOP_EQU3_EQU_C3_BG 0x12E +#define ATV_TOP_EQU3_EQU_C3_DK 0x18E +#define ATV_TOP_EQU3_EQU_C3_I 0x192 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 +#define ATV_TOP_STD_MODE_L 0x0 +#define ATV_TOP_STD_MODE_LP 0x0 +#define ATV_TOP_STD_MODE_BG 0x0 +#define ATV_TOP_STD_MODE_DK 0x0 +#define ATV_TOP_STD_MODE_I 0x0 +#define ATV_TOP_STD_VID_POL_MN 0x0 +#define ATV_TOP_STD_VID_POL_FM 0x0 +#define ATV_TOP_STD_VID_POL_L 0x2 +#define ATV_TOP_STD_VID_POL_LP 0x2 +#define ATV_TOP_STD_VID_POL_BG 0x0 +#define ATV_TOP_STD_VID_POL_DK 0x0 +#define ATV_TOP_STD_VID_POL_I 0x0 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 +#define ATV_TOP_VID_AMP_L 0xF50 +#define ATV_TOP_VID_AMP_LP 0xF50 +#define ATV_TOP_VID_AMP_BG 0x380 +#define ATV_TOP_VID_AMP_DK 0x394 +#define ATV_TOP_VID_AMP_I 0x3D8 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 +/**** END DJCOMBO patches to DRXJ registermap *********************************/ + +#include "drx_driver_version.h" + +//#define DRX_DEBUG +#ifdef DRX_DEBUG +#include +#endif + +/*----------------------------------------------------------------------------- +ENUMS +----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- +DEFINES +----------------------------------------------------------------------------*/ +#ifndef DRXJ_WAKE_UP_KEY +#define DRXJ_WAKE_UP_KEY (demod -> myI2CDevAddr -> i2cAddr) +#endif + +/** +* \def DRXJ_DEF_I2C_ADDR +* \brief Default I2C addres of a demodulator instance. +*/ +#define DRXJ_DEF_I2C_ADDR (0x52) + +/** +* \def DRXJ_DEF_DEMOD_DEV_ID +* \brief Default device identifier of a demodultor instance. +*/ +#define DRXJ_DEF_DEMOD_DEV_ID (1) + +/** +* \def DRXJ_SCAN_TIMEOUT +* \brief Timeout value for waiting on demod lock during channel scan (millisec). +*/ +#define DRXJ_SCAN_TIMEOUT 1000 + +/** +* \def DRXJ_DAP +* \brief Name of structure containing all data access protocol functions. +*/ +#define DRXJ_DAP drxDapDRXJFunct_g + +/** +* \def HI_I2C_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_DIV +*/ +#define HI_I2C_DELAY 42 + +/** +* \def HI_I2C_BRIDGE_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_BDL +*/ +#define HI_I2C_BRIDGE_DELAY 750 + +/** +* \brief Time Window for MER and SER Measurement in Units of Segment duration. +*/ +#define VSB_TOP_MEASUREMENT_PERIOD 64 +#define SYMBOLS_PER_SEGMENT 832 + +/** +* \brief bit rate and segment rate constants used for SER and BER. +*/ +/* values taken from the QAM microcode */ +#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0 +#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768 +#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576 +#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960 +#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480 +#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 +#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 +#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 +/** +* \brief Min supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MIN +#define DRXJ_QAM_SYMBOLRATE_MIN (520000) +#endif + +/** +* \brief Max supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MAX +#define DRXJ_QAM_SYMBOLRATE_MAX (7233000) +#endif + +/** +* \def DRXJ_QAM_MAX_WAITTIME +* \brief Maximal wait time for QAM auto constellation in ms +*/ +#ifndef DRXJ_QAM_MAX_WAITTIME +#define DRXJ_QAM_MAX_WAITTIME 900 +#endif + +#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME +#define DRXJ_QAM_FEC_LOCK_WAITTIME 150 +#endif + +#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME +#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 +#endif + +/** +* \def SCU status and results +* \brief SCU +*/ +#define DRX_SCU_READY 0 +#define DRXJ_MAX_WAITTIME 100 /* ms */ +#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ +#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ + +/** +* \def DRX_AUD_MAX_DEVIATION +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_FM_DEVIATION +#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE +#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_WAITTIME +#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ +#endif + +/* ATV config changed flags */ +#define DRXJ_ATV_CHANGED_COEF ( 0x00000001UL ) +#define DRXJ_ATV_CHANGED_PEAK_FLT ( 0x00000008UL ) +#define DRXJ_ATV_CHANGED_NOISE_FLT ( 0x00000010UL ) +#define DRXJ_ATV_CHANGED_OUTPUT ( 0x00000020UL ) +#define DRXJ_ATV_CHANGED_SIF_ATT ( 0x00000040UL ) + +/* UIO define */ +#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 +#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ +/*=== MICROCODE RELATED DEFINES ==============================================*/ +/*============================================================================*/ + +/** +* \def DRXJ_UCODE_MAGIC_WORD +* \brief Magic word for checking correct Endianess of microcode data. +* +*/ + +#ifndef DRXJ_UCODE_MAGIC_WORD +#define DRXJ_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L')) +#endif + +/** +* \def DRXJ_UCODE_CRC_FLAG +* \brief CRC flag in ucode header, flags field. +* +*/ + +#ifndef DRXJ_UCODE_CRC_FLAG +#define DRXJ_UCODE_CRC_FLAG (0x0001) +#endif + +/** +* \def DRXJ_UCODE_COMPRESSION_FLAG +* \brief Compression flag in ucode header, flags field. +* +*/ + +#ifndef DRXJ_UCODE_COMPRESSION_FLAG +#define DRXJ_UCODE_COMPRESSION_FLAG (0x0002) +#endif + +/** +* \def DRXJ_UCODE_MAX_BUF_SIZE +* \brief Maximum size of buffer used to verify the microcode.Must be an even number. +* +*/ + +#ifndef DRXJ_UCODE_MAX_BUF_SIZE +#define DRXJ_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) +#endif +#if DRXJ_UCODE_MAX_BUF_SIZE & 1 +#error DRXJ_UCODE_MAX_BUF_SIZE must be an even number +#endif + +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/* Pin safe mode macro */ +#define DRXJ_PIN_SAFE_MODE 0x0000 +/*============================================================================*/ +/*=== GLOBAL VARIABLEs =======================================================*/ +/*============================================================================*/ +/** +*/ + +/** +* \brief Temporary register definitions. +* (register definitions that are not yet available in register master) +*/ + +/******************************************************************************/ +/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ +/* RAM adresses directly. This must be READ ONLY to avoid problems. */ +/* Writing to the interface adresses is more than only writing the RAM */ +/* locations */ +/******************************************************************************/ +/** +* \brief RAM location of MODUS registers +*/ +#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 +#define AUD_DEM_RAM_MODUS_HI__M 0xF000 + +#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 +#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF + +/** +* \brief RAM location of I2S config registers +*/ +#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 +#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 + +/** +* \brief RAM location of DCO config registers +*/ +#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 +#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462 +#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 +#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 + +/** +* \brief RAM location of Threshold registers +*/ +#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A +#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB +#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 + +/** +* \brief RAM location of Carrier Threshold registers +*/ +#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF +#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 + +/** +* \brief FM Matrix register fix +*/ +#ifdef AUD_DEM_WR_FM_MATRIX__A +#undef AUD_DEM_WR_FM_MATRIX__A +#endif +#define AUD_DEM_WR_FM_MATRIX__A 0x105006F + +/*============================================================================*/ +/** +* \brief Defines required for audio +*/ +#define AUD_VOLUME_ZERO_DB 115 +#define AUD_VOLUME_DB_MIN -60 +#define AUD_VOLUME_DB_MAX 12 +#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000 +#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421 +#define AUD_MAX_AVC_REF_LEVEL 15 +#define AUD_I2S_FREQUENCY_MAX 48000UL +#define AUD_I2S_FREQUENCY_MIN 12000UL +#define AUD_RDS_ARRAY_SIZE 18 + +/** +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_FM_DEVIATION +#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ +#endif + +/** +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_NICAM_PRESCALE +#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + + +/*============================================================================*/ +/* Values for I2S Master/Slave pin configurations */ +#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000 + +#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008 + +#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000 + +/*============================================================================*/ +/*=== REGISTER ACCESS MACROS =================================================*/ +/*============================================================================*/ + +#ifdef DRXJDRIVER_DEBUG +#include +#define CHK_ERROR( s ) \ + do{ \ + if ( (s) != DRX_STS_OK ) \ + { \ + fprintf(stderr, \ + "ERROR[\n file : %s\n line : %d\n]\n", \ + __FILE__,__LINE__); \ + goto rw_error; }; \ + } \ + while (0 != 0) +#else +#define CHK_ERROR( s ) \ + do{ \ + if ( (s) != DRX_STS_OK ) { goto rw_error; } \ + } while (0 != 0) +#endif + +#define CHK_ZERO( s ) \ + do{ \ + if ( (s) == 0 ) return DRX_STS_ERROR; \ + } while (0) + +#define DUMMY_READ() \ + do{ \ + u16_t dummy; \ + RR16( demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy ); \ + } while (0) + +#define WR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0 ) ) + +#define RR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0 ) ) + +#define WR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0 ) ) + +#define RR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0 ) ) + +#define WRB( dev, addr, len, block ) \ + CHK_ERROR( DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0 ) ) + +#define RRB( dev, addr, len, block ) \ + CHK_ERROR( DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0 ) ) + +#define BCWR16( dev, addr, val ) \ + CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST ) ) + +#define ARR32( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0 ) ) + +#define SARR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0 ) ) + +#define SAWR16( dev, addr, val) \ + CHK_ERROR( DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0 ) ) + +/** +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x -> lowbyte(x), highbyte(x) +*/ +#define DRXJ_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \ + ((u8_t)((((u16_t)x)>>8)&0xFF)) +/** +* This macro is used to convert byte array to 16 bit register value for block read. +* Block read speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +*/ +#define DRXJ_8TO16( x ) ((u16_t) (x[0] | (x[1] << 8))) + +/*============================================================================*/ +/*=== MISC DEFINES ===========================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*=== HI COMMAND RELATED DEFINES =============================================*/ +/*============================================================================*/ + +/** +* \brief General maximum number of retries for ucode command interfaces +*/ +#define DRXJ_MAX_RETRIES (100) + +/*============================================================================*/ +/*=== STANDARD RELATED MACROS ================================================*/ +/*============================================================================*/ + +#define DRXJ_ISATVSTD( std ) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \ + ( std == DRX_STANDARD_PAL_SECAM_DK ) || \ + ( std == DRX_STANDARD_PAL_SECAM_I ) || \ + ( std == DRX_STANDARD_PAL_SECAM_L ) || \ + ( std == DRX_STANDARD_PAL_SECAM_LP ) || \ + ( std == DRX_STANDARD_NTSC ) || \ + ( std == DRX_STANDARD_FM ) ) + +#define DRXJ_ISQAMSTD( std ) ( ( std == DRX_STANDARD_ITU_A ) || \ + ( std == DRX_STANDARD_ITU_B ) || \ + ( std == DRX_STANDARD_ITU_C ) || \ + ( std == DRX_STANDARD_ITU_D )) + +/*----------------------------------------------------------------------------- +STATIC VARIABLES +----------------------------------------------------------------------------*/ +DRXStatus_t DRXJ_Open ( pDRXDemodInstance_t demod ); +DRXStatus_t DRXJ_Close ( pDRXDemodInstance_t demod); +DRXStatus_t DRXJ_Ctrl ( pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*----------------------------------------------------------------------------- +GLOBAL VARIABLES +----------------------------------------------------------------------------*/ +/* + * DRXJ DAP structures + */ + +static DRXStatus_t DRXJ_DAP_ReadBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, + pu8_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, + pu32_t rdata); + +static DRXStatus_t DRXJ_DAP_ReadReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_ReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags); + +static DRXStatus_t DRXJ_DAP_WriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags); + +/* The version structure of this protocol implementation */ +char drxDapDRXJModuleName[] = "DRXJ Data Access Protocol"; +char drxDapDRXJVersionText[] = "0.0.0"; + +DRXVersion_t drxDapDRXJVersion = { + DRX_MODULE_DAP, /**< type identifier of the module */ + drxDapDRXJModuleName, /**< name or description of module */ + + 0, /**< major version number */ + 0, /**< minor version number */ + 0, /**< patch version number */ + drxDapDRXJVersionText /**< version as text string */ +}; + +/* The structure containing the protocol interface */ +DRXAccessFunc_t drxDapDRXJFunct_g = { + &drxDapDRXJVersion, + DRXJ_DAP_WriteBlock, /* Supported */ + DRXJ_DAP_ReadBlock, /* Supported */ + DRXJ_DAP_WriteReg8, /* Not supported */ + DRXJ_DAP_ReadReg8, /* Not supported */ + DRXJ_DAP_ReadModifyWriteReg8, /* Not supported */ + DRXJ_DAP_WriteReg16, /* Supported */ + DRXJ_DAP_ReadReg16, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg16, /* Supported */ + DRXJ_DAP_WriteReg32, /* Supported */ + DRXJ_DAP_ReadReg32, /* Supported */ + DRXJ_DAP_ReadModifyWriteReg32, /* Not supported */ +}; + +/** +* /var DRXJ_Func_g +* /brief The driver functions of the drxj +*/ +DRXDemodFunc_t DRXJFunctions_g = +{ + DRXJ_TYPE_ID, + DRXJ_Open, + DRXJ_Close, + DRXJ_Ctrl +}; + +DRXJData_t DRXJData_g = +{ + FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */ + FALSE, /* hasOOB : TRUE if OOB supported */ + FALSE, /* hasNTSC: TRUE if NTSC supported */ + FALSE, /* hasBTSC: TRUE if BTSC supported */ + FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */ + FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */ + FALSE, /* hasGPIO : TRUE if GPIO pin is available */ + FALSE, /* hasIRQN : TRUE if IRQN pin is available */ + 0, /* mfx A1/A2/A... */ + + /* tuner settings */ + FALSE, /* tuner mirrors RF signal */ + /* standard/channel settings */ + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_CONSTELLATION_AUTO, /* constellation */ + 0, /* frequency in KHz */ + DRX_BANDWIDTH_UNKNOWN, /* currBandwidth */ + DRX_MIRROR_NO, /* mirror */ + + /* signal quality information: */ + /* default values taken from the QAM Programming guide */ + /* fecBitsDesired should not be less than 4000000 */ + 4000000, /* fecBitsDesired */ + 5, /* fecVdPlen */ + 4, /* qamVdPrescale */ + 0xFFFF, /* qamVDPeriod */ + 204*8, /* fecRsPlen annex A */ + 1, /* fecRsPrescale */ + FEC_RS_MEASUREMENT_PERIOD,/* fecRsPeriod */ + TRUE, /* resetPktErrAcc */ + 0, /* pktErrAccStart */ + + /* HI configuration */ + 0, /* HICfgTimingDiv */ + 0, /* HICfgBridgeDelay */ + 0, /* HICfgWakeUpKey */ + 0, /* HICfgCtrl */ + 0, /* HICfgTimeout */ + /* UIO configuartion */ + DRX_UIO_MODE_DISABLE, /* uioSmaRxMode */ + DRX_UIO_MODE_DISABLE, /* uioSmaTxMode */ + DRX_UIO_MODE_DISABLE, /* uioASELMode */ + DRX_UIO_MODE_DISABLE, /* uioIRQNMode */ + /* FS setting */ + 0UL, /* iqmFsRateOfs */ + FALSE, /* posImage */ + /* RC setting */ + 0UL, /* iqmRcRateOfs */ + /* AUD information */ +/* FALSE, * flagSetAUDdone */ +/* FALSE, * detectedRDS */ +/* TRUE, * flagASDRequest */ +/* FALSE, * flagHDevClear */ +/* FALSE, * flagHDevSet */ +/* (u16_t) 0xFFF, * rdsLastCount */ + +/*#ifdef DRXJ_SPLIT_UCODE_UPLOAD + FALSE, * flagAudMcUploaded */ +/*#endif * DRXJ_SPLIT_UCODE_UPLOAD */ + /* ATV configuartion */ + 0UL, /* flags cfg changes */ + /* shadow of ATV_TOP_EQU0__A */ + {-5, + ATV_TOP_EQU0_EQU_C0_FM, + ATV_TOP_EQU0_EQU_C0_L, + ATV_TOP_EQU0_EQU_C0_LP, + ATV_TOP_EQU0_EQU_C0_BG, + ATV_TOP_EQU0_EQU_C0_DK, + ATV_TOP_EQU0_EQU_C0_I + }, + /* shadow of ATV_TOP_EQU1__A */ + {-50, + ATV_TOP_EQU1_EQU_C1_FM, + ATV_TOP_EQU1_EQU_C1_L, + ATV_TOP_EQU1_EQU_C1_LP, + ATV_TOP_EQU1_EQU_C1_BG, + ATV_TOP_EQU1_EQU_C1_DK, + ATV_TOP_EQU1_EQU_C1_I + }, + /* shadow of ATV_TOP_EQU2__A */ + {210, + ATV_TOP_EQU2_EQU_C2_FM, + ATV_TOP_EQU2_EQU_C2_L, + ATV_TOP_EQU2_EQU_C2_LP, + ATV_TOP_EQU2_EQU_C2_BG, + ATV_TOP_EQU2_EQU_C2_DK, + ATV_TOP_EQU2_EQU_C2_I + }, + /* shadow of ATV_TOP_EQU3__A */ + {-160, + ATV_TOP_EQU3_EQU_C3_FM, + ATV_TOP_EQU3_EQU_C3_L, + ATV_TOP_EQU3_EQU_C3_LP, + ATV_TOP_EQU3_EQU_C3_BG, + ATV_TOP_EQU3_EQU_C3_DK, + ATV_TOP_EQU3_EQU_C3_I + }, + FALSE, /* flag: TRUE=bypass */ + ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ + ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ + TRUE, /* flag CVBS ouput enable */ + FALSE, /* flag SIF ouput enable */ + DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ + { /* qamRfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top */ + 0x0000 /* c.o.c. */ + }, + { /* qamIfAgcCfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbRfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsbIfAgcCfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel */ + 0xFFFF, /* maxOutputLevel */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + 0, /* qamPgaCfg */ + 0, /* vsbPgaCfg */ + { /* qamPreSawCfg */ + DRX_STANDARD_ITU_B, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + { /* vsbPreSawCfg */ + DRX_STANDARD_8VSB, /* standard */ + 0, /* reference */ + FALSE /* usePreSaw */ + }, + + /* Version information */ +#ifndef _CH_ + { + "01234567890", /* human readable version microcode */ + "01234567890" /* human readable version device specific code */ + }, + { + { /* DRXVersion_t for microcode */ + DRX_MODULE_UNKNOWN, + (char*)(NULL), + 0, + 0, + 0, + (char*)(NULL) + }, + { /* DRXVersion_t for device specific code */ + DRX_MODULE_UNKNOWN, + (char*)(NULL), + 0, + 0, + 0, + (char*)(NULL) + } + }, + { + { /* DRXVersionList_t for microcode */ + (pDRXVersion_t)(NULL), + (pDRXVersionList_t)(NULL) + }, + { /* DRXVersionList_t for device specific code */ + (pDRXVersion_t)(NULL), + (pDRXVersionList_t)(NULL) + } + }, +#endif + FALSE, /* smartAntInverted */ + /* Tracking filter setting for OOB */ + { + 12000, + 9300, + 6600, + 5280, + 3700, + 3000, + 2000, + 0 + }, + FALSE, /* oobPowerOn */ + 0, /* mpegTsStaticBitrate */ + FALSE, /* disableTEIhandling */ + FALSE, /* bitReverseMpegOutout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */ + + /* Pre SAW & Agc configuration for ATV */ + { + DRX_STANDARD_NTSC, /* standard */ + 7, /* reference */ + TRUE /* usePreSaw */ + }, + { /* ATV RF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 9500, /* top */ + 4000 /* cut-off current */ + }, + { /* ATV IF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrlMode */ + 0, /* outputLevel */ + 0, /* minOutputLevel (d.c.) */ + 0, /* maxOutputLevel (d.c.) */ + 3, /* speed */ + 2400, /* top */ + 0 /* c.o.c. (d.c.) */ + }, + 140, /* ATV PGA config */ + 0, /* currSymbolRate */ + + FALSE, /* pdrSafeMode */ + SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdrSafeRestoreValSmaTx */ + + 4, /* oobPreSaw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */ + { + FALSE /* audData, only first member */ + }, +}; + + +/** +* \var DRXJDefaultAddr_g +* \brief Default I2C address and device identifier. +*/ +I2CDeviceAddr_t DRXJDefaultAddr_g = { + DRXJ_DEF_I2C_ADDR, /* i2c address */ + DRXJ_DEF_DEMOD_DEV_ID /* device id */ +}; + +/** +* \var DRXJDefaultCommAttr_g +* \brief Default common attributes of a drxj demodulator instance. +*/ +DRXCommonAttr_t DRXJDefaultCommAttr_g = { + (pu8_t)NULL, /* ucode ptr */ + 0, /* ucode size */ + TRUE, /* ucode verify switch */ + { 0 }, /* version record */ + + 44000, /* IF in kHz in case no tuner instance is used */ + (151875-0), /* system clock frequency in kHz */ + 0, /* oscillator frequency kHz */ + 0, /* oscillator deviation in ppm, signed */ + FALSE, /* If TRUE mirror frequency spectrum */ + { + /* MPEG output configuration */ + TRUE, /* If TRUE, enable MPEG ouput */ + FALSE, /* If TRUE, insert RS byte */ + TRUE, /* If TRUE, parallel out otherwise serial */ + FALSE, /* If TRUE, invert DATA signals */ + FALSE, /* If TRUE, invert ERR signal */ + FALSE, /* If TRUE, invert STR signals */ + FALSE, /* If TRUE, invert VAL signals */ + FALSE, /* If TRUE, invert CLK signals */ + TRUE, /* If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + 19392658UL, /* Maximum bitrate in b/s in case + static clockrate is selected */ + DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ + }, + /* Initilisations below can be ommited, they require no user input and + are initialy 0, NULL or FALSE. The compiler will initialize them to these + values when ommited. */ + FALSE, /* isOpened */ + + /* SCAN */ + NULL, /* no scan params yet */ + 0, /* current scan index */ + 0, /* next scan frequency */ + FALSE, /* scan ready flag */ + 0, /* max channels to scan */ + 0, /* nr of channels scanned */ + NULL, /* default scan function */ + NULL, /* default context pointer */ + 0, /* millisec to wait for demod lock */ + DRXJ_DEMOD_LOCK, /* desired lock */ + FALSE, + + /* Power management */ + DRX_POWER_UP, + + /* Tuner */ + 1, /* nr of I2C port to wich tuner is */ + 0L, /* minimum RF input frequency, in kHz */ + 0L, /* maximum RF input frequency, in kHz */ + FALSE, /* Rf Agc Polarity */ + FALSE, /* If Agc Polarity */ + FALSE, /* tuner slow mode */ + + + { /* current channel (all 0) */ + 0UL /* channel.frequency */ + }, + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_STANDARD_UNKNOWN, /* previous standard */ + DRX_STANDARD_UNKNOWN, /* diCacheStandard */ + FALSE, /* useBootloader */ + 0UL, /* capabilities */ + 0 /* mfx */ + +}; + +/** +* \var DRXJDefaultDemod_g +* \brief Default drxj demodulator instance. +*/ +DRXDemodInstance_t DRXJDefaultDemod_g = { + &DRXJFunctions_g, /* demod functions */ + &DRXJ_DAP, /* data access protocol functions */ + NULL, /* tuner instance */ + &DRXJDefaultAddr_g, /* i2c address & device id */ + &DRXJDefaultCommAttr_g, /* demod common attributes */ + &DRXJData_g /* demod device specific attributes */ +}; + +/** +* \brief Default audio data structure for DRK demodulator instance. +* +* This structure is DRXK specific. +* +*/ +DRXAudData_t DRXJDefaultAudData_g = +{ + FALSE, /* audioIsActive */ + DRX_AUD_STANDARD_AUTO, /* audioStandard */ + + /* i2sdata */ + { + FALSE, /* outputEnable */ + 48000, /* frequency */ + DRX_I2S_MODE_MASTER, /* mode */ + DRX_I2S_WORDLENGTH_32, /* wordLength */ + DRX_I2S_POLARITY_RIGHT, /* polarity */ + DRX_I2S_FORMAT_WS_WITH_DATA /* format */ + }, + /* volume */ + { + TRUE, /* mute; */ + 0, /* volume */ + DRX_AUD_AVC_OFF , /* avcMode */ + 0, /* avcRefLevel */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avcMaxGain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avcMaxAtten */ + 0, /* strengthLeft */ + 0 /* strengthRight */ + }, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,/* autoSound */ + /* assThresholds */ + { + 440, /* A2 */ + 12, /* BTSC */ + 700, /* NICAM */ + }, + /* carrier */ + { + /* a */ + { + 42, /* thres */ + DRX_NO_CARRIER_NOISE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + /* b */ + { + 42, /* thres */ + DRX_NO_CARRIER_MUTE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + + }, + /* mixer */ + { + DRX_AUD_SRC_STEREO_OR_A, /* sourceI2S */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrixI2S */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrixFm */ + }, + DRX_AUD_DEVIATION_NORMAL, /* deviation */ + DRX_AUD_AVSYNC_OFF, /* avSync */ + + /* prescale */ + { + DRX_AUD_MAX_FM_DEVIATION, /* fmDeviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicamGain */ + }, + DRX_AUD_FM_DEEMPH_75US, /* deemph */ + DRX_BTSC_STEREO, /* btscDetect */ + 0, /* rdsDataCounter */ + FALSE /* rdsDataPresent */ +}; + + +/*----------------------------------------------------------------------------- +STRUCTURES +----------------------------------------------------------------------------*/ +typedef struct { + u16_t eqMSE; + u8_t eqMode; + u8_t eqCtrl; + u8_t eqStat; +} DRXJEQStat_t, *pDRXJEQStat_t; + +/* HI command */ +typedef struct { + u16_t cmd; + u16_t param1; + u16_t param2; + u16_t param3; + u16_t param4; + u16_t param5; + u16_t param6; +} DRXJHiCmd_t, *pDRXJHiCmd_t; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ +/*=== MICROCODE RELATED STRUCTURES ===========================================*/ +/*============================================================================*/ + +typedef struct { + u32_t addr; + u16_t size; + u16_t flags; /* bit[15..2]=reserved, + bit[1]= compression on/off + bit[0]= CRC on/off */ + u16_t CRC; +} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*----------------------------------------------------------------------------- +FUNCTIONS +----------------------------------------------------------------------------*/ +/* Some prototypes */ +static DRXStatus_t +HICommand(const pI2CDeviceAddr_t devAddr, + const pDRXJHiCmd_t cmd, + pu16_t result); + +static DRXStatus_t +CtrlLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ); + +static DRXStatus_t +CtrlPowerMode( pDRXDemodInstance_t demod, + pDRXPowerMode_t mode ); + +static DRXStatus_t +PowerDownAud( pDRXDemodInstance_t demod ); + +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +PowerUpAud( pDRXDemodInstance_t demod, + Bool_t setStandard ); +#endif + +static DRXStatus_t +AUDCtrlSetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ); + +static DRXStatus_t +CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ); + +static DRXStatus_t +CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ); + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +static DRXStatus_t +CtrlUCodeUpload( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, + Bool_t audioMCUpload ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*============================================================================*/ +/*============================================================================*/ +/*== HELPER FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +* \brief 32bitsx32bits signed multiplication +* \param a 32 bits multiplicant, typecast from signed to unisgned +* \param b 32 bits multiplier, typecast from signed to unisgned +* \param h pointer to high part 64 bits result, typecast from signed to unisgned +* \param l pointer to low part 64 bits result +* +* For the 2n+n addition a + b: +* if a >= 0, then h += 0 (sign extension = 0) +* but if a < 0, then h += 2^n-1 ==> h -= 1. +* +* Also, if a + b < 2^n, then a + b >= a && a + b >= b +* but if a + b >= 2^n, then R = a + b - 2^n, +* and because a < 2^n && b < 2*n ==> R < a && R < b. +* Therefore, to detect overflow, simply compare the addition result with +* one of the operands; if the result is smaller, overflow has occurred and +* h must be incremented. +* +* Booth multiplication uses additions and subtractions to reduce the number +* of iterations. This is done by taking three subsequent bits abc and calculating +* the following multiplication factor: -2a + b + c. This factor is multiplied +* by the second operand and added to the result. Next, the first operand is +* shifted two bits (hence one of the three bits is reused) and the process +* repeated. The last iteration has only two bits left, but we simply add +* a zero to the end. +* +* Hence: (n=4) +* 1 * a = 0 * 4a + 1 * a +* 2 * a = 1 * 4a - 2 * a +* 3 * a = 1 * 4a - 1 * a +* -1 * a = 0 * 4a - 1 * a +* -5 * a = -1 * 4a - 1 * a +* +* etc. +* +* Note that the function is type size independent. Any unsigned integer type +* can be substituted for booth_t. +* +*/ + +#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32_t) * 8 - 1))) != 0) + +static void Mult32(u32_t a, u32_t b, pu32_t h, pu32_t l) +{ + unsigned int i; + *h = *l = 0; + + /* n/2 iterations; shift operand a left two bits after each iteration. */ + /* This automatically appends a zero to the operand for the last iteration. */ + for (i = 0; i < sizeof (a) * 8; i += 2, a = a << 2) + { + /* Shift result left two bits */ + *h = (*h << 2) + (*l >> (sizeof (*l) * 8 - 2)); + *l = (*l << 2); + + /* Take the first three bits of operand a for the Booth conversion: */ + /* 0, 7: do nothing */ + /* 1, 2: add b */ + /* 3 : add 2b */ + /* 4 : subtract 2b */ + /* 5, 6: subtract b */ + switch (a >> (sizeof (a) * 8 - 3)) + { + case 3: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); + case 1: + case 2: + *l += b; + *h = *h - DRX_IS_BOOTH_NEGATIVE (b) + (*l < b); + break; + case 4: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); + case 5: + case 6: + *l -= b; + *h = *h - !DRX_IS_BOOTH_NEGATIVE (b) + !b + (*l < ((u32_t) (-((s32_t)b))) ); + break; + } + } +} + +/*============================================================================*/ + +/* +* \fn u32_t Frac28(u32_t N, u32_t D) +* \brief Compute: (1<<28)*N/D +* \param N 32 bits +* \param D 32 bits +* \return (1<<28)*N/D +* This function is used to avoid floating-point calculations as they may +* not be present on the target platform. + +* Frac28 performs an unsigned 28/28 bits division to 32-bit fixed point +* fraction used for setting the Frequency Shifter registers. +* N and D can hold numbers up to width: 28-bits. +* The 4 bits integer part and the 28 bits fractional part are calculated. + +* Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999 + +* N: 0...(1<<28)-1 = 268435454 +* D: 0...(1<<28)-1 +* Q: 0...(1<<32)-1 +*/ +static u32_t Frac28(u32_t N, u32_t D) +{ + int i=0; + u32_t Q1=0; + u32_t R0=0; + + R0 = (N%D)<<4; /* 32-28 == 4 shifts possible at max */ + Q1 = N/D; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i=0; i<7; i++) { + Q1 = (Q1 << 4) | R0/D; + R0 = (R0%D)<<4; + } + /* rounding */ + if ((R0>>3) >= D) Q1++; + + return Q1; +} + +/** +* \fn u32_t Log10Times100( u32_t x) +* \brief Compute: 100*log10(x) +* \param x 32 bits +* \return 100*log10(x) +* +* 100*log10(x) +* = 100*(log2(x)/log2(10))) +* = (100*(2^15)*log2(x))/((2^15)*log2(10)) +* = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2 +* +* where y = 2^k and 1<= (x/y) < 2 +*/ + +static u32_t Log10Times100( u32_t x) +{ + static const u8_t scale=15; + static const u8_t indexWidth=5; + /* + log2lut[n] = (1<0 ; k--) + { + if (x & (((u32_t)1)<>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ( ( ((u32_t)1) << scale ) * 200 ); + + /* remove integer part */ + x &= ((((u32_t)1) << scale)-1); + /* get index */ + i = (u8_t) (x >> (scale -indexWidth)); + /* compute delta (x-a) */ + d = x & ((((u32_t)1) << (scale-indexWidth))-1); + /* compute log, multiplication ( d* (.. )) must be within range ! */ + y += log2lut[i] + (( d*( log2lut[i+1]-log2lut[i] ))>>(scale-indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y>>1); + /* rounding */ + if (y&((u32_t)1)) r++; + + return (r); + +} + +/** +* \fn u32_t FracTimes1e6( u16_t N, u32_t D) +* \brief Compute: (N/D) * 1000000. +* \param N nominator 16-bits. +* \param D denominator 32-bits. +* \return u32_t +* \retval ((N/D) * 1000000), 32 bits +* +* No check on D=0! +*/ +static u32_t FracTimes1e6( u32_t N, u32_t D) +{ + u32_t remainder = 0; + u32_t frac = 0; + + /* + frac = (N * 1000000) / D + To let it fit in a 32 bits computation: + frac = (N * (1000000 >> 4)) / (D >> 4) + This would result in a problem in case D < 16 (div by 0). + So we do it more elaborate as shown below. + */ + frac = ( ((u32_t)N) * (1000000 >> 4) ) / D ; + frac <<= 4 ; + remainder = ( ((u32_t)N) * (1000000 >> 4) ) % D ; + remainder <<= 4; + frac += remainder / D; + remainder = remainder % D ; + if( (remainder * 2) > D ) + { + frac++; + } + + return ( frac ); +} + +/*============================================================================*/ + +/** +* \brief Compute: 100 * 10^( GdB / 200 ). +* \param u32_t GdB Gain in 0.1dB +* \return u32_t Gainfactor in 0.01 resolution +* +*/ +static u32_t dB2LinTimes100( u32_t GdB ) +{ + u32_t result = 0; + u32_t nr6dBSteps = 0; + u32_t remainder = 0; + u32_t remainderFac = 0; + + /* start with factors 2 (6.02dB) */ + nr6dBSteps = GdB * 1000UL / 60206UL; + if ( nr6dBSteps > 17 ) + { + /* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */ + return MAX_U32; + } + result = (1< N ) + { + frac = 0; + remainder = N; + } + else + { + remainder = 0; + frac = N; + while ( bitCnt-- > 0 ) + { + remainder <<= 1; + remainder |= ( ( frac & 0x80000000 ) >> 31 ); + frac <<= 1; + if ( remainder < D ) + { + frac &= 0xFFFFFFFE; + } + else + { + remainder -= D; + frac |= 0x1; + } + } + + /* result correction if needed */ + if ( ( RC == FRAC_CEIL ) && ( remainder != 0 ) ) + { + /* ceil the result */ + /*(remainder is not zero -> value behind decimal point exists) */ + frac++; + } + if ( ( RC == FRAC_ROUND ) && ( remainder >= D>>1 ) ) + { + /* remainder is bigger from D/2 -> round the result */ + frac++; + } + } + + return ( frac ); +} +#endif + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ + +/** +* \fn u16_t UCodeRead16( pu8_t addr) +* \brief Read a 16 bits word, expect big endian data. +* \return u16_t The data read. +*/ +static u16_t +UCodeRead16( pu8_t addr) +{ + /* Works fo any host processor */ + + u16_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |=((u16_t)addr[1]); + + return ( word ); +} + +/*============================================================================*/ + +/** +* \fn u32_t UCodeRead32( pu8_t addr) +* \brief Read a 32 bits word, expect big endian data. +* \return u32_t The data read. +*/ +static u32_t +UCodeRead32( pu8_t addr) +{ + /* Works fo any host processor */ + + u32_t word=0; + + word = ((u16_t)addr[0]); + word <<= 8; + word |= ((u16_t)addr[1]); + word <<= 8; + word |= ((u16_t)addr[2]); + word <<= 8; + word |= ((u16_t)addr[3]); + + return ( word ); +} + +/*============================================================================*/ + +/** +* \fn u16_t UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +* \brief Compute CRC of block of microcode data. +* \param blockData Pointer to microcode data. +* \param nrWords Size of microcode block (number of 16 bits words). +* \return u16_t The computed CRC residu. +*/ +static u16_t +UCodeComputeCRC (pu8_t blockData, u16_t nrWords) +{ + u16_t i = 0; + u16_t j = 0; + u32_t CRCWord=0; + u32_t carry=0; + + while (i < nrWords) { + CRCWord |= (u32_t) UCodeRead16(blockData); + for (j = 0; j < 16; j++) + { + CRCWord <<= 1; + if (carry != 0) + CRCWord ^= 0x80050000UL; + carry = CRCWord & 0x80000000UL; + } + i++; + blockData+=(sizeof(u16_t)); + } + return ((u16_t) (CRCWord >> 16)); +} +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/** +* \brief Values for NICAM prescaler gain. Computed from dB to integer +* and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). +* +*/ +static const u16_t NicamPrescTableVal[43] = { 1,1,1,1,2,2,2,2,3,3,3,4,4, + 5,5,6,6,7,8,9,10,11,13,14,16, + 18,20,23,25,28,32,36,40,45, + 51,57,64,71,80,90,101,113,127 + }; + +/*============================================================================*/ +/*== END HELPER FUNCTIONS ==*/ +/*============================================================================*/ + + +/*============================================================================*/ +/*============================================================================*/ +/*== DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + This layer takes care of some device specific register access protocols: + -conversion to short address format + -access to audio block + This layer is placed between the drx_dap_fasi and the rest of the drxj + specific implementation. This layer can use address map knowledge whereas + dap_fasi may not use memory map knowledge. + + * For audio currently only 16 bits read and write register access is + supported. More is not needed. RMW and 32 or 8 bit access on audio + registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast + single/multi master) will be ignored. + + + TODO: check ignoring single/multimaster is ok for AUD access ? +*/ + +#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?TRUE:FALSE) +#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ +/*============================================================================*/ + +/** +* \fn Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +* \brief Check if this address is handled by the audio token ring interface. +* \param addr +* \return Bool_t +* \retval TRUE Yes, handled by audio token ring interface +* \retval FALSE No, not handled by audio token ring interface +* +*/ +static +Bool_t IsHandledByAudTrIf( DRXaddr_t addr ) +{ + Bool_t retval = FALSE; + + if ( (DRXDAP_FASI_ADDR2BLOCK( addr ) == 4) && + ( DRXDAP_FASI_ADDR2BANK( addr) > 1 ) && + ( DRXDAP_FASI_ADDR2BANK( addr) < 6 ) ) + { + retval=TRUE; + } + + return (retval); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readBlockFunc( devAddr, + addr, + datasize, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u8_t wdata, + pu8_t rdata) +{ + return drxDapFASIFunct_g.readModifyWriteReg8Func( devAddr, + waddr, + raddr, + wdata, + rdata); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_RMWriteReg16Short +* \brief Read modify write 16 bits audio register using short format only. +* \param devAddr +* \param waddr Address to write to +* \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) +* \param wdata Data to write +* \param rdata Buffer for data to read +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register read modify write access using short addressing format only. +* Requires knowledge of the registermap, thus device dependent. +* Using DAP FASI directly to avoid endless recursion of RMWs to audio registers. +* +*/ + +/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + See comments DRXJ_DAP_ReadModifyWriteReg16 */ +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 ) +static DRXStatus_t DRXJ_DAP_RMWriteReg16Short ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata) +{ + DRXStatus_t rc; + + if (rdata == NULL) + { + return DRX_STS_INVALID_ARG; + } + + /* Set RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, + 0x0000); + if (rc == DRX_STS_OK) + { + /* Write new data: triggers RMW */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, waddr, wdata, 0x0000 ); + } + if (rc == DRX_STS_OK) + { + /* Read old data */ + rc = drxDapFASIFunct_g.readReg16Func (devAddr, raddr, rdata, 0x0000 ); + } + if (rc == DRX_STS_OK) + { + /* Reset RMW flag */ + rc = drxDapFASIFunct_g.writeReg16Func (devAddr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + 0, + 0x0000); + } + + return rc; +} +#endif + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u16_t wdata, + pu16_t rdata) +{ + /* TODO: correct short/long addressing format decision, + now long format has higher prio then short because short also + needs virt bnks (not impl yet) for certain audio registers */ +#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) + return drxDapFASIFunct_g.readModifyWriteReg16Func( devAddr, + waddr, + raddr, + wdata, + rdata); +#else + return DRXJ_DAP_RMWriteReg16Short( devAddr, + waddr, + raddr, + wdata, + rdata); +#endif +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadModifyWriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t waddr, + DRXaddr_t raddr, + u32_t wdata, + pu32_t rdata) +{ + return drxDapFASIFunct_g.readModifyWriteReg32Func( devAddr, + waddr, + raddr, + wdata, + rdata); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readReg8Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_ReadAudReg16 +* \brief Read 16 bits audio register +* \param devAddr +* \param addr +* \param data +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register read access via audio token ring interface. +* +*/ +static DRXStatus_t DRXJ_DAP_ReadAudReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data) +{ + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + DRXStatus_t stat = DRX_STS_ERROR; + + /* No read possible for bank 3, return with error */ + if ( DRXDAP_FASI_ADDR2BANK(addr) == 3 ) + { + stat=DRX_STS_INVALID_ARG; + } else { + const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; + + /* Force reset write bit */ + addr &= (~writeBit); + + /* Set up read */ + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, + &trStatus); + + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + + } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || + ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ + + /* Wait for read ready status or timeout */ + if ( stat == DRX_STS_OK ) + { + startTimer = DRXBSP_HST_Clock(); + + while ( ( trStatus & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) + { + stat = DRXJ_DAP_ReadReg16( devAddr, + AUD_TOP_TR_CTR__A, + &trStatus, + 0x0000); + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + } /* while ( ... ) */ + } /* if { stat == DRX_STS_OK ) */ + + /* Read value */ + if ( stat == DRX_STS_OK ) + { + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + AUD_TOP_TR_RD_REG__A, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, + data); + } /* if { stat == DRX_STS_OK ) */ + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags) +{ + DRXStatus_t stat = DRX_STS_ERROR; + + /* Check param */ + if ( ( devAddr == NULL ) || ( data == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + if ( IsHandledByAudTrIf(addr) ) + { + stat = DRXJ_DAP_ReadAudReg16 (devAddr, + addr, + data); + } else { + stat = drxDapFASIFunct_g.readReg16Func( devAddr, + addr, + data, + flags); + } + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_ReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.readReg32Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeBlockFunc( devAddr, + addr, + datasize, + data, + flags); +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg8 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u8_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeReg8Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_WriteAudReg16 +* \brief Write 16 bits audio register +* \param devAddr +* \param addr +* \param data +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +* 16 bits register write access via audio token ring interface. +* +*/ +static DRXStatus_t DRXJ_DAP_WriteAudReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data) +{ + DRXStatus_t stat = DRX_STS_ERROR; + + /* No write possible for bank 2, return with error */ + if ( DRXDAP_FASI_ADDR2BANK(addr) == 2 ) + { + stat=DRX_STS_INVALID_ARG; + } else { + u32_t startTimer = 0; + u32_t currentTimer = 0; + u32_t deltaTimer = 0; + u16_t trStatus = 0; + const DRXaddr_t writeBit = ((DRXaddr_t)1)<<16; + + /* Force write bit */ + addr |= writeBit; + startTimer = DRXBSP_HST_Clock(); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = DRXJ_DAP_ReadModifyWriteReg16( devAddr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + data, + &trStatus); + if ( stat != DRX_STS_OK ) + { + break; + }; + + currentTimer = DRXBSP_HST_Clock(); + deltaTimer = currentTimer - startTimer; + if ( deltaTimer > DRXJ_DAP_AUDTRIF_TIMEOUT ) + { + stat = DRX_STS_ERROR; + break; + }; + + } while ( ( ( trStatus & AUD_TOP_TR_CTR_FIFO_LOCK__M ) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED ) || + ( ( trStatus & AUD_TOP_TR_CTR_FIFO_FULL__M ) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL ) ); + + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags) +{ + DRXStatus_t stat=DRX_STS_ERROR; + + /* Check param */ + if ( devAddr == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + + if ( IsHandledByAudTrIf(addr) ) + { + stat = DRXJ_DAP_WriteAudReg16 (devAddr, + addr, + data); + } else { + stat = drxDapFASIFunct_g.writeReg16Func( devAddr, + addr, + data, + flags); + } + + return stat; +} + +/*============================================================================*/ + +static DRXStatus_t DRXJ_DAP_WriteReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u32_t data, + DRXflags_t flags) +{ + return drxDapFASIFunct_g.writeReg32Func( devAddr, + addr, + data, + flags); +} + +/*============================================================================*/ + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock() +* \brief Basic access routine for atomic read or write access +* \param devAddr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +*/ +static +DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, + pu8_t data, + Bool_t readFlag) +{ + DRXJHiCmd_t hiCmd; + + u16_t word; + u16_t dummy=0; + u16_t i=0; + + /* Parameter check */ + if ( ( data == NULL ) || + ( devAddr == NULL ) || + ( (datasize%2)!= 0 ) || + ( (datasize/2) > 8 ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + /* Set up HI parameters to read or write n bytes */ + hiCmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hiCmd.param1 = + (u16_t)(( DRXDAP_FASI_ADDR2BLOCK( DRXJ_HI_ATOMIC_BUF_START ) << 6 ) + + DRXDAP_FASI_ADDR2BANK( DRXJ_HI_ATOMIC_BUF_START ) ); + hiCmd.param2 = (u16_t)DRXDAP_FASI_ADDR2OFFSET( DRXJ_HI_ATOMIC_BUF_START ); + hiCmd.param3 = (u16_t)((datasize/2) - 1); + if ( readFlag == FALSE ) + { + hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + } else { + hiCmd.param3 |= DRXJ_HI_ATOMIC_READ; + } + hiCmd.param4 = (u16_t) ( ( DRXDAP_FASI_ADDR2BLOCK(addr) << 6 ) + + DRXDAP_FASI_ADDR2BANK(addr) ); + hiCmd.param5 = (u16_t)DRXDAP_FASI_ADDR2OFFSET(addr); + + if ( readFlag == FALSE ) + { + /* write data to buffer */ + for (i = 0; i < (datasize/2); i++) + { + + + word = ((u16_t)data[2*i]); + word += (((u16_t)data[(2*i)+1])<<8); + DRXJ_DAP_WriteReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), word, 0); + } + } + + CHK_ERROR( HICommand( devAddr, &hiCmd, &dummy) ); + + if ( readFlag == TRUE ) + { + /* read data from buffer */ + for (i = 0; i < (datasize/2); i++) + { + DRXJ_DAP_ReadReg16 (devAddr, (DRXJ_HI_ATOMIC_BUF_START + i), &word, 0); + data[2*i] = (u8_t) (word & 0xFF); + data[(2*i) + 1] = (u8_t) (word >> 8 ); + } + } + + return DRX_STS_OK; + + rw_error: + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg32() +* \brief Atomic read of 32 bits words +*/ +static +DRXStatus_t DRXJ_DAP_AtomicReadReg32 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu32_t data, + DRXflags_t flags) +{ + u8_t buf[sizeof (*data)]; + DRXStatus_t rc = DRX_STS_ERROR; + u32_t word = 0; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXJ_DAP_AtomicReadWriteBlock ( devAddr, addr, + sizeof (*data), buf, TRUE); + + word = (u32_t)buf[3]; + word <<= 8; + word |= (u32_t)buf[2]; + word <<= 8; + word |= (u32_t)buf[1]; + word <<= 8; + word |= (u32_t)buf[0]; + + *data = word; + + return rc; +} + + +/*============================================================================*/ + + +/*============================================================================*/ +/*== END DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t HICfgCommand() +* \brief Configure HI with settings stored in the demod structure. +* \param demod Demodulator. +* \return DRXStatus_t. +* +* This routine was created because to much orthogonal settings have +* been put into one HI API function (configure). Especially the I2C bridge +* enable/disable should not need re-configuration of the HI. +* +*/ +static DRXStatus_t +HICfgCommand(const pDRXDemodInstance_t demod) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + DRXJHiCmd_t hiCmd; + u16_t result=0; + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + hiCmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hiCmd.param2 = extAttr -> HICfgTimingDiv; + hiCmd.param3 = extAttr -> HICfgBridgeDelay; + hiCmd.param4 = extAttr -> HICfgWakeUpKey; + hiCmd.param5 = extAttr -> HICfgCtrl; + hiCmd.param6 = extAttr -> HICfgTransmit; + + CHK_ERROR( HICommand( demod -> myI2CDevAddr, &hiCmd, &result) ); + + /* Reset power down flag (set one call only) */ + extAttr -> HICfgCtrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t HICommand() +* \brief Configure HI with settings stored in the demod structure. +* \param devAddr I2C address. +* \param cmd HI command. +* \param result HI command result. +* \return DRXStatus_t. +* +* Sends command to HI +* +*/ +static DRXStatus_t +HICommand(const pI2CDeviceAddr_t devAddr, + const pDRXJHiCmd_t cmd, + pu16_t result) +{ + u16_t waitCmd=0; + u16_t nrRetries = 0; + Bool_t powerdown_cmd = FALSE; + + + /* Write parameters */ + switch ( cmd->cmd ) { + + case SIO_HI_RA_RAM_CMD_CONFIG: + case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: + WR16(devAddr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6); + WR16(devAddr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5); + WR16(devAddr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4); + WR16(devAddr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_BRDCTRL: + WR16(devAddr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2); + WR16(devAddr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1); + /* fallthrough */ + case SIO_HI_RA_RAM_CMD_NULL: + /* No parameters */ + break; + + default: + return (DRX_STS_INVALID_ARG); + break; + } + + /* Write command */ + WR16(devAddr, SIO_HI_RA_RAM_CMD__A, cmd->cmd); + + if ( (cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET ) + { + /* Allow for HI to reset */ + DRXBSP_HST_Sleep(1); + } + + /* Detect power down to ommit reading result */ + powerdown_cmd = (Bool_t)( ( cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG ) && + ( ((cmd->param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ) ); + if ( powerdown_cmd == FALSE ) + { + /* Wait until command rdy */ + do + { + nrRetries++; + if ( nrRetries > DRXJ_MAX_RETRIES ) + { + goto rw_error; + }; + + RR16(devAddr, SIO_HI_RA_RAM_CMD__A, &waitCmd); + } while ( waitCmd != 0 ); + + /* Read result */ + RR16(devAddr, SIO_HI_RA_RAM_RES__A, result); + + } /* if ( powerdown_cmd == TRUE ) */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t InitHI( const pDRXDemodInstance_t demod ) +* \brief Initialise and configurate HI. +* \param demod pointer to demod data. +* \return DRXStatus_t Return status. +* \retval DRX_STS_OK Success. +* \retval DRX_STS_ERROR Failure. +* +* Needs to know Psys (System Clock period) and Posc (Osc Clock period) +* Need to store configuration in driver because of the way I2C +* bridging is controlled. +* +*/ +static DRXStatus_t +InitHI( const pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr =(pDRXJData_t)(NULL); + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + + /* PATCH for bug 5003, HI ucode v3.1.0 */ + WR16( devAddr, 0x4301D7, 0x801 ); + + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + extAttr -> HICfgTimingDiv = + (u16_t)((commonAttr->sysClockFreq/1000)* HI_I2C_DELAY)/1000 ; + /* Clipping */ + if ( (extAttr -> HICfgTimingDiv) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M ) + { + extAttr -> HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + } + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + /* SDA brdige delay */ + extAttr -> HICfgBridgeDelay = + (u16_t)((commonAttr->oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000 ; + /* Clipping */ + if ( (extAttr -> HICfgBridgeDelay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M ) + { + extAttr -> HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + extAttr -> HICfgBridgeDelay += ((extAttr -> HICfgBridgeDelay)<< + SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); + /* Wakeup key, setting the read flag (as suggest in the documentation) does + not always result into a working solution (barebones worked VI2C failed). + Not setting the bit works in all cases . */ + extAttr -> HICfgWakeUpKey = DRXJ_WAKE_UP_KEY; + /* port/bridge/power down ctrl */ + extAttr -> HICfgCtrl = ( SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE ); + /* transit mode time out delay and watch dog divider */ + extAttr ->HICfgTransmit = SIO_HI_RA_RAM_PAR_6__PRE; + + CHK_ERROR( HICfgCommand( demod ) ); + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + + +/*============================================================================*/ +/*== END HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t GetDeviceCapabilities() +* \brief Get and store device capabilities. +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \return DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure +* +* Depending on pulldowns on MDx pins the following internals are set: +* * commonAttr->oscClockFreq +* * extAttr->hasLNA +* * extAttr->hasNTSC +* * extAttr->hasBTSC +* * extAttr->hasOOB +* +*/ +static DRXStatus_t +GetDeviceCapabilities( pDRXDemodInstance_t demod ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t sioPdrOhwCfg = 0; + u32_t sioTopJtagidLo = 0; + u16_t bid = 0; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + devAddr = demod -> myI2CDevAddr; + + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); + RR16 ( devAddr, SIO_PDR_OHW_CFG__A , &sioPdrOhwCfg); + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); + + switch ( (sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M ) ) + { + case 0: + /* ignore (bypass ?)*/ + break; + case 1: + /* 27 MHz */ + commonAttr->oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + commonAttr->oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + commonAttr->oscClockFreq = 4000; + break; + default: + return (DRX_STS_ERROR); + } + + /* + Determine device capabilities + Based on pinning v47 + */ + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo); + extAttr->mfx = (u8_t)((sioTopJtagidLo>>29)&0xF) ; + + switch ((sioTopJtagidLo>>12)&0xFF) + { + case 0x31: + WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY_KEY); + RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); + bid = (bid >> 10) & 0xf; + WR16( devAddr, SIO_TOP_COMM_KEY__A , SIO_TOP_COMM_KEY__PRE); + + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x33: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = FALSE; + extAttr->hasGPIO = FALSE; + extAttr->hasIRQN = FALSE; + break; + case 0x45: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x46: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x41: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x43: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = FALSE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = FALSE; + break; + case 0x32: + extAttr->hasLNA = TRUE; + extAttr->hasNTSC = FALSE; + extAttr->hasBTSC = FALSE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x34: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x42: + extAttr->hasLNA = TRUE ; + extAttr->hasNTSC = TRUE ; + extAttr->hasBTSC = TRUE ; + extAttr->hasOOB = TRUE ; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + case 0x44: + extAttr->hasLNA = FALSE; + extAttr->hasNTSC = TRUE; + extAttr->hasBTSC = TRUE; + extAttr->hasOOB = TRUE; + extAttr->hasSMATX = TRUE; + extAttr->hasSMARX = TRUE; + extAttr->hasGPIO = TRUE; + extAttr->hasIRQN = TRUE; + break; + default: + /* Unknown device variant */ + return (DRX_STS_ERROR); + break; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + + +/** +* \fn DRXStatus_t PowerUpDevice() +* \brief Power up device. +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \return DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure, I2C or max retries reached +* +*/ + +#ifndef DRXJ_MAX_RETRIES_POWERUP +#define DRXJ_MAX_RETRIES_POWERUP 10 +#endif + +static DRXStatus_t +PowerUpDevice( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + u8_t data = 0 ; + u16_t retryCount = 0; + I2CDeviceAddr_t wakeUpAddr; + + devAddr = demod->myI2CDevAddr; + wakeUpAddr.i2cAddr = DRXJ_WAKE_UP_KEY; + wakeUpAddr.i2cDevId = devAddr->i2cDevId; + wakeUpAddr.userData = devAddr->userData; + /* CHK_ERROR macro not used, I2C access may fail in this case: no ack + dummy write must be used to wake uop device, dummy read must be used to + reset HI state machine (avoiding actual writes) */ + do + { + data = 0; + DRXBSP_I2C_WriteRead( &wakeUpAddr, 1, &data, + (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL) ); + DRXBSP_HST_Sleep(10); + retryCount++ ; + }while ( (DRXBSP_I2C_WriteRead( (pI2CDeviceAddr_t)(NULL), 0, (pu8_t)(NULL), + devAddr, 1, &data ) + != DRX_STS_OK ) && + (retryCount < DRXJ_MAX_RETRIES_POWERUP) ); + + /* Need some recovery time .... */ + DRXBSP_HST_Sleep(10); + + if ( retryCount == DRXJ_MAX_RETRIES_POWERUP ) + { + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetCfgMPEGOutput() +* \brief Set MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to mpeg output configuaration. +* \return DRXStatus_t. +* +* Configure MPEG output parameters. +* +*/ +static DRXStatus_t +CtrlSetCfgMPEGOutput( pDRXDemodInstance_t demod, + pDRXCfgMPEGOutput_t cfgData ) +{ + pI2CDeviceAddr_t devAddr =(pI2CDeviceAddr_t)(NULL); + pDRXJData_t extAttr =(pDRXJData_t)(NULL); + pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL); + u16_t fecOcRegMode = 0; + u16_t fecOcRegIprMode = 0; + u16_t fecOcRegIprInvert = 0; + u32_t maxBitRate = 0; + u32_t rcnRate = 0; + u32_t nrBits = 0; + u16_t sioPdrMdCfg = 0; + /* data mask for the output data byte */ + u16_t InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + /* check arguments */ + if (( demod == NULL ) || + ( cfgData == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + if ( cfgData->enableMPEGOutput == TRUE ) + { + /* quick and dirty patch to set MPEG incase current std is not + producing MPEG */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + break; + default: + /* not an MPEG producing std, just store MPEG cfg */ + commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + return (DRX_STS_OK); + } + + WR16( devAddr, FEC_OC_OCR_INVERT__A, 0); + switch (extAttr->standard) + { + case DRX_STANDARD_8VSB: + WR16( devAddr, FEC_OC_FCT_USAGE__A, 7 ); /* 2048 bytes fifo ram */ + WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, 10); + WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 10); + WR16( devAddr, FEC_OC_AVR_PARM_A__A, 5); + WR16( devAddr, FEC_OC_AVR_PARM_B__A, 7); + WR16( devAddr, FEC_OC_RCN_GAIN__A, 10); + /* Low Water Mark for synchronization */ + WR16( devAddr, FEC_OC_SNC_LWM__A, 3 ); + /* High Water Mark for synchronization */ + WR16( devAddr, FEC_OC_SNC_HWM__A, 5 ); + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + nrBits = 8; + break; + case DRX_CONSTELLATION_QAM128: + nrBits = 7; + break; + case DRX_CONSTELLATION_QAM64: + nrBits = 6; + break; + case DRX_CONSTELLATION_QAM32: + nrBits = 5; + break; + case DRX_CONSTELLATION_QAM16: + nrBits = 4; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->constellation */ + /* maxBitRate = symbolRate * nrBits * coef */ + /* coef = 188/204 */ + maxBitRate = ( extAttr->currSymbolRate / 8 ) * nrBits * 188; + /* pass through b/c Annex A/c need following settings */ + case DRX_STANDARD_ITU_B: + WR16( devAddr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE); + WR16( devAddr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE); + WR16( devAddr, FEC_OC_TMD_INT_UPD_RATE__A, 5); + WR16( devAddr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE); + WR16( devAddr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE); + if (cfgData->staticCLK == TRUE) + { + WR16( devAddr, FEC_OC_RCN_GAIN__A, 0xD ); + } + else + { + WR16( devAddr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE ); + } + WR16( devAddr, FEC_OC_SNC_LWM__A, 2); + WR16( devAddr, FEC_OC_SNC_HWM__A, 12); + break; + default: + break; + }/* swtich (standard) */ + + /* Check insertion of the Reed-Solomon parity bytes */ + RR16( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); + RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode ); + if ( cfgData->insertRSByte == TRUE ) + { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + rcnRate = 0x004854D3; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode |= FEC_OC_MODE_TRANSPARENT__M; + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x008945E7; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005F64D4; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 188; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } + else /* insertRSByte == FALSE */ + { + /* disable parity symbol forward */ + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + /* MVAL enable during parity bytes */ + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + rcnRate = 0x0041605C; + break; + case DRX_STANDARD_ITU_B: + fecOcRegMode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + rcnRate = 0x0082D6A0; + break; + case DRX_CONSTELLATION_QAM64: + rcnRate = 0x005AEC1A; + break; + default: + return (DRX_STS_ERROR); + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */ + rcnRate = ( Frac28 ( maxBitRate, ( u32_t )( commonAttr->sysClockFreq / 8 ) ) ) / 204; + break; + default: + return (DRX_STS_ERROR); + } /* extAttr->standard */ + } + + if ( cfgData->enableParallel == TRUE ) + { /* MPEG data output is paralel -> clear ipr_mode[0] */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + } + else + { /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + /* Control slective inversion of output bits */ + if ( cfgData->invertDATA == TRUE ) + { + fecOcRegIprInvert |= InvertDataMask; + } + else + { + fecOcRegIprInvert &= (~(InvertDataMask)); + } + + if ( cfgData->invertERR == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + } + + if ( cfgData->invertSTR == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + } + + if ( cfgData->invertVAL == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + } + + if ( cfgData->invertCLK == TRUE ) + { + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + } + else + { + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + } + + if ( cfgData->staticCLK == TRUE ) /* Static mode */ + { + u32_t dtoRate = 0; + u32_t bitRate = 0; + u16_t fecOcDtoBurstLen = 0; + u16_t fecOcDtoPeriod = 0; + + fecOcDtoBurstLen = FEC_OC_DTO_BURST_LEN__PRE; + + switch ( extAttr->standard ) + { + case DRX_STANDARD_8VSB: + fecOcDtoPeriod = 4; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 208; + } + break; + case DRX_STANDARD_ITU_A: + { + u32_t symbolRateTh = 6400000; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 204; + symbolRateTh = 5900000; + } + if ( extAttr->currSymbolRate >= symbolRateTh) + { + fecOcDtoPeriod = 0; + } + else + { + fecOcDtoPeriod = 1; + } + } + break; + case DRX_STANDARD_ITU_B: + fecOcDtoPeriod = 1; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 128; + } + break; + case DRX_STANDARD_ITU_C: + fecOcDtoPeriod = 1; + if ( cfgData->insertRSByte == TRUE ) + { + fecOcDtoBurstLen = 204; + } + break; + default: + return (DRX_STS_ERROR); + } + bitRate = commonAttr->sysClockFreq * 1000 / (fecOcDtoPeriod + 2); + dtoRate = Frac28(bitRate, commonAttr->sysClockFreq * 1000 ); + dtoRate >>= 3; + WR16 ( devAddr, FEC_OC_DTO_RATE_HI__A, (u16_t) ((dtoRate >> 16) & FEC_OC_DTO_RATE_HI__M) ); + WR16 ( devAddr, FEC_OC_DTO_RATE_LO__A, (u16_t) (dtoRate & FEC_OC_DTO_RATE_LO_RATE_LO__M) ); + WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M ); + WR16 ( devAddr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M ); + WR16 ( devAddr, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen ); + if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) + fecOcDtoPeriod = extAttr->mpegOutputClockRate - 1; + WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod ); + } + else /* Dynamic mode */ + { + WR16 ( devAddr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M ); + WR16 ( devAddr, FEC_OC_FCT_MODE__A, 0 ); + } + + WR32 ( devAddr, FEC_OC_RCN_CTL_RATE_LO__A, rcnRate ); + + /* Write appropriate registers with requested configuration */ + WR16 ( devAddr, FEC_OC_MODE__A, fecOcRegMode ); + WR16 ( devAddr, FEC_OC_IPR_MODE__A, fecOcRegIprMode ); + WR16 ( devAddr, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert ); + + /* enabling for both parallel and serial now */ + /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + /* Set MPEG TS pads to outputmode */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, 0x0013); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A, 0x0013); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, + MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B + | 0x03 << SIO_PDR_MCLK_CFG_MODE__B ); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, 0x0013); + sioPdrMdCfg = MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B + |0x03 << SIO_PDR_MD0_CFG_MODE__B; + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + if ( cfgData->enableParallel == TRUE ) + { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */ + sioPdrMdCfg = MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << SIO_PDR_MD0_CFG_DRIVE__B + |0x03 << SIO_PDR_MD0_CFG_MODE__B; + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, sioPdrMdCfg); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, sioPdrMdCfg); + } + else + { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, 0x0000); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, 0x0000); + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16 ( devAddr, SIO_PDR_MON_CFG__A, 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); + } + else + { + /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); + /* Set MPEG TS pads to inputmode */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD0_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A , 0x0000); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A , 0x0000); + /* Enable Monitor Bus output over MPEG pads and ctl input */ + WR16 ( devAddr, SIO_PDR_MON_CFG__A , 0x0000); + /* Write nomagic word to enable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A , 0x0000); + } + + /* save values for restore after re-acquire */ + commonAttr->mpegCfg.enableMPEGOutput = cfgData->enableMPEGOutput; + commonAttr->mpegCfg.insertRSByte = cfgData->insertRSByte; + commonAttr->mpegCfg.enableParallel = cfgData->enableParallel; + commonAttr->mpegCfg.invertDATA = cfgData->invertDATA; + commonAttr->mpegCfg.invertERR = cfgData->invertERR; + commonAttr->mpegCfg.invertSTR = cfgData->invertSTR; + commonAttr->mpegCfg.invertVAL = cfgData->invertVAL; + commonAttr->mpegCfg.invertCLK = cfgData->invertCLK; + commonAttr->mpegCfg.staticCLK = cfgData->staticCLK; + commonAttr->mpegCfg.bitrate = cfgData->bitrate; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgMPEGOutput() +* \brief Get MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to MPEG output configuaration struct. +* \return DRXStatus_t. +* +* Retrieve MPEG output configuartion. +* +*/ +static DRXStatus_t +CtrlGetCfgMPEGOutput( pDRXDemodInstance_t demod, + pDRXCfgMPEGOutput_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u32_t rateReg = 0; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + + if( cfgData == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + commonAttr = demod->myCommonAttr; + + cfgData->enableMPEGOutput = commonAttr->mpegCfg.enableMPEGOutput; + cfgData->insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgData->enableParallel = commonAttr->mpegCfg.enableParallel; + cfgData->invertDATA = commonAttr->mpegCfg.invertDATA; + cfgData->invertERR = commonAttr->mpegCfg.invertERR; + cfgData->invertSTR = commonAttr->mpegCfg.invertSTR; + cfgData->invertVAL = commonAttr->mpegCfg.invertVAL; + cfgData->invertCLK = commonAttr->mpegCfg.invertCLK; + cfgData->staticCLK = commonAttr->mpegCfg.staticCLK; + cfgData->bitrate = 0; + + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( (lockStatus == DRX_LOCKED) ) + { + RR32 (devAddr, FEC_OC_RCN_DYN_RATE_LO__A, &rateReg); + /* Frcn_rate = rateReg * Fsys / 2 ^ 25 */ + Mult32 ( rateReg, commonAttr->sysClockFreq * 1000, &data64Hi, &data64Lo ); + cfgData->bitrate = (data64Hi << 7) | (data64Lo >> 25); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - begin */ +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t SetMPEGTEIHandling() +* \brief Activate MPEG TEI handling settings. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGTEIHandling( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcDprMode = 0; + u16_t fecOcSncMode = 0; + u16_t fecOcEmsMode = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + RR16( devAddr, FEC_OC_DPR_MODE__A, &fecOcDprMode ); + RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); + RR16( devAddr, FEC_OC_EMS_MODE__A, &fecOcEmsMode ); + + /* reset to default, allow TEI bit to be changed */ + fecOcDprMode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fecOcSncMode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + FEC_OC_SNC_MODE_CORR_DISABLE__M)); + fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M); + + if ( extAttr->disableTEIhandling == TRUE ) + { + /* do not change TEI bit */ + fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + ( (0x2)<<(FEC_OC_SNC_MODE_ERROR_CTL__B)); + fecOcEmsMode |= ((0x01)<<(FEC_OC_EMS_MODE_MODE__B)); + } + + WR16( devAddr, FEC_OC_DPR_MODE__A, fecOcDprMode ); + WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode ); + WR16( devAddr, FEC_OC_EMS_MODE__A, fecOcEmsMode ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t BitReverseMPEGOutput() +* \brief Set MPEG output bit-endian settings. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +BitReverseMPEGOutput ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcIprMode = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + RR16( devAddr, FEC_OC_IPR_MODE__A, &fecOcIprMode ); + + /* reset to default (normal bit order) */ + fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + + if ( extAttr->bitReverseMpegOutout == TRUE) + { + /* reverse bit order */ + fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + } + + WR16( devAddr, FEC_OC_IPR_MODE__A, fecOcIprMode ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SetMPEGOutputClockRate() +* \brief Set MPEG output clock rate. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGOutputClockRate ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + if ( extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO ) + { + WR16 ( devAddr, FEC_OC_DTO_PERIOD__A, extAttr->mpegOutputClockRate - 1 ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SetMPEGStartWidth() +* \brief Set MPEG start width. +* \param devmod Pointer to demodulator instance. +* \return DRXStatus_t. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static DRXStatus_t +SetMPEGStartWidth ( pDRXDemodInstance_t demod ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + u16_t fecOcCommMb = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = demod->myCommonAttr; + + if ((commonAttr->mpegCfg.staticCLK == TRUE) && (commonAttr->mpegCfg.enableParallel == FALSE)) + { + RR16 ( devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb ); + fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON; + if ( extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC ) + { + fecOcCommMb |= FEC_OC_COMM_MB_CTL_ON; + } + WR16 ( devAddr, FEC_OC_COMM_MB__A, fecOcCommMb); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetCfgMpegOutputMisc() +* \brief Set miscellaneous configuartions +* \param devmod Pointer to demodulator instance. +* \param cfgData pDRXJCfgMisc_t +* \return DRXStatus_t. +* +* This routine can be used to set configuartion options that are DRXJ +* specific and/or added to the requirements at a late stage. +* +*/ +static DRXStatus_t +CtrlSetCfgMpegOutputMisc( + pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* + Set disable TEI bit handling flag. + TEI must be left untouched by device in case of BER measurements using + external equipment that is unable to ignore the TEI bit in the TS. + Default will FALSE (enable TEI bit handling). + Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)). + Set clock rate. Default is auto that is derived from symbol rate. + The flags and values will also be used to set registers during a set channel. + */ + extAttr->disableTEIhandling = cfgData->disableTEIHandling; + extAttr->bitReverseMpegOutout = cfgData->bitReverseMpegOutout; + extAttr->mpegOutputClockRate = cfgData->mpegOutputClockRate; + extAttr->mpegStartWidth = cfgData->mpegStartWidth; + /* Don't care what the active standard is, activate setting immediatly */ + CHK_ERROR ( SetMPEGTEIHandling( demod ) ); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGOutputClockRate( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgMpegOutputMisc() +* \brief Get miscellaneous configuartions. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to DRXJCfgMisc_t. +* \return DRXStatus_t. +* +* This routine can be used to retreive the current setting of the configuartion +* options that are DRXJ specific and/or added to the requirements at a +* late stage. +* +*/ +static DRXStatus_t +CtrlGetCfgMpegOutputMisc( + pDRXDemodInstance_t demod, + pDRXJCfgMpegOutputMisc_t cfgData ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t data = 0; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + cfgData->disableTEIHandling = extAttr->disableTEIhandling; + cfgData->bitReverseMpegOutout = extAttr->bitReverseMpegOutout; + cfgData->mpegStartWidth = extAttr->mpegStartWidth; + if (extAttr->mpegOutputClockRate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + { + cfgData->mpegOutputClockRate = extAttr->mpegOutputClockRate; + } + else + { + RR16 ( demod->myI2CDevAddr, FEC_OC_DTO_PERIOD__A, &data ); + cfgData->mpegOutputClockRate = (DRXJMpegOutputClockRate_t) (data + 1); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*----------------------------------------------------------------------------*/ + +/** +* \fn DRXStatus_t CtrlGetCfgHwCfg() +* \brief Get HW configuartions. +* \param devmod Pointer to demodulator instance. +* \param cfgData Pointer to Bool. +* \return DRXStatus_t. +* +* This routine can be used to retreive the current setting of the configuartion +* options that are DRXJ specific and/or added to the requirements at a +* late stage. +* +*/ +static DRXStatus_t +CtrlGetCfgHwCfg( pDRXDemodInstance_t demod, + pDRXJCfgHwCfg_t cfgData ) +{ + u16_t data = 0; + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod -> myExtAttr; + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0xFABA); + RR16 ( demod->myI2CDevAddr, SIO_PDR_OHW_CFG__A, &data ); + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + cfgData->i2cSpeed = (DRXJI2CSpeed_t)((data >> 6) & 0x1); + cfgData->xtalFreq = (DRXJXtalFreq_t)(data & 0x3); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*----------------------------------------------------------------------------*/ +/* miscellaneous configuartions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* UIO Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlSetUIOCfg() +* \brief Configure modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlSetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + if (( UIOCfg == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOCfg->uio ) { + /*====================================================================*/ + case DRX_UIO1 : + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */ + case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaTxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaTxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO2 : + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioSmaRxMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioSmaRxMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO3 : + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + case DRX_UIO_MODE_READWRITE: + extAttr->uioGPIOMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + extAttr->uioGPIOMode = UIOCfg->mode; + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, 0 ); + break; + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO4 : + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + switch ( UIOCfg->mode ) + { + case DRX_UIO_MODE_READWRITE: + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + /* pad configuration register is set 0 - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, 0 ); + extAttr->uioIRQNMode = UIOCfg->mode; + break; + case DRX_UIO_MODE_FIRMWARE0: /* falltrough */ + default: + return DRX_STS_INVALID_ARG; + break; + } /* switch ( UIOCfg->mode ) */ + break; + /*====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOCfg->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetUIOCfg() +* \brief Get modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param UIOCfg Pointer to a configuration setting for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetUIOCfg( pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg ) +{ + + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pDRXUIOMode_t UIOMode[4] = {NULL}; + pBool_t UIOAvailable[4] = {NULL}; + + extAttr = demod->myExtAttr; + + UIOMode[DRX_UIO1] = &extAttr->uioSmaTxMode; + UIOMode[DRX_UIO2] = &extAttr->uioSmaRxMode; + UIOMode[DRX_UIO3] = &extAttr->uioGPIOMode; + UIOMode[DRX_UIO4] = &extAttr->uioIRQNMode; + + UIOAvailable[DRX_UIO1] = &extAttr->hasSMATX; + UIOAvailable[DRX_UIO2] = &extAttr->hasSMARX; + UIOAvailable[DRX_UIO3] = &extAttr->hasGPIO; + UIOAvailable[DRX_UIO4] = &extAttr->hasIRQN; + + if ( UIOCfg == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + if ( ( UIOCfg->uio > DRX_UIO4 ) || + ( UIOCfg->uio < DRX_UIO1 ) ) + { + return DRX_STS_INVALID_ARG; + } + + if( *UIOAvailable[UIOCfg->uio] == FALSE ) + { + return DRX_STS_ERROR; + } + + UIOCfg->mode = *UIOMode[ UIOCfg->uio ]; + + return DRX_STS_OK; +} + +/** +* \fn DRXStatus_t CtrlUIOWrite() +* \brief Write to a UIO. +* \param demod Pointer to demodulator instance. +* \param UIOData Pointer to data container for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUIOWrite( pDRXDemodInstance_t demod, + pDRXUIOData_t UIOData) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; + + if (( UIOData == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOData->uio ) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + if ( ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) + && ( extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW ) ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ + } else { + value |= 0x4000; /* write one to 14th bit - 2nd UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: ASEL UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ + } else { + value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, value ); + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); + + /* use corresponding bit in io data output registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value ); + if (UIOData->value == FALSE) + { + value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ + } else { + value |= 0x1000; /* write one to 12th bit - 4th UIO */ + } + /* write back to io data output register */ + WR16( demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, value ); + break; + /*=====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + + +/** +*\fn DRXStatus_t CtrlUIORead +*\brief Read from a UIO. +* \param demod Pointer to demodulator instance. +* \param UIOData Pointer to data container for a certain UIO. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUIORead( pDRXDemodInstance_t demod, + pDRXUIOData_t UIOData) +{ + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + u16_t pinCfgValue = 0; + u16_t value = 0; + + if (( UIOData == NULL ) || ( demod == NULL )) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + switch ( UIOData->uio ) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (extAttr->hasSMATX != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, pinCfgValue ); + + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + if ( (value & 0x8000) != 0 ) /* check 15th bit - 1st UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (extAttr->hasSMARX != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_RX_CFG__A, pinCfgValue ); + + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + + if ( (value & 0x4000) != 0 ) /* check 14th bit - 2nd UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*=====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (extAttr->hasGPIO != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_GPIO_CFG__A, pinCfgValue ); + + /* read io input data registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value ); + if ( (value & 0x0004) != 0 ) /* check 2nd bit - 3rd UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (extAttr->hasIRQN != TRUE) + return DRX_STS_ERROR; + + if ( extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE ) + { + return DRX_STS_ERROR; + } + pinCfgValue = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pinCfgValue |= 0x0110; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - input mode */ + WR16( demod->myI2CDevAddr, SIO_PDR_IRQN_CFG__A, pinCfgValue ); + + /* read io input data registar */ + RR16( demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value ); + if ( (value & 0x1000) != 0 ) /* check 12th bit - 4th UIO */ + { + UIOData->value = TRUE; + } else { + UIOData->value = FALSE; + } + break; + /*====================================================================*/ + default: + return DRX_STS_INVALID_ARG; + } /* switch ( UIOData->uio ) */ + + /* Write magic word to disable pdr reg write */ + WR16 ( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*---------------------------------------------------------------------------*/ +/* UIO Configuration Functions - end */ +/*---------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t CtrlI2CBridge() +* \brief Open or close the I2C switch to tuner. +* \param demod Pointer to demodulator instance. +* \param bridgeClosed Pointer to bool indication if bridge is closed not. +* \return DRXStatus_t. + +*/ +static DRXStatus_t +CtrlI2CBridge( pDRXDemodInstance_t demod, + pBool_t bridgeClosed ) +{ + DRXJHiCmd_t hiCmd; + u16_t result = 0; + + /* check arguments */ + if (bridgeClosed == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridgeClosed == TRUE) + { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + } + else + { + hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + } + + return HICommand( demod -> myI2CDevAddr, &hiCmd, &result); +} +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* Smart antenna Functions - begin */ +/*----------------------------------------------------------------------------*/ +/** +* \fn DRXStatus_t SmartAntInit() +* \brief Initialize Smart Antenna. +* \param pointer to DRXDemodInstance_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +SmartAntInit(pDRXDemodInstance_t demod) +{ + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA}; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + /* init smart antenna */ + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + if (extAttr->smartAntInverted) + WR16( devAddr, SIO_SA_TX_COMMAND__A, + (data | SIO_SA_TX_COMMAND_TX_INVERT__M ) + | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + else + WR16( devAddr, SIO_SA_TX_COMMAND__A, + (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) + | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + + /* config SMA_TX pin to smart antenna mode*/ + CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_CFG__A, 0x13 ); + WR16( demod->myI2CDevAddr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03 ); + + /* Write magic word to disable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfgSmartAnt() +* \brief Set Smart Antenna. +* \param pointer to DRXJCfgSmartAnt_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgSmartAnt ( pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + u16_t data = 0; + u32_t startTime = 0; + static Bool_t bitInverted = FALSE; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( smartAnt == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( bitInverted != extAttr->smartAntInverted + || extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SMA) + { + CHK_ERROR(SmartAntInit(demod)); + bitInverted = extAttr->smartAntInverted; + } + + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + switch (smartAnt->io) + { + case DRXJ_SMT_ANT_OUTPUT: + /* enable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M ); + */ + startTime = DRXBSP_HST_Clock(); + do{ + RR16( devAddr, SIO_SA_TX_STATUS__A, &data ); + } while ( (data & SIO_SA_TX_STATUS_BUSY__M) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); + + if ( data & SIO_SA_TX_STATUS_BUSY__M ) + { + return (DRX_STS_ERROR); + } + + /* write to smart antenna configuration register */ + WR16( devAddr, SIO_SA_TX_DATA0__A, 0x9200 + | ((smartAnt->ctrlData & 0x0001) << 8) + | ((smartAnt->ctrlData & 0x0002) << 10) + | ((smartAnt->ctrlData & 0x0004) << 12) + ); + WR16( devAddr, SIO_SA_TX_DATA1__A, 0x4924 + | ((smartAnt->ctrlData & 0x0008) >> 2) + | ((smartAnt->ctrlData & 0x0010) ) + | ((smartAnt->ctrlData & 0x0020) << 2) + | ((smartAnt->ctrlData & 0x0040) << 4) + | ((smartAnt->ctrlData & 0x0080) << 6) + ); + WR16( devAddr, SIO_SA_TX_DATA2__A, 0x2492 + | ((smartAnt->ctrlData & 0x0100) >> 8) + | ((smartAnt->ctrlData & 0x0200) >> 6) + | ((smartAnt->ctrlData & 0x0400) >> 4) + | ((smartAnt->ctrlData & 0x0800) >> 2) + | ((smartAnt->ctrlData & 0x1000) ) + | ((smartAnt->ctrlData & 0x2000) << 2) + ); + WR16( devAddr, SIO_SA_TX_DATA3__A, 0xff8d ); + + /* trigger the sending */ + WR16( devAddr, SIO_SA_TX_LENGTH__A, 56 ); + + break; + case DRXJ_SMT_ANT_INPUT: + /* disable Tx if Mode B (input) is supported */ + /* + RR16( devAddr, SIO_SA_TX_COMMAND__A, &data ); + WR16( devAddr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) ); + */ + default: + return (DRX_STS_INVALID_ARG); + } + /* Write magic word to enable pdr reg write */ + WR16( demod->myI2CDevAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +static DRXStatus_t +SCUCommand( pI2CDeviceAddr_t devAddr, pDRXJSCUCmd_t cmd ) +{ + u16_t curCmd = 0; + u32_t startTime = 0; + + /* Check param */ + if ( cmd == NULL ) + return (DRX_STS_INVALID_ARG); + + /* Wait until SCU command interface is ready to receive command */ + RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); + if ( curCmd != DRX_SCU_READY ) + { + return (DRX_STS_ERROR); + } + + switch ( cmd->parameterLen ) + { + case 5: + WR16( devAddr, SCU_RAM_PARAM_4__A , *(cmd->parameter + 4)); /* fallthrough */ + case 4: + WR16( devAddr, SCU_RAM_PARAM_3__A , *(cmd->parameter + 3)); /* fallthrough */ + case 3: + WR16( devAddr, SCU_RAM_PARAM_2__A , *(cmd->parameter + 2)); /* fallthrough */ + case 2: + WR16( devAddr, SCU_RAM_PARAM_1__A , *(cmd->parameter + 1)); /* fallthrough */ + case 1: + WR16( devAddr, SCU_RAM_PARAM_0__A , *(cmd->parameter + 0)); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + WR16( devAddr, SCU_RAM_COMMAND__A, cmd->command ); + + /* Wait until SCU has processed command */ + startTime = DRXBSP_HST_Clock(); + do{ + RR16( devAddr, SCU_RAM_COMMAND__A, &curCmd ); + } while ( ! ( curCmd == DRX_SCU_READY ) && ( (DRXBSP_HST_Clock() - startTime) < DRXJ_MAX_WAITTIME ) ); + + if ( curCmd != DRX_SCU_READY ) + { + return (DRX_STS_ERROR); + } + + /* read results */ + if ( (cmd->resultLen > 0) && (cmd->result != NULL) ) + { + s16_t err; + + switch ( cmd->resultLen ) + { + case 4: + RR16( devAddr, SCU_RAM_PARAM_3__A , cmd->result + 3); /* fallthrough */ + case 3: + RR16( devAddr, SCU_RAM_PARAM_2__A , cmd->result + 2); /* fallthrough */ + case 2: + RR16( devAddr, SCU_RAM_PARAM_1__A , cmd->result + 1); /* fallthrough */ + case 1: + RR16( devAddr, SCU_RAM_PARAM_0__A , cmd->result + 0); /* fallthrough */ + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return (DRX_STS_ERROR); + } + + + /* Check if an error was reported by SCU */ + err = cmd->result[0]; + + /* check a few fixed error codes */ + if ( ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKSTD ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_UNKCMD ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_INVPAR ) + || ( err == (s16_t)SCU_RAM_PARAM_0_RESULT_SIZE ) + ) + { + return DRX_STS_INVALID_ARG; + } + /* here it is assumed that negative means error, and positive no error */ + else if ( err < 0 ) + { + return DRX_STS_ERROR; + } + else + { + return DRX_STS_OK; + } + } + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t DRXJ_DAP_SCUAtomicReadWriteBlock() +* \brief Basic access routine for SCU atomic read or write access +* \param devAddr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return DRXStatus_t +* \retval DRX_STS_OK Succes +* \retval DRX_STS_ERROR Timeout, I2C error, illegal bank +* +*/ +#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) +static +DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t datasize, /* max 30 bytes because the limit of SCU parameter */ + pu8_t data, + Bool_t readFlag) +{ + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[15]; + u16_t cmdResult[15]; + + /* Parameter check */ + if ( ( data == NULL ) || + ( devAddr == NULL ) || + ( (datasize%2)!= 0 ) || + ( (datasize/2) > 16 ) + ) + { + return (DRX_STS_INVALID_ARG); + } + + setParamParameters[1] = (u16_t)ADDR_AT_SCU_SPACE (addr); + if (readFlag) /* read */ + { + setParamParameters[0] = ((~(0x0080)) & datasize); + scuCmd.parameterLen = 2; + scuCmd.resultLen = datasize/2 + 2; + } else { + int i = 0; + + setParamParameters[0] = 0x0080 | datasize; + for (i = 0; i < (datasize/2); i++) + { + setParamParameters[i+2] = (data[2*i] | (data[(2*i)+1]<<8)); + } + scuCmd.parameterLen = datasize / 2 + 2; + scuCmd.resultLen = 1; + } + + scuCmd.command = SCU_RAM_COMMAND_STANDARD_TOP | SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; + scuCmd.result = cmdResult; + scuCmd.parameter = setParamParameters; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + if ( readFlag==TRUE ) + { + int i = 0; + /* read data from buffer */ + for (i = 0; i < (datasize/2); i++) + { + data[2*i] = (u8_t) (scuCmd.result[i+2] & 0xFF); + data[(2*i) + 1] = (u8_t) (scuCmd.result[i+2] >> 8 ); + } + } + + return DRX_STS_OK; + + rw_error: + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t DRXJ_DAP_AtomicReadReg16() +* \brief Atomic read of 16 bits words +*/ +static +DRXStatus_t DRXJ_DAP_SCU_AtomicReadReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + pu16_t data, + DRXflags_t flags) +{ + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; + u16_t word = 0; + + if (!data) + { + return DRX_STS_INVALID_ARG; + } + + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, + 2, buf, TRUE); + + word = (u16_t)(buf[0] + (buf[1] << 8)); + + *data = word; + + return rc; +} +/*============================================================================*/ +/** +* \fn DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16() +* \brief Atomic read of 16 bits words +*/ +static +DRXStatus_t DRXJ_DAP_SCU_AtomicWriteReg16 ( + pI2CDeviceAddr_t devAddr, + DRXaddr_t addr, + u16_t data, + DRXflags_t flags) +{ + u8_t buf[2]; + DRXStatus_t rc = DRX_STS_ERROR; + + buf[0] = (u8_t) (data & 0xff); + buf[1] = (u8_t) ((data >> 8) & 0xff); + + rc = DRXJ_DAP_SCU_AtomicReadWriteBlock ( devAddr, addr, + 2, buf, FALSE); + + return rc; +} + +static DRXStatus_t +CtrlI2CWriteRead( pDRXDemodInstance_t demod, + pDRXI2CData_t i2cData ) +{ + return (DRX_STS_FUNC_NOT_AVAILABLE); +} + +DRXStatus_t +TunerI2CWriteRead( pTUNERInstance_t tuner, + pI2CDeviceAddr_t wDevAddr, + u16_t wCount, + pu8_t wData, + pI2CDeviceAddr_t rDevAddr, + u16_t rCount, + pu8_t rData) +{ + pDRXDemodInstance_t demod; + DRXI2CData_t i2cData = { 2, wDevAddr, wCount, wData, rDevAddr, rCount, rData }; + + demod = (pDRXDemodInstance_t) (tuner->myCommonAttr->myUserData); + + return ( CtrlI2CWriteRead( demod, &i2cData ) ); +} + +/* -------------------------------------------------------------------------- */ +/** +* \brief Measure result of ADC synchronisation +* \param demod demod instance +* \param count (returned) count +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure: I2C error +* +*/ +static DRXStatus_t +ADCSyncMeasurement( pDRXDemodInstance_t demod, + pu16_t count ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + /* Start measurement */ + WR16( devAddr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); + WR16( devAddr, IQM_AF_START_LOCK__A, 1); + + /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ + CHK_ERROR( DRXBSP_HST_Sleep(1)); + + *count = 0; + RR16( devAddr, IQM_AF_PHASE0__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + RR16( devAddr, IQM_AF_PHASE1__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + RR16( devAddr, IQM_AF_PHASE2__A, &data); + if ( data == 127 ) + { + *count = *count+1; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \brief Synchronize analog and digital clock domains +* \param demod demod instance +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR Failure: I2C error or failure to synchronize +* +* An IQM reset will also reset the results of this synchronization. +* After an IQM reset this routine needs to be called again. +* +*/ + +static DRXStatus_t +ADCSynchronization( pDRXDemodInstance_t demod ) +{ + u16_t count = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + CHK_ERROR( ADCSyncMeasurement( demod, &count )); + + if (count==1) + { + /* Try sampling on a diffrent edge */ + u16_t clkNeg = 0; + + RR16( devAddr, IQM_AF_CLKNEG__A, &clkNeg); + + clkNeg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + WR16( devAddr, IQM_AF_CLKNEG__A, clkNeg); + + CHK_ERROR( ADCSyncMeasurement( demod, &count )); + } + + if ( count < 2 ) + { + /* TODO: implement fallback scenarios */ + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +IQMSetAf ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Configure IQM */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + if( !active ) + { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } else /* active */ + { + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE + ); + } + WR16( devAddr, IQM_AF_STDBY__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +static DRXStatus_t +CtrlSetCfgATVOutput( pDRXDemodInstance_t demod , + pDRXJCfgAtvOutput_t outputCfg ); + +/** +* \brief set configuration of pin-safe mode +* \param demod instance of demodulator. +* \param enable boolean; TRUE: activate pin-safe mode, FALSE: de-activate p.s.m. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlSetCfgPdrSafeMode ( pDRXDemodInstance_t demod, + pBool_t enable ) +{ + pDRXJData_t extAttr = (pDRXJData_t) NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) NULL; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) NULL; + + if ( enable == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + commonAttr = demod->myCommonAttr; + + /* Write magic word to enable pdr reg write */ + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + if ( *enable == TRUE ) + { + Bool_t bridgeEnabled = FALSE; + + /* MPEG pins to input */ + WR16 ( devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_I2C_SDA2 Bridge off, Port2 Inactive + PD_I2C_SCL2 Bridge off, Port2 Inactive */ + CHK_ERROR( CtrlI2CBridge( demod, &bridgeEnabled ) ); + WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_GPIO Store and set to input + PD_VSYNC Store and set to input + PD_SMA_RX Store and set to input + PD_SMA_TX Store and set to input */ + RR16 ( devAddr, SIO_PDR_GPIO_CFG__A, &extAttr->pdrSafeRestoreValGpio ); + RR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, &extAttr->pdrSafeRestoreValVSync ); + RR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, &extAttr->pdrSafeRestoreValSmaRx ); + RR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, &extAttr->pdrSafeRestoreValSmaTx ); + WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE ); + + /* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate! + PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */ + CHK_ERROR( IQMSetAf ( demod, FALSE ) ); + + /* PD_CVBS Analog DAC output, standby mode + PD_SIF Analog DAC output, standby mode */ + WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); + + /* PD_I2S_CL Input + PD_I2S_DA Input + PD_I2S_WS Input */ + WR16 ( devAddr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE ); + WR16 ( devAddr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE ); + } + else + { + /* No need to restore MPEG pins; + is done in SetStandard/SetChannel */ + + /* PD_I2C_SDA2 Port2 active + PD_I2C_SCL2 Port2 active */ + WR16 ( devAddr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE ); + WR16 ( devAddr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE ); + + /* PD_GPIO Restore + PD_VSYNC Restore + PD_SMA_RX Restore + PD_SMA_TX Restore */ + WR16 ( devAddr, SIO_PDR_GPIO_CFG__A, extAttr->pdrSafeRestoreValGpio ); + WR16 ( devAddr, SIO_PDR_VSYNC_CFG__A, extAttr->pdrSafeRestoreValVSync ); + WR16 ( devAddr, SIO_PDR_SMA_RX_CFG__A, extAttr->pdrSafeRestoreValSmaRx ); + WR16 ( devAddr, SIO_PDR_SMA_TX_CFG__A, extAttr->pdrSafeRestoreValSmaTx ); + + /* PD_RF_AGC, PD_IF_AGC + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_CVBS, PD_SIF + No need to restore; will be restored in SetStandard/SetChannel */ + + /* PD_I2S_CL, PD_I2S_DA, PD_I2S_WS + Should be restored via DRX_CTRL_SET_AUD */ + } + + /* Write magic word to disable pdr reg write */ + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000 ); + extAttr->pdrSafeMode = *enable; + + return (DRX_STS_OK); + + rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ + +/** +* \brief get configuration of pin-safe mode +* \param demod instance of demodulator. +* \param enable boolean indicating whether pin-safe mode is active +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetCfgPdrSafeMode ( pDRXDemodInstance_t demod, + pBool_t enabled ) +{ + pDRXJData_t extAttr = (pDRXJData_t) NULL; + + if ( enabled == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t) demod->myExtAttr; + *enabled = extAttr->pdrSafeMode; + + return (DRX_STS_OK); +} + +/** +* \brief Verifies whether microcode can be loaded. +* \param demod Demodulator instance. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlValidateUCode (pDRXDemodInstance_t demod) +{ + u32_t mcDev, mcPatch; + u16_t verType; + + /* Check device. + * Disallow microcode if: + * - MC has version record AND + * - device ID in version record is not 0 AND + * - product ID in version record's device ID does not + * match DRXJ1 product IDs - 0x393 or 0x394 + */ + DRX_GET_MCVERTYPE (demod, verType); + DRX_GET_MCDEV (demod, mcDev); + DRX_GET_MCPATCH (demod, mcPatch); + + if (DRX_ISMCVERTYPE (verType)) + { + if ((mcDev != 0) && + (((mcDev >> 16) & 0xFFF) != 0x393) && + (((mcDev >> 16) & 0xFFF) != 0x394)) + { + /* Microcode is marked for another device - error */ + return DRX_STS_INVALID_ARG; + } + else if (mcPatch != 0) + { + /* Patch not allowed because there is no ROM */ + return DRX_STS_INVALID_ARG; + } + } + + /* Everything else: OK */ + return DRX_STS_OK; +} + +/*============================================================================*/ +/*== END AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +/** +* \fn DRXStatus_t InitAGC () +* \brief Initialize AGC for all standards. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +InitAGC ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcRfSettings = NULL; + pDRXJCfgAgc_t pAgcIfSettings = NULL; + u16_t IngainTgtMax = 0; + u16_t clpDirTo = 0; + u16_t snsSumMax = 0; + u16_t clpSumMax = 0; + u16_t snsDirTo = 0; + u16_t kiInnergainMin = 0; + u16_t agcKi = 0; + u16_t kiMax = 0; + u16_t ifIaccuHiTgtMin = 0; + u16_t data = 0; + u16_t agcKiDgain = 0; + u16_t kiMin = 0; + u16_t clpCtrlMode = 0; + u16_t agcRf = 0; + u16_t agcIf = 0; + devAddr = demod->myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch (extAttr->standard) + { + case DRX_STANDARD_8VSB : + clpSumMax = 1023; + clpDirTo = (u16_t)(-9); + snsSumMax = 1023; + snsDirTo = (u16_t)(-9); + kiInnergainMin = (u16_t)(-32768); + kiMax = 0x032C; + agcKiDgain = 0xC; + ifIaccuHiTgtMin = 2047; + kiMin = 0x0117; + IngainTgtMax = 16383; + clpCtrlMode = 0; + WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_INGAIN__A, 1024 ); + WR16( devAddr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600 ); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, 13200 ); + pAgcIfSettings = &(extAttr->vsbIfAgcCfg); + pAgcRfSettings = &(extAttr->vsbRfAgcCfg); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_B: + IngainTgtMax = 5119; + clpSumMax = 1023; + clpDirTo = (u16_t)(-5); + snsSumMax = 127; + snsDirTo = (u16_t)(-3); + kiInnergainMin = 0; + kiMax = 0x0657; + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0117; + clpCtrlMode = 0; + WR16( devAddr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_STP__A, 1 ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCCNT__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_WD__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_STP__A, 1 ); + pAgcIfSettings = &(extAttr->qamIfAgcCfg); + pAgcRfSettings = &(extAttr->qamRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + + RR16( devAddr, SCU_RAM_AGC_KI__A, &agcKi ); + agcKi &= 0xf000; + WR16( devAddr, SCU_RAM_AGC_KI__A, agcKi ); + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_FM: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + snsDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I : + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + snsDirTo = (u16_t)(-9); + clpCtrlMode = 1; + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; + case DRX_STANDARD_PAL_SECAM_L : + case DRX_STANDARD_PAL_SECAM_LP: + clpSumMax = 1023; + snsSumMax = 1023; + kiInnergainMin = (u16_t)(-32768); + ifIaccuHiTgtMin = 2047; + agcKiDgain = 0x7; + kiMin = 0x0225; + kiMax = 0x0547; + clpDirTo = (u16_t)(-9); + snsDirTo = (u16_t)(-9); + IngainTgtMax = 9000; + clpCtrlMode = 1; + pAgcIfSettings = &(extAttr->atvIfAgcCfg); + pAgcRfSettings = &(extAttr->atvRfAgcCfg); + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT__A, pAgcIfSettings->top ); + break; +#endif + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* for new AGC interface */ + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcIfSettings->top ); + WR16( devAddr, SCU_RAM_AGC_INGAIN__A, pAgcIfSettings->top ); /* Gain fed from inner to outer AGC */ + WR16( devAddr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, IngainTgtMax ); + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin ); + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, 0 ); /* set to pAgcSettings->top before */ + WR16( devAddr, SCU_RAM_AGC_IF_IACCU_LO__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_IACCU_LO__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_RF_MAX__A, 32767 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax ); + WR16( devAddr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin ); + WR16( devAddr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50 ); + WR16( devAddr, SCU_RAM_AGC_KI_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_SNS_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20 ); + WR16( devAddr, SCU_RAM_AGC_KI_MIN__A, kiMin ); + WR16( devAddr, SCU_RAM_AGC_KI_MAX__A, kiMax ); + WR16( devAddr, SCU_RAM_AGC_KI_RED__A, 0 ); + WR16( devAddr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CYCLEN__A, 500 ); + WR16( devAddr, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo ); + WR16( devAddr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8 ); + WR16( devAddr, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo ); + WR16( devAddr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50 ); + WR16( devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode ); + + agcRf = 0x800 + pAgcRfSettings->cutOffCurrent; + if ( commonAttr->tunerRfAgcPol == TRUE ) + { + agcRf = 0x87ff - agcRf; + } + + agcIf = 0x800; + if ( commonAttr->tunerIfAgcPol == TRUE ) + { + agcRf = 0x87ff - agcRf; + } + + WR16( devAddr, IQM_AF_AGC_RF__A, agcRf ); + WR16( devAddr, IQM_AF_AGC_IF__A, agcIf ); + + /* Set/restore Ki DGAIN factor */ + RR16( devAddr, SCU_RAM_AGC_KI__A, &data ); + data &= ~SCU_RAM_AGC_KI_DGAIN__M; + data |= ( agcKiDgain << SCU_RAM_AGC_KI_DGAIN__B ); + WR16( devAddr, SCU_RAM_AGC_KI__A, data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetFrequency () +* \brief Set frequency shift. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \param tunerFreqOffset residual frequency from tuner. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetFrequency ( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset + ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t samplingFrequency = 0; + DRXFrequency_t frequencyShift = 0; + DRXFrequency_t ifFreqActual = 0; + DRXFrequency_t rfFreqResidual = 0; + DRXFrequency_t adcFreq = 0; + DRXFrequency_t intermediateFreq = 0; + u32_t iqmFsRateOfs = 0; + pDRXJData_t extAttr = NULL; + Bool_t adcFlip = TRUE; + Bool_t selectPosImage = FALSE; + Bool_t rfMirror = FALSE; + Bool_t tunerMirror = TRUE; + Bool_t imageToSelect = TRUE; + DRXFrequency_t fmFrequencyShift = 0; + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + rfFreqResidual = -1 * tunerFreqOffset; + rfMirror = (extAttr->mirror == DRX_MIRROR_YES)?TRUE:FALSE; + tunerMirror = demod->myCommonAttr->mirrorFreqSpect?FALSE:TRUE; + /* + Program frequency shifter + No need to account for mirroring on RF + */ + switch (extAttr->standard) + { + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_C: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */ + case DRX_STANDARD_8VSB: + selectPosImage = TRUE; + break; + case DRX_STANDARD_FM: + /* After IQM FS sound carrier must appear at 4 Mhz in spect. + Sound carrier is already 3Mhz above centre frequency due + to tuner setting so now add an extra shift of 1MHz... */ + fmFrequencyShift = 1000; + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: + selectPosImage = FALSE; + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + intermediateFreq = demod->myCommonAttr->intermediateFreq; + samplingFrequency = demod->myCommonAttr->sysClockFreq/3; + if ( tunerMirror == TRUE ) + { + /* tuner doesn't mirror */ + ifFreqActual = intermediateFreq + rfFreqResidual + fmFrequencyShift; + } else { + /* tuner mirrors */ + ifFreqActual = intermediateFreq - rfFreqResidual - fmFrequencyShift; + } + if ( ifFreqActual > samplingFrequency / 2) + { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = TRUE; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = FALSE; + } + + frequencyShift = adcFreq; + imageToSelect = (Bool_t)(rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage); + iqmFsRateOfs = Frac28(frequencyShift,samplingFrequency); + + if (imageToSelect) + iqmFsRateOfs = ~iqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (Bool_t)(rfMirror ^ tunerMirror ^ selectPosImage); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetSigStrength() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param u16-t Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +*/ +#define DRXJ_AGC_TOP 0x2800 +#define DRXJ_AGC_SNS 0x1600 +#define DRXJ_RFAGC_MAX 0x3fff +#define DRXJ_RFAGC_MIN 0x800 + +static DRXStatus_t +GetSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + u16_t rfGain = 0; + u16_t ifGain = 0; + u16_t ifAgcSns = 0; + u16_t ifAgcTop = 0; + u16_t rfAgcMax = 0; + u16_t rfAgcMin = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + RR16( devAddr, IQM_AF_AGC_IF__A, &ifGain ); + ifGain &= IQM_AF_AGC_IF__M; + RR16( devAddr, IQM_AF_AGC_RF__A, &rfGain ); + rfGain &= IQM_AF_AGC_RF__M; + + ifAgcSns = DRXJ_AGC_SNS; + ifAgcTop = DRXJ_AGC_TOP; + rfAgcMax = DRXJ_RFAGC_MAX; + rfAgcMin = DRXJ_RFAGC_MIN; + + if (ifGain > ifAgcTop) + { + if (rfGain > rfAgcMax) + *sigStrength = 100; + else if (rfGain > rfAgcMin) + { + CHK_ZERO (rfAgcMax - rfAgcMin); + *sigStrength = 75 + 25 * (rfGain - rfAgcMin) / (rfAgcMax - rfAgcMin); + } + else + *sigStrength = 75; + } + else if (ifGain > ifAgcSns) + { + CHK_ZERO(ifAgcTop - ifAgcSns); + *sigStrength = 20 + 55* (ifGain - ifAgcSns)/ (ifAgcTop - ifAgcSns); + } + else + { + CHK_ZERO (ifAgcSns); + *sigStrength = (20 * ifGain / ifAgcSns); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAccPktErr() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param packetErr Pointer to packet error +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. +*/ +#ifdef DRXJ_SIGNAL_ACCUM_ERR +static DRXStatus_t +GetAccPktErr( pDRXDemodInstance_t demod, + pu16_t packetErr ) +{ + static u16_t pktErr = 0; + static u16_t lastPktErr = 0; + u16_t data = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + RR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data ); + if ( extAttr->resetPktErrAcc == TRUE ) + { + lastPktErr = data; + pktErr = 0; + extAttr->resetPktErrAcc = FALSE; + } + + if (data < lastPktErr) + { + pktErr += 0xffff - lastPktErr; + pktErr += data; + } + else + { + pktErr += (data - lastPktErr); + } + *packetErr = pktErr; + lastPktErr = data; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t ResetAccPktErr() +* \brief Reset Accumulating packet error count. +* \param demod Pointer to demod instance +* \return DRXStatus_t. +* \retval DRX_STS_OK. +* \retval DRX_STS_ERROR Erroneous data. +*/ +static DRXStatus_t +CtrlSetCfgResetPktErr( pDRXDemodInstance_t demod ) +{ +#ifdef DRXJ_SIGNAL_ACCUM_ERR + pDRXJData_t extAttr = NULL; + u16_t packetError = 0; + + extAttr = (pDRXJData_t)demod->myExtAttr; + extAttr->resetPktErrAcc = TRUE; + /* call to reset counter */ + CHK_ERROR (GetAccPktErr (demod, &packetError)); + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetSTRFreqOffset() +* \brief Get symbol rate offset in QAM & 8VSB mode +* \return Error code +*/ +static DRXStatus_t +GetSTRFreqOffset( pDRXDemodInstance_t demod, + s32_t *STRFreq + ) +{ + u32_t symbolFrequencyRatio = 0; + u32_t symbolNomFrequencyRatio = 0; + + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + ARR32( devAddr, IQM_RC_RATE_LO__A, &symbolFrequencyRatio ); + symbolNomFrequencyRatio = extAttr->iqmRcRateOfs; + + if ( symbolFrequencyRatio > symbolNomFrequencyRatio ) + *STRFreq = -1 * FracTimes1e6( ( symbolFrequencyRatio - symbolNomFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); + else + *STRFreq = FracTimes1e6( ( symbolNomFrequencyRatio - symbolFrequencyRatio ), (symbolFrequencyRatio + (1 << 23)) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetCTLFreqOffset +* \brief Get the value of CTLFreq in QAM & ATSC mode +* \return Error code +*/ +static DRXStatus_t +GetCTLFreqOffset ( pDRXDemodInstance_t demod, + s32_t *CTLFreq + ) +{ + DRXFrequency_t samplingFrequency = 0; + s32_t currentFrequency = 0; + s32_t nominalFrequency = 0; + s32_t carrierFrequencyShift = 0; + s32_t sign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + samplingFrequency = commonAttr->sysClockFreq/3; + + /* both registers are sign extended */ + nominalFrequency = extAttr->iqmFsRateOfs; + ARR32( devAddr, IQM_FS_RATE_LO__A, (pu32_t) ¤tFrequency ); + + if ( extAttr->posImage == TRUE ) + { + /* negative image */ + carrierFrequencyShift = nominalFrequency - currentFrequency; + } else { + /* positive image */ + carrierFrequencyShift = currentFrequency - nominalFrequency; + } + + /* carrier Frequency Shift In Hz */ + if (carrierFrequencyShift < 0) + { + sign = -1; + carrierFrequencyShift *= sign; + } + + /* *CTLFreq = carrierFrequencyShift * 50.625e6 / (1 << 28); */ + Mult32 ( carrierFrequencyShift, samplingFrequency, &data64Hi, &data64Lo ); + *CTLFreq = (s32_t)((((data64Lo >> 28) & 0xf) | (data64Hi << 4)) * sign); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetAgcRf () +* \brief Configure RF AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + if (atomic) + { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } + else + { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active*/ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + u16_t data = 0; + + switch ( agcSettings->ctrlMode ) + { + case DRX_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A, data ); + + /* Enable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + if ( extAttr->standard == DRX_STANDARD_8VSB ) + { + data |= ( 2 << SCU_RAM_AGC_KI_RF__B ); + } + else if (DRXJ_ISQAMSTD( extAttr->standard )) + { + data |= ( 5 << SCU_RAM_AGC_KI_RF__B ); + } + else + { + data |= ( 4 << SCU_RAM_AGC_KI_RF__B ); + } + + if (commonAttr->tunerRfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Set speed ( using complementary reduction value ) */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , + (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) + & SCU_RAM_AGC_KI_RED_RAGC_RED__M ) + | data, 0 )); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbIfAgcCfg); + else if (DRXJ_ISQAMSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->qamIfAgcCfg); + else if (DRXJ_ISATVSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->atvIfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->top, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + agcSettings->top, 0 )); + } + + /* Cut-Off current */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + agcSettings->cutOffCurrent, 0 )); + break; + case DRX_AGC_CTRL_USER: + + /* Enable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + if (commonAttr->tunerRfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, agcSettings->outputLevel, 0 )); + break; + case DRX_AGC_CTRL_OFF: + + /* Disable RF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU RF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RF__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + } + + /* Store rf agc settings */ + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbRfAgcCfg = *agcSettings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamRfAgcCfg = *agcSettings; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvRfAgcCfg = *agcSettings; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAgcRf () +* \brief get configuration of RF AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +GetAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Return stored AGC settings */ + standard = agcSettings->standard; + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbRfAgcCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamRfAgcCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvRfAgcCfg; + break; +#endif + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active. */ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + SARR16( devAddr, SCU_RAM_AGC_RF_IACCU_HI__A, + &(agcSettings->outputLevel)); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetAgcIf () +* \brief Configure If AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXJCfgAgc_t pAgcSettings = NULL; + pDRXCommonAttr_t commonAttr = NULL; + DRXWriteReg16Func_t ScuWr16 = NULL; + DRXReadReg16Func_t ScuRr16 = NULL; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + if (atomic) + { + ScuRr16 = DRXJ_DAP_SCU_AtomicReadReg16; + ScuWr16 = DRXJ_DAP_SCU_AtomicWriteReg16; + } + else + { + ScuRr16 = DRXJ_DAP.readReg16Func; + ScuWr16 = DRXJ_DAP.writeReg16Func; + } + + /* Configure AGC only if standard is currently active*/ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + u16_t data = 0; + + switch ( agcSettings->ctrlMode ) + { + case DRX_AGC_CTRL_AUTO: + /* Enable IF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Enable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data &= ~SCU_RAM_AGC_KI_IF__M; + if ( extAttr->standard == DRX_STANDARD_8VSB ) + { + data |= (3 << SCU_RAM_AGC_KI_IF__B ); + } + else if (DRXJ_ISQAMSTD( extAttr->standard )) + { + data |= (6 << SCU_RAM_AGC_KI_IF__B ); + } + else + { + data |= ( 5 << SCU_RAM_AGC_KI_IF__B ); + } + + if (commonAttr->tunerIfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI_RED__A , &data, 0 )); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI_RED__A , + (~(agcSettings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) + & SCU_RAM_AGC_KI_RED_IAGC_RED__M ) + | data, 0 )); + + if (agcSettings->standard == DRX_STANDARD_8VSB) + pAgcSettings = &(extAttr->vsbRfAgcCfg); + else if (DRXJ_ISQAMSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->qamRfAgcCfg); + else if (DRXJ_ISATVSTD( agcSettings->standard )) + pAgcSettings = &(extAttr->atvRfAgcCfg); + else + return (DRX_STS_INVALID_ARG); + + /* Restore TOP */ + if ( pAgcSettings->ctrlMode == DRX_AGC_CTRL_AUTO) + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcSettings->top, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + pAgcSettings->top, 0 )); + } + else + { + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0 )); + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0 )); + } + break; + + case DRX_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + if (commonAttr->tunerIfAgcPol) + { + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + } + else + { + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + } + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + + /* Write value to output pin */ + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + agcSettings->outputLevel, 0 )); + break; + + case DRX_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); + WR16( devAddr, IQM_AF_STDBY__A , data ); + + /* Disable SCU IF AGC loop */ + CHK_ERROR((*ScuRr16)( devAddr, SCU_RAM_AGC_KI__A, &data, 0 )); + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + CHK_ERROR((*ScuWr16)( devAddr, SCU_RAM_AGC_KI__A, data, 0 )); + break; + default: + return (DRX_STS_INVALID_ARG); + } /* switch ( agcsettings->ctrlMode ) */ + + /* always set the top to support configurations without if-loop */ + CHK_ERROR((*ScuWr16)( devAddr, + SCU_RAM_AGC_INGAIN_TGT_MIN__A, + agcSettings->top, + 0 ) ); + } + + /* Store if agc settings */ + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbIfAgcCfg = *agcSettings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + extAttr->qamIfAgcCfg = *agcSettings; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + extAttr->atvIfAgcCfg = *agcSettings; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetAgcIf () +* \brief get configuration of If AGC +* \param demod instance of demodulator. +* \param agcSettings AGC configuration structure +* \return DRXStatus_t. +*/ +static DRXStatus_t +GetAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Return stored ATV AGC settings */ + standard = agcSettings->standard; + switch ( agcSettings->standard){ + case DRX_STANDARD_8VSB: + *agcSettings = extAttr->vsbIfAgcCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + *agcSettings = extAttr->qamIfAgcCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + *agcSettings = extAttr->atvIfAgcCfg; + break; +#endif + default: + return (DRX_STS_ERROR); + } + agcSettings->standard = standard; + + /* Get AGC output only if standard is currently active */ + if ( ( extAttr->standard == agcSettings->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( agcSettings->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( agcSettings->standard ) ) ) + { + /* read output level */ + SARR16( devAddr, SCU_RAM_AGC_IF_IACCU_HI__A, + &(agcSettings->outputLevel) ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetIqmAf () +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetIqmAf ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + /* Configure IQM */ + RR16( devAddr, IQM_AF_STDBY__A , &data ); + if( !active ) + { + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE) + ); + } + else /* active */ + { + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE + | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE + | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE + | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE + ); + } + WR16( devAddr, IQM_AF_STDBY__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + + +/** +* \fn DRXStatus_t PowerDownVSB () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +PowerDownVSB( pDRXDemodInstance_t demod, Bool_t primary ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* + STOP demodulator + reset of FEC and VSB HW + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t SetVSBLeakNGain () +* \brief Set ATSC demod. +* \param demod instance of demodulator. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetVSBLeakNGain ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + + const u8_t vsb_ffe_leak_gain_ram0[]= { + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO1 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO2 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO3 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO4 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO5 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO6 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO7 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO8 */ + DRXJ_16TO8( 0xf ), /* FFETRAINLKRATIO9 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO10 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO11 */ + DRXJ_16TO8( 0x8 ), /* FFETRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1TRAINLKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1TRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA1DATALKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA1DATALKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2TRAINLKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2TRAINLKRATIO12 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO1 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO2 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO3 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO4 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO5 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO6 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO7 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO8 */ + DRXJ_16TO8( 0x20 ), /* FFERCA2DATALKRATIO9 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO10 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO11 */ + DRXJ_16TO8( 0x10 ), /* FFERCA2DATALKRATIO12 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO1 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO2 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO3 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO4 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO5 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO6 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO7 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO8 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1TRAINLKRATIO9 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO10 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO11 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1TRAINLKRATIO12 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO1 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO2 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO3 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO4 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO5 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO6 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO7 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO8 */ + DRXJ_16TO8( 0x0e ), /* FFEDDM1DATALKRATIO9 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO10 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO11 */ + DRXJ_16TO8( 0x07 ), /* FFEDDM1DATALKRATIO12 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO1 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO2 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO3 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO4 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO5 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO6 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO7 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO8 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2TRAINLKRATIO9 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO10 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO11 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2TRAINLKRATIO12 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO1 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO2 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO3 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO4 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO5 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO6 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO7 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO8 */ + DRXJ_16TO8( 0x0c ), /* FFEDDM2DATALKRATIO9 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO10 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO11 */ + DRXJ_16TO8( 0x06 ), /* FFEDDM2DATALKRATIO12 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN1 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN2 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN3 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN4 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN5 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN6 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN7 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN8 */ + DRXJ_16TO8( 0x4040 ), /* FIRTRAINGAIN9 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN10 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN11 */ + DRXJ_16TO8( 0x2020 ), /* FIRTRAINGAIN12 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN1 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN2 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN3 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN4 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN5 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN6 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN7 */ + DRXJ_16TO8( 0x1010 ) /* FIRRCA1GAIN8 */ + }; + + const u8_t vsb_ffe_leak_gain_ram1[]= { + DRXJ_16TO8( 0x1010 ), /* FIRRCA1GAIN9 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN10 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN11 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA1GAIN12 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN1 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN2 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN3 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN4 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN5 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN6 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN7 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN8 */ + DRXJ_16TO8( 0x1010 ), /* FIRRCA2GAIN9 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN10 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN11 */ + DRXJ_16TO8( 0x0808 ), /* FIRRCA2GAIN12 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN1 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN2 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN3 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN4 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN5 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN6 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN7 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN8 */ + DRXJ_16TO8( 0x0606 ), /* FIRDDM1GAIN9 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN10 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN11 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM1GAIN12 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN1 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN2 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN3 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN4 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN5 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN6 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN7 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN8 */ + DRXJ_16TO8( 0x0505 ), /* FIRDDM2GAIN9 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN10 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN11 */ + DRXJ_16TO8( 0x0303 ), /* FIRDDM2GAIN12 */ + DRXJ_16TO8( 0x001f ), /* DFETRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFERCA1TRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFERCA1DATALKRATIO */ + DRXJ_16TO8( 0x004f ), /* DFERCA2TRAINLKRATIO */ + DRXJ_16TO8( 0x004f ), /* DFERCA2DATALKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFEDDM1TRAINLKRATIO */ + DRXJ_16TO8( 0x01ff ), /* DFEDDM1DATALKRATIO */ + DRXJ_16TO8( 0x0352 ), /* DFEDDM2TRAINLKRATIO */ + DRXJ_16TO8( 0x0352 ), /* DFEDDM2DATALKRATIO */ + DRXJ_16TO8( 0x0000 ), /* DFETRAINGAIN */ + DRXJ_16TO8( 0x2020 ), /* DFERCA1GAIN */ + DRXJ_16TO8( 0x1010 ), /* DFERCA2GAIN */ + DRXJ_16TO8( 0x1818 ), /* DFEDDM1GAIN */ + DRXJ_16TO8( 0x1212 ) /* DFEDDM2GAIN */ + }; + + devAddr = demod -> myI2CDevAddr; + WRB ( devAddr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, + sizeof(vsb_ffe_leak_gain_ram0), ((pu8_t)vsb_ffe_leak_gain_ram0) ); + WRB ( devAddr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, + sizeof(vsb_ffe_leak_gain_ram1), ((pu8_t)vsb_ffe_leak_gain_ram1) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetVSB() +* \brief Set 8VSB demod. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +SetVSB ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t cmdResult = 0; + u16_t cmdParam = 0; + pDRXCommonAttr_t commonAttr = NULL; + DRXJSCUCmd_t cmdSCU; + pDRXJData_t extAttr = NULL; + const u8_t vsb_taps_re[]= { + DRXJ_16TO8( -2 ), /* re0 */ + DRXJ_16TO8( 4 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 1 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -3 ), /* re6 */ + DRXJ_16TO8( -3 ), /* re7 */ + DRXJ_16TO8( 6 ), /* re8 */ + DRXJ_16TO8( 1 ), /* re9 */ + DRXJ_16TO8( -9 ), /* re10 */ + DRXJ_16TO8( 3 ), /* re11 */ + DRXJ_16TO8( 12 ), /* re12 */ + DRXJ_16TO8( -9 ), /* re13 */ + DRXJ_16TO8( -15 ), /* re14 */ + DRXJ_16TO8( 17 ), /* re15 */ + DRXJ_16TO8( 19 ), /* re16 */ + DRXJ_16TO8( -29 ), /* re17 */ + DRXJ_16TO8( -22 ), /* re18 */ + DRXJ_16TO8( 45 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -70 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 111 ), /* re23 */ + DRXJ_16TO8( 30 ), /* re24 */ + DRXJ_16TO8( -201 ), /* re25 */ + DRXJ_16TO8( -31 ), /* re26 */ + DRXJ_16TO8( 629 ) /* re27 */ + }; + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + + /* reset demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16( devAddr, IQM_AF_DCF_BYPASS__A, 1 ); + WR16( devAddr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB ); + WR16( devAddr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB ); + extAttr->iqmRcRateOfs = 0x00AD0D79; + WR32( devAddr, IQM_RC_RATE_OFS_LO__A, extAttr->iqmRcRateOfs ); + WR16( devAddr, VSB_TOP_CFAGC_GAINSHIFT__A, 4); + WR16( devAddr, VSB_TOP_CYGN1TRK__A, 1); + + WR16( devAddr, IQM_RC_CROUT_ENA__A, 1 ); + WR16( devAddr, IQM_RC_STRETCH__A, 28 ); + WR16( devAddr, IQM_RT_ACTIVE__A, 0 ); + WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); + WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); + WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M ); + WR16( devAddr, IQM_CF_SCALE__A, 1393 ); + WR16( devAddr, IQM_CF_SCALE_SH__A, 0 ); + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((pu8_t)vsb_taps_re) ); + + WR16( devAddr, VSB_TOP_BNTHRESH__A, 330 ); /* set higher threshold */ + WR16( devAddr, VSB_TOP_CLPLASTNUM__A, 90 ); /* burst detection on */ + WR16( devAddr, VSB_TOP_SNRTH_RCA1__A, 0x0042 ); /* drop thresholds by 1 dB */ + WR16( devAddr, VSB_TOP_SNRTH_RCA2__A, 0x0053 ); /* drop thresholds by 2 dB */ + WR16( devAddr, VSB_TOP_EQCTRL__A, 0x1 ); /* cma on */ + WR16( devAddr, SCU_RAM_GPIO__A, 0 ); /* GPIO */ + + /* Initialize the FEC Subsystem */ + WR16( devAddr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D ); + { + u16_t fecOcSncMode = 0; + RR16( devAddr, FEC_OC_SNC_MODE__A, &fecOcSncMode ); + /* output data even when not locked */ + WR16( devAddr, FEC_OC_SNC_MODE__A, fecOcSncMode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M ); + } + + /* set clip */ + WR16( devAddr, IQM_AF_CLP_LEN__A, 0); + WR16( devAddr, IQM_AF_CLP_TH__A, 470); + WR16( devAddr, IQM_AF_SNS_LEN__A, 0); + WR16( devAddr, VSB_TOP_SNRTH_PT__A, 0xD4 ); + /* no transparent, no A&C framing; parity is set in mpegoutput*/ + { + u16_t fecOcRegMode = 0; + RR16 ( devAddr, FEC_OC_MODE__A , &fecOcRegMode ); + WR16( devAddr, FEC_OC_MODE__A, fecOcRegMode & + (~(FEC_OC_MODE_TRANSPARENT__M + | FEC_OC_MODE_CLEAR__M + | FEC_OC_MODE_RETAIN_FRAMING__M) + ) ); + } + + WR16( devAddr, FEC_DI_TIMEOUT_LO__A, 0 ); /* timeout counter for restarting */ + WR16( devAddr, FEC_DI_TIMEOUT_HI__A, 3 ); + WR16( devAddr, FEC_RS_MODE__A, 0 ); /* bypass disabled */ + /* initialize RS packet error measurement parameters */ + WR16( devAddr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD ); + WR16( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE ); + + /* init measurement period of MER/SER */ + WR16( devAddr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD ); + WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); + + WR16( devAddr, VSB_TOP_CKGN1TRK__A, 128 ); + /* B-Input to ADC, PGA+filter in standby */ + if ( extAttr->hasLNA == FALSE ) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x02); + }; + + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->vsbIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->vsbRfAgcCfg), FALSE ) ); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t vsbPgaCfg = { DRX_STANDARD_8VSB, 0 }; + + vsbPgaCfg.gain = extAttr->vsbPgaCfg; + CHK_ERROR( CtrlSetCfgAfeGain( demod, &vsbPgaCfg ) ); + } + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->vsbPreSawCfg)) ); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR ( SetMPEGTEIHandling ( demod )); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + } + + /* TBD: what parameters should be set */ + cmdParam = 0x00; /* Default mode AGC on, etc */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16(devAddr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004 ); + WR16(devAddr, VSB_TOP_SNRTH_PT__A, 0x00D2 ); + WR16(devAddr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE + |VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M ); + WR16(devAddr, VSB_TOP_BEDETCTRL__A, 0x142 ); + WR16(devAddr, VSB_TOP_LBAGCREFLVL__A, 640 ); + WR16(devAddr, VSB_TOP_CYGN1ACQ__A, 4 ); + WR16(devAddr, VSB_TOP_CYGN1TRK__A, 2 ); + WR16(devAddr, VSB_TOP_CYGN2TRK__A, 3 ); + + /* start demodulator */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE ); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t PckErrs) +* \brief Get the values of packet error in 8VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBPostRSPckErr(pI2CDeviceAddr_t devAddr, pu16_t pckErrs) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t packetErrorsMant = 0; + u16_t packetErrorsExp = 0; + + RR16(devAddr, FEC_RS_NR_FAILURES__A, &data ); + packetErrorsMant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packetErrorsExp = (data & FEC_RS_NR_FAILURES_EXP__M) + >> FEC_RS_NR_FAILURES_EXP__B; + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + /* packet error rate = (error packet number) per second */ + /* 77.3 us is time for per packet */ + CHK_ZERO (period * prescale); + *pckErrs = (u16_t)FracTimes1e6(packetErrorsMant * (1 << packetErrorsExp), + (period * prescale * 77)); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBpostViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t bitErrorsMant = 0; + u16_t bitErrorsExp = 0; + + RR16 ( devAddr, FEC_RS_NR_BIT_ERRORS__A, &data ); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + bitErrorsMant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bitErrorsExp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + >> FEC_RS_NR_BIT_ERRORS_EXP__B; + + if ( ((bitErrorsMant << bitErrorsExp) >> 3) > 68700) + *ber = 26570; + else + { + CHK_ZERO (period * prescale); + *ber = FracTimes1e6(bitErrorsMant << ((bitErrorsExp > 2)? (bitErrorsExp - 3):bitErrorsExp), + period * prescale * 207 * ((bitErrorsExp > 2)?1:8) ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBpreViterbiBer(pI2CDeviceAddr_t devAddr, pu32_t ber) +{ + u16_t data = 0; + + RR16 ( devAddr, VSB_TOP_NR_SYM_ERRS__A, &data ); + *ber = FracTimes1e6( data, VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static short GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static DRXStatus_t +GetVSBSymbErr(pI2CDeviceAddr_t devAddr, pu32_t ser) +{ + u16_t data = 0; + u16_t period = 0; + u16_t prescale = 0; + u16_t symbErrorsMant = 0; + u16_t symbErrorsExp = 0; + + RR16 ( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &data ); + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + symbErrorsMant = data & FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M; + symbErrorsExp = (data & FEC_RS_NR_SYMBOL_ERRORS_EXP__M) + >> FEC_RS_NR_SYMBOL_ERRORS_EXP__B; + + CHK_ZERO (period * prescale); + *ser = (u32_t)FracTimes1e6((symbErrorsMant << symbErrorsExp) * 1000, + (period * prescale * 77318)); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn static DRXStatus_t GetVSBMER(pI2CDeviceAddr_t devAddr, pu16_t mer) +* \brief Get the values of MER +* \return Error code +*/ +static DRXStatus_t +GetVSBMER (pI2CDeviceAddr_t devAddr, pu16_t mer) +{ + u16_t dataHi = 0; + + RR16( devAddr, VSB_TOP_ERR_ENERGY_H__A, &dataHi ); + *mer = (u16_t)(Log10Times100( 21504 ) - Log10Times100( (dataHi << 6) / 52 )); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetVSBConstel() +* \brief Retreive a VSB constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetVSBConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + pI2CDeviceAddr_t devAddr = NULL; /**< device address */ + u16_t vsbTopCommMb = 0; /**< VSB SL MB configuration */ + u16_t vsbTopCommMbInit = 0; /**< VSB SL MB intial configuration */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + + /* read device info */ + devAddr = demod -> myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16( devAddr, VSB_TOP_COMM_MB__A, &vsbTopCommMbInit ); + /* set observe flag & MB mux */ + vsbTopCommMb = (vsbTopCommMbInit | + VSB_TOP_COMM_MB_OBS_OBS_ON | + VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 ); + WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMb ); + + /* Enable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, FEC_OC_OCR_MODE_GRAB_ENABLE__M ); + + /* Disable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, 0x0 ); + + /* read data */ + RR32( devAddr, FEC_OC_OCR_GRAB_RD1__A, &data ); + re = (u16_t)(((data >> 10) & 0x300 ) | ((data >> 2) & 0xff)); + if (re & 0x0200) + { + re |= 0xfc00; + } + complexNr->re = re; + complexNr->im = 0; + + /* Restore MB (Monitor bus) */ + WR16( devAddr, VSB_TOP_COMM_MB__A, vsbTopCommMbInit ); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ +/*== END 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/** +* \fn DRXStatus_t PowerDownQAM () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +PowerDownQAM( pDRXDemodInstance_t demod, Bool_t primary ) +{ + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + STOP demodulator + resets IQM, QAM and FEC HW blocks + */ + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); + WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAMMeasurement () +* \brief Setup of the QAM Measuremnt intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return DRXStatus_t. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +* TODO: overriding the extAttr->fecBitsDesired by constellation dependent +* constants to get a measurement period of approx. 1 sec. Remove fecBitsDesired +* field ? +* +*/ +#ifndef DRXJ_VSB_ONLY +static DRXStatus_t +SetQAMMeasurement ( pDRXDemodInstance_t demod, + DRXConstellation_t constellation, + u32_t symbolRate ) +{ + pI2CDeviceAddr_t devAddr = NULL; /* device address for I2C writes */ + pDRXJData_t extAttr = NULL; /* Global data container for DRXJ specif data */ + u32_t fecBitsDesired = 0; /* BER accounting period */ + u16_t fecRsPlen = 0; /* defines RS BER measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u32_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + u32_t fecRsBitCnt = 0; /* Actual precise amount of bits */ + u32_t fecOcSncFailPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdPeriod = 0; /* Value for corresponding I2C register */ + u32_t qamVdBitCnt = 0; /* Actual precise amount of bits */ + u16_t fecVdPlen = 0; /* no of trellis symbols: VD SER measur period */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + fecBitsDesired = extAttr->fecBitsDesired; + fecRsPrescale = extAttr->fecRsPrescale; + + switch ( constellation ) { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* Parameters for Reed-Solomon Decoder */ + /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ + /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* TODO: use constant instead of calculation and remove the fecRsPlen in extAttr */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + fecRsPlen = 204 * 8; + break; + case DRX_STANDARD_ITU_B: + fecRsPlen = 128 * 7; + break; + default: + return (DRX_STS_INVALID_ARG); + } + + extAttr->fecRsPlen = fecRsPlen; /* for getSigQual */ + fecRsBitCnt = fecRsPrescale * fecRsPlen; /* temp storage */ + CHK_ZERO (fecRsBitCnt); + fecRsPeriod = fecBitsDesired / fecRsBitCnt + 1; /* ceil */ + if (extAttr->standard != DRX_STANDARD_ITU_B) + fecOcSncFailPeriod = fecRsPeriod; + + /* limit to max 16 bit value (I2C register width) if needed */ + if ( fecRsPeriod > 0xFFFF ) + fecRsPeriod = 0xFFFF; + + /* write corresponding registers */ + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + break; + case DRX_STANDARD_ITU_B: + switch ( constellation ) { + case DRX_CONSTELLATION_QAM64: + fecRsPeriod = 31581; + fecOcSncFailPeriod = 17932; + break; + case DRX_CONSTELLATION_QAM256: + fecRsPeriod = 45446; + fecOcSncFailPeriod = 25805; + break; + default: + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + + WR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A , ( u16_t ) fecOcSncFailPeriod ); + WR16 ( devAddr, FEC_RS_MEASUREMENT_PERIOD__A , ( u16_t ) fecRsPeriod ); + WR16 ( devAddr, FEC_RS_MEASUREMENT_PRESCALE__A , fecRsPrescale ); + extAttr->fecRsPeriod = (u16_t) fecRsPeriod; + extAttr->fecRsPrescale = fecRsPrescale; + WR32( devAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_MEAS_COUNT__A, 0 ); + WR16( devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0 ); + + if (extAttr->standard == DRX_STANDARD_ITU_B) + { + /* Parameters for Viterbi Decoder */ + /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ + /* (qamvd_prescale*plen*(qam_constellation+1))) */ + /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* a(8 bit) * b(8 bit) = 16 bit result => Mult32 not needed */ + fecVdPlen = extAttr->fecVdPlen; + qamVdPrescale = extAttr->qamVdPrescale; + qamVdBitCnt = qamVdPrescale * fecVdPlen; /* temp storage */ + + switch ( constellation ) { + case DRX_CONSTELLATION_QAM64: + /* a(16 bit) * b(4 bit) = 20 bit result => Mult32 not needed */ + qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ) + * ( QAM_TOP_CONSTELLATION_QAM64 + 1 ); + break; + case DRX_CONSTELLATION_QAM256: + /* a(16 bit) * b(5 bit) = 21 bit result => Mult32 not needed */ + qamVdPeriod = qamVdBitCnt * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ) + * ( QAM_TOP_CONSTELLATION_QAM256 + 1 ); + break; + default: + return (DRX_STS_INVALID_ARG); + } + CHK_ZERO (qamVdPeriod); + qamVdPeriod = fecBitsDesired / qamVdPeriod; + /* limit to max 16 bit value (I2C register width) if needed */ + if ( qamVdPeriod > 0xFFFF ) + qamVdPeriod = 0xFFFF; + + /* a(16 bit) * b(16 bit) = 32 bit result => Mult32 not needed */ + qamVdBitCnt *= qamVdPeriod; + + WR16 ( devAddr, QAM_VD_MEASUREMENT_PERIOD__A , ( u16_t ) qamVdPeriod ); + WR16 ( devAddr, QAM_VD_MEASUREMENT_PRESCALE__A , qamVdPrescale ); + extAttr->qamVdPeriod = (u16_t) qamVdPeriod; + extAttr->qamVdPrescale = qamVdPrescale; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM16 () +* \brief QAM16 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM16 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 2 ), /* fun0 */ + DRXJ_16TO8( 2 ), /* fun1 */ + DRXJ_16TO8( 2 ), /* fun2 */ + DRXJ_16TO8( 2 ), /* fun3 */ + DRXJ_16TO8( 3 ), /* fun4 */ + DRXJ_16TO8( 3 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 13517 ), /* RAD0 */ + DRXJ_16TO8( 13517 ), /* RAD1 */ + DRXJ_16TO8( 13517 ), /* RAD2 */ + DRXJ_16TO8( 13517 ), /* RAD3 */ + DRXJ_16TO8( 13517 ), /* RAD4 */ + DRXJ_16TO8( 13517 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 120); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 230); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 95); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 105); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-24) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-65)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-127)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 240); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM32 () +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM32 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 3 ), /* fun0 */ + DRXJ_16TO8( 3 ), /* fun1 */ + DRXJ_16TO8( 3 ), /* fun2 */ + DRXJ_16TO8( 3 ), /* fun3 */ + DRXJ_16TO8( 4 ), /* fun4 */ + DRXJ_16TO8( 4 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 6707 ), /* RAD0 */ + DRXJ_16TO8( 6707 ), /* RAD1 */ + DRXJ_16TO8( 6707 ), /* RAD2 */ + DRXJ_16TO8( 6707 ), /* RAD3 */ + DRXJ_16TO8( 6707 ), /* RAD4 */ + DRXJ_16TO8( 6707 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 90); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 170); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16_t)(-8) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16_t)(-16) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-26) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-56)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-86)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 176); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM64 () +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM64 ( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { /* this is hw reset value. no necessary to re-write */ + DRXJ_16TO8( 4 ), /* fun0 */ + DRXJ_16TO8( 4 ), /* fun1 */ + DRXJ_16TO8( 4 ), /* fun2 */ + DRXJ_16TO8( 4 ), /* fun3 */ + DRXJ_16TO8( 6 ), /* fun4 */ + DRXJ_16TO8( 6 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 13336 ), /* RAD0 */ + DRXJ_16TO8( 12618 ), /* RAD1 */ + DRXJ_16TO8( 11988 ), /* RAD2 */ + DRXJ_16TO8( 13809 ), /* RAD3 */ + DRXJ_16TO8( 13809 ), /* RAD4 */ + DRXJ_16TO8( 15609 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 105); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 195); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 84); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-15)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16_t)(-45)); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-80)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 160); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM128 () +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM128( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 6 ), /* fun0 */ + DRXJ_16TO8( 6 ), /* fun1 */ + DRXJ_16TO8( 6 ), /* fun2 */ + DRXJ_16TO8( 6 ), /* fun3 */ + DRXJ_16TO8( 9 ), /* fun4 */ + DRXJ_16TO8( 9 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 6164 ), /* RAD0 */ + DRXJ_16TO8( 6598 ), /* RAD1 */ + DRXJ_16TO8( 6394 ), /* RAD2 */ + DRXJ_16TO8( 6409 ), /* RAD3 */ + DRXJ_16TO8( 6656 ), /* RAD4 */ + DRXJ_16TO8( 7238 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 140); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 100); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3 ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16_t)(-1) ); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-23)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 144); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t SetQAM256 () +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM256( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = demod -> myI2CDevAddr; + const u8_t qamDqQualFun[]= { + DRXJ_16TO8( 8 ), /* fun0 */ + DRXJ_16TO8( 8 ), /* fun1 */ + DRXJ_16TO8( 8 ), /* fun2 */ + DRXJ_16TO8( 8 ), /* fun3 */ + DRXJ_16TO8( 12 ), /* fun4 */ + DRXJ_16TO8( 12 ), /* fun5 */ + }; + const u8_t qamEqCmaRad[]= { + DRXJ_16TO8( 12345 ), /* RAD0 */ + DRXJ_16TO8( 12345 ), /* RAD1 */ + DRXJ_16TO8( 13626 ), /* RAD2 */ + DRXJ_16TO8( 12931 ), /* RAD3 */ + DRXJ_16TO8( 14719 ), /* RAD4 */ + DRXJ_16TO8( 15356 ), /* RAD5 */ + }; + + WRB ( devAddr, QAM_DQ_QUAL_FUN0__A, sizeof(qamDqQualFun), ((pu8_t)qamDqQualFun) ); + WRB ( devAddr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qamEqCmaRad), ((pu8_t)qamEqCmaRad) ); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RTH__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FTH__A, 60); + WR16 ( devAddr, SCU_RAM_QAM_FSM_PTH__A, 100); + WR16 ( devAddr, SCU_RAM_QAM_FSM_QTH__A, 150); + WR16 ( devAddr, SCU_RAM_QAM_FSM_CTH__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_FSM_MTH__A, 110); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3); + + WR16 ( devAddr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8); + WR16 ( devAddr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0); + WR16 ( devAddr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16_t)(-8)); + + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_FINE__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CA_COARSE__A, 40); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); + WR16 ( devAddr, SCU_RAM_QAM_LC_CP_COARSE__A, 255); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_FINE__A, 2); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25); + WR16 ( devAddr, SCU_RAM_QAM_LC_CI_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EP_COARSE__A, 24); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_FINE__A, 12); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_EI_COARSE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_FINE__A, 16); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF_COARSE__A, 80); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_FINE__A, 5); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15); + WR16 ( devAddr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16); + + WR16 ( devAddr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +#define QAM_SET_OP_ALL 0x1 +#define QAM_SET_OP_CONSTELLATION 0x2 +#define QAM_SET_OP_SPECTRUM 0X4 + +/** +* \fn DRXStatus_t SetQAM () +* \brief Set QAM demod. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAM( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + u32_t op + ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u16_t cmdResult = 0; + u32_t adcFrequency = 0; + u32_t iqmRcRate = 0; + u16_t lcSymbolFreq = 0; + u16_t iqmRcStretch = 0; + u16_t setEnvParameters = 0; + u16_t setParamParameters[2] = {0}; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + const u8_t qamA_taps[]= { + DRXJ_16TO8( -1 ), /* re0 */ + DRXJ_16TO8( 1 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -1 ), /* re3 */ + DRXJ_16TO8( -1 ), /* re4 */ + DRXJ_16TO8( 2 ), /* re5 */ + DRXJ_16TO8( 1 ), /* re6 */ + DRXJ_16TO8( -2 ), /* re7 */ + DRXJ_16TO8( 0 ), /* re8 */ + DRXJ_16TO8( 3 ), /* re9 */ + DRXJ_16TO8( -1 ), /* re10 */ + DRXJ_16TO8( -3 ), /* re11 */ + DRXJ_16TO8( 4 ), /* re12 */ + DRXJ_16TO8( 1 ), /* re13 */ + DRXJ_16TO8( -8 ), /* re14 */ + DRXJ_16TO8( 4 ), /* re15 */ + DRXJ_16TO8( 13 ), /* re16 */ + DRXJ_16TO8( -13 ), /* re17 */ + DRXJ_16TO8( -19 ), /* re18 */ + DRXJ_16TO8( 28 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -53 ), /* re21 */ + DRXJ_16TO8( -31 ), /* re22 */ + DRXJ_16TO8( 96 ), /* re23 */ + DRXJ_16TO8( 37 ), /* re24 */ + DRXJ_16TO8( -190 ), /* re25 */ + DRXJ_16TO8( -40 ), /* re26 */ + DRXJ_16TO8( 619 ) /* re27 */ + }; + const u8_t qamB64_taps[]= { + DRXJ_16TO8( 0 ), /* re0 */ + DRXJ_16TO8( -2 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( 2 ), /* re3 */ + DRXJ_16TO8( -2 ), /* re4 */ + DRXJ_16TO8( 0 ), /* re5 */ + DRXJ_16TO8( 4 ), /* re6 */ + DRXJ_16TO8( -2 ), /* re7 */ + DRXJ_16TO8( -4 ), /* re8 */ + DRXJ_16TO8( 4 ), /* re9 */ + DRXJ_16TO8( 3 ), /* re10 */ + DRXJ_16TO8( -6 ), /* re11 */ + DRXJ_16TO8( 0 ), /* re12 */ + DRXJ_16TO8( 6 ), /* re13 */ + DRXJ_16TO8( -5 ), /* re14 */ + DRXJ_16TO8( -3 ), /* re15 */ + DRXJ_16TO8( 11 ), /* re16 */ + DRXJ_16TO8( -4 ), /* re17 */ + DRXJ_16TO8( -19 ), /* re18 */ + DRXJ_16TO8( 19 ), /* re19 */ + DRXJ_16TO8( 28 ), /* re20 */ + DRXJ_16TO8( -45 ), /* re21 */ + DRXJ_16TO8( -36 ), /* re22 */ + DRXJ_16TO8( 90 ), /* re23 */ + DRXJ_16TO8( 42 ), /* re24 */ + DRXJ_16TO8( -185 ), /* re25 */ + DRXJ_16TO8( -46 ), /* re26 */ + DRXJ_16TO8( 614 ) /* re27 */ + }; + const u8_t qamB256_taps[]= { + DRXJ_16TO8( -2 ), /* re0 */ + DRXJ_16TO8( 4 ), /* re1 */ + DRXJ_16TO8( 1 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -2 ), /* re6 */ + DRXJ_16TO8( -4 ), /* re7 */ + DRXJ_16TO8( 5 ), /* re8 */ + DRXJ_16TO8( 2 ), /* re9 */ + DRXJ_16TO8( -8 ), /* re10 */ + DRXJ_16TO8( 2 ), /* re11 */ + DRXJ_16TO8( 11 ), /* re12 */ + DRXJ_16TO8( -8 ), /* re13 */ + DRXJ_16TO8( -15 ), /* re14 */ + DRXJ_16TO8( 16 ), /* re15 */ + DRXJ_16TO8( 19 ), /* re16 */ + DRXJ_16TO8( -27 ), /* re17 */ + DRXJ_16TO8( -22 ), /* re18 */ + DRXJ_16TO8( 44 ), /* re19 */ + DRXJ_16TO8( 26 ), /* re20 */ + DRXJ_16TO8( -69 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 110 ), /* re23 */ + DRXJ_16TO8( 31 ), /* re24 */ + DRXJ_16TO8( -201 ), /* re25 */ + DRXJ_16TO8( -32 ), /* re26 */ + DRXJ_16TO8( 628 ) /* re27 */ + }; + const u8_t qamC_taps[]= { + DRXJ_16TO8( -3 ), /* re0 */ + DRXJ_16TO8( 3 ), /* re1 */ + DRXJ_16TO8( 2 ), /* re2 */ + DRXJ_16TO8( -4 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 4 ), /* re5 */ + DRXJ_16TO8( -1 ), /* re6 */ + DRXJ_16TO8( -4 ), /* re7 */ + DRXJ_16TO8( 3 ), /* re8 */ + DRXJ_16TO8( 3 ), /* re9 */ + DRXJ_16TO8( -5 ), /* re10 */ + DRXJ_16TO8( 0 ), /* re11 */ + DRXJ_16TO8( 9 ), /* re12 */ + DRXJ_16TO8( -4 ), /* re13 */ + DRXJ_16TO8( -12 ), /* re14 */ + DRXJ_16TO8( 10 ), /* re15 */ + DRXJ_16TO8( 16 ), /* re16 */ + DRXJ_16TO8( -21 ), /* re17 */ + DRXJ_16TO8( -20 ), /* re18 */ + DRXJ_16TO8( 37 ), /* re19 */ + DRXJ_16TO8( 25 ), /* re20 */ + DRXJ_16TO8( -62 ), /* re21 */ + DRXJ_16TO8( -28 ), /* re22 */ + DRXJ_16TO8( 105 ), /* re23 */ + DRXJ_16TO8( 31 ), /* re24 */ + DRXJ_16TO8( -197 ), /* re25 */ + DRXJ_16TO8( -33 ), /* re26 */ + DRXJ_16TO8( 626 ) /* re27 */ + }; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) + { + case DRX_CONSTELLATION_QAM256 : + iqmRcRate = 0x00AE3562; + lcSymbolFreq = QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; + channel->symbolrate = 5360537; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_256; + break; + case DRX_CONSTELLATION_QAM64 : + iqmRcRate = 0x00C05A0E; + lcSymbolFreq = 409; + channel->symbolrate = 5056941; + iqmRcStretch = IQM_RC_STRETCH_QAM_B_64; + break; + default : + return (DRX_STS_INVALID_ARG); + } + } + else + { + adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; + CHK_ZERO (channel->symbolrate); + iqmRcRate = ( adcFrequency / channel->symbolrate ) * ( 1 << 21 ) + + ( Frac28 ( ( adcFrequency % channel->symbolrate ), channel->symbolrate ) >> 7 ) - ( 1 << 23 ); + lcSymbolFreq = (u16_t)( Frac28 ( channel->symbolrate + (adcFrequency >> 13), adcFrequency ) >> 16 ); + if (lcSymbolFreq > 511) + lcSymbolFreq = 511; + + iqmRcStretch = 21; + } + + if( extAttr->standard == DRX_STANDARD_ITU_A ) + { + setEnvParameters = QAM_TOP_ANNEX_A; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } + else if( extAttr->standard == DRX_STANDARD_ITU_B ) + { + setEnvParameters = QAM_TOP_ANNEX_B; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = channel->interleavemode; /* interleave mode */ + } + else if( extAttr->standard == DRX_STANDARD_ITU_C ) + { + setEnvParameters = QAM_TOP_ANNEX_C; /* annex */ + setParamParameters[0] = channel->constellation; /* constellation */ + setParamParameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } + else + { + return (DRX_STS_INVALID_ARG); + } + } + + if (op & QAM_SET_OP_ALL) + { + /* + STEP 1: reset demodulator + resets IQM, QAM and FEC HW blocks + resets SCU variables + */ + /* stop all comm_exec */ + WR16( devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP ); + WR16( devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + /* + STEP 2: configure demodulator + -set env + -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) + */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &setEnvParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmdSCU.parameterLen = 2; + cmdSCU.resultLen = 1; + cmdSCU.parameter = setParamParameters; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + /* set symbol rate */ + WR32( devAddr, IQM_RC_RATE_OFS_LO__A, iqmRcRate ); + extAttr->iqmRcRateOfs = iqmRcRate; + CHK_ERROR( SetQAMMeasurement ( demod, channel->constellation, channel->symbolrate)); + } + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ + /* from qam_cmd.py script (qam_driver_b)*/ + /* TODO: remove re-writes of HW reset values */ + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM )) + { + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + + WR16( devAddr, QAM_LC_SYMBOL_FREQ__A, lcSymbolFreq); + WR16( devAddr, IQM_RC_STRETCH__A, iqmRcStretch ); + } + + if (op & QAM_SET_OP_ALL) + { + if (extAttr->hasLNA==FALSE) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x02); + } + WR16( devAddr, IQM_CF_SYMMETRIC__A, 0 ); + WR16( devAddr, IQM_CF_MIDTAP__A, 3 ); + WR16( devAddr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M ); + + WR16( devAddr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f); /* scu temporary shut down agc */ + + WR16( devAddr, IQM_AF_SYNC_SEL__A, 3); + WR16( devAddr, IQM_AF_CLP_LEN__A, 0); + WR16( devAddr, IQM_AF_CLP_TH__A, 448); + WR16( devAddr, IQM_AF_SNS_LEN__A, 0); + WR16( devAddr, IQM_AF_PDREF__A, 4); + WR16( devAddr, IQM_AF_STDBY__A, 0x10); + WR16( devAddr, IQM_AF_PGA_GAIN__A, 11); + + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 1); + WR16( devAddr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); /*! reset default val ! */ + + WR16( devAddr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); /*! reset default val ! */ + if( extAttr->standard == DRX_STANDARD_ITU_B ) + { + WR16( devAddr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + } + else + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x04); + WR16( devAddr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE); /*! reset default val ! */ + break; + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + WR16( devAddr, QAM_SY_SYNC_LWM__A, 0x03); + WR16( devAddr, QAM_SY_SYNC_AWM__A, 0x05); + WR16( devAddr, QAM_SY_SYNC_HWM__A, 0x06); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } + + WR16( devAddr, QAM_LC_MODE__A, QAM_LC_MODE__PRE); /*! reset default val ! */ + WR16( devAddr, QAM_LC_RATE_LIMIT__A, 3); + WR16( devAddr, QAM_LC_LPF_FACTORP__A, 4); + WR16( devAddr, QAM_LC_LPF_FACTORI__A, 4); + WR16( devAddr, QAM_LC_MODE__A, 7); + WR16( devAddr, QAM_LC_QUAL_TAB0__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB1__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB2__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB3__A, 1); + WR16( devAddr, QAM_LC_QUAL_TAB4__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB5__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB6__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB8__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB9__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB10__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB12__A, 2); + WR16( devAddr, QAM_LC_QUAL_TAB15__A, 3); + WR16( devAddr, QAM_LC_QUAL_TAB16__A, 3); + WR16( devAddr, QAM_LC_QUAL_TAB20__A, 4); + WR16( devAddr, QAM_LC_QUAL_TAB25__A, 4); + + WR16( devAddr, IQM_FS_ADJ_SEL__A, 1); + WR16( devAddr, IQM_RC_ADJ_SEL__A, 1); + WR16( devAddr, IQM_CF_ADJ_SEL__A, 1); + WR16( devAddr, IQM_CF_POW_MEAS_LEN__A, 0); + WR16( devAddr, SCU_RAM_GPIO__A, 0 ); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + /* turn on IQMAF. It has to be in front of setAgc**() */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->qamIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->qamRfAgcCfg), FALSE ) ); + { + /* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead + of only the gain */ + DRXJCfgAfeGain_t qamPgaCfg = { DRX_STANDARD_ITU_B, 0 }; + + qamPgaCfg.gain = extAttr->qamPgaCfg; + CHK_ERROR( CtrlSetCfgAfeGain( demod, &qamPgaCfg ) ); + } + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->qamPreSawCfg)) ); + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + if( extAttr->standard == DRX_STANDARD_ITU_A ) + { + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamA_taps), ((pu8_t)qamA_taps) ); + } + else if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM64: + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB64_taps), ((pu8_t)qamB64_taps) ); + break; + case DRX_CONSTELLATION_QAM256: + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamB256_taps), ((pu8_t)qamB256_taps) ); + break; + default: + return (DRX_STS_ERROR); + } + } + else if ( extAttr->standard == DRX_STANDARD_ITU_C ) + { + WRB ( devAddr, IQM_CF_TAP_RE0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A, sizeof(qamC_taps), ((pu8_t)qamC_taps) ); + } + + /* SETP 4: constellation specific setup */ + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16: + CHK_ERROR(SetQAM16( demod )); + break; + case DRX_CONSTELLATION_QAM32: + CHK_ERROR(SetQAM32( demod )); + break; + case DRX_CONSTELLATION_QAM64: + CHK_ERROR(SetQAM64( demod )); + break; + case DRX_CONSTELLATION_QAM128: + CHK_ERROR(SetQAM128( demod )); + break; + case DRX_CONSTELLATION_QAM256: + CHK_ERROR(SetQAM256( demod )); + break; + default: + return (DRX_STS_ERROR); + } /* switch */ + } + + if ((op & QAM_SET_OP_ALL)) + { + WR16(devAddr, IQM_CF_SCALE_SH__A, 0 ); + + /* Mpeg output has to be in front of FEC active */ + CHK_ERROR ( SetMPEGTEIHandling( demod )); + CHK_ERROR ( BitReverseMPEGOutput( demod ) ); + CHK_ERROR ( SetMPEGStartWidth ( demod ) ); + { + /* TODO: move to setStandard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + DRXCfgMPEGOutput_t cfgMPEGOutput; + + cfgMPEGOutput.enableMPEGOutput = TRUE; + cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte; + cfgMPEGOutput.enableParallel = commonAttr->mpegCfg.enableParallel; + cfgMPEGOutput.invertDATA = commonAttr->mpegCfg.invertDATA; + cfgMPEGOutput.invertERR = commonAttr->mpegCfg.invertERR; + cfgMPEGOutput.invertSTR = commonAttr->mpegCfg.invertSTR; + cfgMPEGOutput.invertVAL = commonAttr->mpegCfg.invertVAL; + cfgMPEGOutput.invertCLK = commonAttr->mpegCfg.invertCLK; + cfgMPEGOutput.staticCLK = commonAttr->mpegCfg.staticCLK; + cfgMPEGOutput.bitrate = commonAttr->mpegCfg.bitrate; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION )) + { + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + } + + WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + WR16(devAddr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE ); + WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +static DRXStatus_t +CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ); +static DRXStatus_t +qamFlipSpec ( pDRXDemodInstance_t demod, + pDRXChannel_t channel) +{ + u32_t iqmFsRateOfs = 0; + u32_t iqmFsRateLo = 0; + u16_t qamCtlEna = 0; + u16_t data = 0; + u16_t equMode = 0; + u16_t fsmState = 0; + int i = 0; + int ofsofs = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Silence the controlling of lc, equ, and the acquisition state machine */ + RR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna + & ~ ( SCU_RAM_QAM_CTL_ENA_ACQ__M + | SCU_RAM_QAM_CTL_ENA_EQU__M + | SCU_RAM_QAM_CTL_ENA_LC__M) ); + + /* freeze the frequency control loop */ + WR16( devAddr, QAM_LC_CF__A, 0); + WR16( devAddr, QAM_LC_CF1__A, 0); + + ARR32( devAddr, IQM_FS_RATE_OFS_LO__A , &iqmFsRateOfs ); + ARR32( devAddr, IQM_FS_RATE_LO__A, &iqmFsRateLo ); + ofsofs = iqmFsRateLo - iqmFsRateOfs; + iqmFsRateOfs = ~iqmFsRateOfs + 1; + iqmFsRateOfs -= 2 * ofsofs; + + /* freeze dq/fq updating */ + RR16( devAddr, QAM_DQ_MODE__A, &data); + data = (data & 0xfff9); + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + /* lc_cp / _ci / _ca */ + WR16( devAddr, QAM_LC_CI__A, 0 ); + WR16( devAddr, QAM_LC_EP__A, 0 ); + WR16( devAddr, QAM_FQ_LA_FACTOR__A, 0 ); + + /* flip the spec */ + WR32( devAddr, IQM_FS_RATE_OFS_LO__A , iqmFsRateOfs ); + extAttr->iqmFsRateOfs = iqmFsRateOfs; + extAttr->posImage = (extAttr->posImage)?FALSE:TRUE; + + /* freeze dq/fq updating */ + RR16( devAddr, QAM_DQ_MODE__A, &data); + equMode = data; + data = (data & 0xfff9); + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + for ( i = 0; i < 28; i++) + { + RR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data); + WR16( devAddr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data); + } + + for ( i = 0; i < 24; i++) + { + RR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data); + WR16( devAddr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data); + } + + data = equMode; + WR16( devAddr, QAM_DQ_MODE__A, data ); + WR16( devAddr, QAM_FQ_MODE__A, data ); + + WR16( devAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4 ); + + i = 0; + while ( (fsmState != 4) && (i++ < 100) ) + { + RR16( devAddr, SCU_RAM_QAM_FSM_STATE__A, &fsmState ); + } + WR16( devAddr, SCU_RAM_QAM_CTL_ENA__A, (qamCtlEna | 0x0016) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); + +} + +#define NO_LOCK 0x0 +#define DEMOD_LOCKED 0x1 +#define SYNC_FLIPPED 0x2 +#define SPEC_MIRRORED 0x4 +/** +* \fn DRXStatus_t QAM64Auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tunerFreqOffset: tuner frequency offset. +* \param lockStatus: pointer to lock status. +* \return DRXStatus_t. +*/ +static DRXStatus_t +QAM64Auto( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + pDRXLockStatus_t lockStatus + ) +{ + DRXSigQuality_t sigQuality; + u16_t data = 0; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime= 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = 0; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod -> myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do + { + CHK_ERROR( CtrlLockStatus(demod, lockStatus) ); + + switch (state) + { + case NO_LOCK: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 208) + { + state = DEMOD_LOCKED; + /* some delay to see if fec_lock possible TODO find the right value */ + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); + state = SYNC_FLIPPED; + DRXBSP_HST_Sleep(10); + } + break; + case SYNC_FLIPPED: + if (*lockStatus == DRXJ_DEMOD_LOCK) + { + if (channel->mirror == DRX_MIRROR_AUTO) + { + /* flip sync pattern back */ + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data & 0xFFFE ); + /* flip spectrum */ + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR ( qamFlipSpec ( demod, channel ) ); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 500ms? */ + startTime = dLockedTime = DRXBSP_HST_Clock(); + timeoutOfs = 0; + } + else /* no need to wait lock */ + { + startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + case SPEC_MIRRORED: + if ((*lockStatus == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms*/ + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 208) + { + RR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, &data ); + WR16( demod->myI2CDevAddr, QAM_SY_TIMEOUT__A, data | 0x1 ); + /* no need to wait lock */ + startTime = DRXBSP_HST_Clock() - DRXJ_QAM_MAX_WAITTIME - timeoutOfs; + } + } + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ( ( *lockStatus != DRX_LOCKED ) && + ( *lockStatus != DRX_NEVER_LOCK ) && + ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) + ); + /* Returning control to apllication ... */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t QAM256Auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tunerFreqOffset: tuner frequency offset. +* \param lockStatus: pointer to lock status. +* \return DRXStatus_t. +*/ +static DRXStatus_t +QAM256Auto( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset, + pDRXLockStatus_t lockStatus + ) +{ + DRXSigQuality_t sigQuality; + u32_t state = NO_LOCK; + u32_t startTime = 0; + u32_t dLockedTime= 0; + pDRXJData_t extAttr = NULL; + u32_t timeoutOfs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod -> myExtAttr; + *lockStatus = DRX_NOT_LOCKED; + startTime = DRXBSP_HST_Clock(); + state = NO_LOCK; + do + { + CHK_ERROR( CtrlLockStatus( demod, lockStatus) ); + switch (state) + { + case NO_LOCK: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, &sigQuality ) ); + if (sigQuality.MER > 268) + { + state = DEMOD_LOCKED; + timeoutOfs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + dLockedTime = DRXBSP_HST_Clock(); + } + } + break; + case DEMOD_LOCKED: + if ( *lockStatus == DRXJ_DEMOD_LOCK ) + { + if ((channel->mirror == DRX_MIRROR_AUTO) && + ((DRXBSP_HST_Clock() - dLockedTime) > DRXJ_QAM_FEC_LOCK_WAITTIME)) + { + extAttr->mirror = DRX_MIRROR_YES; + CHK_ERROR ( qamFlipSpec ( demod, channel ) ); + state = SPEC_MIRRORED; + /* reset timer TODO: still need 300ms? */ + startTime = DRXBSP_HST_Clock(); + timeoutOfs = - DRXJ_QAM_MAX_WAITTIME / 2; + } + } + break; + case SPEC_MIRRORED: + break; + default: + break; + } + DRXBSP_HST_Sleep(10); + } while + ( ( *lockStatus < DRX_LOCKED ) && + ( *lockStatus != DRX_NEVER_LOCK ) && + ( (DRXBSP_HST_Clock() - startTime) < (DRXJ_QAM_MAX_WAITTIME + timeoutOfs)) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t SetQAMChannel () +* \brief Set QAM channel according to the requested constellation. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetQAMChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXFrequency_t tunerFreqOffset + ) +{ + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + Bool_t autoFlag = FALSE; + + /* external attributes for storing aquired channel constellation */ + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* set QAM channel constellation */ + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16 : + case DRX_CONSTELLATION_QAM32 : + case DRX_CONSTELLATION_QAM64 : + case DRX_CONSTELLATION_QAM128 : + case DRX_CONSTELLATION_QAM256 : + extAttr->constellation = channel->constellation; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL) ); + + if ( (extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->constellation == DRX_CONSTELLATION_QAM64) ) + { + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus)); + } + + if ( (extAttr->standard == DRX_STANDARD_ITU_B) && + (channel->mirror == DRX_MIRROR_AUTO) && + (channel->constellation == DRX_CONSTELLATION_QAM256) ) + { + CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus)); + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if ( extAttr->standard == DRX_STANDARD_ITU_B ) + { + autoFlag = TRUE; + /* try to lock default QAM constellation: QAM64 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + extAttr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_ALL ) ); + CHK_ERROR ( QAM256Auto( demod, channel, tunerFreqOffset, &lockStatus )); + + if ( lockStatus < DRX_LOCKED ) + { + /* QAM254 not locked -> try to lock QAM64 constellation */ + channel->constellation = DRX_CONSTELLATION_QAM64; + extAttr->constellation = DRX_CONSTELLATION_QAM64; + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ + + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); + } + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); + } + channel->constellation = DRX_CONSTELLATION_AUTO; + } + else if ( extAttr->standard == DRX_STANDARD_ITU_C ) + { + channel->constellation = DRX_CONSTELLATION_QAM64; + extAttr->constellation = DRX_CONSTELLATION_QAM64; + autoFlag = TRUE; + + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + { + u16_t qamCtlEna = 0; + RR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, &qamCtlEna ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna & ~SCU_RAM_QAM_CTL_ENA_ACQ__M ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_FSM_STATE_TGT__A, 0x2 ); /* force to rate hunting */ + + CHK_ERROR ( SetQAM( demod, channel, tunerFreqOffset, QAM_SET_OP_CONSTELLATION) ); + WR16( demod->myI2CDevAddr, SCU_RAM_QAM_CTL_ENA__A, qamCtlEna ); + } + CHK_ERROR ( QAM64Auto( demod, channel, tunerFreqOffset, &lockStatus )); + channel->constellation = DRX_CONSTELLATION_AUTO; + } + else + { + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_INVALID_ARG); + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + /* restore starting value */ + if (autoFlag) + channel->constellation = DRX_CONSTELLATION_AUTO; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn static short GetQAMRSErrCount(pI2CDeviceAddr_t devAddr) +* \brief Get RS error count in QAM mode (used for post RS BER calculation) +* \return Error code +* +* precondition: measurement period & measurement prescale must be set +* +*/ +static DRXStatus_t +GetQAMRSErrCount(pI2CDeviceAddr_t devAddr, pDRXJRSErrors_t RSErrors) +{ + u16_t nrBitErrors = 0, + nrSymbolErrors = 0, + nrPacketErrors = 0, + nrFailures = 0, + nrSncParFailCount = 0; + + /* check arguments */ + if ( devAddr == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + /* all reported errors are received in the */ + /* most recently finished measurment period */ + /* no of pre RS bit errors */ + RR16( devAddr, FEC_RS_NR_BIT_ERRORS__A, &nrBitErrors ); + /* no of symbol errors */ + RR16( devAddr, FEC_RS_NR_SYMBOL_ERRORS__A, &nrSymbolErrors ); + /* no of packet errors */ + RR16( devAddr, FEC_RS_NR_PACKET_ERRORS__A, &nrPacketErrors ); + /* no of failures to decode */ + RR16( devAddr, FEC_RS_NR_FAILURES__A, &nrFailures ); + /* no of post RS bit erros */ + RR16( devAddr, FEC_OC_SNC_FAIL_COUNT__A, &nrSncParFailCount ); + /* TODO: NOTE */ + /* These register values are fetched in non-atomic fashion */ + /* It is possible that the read values contain unrelated information */ + + RSErrors->nrBitErrors = nrBitErrors & FEC_RS_NR_BIT_ERRORS__M; + RSErrors->nrSymbolErrors = nrSymbolErrors & FEC_RS_NR_SYMBOL_ERRORS__M; + RSErrors->nrPacketErrors = nrPacketErrors & FEC_RS_NR_PACKET_ERRORS__M; + RSErrors->nrFailures = nrFailures & FEC_RS_NR_FAILURES__M; + RSErrors->nrSncParFailCount = nrSncParFailCount & FEC_OC_SNC_FAIL_COUNT__M; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetQAMSigQuality() +* \brief Retreive QAM signal quality from device. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality data. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_INVALID_ARG sigQuality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. + +* Pre-condition: Device must be started and in lock. +*/ +static DRXStatus_t +CtrlGetQAMSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXConstellation_t constellation = DRX_CONSTELLATION_UNKNOWN; + DRXJRSErrors_t measuredRSErrors = { 0, 0, 0, 0, 0 }; + + u32_t preBitErrRS = 0; /* pre RedSolomon Bit Error Rate */ + u32_t postBitErrRS = 0; /* post RedSolomon Bit Error Rate */ + u32_t pktErrs = 0; /* no of packet errors in RS */ + u16_t qamSlErrPower = 0; /* accumulated error between raw and sliced symbols */ + u16_t qsymErrVD = 0; /* quadrature symbol errors in QAM_VD */ + u16_t fecOcPeriod = 0; /* SNC sync failure measurement period */ + u16_t fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod = 0; /* Value for corresponding I2C register */ + /* calculation constants */ + u32_t rsBitCnt = 0; /* RedSolomon Bit Count */ + u32_t qamSlSigPower = 0; /* used for MER, depends of QAM constellation */ + /* intermediate results */ + u32_t e = 0; /* exponent value used for QAM BER/SER */ + u32_t m = 0; /* mantisa value used for QAM BER/SER */ + u32_t berCnt = 0; /* BER count */ + /* signal quality info */ + u32_t qamSlMer = 0; /* QAM MER */ + u32_t qamPreRSBer = 0; /* Pre RedSolomon BER */ + u32_t qamPostRSBer = 0; /* Post RedSolomon BER */ + u32_t qamVDSer = 0; /* ViterbiDecoder SER */ + u16_t qamVdPrescale = 0; /* Viterbi Measurement Prescale */ + u16_t qamVdPeriod = 0; /* Viterbi Measurement period */ + u32_t vdBitCnt = 0; /* ViterbiDecoder Bit Count */ + + /* get device basic information */ + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + constellation = extAttr->constellation; + + /* read the physical registers */ + /* Get the RS error data */ + CHK_ERROR ( GetQAMRSErrCount ( devAddr, &measuredRSErrors ) ); + /* get the register value needed for MER */ + RR16( devAddr, QAM_SL_ERR_POWER__A, &qamSlErrPower ); + /* get the register value needed for post RS BER */ + RR16 ( devAddr, FEC_OC_SNC_FAIL_PERIOD__A, &fecOcPeriod ); + + /* get constants needed for signal quality calculation */ + fecRsPeriod = extAttr->fecRsPeriod; + fecRsPrescale = extAttr->fecRsPrescale; + rsBitCnt = fecRsPeriod * fecRsPrescale * extAttr->fecRsPlen; + qamVdPeriod = extAttr->qamVdPeriod; + qamVdPrescale = extAttr->qamVdPrescale; + vdBitCnt = qamVdPeriod * qamVdPrescale * extAttr->fecVdPlen; + + /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ + switch ( constellation ) + { + case DRX_CONSTELLATION_QAM16: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case DRX_CONSTELLATION_QAM32: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case DRX_CONSTELLATION_QAM64: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case DRX_CONSTELLATION_QAM128: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + break; + case DRX_CONSTELLATION_QAM256: + qamSlSigPower = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + break; + default: + return (DRX_STS_ERROR); + } + + /* ------------------------------ */ + /* MER Calculation */ + /* ------------------------------ */ + /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ + + /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ + if ( qamSlErrPower == 0 ) + qamSlMer = 0; + else + qamSlMer = Log10Times100( qamSlSigPower ) - Log10Times100( ( u32_t ) qamSlErrPower ); + + + /* ----------------------------------------- */ + /* Pre Viterbi Symbol Error Rate Calculation */ + /* ----------------------------------------- */ + /* pre viterbi SER is good if it is bellow 0.025 */ + + /* get the register value */ + /* no of quadrature symbol errors */ + RR16( devAddr, QAM_VD_NR_QSYM_ERRORS__A , &qsymErrVD ); + /* Extract the Exponent and the Mantisa */ + /* of number of quadrature symbol errors */ + e = ( qsymErrVD & QAM_VD_NR_QSYM_ERRORS_EXP__M ) >> + QAM_VD_NR_QSYM_ERRORS_EXP__B; + m = ( qsymErrVD & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M ) >> + QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; + + if ( (m << e) >> 3 > 549752 ) /* the max of FracTimes1e6 */ + { + qamVDSer = 500000; /* clip BER 0.5 */ + } + else + { + qamVDSer = FracTimes1e6(m << ((e > 2)? (e - 3):e), vdBitCnt * ((e > 2)?1:8) / 8 ); + } + + /* --------------------------------------- */ + /* pre and post RedSolomon BER Calculation */ + /* --------------------------------------- */ + /* pre RS BER is good if it is below 3.5e-4 */ + + /* get the register values */ + preBitErrRS = ( u32_t ) measuredRSErrors.nrBitErrors; + pktErrs = postBitErrRS = ( u32_t ) measuredRSErrors.nrSncParFailCount; + + /* Extract the Exponent and the Mantisa of the */ + /* pre Reed-Solomon bit error count */ + e = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_EXP__M ) >> + FEC_RS_NR_BIT_ERRORS_EXP__B; + m = ( preBitErrRS & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M ) >> + FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + + berCnt = m << e; + + /*qamPreRSBer = FracTimes1e6( berCnt, rsBitCnt ); */ + if ( m > (rsBitCnt >> (e + 1)) || (rsBitCnt >> e) == 0 ) + { + qamPreRSBer = 500000; /* clip BER 0.5 */ + } + else + { + qamPreRSBer = FracTimes1e6(m, rsBitCnt >> e ); + } + + /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ + /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ + /* + => c = (1000000*100*11.17)/1504 = + post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / + (100 * FEC_OC_SNC_FAIL_PERIOD__A) + *100 and /100 is for more precision. + => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation + + Precision errors still possible. + */ + e = postBitErrRS * 742686; + m = fecOcPeriod * 100; + if ( fecOcPeriod == 0 ) + qamPostRSBer = 0xFFFFFFFF; + else + qamPostRSBer = e/m; + + /* fill signal quality data structure */ + sigQuality->MER = ( ( u16_t ) qamSlMer ); + if (extAttr->standard == DRX_STANDARD_ITU_B) + { + sigQuality->preViterbiBER = qamVDSer; + } + else + { + sigQuality->preViterbiBER = qamPreRSBer; + } + sigQuality->postViterbiBER = qamPreRSBer; + sigQuality->postReedSolomonBER = qamPostRSBer; + sigQuality->scaleFactorBER = ( ( u32_t ) 1000000 ); +#ifdef DRXJ_SIGNAL_ACCUM_ERR + CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); +#else + sigQuality->packetError = ( ( u16_t ) pktErrs ); +#endif + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlGetQAMConstel() +* \brief Retreive a QAM constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetQAMConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + u16_t fecOcOcrMode = 0; /**< FEC OCR grabber configuration */ + u16_t qamSlCommMb = 0; /**< QAM SL MB configuration */ + u16_t qamSlCommMbInit = 0; /**< QAM SL MB intial configuration */ + u16_t im = 0; /**< constellation Im part */ + u16_t re = 0; /**< constellation Re part */ + u32_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; /**< device address */ + + /* read device info */ + devAddr = demod -> myI2CDevAddr; + + /* TODO: */ + /* Monitor bus grabbing is an open external interface issue */ + /* Needs to be checked when external interface PG is updated */ + + /* Configure MB (Monitor bus) */ + RR16( devAddr, QAM_SL_COMM_MB__A, &qamSlCommMbInit ); + /* set observe flag & MB mux */ + qamSlCommMb = qamSlCommMbInit & (~ ( QAM_SL_COMM_MB_OBS__M + + QAM_SL_COMM_MB_MUX_OBS__M ) ); + qamSlCommMb |= ( QAM_SL_COMM_MB_OBS_ON + + QAM_SL_COMM_MB_MUX_OBS_CONST_CORR ); + WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMb ); + + /* Enable MB grabber in the FEC OC */ + fecOcOcrMode = ( /* output select: observe bus */ + ( FEC_OC_OCR_MODE_MB_SELECT__M & + ( 0x0 << FEC_OC_OCR_MODE_MB_SELECT__B ) ) | + /* grabber enable: on */ + ( FEC_OC_OCR_MODE_GRAB_ENABLE__M & + ( 0x1 << FEC_OC_OCR_MODE_GRAB_ENABLE__B ) ) | + /* grabber select: observe bus */ + ( FEC_OC_OCR_MODE_GRAB_SELECT__M & + ( 0x0 << FEC_OC_OCR_MODE_GRAB_SELECT__B ) ) | + /* grabber mode: continuous */ + ( FEC_OC_OCR_MODE_GRAB_COUNTED__M & + ( 0x0 << FEC_OC_OCR_MODE_GRAB_COUNTED__B ) ) ); + WR16( devAddr, FEC_OC_OCR_MODE__A, fecOcOcrMode ); + + /* Disable MB grabber in the FEC OC */ + WR16( devAddr, FEC_OC_OCR_MODE__A, 0x00 ); + + /* read data */ + RR32( devAddr, FEC_OC_OCR_GRAB_RD0__A, &data ); + re = (u16_t)(data & FEC_OC_OCR_GRAB_RD0__M); + im = (u16_t)((data >> 16) & FEC_OC_OCR_GRAB_RD1__M); + + /* TODO: */ + /* interpret data (re & im) according to the Monitor bus mapping ?? */ + + /* sign extension, 10th bit is sign bit */ + if ( (re & 0x0200) == 0x0200 ) + { + re |= 0xFC00; + } + if ( (im & 0x0200) == 0x0200 ) + { + im |= 0xFC00; + } + complexNr->re = ( ( s16_t ) re ) ; + complexNr->im = ( ( s16_t ) im ) ; + + /* Restore MB (Monitor bus) */ + WR16( devAddr, QAM_SL_COMM_MB__A, qamSlCommMbInit ); + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +#endif /* #ifndef DRXJ_VSB_ONLY */ + +/*============================================================================*/ +/*== END QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + Implementation notes. + + NTSC/FM AGCs + + Four AGCs are used for NTSC: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) Video AGC (used to amplify the output signal in case input to low) + (4) SIF AGC (used to amplify the output signal in case input to low) + + Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed + that the coupling between Video AGC and the RF and IF AGCs also works in + favor of the SIF AGC. + + Three AGCs are used for FM: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) SIF AGC (used to amplify the output signal in case input to low) + + The SIF AGC is now coupled to the RF/IF AGCs. + The SIF AGC is needed for both SIF ouput and the internal SIF signal to + the AUD block. + + RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of + the ATV block. The AGC control algorithms are all implemented in + microcode. + + ATV SETTINGS + + (Shadow settings will not be used for now, they will be implemented + later on because of the schedule) + + Several HW/SCU "settings" can be used for ATV. The standard selection + will reset most of these settings. To avoid that the end user apllication + has to perform these settings each time the ATV or FM standards is + selected the driver will shadow these settings. This enables the end user + to perform the settings only once after a DRX_Open(). The driver must + write the shadow settings to HW/SCU incase: + ( setstandard FM/ATV) || + ( settings have changed && FM/ATV standard is active) + The shadow settings will be stored in the device specific data container. + A set of flags will be defined to flag changes in shadow settings. + A routine will be implemented to write all changed shadow settings to + HW/SCU. + + The "settings" will consist of: AGC settings, filter settings etc. + + Disadvantage of use of shadow settings: + Direct changes in HW/SCU registers will not be reflected in the + shadow settings and these changes will be overwritten during a next + update. This can happen during evaluation. This will not be a problem + for normal customer usage. +*/ +/* -------------------------------------------------------------------------- */ + +/** +* \brief Get array index for atv coef (extAttr->atvTopCoefX[index]) +* \param standard +* \param pointer to index +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AtvEquCoefIndex( DRXStandard_t standard, int *index) +{ + switch(standard) + { + case DRX_STANDARD_PAL_SECAM_BG: + *index=(int)DRXJ_COEF_IDX_BG; + break; + case DRX_STANDARD_PAL_SECAM_DK: + *index=(int)DRXJ_COEF_IDX_DK; + break; + case DRX_STANDARD_PAL_SECAM_I: + *index=(int)DRXJ_COEF_IDX_I; + break; + case DRX_STANDARD_PAL_SECAM_L: + *index=(int)DRXJ_COEF_IDX_L; + break; + case DRX_STANDARD_PAL_SECAM_LP: + *index=(int)DRXJ_COEF_IDX_LP; + break; + case DRX_STANDARD_NTSC: + *index=(int)DRXJ_COEF_IDX_MN; + break; + case DRX_STANDARD_FM: + *index=(int)DRXJ_COEF_IDX_FM; + break; + default: + *index=(int)DRXJ_COEF_IDX_MN; /* still return a valid index */ + return DRX_STS_ERROR; + break; + } + + return DRX_STS_OK; +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t AtvUpdateConfig () +* \brief Flush changes in ATV shadow registers to physical registers. +* \param demod instance of demodulator +* \param forceUpdate don't look at standard or change flags, flush all. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AtvUpdateConfig( pDRXDemodInstance_t demod, + Bool_t forceUpdate ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* equalizer coefficients */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_COEF) != 0) ) + { + int index=0; + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + WR16( devAddr, ATV_TOP_EQU0__A, extAttr->atvTopEqu0[index] ); + WR16( devAddr, ATV_TOP_EQU1__A, extAttr->atvTopEqu1[index] ); + WR16( devAddr, ATV_TOP_EQU2__A, extAttr->atvTopEqu2[index] ); + WR16( devAddr, ATV_TOP_EQU3__A, extAttr->atvTopEqu3[index] ); + } + + /* bypass fast carrier recovery */ + if ( forceUpdate ) + { + u16_t data=0; + + RR16( devAddr, IQM_RT_ROT_BP__A, &data ); + data &= (~((u16_t)IQM_RT_ROT_BP_ROT_OFF__M)); + if (extAttr->phaseCorrectionBypass) + { + data |= IQM_RT_ROT_BP_ROT_OFF_OFF; + } else { + data |= IQM_RT_ROT_BP_ROT_OFF_ACTIVE; + } + WR16( devAddr, IQM_RT_ROT_BP__A, data ); + } + + /* peak filter setting */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_PEAK_FLT) != 0) ) + { + WR16( devAddr, ATV_TOP_VID_PEAK__A, extAttr->atvTopVidPeak ); + } + + /* noise filter setting */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_NOISE_FLT) != 0) ) + { + WR16( devAddr, ATV_TOP_NOISE_TH__A, extAttr->atvTopNoiseTh ); + } + + /* SIF attenuation */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_SIF_ATT) != 0) ) + { + u16_t attenuation=0; + + switch( extAttr->sifAttenuation ){ + case DRXJ_SIF_ATTENUATION_0DB: + attenuation = ATV_TOP_AF_SIF_ATT_0DB; + break; + case DRXJ_SIF_ATTENUATION_3DB: + attenuation = ATV_TOP_AF_SIF_ATT_M3DB; + break; + case DRXJ_SIF_ATTENUATION_6DB: + attenuation = ATV_TOP_AF_SIF_ATT_M6DB; + break; + case DRXJ_SIF_ATTENUATION_9DB: + attenuation = ATV_TOP_AF_SIF_ATT_M9DB; + break; + default: + return DRX_STS_ERROR; + break; + } + WR16( devAddr, ATV_TOP_AF_SIF_ATT__A, attenuation ); + } + + /* SIF & CVBS enable */ + if ( forceUpdate || + ((extAttr->atvCfgChangedFlags & DRXJ_ATV_CHANGED_OUTPUT) != 0) ) + { + u16_t data = 0; + + RR16( devAddr, ATV_TOP_STDBY__A, &data ); + if ( extAttr->enableCVBSOutput ) + { + data |=ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE; + } else { + data &= (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE); + } + + if ( extAttr->enableSIFOutput ) + { + data &= (~ATV_TOP_STDBY_SIF_STDBY_STANDBY); + } else { + data |= ATV_TOP_STDBY_SIF_STDBY_STANDBY; + } + WR16( devAddr, ATV_TOP_STDBY__A, data ); + } + + extAttr->atvCfgChangedFlags = 0; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlSetCfgATVOutput() +* \brief Configure ATV ouputs +* \param demod instance of demodulator +* \param outputCfg output configuaration +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgATVOutput( pDRXDemodInstance_t demod, + pDRXJCfgAtvOutput_t outputCfg ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( outputCfg == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + if ( outputCfg->enableSIFOutput ) + { + switch( outputCfg->sifAttenuation ){ + case DRXJ_SIF_ATTENUATION_0DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_3DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_6DB: /* fallthrough */ + case DRXJ_SIF_ATTENUATION_9DB: + /* Do nothing */ + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + if(extAttr->sifAttenuation != outputCfg->sifAttenuation ) + { + extAttr->sifAttenuation = outputCfg->sifAttenuation; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_SIF_ATT; + } + } + + if ( extAttr->enableCVBSOutput != outputCfg->enableCVBSOutput ) + { + extAttr->enableCVBSOutput = outputCfg->enableCVBSOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } + + if ( extAttr->enableSIFOutput != outputCfg->enableSIFOutput ) + { + extAttr->enableSIFOutput = outputCfg->enableSIFOutput; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT; + } + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t CtrlSetCfgAtvEquCoef() +* \brief Set ATV equalizer coefficients +* \param demod instance of demodulator +* \param coef the equalizer coefficients +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgAtvEquCoef( pDRXDemodInstance_t demod , + pDRXJCfgAtvEquCoef_t coef) +{ + pDRXJData_t extAttr = NULL; + int index; + + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard )) + { + return DRX_STS_ERROR; + } + + /* Check arguments */ + if ( ( coef == NULL ) || + ( coef->coef0 > (ATV_TOP_EQU0_EQU_C0__M / 2) ) || + ( coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2) ) || + ( coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2) ) || + ( coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2) ) || + ( coef->coef0 < ((s16_t)~(ATV_TOP_EQU0_EQU_C0__M >> 1)) ) || + ( coef->coef1 < ((s16_t)~(ATV_TOP_EQU1_EQU_C1__M >> 1)) ) || + ( coef->coef2 < ((s16_t)~(ATV_TOP_EQU2_EQU_C2__M >> 1)) ) || + ( coef->coef3 < ((s16_t)~(ATV_TOP_EQU3_EQU_C3__M >> 1)) ) ) + { + return (DRX_STS_INVALID_ARG); + } + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + extAttr->atvTopEqu0[index] = coef->coef0; + extAttr->atvTopEqu1[index] = coef->coef1; + extAttr->atvTopEqu2[index] = coef->coef2; + extAttr->atvTopEqu3[index] = coef->coef3; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF; + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvEquCoef() +* \brief Get ATV equ coef settings +* \param demod instance of demodulator +* \param coef The ATV equ coefficients +* \return DRXStatus_t. +* +* The values are read from the shadow registers maintained by the drxdriver +* If registers are manipulated outside of the drxdriver scope the reported +* settings will not reflect these changes because of the use of shadow +* regitsers. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvEquCoef( pDRXDemodInstance_t demod , + pDRXJCfgAtvEquCoef_t coef) +{ + pDRXJData_t extAttr = NULL; + int index=0; + + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* current standard needs to be an ATV standard */ + if (!DRXJ_ISATVSTD(extAttr->standard )) + { + return DRX_STS_ERROR; + } + + /* Check arguments */ + if ( coef == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + CHK_ERROR(AtvEquCoefIndex( extAttr->standard, &index )); + coef->coef0 = extAttr->atvTopEqu0[index]; + coef->coef1 = extAttr->atvTopEqu1[index]; + coef->coef2 = extAttr->atvTopEqu2[index]; + coef->coef3 = extAttr->atvTopEqu3[index]; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlSetCfgAtvMisc() +* \brief Set misc. settings for ATV. +* \param demod instance of demodulator +* \param +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlSetCfgAtvMisc( pDRXDemodInstance_t demod , + pDRXJCfgAtvMisc_t settings ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( ( settings == NULL ) || + ((settings->peakFilter) < (s16_t)(-8) ) || + ((settings->peakFilter) > (s16_t)(15) ) || + ((settings->noiseFilter) > 15 ) ) + { + return (DRX_STS_INVALID_ARG); + } /* if */ + + extAttr = (pDRXJData_t)demod->myExtAttr; + + if ( settings->peakFilter != extAttr->atvTopVidPeak ) + { + extAttr->atvTopVidPeak = settings->peakFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_PEAK_FLT; + } + + if ( settings->noiseFilter != extAttr->atvTopNoiseTh ) + { + extAttr->atvTopNoiseTh = settings->noiseFilter; + extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT; + } + + CHK_ERROR( AtvUpdateConfig(demod, FALSE) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvMisc() +* \brief Get misc settings of ATV. +* \param demod instance of demodulator +* \param settings misc. ATV settings +* \return DRXStatus_t. +* +* The values are read from the shadow registers maintained by the drxdriver +* If registers are manipulated outside of the drxdriver scope the reported +* settings will not reflect these changes because of the use of shadow +* regitsers. +*/ +static DRXStatus_t +CtrlGetCfgAtvMisc( pDRXDemodInstance_t demod , + pDRXJCfgAtvMisc_t settings ) +{ + pDRXJData_t extAttr = NULL; + + /* Check arguments */ + if ( settings == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + + settings->peakFilter = extAttr->atvTopVidPeak ; + settings->noiseFilter = extAttr->atvTopNoiseTh ; + + return (DRX_STS_OK); +} + +/* -------------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvOutput() +* \brief +* \param demod instance of demodulator +* \param outputCfg output configuaration +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvOutput( pDRXDemodInstance_t demod , + pDRXJCfgAtvOutput_t outputCfg ) +{ + u16_t data = 0; + + /* Check arguments */ + if ( outputCfg == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + RR16( demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data ); + if ( data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE ) + { + outputCfg->enableCVBSOutput = TRUE; + } else { + outputCfg->enableCVBSOutput = FALSE; + } + + if ( data & ATV_TOP_STDBY_SIF_STDBY_STANDBY ) + { + outputCfg->enableSIFOutput = FALSE; + } else { + outputCfg->enableSIFOutput = TRUE; + RR16( demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data ); + outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t CtrlGetCfgAtvAgcStatus() +* \brief +* \param demod instance of demodulator +* \param agcStatus agc status +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgAtvAgcStatus( pDRXDemodInstance_t demod , + pDRXJCfgAtvAgcStatus_t agcStatus ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; + u32_t tmp = 0; + + /* Check arguments */ + if ( agcStatus == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + RFgain = (IQM_AF_AGC_RF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_RF__A * 27) - (0.25*IQM_AF_AGC_RF__A))/1000 + + IQM_AF_AGC_RF__A * 27 is 20 bits worst case. + */ + RR16( devAddr, IQM_AF_AGC_RF__A, &data ); + tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ + agcStatus->rfAgcGain = (u16_t)(tmp/1000) ; /* uA */ + /* rounding */ + if ( tmp%1000 >= 500 ) + { + (agcStatus->rfAgcGain)++; + } + + /* + IFgain = (IQM_AF_AGC_IF__A * 26.75)/1000 (uA) + = ((IQM_AF_AGC_IF__A * 27) - (0.25*IQM_AF_AGC_IF__A))/1000 + + IQM_AF_AGC_IF__A * 27 is 20 bits worst case. + */ + RR16( devAddr, IQM_AF_AGC_IF__A, &data ); + tmp = ((u32_t)data) * 27 - ((u32_t)(data>>2)); /* nA */ + agcStatus->ifAgcGain = (u16_t)(tmp/1000) ; /* uA */ + /* rounding */ + if ( tmp%1000 >= 500 ) + { + (agcStatus->ifAgcGain)++; + } + + /* + videoGain = (ATV_TOP_SFR_VID_GAIN__A/16 -150)* 0.05 (dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (dB) + = 10*(ATV_TOP_SFR_VID_GAIN__A/16 -150)/20 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/16 -150)/2 (in 0.1 dB) + = (ATV_TOP_SFR_VID_GAIN__A/32) - 75 (in 0.1 dB) + */ + + SARR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A , &data ); + /* dividing by 32 inclusive rounding */ + data >>=4; + if ((data & 1) !=0 ) + { + data++; + } + data >>= 1; + agcStatus->videoAgcGain = ((s16_t)data)-75; /* 0.1 dB */ + + /* + audioGain = (SCU_RAM_ATV_SIF_GAIN__A -8)* 0.05 (dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/20 (dB) + = 10*(SCU_RAM_ATV_SIF_GAIN__A -8)/20 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A -8)/2 (in 0.1 dB) + = (SCU_RAM_ATV_SIF_GAIN__A/2) - 4 (in 0.1 dB) + */ + + SARR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A, &data ); + data &= SCU_RAM_ATV_SIF_GAIN__M; + /* dividing by 2 inclusive rounding */ + if ((data & 1) !=0 ) + { + data++; + } + data >>= 1; + agcStatus->audioAgcGain = ((s16_t)data)-4; /* 0.1 dB */ + + /* Loop gain's */ + SARR16( devAddr, SCU_RAM_AGC_KI__A, &data ); + agcStatus->videoAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_DGAIN__M)>>SCU_RAM_AGC_KI_DGAIN__B) ; + agcStatus->rfAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_RF__M)>>SCU_RAM_AGC_KI_RF__B) ; + agcStatus->ifAgcLoopGain = + ( (data & SCU_RAM_AGC_KI_IF__M)>>SCU_RAM_AGC_KI_IF__B) ; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t PowerUpATV () +* \brief Power up ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* * Starts ATV and IQM +* * AUdio already started during standard init for ATV. +*/ +static DRXStatus_t +PowerUpATV( pDRXDemodInstance_t demod , DRXStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* ATV NTSC */ + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE ); + /* turn on IQM_AF */ + CHK_ERROR( SetIqmAf( demod, TRUE ) ); + CHK_ERROR(ADCSynchronization (demod)); + + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE ); + + /* Audio, already done during set standard */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif /* #ifndef DRXJ_DIGITAL_ONLY */ + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t PowerDownATV () +* \brief Power down ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* Stops and thus resets ATV and IQM block +* SIF and CVBS ADC are powered down +* Calls audio power down +*/ +static DRXStatus_t +PowerDownATV( pDRXDemodInstance_t demod , DRXStandard_t standard, Bool_t primary ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + /* ATV NTSC */ + + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + WR16 ( devAddr, ATV_TOP_STDBY__A, ( ATV_TOP_STDBY_SIF_STDBY_STANDBY & + (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) ) ); + + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP); + if (primary == TRUE) + { + WR16( devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP ); + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + } + else + { + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + } + CHK_ERROR( PowerDownAud(demod) ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t SetATVStandard () +* \brief Set up ATV demodulator. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return DRXStatus_t. +* +* Init all channel independent registers. +* Assuming that IQM, ATV and AUD blocks have been reset and are in STOP mode +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D /* TODO remove after done with reg import */ +static DRXStatus_t +SetATVStandard( pDRXDemodInstance_t demod , pDRXStandard_t standard ) +{ +/* TODO: enable alternative for tap settings via external file + +something like: +#ifdef DRXJ_ATV_COEF_FILE +#include DRXJ_ATV_COEF_FILE +#else +... code defining fixed coef's ... +#endif + +Cutsomer must create file "customer_coefs.c.inc" containing +modified copy off the constants below, and define the compiler +switch DRXJ_ATV_COEF_FILE="customer_coefs.c.inc". + +Still to check if this will work; DRXJ_16TO8 macro may cause +trouble ? +*/ + const u8_t ntsc_taps_re[]= { + DRXJ_16TO8(-12 ), /* re0 */ + DRXJ_16TO8(-9 ), /* re1 */ + DRXJ_16TO8( 9 ), /* re2 */ + DRXJ_16TO8( 19 ), /* re3 */ + DRXJ_16TO8(-4 ), /* re4 */ + DRXJ_16TO8(-24 ), /* re5 */ + DRXJ_16TO8(-6 ), /* re6 */ + DRXJ_16TO8( 16 ), /* re7 */ + DRXJ_16TO8( 6 ), /* re8 */ + DRXJ_16TO8(-16 ), /* re9 */ + DRXJ_16TO8(-5 ), /* re10 */ + DRXJ_16TO8( 13 ), /* re11 */ + DRXJ_16TO8(-2 ), /* re12 */ + DRXJ_16TO8(-20 ), /* re13 */ + DRXJ_16TO8( 4 ), /* re14 */ + DRXJ_16TO8( 25 ), /* re15 */ + DRXJ_16TO8(-6 ), /* re16 */ + DRXJ_16TO8(-36 ), /* re17 */ + DRXJ_16TO8( 2 ), /* re18 */ + DRXJ_16TO8( 38 ), /* re19 */ + DRXJ_16TO8(-10 ), /* re20 */ + DRXJ_16TO8(-48 ), /* re21 */ + DRXJ_16TO8( 35 ), /* re22 */ + DRXJ_16TO8( 94 ), /* re23 */ + DRXJ_16TO8(-59 ), /* re24 */ + DRXJ_16TO8(-217 ), /* re25 */ + DRXJ_16TO8( 50 ), /* re26 */ + DRXJ_16TO8( 679 ) /* re27 */ + }; + const u8_t ntsc_taps_im[]= { + DRXJ_16TO8( 11 ), /* im0 */ + DRXJ_16TO8( 1 ), /* im1 */ + DRXJ_16TO8(-10 ), /* im2 */ + DRXJ_16TO8( 2 ), /* im3 */ + DRXJ_16TO8( 24 ), /* im4 */ + DRXJ_16TO8( 21 ), /* im5 */ + DRXJ_16TO8( 1 ), /* im6 */ + DRXJ_16TO8(-4 ), /* im7 */ + DRXJ_16TO8( 7 ), /* im8 */ + DRXJ_16TO8( 14 ), /* im9 */ + DRXJ_16TO8( 27 ), /* im10 */ + DRXJ_16TO8( 42 ), /* im11 */ + DRXJ_16TO8( 22 ), /* im12 */ + DRXJ_16TO8(-20 ), /* im13 */ + DRXJ_16TO8( 2 ), /* im14 */ + DRXJ_16TO8( 98 ), /* im15 */ + DRXJ_16TO8( 122 ), /* im16 */ + DRXJ_16TO8( 0 ), /* im17 */ + DRXJ_16TO8(-85 ), /* im18 */ + DRXJ_16TO8( 51 ), /* im19 */ + DRXJ_16TO8( 247 ), /* im20 */ + DRXJ_16TO8( 192 ), /* im21 */ + DRXJ_16TO8(-55 ), /* im22 */ + DRXJ_16TO8(-95 ), /* im23 */ + DRXJ_16TO8( 217 ), /* im24 */ + DRXJ_16TO8( 544 ), /* im25 */ + DRXJ_16TO8( 553 ), /* im26 */ + DRXJ_16TO8( 302 ) /* im27 */ + }; + const u8_t bg_taps_re[]= { + DRXJ_16TO8(-18 ), /* re0 */ + DRXJ_16TO8( 18 ), /* re1 */ + DRXJ_16TO8( 19 ), /* re2 */ + DRXJ_16TO8(-26 ), /* re3 */ + DRXJ_16TO8(-20 ), /* re4 */ + DRXJ_16TO8( 36 ), /* re5 */ + DRXJ_16TO8( 5 ), /* re6 */ + DRXJ_16TO8(-51 ), /* re7 */ + DRXJ_16TO8( 15 ), /* re8 */ + DRXJ_16TO8( 45 ), /* re9 */ + DRXJ_16TO8(-46 ), /* re10 */ + DRXJ_16TO8(-24 ), /* re11 */ + DRXJ_16TO8( 71 ), /* re12 */ + DRXJ_16TO8(-17 ), /* re13 */ + DRXJ_16TO8(-83 ), /* re14 */ + DRXJ_16TO8( 74 ), /* re15 */ + DRXJ_16TO8( 75 ), /* re16 */ + DRXJ_16TO8(-134 ), /* re17 */ + DRXJ_16TO8(-40 ), /* re18 */ + DRXJ_16TO8( 191 ), /* re19 */ + DRXJ_16TO8(-11 ), /* re20 */ + DRXJ_16TO8(-233 ), /* re21 */ + DRXJ_16TO8( 74 ), /* re22 */ + DRXJ_16TO8( 271 ), /* re23 */ + DRXJ_16TO8(-132 ), /* re24 */ + DRXJ_16TO8(-341 ), /* re25 */ + DRXJ_16TO8( 172 ), /* re26 */ + DRXJ_16TO8( 801 ) /* re27 */ + }; + const u8_t bg_taps_im[]= { + DRXJ_16TO8(-24 ), /* im0 */ + DRXJ_16TO8(-10 ), /* im1 */ + DRXJ_16TO8( 9 ), /* im2 */ + DRXJ_16TO8(-5 ), /* im3 */ + DRXJ_16TO8(-51 ), /* im4 */ + DRXJ_16TO8(-17 ), /* im5 */ + DRXJ_16TO8( 31 ), /* im6 */ + DRXJ_16TO8(-48 ), /* im7 */ + DRXJ_16TO8(-95 ), /* im8 */ + DRXJ_16TO8( 25 ), /* im9 */ + DRXJ_16TO8( 37 ), /* im10 */ + DRXJ_16TO8(-123 ), /* im11 */ + DRXJ_16TO8(-77 ), /* im12 */ + DRXJ_16TO8( 94 ), /* im13 */ + DRXJ_16TO8(-10 ), /* im14 */ + DRXJ_16TO8(-149 ), /* im15 */ + DRXJ_16TO8( 10 ), /* im16 */ + DRXJ_16TO8( 108 ), /* im17 */ + DRXJ_16TO8(-49 ), /* im18 */ + DRXJ_16TO8(-59 ), /* im19 */ + DRXJ_16TO8( 90 ), /* im20 */ + DRXJ_16TO8( 73 ), /* im21 */ + DRXJ_16TO8( 55 ), /* im22 */ + DRXJ_16TO8( 148 ), /* im23 */ + DRXJ_16TO8( 86 ), /* im24 */ + DRXJ_16TO8( 146 ), /* im25 */ + DRXJ_16TO8( 687 ), /* im26 */ + DRXJ_16TO8( 877 ) /* im27 */ + }; + const u8_t dk_i_l_lp_taps_re[]= { + DRXJ_16TO8(-23 ), /* re0 */ + DRXJ_16TO8( 9 ), /* re1 */ + DRXJ_16TO8( 16 ), /* re2 */ + DRXJ_16TO8(-26 ), /* re3 */ + DRXJ_16TO8(-3 ), /* re4 */ + DRXJ_16TO8( 13 ), /* re5 */ + DRXJ_16TO8(-19 ), /* re6 */ + DRXJ_16TO8(-3 ), /* re7 */ + DRXJ_16TO8( 13 ), /* re8 */ + DRXJ_16TO8(-26 ), /* re9 */ + DRXJ_16TO8(-4 ), /* re10 */ + DRXJ_16TO8( 28 ), /* re11 */ + DRXJ_16TO8(-15 ), /* re12 */ + DRXJ_16TO8(-14 ), /* re13 */ + DRXJ_16TO8( 10 ), /* re14 */ + DRXJ_16TO8( 1 ), /* re15 */ + DRXJ_16TO8( 39 ), /* re16 */ + DRXJ_16TO8(-18 ), /* re17 */ + DRXJ_16TO8(-90 ), /* re18 */ + DRXJ_16TO8( 109 ), /* re19 */ + DRXJ_16TO8( 113 ), /* re20 */ + DRXJ_16TO8(-235 ), /* re21 */ + DRXJ_16TO8(-49 ), /* re22 */ + DRXJ_16TO8( 359 ), /* re23 */ + DRXJ_16TO8(-79 ), /* re24 */ + DRXJ_16TO8(-459 ), /* re25 */ + DRXJ_16TO8( 206 ), /* re26 */ + DRXJ_16TO8( 894 ) /* re27 */ + }; + const u8_t dk_i_l_lp_taps_im[]= { + DRXJ_16TO8(-8 ), /* im0 */ + DRXJ_16TO8(-20 ), /* im1 */ + DRXJ_16TO8( 17 ), /* im2 */ + DRXJ_16TO8(-14 ), /* im3 */ + DRXJ_16TO8(-52 ), /* im4 */ + DRXJ_16TO8( 4 ), /* im5 */ + DRXJ_16TO8( 9 ), /* im6 */ + DRXJ_16TO8(-62 ), /* im7 */ + DRXJ_16TO8(-47 ), /* im8 */ + DRXJ_16TO8( 0 ), /* im9 */ + DRXJ_16TO8(-20 ), /* im10 */ + DRXJ_16TO8(-48 ), /* im11 */ + DRXJ_16TO8(-65 ), /* im12 */ + DRXJ_16TO8(-23 ), /* im13 */ + DRXJ_16TO8( 44 ), /* im14 */ + DRXJ_16TO8(-60 ), /* im15 */ + DRXJ_16TO8(-113 ), /* im16 */ + DRXJ_16TO8( 92 ), /* im17 */ + DRXJ_16TO8( 81 ), /* im18 */ + DRXJ_16TO8(-125 ), /* im19 */ + DRXJ_16TO8( 28 ), /* im20 */ + DRXJ_16TO8( 182 ), /* im21 */ + DRXJ_16TO8( 35 ), /* im22 */ + DRXJ_16TO8( 94 ), /* im23 */ + DRXJ_16TO8( 180 ), /* im24 */ + DRXJ_16TO8( 134 ), /* im25 */ + DRXJ_16TO8( 657 ), /* im26 */ + DRXJ_16TO8( 1023 ) /* im27 */ + }; + const u8_t fm_taps_re[]= { + DRXJ_16TO8( 0 ), /* re0 */ + DRXJ_16TO8( 0 ), /* re1 */ + DRXJ_16TO8( 0 ), /* re2 */ + DRXJ_16TO8( 0 ), /* re3 */ + DRXJ_16TO8( 0 ), /* re4 */ + DRXJ_16TO8( 0 ), /* re5 */ + DRXJ_16TO8( 0 ), /* re6 */ + DRXJ_16TO8( 0 ), /* re7 */ + DRXJ_16TO8( 0 ), /* re8 */ + DRXJ_16TO8( 0 ), /* re9 */ + DRXJ_16TO8( 0 ), /* re10 */ + DRXJ_16TO8( 0 ), /* re11 */ + DRXJ_16TO8( 0 ), /* re12 */ + DRXJ_16TO8( 0 ), /* re13 */ + DRXJ_16TO8( 0 ), /* re14 */ + DRXJ_16TO8( 0 ), /* re15 */ + DRXJ_16TO8( 0 ), /* re16 */ + DRXJ_16TO8( 0 ), /* re17 */ + DRXJ_16TO8( 0 ), /* re18 */ + DRXJ_16TO8( 0 ), /* re19 */ + DRXJ_16TO8( 0 ), /* re20 */ + DRXJ_16TO8( 0 ), /* re21 */ + DRXJ_16TO8( 0 ), /* re22 */ + DRXJ_16TO8( 0 ), /* re23 */ + DRXJ_16TO8( 0 ), /* re24 */ + DRXJ_16TO8( 0 ), /* re25 */ + DRXJ_16TO8( 0 ), /* re26 */ + DRXJ_16TO8( 0 ) /* re27 */ + }; + const u8_t fm_taps_im[]= { + DRXJ_16TO8(-6 ), /* im0 */ + DRXJ_16TO8( 2 ), /* im1 */ + DRXJ_16TO8( 14 ), /* im2 */ + DRXJ_16TO8(-38 ), /* im3 */ + DRXJ_16TO8( 58 ), /* im4 */ + DRXJ_16TO8(-62 ), /* im5 */ + DRXJ_16TO8( 42 ), /* im6 */ + DRXJ_16TO8( 0 ), /* im7 */ + DRXJ_16TO8(-45 ), /* im8 */ + DRXJ_16TO8( 73 ), /* im9 */ + DRXJ_16TO8(-65 ), /* im10 */ + DRXJ_16TO8( 23 ), /* im11 */ + DRXJ_16TO8( 34 ), /* im12 */ + DRXJ_16TO8(-77 ), /* im13 */ + DRXJ_16TO8( 80 ), /* im14 */ + DRXJ_16TO8(-39 ), /* im15 */ + DRXJ_16TO8(-25 ), /* im16 */ + DRXJ_16TO8( 78 ), /* im17 */ + DRXJ_16TO8(-90 ), /* im18 */ + DRXJ_16TO8( 52 ), /* im19 */ + DRXJ_16TO8( 16 ), /* im20 */ + DRXJ_16TO8(-77 ), /* im21 */ + DRXJ_16TO8( 97 ), /* im22 */ + DRXJ_16TO8(-62 ), /* im23 */ + DRXJ_16TO8(-8 ), /* im24 */ + DRXJ_16TO8( 75 ), /* im25 */ + DRXJ_16TO8(-100 ), /* im26 */ + DRXJ_16TO8( 70 ) /* im27 */ + }; + + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult = 0; + u16_t cmdParam = 0; +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + DRXUCodeInfo_t ucodeInfo; + pDRXCommonAttr_t commonAttr = NULL; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + commonAttr = demod -> myCommonAttr; + + /* Check if audio microcode is already uploaded */ + if ( !( extAttr->flagAudMcUploaded ) ) + { + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; + + /* Upload only audio microcode */ + CHK_ERROR ( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, TRUE ) ); + + if ( commonAttr->verifyMicrocode == TRUE ) + { + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, TRUE ) ); + } + + /* Prevent uploading audio microcode again */ + extAttr->flagAudMcUploaded = TRUE; + } +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + + WR16( devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP ); + WR16( devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP ); + WR16( devAddr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP ); + WR16( devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP ); + /* Reset ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + WR16( devAddr, ATV_TOP_MOD_CONTROL__A, ATV_TOP_MOD_CONTROL__PRE ); + + /* TODO remove AUTO/OFF patches after ucode fix. */ + switch ( *standard ) + { + case DRX_STANDARD_NTSC: + /* NTSC */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_MN; + + WR16( devAddr, IQM_RT_LO_INCR__A , IQM_RT_LO_INCR_MN ); + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(ntsc_taps_re) , + ((pu8_t)ntsc_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(ntsc_taps_im) , + ((pu8_t)ntsc_taps_im) ); + + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_MN ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_MN | + ATV_TOP_CR_CONT_CR_D_MN | + ATV_TOP_CR_CONT_CR_I_MN ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_MN ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_MN | + ATV_TOP_STD_VID_POL_MN ) ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_MN ); + + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A, + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_FM: + /* FM */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_FM; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2994 ); + WR16( devAddr, IQM_CF_MIDTAP__A , 0 ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(fm_taps_re) , + ((pu8_t)fm_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(fm_taps_im) , + ((pu8_t)fm_taps_im) ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_FM | + ATV_TOP_STD_VID_POL_FM ) ); + WR16( devAddr, ATV_TOP_MOD_CONTROL__A, 0 ); + WR16( devAddr, ATV_TOP_CR_CONT__A , 0 ); + + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW | + SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM )); + WR16( devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF ); + extAttr->phaseCorrectionBypass = TRUE; + extAttr->enableCVBSOutput = FALSE; + break; + case DRX_STANDARD_PAL_SECAM_BG: + /* PAL/SECAM B/G */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_B; + + WR16( devAddr, IQM_RT_LO_INCR__A , 1820 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(bg_taps_re) , + ((pu8_t)bg_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(bg_taps_im) , + ((pu8_t)bg_taps_im) ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_BG ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A, ATV_TOP_CR_AMP_TH_BG ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_BG | + ATV_TOP_CR_CONT_CR_D_BG | + ATV_TOP_CR_CONT_CR_I_BG ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_BG ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_BG | + ATV_TOP_STD_VID_POL_BG ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_DK: + /* PAL/SECAM D/K */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_DK; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_DK ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_DK ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_DK | + ATV_TOP_CR_CONT_CR_D_DK | + ATV_TOP_CR_CONT_CR_I_DK ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_DK ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_DK | + ATV_TOP_STD_VID_POL_DK ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode =DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_I: + /* PAL/SECAM I */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_I; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 );/* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , ATV_TOP_CR_AMP_TH_I ); + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_I ); + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_I | + ATV_TOP_CR_CONT_CR_D_I | + ATV_TOP_CR_CONT_CR_I_I ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_I ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_I | + ATV_TOP_STD_VID_POL_I ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM | + SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_L: + /* PAL/SECAM L with negative modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_L; + + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_L ); + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_L | + ATV_TOP_CR_CONT_CR_D_L | + ATV_TOP_CR_CONT_CR_I_L ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_L ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_L | + ATV_TOP_STD_VID_POL_L ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + case DRX_STANDARD_PAL_SECAM_LP: + /* PAL/SECAM L with positive modulation */ + cmdParam = SCU_RAM_ATV_STANDARD_STANDARD_LP; + + WR16( devAddr, ATV_TOP_VID_AMP__A , ATV_TOP_VID_AMP_LP ); + WR16( devAddr, IQM_RT_LO_INCR__A , 2225 ); /* TODO check with IS */ + WR16( devAddr, IQM_CF_MIDTAP__A , IQM_CF_MIDTAP_RE__M ); + WRB ( devAddr, IQM_CF_TAP_RE0__A , sizeof(dk_i_l_lp_taps_re) , + ((pu8_t)dk_i_l_lp_taps_re) ); + WRB ( devAddr, IQM_CF_TAP_IM0__A , sizeof(dk_i_l_lp_taps_im) , + ((pu8_t)dk_i_l_lp_taps_im) ); + WR16( devAddr, ATV_TOP_CR_AMP_TH__A , 0x2 ); /* TODO check with IS */ + WR16( devAddr, ATV_TOP_CR_CONT__A , + ( ATV_TOP_CR_CONT_CR_P_LP | + ATV_TOP_CR_CONT_CR_D_LP | + ATV_TOP_CR_CONT_CR_I_LP ) ); + WR16( devAddr, ATV_TOP_CR_OVM_TH__A , ATV_TOP_CR_OVM_TH_LP ); + WR16( devAddr, ATV_TOP_STD__A , (ATV_TOP_STD_MODE_LP | + ATV_TOP_STD_VID_POL_LP ) ); + WR16( devAddr, SCU_RAM_ATV_AGC_MODE__A , + ( SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM | + SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE | + SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW ) ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, 0x1000 ); + WR16( devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX_REF__A, + SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP); + extAttr->phaseCorrectionBypass = FALSE; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER; + extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top; + extAttr->enableCVBSOutput = TRUE; + break; + default: + return ( DRX_STS_ERROR ); + } + + /* Common initializations FM & NTSC & B/G & D/K & I & L & LP */ + if (extAttr->hasLNA == FALSE) + { + WR16( devAddr, IQM_AF_AMUX__A, 0x01); + } + + WR16( devAddr, SCU_RAM_ATV_STANDARD__A , 0x002 ); + WR16( devAddr, IQM_AF_CLP_LEN__A , IQM_AF_CLP_LEN_ATV ); + WR16( devAddr, IQM_AF_CLP_TH__A , IQM_AF_CLP_TH_ATV ); + WR16( devAddr, IQM_AF_SNS_LEN__A , IQM_AF_SNS_LEN_ATV ); + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); + WR16( devAddr, IQM_AF_AGC_IF__A , 10248 ); + + extAttr->iqmRcRateOfs = 0x00200000L; + WR32( devAddr, IQM_RC_RATE_OFS_LO__A , extAttr->iqmRcRateOfs ); + WR16( devAddr, IQM_RC_ADJ_SEL__A , IQM_RC_ADJ_SEL_B_OFF ); + WR16( devAddr, IQM_RC_STRETCH__A , IQM_RC_STRETCH_ATV ); + + WR16( devAddr, IQM_RT_ACTIVE__A , IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON | + IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON ); + + WR16( devAddr, IQM_CF_OUT_ENA__A , IQM_CF_OUT_ENA_ATV__M ); + WR16( devAddr, IQM_CF_SYMMETRIC__A , IQM_CF_SYMMETRIC_IM__M ); + /* default: SIF in standby */ + WR16( devAddr, ATV_TOP_SYNC_SLICE__A , ATV_TOP_SYNC_SLICE_MN ); + WR16( devAddr, ATV_TOP_MOD_ACCU__A , ATV_TOP_MOD_ACCU__PRE ); + + WR16( devAddr, SCU_RAM_ATV_SIF_GAIN__A , 0x080 ); + WR16( devAddr, SCU_RAM_ATV_FAGC_TH_RED__A , 10 ); + WR16( devAddr, SCU_RAM_ATV_AAGC_CNT__A , 7 ); + WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MIN__A , 0x0225 ); + WR16( devAddr, SCU_RAM_ATV_NAGC_KI_MAX__A , 0x0547 ); + WR16( devAddr, SCU_RAM_ATV_KI_CHANGE_TH__A , 20 ); + WR16( devAddr, SCU_RAM_ATV_LOCK__A , 0 ); + + WR16( devAddr, IQM_RT_DELAY__A , IQM_RT_DELAY__PRE ); + WR16( devAddr, SCU_RAM_ATV_BPC_KI_MIN__A , 531 ); + WR16( devAddr, SCU_RAM_ATV_PAGC_KI_MIN__A, 1061 ); + WR16( devAddr, SCU_RAM_ATV_BP_REF_MIN__A , 100 ); + WR16( devAddr, SCU_RAM_ATV_BP_REF_MAX__A , 260 ); + WR16( devAddr, SCU_RAM_ATV_BP_LVL__A , 0 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MAX__A , 0 ); + WR16( devAddr, SCU_RAM_ATV_AMS_MIN__A , 2047 ); + WR16( devAddr, SCU_RAM_GPIO__A , 0 ); + + /* Override reset values with current shadow settings */ + CHK_ERROR( AtvUpdateConfig( demod, TRUE) ); + + /* Configure/restore AGC settings */ + CHK_ERROR( InitAGC( demod ) ); + CHK_ERROR( SetAgcIf( demod, &(extAttr->atvIfAgcCfg), FALSE ) ); + CHK_ERROR( SetAgcRf( demod, &(extAttr->atvRfAgcCfg), FALSE ) ); + CHK_ERROR( CtrlSetCfgPreSaw( demod, &(extAttr->atvPreSawCfg)) ); + + /* Set SCU ATV substandard,assuming this doesn't require running ATV block */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmdSCU.parameterLen = 1; + cmdSCU.resultLen = 1; + cmdSCU.parameter = &cmdParam; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* turn the analog work around on/off (must after set_env b/c it is set in mc)*/ + if ( extAttr->mfx == 0x03 ) + { + WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 0 ); + } + else + { + WR16( devAddr, SCU_RAM_ATV_ENABLE_IIR_WA__A, 1 ); + WR16( devAddr, SCU_RAM_ATV_IIR_CRIT__A , 225 ); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/* -------------------------------------------------------------------------- */ + +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t SetATVChannel () +* \brief Set ATV channel. +* \param demod: instance of demod. +* \return DRXStatus_t. +* +* Not much needs to be done here, only start the SCU for NTSC/FM. +* Mirrored channels are not expected in the RF domain, so IQM FS setting +* doesn't need to be remembered. +* The channel->mirror parameter is therefor ignored. +* +*/ +static DRXStatus_t +SetATVChannel( pDRXDemodInstance_t demod, + DRXFrequency_t tunerFreqOffset, + pDRXChannel_t channel, + DRXStandard_t standard ) +{ + DRXJSCUCmd_t cmdSCU = {/* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + u16_t cmdResult = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + WR16(devAddr, ATV_TOP_CR_FREQ__A, ATV_TOP_CR_FREQ__PRE); + + /* Start ATV SCU */ + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 1; + cmdSCU.parameter = NULL; + cmdSCU.result = &cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + +/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == TRUE) ) + { + extAttr->detectedRDS = (Bool_t)FALSE; + }*/ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/* -------------------------------------------------------------------------- */ + +/** +* \fn DRXStatus_t GetATVChannel () +* \brief Set ATV channel. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param standard: NTSC or FM. +* \return DRXStatus_t. +* +* Covers NTSC, PAL/SECAM - B/G, D/K, I, L, LP and FM. +* Computes the frequency offset in te RF domain and adds it to +* channel->frequency. Determines the value for channel->bandwidth. +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +GetATVChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel, + DRXStandard_t standard ) +{ + DRXFrequency_t offset = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* Bandwidth */ + channel->bandwidth = ((pDRXJData_t)demod -> myExtAttr)->currBandwidth; + + switch ( standard ) + { + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + { + u16_t measuredOffset=0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ( (measuredOffset & 0x0080) != 0) + { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset+= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); + break; + } + case DRX_STANDARD_PAL_SECAM_LP: + { + u16_t measuredOffset=0; + + /* get measured frequency offset */ + RR16(devAddr, ATV_TOP_CR_FREQ__A, &measuredOffset); + /* Signed 8 bit register => sign extension needed */ + if ( (measuredOffset & 0x0080) != 0) + { + /* sign extension */ + measuredOffset |= 0xFF80; + } + offset-= (DRXFrequency_t)( ((s16_t)measuredOffset)*10); + } + break; + case DRX_STANDARD_FM: + /* TODO: compute offset using AUD_DSP_RD_FM_DC_LEVEL_A__A and + AUD_DSP_RD_FM_DC_LEVEL_B__A. For now leave frequency as is. + */ + /* No bandwidth know for FM */ + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + break; + default: + return ( DRX_STS_ERROR ); + } + + channel->frequency -= offset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t GetAtvSigStrength() +* \brief Retrieve signal strength for ATV & FM. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sigStrength equals 0. +* +* Taking into account: +* * digital gain +* * IF gain (not implemented yet, waiting for IF gain control by ucode) +* * RF gain +* +* All weights (digital, if, rf) must add up to 100. +* +* TODO: ? dynamically adapt weights in case RF and/or IF agc of drxj +* is not used ? +*/ +static DRXStatus_t +GetAtvSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* All weights must add up to 100 (%) + TODO: change weights when IF ctrl is available */ + u32_t digitalWeight = 50; /* 0 .. 100 */ + u32_t rfWeight = 50; /* 0 .. 100 */ + u32_t ifWeight = 0; /* 0 .. 100 */ + + u16_t digitalCurrGain = 0; + u32_t digitalMaxGain = 0; + u32_t digitalMinGain = 0; + u16_t rfCurrGain = 0; + u32_t rfMaxGain = 0x800; /* taken from ucode */ + u32_t rfMinGain = 0x7fff; + u16_t ifCurrGain = 0; + u32_t ifMaxGain = 0x800; /* taken from ucode */ + u32_t ifMinGain = 0x7fff; + + u32_t digitalStrength = 0; /* 0.. 100 */ + u32_t rfStrength = 0; /* 0.. 100 */ + u32_t ifStrength = 0; /* 0.. 100 */ + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + *sigStrength = 0; + + switch( extAttr->standard ) + { + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: + SARR16(devAddr, SCU_RAM_ATV_VID_GAIN_HI__A, &digitalCurrGain); + digitalMaxGain = 22512; /* taken from ucode */ + digitalMinGain = 2400; /* taken from ucode */ + break; + case DRX_STANDARD_FM: + SARR16(devAddr, SCU_RAM_ATV_SIF_GAIN__A, &digitalCurrGain); + digitalMaxGain = 0x4ff; /* taken from ucode */ + digitalMinGain = 0; /* taken from ucode */ + break; + default: + return (DRX_STS_ERROR); + break; + } + RR16(devAddr, IQM_AF_AGC_RF__A, &rfCurrGain); + RR16(devAddr, IQM_AF_AGC_IF__A, &ifCurrGain); + + /* clipping */ + if ( digitalCurrGain >= digitalMaxGain ) digitalCurrGain = (u16_t)digitalMaxGain; + if ( digitalCurrGain <= digitalMinGain ) digitalCurrGain = (u16_t)digitalMinGain; + if ( ifCurrGain <= ifMaxGain ) ifCurrGain = (u16_t)ifMaxGain; + if ( ifCurrGain >= ifMinGain ) ifCurrGain = (u16_t)ifMinGain; + if ( rfCurrGain <= rfMaxGain ) rfCurrGain = (u16_t)rfMaxGain; + if ( rfCurrGain >= rfMinGain ) rfCurrGain = (u16_t)rfMinGain; + + /* TODO: use SCU_RAM_ATV_RAGC_HR__A to shift max and min in case + of clipping at ADC */ + + /* Compute signal strength (in %) per "gain domain" */ + + /* Digital gain */ + /* TODO: ADC clipping not handled */ + digitalStrength = ( 100 *(digitalMaxGain-(u32_t)digitalCurrGain) )/ + (digitalMaxGain -digitalMinGain); + + /* TODO: IF gain not implemented yet in microcode, check after impl. */ + ifStrength = ( 100 *((u32_t)ifCurrGain-ifMaxGain) )/ + ( ifMinGain - ifMaxGain ); + + /* Rf gain */ + /* TODO: ADC clipping not handled */ + rfStrength = ( 100 *((u32_t)rfCurrGain-rfMaxGain) )/ + ( rfMinGain - rfMaxGain ); + + /* Compute a weighted signal strength (in %) */ + *sigStrength = (u16_t) (digitalWeight*digitalStrength + + rfWeight*rfStrength + + ifWeight*ifStrength); + *sigStrength /= 100; + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/* -------------------------------------------------------------------------- */ +/** +* \fn DRXStatus_t AtvSigQuality() +* \brief Retrieve signal quality indication for ATV. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality structure. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_ERROR Erroneous data, sigQuality indicator equals 0. +* +* +*/ +static DRXStatus_t +AtvSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t qualityIndicator = 0; + + devAddr = demod -> myI2CDevAddr; + + /* defined values for fields not used */ + sigQuality->MER = 0; + sigQuality->preViterbiBER = 0; + sigQuality->postViterbiBER = 0; + sigQuality->scaleFactorBER = 1; + sigQuality->packetError = 0; + sigQuality->postReedSolomonBER = 0; + + /* + Mapping: + 0x000..0x080: strong signal => 80% .. 100% + 0x080..0x700: weak signal => 30% .. 80% + 0x700..0x7ff: no signal => 0% .. 30% + */ + + SARR16( devAddr, SCU_RAM_ATV_CR_LOCK__A, &qualityIndicator ); + qualityIndicator &= SCU_RAM_ATV_CR_LOCK_CR_LOCK__M; + if ( qualityIndicator <= 0x80 ) + { + sigQuality->indicator = 80 + ( (20*(0x80-qualityIndicator))/0x80); + } else if ( qualityIndicator <= 0x700 ) + { + sigQuality->indicator = 30 + + ( (50*(0x700-qualityIndicator))/(0x700-0x81)); + } else { + sigQuality->indicator = + (30*(0x7FF-qualityIndicator))/(0x7FF-0x701); + } + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} +#endif /* DRXJ_DIGITAL_ONLY */ + +/*============================================================================*/ +/*== END ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +#ifndef DRXJ_EXCLUDE_AUDIO +/*===========================================================================*/ +/*===========================================================================*/ +/*== AUDIO DATAPATH FUNCTIONS ==*/ +/*===========================================================================*/ +/*===========================================================================*/ + +/* +* \brief Power up AUD. +* \param demod instance of demodulator +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +PowerUpAud( pDRXDemodInstance_t demod, + Bool_t setStandard) +{ + DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod->myI2CDevAddr; + + WR16( devAddr, AUD_TOP_COMM_EXEC__A, AUD_TOP_COMM_EXEC_ACTIVE); + /* setup TR interface: R/W mode, fifosize=8 */ + WR16( devAddr, AUD_TOP_TR_MDE__A, 8); + WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE); + + if ( setStandard == TRUE ) + { + CHK_ERROR( AUDCtrlSetStandard ( demod, &audStandard ) ); + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ + +/** +* \brief Power up AUD. +* \param demod instance of demodulator +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +PowerDownAud( pDRXDemodInstance_t demod ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP ); + + extAttr->audData.audioIsActive = FALSE; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} +/*============================================================================*/ +/** +* \brief Get Modus data from audio RAM +* \param demod instance of demodulator +* \param pointer to modus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDGetModus ( pDRXDemodInstance_t demod, + pu16_t modus ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rModus = 0; + u16_t rModusHi = 0; + u16_t rModusLo = 0; + + if ( modus == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Modus register is combined in to RAM location */ + RR16( devAddr, AUD_DEM_RAM_MODUS_HI__A, &rModusHi ); + RR16( devAddr, AUD_DEM_RAM_MODUS_LO__A, &rModusLo ); + + rModus = ( (rModusHi << 12 ) & AUD_DEM_RAM_MODUS_HI__M) + | ((( rModusLo & AUD_DEM_RAM_MODUS_LO__M) )); + + *modus = rModus; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; + +} + +/*============================================================================*/ +/** +* \brief Get audio RDS dat +* \param demod instance of demodulator +* \param pointer to DRXCfgAudRDS_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgRDS ( pDRXDemodInstance_t demod, + pDRXCfgAudRDS_t status ) +{ + pI2CDeviceAddr_t addr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rRDSArrayCntInit = 0; + u16_t rRDSArrayCntCheck = 0; + u16_t rRDSData = 0; + u16_t RDSDataCnt = 0; + + addr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + + if ( status == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + status->valid = FALSE; + + RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit); + + if ( rRDSArrayCntInit == + AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID ) + { + /* invalid data */ + return DRX_STS_OK; + } + + if ( extAttr->audData.rdsDataCounter == rRDSArrayCntInit) + { + /* no new data */ + return DRX_STS_OK; + } + + /* RDS is detected, as long as FM radio is selected assume + RDS will be available */ + extAttr->audData.rdsDataPresent = TRUE; + + /* new data */ + /* read the data */ + for ( RDSDataCnt = 0; + RDSDataCnt < AUD_RDS_ARRAY_SIZE; + RDSDataCnt++) + { + RR16 ( addr, AUD_DEM_RD_RDS_DATA__A, &rRDSData ); + status->data[RDSDataCnt] = rRDSData; + } + + RR16( addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck); + + if ( rRDSArrayCntCheck == rRDSArrayCntInit ) + { + status->valid = TRUE; + extAttr->audData.rdsDataCounter = rRDSArrayCntCheck; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current audio carrier detection status +* \param demod instance of demodulator +* \param pointer to AUDCtrlGetStatus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCarrierDetectStatus ( pDRXDemodInstance_t demod, + pDRXAudStatus_t status ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + + u16_t rData = 0; + + if ( status == NULL) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* initialize the variables */ + status->carrierA = FALSE; + status->carrierB = FALSE; + status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED; + status->sap = FALSE; + status->stereo = FALSE; + + /* read stereo sound mode indication */ + RR16( devAddr, AUD_DEM_RD_STATUS__A, &rData ); + + /* carrier a detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M ) == + AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED ) + { + status->carrierA = TRUE; + } + + /* carrier b detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M ) == + AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED ) + { + status->carrierB = TRUE; + } + /* nicam detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) == + AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED) + { + if ((rData & AUD_DEM_RD_STATUS_BAD_NICAM__M) == + AUD_DEM_RD_STATUS_BAD_NICAM_OK) + { + status->nicamStatus = DRX_AUD_NICAM_DETECTED; + } + else + { + status->nicamStatus = DRX_AUD_NICAM_BAD; + } + } + + /* audio mode bilingual or SAP detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) == + AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) + { + status->sap = TRUE; + } + + /* stereo detected */ + if ( (rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) == + AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) + { + status->stereo = TRUE; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get the current audio status parameters +* \param demod instance of demodulator +* \param pointer to AUDCtrlGetStatus +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetStatus ( pDRXDemodInstance_t demod, + pDRXAudStatus_t status ) +{ + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXCfgAudRDS_t rds = { FALSE, {0} }; + u16_t rData = 0; + + if ( status == NULL) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* carrier detection */ + CHK_ERROR ( AUDCtrlGetCarrierDetectStatus ( demod, status ) ); + + /* rds data */ + status->rds = FALSE; + CHK_ERROR ( AUDCtrlGetCfgRDS ( demod, &rds ) ); + status->rds = extAttr->audData.rdsDataPresent; + + /* fmIdent */ + RR16( devAddr, AUD_DSP_RD_FM_IDENT_VALUE__A, &rData); + rData >>= AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B; + status->fmIdent = (s8_t)rData; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current volume settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudVolume_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgVolume ( pDRXDemodInstance_t demod, + pDRXCfgAudVolume_t volume ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rVolume = 0; + u16_t rAVC = 0; + u16_t rStrengthLeft = 0; + u16_t rStrengthRight = 0; + + if ( volume == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* volume */ + volume->mute = extAttr->audData.volume.mute; + RR16( devAddr, AUD_DSP_WR_VOLUME__A, &rVolume ); + if ( rVolume == 0 ) + { + volume->mute = TRUE; + volume->volume = extAttr->audData.volume.volume; + } + else + { + volume->mute = FALSE; + volume->volume = ( ( rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M ) >> + AUD_DSP_WR_VOLUME_VOL_MAIN__B ) - + AUD_VOLUME_ZERO_DB; + if ( volume->volume < AUD_VOLUME_DB_MIN ) + { + volume->volume = AUD_VOLUME_DB_MIN; + } + if ( volume->volume > AUD_VOLUME_DB_MAX ) + { + volume->volume = AUD_VOLUME_DB_MAX; + } + } + + /* automatic volume control */ + RR16( devAddr, AUD_DSP_WR_AVC__A, &rAVC ); + + if( ( rAVC & AUD_DSP_WR_AVC_AVC_ON__M) == + AUD_DSP_WR_AVC_AVC_ON_OFF ) + + { + volume->avcMode = DRX_AUD_AVC_OFF; + } + else + { + switch ( rAVC & AUD_DSP_WR_AVC_AVC_DECAY__M ) + { + case AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_20MS; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_8_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_8S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_4_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_4S; + break; + case AUD_DSP_WR_AVC_AVC_DECAY_2_SEC: + volume->avcMode = DRX_AUD_AVC_DECAYTIME_2S; + break; + default: + return DRX_STS_ERROR; + break; + } + } + + /* max attenuation */ + switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_ATT__M ) + { + case AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_12DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_18DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB: + volume->avcMaxAtten = DRX_AUD_AVC_MAX_ATTEN_24DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* max gain */ + switch ( rAVC & AUD_DSP_WR_AVC_AVC_MAX_GAIN__M ) + { + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_0DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_6DB; + break; + case AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB: + volume->avcMaxGain = DRX_AUD_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* reference level */ + volume->avcRefLevel = (u16_t)( ( rAVC & AUD_DSP_WR_AVC_AVC_REF_LEV__M) >> + AUD_DSP_WR_AVC_AVC_REF_LEV__B ); + + /* read qpeak registers and calculate strength of left and right carrier */ + /* quasi peaks formula: QP(dB) = 20 * log( AUD_DSP_RD_QPEAKx / Q(0dB) */ + /* Q(0dB) represents QP value of 0dB (hex value 0x4000) */ + /* left carrier */ + + /* QP vaues */ + /* left carrier */ + RR16 (devAddr, AUD_DSP_RD_QPEAK_L__A, &rStrengthLeft); + volume->strengthLeft = ( ( (s16_t) Log10Times100 ( rStrengthLeft ) ) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; + + /* right carrier */ + RR16 (devAddr, AUD_DSP_RD_QPEAK_R__A, &rStrengthRight); + volume->strengthRight = ( ( (s16_t) Log10Times100 ( rStrengthRight ) ) - + AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 ) / 5; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Set the current volume settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudVolume_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgVolume ( pDRXDemodInstance_t demod, + pDRXCfgAudVolume_t volume ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wVolume = 0; + u16_t wAVC = 0; + + + if ( volume == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* volume */ + /* volume range from -60 to 12 (expressed in dB) */ + if ( ( volume->volume < AUD_VOLUME_DB_MIN ) || + ( volume->volume > AUD_VOLUME_DB_MAX ) ) + { + return DRX_STS_INVALID_ARG; + } + + RR16( devAddr, AUD_DSP_WR_VOLUME__A, &wVolume ); + + /* clear the volume mask */ + wVolume &= (u16_t)~AUD_DSP_WR_VOLUME_VOL_MAIN__M; + if ( volume->mute == TRUE ) + { + /* mute */ + /* mute overrules volume */ + wVolume |= (u16_t) ( 0 ); + + } + else + { + wVolume |= (u16_t) ( ( volume->volume + AUD_VOLUME_ZERO_DB ) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B ); + } + + WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); + + /* automatic volume control */ + RR16( devAddr, AUD_DSP_WR_AVC__A, &wAVC ); + + /* clear masks that require writing */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_ON__M; + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_DECAY__M; + + if ( volume->avcMode == DRX_AUD_AVC_OFF ) + { + wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_OFF ); + } + else + { + + wAVC |= ( AUD_DSP_WR_AVC_AVC_ON_ON ); + + /* avc decay */ + switch ( volume->avcMode ) + { + case DRX_AUD_AVC_DECAYTIME_20MS: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC; + break; + case DRX_AUD_AVC_DECAYTIME_8S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_8_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_4S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_4_SEC; + break; + case DRX_AUD_AVC_DECAYTIME_2S: + wAVC |= AUD_DSP_WR_AVC_AVC_DECAY_2_SEC; + break; + default: + return DRX_STS_INVALID_ARG; + } + } + + /* max attenuation */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M; + switch ( volume->avcMaxAtten ) + { + case DRX_AUD_AVC_MAX_ATTEN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_18DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB; + break; + case DRX_AUD_AVC_MAX_ATTEN_24DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* max gain */ + wAVC &= (u16_t) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M; + switch ( volume->avcMaxGain ) + { + case DRX_AUD_AVC_MAX_GAIN_0DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB; + break; + case DRX_AUD_AVC_MAX_GAIN_6DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB; + break; + case DRX_AUD_AVC_MAX_GAIN_12DB: + wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* avc reference level */ + if ( volume->avcRefLevel > AUD_MAX_AVC_REF_LEVEL ) + { + return DRX_STS_INVALID_ARG; + } + + wAVC &= (u16_t)~AUD_DSP_WR_AVC_AVC_REF_LEV__M; + wAVC |= (u16_t)( volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B ); + + WR16( devAddr, AUD_DSP_WR_AVC__A, wAVC ); + + /* all done, store config in data structure */ + extAttr->audData.volume = *volume; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get the I2S settings +* \param demod instance of demodulator +* \param pointer to DRXCfgI2SOutput_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgOutputI2S ( pDRXDemodInstance_t demod, + pDRXCfgI2SOutput_t output ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wI2SConfig = 0; + u16_t rI2SFreq = 0; + + if ( output == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); + RR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, &rI2SFreq ); + + /* I2S mode */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER: + output->mode = DRX_I2S_MODE_MASTER; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE: + output->mode = DRX_I2S_MODE_SLAVE; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S format */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY: + output->format = DRX_I2S_FORMAT_WS_ADVANCED; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY: + output->format = DRX_I2S_FORMAT_WS_WITH_DATA; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S word length */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16: + output->wordLength = DRX_I2S_WORDLENGTH_16; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32: + output->wordLength = DRX_I2S_WORDLENGTH_32; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S polarity */ + switch ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M ) + { + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH: + output->polarity = DRX_I2S_POLARITY_LEFT; + break; + case AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW: + output->polarity = DRX_I2S_POLARITY_RIGHT; + break; + default: + return DRX_STS_ERROR; + } + + /* I2S output enabled */ + if ( ( wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M ) + == AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE ) + { + output->outputEnable = TRUE; + } + else + { + output->outputEnable = FALSE; + } + + if ( rI2SFreq > 0 ) + { + output->frequency = 6144UL * 48000 / rI2SFreq; + if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) + { + output->frequency *= 2; + } + } + else + { + output->frequency = AUD_I2S_FREQUENCY_MAX; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set the I2S settings +* \param demod instance of demodulator +* \param pointer to DRXCfgI2SOutput_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgOutputI2S ( pDRXDemodInstance_t demod, + pDRXCfgI2SOutput_t output ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t wI2SConfig = 0; + u16_t wI2SPadsDataDa = 0; + u16_t wI2SPadsDataCl = 0; + u16_t wI2SPadsDataWs = 0; + u32_t wI2SFreq = 0; + + if ( output == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig ); + + /* I2S mode */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M; + + switch ( output->mode ) + { + case DRX_I2S_MODE_MASTER: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER; + break; + case DRX_I2S_MODE_SLAVE: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S format */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M; + + switch ( output->format ) + { + case DRX_I2S_FORMAT_WS_ADVANCED: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY; + break; + case DRX_I2S_FORMAT_WS_WITH_DATA: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S word length */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M; + + switch ( output->wordLength ) + { + case DRX_I2S_WORDLENGTH_16: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16; + break; + case DRX_I2S_WORDLENGTH_32: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S polarity */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M; + switch ( output->polarity ) + { + case DRX_I2S_POLARITY_LEFT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH; + break; + case DRX_I2S_POLARITY_RIGHT: + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* I2S output enabled */ + wI2SConfig &= (u16_t)~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M; + if ( output->outputEnable == TRUE ) + { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE; + } + else + { + wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE; + } + + /* + I2S frequency + + wI2SFreq = 6144 * 48000 * nrbits / ( 32 * frequency ) + + 16bit: 6144 * 48000 / ( 2 * freq ) = ( 6144 * 48000 / freq ) / 2 + 32bit: 6144 * 48000 / freq = ( 6144 * 48000 / freq ) + */ + if ( ( output->frequency > AUD_I2S_FREQUENCY_MAX ) || + output->frequency < AUD_I2S_FREQUENCY_MIN ) + { + return DRX_STS_INVALID_ARG; + } + + wI2SFreq = (6144UL * 48000UL) + (output->frequency >> 1); + wI2SFreq /= output->frequency; + + if ( output->wordLength == DRX_I2S_WORDLENGTH_16 ) + { + wI2SFreq *= 2; + } + + WR16( devAddr, AUD_DEM_WR_I2S_CONFIG2__A, wI2SConfig ); + WR16( devAddr, AUD_DSP_WR_I2S_OUT_FS__A, (u16_t) wI2SFreq ); + + /* configure I2S output pads for master or slave mode */ + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY ); + + if (output->mode == DRX_I2S_MODE_MASTER) + { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__MASTER | + SIO_PDR_I2S_DA_CFG_DRIVE__MASTER; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__MASTER | + SIO_PDR_I2S_CL_CFG_DRIVE__MASTER; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__MASTER | + SIO_PDR_I2S_WS_CFG_DRIVE__MASTER; + } + else + { + wI2SPadsDataDa = SIO_PDR_I2S_DA_CFG_MODE__SLAVE | + SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE; + wI2SPadsDataCl = SIO_PDR_I2S_CL_CFG_MODE__SLAVE | + SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE; + wI2SPadsDataWs = SIO_PDR_I2S_WS_CFG_MODE__SLAVE | + SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE; + } + + WR16( devAddr, SIO_PDR_I2S_DA_CFG__A, wI2SPadsDataDa ); + WR16( devAddr, SIO_PDR_I2S_CL_CFG__A, wI2SPadsDataCl ); + WR16( devAddr, SIO_PDR_I2S_WS_CFG__A, wI2SPadsDataWs ); + + WR16( devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE ); + + + /* all done, store config in data structure */ + extAttr->audData.i2sdata = *output; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select (ASS) +* and Automatic Sound Change (ASC) +* \param demod instance of demodulator +* \param pointer to pDRXAudAutoSound_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgAutoSound ( pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + + if ( autoSound == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + switch ( rModus & ( AUD_DEM_WR_MODUS_MOD_ASS__M | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M ) ) + { + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + case AUD_DEM_WR_MODUS_MOD_ASS_OFF | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = DRX_AUD_AUTO_SOUND_OFF; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED: + *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON; + break; + case AUD_DEM_WR_MODUS_MOD_ASS_ON | + AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED: + *autoSound = DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF; + break; + default: + return DRX_STS_ERROR; + } + + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} +/*============================================================================*/ +/** +* \brief Set the Automatic Standard Select (ASS) +* and Automatic Sound Change (ASC) +* \param demod instance of demodulator +* \param pointer to pDRXAudAutoSound_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrSetlCfgAutoSound ( pDRXDemodInstance_t demod, + pDRXCfgAudAutoSound_t autoSound ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + u16_t wModus = 0; + + if ( autoSound == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + /* clear ASS & ASC bits */ + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_ASS__M; + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M; + + switch ( *autoSound ) + { + case DRX_AUD_AUTO_SOUND_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_OFF; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED; + break; + case DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF: + wModus |= AUD_DEM_WR_MODUS_MOD_ASS_ON; + wModus |= AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED; + break; + default: + return DRX_STS_INVALID_ARG; + } + + if ( wModus != rModus ) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + /* copy to data structure */ + extAttr->audData.autoSound = *autoSound; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select thresholds +* \param demod instance of demodulator +* \param pointer to pDRXAudASSThres_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgASSThres ( pDRXDemodInstance_t demod, + pDRXCfgAudASSThres_t thres ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t thresA2 = 0; + u16_t thresBtsc = 0; + u16_t thresNicam = 0; + + if ( thres == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + RR16( devAddr , AUD_DEM_RAM_A2_THRSHLD__A, &thresA2 ); + RR16( devAddr , AUD_DEM_RAM_BTSC_THRSHLD__A, &thresBtsc ); + RR16( devAddr , AUD_DEM_RAM_NICAM_THRSHLD__A, &thresNicam ); + + thres->a2 = thresA2; + thres->btsc = thresBtsc; + thres->nicam = thresNicam; + + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the Automatic Standard Select thresholds +* \param demod instance of demodulator +* \param pointer to pDRXAudASSThres_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgASSThres ( pDRXDemodInstance_t demod, + pDRXCfgAudASSThres_t thres ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + if ( thres == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + WR16( devAddr , AUD_DEM_WR_A2_THRSHLD__A, thres->a2 ); + WR16( devAddr , AUD_DEM_WR_BTSC_THRSHLD__A, thres->btsc ); + WR16( devAddr , AUD_DEM_WR_NICAM_THRSHLD__A, thres->nicam ); + + /* update DRXK data structure with hardware values */ + extAttr->audData.assThresholds = *thres; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get Audio Carrier settings +* \param demod instance of demodulator +* \param pointer to pDRXAudCarrier_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgCarrier ( pDRXDemodInstance_t demod, + pDRXCfgAudCarriers_t carriers ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; + + u32_t valA = 0; + u32_t valB = 0; + + u16_t dcLvlA = 0; + u16_t dcLvlB = 0; + + u16_t cmThesA = 0; + u16_t cmThesB = 0; + + if ( carriers == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + CHK_ERROR ( AUDGetModus ( demod, &wModus )); + + /* Behaviour of primary audio channel */ + switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_A__M) ) + { + case AUD_DEM_WR_MODUS_MOD_CM_A_MUTE: + carriers->a.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_A_NOISE: + carriers->a.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* Behaviour of secondary audio channel */ + switch ( wModus & ( AUD_DEM_WR_MODUS_MOD_CM_B__M) ) + { + case AUD_DEM_WR_MODUS_MOD_CM_B_MUTE: + carriers->b.opt = DRX_NO_CARRIER_MUTE; + break; + case AUD_DEM_WR_MODUS_MOD_CM_B_NOISE: + carriers->b.opt = DRX_NO_CARRIER_NOISE; + break; + default: + return DRX_STS_ERROR; + break; + } + + /* frequency adjustment for primary & secondary audio channel */ + RR16( devAddr, AUD_DEM_RAM_DCO_A_HI__A, &dcoAHi ); + RR16( devAddr, AUD_DEM_RAM_DCO_A_LO__A, &dcoALo ); + RR16( devAddr, AUD_DEM_RAM_DCO_B_HI__A, &dcoBHi ); + RR16( devAddr, AUD_DEM_RAM_DCO_B_LO__A, &dcoBLo ); + + valA = ( ( (u32_t) dcoAHi) << 12 ) | ( (u32_t) dcoALo & 0xFFF ); + valB = ( ( (u32_t) dcoBHi) << 12 ) | ( (u32_t) dcoBLo & 0xFFF ); + + /* Multiply by 20250 * 1>>24 ~= 2 / 1657 */ + carriers->a.dco = DRX_S24TODRXFREQ( valA ) * 2L / 1657L; + carriers->b.dco = DRX_S24TODRXFREQ( valB ) * 2L / 1657L; + + /* DC level of the incoming FM signal on the primary + & seconday sound channel */ + RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_A__A, &dcLvlA ); + RR16( devAddr, AUD_DSP_RD_FM_DC_LEVEL_B__A, &dcLvlB ); + + /* offset (kHz) = (dcLvl / 322) */ + carriers->a.shift = ( DRX_U16TODRXFREQ( dcLvlA ) / 322L ); + carriers->b.shift = ( DRX_U16TODRXFREQ( dcLvlB ) / 322L ); + + /* Carrier detetcion threshold for primary & secondary channel */ + RR16( devAddr, AUD_DEM_RAM_CM_A_THRSHLD__A, &cmThesA); + RR16( devAddr, AUD_DEM_RAM_CM_B_THRSHLD__A, &cmThesB); + + carriers->a.thres = cmThesA; + carriers->b.thres = cmThesB; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set Audio Carrier settings +* \param demod instance of demodulator +* \param pointer to pDRXAudCarrier_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgCarrier ( pDRXDemodInstance_t demod, + pDRXCfgAudCarriers_t carriers ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + u16_t rModus = 0; + + u16_t dcoAHi = 0; + u16_t dcoALo = 0; + u16_t dcoBHi = 0; + u16_t dcoBLo = 0; + + s32_t valA = 0; + s32_t valB = 0; + + if ( carriers == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + + wModus = rModus; + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_A__M; + /* Behaviour of primary audio channel */ + switch ( carriers->a.opt ) + { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_A_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + /* Behaviour of secondary audio channel */ + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_CM_B__M; + switch ( carriers->b.opt ) + { + case DRX_NO_CARRIER_MUTE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE; + break; + case DRX_NO_CARRIER_NOISE: + wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_NOISE; + break; + default: + return DRX_STS_INVALID_ARG; + break; + } + + /* now update the modus register */ + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + + /* frequency adjustment for primary & secondary audio channel */ + valA = (s32_t) ( ( carriers->a.dco ) * 1657L / 2); + valB = (s32_t) ( ( carriers->b.dco ) * 1657L / 2); + + dcoAHi = (u16_t) ( ( valA >> 12 ) & 0xFFF ); + dcoALo = (u16_t) ( valA & 0xFFF ); + dcoBHi = (u16_t) ( ( valB >> 12 ) & 0xFFF ); + dcoBLo = (u16_t) ( valB & 0xFFF ); + + WR16( devAddr, AUD_DEM_WR_DCO_A_HI__A, dcoAHi ); + WR16( devAddr, AUD_DEM_WR_DCO_A_LO__A, dcoALo ); + WR16( devAddr, AUD_DEM_WR_DCO_B_HI__A, dcoBHi ); + WR16( devAddr, AUD_DEM_WR_DCO_B_LO__A, dcoBLo ); + + /* Carrier detetcion threshold for primary & secondary channel */ + WR16( devAddr, AUD_DEM_WR_CM_A_THRSHLD__A, carriers->a.thres); + WR16( devAddr, AUD_DEM_WR_CM_B_THRSHLD__A, carriers->b.thres); + + /* update DRXK data structure */ + extAttr->audData.carriers = *carriers; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get I2S Source, I2S matrix and FM matrix +* \param demod instance of demodulator +* \param pointer to pDRXAudmixer_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgMixer ( pDRXDemodInstance_t demod, + pDRXCfgAudMixer_t mixer ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; + + if ( mixer == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Source Selctor */ + RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + + switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M ) + { + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO: + mixer->sourceI2S = DRX_AUD_SRC_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_AB; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_A; + break; + case AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B: + mixer->sourceI2S = DRX_AUD_SRC_STEREO_OR_B; + break; + default: + return DRX_STS_ERROR; + } + + /* Matrix */ + switch ( srcI2SMatr & AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M ) + { + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_STEREO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_A_MONO; + break; + case AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B: + mixer->matrixI2S = DRX_AUD_I2S_MATRIX_B_MONO; + break; + default: + return DRX_STS_ERROR; + } + + /* FM Matrix */ + RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); + switch ( fmMatr & AUD_DEM_WR_FM_MATRIX__M ) + { + case AUD_DEM_WR_FM_MATRIX_NO_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_NO_MATRIX; + break; + case AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_GERMAN; + break; + case AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX: + mixer->matrixFm = DRX_AUD_FM_MATRIX_KOREAN; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_A: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_A; + break; + case AUD_DEM_WR_FM_MATRIX_SOUND_B: + mixer->matrixFm = DRX_AUD_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set I2S Source, I2S matrix and FM matrix +* \param demod instance of demodulator +* \param pointer to DRXAudmixer_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgMixer ( pDRXDemodInstance_t demod, + pDRXCfgAudMixer_t mixer ) + { + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t srcI2SMatr = 0; + u16_t fmMatr = 0; + + if ( mixer == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* Source Selctor */ + RR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr); + srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M; + + switch (mixer->sourceI2S) + { + case DRX_AUD_SRC_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO; + break; + case DRX_AUD_SRC_STEREO_OR_AB: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB; + break; + case DRX_AUD_SRC_STEREO_OR_A: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A; + break; + case DRX_AUD_SRC_STEREO_OR_B: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* Matrix */ + srcI2SMatr &= (u16_t)~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M; + switch (mixer->matrixI2S) + { + case DRX_AUD_I2S_MATRIX_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO; + break; + case DRX_AUD_I2S_MATRIX_STEREO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO ; + break; + case DRX_AUD_I2S_MATRIX_A_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A; + break; + case DRX_AUD_I2S_MATRIX_B_MONO: + srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + /* write the result */ + WR16( devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, srcI2SMatr); + + /* FM Matrix */ + RR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr ); + fmMatr &= (u16_t)~AUD_DEM_WR_FM_MATRIX__M; + switch (mixer->matrixFm) + { + case DRX_AUD_FM_MATRIX_NO_MATRIX: + fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX; + break; + case DRX_AUD_FM_MATRIX_GERMAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_KOREAN: + fmMatr |= AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX; + break; + case DRX_AUD_FM_MATRIX_SOUND_A: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_A; + break; + case DRX_AUD_FM_MATRIX_SOUND_B: + fmMatr |= AUD_DEM_WR_FM_MATRIX_SOUND_B; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* Only write if ASS is off */ + if ( extAttr->audData.autoSound == DRX_AUD_AUTO_SOUND_OFF ) + { + WR16( devAddr, AUD_DEM_WR_FM_MATRIX__A, fmMatr ); + } + + /* update the data structure with hardware state */ + extAttr->audData.mixer = *mixer; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set AV Sync settings +* \param demod instance of demodulator +* \param pointer to DRXICfgAVSync_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgAVSync ( pDRXDemodInstance_t demod, + pDRXCfgAudAVSync_t avSync ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wAudVidSync = 0; + + if ( avSync == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* audio/video synchronisation */ + RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + + wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_ON__M; + + if ( *avSync == DRX_AUD_AVSYNC_OFF ) + { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE; + } + else + { + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE; + } + + wAudVidSync &= (u16_t)~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M; + + switch ( *avSync ) + { + case DRX_AUD_AVSYNC_NTSC: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC; + break; + case DRX_AUD_AVSYNC_MONOCHROME: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME; + break; + case DRX_AUD_AVSYNC_PAL_SECAM: + wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM; + break; + case DRX_AUD_AVSYNC_OFF: + /* OK */ + break; + default: + return DRX_STS_INVALID_ARG; + } + + WR16( devAddr, AUD_DSP_WR_AV_SYNC__A, wAudVidSync ); + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get AV Sync settings +* \param demod instance of demodulator +* \param pointer to DRXICfgAVSync_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgAVSync ( pDRXDemodInstance_t demod, + pDRXCfgAudAVSync_t avSync ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wAudVidSync = 0; + + if ( avSync == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* audio/video synchronisation */ + RR16( devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync ); + + if ( ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_ON__M ) == + AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE ) + { + *avSync = DRX_AUD_AVSYNC_OFF; + return DRX_STS_OK; + } + + switch ( wAudVidSync & AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M ) + { + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC: + *avSync = DRX_AUD_AVSYNC_NTSC; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME: + *avSync = DRX_AUD_AVSYNC_MONOCHROME; + break; + case AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM: + *avSync = DRX_AUD_AVSYNC_PAL_SECAM; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get deviation mode +* \param demod instance of demodulator +* \param pointer to DRXCfgAudDeviation_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgDev ( pDRXDemodInstance_t demod, + pDRXCfgAudDeviation_t dev ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rModus = 0; + + + if ( dev == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + switch ( rModus & AUD_DEM_WR_MODUS_MOD_HDEV_A__M) + { + case AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL: + *dev = DRX_AUD_DEVIATION_NORMAL; + break; + case AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION: + *dev = DRX_AUD_DEVIATION_HIGH; + break; + default: + return DRX_STS_ERROR; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get deviation mode +* \param demod instance of demodulator +* \param pointer to DRXCfgAudDeviation_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgDev ( pDRXDemodInstance_t demod, + pDRXCfgAudDeviation_t dev ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wModus = 0; + u16_t rModus = 0; + + if ( dev == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod->myI2CDevAddr; + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_HDEV_A__M; + + switch ( *dev ) + { + case DRX_AUD_DEVIATION_NORMAL: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL; + break; + case DRX_AUD_DEVIATION_HIGH: + wModus |= AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION; + break; + default: + return DRX_STS_INVALID_ARG; + } + + /* now update the modus register */ + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + /* store in drxk data struct */ + extAttr->audData.deviation = *dev; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Get Prescaler settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudPrescale_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetCfgPrescale( pDRXDemodInstance_t demod, + pDRXCfgAudPrescale_t presc ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t rMaxFMDeviation = 0; + u16_t rNicamPrescaler = 0; + + if ( presc == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* read register data */ + RR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, &rNicamPrescaler ); + RR16( devAddr, AUD_DSP_WR_FM_PRESC__A, &rMaxFMDeviation ); + + /* calculate max FM deviation */ + rMaxFMDeviation >>= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if ( rMaxFMDeviation > 0 ) + { + presc->fmDeviation = 3600UL + (rMaxFMDeviation >> 1); + presc->fmDeviation /= rMaxFMDeviation; + } + else + { + presc->fmDeviation = 380; /* kHz */ + } + + /* calculate NICAM gain from pre-scaler */ + /* + nicamGain = 20 * ( log10( preScaler / 16) ) + = ( 100log10( preScaler ) - 100log10( 16 ) ) / 5 + + because Log10Times100() cannot return negative numbers + = ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) / 5 + + + for 0.1dB resolution: + + nicamGain = 200 * ( log10( preScaler / 16) ) + = 2 * ( 100log10( 10 * preScaler ) - 100log10( 10 * 16) ) + = ( 100log10( 10 * preScaler^2 ) - 100log10( 10 * 16^2 ) ) + + + */ + rNicamPrescaler >>= 8; + if ( rNicamPrescaler <= 1 ) + { + presc->nicamGain = -241; + } + else + { + + presc->nicamGain = (s16_t)( ( (s32_t) + ( Log10Times100( 10 * rNicamPrescaler * + rNicamPrescaler ) ) - + (s32_t) + ( Log10Times100( 10 * 16 * 16 ) ) ) ); + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + + +/*============================================================================*/ +/** +* \brief Set Prescaler settings +* \param demod instance of demodulator +* \param pointer to DRXCfgAudPrescale_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetCfgPrescale( pDRXDemodInstance_t demod, + pDRXCfgAudPrescale_t presc ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t wMaxFMDeviation = 0; + u16_t nicamPrescaler; + + if ( presc == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + /* setting of max FM deviation */ + wMaxFMDeviation = (u16_t)(Frac (3600UL, presc->fmDeviation, 0)); + wMaxFMDeviation <<= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B; + if ( wMaxFMDeviation >= AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION ) + { + wMaxFMDeviation = AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION; + } + + /* NICAM Prescaler */ + if( ( presc->nicamGain >= -241) && ( presc->nicamGain <= 180) ) + { + /* calculation + + prescaler = 16 * 10^( GdB / 20 ) + + minval of GdB = -20*log( 16 ) = -24.1dB + + negative numbers not allowed for dB2LinTimes100, so + + prescaler = 16 * 10^( GdB / 20 ) + = 10^( (GdB / 20) + log10(16) ) + = 10^( (GdB + 20log10(16)) / 20 ) + + in 0.1dB + + = 10^( G0.1dB + 200log10(16)) / 200 ) + + */ + nicamPrescaler = (u16_t) + ( ( dB2LinTimes100( presc->nicamGain + 241UL ) + 50UL ) / 100UL ); + + /* clip result */ + if ( nicamPrescaler > 127 ) + { + nicamPrescaler = 127; + } + + /* shift before writing to register */ + nicamPrescaler <<= 8; + } + else + { + return(DRX_STS_INVALID_ARG); + } + /* end of setting NICAM Prescaler */ + + WR16( devAddr, AUD_DSP_WR_NICAM_PRESC__A, nicamPrescaler ); + WR16( devAddr, AUD_DSP_WR_FM_PRESC__A, wMaxFMDeviation ); + + extAttr->audData.prescale = *presc; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Beep +* \param demod instance of demodulator +* \param pointer to DRXAudBeep_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlBeep ( pDRXDemodInstance_t demod, + pDRXAudBeep_t beep ) +{ + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + + u16_t theBeep = 0; + u16_t volume = 0; + u32_t frequency = 0; + + + if ( beep == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + if (( beep->volume > 0 ) || ( beep->volume < -127 )) + { + return DRX_STS_INVALID_ARG; + } + + if ( beep->frequency > 3000 ) + { + return DRX_STS_INVALID_ARG; + } + + volume = (u16_t)beep->volume + 127; + theBeep |= volume << AUD_DSP_WR_BEEPER_BEEP_VOLUME__B; + + + frequency = ( (u32_t) beep->frequency ) * 23 / 500 ; + if ( frequency > AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M ) + { + frequency = AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M; + } + theBeep |= (u16_t) frequency; + + if ( beep->mute == TRUE ) + { + theBeep = 0; + } + + WR16( devAddr, AUD_DSP_WR_BEEPER__A, theBeep); + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Set an audio standard +* \param demod instance of demodulator +* \param pointer to DRXAudStandard_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlSetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t currentStandard = DRX_STANDARD_UNKNOWN; + + u16_t wStandard = 0; + u16_t wModus = 0; + u16_t rModus = 0; + + Bool_t muteBuffer = FALSE; + s16_t volumeBuffer = 0; + u16_t wVolume = 0; + + if ( standard == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , FALSE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + + /* reset RDS data availability flag */ + extAttr->audData.rdsDataPresent = FALSE; + + + /* we need to mute from here to avoid noise during standard switching */ + muteBuffer = extAttr->audData.volume.mute; + volumeBuffer = extAttr->audData.volume.volume; + + extAttr->audData.volume.mute = TRUE; + /* restore data structure from DRX ExtAttr, call volume first to mute */ + CHK_ERROR ( AUDCtrlSetCfgVolume + ( demod, &extAttr->audData.volume ) ); + CHK_ERROR ( AUDCtrlSetCfgCarrier + ( demod, &extAttr->audData.carriers ) ); + CHK_ERROR ( AUDCtrlSetCfgASSThres + ( demod, &extAttr->audData.assThresholds ) ); + CHK_ERROR ( AUDCtrSetlCfgAutoSound + ( demod, &extAttr->audData.autoSound ) ); + CHK_ERROR ( AUDCtrlSetCfgMixer + ( demod, &extAttr->audData.mixer ) ); + CHK_ERROR ( AUDCtrlSetCfgAVSync + ( demod, &extAttr->audData.avSync ) ); + CHK_ERROR ( AUDCtrlSetCfgOutputI2S + ( demod, &extAttr->audData.i2sdata ) ); + + /* get prescaler from presets */ + CHK_ERROR ( AUDCtrlSetCfgPrescale + ( demod, &extAttr->audData.prescale) ); + + CHK_ERROR ( AUDGetModus ( demod, &rModus )); + + wModus = rModus; + + switch ( *standard ) + { + case DRX_AUD_STANDARD_AUTO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + case DRX_AUD_STANDARD_BTSC: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO; + if (extAttr->audData.btscDetect == DRX_BTSC_MONO_AND_SAP) + { + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP; + } + break; + case DRX_AUD_STANDARD_A2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA; + break; + case DRX_AUD_STANDARD_EIAJ: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J; + break; + case DRX_AUD_STANDARD_FM_STEREO: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO; + break; + case DRX_AUD_STANDARD_BG_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM; + break; + case DRX_AUD_STANDARD_D_K1: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1; + break; + case DRX_AUD_STANDARD_D_K2: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2; + break; + case DRX_AUD_STANDARD_D_K3: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3; + break; + case DRX_AUD_STANDARD_BG_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM; + break; + case DRX_AUD_STANDARD_L_NICAM_AM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM; + break; + case DRX_AUD_STANDARD_I_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM; + break; + case DRX_AUD_STANDARD_D_K_NICAM_FM: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM; + break; + case DRX_AUD_STANDARD_UNKNOWN: + wStandard = AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO; + break; + default: + return DRX_STS_ERROR; + } + + if ( *standard == DRX_AUD_STANDARD_AUTO ) + { + /* we need the current standard here */ + currentStandard = extAttr->standard; + + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M; + + if ( ( currentStandard == DRX_STANDARD_PAL_SECAM_L ) || + ( currentStandard == DRX_STANDARD_PAL_SECAM_LP ) ) + { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM); + } + else + { + wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K); + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M; + if ( currentStandard == DRX_STANDARD_NTSC ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC); + + } + else /* non USA, ignore standard M to save time */ + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA); + } + + + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_FMRADIO__M; + + /* just get hardcoded deemphasis and activate here */ + if ( extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U); + } + else + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U); + } + + wModus &= (u16_t)~AUD_DEM_WR_MODUS_MOD_BTSC__M; + if( extAttr->audData.btscDetect == DRX_BTSC_STEREO ) + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO); + } + else /* DRX_BTSC_MONO_AND_SAP */ + { + wModus |= ( AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP); + } + + if ( wModus != rModus) + { + WR16( devAddr, AUD_DEM_WR_MODUS__A, wModus ); + } + + WR16( devAddr, AUD_DEM_WR_STANDARD_SEL__A, wStandard ); + + /**************************************************************************/ + /* NOT calling AUDCtrlSetCfgVolume to avoid interfering standard */ + /* detection, need to keep things very minimal here, but keep audio */ + /* buffers intact */ + /**************************************************************************/ + extAttr->audData.volume.mute = muteBuffer; + if ( extAttr->audData.volume.mute == FALSE ) + { + wVolume |= (u16_t) ( ( volumeBuffer + AUD_VOLUME_ZERO_DB ) << + AUD_DSP_WR_VOLUME_VOL_MAIN__B ); + WR16( devAddr, AUD_DSP_WR_VOLUME__A, wVolume ); + } + + /* write standard selected */ + extAttr->audData.audioStandard = *standard; + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; +} + +/*============================================================================*/ +/** +* \brief Get the current audio standard +* \param demod instance of demodulator +* \param pointer to DRXAudStandard_t +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +AUDCtrlGetStandard ( pDRXDemodInstance_t demod, + pDRXAudStandard_t standard ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + u16_t rData = 0; + + if ( standard == NULL ) + { + return DRX_STS_INVALID_ARG; + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = (pI2CDeviceAddr_t)demod->myI2CDevAddr; + + /* power up */ + if ( extAttr->audData.audioIsActive == FALSE ) + { + CHK_ERROR ( PowerUpAud( demod , TRUE ) ); + extAttr->audData.audioIsActive = TRUE; + } + + *standard = DRX_AUD_STANDARD_UNKNOWN; + + RR16( devAddr, AUD_DEM_RD_STANDARD_RES__A, &rData ); + + /* return OK if the detection is not ready yet */ + if ( rData >= + AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE ) + { + *standard = DRX_AUD_STANDARD_NOT_READY; + return DRX_STS_OK; + } + + /* detection done, return correct standard */ + switch ( rData ) + { + /* no standard detected */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD: + *standard = DRX_AUD_STANDARD_UNKNOWN; + break; + /* standard is KOREA(A2) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_A2; + break; + /* standard is EIA-J (Japan) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J: + *standard = DRX_AUD_STANDARD_EIAJ; + break; + /* standard is BTSC-stereo */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is BTSC-mono (SAP) */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP: + *standard = DRX_AUD_STANDARD_BTSC; + break; + /* standard is FM radio */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO: + *standard = DRX_AUD_STANDARD_FM_STEREO; + break; + /* standard is BG FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_BG_FM; + break; + /* standard is DK-1 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K1; + break; + /* standard is DK-2 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K2; + break; + /* standard is DK-3 FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM: + *standard = DRX_AUD_STANDARD_D_K3; + break; + /* standard is BG-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM: + *standard = DRX_AUD_STANDARD_BG_NICAM_FM; + break; + /* standard is L-NICAM AM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM: + *standard = DRX_AUD_STANDARD_L_NICAM_AM; + break; + /* standard is I-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM: + *standard = DRX_AUD_STANDARD_I_NICAM_FM; + break; + /* standard is DK-NICAM FM */ + case AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM: + *standard = DRX_AUD_STANDARD_D_K_NICAM_FM; + break; + default: + *standard = DRX_AUD_STANDARD_UNKNOWN; + } + + return DRX_STS_OK; +rw_error: + return DRX_STS_ERROR; + +} + + +/*============================================================================*/ +/** +* \brief Retreive lock status in case of FM standard +* \param demod instance of demodulator +* \param pointer to lock status +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +FmLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ) +{ + DRXAudStatus_t status; + + /* Check detection of audio carriers */ + CHK_ERROR( AUDCtrlGetCarrierDetectStatus ( demod, &status ) ); + + /* locked if either primary or secondary carrier is detected */ + if ( ( status.carrierA == TRUE ) || + ( status.carrierB == TRUE ) ) + { + *lockStat = DRX_LOCKED; + } else { + *lockStat = DRX_NOT_LOCKED; + } + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \brief retreive signal quality in case of FM standard +* \param demod instance of demodulator +* \param pointer to signal quality +* \return DRXStatus_t. +* +* Only the quality indicator field is will be supplied. +* This will either be 0% or 100%, nothing in between. +* +*/ +static DRXStatus_t +FmSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + + CHK_ERROR( FmLockStatus( demod, &lockStatus ) ); + if ( lockStatus == DRX_LOCKED ) + { + sigQuality->indicator = 100; + } else { + sigQuality->indicator = 0; + } + + return (DRX_STS_OK); + +rw_error: + return (DRX_STS_ERROR); +} + +#endif + + +/*===========================================================================*/ +/*== END AUDIO DATAPATH FUNCTIONS ==*/ +/*===========================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +#ifndef DRXJ_DIGITAL_ONLY +/** +* \fn DRXStatus_t GetOOBLockStatus () +* \brief Get OOB lock status. +* \param devAddr I2C address + \ oobLock OOB lock status. +* \return DRXStatus_t. +* +* Gets OOB lock status +* +*/ +static DRXStatus_t +GetOOBLockStatus( pDRXDemodInstance_t demod, + pI2CDeviceAddr_t devAddr, + pDRXLockStatus_t oobLock ) +{ + DRXJSCUCmd_t scuCmd; + u16_t cmdResult[2]; + u16_t OOBLockState; + + *oobLock = DRX_NOT_LOCKED; + + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + scuCmd.resultLen = 2; + scuCmd.result = cmdResult; + scuCmd.parameterLen = 0; + + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + if ( scuCmd.result[1] < 0x4000 ) + { + /* 0x00 NOT LOCKED */ + *oobLock = DRX_NOT_LOCKED; + } + else if ( scuCmd.result[1] < 0x8000 ) + { + /* 0x40 DEMOD LOCKED */ + *oobLock = DRXJ_OOB_SYNC_LOCK; + } + else if ( scuCmd.result[1] < 0xC000 ) + { + /* 0x80 DEMOD + OOB LOCKED (system lock) */ + OOBLockState = scuCmd.result[1] & 0x00FF; + + if(OOBLockState & 0x0008) + { + *oobLock = DRXJ_OOB_SYNC_LOCK; + } + else if ((OOBLockState & 0x0002) && (OOBLockState & 0x0001)) + { + *oobLock = DRXJ_OOB_AGC_LOCK; + } + } + else + { + /* 0xC0 NEVER LOCKED (system will never be able to lock to the signal) */ + *oobLock = DRX_NEVER_LOCK; + } + + /* *oobLock = scuCmd.result[1]; */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetOOBSymbolRateOffset () +* \brief Get OOB Symbol rate offset. Unit is [ppm] +* \param devAddr I2C address +* \ Symbol Rate Offset OOB parameter. +* \return DRXStatus_t. +* +* Gets OOB frequency offset +* +*/ +static DRXStatus_t +GetOOBSymbolRateOffset( pI2CDeviceAddr_t devAddr, ps32_t SymbolRateOffset ) +{ +/* offset = -{(timingOffset/2^19)*(symbolRate/12,656250MHz)}*10^6 [ppm] */ +/* offset = -{(timingOffset/2^19)*(symbolRate/12656250)}*10^6 [ppm] */ +/* after reconfiguration: */ +/* offset = -{(timingOffset*symbolRate)/(2^19*12656250)}*10^6 [ppm] */ +/* shift symbol rate left by 5 without lossing information */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^14*12656250)}*10^6 [ppm]*/ +/* shift 10^6 left by 6 without loosing information */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*12656250)}*15625 [ppm]*/ +/* trim 12656250/15625 = 810 */ +/* offset = -{(timingOffset*(symbolRate * 2^-5))/(2^8*810)} [ppm] */ +/* offset = -[(symbolRate * 2^-5)*(timingOffset)/(2^8)]/810 [ppm] */ + s32_t timingOffset = 0; + u32_t unsignedTimingOffset = 0; + s32_t divisionFactor = 810; + u16_t data = 0; + u32_t symbolRate = 0; + Bool_t negative = FALSE; + + *SymbolRateOffset = 0; + /* read data rate */ + SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &data ); + switch(data & SCU_RAM_ORX_RF_RX_DATA_RATE__M) + { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000;/* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000;/* bps */ + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000;/* bps */ + break; + default: + return (DRX_STS_ERROR); + } + + RR16( devAddr, ORX_CON_CTI_DTI_R__A, &data ); + /* convert data to positive and keep information about sign */ + if((data & 0x8000) == 0x8000){ + if(data == 0x8000) + unsignedTimingOffset = 32768; + else + unsignedTimingOffset = 0x00007FFF & (u32_t)(-data); + negative = TRUE; + } + else + unsignedTimingOffset = (u32_t)data; + + symbolRate = symbolRate >> 5; + unsignedTimingOffset = ( unsignedTimingOffset * symbolRate ); + unsignedTimingOffset = Frac( unsignedTimingOffset, 256, FRAC_ROUND ); + unsignedTimingOffset = Frac( unsignedTimingOffset, + divisionFactor, FRAC_ROUND ); + if(negative) + timingOffset = (s32_t)unsignedTimingOffset; + else + timingOffset = -(s32_t)unsignedTimingOffset; + + *SymbolRateOffset = timingOffset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t GetOOBFreqOffset () +* \brief Get OOB lock status. +* \param devAddr I2C address +* \ freqOffset OOB frequency offset. +* \return DRXStatus_t. +* +* Gets OOB frequency offset +* +*/ +static DRXStatus_t +GetOOBFreqOffset( pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset ) +{ + u16_t data = 0; + u16_t rot = 0; + u16_t symbolRateReg = 0; + u32_t symbolRate = 0; + s32_t coarseFreqOffset = 0; + s32_t fineFreqOffset = 0; + s32_t fineSign = 1; + s32_t coarseSign = 1; + u32_t data64Hi = 0; + u32_t data64Lo = 0; + u32_t tempFreqOffset = 0; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + pI2CDeviceAddr_t devAddr = NULL; + + /* check arguments */ + if ( ( demod == NULL ) || + ( freqOffset == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + *freqOffset = 0; + + /* read sign (spectrum inversion) */ + RR16( devAddr, ORX_FWP_IQM_FRQ_W__A, &rot ); + + /* read frequency offset */ + SARR16( devAddr, SCU_RAM_ORX_FRQ_OFFSET__A, &data ); + /* find COARSE frequency offset */ + /* coarseFreqOffset = ( 25312500Hz*FRQ_OFFSET >> 21 ); */ + if (data & 0x8000) + { + data = (0xffff - data + 1); + coarseSign = -1; + } + Mult32 ( data, (commonAttr->sysClockFreq * 1000)/6, &data64Hi, &data64Lo ); + tempFreqOffset = (((data64Lo >> 21) & 0x7ff) | (data64Hi << 11)); + + /* get value in KHz */ + coarseFreqOffset = coarseSign * Frac( tempFreqOffset, 1000, FRAC_ROUND ); /* KHz */ + /* read data rate */ + SARR16( devAddr, SCU_RAM_ORX_RF_RX_DATA_RATE__A, &symbolRateReg ); + switch(symbolRateReg & SCU_RAM_ORX_RF_RX_DATA_RATE__M) + { + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT: + case SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT: + symbolRate = 1024000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC: + symbolRate = 772000; + break; + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC: + case SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC: + symbolRate = 1544000; + break; + default: + return (DRX_STS_ERROR); + } + + /* find FINE frequency offset */ + /* fineFreqOffset = ( (CORRECTION_VALUE*symbolRate) >> 18 ); */ + RR16( devAddr, ORX_CON_CPH_FRQ_R__A, &data ); + /* at least 5 MSB are 0 so first divide with 2^5 without information loss*/ + fineFreqOffset = ( symbolRate >> 5 ); + if (data & 0x8000) + { + fineFreqOffset *= 0xffff - data + 1; /* Hz */ + fineSign = -1; + } else { + fineFreqOffset *= data; /* Hz */ + } + /* Left to divide with 8192 (2^13) */ + fineFreqOffset = Frac( fineFreqOffset, 8192, FRAC_ROUND ); + /* and to divide with 1000 to get KHz*/ + fineFreqOffset = fineSign * Frac( fineFreqOffset, 1000, FRAC_ROUND ); /* KHz */ + + if ( (rot & 0x8000) == 0x8000 ) + *freqOffset = -(coarseFreqOffset + fineFreqOffset); + else + *freqOffset = (coarseFreqOffset + fineFreqOffset); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t GetOOBFrequency () +* \brief Get OOB frequency (Unit:KHz). +* \param devAddr I2C address +* \ frequency OOB frequency parameters. +* \return DRXStatus_t. +* +* Gets OOB frequency +* +*/ +static DRXStatus_t +GetOOBFrequency( pDRXDemodInstance_t demod, pDRXFrequency_t frequency ) +{ + u16_t data = 0; + DRXFrequency_t freqOffset = 0; + DRXFrequency_t freq = 0; + pI2CDeviceAddr_t devAddr = NULL; + + devAddr = demod -> myI2CDevAddr; + + *frequency = 0;/* KHz */ + + SARR16( devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data ); + + freq = (DRXFrequency_t)((DRXFrequency_t)data * 50 + 50000L); + + CHK_ERROR ( GetOOBFreqOffset ( demod, &freqOffset ) ); + + *frequency = freq + freqOffset; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t GetOOBMER () +* \brief Get OOB MER. +* \param devAddr I2C address + \ MER OOB parameter in dB. +* \return DRXStatus_t. +* +* Gets OOB MER. Table for MER is in Programming guide. +* +*/ +static DRXStatus_t +GetOOBMER( pI2CDeviceAddr_t devAddr, pu32_t mer ) +{ + u16_t data = 0; + + *mer = 0; + /* READ MER */ + RR16( devAddr, ORX_EQU_MER_MER_R__A, &data ); + switch (data) + { + case 0:/* fall through */ + case 1: + *mer = 39; + break; + case 2: + *mer = 33; + break; + case 3: + *mer = 29; + break; + case 4: + *mer = 27; + break; + case 5: + *mer = 25; + break; + case 6: + *mer = 23; + break; + case 7: + *mer = 22; + break; + case 8: + *mer = 21; + break; + case 9: + *mer = 20; + break; + case 10: + *mer = 19; + break; + case 11: + *mer = 18; + break; + case 12: + *mer = 17; + break; + case 13:/* fall through */ + case 14: + *mer = 16; + break; + case 15:/* fall through */ + case 16: + *mer = 15; + break; + case 17:/* fall through */ + case 18: + *mer = 14; + break; + case 19:/* fall through */ + case 20: + *mer = 13; + break; + case 21:/* fall through */ + case 22: + *mer = 12; + break; + case 23:/* fall through */ + case 24:/* fall through */ + case 25: + *mer = 11; + break; + case 26:/* fall through */ + case 27:/* fall through */ + case 28: + *mer = 10; + break; + case 29:/* fall through */ + case 30:/* fall through */ + case 31:/* fall through */ + case 32: + *mer = 9; + break; + case 33:/* fall through */ + case 34:/* fall through */ + case 35:/* fall through */ + case 36: + *mer = 8; + break; + case 37:/* fall through */ + case 38:/* fall through */ + case 39:/* fall through */ + case 40: + *mer = 7; + break; + case 41:/* fall through */ + case 42:/* fall through */ + case 43:/* fall through */ + case 44:/* fall through */ + case 45: + *mer = 6; + break; + case 46:/* fall through */ + case 47:/* fall through */ + case 48:/* fall through */ + case 49:/* fall through */ + case 50:/* fall through */ + *mer = 5; + break; + case 51:/* fall through */ + case 52:/* fall through */ + case 53:/* fall through */ + case 54:/* fall through */ + case 55:/* fall through */ + case 56:/* fall through */ + case 57: + *mer = 4; + break; + case 58:/* fall through */ + case 59:/* fall through */ + case 60:/* fall through */ + case 61:/* fall through */ + case 62:/* fall through */ + case 63: + *mer = 0; + break; + default: + *mer = 0; + break; + } + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif /*#ifndef DRXJ_DIGITAL_ONLY */ + +/** +* \fn DRXStatus_t SetOrxNsuAox() +* \brief Configure OrxNsuAox for OOB +* \param demod instance of demodulator. +* \param active +* \return DRXStatus_t. +*/ +static DRXStatus_t +SetOrxNsuAox ( pDRXDemodInstance_t demod, Bool_t active ) +{ + u16_t data = 0; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Configure NSU_AOX */ + RR16( devAddr, ORX_NSU_AOX_STDBY_W__A , &data ); + if( !active ) + { + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) + & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON) + ); + } + else /* active */ + { + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON + | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON + ); + } + WR16( devAddr, ORX_NSU_AOX_STDBY_W__A , data ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetOOB() +* \brief Set OOB channel to be used. +* \param demod instance of demodulator +* \param oobParam OOB parameters for channel setting. +* \frequency should be in KHz +* \return DRXStatus_t. +* +* Accepts only. Returns error otherwise. +* Demapper value is written after SCUCommand START +* because START command causes COMM_EXEC transition +* from 0 to 1 which causes all registers to be +* overwritten with initial value +* +*/ + +/* Nyquist filter impulse response */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ + +/* Coefficients for the nyquist fitler (total: 27 taps) */ +#define NYQFILTERLEN 27 + +static DRXStatus_t +CtrlSetOOB( pDRXDemodInstance_t demod, pDRXOOB_t oobParam ) +{ +#ifndef DRXJ_DIGITAL_ONLY + DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A; + DRXFrequency_t freq = 0; /* KHz */ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t i = 0; + Bool_t mirrorFreqSpectOOB = FALSE; + u16_t trkFilterValue = 0; + DRXJSCUCmd_t scuCmd; + u16_t setParamParameters[3]; + u16_t cmdResult[2] = {0, 0}; + s16_t NyquistCoeffs[4][(NYQFILTERLEN+1)/2] = + { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8_t mode_val[4] = {2, 2, 0, 1}; + u8_t PFICoeffs[4][6] = + { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100) }, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80) }, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) }, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92) } /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16_t mode_index; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + mirrorFreqSpectOOB = extAttr->mirrorFreqSpectOOB; + + /* Check parameters */ + if (oobParam == NULL) + { + /* power off oob module */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + + extAttr->oobPowerOn = FALSE; + return (DRX_STS_OK); + } + + standard = oobParam->standard; + + freq = oobParam->frequency; + if ((freq < 70000) || (freq > 130000)) + return (DRX_STS_ERROR); + freq = (freq - 50000) / 50; + + { + u16_t index = 0; + u16_t remainder = 0; + pu16_t trkFiltercfg = extAttr->oobTrkFilterCfg; + + index = (u16_t)((freq - 400) / 200); + remainder = (u16_t)((freq - 400) % 200); + trkFilterValue = trkFiltercfg[index] - (trkFiltercfg[index] - trkFiltercfg[index + 1])/10 + * remainder / 20; + } + + + /*********/ + /* Stop */ + /*********/ + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP); + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + /*********/ + /* Reset */ + /*********/ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + /***********/ + /* SET_ENV */ + /***********/ + /* set frequency, spectrum inversion and data rate */ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scuCmd.parameterLen = 3; + /* 1-data rate;2-frequency */ + switch ( oobParam->standard ) + { + case DRX_OOB_MODE_A: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if( + /* signal is transmitted inverted */ + ( (oobParam->spectrumInverted == TRUE) & + /* and tuner is not mirroring the signal */ + (mirrorFreqSpectOOB == FALSE) ) | + /* or */ + /* signal is transmitted noninverted */ + ( (oobParam->spectrumInverted == FALSE) & + /* and tuner is mirroring the signal */ + (mirrorFreqSpectOOB == TRUE) ) + ) + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + setParamParameters[0] = SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + setParamParameters[1] = ( u16_t )( freq & 0xFFFF ); + setParamParameters[2] = trkFilterValue; + scuCmd.parameter = setParamParameters; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + mode_index = mode_val[(setParamParameters[0] & 0xC0) >> 6]; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0xFABA); /* Write magic word to enable pdr reg write */ + WR16 ( devAddr, SIO_PDR_OOB_CRX_CFG__A, + OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B ); + WR16 ( devAddr, SIO_PDR_OOB_DRX_CFG__A, + OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B + | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B ); + WR16 ( devAddr, SIO_TOP_COMM_KEY__A, 0x0000); /* Write magic word to disable pdr reg write */ + + WR16 ( devAddr, ORX_TOP_COMM_KEY__A, 0); + WR16 ( devAddr, ORX_FWP_AAG_LEN_W__A, 16000); + WR16 ( devAddr, ORX_FWP_AAG_THR_W__A, 40); + + /* ddc */ + WR16( devAddr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE); + + /* nsu */ + WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, extAttr->oobLoPow); + + /* initialization for target mode */ + WR16( devAddr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT); + WR16( devAddr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS); + + /* Reset bits for timing and freq. recovery */ + WR16( devAddr, SCU_RAM_ORX_RST_CPH__A, 0x0001); + WR16( devAddr, SCU_RAM_ORX_RST_CTI__A, 0x0002); + WR16( devAddr, SCU_RAM_ORX_RST_KRN__A, 0x0004); + WR16( devAddr, SCU_RAM_ORX_RST_KRP__A, 0x0008); + + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048>>3); + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16_t) (-2048)); + WR16( devAddr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1); + + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10); + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1<<1); + + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17); + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1<<2); + + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000); + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1<<3); + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400); + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8); + WR16( devAddr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16_t)(-8)); + WR16( devAddr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1<<4); + + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20); + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16_t)(-2048)); + WR16( devAddr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4); + WR16( devAddr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16_t)(-4)); + WR16( devAddr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1<<5); + + /* PRE-Filter coefficients (PFI) */ + WRB( devAddr, ORX_FWP_PFI_A_W__A, sizeof(PFICoeffs[mode_index]), ((pu8_t)PFICoeffs[mode_index])); + WR16( devAddr, ORX_TOP_MDE_W__A, mode_index); + + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) + { + WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, i); + WR16( devAddr, ORX_FWP_NYQ_COF_RW__A, NyquistCoeffs[mode_index][i]); + } + WR16( devAddr, ORX_FWP_NYQ_ADR_W__A, 31); + WR16 ( devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE); + /*********/ + /* Start */ + /*********/ + scuCmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scuCmd.parameterLen = 0; + scuCmd.resultLen = 1; + scuCmd.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &scuCmd ) ); + + CHK_ERROR( SetOrxNsuAox( demod, TRUE ) ); + WR16( devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw ); + + extAttr->oobPowerOn = TRUE; + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} +/** +* \fn DRXStatus_t CtrlGetOOB() +* \brief Set modulation standard to be used. +* \param demod instance of demodulator +* \param oobStatus OOB status parameters. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetOOB( pDRXDemodInstance_t demod, pDRXOOBStatus_t oobStatus ) +{ +#ifndef DRXJ_DIGITAL_ONLY + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u16_t data = 0; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod->myExtAttr; + + /* check arguments */ + if ( oobStatus == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + if ( extAttr->oobPowerOn == FALSE) + return (DRX_STS_ERROR); + + RR16 ( devAddr, ORX_DDC_OFO_SET_W__A, &data); + RR16 ( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &data); + RR16 ( devAddr, ORX_FWP_AAG_THR_W__A, &data); + SARR16 ( devAddr, SCU_RAM_ORX_DGN_KI__A, &data); + RR16 ( devAddr, ORX_FWP_SRC_DGN_W__A, &data); + + CHK_ERROR ( GetOOBLockStatus ( demod, devAddr, &oobStatus->lock )); + CHK_ERROR ( GetOOBFrequency ( demod, &oobStatus->frequency )); + CHK_ERROR ( GetOOBMER ( devAddr, &oobStatus->mer )); + CHK_ERROR ( GetOOBSymbolRateOffset ( devAddr, &oobStatus->symbolRateOffset )); + + return (DRX_STS_OK); +rw_error: +#endif + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfgOOBPreSAW() +* \brief Configure PreSAW treshold value +* \param cfgData Pointer to configuration parameter +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlSetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, ORX_NSU_AOX_STHR_W__A, *cfgData ); + extAttr->oobPreSaw = *cfgData; + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgOOBPreSAW() +* \brief Configure PreSAW treshold value +* \param cfgData Pointer to configuration parameter +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBPreSAW( pDRXDemodInstance_t demod, pu16_t cfgData ) +{ + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t)demod->myExtAttr; + + *cfgData = extAttr->oobPreSaw; + + return (DRX_STS_OK); +} +#endif + +/** +* \fn DRXStatus_t CtrlSetCfgOOBLoPower() +* \brief Configure LO Power value +* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlSetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod->myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + WR16( devAddr, ORX_NSU_AOX_LOPOW_W__A, *cfgData ); + extAttr->oobLoPow = *cfgData; + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgOOBLoPower() +* \brief Configure LO Power value +* \param cfgData Pointer to pDRXJCfgOobLoPower_t +* \return Error code +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBLoPower( pDRXDemodInstance_t demod, pDRXJCfgOobLoPower_t cfgData ) +{ + pDRXJData_t extAttr = NULL; + + if(cfgData == NULL) + { + return (DRX_STS_INVALID_ARG); + } + extAttr = (pDRXJData_t)demod->myExtAttr; + + *cfgData = extAttr->oobLoPow; + + return (DRX_STS_OK); +} +#endif +/*============================================================================*/ +/*== END OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================= + ===== MC command related functions ========================================== + ===========================================================================*/ + +/*============================================================================= + ===== CtrlSetChannel() ========================================================== + ===========================================================================*/ +/** +* \fn DRXStatus_t CtrlSetChannel() +* \brief Select a new transmission channel. +* \param demod instance of demod. +* \param channel Pointer to channel data. +* \return DRXStatus_t. +* +* In case the tuner module is not used and in case of NTSC/FM the pogrammer +* must tune the tuner to the centre frequency of the NTSC/FM channel. +* +*/ +static DRXStatus_t +CtrlSetChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + + DRXFrequency_t tunerSetFreq = 0; + DRXFrequency_t tunerGetFreq = 0; + DRXFrequency_t tunerFreqOffset = 0; + DRXFrequency_t intermediateFreq = 0; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + TUNERMode_t tunerMode = 0; + pDRXCommonAttr_t commonAttr = NULL; + Bool_t bridgeClosed = FALSE; +#ifndef DRXJ_VSB_ONLY + u32_t minSymbolRate = 0; + u32_t maxSymbolRate = 0; + int bandwidthTemp = 0; + int bandwidth = 0; +#endif + /*== check arguments ======================================================*/ + if ( ( demod == NULL ) || + ( channel == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + standard = extAttr->standard; + + /* check valid standards */ + switch ( standard ) + { + case DRX_STANDARD_8VSB: +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif /* DRXJ_VSB_ONLY */ +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: +#endif /* DRXJ_DIGITAL_ONLY */ + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ( ( standard == DRX_STANDARD_ITU_B ) || + ( standard == DRX_STANDARD_8VSB ) || + ( standard == DRX_STANDARD_NTSC ) ) + { + switch ( channel->bandwidth ) { + case DRX_BANDWIDTH_6MHZ : + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ : /* fall through */ + case DRX_BANDWIDTH_7MHZ : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } + +#ifndef DRXJ_DIGITAL_ONLY + if ( standard == DRX_STANDARD_PAL_SECAM_BG ) + { + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_7MHZ : /* fall through */ + case DRX_BANDWIDTH_8MHZ : + /* ok */ + break; + case DRX_BANDWIDTH_6MHZ : /* fall through */ + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } + /* check bandwidth PAL/SECAM */ + if ( ( standard == DRX_STANDARD_PAL_SECAM_BG ) || + ( standard == DRX_STANDARD_PAL_SECAM_DK ) || + ( standard == DRX_STANDARD_PAL_SECAM_I ) || + ( standard == DRX_STANDARD_PAL_SECAM_L ) || + ( standard == DRX_STANDARD_PAL_SECAM_LP ) ) + { + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_8MHZ : + case DRX_BANDWIDTH_UNKNOWN : /* fall through */ + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + break; + case DRX_BANDWIDTH_6MHZ : /* fall through */ + case DRX_BANDWIDTH_7MHZ : /* fall through */ + default : + return (DRX_STS_INVALID_ARG); + } + } +#endif + + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ +#ifndef DRXJ_VSB_ONLY + if( ( standard == DRX_STANDARD_ITU_A ) || + ( standard == DRX_STANDARD_ITU_C ) ) + { + DRXUIOCfg_t UIOCfg = {DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW}; + int bwRolloffFactor = 0; + + bwRolloffFactor = (standard == DRX_STANDARD_ITU_A)?115:113; + minSymbolRate = DRXJ_QAM_SYMBOLRATE_MIN; + maxSymbolRate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode*/ + CHK_ERROR( CtrlSetUIOCfg( demod, &UIOCfg ) ); + + if ( channel->symbolrate < minSymbolRate || + channel->symbolrate > maxSymbolRate ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( channel->constellation ) { + case DRX_CONSTELLATION_QAM16 : /* fall through */ + case DRX_CONSTELLATION_QAM32 : /* fall through */ + case DRX_CONSTELLATION_QAM64 : /* fall through */ + case DRX_CONSTELLATION_QAM128 : /* fall through */ + case DRX_CONSTELLATION_QAM256 : + bandwidthTemp = channel->symbolrate * bwRolloffFactor; + bandwidth = bandwidthTemp / 100; + + if( ( bandwidthTemp % 100 ) >= 50 ) + { + bandwidth++; + } + + if( bandwidth <= 6100000 ) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else if( ( bandwidth > 6100000 ) && ( bandwidth <= 7100000 ) ) + { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } + else if( bandwidth > 7100000 ) + { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + /* For QAM annex B: + -check constellation + */ + if ( standard == DRX_STANDARD_ITU_B ) + { + switch ( channel->constellation ) { + case DRX_CONSTELLATION_AUTO : + case DRX_CONSTELLATION_QAM256 : + case DRX_CONSTELLATION_QAM64 : + break; + default : + return (DRX_STS_INVALID_ARG); + } + + switch (channel->interleavemode) + { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: + break; + default: + return (DRX_STS_INVALID_ARG); + } + } + + if ( (extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW ) + { + /* SAW SW, user UIO is used for switchable SAW */ + DRXUIOData_t uio1 = { DRX_UIO1, FALSE }; + + switch ( channel->bandwidth ) + { + case DRX_BANDWIDTH_8MHZ: + uio1.value = TRUE; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = FALSE; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + CHK_ERROR( CtrlUIOWrite( demod, &uio1 ) ); + } +#endif /* DRXJ_VSB_ONLY */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + /*== Tune, fast mode ======================================================*/ + if ( demod->myTuner != NULL ) + { + /* Determine tuner mode and freq to tune to ... */ + switch ( standard ) { +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + /* expecting center frequency, not picture carrier so no + conversion .... */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_FM: + /* center frequency (equals sound carrier) as input, + tune to edge of SAW */ + tunerMode |= TUNER_MODE_ANALOG; + tunerSetFreq = channel->frequency + DRXJ_FM_CARRIER_FREQ_OFFSET; + break; +#endif + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + tunerMode |= TUNER_MODE_DIGITAL; + tunerSetFreq = channel->frequency; + break; + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } /* switch(standard) */ + + tunerMode |= TUNER_MODE_SWITCH; + switch ( channel->bandwidth ) { + case DRX_BANDWIDTH_8MHZ : + tunerMode |= TUNER_MODE_8MHZ; + break; + case DRX_BANDWIDTH_7MHZ : + tunerMode |= TUNER_MODE_7MHZ; + break; + case DRX_BANDWIDTH_6MHZ : + tunerMode |= TUNER_MODE_6MHZ; + break; + default: + /* TODO: for FM which bandwidth to use ? + also check offset from centre frequency ? + For now using 6MHz. + */ + tunerMode |= TUNER_MODE_6MHZ; + break; + /* return (DRX_STS_INVALID_ARG); */ + } + + /* store bandwidth for GetChannel() */ + extAttr->currBandwidth = channel->bandwidth; + extAttr->currSymbolRate = channel->symbolrate; + extAttr->frequency = tunerSetFreq; + if ( commonAttr->tunerPortNr == 1 ) + { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + /* set tuner frequency */ + } + + CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + tunerSetFreq ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + /* Get actual frequency set by tuner and compute offset */ + CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, + 0, + &tunerGetFreq, + &intermediateFreq ) ); + tunerFreqOffset = tunerGetFreq - tunerSetFreq; + commonAttr->intermediateFreq = intermediateFreq; + } + else + { + /* no tuner instance defined, use fixed intermediate frequency */ + tunerFreqOffset = 0; + intermediateFreq = demod->myCommonAttr->intermediateFreq; + } /* if ( demod->myTuner != NULL ) */ + + /*== Setup demod for specific standard ====================================*/ + switch ( standard ) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetVSB(demod) ); + CHK_ERROR ( SetFrequency ( demod, channel, tunerFreqOffset ) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + if (channel->mirror == DRX_MIRROR_AUTO) + { + extAttr->mirror = DRX_MIRROR_NO; + } + else + { + extAttr->mirror = channel->mirror; + } + CHK_ERROR ( SetATVChannel( demod, + tunerFreqOffset, + channel, + standard ) ); + break; +#endif +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR ( SetQAMChannel( demod, channel, tunerFreqOffset ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } + + /*== Re-tune, slow mode ===================================================*/ + if ( demod->myTuner != NULL ) + { + /* tune to slow mode */ + tunerMode &= ~TUNER_MODE_SWITCH; + tunerMode |= TUNER_MODE_LOCK; + + if ( commonAttr->tunerPortNr == 1 ) + { + /* close tuner bridge */ + bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + /* set tuner frequency*/ + CHK_ERROR( DRXBSP_TUNER_SetFrequency( demod->myTuner, + tunerMode, + tunerSetFreq ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + /* open tuner bridge */ + bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + } /* if ( demod->myTuner !=NULL ) */ + + /* flag the packet error counter reset */ + extAttr->resetPktErrAcc = TRUE; + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= + ===== CtrlGetChannel() ========================================================== + ===========================================================================*/ +/** +* \fn DRXStatus_t CtrlGetChannel() +* \brief Retreive parameters of current transmission channel. +* \param demod Pointer to demod instance. +* \param channel Pointer to channel data. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlGetChannel( pDRXDemodInstance_t demod, + pDRXChannel_t channel ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXCommonAttr_t commonAttr = NULL; + DRXFrequency_t intermediateFreq = 0; + s32_t CTLFreqOffset = 0; + u32_t iqmRcRateLo = 0; + u32_t adcFrequency = 0; +#ifndef DRXJ_VSB_ONLY + int bandwidthTemp = 0; + int bandwidth = 0; +#endif + + /* check arguments */ + if ( ( demod == NULL ) || + ( channel == NULL ) ) + { + return DRX_STS_INVALID_ARG; + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + standard = extAttr->standard; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + /* initialize channel fields */ + channel->mirror = DRX_MIRROR_UNKNOWN; + channel->hierarchy = DRX_HIERARCHY_UNKNOWN; + channel->priority = DRX_PRIORITY_UNKNOWN; + channel->coderate = DRX_CODERATE_UNKNOWN; + channel->guard = DRX_GUARD_UNKNOWN; + channel->fftmode = DRX_FFTMODE_UNKNOWN; + channel->classification = DRX_CLASSIFICATION_UNKNOWN; + channel->bandwidth = DRX_BANDWIDTH_UNKNOWN; + channel->constellation = DRX_CONSTELLATION_UNKNOWN; + channel->symbolrate = 0; + channel->interleavemode = DRX_INTERLEAVEMODE_UNKNOWN; + channel->carrier = DRX_CARRIER_UNKNOWN; + channel->framemode = DRX_FRAMEMODE_UNKNOWN; +/* channel->interleaver = DRX_INTERLEAVER_UNKNOWN;*/ + channel->ldpc = DRX_LDPC_UNKNOWN; + + if ( demod->myTuner != NULL ) + { + DRXFrequency_t tunerFreqOffset = 0; + Bool_t tunerMirror = commonAttr->mirrorFreqSpect?FALSE:TRUE; + + /* Get frequency from tuner */ + CHK_ERROR( DRXBSP_TUNER_GetFrequency( demod->myTuner, + 0, + &(channel->frequency), + &intermediateFreq ) ); + tunerFreqOffset = channel->frequency - extAttr->frequency; + if ( tunerMirror == TRUE ) + { + /* positive image */ + channel->frequency += tunerFreqOffset; + } else { + /* negative image */ + channel->frequency -= tunerFreqOffset; + } + + /* Handle sound carrier offset in RF domain */ + if ( standard == DRX_STANDARD_FM ) + { + channel->frequency -= DRXJ_FM_CARRIER_FREQ_OFFSET; + } + } + else + { + intermediateFreq = commonAttr->intermediateFreq; + } + + /* check lock status */ + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( (lockStatus == DRX_LOCKED) || (lockStatus == DRXJ_DEMOD_LOCK) ) + { + ARR32( devAddr, IQM_RC_RATE_LO__A, &iqmRcRateLo ); + adcFrequency = ( commonAttr->sysClockFreq * 1000 ) / 3; + + channel->symbolrate = Frac28(adcFrequency, (iqmRcRateLo + (1<<23))) >> 7; + + switch ( standard ) + { + case DRX_STANDARD_8VSB: + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + /* get the channel frequency */ + CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); + channel->frequency -= CTLFreqOffset; + /* get the channel constellation */ + channel->constellation = DRX_CONSTELLATION_AUTO; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + { + /* get the channel frequency */ + CHK_ERROR( GetCTLFreqOffset ( demod, &CTLFreqOffset ) ); + channel->frequency -= CTLFreqOffset; + + if (standard == DRX_STANDARD_ITU_B) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else + { + /* annex A & C */ + + u32_t rollOff=113; /* default annex C */ + + if ( standard==DRX_STANDARD_ITU_A) + { + rollOff=115; + } + + bandwidthTemp = channel->symbolrate * rollOff; + bandwidth = bandwidthTemp / 100; + + if( ( bandwidthTemp % 100 ) >= 50 ) + { + bandwidth++; + } + + if( bandwidth <= 6000000 ) + { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } + else if( ( bandwidth > 6000000 ) && ( bandwidth <= 7000000 ) ) + { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } + else if( bandwidth > 7000000 ) + { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + } /* if (standard == DRX_STANDARD_ITU_B) */ + + { + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* parameter */ NULL, + /* result */ NULL }; + u16_t cmdResult[3] = { 0, 0, 0 }; + + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM; + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 3; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + channel->interleavemode = (DRXInterleaveModes_t)(cmdSCU.result[2]); + } + + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + channel->constellation = DRX_CONSTELLATION_QAM256; + break; + case DRX_CONSTELLATION_QAM128: + channel->constellation = DRX_CONSTELLATION_QAM128; + break; + case DRX_CONSTELLATION_QAM64: + channel->constellation = DRX_CONSTELLATION_QAM64; + break; + case DRX_CONSTELLATION_QAM32: + channel->constellation = DRX_CONSTELLATION_QAM32; + break; + case DRX_CONSTELLATION_QAM16: + channel->constellation = DRX_CONSTELLATION_QAM16; + break; + default: + channel->constellation = DRX_CONSTELLATION_UNKNOWN; + return (DRX_STS_ERROR); + } + } + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fall trough */ + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_FM: + CHK_ERROR( GetATVChannel(demod, channel, standard)); + break; +#endif + case DRX_STANDARD_UNKNOWN: /* fall trough */ + default: + return (DRX_STS_ERROR); + } /* switch ( standard ) */ + + if (lockStatus == DRX_LOCKED) + { + channel->mirror = extAttr->mirror; + } + } /* if ( lockStatus == DRX_LOCKED ) */ + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= + ===== SigQuality() ========================================================== + ===========================================================================*/ + +static u16_t +mer2indicator ( + u16_t mer, + u16_t minMer, + u16_t thresholdMer, + u16_t maxMer) +{ + u16_t indicator = 0; + + if ( mer < minMer ) + { + indicator = 0; + } + else if ( mer < thresholdMer ) + { + if ((thresholdMer - minMer) != 0) + { + indicator = 25 * (mer - minMer) / (thresholdMer - minMer); + } + } + else if ( mer < maxMer ) + { + if ((maxMer - thresholdMer) != 0) + { + indicator = 25 + 75 * (mer - thresholdMer) / (maxMer - thresholdMer); + } + else + { + indicator = 25; + } + } + else + { + indicator = 100; + } + + return indicator; +} +/** +* \fn DRXStatus_t CtrlSigQuality() +* \brief Retreive signal quality form device. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal quality data. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigQuality contains valid data. +* \retval DRX_STS_INVALID_ARG sigQuality is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigQuality contains invalid data. + +*/ +static DRXStatus_t +CtrlSigQuality( pDRXDemodInstance_t demod, + pDRXSigQuality_t sigQuality ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + u16_t minMer = 0; + u16_t maxMer = 0; + u16_t thresholdMer = 0; + + /* Check arguments */ + if (( sigQuality == NULL ) || + ( demod == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + /* get basic information */ + devAddr = demod -> myI2CDevAddr; + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + switch ( standard ) { + case DRX_STANDARD_8VSB: +#ifdef DRXJ_SIGNAL_ACCUM_ERR + CHK_ERROR (GetAccPktErr (demod, &sigQuality->packetError)); +#else + CHK_ERROR (GetVSBPostRSPckErr (devAddr, &sigQuality->packetError)); +#endif + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + sigQuality->postViterbiBER = 500000; + sigQuality->MER = 20; + sigQuality->preViterbiBER = 0; + } else { + /* PostViterbi is compute in steps of 10^(-6) */ + CHK_ERROR (GetVSBpreViterbiBer (devAddr, &sigQuality->preViterbiBER)); + CHK_ERROR (GetVSBpostViterbiBer (devAddr, &sigQuality->postViterbiBER)); + CHK_ERROR (GetVSBMER (devAddr, &sigQuality->MER)); + } + minMer = 20; + maxMer = 360; + thresholdMer = 145; + sigQuality->postReedSolomonBER = 0; + sigQuality->scaleFactorBER = 1000000; + sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR ( CtrlGetQAMSigQuality ( demod, sigQuality ) ); + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + sigQuality->MER = 210; + break; + case DRX_CONSTELLATION_QAM128: + sigQuality->MER = 180; + break; + case DRX_CONSTELLATION_QAM64: + sigQuality->MER = 150; + break; + case DRX_CONSTELLATION_QAM32: + sigQuality->MER = 120; + break; + case DRX_CONSTELLATION_QAM16: + sigQuality->MER = 90; + break; + default: + sigQuality->MER = 0; + return (DRX_STS_ERROR); + } + } + + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + minMer = 210; + thresholdMer = 270; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM64: + minMer = 150; + thresholdMer = 210; + maxMer = 380; + break; + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + break; + default: + return (DRX_STS_ERROR); + } + sigQuality->indicator = mer2indicator (sigQuality->MER, minMer, thresholdMer, maxMer); + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + CHK_ERROR ( AtvSigQuality ( demod, sigQuality ) ); + break; + case DRX_STANDARD_FM: + CHK_ERROR ( FmSigQuality ( demod, sigQuality ) ); + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlLockStatus() +* \brief Retreive lock status . +* \param devAddr Pointer to demodulator device address. +* \param lockStat Pointer to lock status structure. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlLockStatus( pDRXDemodInstance_t demod, + pDRXLockStatus_t lockStat ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pDRXJData_t extAttr = NULL; + pI2CDeviceAddr_t devAddr = NULL; + DRXJSCUCmd_t cmdSCU = { /* command */ 0, + /* parameterLen */ 0, + /* resultLen */ 0, + /* *parameter */ NULL, + /* *result */ NULL }; + u16_t cmdResult[2] = { 0, 0 }; + u16_t demodLock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + + /* check arguments */ + if ( ( demod == NULL ) || + ( lockStat == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + *lockStat = DRX_NOT_LOCKED; + + /* define the SCU command code */ + switch ( standard ) { + case DRX_STANDARD_8VSB: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demodLock |= 0x6; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + cmdSCU.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; + case DRX_STANDARD_FM: + return FmLockStatus( demod, lockStat); +#endif + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_ERROR); + } + + /* define the SCU command paramters and execute the command */ + cmdSCU.parameterLen = 0; + cmdSCU.resultLen = 2; + cmdSCU.parameter = NULL; + cmdSCU.result = cmdResult; + CHK_ERROR( SCUCommand( devAddr, &cmdSCU ) ); + + /* set the lock status */ + if ( cmdSCU.result[1] < demodLock ) + { + /* 0x0000 NOT LOCKED */ + *lockStat = DRX_NOT_LOCKED; + } + else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED ) + { + *lockStat = DRXJ_DEMOD_LOCK; + } + else if ( cmdSCU.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK ) + { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lockStat = DRX_LOCKED; + } + else + { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lockStat = DRX_NEVER_LOCK; + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlConstel() +* \brief Retreive a constellation point via I2C. +* \param demod Pointer to demodulator instance. +* \param complexNr Pointer to the structure in which to store the + constellation point. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlConstel( pDRXDemodInstance_t demod, + pDRXComplex_t complexNr ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; /**< active standard */ + + /* check arguments */ + if ( ( demod == NULL ) || + ( complexNr == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + /* read device info */ + standard = ((pDRXJData_t)demod->myExtAttr)->standard; + + /* Read constellation point */ + switch ( standard ) { + case DRX_STANDARD_8VSB: + CHK_ERROR( CtrlGetVSBConstel( demod, complexNr ) ); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR( CtrlGetQAMConstel( demod, complexNr ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_ERROR); + } + + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetStandard() +* \brief Set modulation standard to be used. +* \param standard Modulation standard. +* \return DRXStatus_t. +* +* Setup stuff for the desired demodulation standard. +* Disable and power down the previous selected demodulation standard +* +*/ +static DRXStatus_t +CtrlSetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +{ + pDRXJData_t extAttr = NULL; + DRXStandard_t prevStandard; + + /* check arguments */ + if (( standard == NULL ) || + ( demod == NULL )) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + prevStandard=extAttr->standard; + + /* + Stop and power down previous standard + */ + switch ( prevStandard ) + { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + CHK_ERROR( PowerDownQAM(demod, FALSE) ); + break; +#endif + case DRX_STANDARD_8VSB: + CHK_ERROR( PowerDownVSB(demod, FALSE) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR( PowerDownATV( demod, prevStandard, FALSE )); + break; +#endif + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* + Initialize channel independent registers + Power up new standard + */ + extAttr->standard=*standard; + + switch ( *standard ) + { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + DUMMY_READ(); + break; +#endif + case DRX_STANDARD_8VSB: + CHK_ERROR(SetVSBLeakNGain(demod)); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP: + CHK_ERROR( SetATVStandard( demod, standard )); + CHK_ERROR( PowerUpATV( demod, *standard )); + break; +#endif + default: + extAttr->standard=DRX_STANDARD_UNKNOWN; + return ( DRX_STS_INVALID_ARG ); + break; + } + + return (DRX_STS_OK); +rw_error: + /* Don't know what the standard is now ... try again */ + extAttr->standard=DRX_STANDARD_UNKNOWN; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetStandard() +* \brief Get modulation standard currently used to demodulate. +* \param standard Modulation standard. +* \return DRXStatus_t. +* +* Returns 8VSB, NTSC, QAM only. +* +*/ +static DRXStatus_t +CtrlGetStandard( pDRXDemodInstance_t demod, pDRXStandard_t standard ) +{ + pDRXJData_t extAttr = NULL; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( standard == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + (*standard) = extAttr->standard; + DUMMY_READ(); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgSymbolClockOffset() +* \brief Get frequency offsets of STR. +* \param pointer to s32_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgSymbolClockOffset ( pDRXDemodInstance_t demod, + ps32_t rateOffset ) +{ + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( rateOffset == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + + switch ( standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + CHK_ERROR ( GetSTRFreqOffset ( demod, rateOffset )); + break; + case DRX_STANDARD_NTSC: + case DRX_STANDARD_UNKNOWN: + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlPowerMode() +* \brief Set the power mode of the device to the specified power mode +* \param demod Pointer to demodulator instance. +* \param mode Pointer to new power mode. +* \return DRXStatus_t. +* \retval DRX_STS_OK Success +* \retval DRX_STS_ERROR I2C error or other failure +* \retval DRX_STS_INVALID_ARG Invalid mode argument. +* +* +*/ +static DRXStatus_t +CtrlPowerMode( pDRXDemodInstance_t demod, + pDRXPowerMode_t mode ) +{ + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)NULL; + pDRXJData_t extAttr = (pDRXJData_t)NULL; + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)NULL; + u16_t sioCcPwdMode = 0; + + commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; + extAttr = (pDRXJData_t)demod->myExtAttr; + devAddr = demod -> myI2CDevAddr; + + /* Check arguments */ + if ( mode == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + /* If already in requested power mode, do nothing */ + if ( commonAttr->currentPowerMode == *mode ) + { + return (DRX_STS_OK); + } + + switch ( *mode ) + { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXJ_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return (DRX_STS_INVALID_ARG); + break; + } + + + /* Check if device needs to be powered up */ + if ( ( commonAttr->currentPowerMode != DRX_POWER_UP ) ) + { + CHK_ERROR(PowerUpDevice(demod)); + } + + if ( ( *mode == DRX_POWER_UP ) ) + { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch ( extAttr->standard ) + { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + CHK_ERROR( PowerDownQAM(demod, TRUE) ); + break; + case DRX_STANDARD_8VSB: + CHK_ERROR( PowerDownVSB(demod, TRUE) ); + break; + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR( PowerDownATV( demod, extAttr->standard, TRUE )); + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: /* fallthrough */ + default: + return ( DRX_STS_ERROR ); + } + + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) + { + WR16( devAddr, SIO_CC_PWD_MODE__A, sioCcPwdMode); + WR16( devAddr, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY); + + /* Initialize HI, wakeup key especially before put IC to sleep */ + CHK_ERROR(InitHI(demod) ); + + extAttr -> HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR( HICfgCommand( demod ) ); + } + } + + commonAttr->currentPowerMode = *mode; + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlVersion() +* \brief Report version of microcode and if possible version of device +* \param demod Pointer to demodulator instance. +* \param versionList Pointer to pointer of linked list of versions. +* \return DRXStatus_t. +* +* Using static structures so no allocation of memory is needed. +* Filling in all the fields each time, cause you don't know if they are +* changed by the application. +* +* For device: +* Major version number will be last two digits of family number. +* Minor number will be full respin number +* Patch will be metal fix number+1 +* Examples: +* DRX3942J A2 => number: 42.1.2 text: "DRX3942J:A2" +* DRX3933J B1 => number: 33.2.1 text: "DRX3933J:B1" +* +*/ +static DRXStatus_t +CtrlVersion( pDRXDemodInstance_t demod, + pDRXVersionList_t *versionList ) +{ + pDRXJData_t extAttr = (pDRXJData_t) (NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL); + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + u16_t ucodeMajorMinor = 0; /* BCD Ma:Ma:Ma:Mi */ + u16_t ucodePatch = 0; /* BCD Pa:Pa:Pa:Pa */ + u16_t major = 0; + u16_t minor = 0; + u16_t patch = 0; + u16_t idx = 0; + u32_t jtag = 0; + u16_t subtype = 0; + u16_t mfx = 0; + u16_t bid = 0; + u16_t key = 0; + + static char ucodeName[] = "Microcode"; + static char deviceName[] = "Device"; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr; + + /* Microcode version ****************************************/ + + extAttr->vVersion[0].moduleType = DRX_MODULE_MICROCODE; + extAttr->vVersion[0].moduleName = ucodeName; + extAttr->vVersion[0].vString = extAttr->vText[0]; + + if ( commonAttr->isOpened == TRUE ) + { + SARR16( devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor ); + SARR16( devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch ); + + /* Translate BCD to numbers and string */ + /* TODO: The most significant Ma and Pa will be ignored, check with spec */ + minor = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major = (ucodeMajorMinor & 0xF); + ucodeMajorMinor >>= 4; + major += (10* (ucodeMajorMinor & 0xF)); + patch = (ucodePatch & 0xF); + ucodePatch >>= 4; + patch += (10*(ucodePatch & 0xF)); + ucodePatch >>= 4; + patch += (100*(ucodePatch & 0xF)); + } + else + { + /* No microcode uploaded, No Rom existed, set version to 0.0.0 */ + patch = 0; + minor = 0; + major = 0; + } + extAttr->vVersion[0].vMajor = major; + extAttr->vVersion[0].vMinor = minor; + extAttr->vVersion[0].vPatch = patch; + + if ( major/10 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(major/10))+'0'; + major %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)major)+'0'; + extAttr->vVersion[0].vString[idx++] = '.'; + extAttr->vVersion[0].vString[idx++] = ((char)minor)+'0'; + extAttr->vVersion[0].vString[idx++] = '.'; + if ( patch/100 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(patch/100))+'0'; + patch %= 100; + } + if ( patch/10 != 0 ) + { + extAttr->vVersion[0].vString[idx++] = ((char)(patch/10))+'0'; + patch %= 10; + } + extAttr->vVersion[0].vString[idx++] = ((char)patch)+'0'; + extAttr->vVersion[0].vString[idx] = '\0'; + + extAttr->vListElements[0].version = &(extAttr->vVersion[0]); + extAttr->vListElements[0].next = &(extAttr->vListElements[1]); + + + /* Device version ****************************************/ + /* Check device id */ + RR16( devAddr, SIO_TOP_COMM_KEY__A , &key); + WR16( devAddr, SIO_TOP_COMM_KEY__A , 0xFABA); + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag ); + RR16( devAddr, SIO_PDR_UIO_IN_HI__A , &bid); + WR16( devAddr, SIO_TOP_COMM_KEY__A , key); + + extAttr->vVersion[1].moduleType = DRX_MODULE_DEVICE; + extAttr->vVersion[1].moduleName = deviceName; + extAttr->vVersion[1].vString = extAttr->vText[1]; + extAttr->vVersion[1].vString[0] = 'D'; + extAttr->vVersion[1].vString[1] = 'R'; + extAttr->vVersion[1].vString[2] = 'X'; + extAttr->vVersion[1].vString[3] = '3'; + extAttr->vVersion[1].vString[4] = '9'; + extAttr->vVersion[1].vString[7] = 'J'; + extAttr->vVersion[1].vString[8] = ':'; + extAttr->vVersion[1].vString[11] = '\0'; + + /* DRX39xxJ type Ax */ + /* TODO semantics of mfx and spin are unclear */ + subtype = (u16_t)((jtag>>12)&0xFF); + mfx = (u16_t)(jtag>>29); + extAttr->vVersion[1].vMinor = 1; + if (mfx == 0x03) + { + extAttr->vVersion[1].vPatch = mfx+2; + } + else + { + extAttr->vVersion[1].vPatch = mfx+1; + } + extAttr->vVersion[1].vString[6] = ((char)(subtype&0xF))+'0'; + extAttr->vVersion[1].vMajor = (subtype & 0x0F); + subtype>>=4; + extAttr->vVersion[1].vString[5] = ((char)(subtype&0xF))+'0'; + extAttr->vVersion[1].vMajor += 10*subtype; + extAttr->vVersion[1].vString[9] = 'A'; + if (mfx == 0x03) + { + extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '2' ; + } + else + { + extAttr->vVersion[1].vString[10] = ((char)(mfx&0xF)) + '1' ; + } + + extAttr->vListElements[1].version = &(extAttr->vVersion[1]); + extAttr->vListElements[1].next = (pDRXVersionList_t)(NULL); + + *versionList = &(extAttr->vListElements[0]); + + return ( DRX_STS_OK ); + + rw_error: + *versionList = (pDRXVersionList_t)(NULL); + return (DRX_STS_ERROR); + +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlProbeDevice() +* \brief Probe device, check if it is present +* \param demod Pointer to demodulator instance. +* \return DRXStatus_t. +* \retval DRX_STS_OK a drx39xxj device has been detected. +* \retval DRX_STS_ERROR no drx39xxj device detected. +* +* This funtion can be caled before open() and after close(). +* +*/ + +static DRXStatus_t +CtrlProbeDevice( pDRXDemodInstance_t demod ) +{ + DRXPowerMode_t orgPowerMode = DRX_POWER_UP; + DRXStatus_t retStatus = DRX_STS_OK; + pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL); + + commonAttr = (pDRXCommonAttr_t)demod -> myCommonAttr; + + if ( commonAttr->isOpened == FALSE || commonAttr->currentPowerMode != DRX_POWER_UP) + { + pI2CDeviceAddr_t devAddr = NULL; + DRXPowerMode_t powerMode = DRX_POWER_UP; + u32_t jtag = 0; + + devAddr = demod -> myI2CDevAddr; + + /* Remeber original power mode */ + orgPowerMode = commonAttr->currentPowerMode; + + if(demod->myCommonAttr->isOpened == FALSE) + { + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; + } + else + { + /* Wake-up device, feedback from device */ + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + } + /* Initialize HI, wakeup key especially */ + CHK_ERROR(InitHI(demod) ); + + /* Check device id */ + RR32( devAddr, SIO_TOP_JTAGID_LO__A , &jtag); + jtag = (jtag>>12) & 0xFFFF; + switch ( jtag ) + { + case 0x3931: /* fallthrough */ + case 0x3932: /* fallthrough */ + case 0x3933: /* fallthrough */ + case 0x3934: /* fallthrough */ + case 0x3941: /* fallthrough */ + case 0x3942: /* fallthrough */ + case 0x3943: /* fallthrough */ + case 0x3944: /* fallthrough */ + case 0x3945: /* fallthrough */ + case 0x3946: + /* ok , do nothing */ + break; + default: + retStatus = DRX_STS_ERROR; + break; + } + + /* Device was not opened, return to orginal powermode, + feedback from device */ + CHK_ERROR( CtrlPowerMode( demod, &orgPowerMode )); + } + else + { + /* dummy read to make this function fail in case device + suddenly disappears after a succesful DRX_Open */ + DUMMY_READ(); + } + + return ( retStatus ); + + rw_error: + commonAttr->currentPowerMode=orgPowerMode; + return (DRX_STS_ERROR); +} + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD +/*============================================================================*/ + +/** +* \fn DRXStatus_t IsMCBlockAudio() +* \brief Check if MC block is Audio or not Audio. +* \param addr Pointer to demodulator instance. +* \param audioUpload TRUE if MC block is Audio + FALSE if MC block not Audio +* \return Bool_t. +*/ +Bool_t IsMCBlockAudio( u32_t addr ) +{ + if ( ( addr == AUD_XFP_PRAM_4K__A ) || + ( addr == AUD_XDFP_PRAM_4K__A ) ) + { + return ( TRUE ); + } + return ( FALSE ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlUCodeUpload() +* \brief Handle Audio or !Audio part of microcode upload. +* \param demod Pointer to demodulator instance. +* \param mcInfo Pointer to information about microcode data. +* \param action Either UCODE_UPLOAD or UCODE_VERIFY. +* \param uploadAudioMC TRUE if Audio MC need to be uploaded. + FALSE if !Audio MC need to be uploaded. +* \return DRXStatus_t. +*/ +static DRXStatus_t +CtrlUCodeUpload( pDRXDemodInstance_t demod, + pDRXUCodeInfo_t mcInfo, + DRXUCodeAction_t action, + Bool_t uploadAudioMC ) +{ + u16_t i = 0; + u16_t mcNrOfBlks = 0; + u16_t mcMagicWord = 0; + pu8_t mcData = (pu8_t)(NULL); + pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL); + pDRXJData_t extAttr = (pDRXJData_t)(NULL); + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod -> myExtAttr; + + /* Check arguments */ + if ( ( mcInfo == NULL ) || + ( mcInfo->mcData == NULL ) || + ( mcInfo->mcSize == 0 ) ) + { + return DRX_STS_INVALID_ARG; + } + + mcData = mcInfo->mcData; + + /* Check data */ + mcMagicWord = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + mcNrOfBlks = UCodeRead16( mcData ); + mcData += sizeof( u16_t ); + + if ( ( mcMagicWord != DRXJ_UCODE_MAGIC_WORD ) || + ( mcNrOfBlks == 0 ) ) + { + /* wrong endianess or wrong data ? */ + return DRX_STS_INVALID_ARG; + } + + /* Process microcode blocks */ + for( i = 0 ; i 0x7FFF ) || + ( (( blockHdr.flags & DRXJ_UCODE_CRC_FLAG ) != 0) && + ( blockHdr.CRC != UCodeComputeCRC( mcData, blockHdr.size)) ) + ) + { + /* Wrong data ! */ + return DRX_STS_INVALID_ARG; + } + + mcBlockNrBytes = blockHdr.size * sizeof(u16_t); + + /* Perform the desired action */ + /* Check which part of MC need to be uploaded - Audio or not Audio */ + if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) + { + switch ( action ) { + /*===================================================================*/ + case UCODE_UPLOAD : + { + /* Upload microcode */ + if ( demod->myAccessFunct->writeBlockFunc( + devAddr, + (DRXaddr_t) blockHdr.addr, + mcBlockNrBytes, + mcData, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + }; + break; + + /*===================================================================*/ + case UCODE_VERIFY : + { + int result = 0; + u8_t mcDataBuffer[DRXJ_UCODE_MAX_BUF_SIZE]; + u32_t bytesToCompare=0; + u32_t bytesLeftToCompare=0; + DRXaddr_t currAddr = (DRXaddr_t)0; + pu8_t currPtr =NULL; + + bytesLeftToCompare = mcBlockNrBytes; + currAddr = blockHdr.addr; + currPtr = mcData; + + while( bytesLeftToCompare != 0 ) + { + if (bytesLeftToCompare > ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE) ) + { + bytesToCompare = ((u32_t)DRXJ_UCODE_MAX_BUF_SIZE); + } else { + bytesToCompare = bytesLeftToCompare; + } + + if ( demod->myAccessFunct->readBlockFunc( + devAddr, + currAddr, + (u16_t)bytesToCompare, + (pu8_t)mcDataBuffer, + 0x0000) != DRX_STS_OK) + { + return (DRX_STS_ERROR); + } + + result = DRXBSP_HST_Memcmp( currPtr, + mcDataBuffer, + bytesToCompare); + + if ( result != 0 ) + { + return (DRX_STS_ERROR); + }; + + currAddr += ((DRXaddr_t)(bytesToCompare/2)); + currPtr = &(currPtr[bytesToCompare]); + bytesLeftToCompare -= ((u32_t)bytesToCompare); + } /* while( bytesToCompare > DRXJ_UCODE_MAX_BUF_SIZE ) */ + }; + break; + + /*===================================================================*/ + default: + return DRX_STS_INVALID_ARG; + break; + + } /* switch ( action ) */ + } /* if( IsMCBlockAudio( blockHdr.addr ) == uploadAudioMC ) */ + + /* Next block */ + mcData += mcBlockNrBytes; + } /* for( i = 0 ; iflagAudMcUploaded = FALSE; + } + + return (DRX_STS_OK); +} +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + +/*============================================================================*/ +/*== CTRL Set/Get Config related functions ===================================*/ +/*============================================================================*/ + +/*===== SigStrength() =========================================================*/ +/** +* \fn DRXStatus_t CtrlSigStrength() +* \brief Retrieve signal strength. +* \param devmod Pointer to demodulator instance. +* \param sigQuality Pointer to signal strength data; range 0, .. , 100. +* \return DRXStatus_t. +* \retval DRX_STS_OK sigStrength contains valid data. +* \retval DRX_STS_INVALID_ARG sigStrength is NULL. +* \retval DRX_STS_ERROR Erroneous data, sigStrength contains invalid data. + +*/ +static DRXStatus_t +CtrlSigStrength( pDRXDemodInstance_t demod, + pu16_t sigStrength ) +{ + pDRXJData_t extAttr = NULL; + DRXStandard_t standard = DRX_STANDARD_UNKNOWN; + + /* Check arguments */ + if ( ( sigStrength == NULL ) || + ( demod == NULL ) ) + { + return (DRX_STS_INVALID_ARG); + } + + extAttr = (pDRXJData_t)demod->myExtAttr; + standard = extAttr->standard; + *sigStrength = 0; + + /* Signal strength indication for each standard */ + switch ( standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + CHK_ERROR( GetSigStrength( demod, sigStrength ) ); + break; +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + CHK_ERROR( GetAtvSigStrength( demod, sigStrength ) ); + break; +#endif + case DRX_STANDARD_UNKNOWN: /* fallthrough */ + default: + return (DRX_STS_INVALID_ARG); + } + + /* TODO */ + /* find out if signal strength is calculated in the same way for all standards */ + return (DRX_STS_OK); + rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXStatus_t CtrlGetCfgOOBMisc() +* \brief Get current state information of OOB. +* \param pointer to DRXJCfgOOBMisc_t. +* \return DRXStatus_t. +* +*/ +#ifndef DRXJ_DIGITAL_ONLY +static DRXStatus_t +CtrlGetCfgOOBMisc ( pDRXDemodInstance_t demod, pDRXJCfgOOBMisc_t misc ) +{ + pI2CDeviceAddr_t devAddr = NULL; + u16_t lock = 0U; + u16_t state = 0U; + u16_t data = 0U; + u16_t digitalAGCMant = 0U; + u16_t digitalAGCExp = 0U; + + /* check arguments */ + if ( misc == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod -> myI2CDevAddr; + + /* TODO */ + /* check if the same registers are used for all standards (QAM/VSB/ATV) */ + RR16( devAddr, ORX_NSU_TUN_IFGAIN_W__A, &misc->agc.IFAGC ); + RR16( devAddr, ORX_NSU_TUN_RFGAIN_W__A, &misc->agc.RFAGC ); + RR16( devAddr, ORX_FWP_SRC_DGN_W__A, &data ); + + digitalAGCMant = data & ORX_FWP_SRC_DGN_W_MANT__M; + digitalAGCExp = (data & ORX_FWP_SRC_DGN_W_EXP__M) + >> ORX_FWP_SRC_DGN_W_EXP__B; + misc->agc.DigitalAGC = digitalAGCMant << digitalAGCExp; + + SARR16( devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock ); + + misc->anaGainLock = ((lock & 0x0001)?TRUE:FALSE); + misc->digGainLock = ((lock & 0x0002)?TRUE:FALSE); + misc->freqLock = ((lock & 0x0004)?TRUE:FALSE); + misc->phaseLock = ((lock & 0x0008)?TRUE:FALSE); + misc->symTimingLock = ((lock & 0x0010)?TRUE:FALSE); + misc->eqLock = ((lock & 0x0020)?TRUE:FALSE); + + SARR16( devAddr, SCU_RAM_ORX_SCU_STATE__A, &state ); + misc->state = (state>>8) & 0xff; + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +#endif + +/** +* \fn DRXStatus_t CtrlGetCfgVSBMisc() +* \brief Get current state information of OOB. +* \param pointer to DRXJCfgOOBMisc_t. +* \return DRXStatus_t. +* +*/ +static DRXStatus_t +CtrlGetCfgVSBMisc ( pDRXDemodInstance_t demod, pDRXJCfgVSBMisc_t misc ) +{ + pI2CDeviceAddr_t devAddr = NULL; + + /* check arguments */ + if ( misc == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + devAddr = demod -> myI2CDevAddr; + + CHK_ERROR(GetVSBSymbErr(devAddr, &misc->symbError)); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAgcIf() +* \brief Set IF AGC. +* \param demod demod instance +* \param agcSettings If agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( agcSettings->ctrlMode ) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: /* fallthrough */ + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return SetAgcIf ( demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcIf() +* \brief Retrieve IF AGC settings. +* \param demod demod instance +* \param agcSettings If agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcIf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return GetAgcIf ( demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAgcRf() +* \brief Set RF AGC. +* \param demod demod instance +* \param agcSettings rf agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + switch ( agcSettings->ctrlMode ) { + case DRX_AGC_CTRL_AUTO: /* fallthrough */ + case DRX_AGC_CTRL_USER: /* fallthrough */ + case DRX_AGC_CTRL_OFF: + break; + default: + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return SetAgcRf ( demod, agcSettings, TRUE); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcRf() +* \brief Retrieve RF AGC settings. +* \param demod demod instance +* \param agcSettings Rf agc configuration +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcRf ( pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings ) +{ + /* check arguments */ + if ( agcSettings == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Distpatch */ + switch ( agcSettings->standard ) { + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: +#endif + return GetAgcRf ( demod, agcSettings); + case DRX_STANDARD_UNKNOWN: + default: + return ( DRX_STS_INVALID_ARG ); + } + + return ( DRX_STS_OK ); +} + + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAgcInternal() +* \brief Retrieve internal AGC value. +* \param demod demod instance +* \param u16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAgcInternal ( pDRXDemodInstance_t demod, pu16_t agcInternal ) +{ + pI2CDeviceAddr_t devAddr = NULL; + DRXLockStatus_t lockStatus = DRX_NOT_LOCKED; + pDRXJData_t extAttr = NULL; + u16_t iqmCfScaleSh = 0; + u16_t iqmCfPower = 0; + u16_t iqmCfAmp = 0; + u16_t iqmCfGain = 0; + + /* check arguments */ + if ( agcInternal == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + CHK_ERROR( CtrlLockStatus( demod, &lockStatus) ); + if ( lockStatus != DRXJ_DEMOD_LOCK && lockStatus != DRX_LOCKED ) + { + *agcInternal = 0; + return DRX_STS_OK; + } + + /* Distpatch */ + switch ( extAttr->standard ) { + case DRX_STANDARD_8VSB: + iqmCfGain = 57; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + switch ( extAttr->constellation ) + { + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM16: + iqmCfGain = 57; + break; + case DRX_CONSTELLATION_QAM64: + iqmCfGain = 56; + break; + default: + return (DRX_STS_ERROR); + } + break; +#endif + default: + return ( DRX_STS_INVALID_ARG ); + } + + RR16( devAddr, IQM_CF_POW__A, &iqmCfPower); + RR16( devAddr, IQM_CF_SCALE_SH__A, &iqmCfScaleSh); + RR16( devAddr, IQM_CF_AMP__A, &iqmCfAmp); + /* IQM_CF_PWR_CORRECTION_dB = 3; + P5dB =10*log10(IQM_CF_POW)+12-6*9-IQM_CF_PWR_CORRECTION_dB; */ + /* P4dB = P5dB -20*log10(IQM_CF_AMP)-6*10 + -IQM_CF_Gain_dB-18+6*(27-IQM_CF_SCALE_SH*2-10) + +6*7+10*log10(1+0.115/4); */ + /* PadcdB = P4dB +3 -6 +60; dBmV */ + *agcInternal = (u16_t) ( Log10Times100 (iqmCfPower) + - 2 * Log10Times100 (iqmCfAmp) + - iqmCfGain + - 120 * iqmCfScaleSh + + 781 ); + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgPreSaw() +* \brief Set Pre-saw reference. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + /* check arguments */ + if ( ( preSaw == NULL ) || + ( preSaw->reference > IQM_AF_PDREF__M ) + ) + { + return ( DRX_STS_INVALID_ARG ); + } + + /* Only if standard is currently active*/ + if ( ( extAttr->standard == preSaw->standard ) || + ( DRXJ_ISQAMSTD( extAttr->standard ) && + DRXJ_ISQAMSTD( preSaw->standard ) ) || + ( DRXJ_ISATVSTD( extAttr->standard ) && + DRXJ_ISATVSTD( preSaw->standard ) ) ) + { + WR16( devAddr, IQM_AF_PDREF__A , preSaw->reference); + } + + /* Store pre-saw settings */ + switch ( preSaw->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbPreSawCfg = *preSaw; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPreSawCfg = *preSaw; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: /* fallthrough */ + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg = *preSaw; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlSetCfgAfeGain() +* \brief Set AFE Gain. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlSetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + u8_t gain = 0; + + /* check arguments */ + if ( afeGain == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: /* fallthrough */ +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: +#endif + /* Do nothing */ + break; + default: + return (DRX_STS_INVALID_ARG); + } + + /* TODO PGA gain is also written by microcode (at least by QAM and VSB) + So I (PJ) think interface requires choice between auto, user mode */ + + if (afeGain->gain >= 329) + gain = 15; + else if (afeGain->gain <= 147) + gain = 0; + else + gain = (afeGain->gain - 140 + 6) / 13; + + /* Only if standard is currently active*/ + if( extAttr->standard == afeGain->standard ) + WR16( devAddr, IQM_AF_PGA_GAIN__A, gain); + + /* Store AFE Gain settings */ + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: + extAttr->vsbPgaCfg = gain * 13 + 140; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + extAttr->qamPgaCfg = gain * 13 + 140; + break; +#endif + default: + return (DRX_STS_ERROR); + } + + return ( DRX_STS_OK ); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgPreSaw() +* \brief Get Pre-saw reference setting. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgPreSaw ( pDRXDemodInstance_t demod, pDRXJCfgPreSaw_t preSaw ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( preSaw == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( preSaw->standard ){ + case DRX_STANDARD_8VSB: + *preSaw = extAttr->vsbPreSawCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + *preSaw = extAttr->qamPreSawCfg; + break; +#endif +#ifndef DRXJ_DIGITAL_ONLY + case DRX_STANDARD_PAL_SECAM_BG : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_DK : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_I : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_L : /* fallthrough */ + case DRX_STANDARD_PAL_SECAM_LP : /* fallthrough */ + case DRX_STANDARD_NTSC: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; + *preSaw = extAttr->atvPreSawCfg; + break; + case DRX_STANDARD_FM: + extAttr->atvPreSawCfg.standard = DRX_STANDARD_FM; + *preSaw = extAttr->atvPreSawCfg; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfgAfeGain() +* \brief Get AFE Gain. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetCfgAfeGain ( pDRXDemodInstance_t demod, pDRXJCfgAfeGain_t afeGain ) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + + /* check arguments */ + if ( afeGain == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t)demod->myExtAttr; + + switch ( afeGain->standard){ + case DRX_STANDARD_8VSB: + afeGain->gain = extAttr->vsbPgaCfg; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: /* fallthrough */ + case DRX_STANDARD_ITU_B: /* fallthrough */ + case DRX_STANDARD_ITU_C: + afeGain->gain = extAttr->qamPgaCfg; + break; +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return ( DRX_STS_OK ); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetFecMeasSeqCount() +* \brief Get FEC measurement sequnce number. +* \param demod demod instance +* \param pu16_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetFecMeasSeqCount ( pDRXDemodInstance_t demod, pu16_t fecMeasSeqCount) +{ + /* check arguments */ + if ( fecMeasSeqCount == NULL ) + { + return ( DRX_STS_INVALID_ARG ); + } + + RR16 ( demod->myI2CDevAddr, SCU_RAM_FEC_MEAS_COUNT__A, fecMeasSeqCount ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetAccumCrRSCwErr() +* \brief Get accumulative corrected RS codeword number. +* \param demod demod instance +* \param pu32_t +* \return DRXStatus_t. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static DRXStatus_t +CtrlGetAccumCrRSCwErr ( pDRXDemodInstance_t demod, pu32_t accumCrRsCWErr) +{ + if(accumCrRsCWErr == NULL) + { + return (DRX_STS_INVALID_ARG); + } + + RR32 ( demod->myI2CDevAddr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, accumCrRsCWErr ); + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/** +* \fn DRXStatus_t CtrlSetCfg() +* \brief Set 'some' configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param config Pointer to configuration parameters (type and data). +* \return DRXStatus_t. + +*/ +static DRXStatus_t +CtrlSetCfg( pDRXDemodInstance_t demod, + pDRXCfg_t config ) +{ + if ( config == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + DUMMY_READ(); + switch ( config->cfgType ) + { + case DRX_CFG_MPEG_OUTPUT: + return CtrlSetCfgMPEGOutput( demod, (pDRXCfgMPEGOutput_t) config->cfgData ); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlSetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); + case DRXJ_CFG_AGC_RF: + return CtrlSetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_IF: + return CtrlSetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_PRE_SAW: + return CtrlSetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); + case DRXJ_CFG_AFE_GAIN: + return CtrlSetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); + case DRXJ_CFG_SMART_ANT: + return CtrlSetCfgSmartAnt ( demod, (pDRXJCfgSmartAnt_t)(config->cfgData) ); + case DRXJ_CFG_RESET_PACKET_ERR: + return CtrlSetCfgResetPktErr ( demod ); +#ifndef DRXJ_DIGITAL_ONLY + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlSetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); + case DRXJ_CFG_OOB_LO_POW: + return CtrlSetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); + case DRXJ_CFG_ATV_MISC: + return CtrlSetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlSetCfgAtvEquCoef( demod, + (pDRXJCfgAtvEquCoef_t) config->cfgData ); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlSetCfgATVOutput( demod, + (pDRXJCfgAtvOutput_t) config->cfgData ); +#endif + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlSetCfgMpegOutputMisc( demod, + (pDRXJCfgMpegOutputMisc_t) config->cfgData ); +#ifndef DRXJ_EXCLUDE_AUDIO + case DRX_CFG_AUD_VOLUME: + return AUDCtrlSetCfgVolume( demod, + (pDRXCfgAudVolume_t)config->cfgData ); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlSetCfgOutputI2S( demod, + (pDRXCfgI2SOutput_t)config->cfgData ); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrSetlCfgAutoSound( demod, + (pDRXCfgAudAutoSound_t) + config->cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlSetCfgASSThres( demod, + (pDRXCfgAudASSThres_t) + config->cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlSetCfgCarrier( demod, + (pDRXCfgAudCarriers_t)config->cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlSetCfgDev( demod, + (pDRXCfgAudDeviation_t)config->cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlSetCfgPrescale( demod, + (pDRXCfgAudPrescale_t)config->cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlSetCfgMixer( demod, + (pDRXCfgAudMixer_t)config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlSetCfgAVSync( demod, + (pDRXCfgAudAVSync_t)config->cfgData); + +#endif + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ + +/** +* \fn DRXStatus_t CtrlGetCfg() +* \brief Get 'some' configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param config Pointer to configuration parameters (type and data). +* \return DRXStatus_t. +*/ + +static DRXStatus_t +CtrlGetCfg( pDRXDemodInstance_t demod, + pDRXCfg_t config ) +{ + if ( config == NULL ) + { + return (DRX_STS_INVALID_ARG); + } + + DUMMY_READ(); + + switch ( config->cfgType ) + { + case DRX_CFG_MPEG_OUTPUT: + return CtrlGetCfgMPEGOutput( demod, + (pDRXCfgMPEGOutput_t) config->cfgData ); + case DRX_CFG_PINS_SAFE_MODE: + return CtrlGetCfgPdrSafeMode( demod, (pBool_t) config->cfgData ); + case DRXJ_CFG_AGC_RF: + return CtrlGetCfgAgcRf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_IF: + return CtrlGetCfgAgcIf ( demod, (pDRXJCfgAgc_t) config->cfgData ); + case DRXJ_CFG_AGC_INTERNAL: + return CtrlGetCfgAgcInternal ( demod, (pu16_t) config->cfgData ); + case DRXJ_CFG_PRE_SAW: + return CtrlGetCfgPreSaw ( demod, (pDRXJCfgPreSaw_t) config->cfgData ); + case DRXJ_CFG_AFE_GAIN: + return CtrlGetCfgAfeGain ( demod, (pDRXJCfgAfeGain_t) config->cfgData ); + case DRXJ_CFG_ACCUM_CR_RS_CW_ERR: + return CtrlGetAccumCrRSCwErr ( demod, (pu32_t) config->cfgData ); + case DRXJ_CFG_FEC_MERS_SEQ_COUNT: + return CtrlGetFecMeasSeqCount ( demod, (pu16_t) config->cfgData ); + case DRXJ_CFG_VSB_MISC: + return CtrlGetCfgVSBMisc ( demod, (pDRXJCfgVSBMisc_t) config->cfgData ); + case DRXJ_CFG_SYMBOL_CLK_OFFSET: + return CtrlGetCfgSymbolClockOffset ( demod, (ps32_t) config->cfgData ); +#ifndef DRXJ_DIGITAL_ONLY + case DRXJ_CFG_OOB_MISC: + return CtrlGetCfgOOBMisc ( demod, (pDRXJCfgOOBMisc_t) config->cfgData ); + case DRXJ_CFG_OOB_PRE_SAW: + return CtrlGetCfgOOBPreSAW ( demod, (pu16_t)(config->cfgData) ); + case DRXJ_CFG_OOB_LO_POW: + return CtrlGetCfgOOBLoPower ( demod, (pDRXJCfgOobLoPower_t)(config->cfgData) ); + case DRXJ_CFG_ATV_EQU_COEF: + return CtrlGetCfgAtvEquCoef( demod, + (pDRXJCfgAtvEquCoef_t) config->cfgData ); + case DRXJ_CFG_ATV_MISC: + return CtrlGetCfgAtvMisc( demod, (pDRXJCfgAtvMisc_t) config->cfgData ); + case DRXJ_CFG_ATV_OUTPUT: + return CtrlGetCfgAtvOutput( demod, + (pDRXJCfgAtvOutput_t) config->cfgData ); + case DRXJ_CFG_ATV_AGC_STATUS: + return CtrlGetCfgAtvAgcStatus( demod, + (pDRXJCfgAtvAgcStatus_t) config->cfgData ); +#endif + case DRXJ_CFG_MPEG_OUTPUT_MISC: + return CtrlGetCfgMpegOutputMisc( demod, + (pDRXJCfgMpegOutputMisc_t) config->cfgData ); + case DRXJ_CFG_HW_CFG: + return CtrlGetCfgHwCfg( demod, + (pDRXJCfgHwCfg_t) config->cfgData ); +#ifndef DRXJ_EXCLUDE_AUDIO + case DRX_CFG_AUD_VOLUME: + return AUDCtrlGetCfgVolume ( demod, + (pDRXCfgAudVolume_t)config->cfgData ); + case DRX_CFG_I2S_OUTPUT: + return AUDCtrlGetCfgOutputI2S ( demod, + (pDRXCfgI2SOutput_t)config->cfgData ); + + case DRX_CFG_AUD_RDS: + return AUDCtrlGetCfgRDS ( demod, + (pDRXCfgAudRDS_t)config->cfgData ); + case DRX_CFG_AUD_AUTOSOUND: + return AUDCtrlGetCfgAutoSound ( demod, + (pDRXCfgAudAutoSound_t)config->cfgData); + case DRX_CFG_AUD_ASS_THRES: + return AUDCtrlGetCfgASSThres ( demod, + (pDRXCfgAudASSThres_t)config->cfgData); + case DRX_CFG_AUD_CARRIER: + return AUDCtrlGetCfgCarrier ( demod, + (pDRXCfgAudCarriers_t)config->cfgData); + case DRX_CFG_AUD_DEVIATION: + return AUDCtrlGetCfgDev ( demod, + (pDRXCfgAudDeviation_t)config->cfgData); + case DRX_CFG_AUD_PRESCALE: + return AUDCtrlGetCfgPrescale ( demod, + (pDRXCfgAudPrescale_t)config->cfgData); + case DRX_CFG_AUD_MIXER: + return AUDCtrlGetCfgMixer ( demod, + (pDRXCfgAudMixer_t)config->cfgData); + case DRX_CFG_AUD_AVSYNC: + return AUDCtrlGetCfgAVSync ( demod, + (pDRXCfgAudAVSync_t)config->cfgData); +#endif + + default: + return (DRX_STS_INVALID_ARG); + } + + return (DRX_STS_OK); +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================= +===== EXPORTED FUNCTIONS ====================================================*/ +/** +* \fn DRXJ_Open() +* \brief Open the demod instance, configure device, configure drxdriver +* \return Status_t Return status. +* +* DRXJ_Open() can be called with a NULL ucode image => no ucode upload. +* This means that DRXJ_Open() must NOT contain SCU commands or, in general, +* rely on SCU or AUD ucode to be present. +* +*/ +DRXStatus_t +DRXJ_Open(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr = NULL; + pDRXJData_t extAttr = NULL; + pDRXCommonAttr_t commonAttr = NULL; + u32_t driverVersion = 0; + DRXUCodeInfo_t ucodeInfo; + DRXCfgMPEGOutput_t cfgMPEGOutput; + + /* Check arguments */ + if (demod -> myExtAttr == NULL ) + { + return ( DRX_STS_INVALID_ARG); + } + + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + + CHK_ERROR(PowerUpDevice(demod)); + commonAttr->currentPowerMode = DRX_POWER_UP; + + /* has to be in front of setIqmAf and setOrxNsuAox */ + CHK_ERROR(GetDeviceCapabilities(demod)); + + /* Soft reset of sys- and osc-clockdomain */ + WR16( devAddr, SIO_CC_SOFT_RST__A, ( SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M ) ); + WR16( devAddr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + CHK_ERROR( DRXBSP_HST_Sleep(1) ); + + /* TODO first make sure that everything keeps working before enabling this */ + /* PowerDownAnalogBlocks() */ + WR16( devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) + |ATV_TOP_STDBY_SIF_STDBY_STANDBY ); + + CHK_ERROR( SetIqmAf( demod, FALSE ) ); + CHK_ERROR( SetOrxNsuAox( demod, FALSE ) ); + + CHK_ERROR(InitHI(demod) ); + + /* disable mpegoutput pins */ + cfgMPEGOutput.enableMPEGOutput = FALSE; + CHK_ERROR( CtrlSetCfgMPEGOutput( demod, &cfgMPEGOutput) ); + /* Stop AUD Inform SetAudio it will need to do all setting */ + CHK_ERROR( PowerDownAud(demod) ); + /* Stop SCU */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); + + /* Upload microcode */ + if ( commonAttr->microcode != NULL ) + { + /* Dirty trick to use common ucode upload & verify, + pretend device is already open */ + commonAttr->isOpened = TRUE; + ucodeInfo.mcData = commonAttr->microcode; + ucodeInfo.mcSize = commonAttr->microcodeSize; + +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + /* Upload microcode without audio part */ + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_UPLOAD, FALSE ) ); +#else + CHK_ERROR( DRX_Ctrl( demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo) ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + if ( commonAttr->verifyMicrocode == TRUE ) + { +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + CHK_ERROR( CtrlUCodeUpload( demod, &ucodeInfo, UCODE_VERIFY, FALSE ) ); +#else + CHK_ERROR( DRX_Ctrl ( demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo) ); +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + } + commonAttr->isOpened = FALSE; + } + + /* Run SCU for a little while to initialize microcode version numbers */ + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + + /* Open tuner instance */ + if ( demod->myTuner != NULL ) + { + demod->myTuner->myCommonAttr->myUserData = (void *)demod; + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + + CHK_ERROR( DRXBSP_TUNER_Open( demod -> myTuner ) ); + + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + commonAttr->tunerMinFreqRF = ((demod->myTuner)->myCommonAttr->minFreqRF); + commonAttr->tunerMaxFreqRF = ((demod->myTuner)->myCommonAttr->maxFreqRF); + } + + /* Initialize scan timeout */ + commonAttr -> scanDemodLockTimeout = DRXJ_SCAN_TIMEOUT; + commonAttr -> scanDesiredLock = DRX_LOCKED; + + /* Initialize default AFE configuartion for QAM */ + if (extAttr->hasLNA) + { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->qamPgaCfg = 140+(11*13); +#endif + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_OFF; + extAttr->vsbPgaCfg = 140+(11*13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamIfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamIfAgcCfg.minOutputLevel = 0; + extAttr->qamIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamIfAgcCfg.speed = 3; + extAttr->qamIfAgcCfg.top = 1297; + extAttr->qamPgaCfg = 140; +#endif + extAttr->vsbIfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbIfAgcCfg.minOutputLevel = 0; + extAttr->vsbIfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbIfAgcCfg.speed = 3; + extAttr->vsbIfAgcCfg.top = 1024; + extAttr->vsbPgaCfg = 140; + } + /* TODO: remove minOutputLevel and maxOutputLevel for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + extAttr->qamRfAgcCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->qamRfAgcCfg.minOutputLevel = 0; + extAttr->qamRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->qamRfAgcCfg.speed = 3; + extAttr->qamRfAgcCfg.top = 9500; + extAttr->qamRfAgcCfg.cutOffCurrent = 4000; + extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B; + extAttr->qamPreSawCfg.reference = 0x07; + extAttr->qamPreSawCfg.usePreSaw = TRUE; +#endif + /* Initialize default AFE configuartion for VSB */ + extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->vsbRfAgcCfg.minOutputLevel = 0; + extAttr->vsbRfAgcCfg.maxOutputLevel = 0x7FFF; + extAttr->vsbRfAgcCfg.speed = 3; + extAttr->vsbRfAgcCfg.top = 9500; + extAttr->vsbRfAgcCfg.cutOffCurrent = 4000; + extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB; + extAttr->vsbPreSawCfg.reference = 0x07; + extAttr->vsbPreSawCfg.usePreSaw = TRUE; + +#ifndef DRXJ_DIGITAL_ONLY + /* Initialize default AFE configuartion for ATV */ + extAttr->atvRfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvRfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvRfAgcCfg.top = 9500; + extAttr->atvRfAgcCfg.cutOffCurrent = 4000; + extAttr->atvRfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.standard = DRX_STANDARD_NTSC; + extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO; + extAttr->atvIfAgcCfg.speed = 3; + extAttr->atvIfAgcCfg.top = 2400; + extAttr->atvPreSawCfg.reference = 0x0007; + extAttr->atvPreSawCfg.usePreSaw = TRUE; + extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC; +#endif + extAttr->standard=DRX_STANDARD_UNKNOWN; + + CHK_ERROR(SmartAntInit(demod)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM + */ + driverVersion = (VERSION_MAJOR/100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR/10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_MAJOR%10); + driverVersion <<= 4; + driverVersion += (VERSION_MINOR%10); + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/1000) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/100) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH/10) % 10; + driverVersion <<= 4; + driverVersion += (VERSION_PATCH%10); + WR16(devAddr, SCU_RAM_DRIVER_VER_HI__A, (u16_t)(driverVersion>>16) ); + WR16(devAddr, SCU_RAM_DRIVER_VER_LO__A, (u16_t)(driverVersion&0xFFFF) ); + + /* refresh the audio data structure with default */ + extAttr->audData = DRXJDefaultAudData_g; + + return ( DRX_STS_OK ); +rw_error: + commonAttr->isOpened = FALSE; + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXJ_Close() +* \brief Close the demod instance, power down the device +* \return Status_t Return status. +* +*/ +DRXStatus_t +DRXJ_Close(pDRXDemodInstance_t demod) +{ + pI2CDeviceAddr_t devAddr =NULL; + pDRXJData_t extAttr =NULL; + pDRXCommonAttr_t commonAttr =NULL; + DRXPowerMode_t powerMode =DRX_POWER_UP; + + commonAttr = (pDRXCommonAttr_t) demod -> myCommonAttr; + devAddr = demod -> myI2CDevAddr; + extAttr = (pDRXJData_t) demod -> myExtAttr; + + /* power up */ + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + + if ( demod->myTuner != NULL ) + { + /* Check if bridge is used */ + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = TRUE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + CHK_ERROR( DRXBSP_TUNER_Close( demod -> myTuner ) ); + if ( commonAttr->tunerPortNr == 1 ) + { + Bool_t bridgeClosed = FALSE; + CHK_ERROR( CtrlI2CBridge( demod, &bridgeClosed ) ); + } + }; + + WR16( devAddr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); + powerMode =DRX_POWER_DOWN; + CHK_ERROR( CtrlPowerMode( demod, &powerMode )); + + return DRX_STS_OK; +rw_error: + return (DRX_STS_ERROR); +} + +/*============================================================================*/ +/** +* \fn DRXJ_Ctrl() +* \brief DRXJ specific control function +* \return Status_t Return status. +*/ +DRXStatus_t +DRXJ_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, + void *ctrlData) +{ + switch ( ctrl ) { + /*======================================================================*/ + case DRX_CTRL_SET_CHANNEL: + { + return CtrlSetChannel ( demod, + (pDRXChannel_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_CHANNEL: + { + return CtrlGetChannel ( demod, + (pDRXChannel_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SIG_QUALITY: + { + return CtrlSigQuality ( demod, + (pDRXSigQuality_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_SIG_STRENGTH: + { + return CtrlSigStrength ( demod, + (pu16_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_CONSTEL: + { + return CtrlConstel ( demod, + (pDRXComplex_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_CFG: + { + return CtrlSetCfg ( demod, + (pDRXCfg_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_CFG: + { + return CtrlGetCfg ( demod, (pDRXCfg_t) ctrlData); + } + break; + /*======================================================================*/ + case DRX_CTRL_I2C_BRIDGE: + { + return CtrlI2CBridge( demod, (pBool_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_LOCK_STATUS: + { + return CtrlLockStatus( demod, (pDRXLockStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_STANDARD: + { + return CtrlSetStandard( demod, (pDRXStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_STANDARD: + { + return CtrlGetStandard( demod, (pDRXStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_POWER_MODE: + { + return CtrlPowerMode( demod, (pDRXPowerMode_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_VERSION: + { + return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_PROBE_DEVICE: + { + return CtrlProbeDevice( demod ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_OOB: + { + return CtrlSetOOB( demod, (pDRXOOB_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_OOB: + { + return CtrlGetOOB( demod, (pDRXOOBStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_SET_UIO_CFG: + { + return CtrlSetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_GET_UIO_CFG: + { + return CtrlGetUIOCfg( demod, (pDRXUIOCfg_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_UIO_READ: + { + return CtrlUIORead( demod, (pDRXUIOData_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_UIO_WRITE: + { + return CtrlUIOWrite( demod, (pDRXUIOData_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_SET_STANDARD: + { + return AUDCtrlSetStandard( demod, (pDRXAudStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_GET_STANDARD: + { + return AUDCtrlGetStandard( demod, (pDRXAudStandard_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_GET_STATUS: + { + return AUDCtrlGetStatus( demod, (pDRXAudStatus_t) ctrlData ); + } + break; + /*======================================================================*/ + case DRX_CTRL_AUD_BEEP: + { + return AUDCtrlBeep( demod, (pDRXAudBeep_t) ctrlData ); + } + break; + + /*======================================================================*/ + case DRX_CTRL_I2C_READWRITE: + { + return CtrlI2CWriteRead( demod, (pDRXI2CData_t) ctrlData ); + } + break; +#ifdef DRXJ_SPLIT_UCODE_UPLOAD + case DRX_CTRL_LOAD_UCODE: + { + return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_UPLOAD, FALSE ); + } + break; + case DRX_CTRL_VERIFY_UCODE: + { + return CtrlUCodeUpload( demod, (pDRXUCodeInfo_t) ctrlData, UCODE_VERIFY, FALSE ); + } + break; +#endif /* DRXJ_SPLIT_UCODE_UPLOAD */ + case DRX_CTRL_VALIDATE_UCODE: + { + return CtrlValidateUCode (demod); + } + break; + default: + return (DRX_STS_FUNC_NOT_AVAILABLE); + } + return (DRX_STS_OK); +} +/* END OF FILE */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h new file mode 100644 index 000000000000..ee7aa6aeac51 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -0,0 +1,732 @@ +/** +* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ +* +* \brief DRXJ specific header file +* +* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +/* +* $(c) 2006-2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ +#ifndef __DRXJ_H__ +#define __DRXJ_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#include "drx_driver.h" +#include "drx_dap_fasi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Check DRX-J specific dap condition */ +/* Multi master mode and short addr format only will not work. + RMW, CRC reset, broadcast and switching back to single master mode + cannot be done with short addr only in multi master mode. */ +#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0)) +#error "Multi master mode and short addressing only is an illegal combination" +*; /* Generate a fatal compiler error to make sure it stops here, + this is necesarry because not all compilers stop after a #error. */ +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ +/*============================================================================*/ +/*============================================================================*/ +/*== code support ============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== SCU cmd if =============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +typedef struct { + u16_t command; /**< Command number */ + u16_t parameterLen; /**< Data length in byte */ + u16_t resultLen; /**< result length in byte */ + u16_t *parameter; /**< General purpous param */ + u16_t *result; /**< General purpous param */ +} DRXJSCUCmd_t, *pDRXJSCUCmd_t; + + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* extra intermediate lock state for VSB,QAM,NTSC */ +#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) + +/* OOB lock states */ +#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ +#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ + +/* Intermediate powermodes for DRXJ */ +#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 +#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 +#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 + +/* supstition for GPIO FNC mux */ +#define APP_O (0x0000) + +/*#define DRX_CTRL_BASE (0x0000)*/ + +#define DRXJ_CTRL_CFG_BASE (0x1000) +typedef enum { + DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, + DRXJ_CFG_AGC_IF, + DRXJ_CFG_AGC_INTERNAL, + DRXJ_CFG_PRE_SAW, + DRXJ_CFG_AFE_GAIN, + DRXJ_CFG_SYMBOL_CLK_OFFSET, + DRXJ_CFG_ACCUM_CR_RS_CW_ERR, + DRXJ_CFG_FEC_MERS_SEQ_COUNT, + DRXJ_CFG_OOB_MISC, + DRXJ_CFG_SMART_ANT, + DRXJ_CFG_OOB_PRE_SAW, + DRXJ_CFG_VSB_MISC, + DRXJ_CFG_RESET_PACKET_ERR, + + /* ATV (FM) */ + DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ + DRXJ_CFG_ATV_MISC, + DRXJ_CFG_ATV_EQU_COEF, + DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ + + DRXJ_CFG_MPEG_OUTPUT_MISC, + DRXJ_CFG_HW_CFG, + DRXJ_CFG_OOB_LO_POW, + + DRXJ_CFG_MAX /* dummy, never to be used */ + +} DRXJCfgType_t, *pDRXJCfgType_t; + +/** +* /struct DRXJCfgSmartAntIO_t +* smart antenna i/o. +*/ +typedef enum DRXJCfgSmartAntIO_t { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT +} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; + +/** +* /struct DRXJCfgSmartAnt_t +* Set smart antenna. +*/ +typedef struct { + DRXJCfgSmartAntIO_t io; + u16_t ctrlData; +} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; + +/** +* /struct DRXJAGCSTATUS_t +* AGC status information from the DRXJ-IQM-AF. +*/ +typedef struct { + u16_t IFAGC; + u16_t RFAGC; + u16_t DigitalAGC; +}DRXJAgcStatus_t, *pDRXJAgcStatus_t; + +/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ + +/** +* /struct DRXJAgcCtrlMode_t +* Available AGCs modes in the DRXJ. +*/ +typedef enum { + DRX_AGC_CTRL_AUTO = 0, + DRX_AGC_CTRL_USER, + DRX_AGC_CTRL_OFF +} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; + +/** +* /struct DRXJCfgAgc_t +* Generic interface for all AGCs present on the DRXJ. +*/ +typedef struct { + DRXStandard_t standard; /* standard for which these settings apply */ + DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ + u16_t outputLevel; /* range dependent on AGC */ + u16_t minOutputLevel; /* range dependent on AGC */ + u16_t maxOutputLevel; /* range dependent on AGC */ + u16_t speed; /* range dependent on AGC */ + u16_t top; /* rf-agc take over point */ + u16_t cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ +}DRXJCfgAgc_t, *pDRXJCfgAgc_t; + +/* DRXJ_CFG_PRE_SAW */ + +/** +* /struct DRXJCfgPreSaw_t +* Interface to configure pre SAW sense. +*/ +typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t reference; /* pre SAW reference value, range 0 .. 31 */ + Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */ +} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; + +/* DRXJ_CFG_AFE_GAIN */ + +/** +* /struct DRXJCfgAfeGain_t +* Interface to configure gain of AFE (LNA + PGA). +*/ +typedef struct { + DRXStandard_t standard; /* standard to which these settings apply */ + u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ +} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; + +/** +* /struct DRXJRSErrors_t +* Available failure information in DRXJ_FEC_RS. +* +* Container for errors that are received in the most recently finished measurment period +* +*/ +typedef struct { + u16_t nrBitErrors; /**< no of pre RS bit errors */ + u16_t nrSymbolErrors; /**< no of pre RS symbol errors */ + u16_t nrPacketErrors; /**< no of pre RS packet errors */ + u16_t nrFailures; /**< no of post RS failures to decode */ + u16_t nrSncParFailCount; /**< no of post RS bit erros */ +} DRXJRSErrors_t, *pDRXJRSErrors_t; + +/** +* /struct DRXJCfgVSBMisc_t +* symbol error rate +*/ +typedef struct{ + u32_t symbError; /**< symbol error rate sps */ +}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; + +/** +* /enum DRXJMpegOutputClockRate_t +* Mpeg output clock rate. +* +*/ +typedef enum { + DRXJ_MPEG_START_WIDTH_1CLKCYC, + DRXJ_MPEG_START_WIDTH_8CLKCYC +} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; + +/** +* /enum DRXJMpegOutputClockRate_t +* Mpeg output clock rate. +* +*/ +typedef enum { + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, + DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K +} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; + +/** +* /struct DRXJCfgMisc_t +* Change TEI bit of MPEG output +* reverse MPEG output bit order +* set MPEG output clock rate +*/ +typedef struct{ + Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */ + Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */ + DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ +}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; + +/** +* /enum DRXJXtalFreq_t +* Supported external crystal reference frequency. +*/ +typedef enum{ + DRXJ_XTAL_FREQ_RSVD, + DRXJ_XTAL_FREQ_27MHZ, + DRXJ_XTAL_FREQ_20P25MHZ, + DRXJ_XTAL_FREQ_4MHZ +}DRXJXtalFreq_t, *pDRXJXtalFreq_t; + +/** +* /enum DRXJXtalFreq_t +* Supported external crystal reference frequency. +*/ +typedef enum{ + DRXJ_I2C_SPEED_400KBPS, + DRXJ_I2C_SPEED_100KBPS +}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; + +/** +* /struct DRXJCfgHwCfg_t +* Get hw configuration, such as crystal reference frequency, I2C speed, etc... +*/ +typedef struct{ + DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */ + DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */ +}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; + +/* + * DRXJ_CFG_ATV_MISC + */ +typedef struct{ + s16_t peakFilter; /* -8 .. 15 */ + u16_t noiseFilter; /* 0 .. 15 */ +}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; + +/* + * DRXJCfgOOBMisc_t + */ +#define DRXJ_OOB_STATE_RESET 0x0 +#define DRXJ_OOB_STATE_AGN_HUNT 0x1 +#define DRXJ_OOB_STATE_DGN_HUNT 0x2 +#define DRXJ_OOB_STATE_AGC_HUNT 0x3 +#define DRXJ_OOB_STATE_FRQ_HUNT 0x4 +#define DRXJ_OOB_STATE_PHA_HUNT 0x8 +#define DRXJ_OOB_STATE_TIM_HUNT 0x10 +#define DRXJ_OOB_STATE_EQU_HUNT 0x20 +#define DRXJ_OOB_STATE_EQT_HUNT 0x30 +#define DRXJ_OOB_STATE_SYNC 0x40 + +typedef struct{ + DRXJAgcStatus_t agc; + Bool_t eqLock; + Bool_t symTimingLock; + Bool_t phaseLock; + Bool_t freqLock; + Bool_t digGainLock; + Bool_t anaGainLock; + u8_t state; +}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; + +/* + * Index of in array of coef + */ +typedef enum { + DRXJ_OOB_LO_POW_MINUS0DB = 0, + DRXJ_OOB_LO_POW_MINUS5DB, + DRXJ_OOB_LO_POW_MINUS10DB, + DRXJ_OOB_LO_POW_MINUS15DB, + DRXJ_OOB_LO_POW_MAX +} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; + +/* + * DRXJ_CFG_ATV_EQU_COEF + */ +typedef struct { + s16_t coef0; /* -256 .. 255 */ + s16_t coef1; /* -256 .. 255 */ + s16_t coef2; /* -256 .. 255 */ + s16_t coef3; /* -256 .. 255 */ +} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; + +/* + * Index of in array of coef + */ +typedef enum { + DRXJ_COEF_IDX_MN = 0, + DRXJ_COEF_IDX_FM , + DRXJ_COEF_IDX_L , + DRXJ_COEF_IDX_LP , + DRXJ_COEF_IDX_BG , + DRXJ_COEF_IDX_DK , + DRXJ_COEF_IDX_I , + DRXJ_COEF_IDX_MAX +} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; + +/* + * DRXJ_CFG_ATV_OUTPUT + */ + +/** +* /enum DRXJAttenuation_t +* Attenuation setting for SIF AGC. +* +*/ +typedef enum { + DRXJ_SIF_ATTENUATION_0DB, + DRXJ_SIF_ATTENUATION_3DB, + DRXJ_SIF_ATTENUATION_6DB, + DRXJ_SIF_ATTENUATION_9DB +} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; + +/** +* /struct DRXJCfgAtvOutput_t +* SIF attenuation setting. +* +*/ +typedef struct { + Bool_t enableCVBSOutput; /* TRUE= enabled */ + Bool_t enableSIFOutput; /* TRUE= enabled */ + DRXJSIFAttenuation_t sifAttenuation; +} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; + +/* + DRXJ_CFG_ATV_AGC_STATUS (get only) +*/ +/* TODO : AFE interface not yet finished, subject to change */ +typedef struct { + u16_t rfAgcGain ; /* 0 .. 877 uA */ + u16_t ifAgcGain ; /* 0 .. 877 uA */ + s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */ + s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */ + u16_t rfAgcLoopGain ; /* 0 .. 7 */ + u16_t ifAgcLoopGain ; /* 0 .. 7 */ + u16_t videoAgcLoopGain; /* 0 .. 7 */ +} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* NONE */ + +/*============================================================================*/ +/*============================================================================*/ + +/*========================================*/ +/** +* /struct DRXJData_t +* DRXJ specific attributes. +* +* Global data container for DRXJ specific data. +* +*/ +typedef struct { + /* device capabilties (determined during DRX_Open()) */ + Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */ + Bool_t hasOOB; /**< TRUE if OOB supported */ + Bool_t hasNTSC; /**< TRUE if NTSC supported */ + Bool_t hasBTSC; /**< TRUE if BTSC supported */ + Bool_t hasSMATX; /**< TRUE if mat_tx is available */ + Bool_t hasSMARX; /**< TRUE if mat_rx is available */ + Bool_t hasGPIO; /**< TRUE if GPIO is available */ + Bool_t hasIRQN; /**< TRUE if IRQN is available */ + /* A1/A2/A... */ + u8_t mfx; /**< metal fix */ + + /* tuner settings */ + Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */ + + /* standard/channel settings */ + DRXStandard_t standard; /**< current standard information */ + DRXConstellation_t constellation; /**< current constellation */ + DRXFrequency_t frequency; /**< center signal frequency in KHz */ + DRXBandwidth_t currBandwidth; /**< current channel bandwidth */ + DRXMirror_t mirror; /**< current channel mirror */ + + /* signal quality information */ + u32_t fecBitsDesired; /**< BER accounting period */ + u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ + u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */ + u16_t qamVdPeriod; /**< Viterbi Measurement period */ + u16_t fecRsPlen; /**< defines RS BER measurement period */ + u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */ + u16_t fecRsPeriod; /**< ReedSolomon Measurement period */ + Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ + u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */ + + /* HI configuration */ + u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */ + u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */ + u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */ + u16_t HICfgCtrl; /**< HI Configure() parameter 5 */ + u16_t HICfgTransmit; /**< HI Configure() parameter 6 */ + + /* UIO configuartion */ + DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */ + DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */ + DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ + DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ + + /* IQM fs frequecy shift and inversion */ + u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */ + Bool_t posImage; /**< Ture: positive image */ + /* IQM RC frequecy shift */ + u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */ + + /* ATV configuartion */ + u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */ + s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ + s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ + s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ + s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ + Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */ + s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ + u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ + Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */ + Bool_t enableSIFOutput; /**< flag SIF ouput enable */ + DRXJSIFAttenuation_t + sifAttenuation; /**< current SIF att setting */ + /* Agc configuration for QAM and VSB */ + DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ + DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ + DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ + DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ + + /* PGA gain configuration for QAM and VSB */ + u16_t qamPgaCfg; /**< qam PGA config */ + u16_t vsbPgaCfg; /**< vsb PGA config */ + + /* Pre SAW configuration for QAM and VSB */ + DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */ + DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */ + + /* Version information */ + char vText[2][12]; /**< allocated text versions */ + DRXVersion_t vVersion[2]; /**< allocated versions structs */ + DRXVersionList_t vListElements[2]; /**< allocated version list */ + + /* smart antenna configuration */ + Bool_t smartAntInverted; + + /* Tracking filter setting for OOB */ + u16_t oobTrkFilterCfg[8]; + Bool_t oobPowerOn; + + /* MPEG static bitrate setting */ + u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */ + Bool_t disableTEIhandling; /**< MPEG TS TEI handling */ + Bool_t bitReverseMpegOutout; /**< MPEG output bit order */ + DRXJMpegOutputClockRate_t + mpegOutputClockRate; /**< MPEG output clock rate */ + DRXJMpegStartWidth_t + mpegStartWidth; /**< MPEG Start width */ + + /* Pre SAW & Agc configuration for ATV */ + DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */ + DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ + DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ + u16_t atvPgaCfg; /**< atv pga config */ + + u32_t currSymbolRate; + + /* pin-safe mode */ + Bool_t pdrSafeMode; /**< PDR safe mode activated */ + u16_t pdrSafeRestoreValGpio; + u16_t pdrSafeRestoreValVSync; + u16_t pdrSafeRestoreValSmaRx; + u16_t pdrSafeRestoreValSmaTx; + + /* OOB pre-saw value */ + u16_t oobPreSaw; + DRXJCfgOobLoPower_t oobLoPow; + + DRXAudData_t audData; /**< audio storage */ + +} DRXJData_t, *pDRXJData_t; + +/*------------------------------------------------------------------------- +Access MACROS +-------------------------------------------------------------------------*/ +/** +* \brief Compilable references to attributes +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Can be used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRXJ_ATTR_BTSC_DETECT( d ) \ + (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) + +/** +* \brief Actual access macros +* \param d pointer to demod instance +* \param x value to set or to get +* +* SET macros must be used to set the value of an attribute. +* GET macros must be used to retrieve the value of an attribute. +* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be +* substituted by "direct-access-inline-code" or a function call. +* +*/ +#define DRXJ_GET_BTSC_DETECT( d, x ) \ + do { \ + (x) = DRXJ_ATTR_BTSC_DETECT(( d ); \ + } while(0) + +#define DRXJ_SET_BTSC_DETECT( d, x ) \ + do { \ + DRXJ_ATTR_BTSC_DETECT( d ) = (x); \ + } while(0) + + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/** +* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For NTSC standard. +* NTSC channels are listed by their picture carrier frequency (Fpc). +* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the centre frequency of the channel: +* +* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750)) + +/** +* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - BG standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375)) + +/** +* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775)) + +/** +* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - LP standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +*/ +#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255)) + +/** +* \def DRXJ_FM_CARRIER_FREQ_OFFSET +* \brief Offset from sound carrier to centre frequency in kHz, in RF domain +* +* For FM standard. +* FM channels are listed by their sound carrier frequency (Fsc). +* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as +* input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the Ffm frequency of the channel. +* +* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000)) + +/* Revision types -------------------------------------------------------*/ + +#define DRXJ_TYPE_ID (0x3946000DUL) + +/* Macros ---------------------------------------------------------------*/ + +/* Convert OOB lock status to string */ +#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ + ( x == DRX_NEVER_LOCK ) ? "Never" : \ + ( x == DRX_NOT_LOCKED ) ? "No" : \ + ( x == DRX_LOCKED ) ? "Locked" : \ + ( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \ + ( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \ + "(Invalid)" ) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- +Exported FUNCTIONS +-------------------------------------------------------------------------*/ + +extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod); +extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod); +extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod, + DRXCtrlIndex_t ctrl, + void *ctrlData); + +/*------------------------------------------------------------------------- +Exported GLOBAL VARIABLES +-------------------------------------------------------------------------*/ +extern DRXAccessFunc_t drxDapDRXJFunct_g; +extern DRXDemodFunc_t DRXJFunctions_g; +extern DRXJData_t DRXJData_g; +extern I2CDeviceAddr_t DRXJDefaultAddr_g; +extern DRXCommonAttr_t DRXJDefaultCommAttr_g; +extern DRXDemodInstance_t DRXJDefaultDemod_g; + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h new file mode 100644 index 000000000000..941aa14ca06e --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -0,0 +1,15350 @@ +/* + *********************************************************************************************************************** + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drxj_map.h + * Generated on: Mon Jan 18 12:09:24 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: reg_map + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - + * + * $(c) 2010 Trident Microsystems, Inc. - All rights reserved. + * + * This software and related documentation (the 'Software') are intellectual property owned by Trident and are + * copyright of Trident, unless specifically noted otherwise. + * + * Any use of the Software is permitted only pursuant to the terms of the license agreement, if any, which accompanies, + * is included with or applicable to the Software ('License Agreement') or upon express written consent of Trident. Any + * copying, reproduction or redistribution of the Software in whole or in part by any means not in accordance with the + * License Agreement or as agreed in writing by Trident is expressly prohibited. + * + * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE LICENSE AGREEMENT. EXCEPT AS WARRANTED IN + * THE LICENSE AGREEMENT THE SOFTWARE IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS + * WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE, QUIT ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY OR OTHER + * RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO USE THE SOFTWARE. + * + * IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, SPECIAL OR OTHER DAMAGES + * WHATSOEVER INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF + * BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE INABILITY TO USE THE SOFTWARE, + * EVEN IF TRIDENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM + * TRIDENT'S NEGLIGENCE. $ + * + *********************************************************************************************************************** + */ + +#ifndef __DRXJ_MAP__H__ +#define __DRXJ_MAP__H__ INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _REGISTERTABLE_ +#include +extern RegisterTable_t drxj_map[]; +extern RegisterTableInfo_t drxj_map_info[]; +#endif + + + + + + +#define ATV_COMM_EXEC__A 0xC00000 +#define ATV_COMM_EXEC__W 2 +#define ATV_COMM_EXEC__M 0x3 +#define ATV_COMM_EXEC__PRE 0x0 +#define ATV_COMM_EXEC_STOP 0x0 +#define ATV_COMM_EXEC_ACTIVE 0x1 +#define ATV_COMM_EXEC_HOLD 0x2 + +#define ATV_COMM_STATE__A 0xC00001 +#define ATV_COMM_STATE__W 16 +#define ATV_COMM_STATE__M 0xFFFF +#define ATV_COMM_STATE__PRE 0x0 +#define ATV_COMM_MB__A 0xC00002 +#define ATV_COMM_MB__W 16 +#define ATV_COMM_MB__M 0xFFFF +#define ATV_COMM_MB__PRE 0x0 +#define ATV_COMM_INT_REQ__A 0xC00003 +#define ATV_COMM_INT_REQ__W 16 +#define ATV_COMM_INT_REQ__M 0xFFFF +#define ATV_COMM_INT_REQ__PRE 0x0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0 + +#define ATV_COMM_INT_STA__A 0xC00005 +#define ATV_COMM_INT_STA__W 16 +#define ATV_COMM_INT_STA__M 0xFFFF +#define ATV_COMM_INT_STA__PRE 0x0 +#define ATV_COMM_INT_MSK__A 0xC00006 +#define ATV_COMM_INT_MSK__W 16 +#define ATV_COMM_INT_MSK__M 0xFFFF +#define ATV_COMM_INT_MSK__PRE 0x0 +#define ATV_COMM_INT_STM__A 0xC00007 +#define ATV_COMM_INT_STM__W 16 +#define ATV_COMM_INT_STM__M 0xFFFF +#define ATV_COMM_INT_STM__PRE 0x0 + +#define ATV_COMM_KEY__A 0xC0000F +#define ATV_COMM_KEY__W 16 +#define ATV_COMM_KEY__M 0xFFFF +#define ATV_COMM_KEY__PRE 0x0 +#define ATV_COMM_KEY_KEY 0xFABA +#define ATV_COMM_KEY_MIN 0x0 +#define ATV_COMM_KEY_MAX 0xFFFF + + + +#define ATV_TOP_COMM_EXEC__A 0xC10000 +#define ATV_TOP_COMM_EXEC__W 2 +#define ATV_TOP_COMM_EXEC__M 0x3 +#define ATV_TOP_COMM_EXEC__PRE 0x0 +#define ATV_TOP_COMM_EXEC_STOP 0x0 +#define ATV_TOP_COMM_EXEC_ACTIVE 0x1 +#define ATV_TOP_COMM_EXEC_HOLD 0x2 + +#define ATV_TOP_COMM_STATE__A 0xC10001 +#define ATV_TOP_COMM_STATE__W 16 +#define ATV_TOP_COMM_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE__PRE 0x0 +#define ATV_TOP_COMM_STATE_STATE__B 0 +#define ATV_TOP_COMM_STATE_STATE__W 16 +#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE_STATE__PRE 0x0 + +#define ATV_TOP_COMM_MB__A 0xC10002 +#define ATV_TOP_COMM_MB__W 16 +#define ATV_TOP_COMM_MB__M 0xFFFF +#define ATV_TOP_COMM_MB__PRE 0x0 +#define ATV_TOP_COMM_MB_CTL__B 0 +#define ATV_TOP_COMM_MB_CTL__W 1 +#define ATV_TOP_COMM_MB_CTL__M 0x1 +#define ATV_TOP_COMM_MB_CTL__PRE 0x0 +#define ATV_TOP_COMM_MB_OBS__B 1 +#define ATV_TOP_COMM_MB_OBS__W 1 +#define ATV_TOP_COMM_MB_OBS__M 0x2 +#define ATV_TOP_COMM_MB_OBS__PRE 0x0 + +#define ATV_TOP_COMM_MB_MUX_CTRL__B 2 +#define ATV_TOP_COMM_MB_MUX_CTRL__W 4 +#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4 +#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8 +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10 +#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C +#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20 + +#define ATV_TOP_COMM_MB_MUX_OBS__B 6 +#define ATV_TOP_COMM_MB_MUX_OBS__W 4 +#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40 +#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100 +#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 +#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 + + +#define ATV_TOP_COMM_INT_REQ__A 0xC10003 +#define ATV_TOP_COMM_INT_REQ__W 16 +#define ATV_TOP_COMM_INT_REQ__M 0xFFFF +#define ATV_TOP_COMM_INT_REQ__PRE 0x0 +#define ATV_TOP_COMM_INT_STA__A 0xC10005 +#define ATV_TOP_COMM_INT_STA__W 16 +#define ATV_TOP_COMM_INT_STA__M 0xFFFF +#define ATV_TOP_COMM_INT_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2 +#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK__A 0xC10006 +#define ATV_TOP_COMM_INT_MSK__W 16 +#define ATV_TOP_COMM_INT_MSK__M 0xFFFF +#define ATV_TOP_COMM_INT_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM__A 0xC10007 +#define ATV_TOP_COMM_INT_STM__W 16 +#define ATV_TOP_COMM_INT_STM__M 0xFFFF +#define ATV_TOP_COMM_INT_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2 +#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0 + +#define ATV_TOP_COMM_KEY__A 0xC1000F +#define ATV_TOP_COMM_KEY__W 16 +#define ATV_TOP_COMM_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY__PRE 0x0 + +#define ATV_TOP_COMM_KEY_KEY__B 0 +#define ATV_TOP_COMM_KEY_KEY__W 16 +#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY_KEY__PRE 0x0 +#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA +#define ATV_TOP_COMM_KEY_KEY_MIN 0x0 +#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF + + +#define ATV_TOP_CR_AMP_TH__A 0xC10010 +#define ATV_TOP_CR_AMP_TH__W 8 +#define ATV_TOP_CR_AMP_TH__M 0xFF +#define ATV_TOP_CR_AMP_TH__PRE 0x8 +#define ATV_TOP_CR_AMP_TH_MN 0x8 + +#define ATV_TOP_CR_CONT__A 0xC10011 +#define ATV_TOP_CR_CONT__W 9 +#define ATV_TOP_CR_CONT__M 0x1FF +#define ATV_TOP_CR_CONT__PRE 0x9C + +#define ATV_TOP_CR_CONT_CR_P__B 0 +#define ATV_TOP_CR_CONT_CR_P__W 3 +#define ATV_TOP_CR_CONT_CR_P__M 0x7 +#define ATV_TOP_CR_CONT_CR_P__PRE 0x4 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_D__B 3 +#define ATV_TOP_CR_CONT_CR_D__W 3 +#define ATV_TOP_CR_CONT_CR_D__M 0x38 +#define ATV_TOP_CR_CONT_CR_D__PRE 0x18 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_I__B 6 +#define ATV_TOP_CR_CONT_CR_I__W 3 +#define ATV_TOP_CR_CONT_CR_I__M 0x1C0 +#define ATV_TOP_CR_CONT_CR_I__PRE 0x80 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 + + +#define ATV_TOP_CR_OVM_TH__A 0xC10012 +#define ATV_TOP_CR_OVM_TH__W 8 +#define ATV_TOP_CR_OVM_TH__M 0xFF +#define ATV_TOP_CR_OVM_TH__PRE 0xA0 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 + + +#define ATV_TOP_NOISE_TH__A 0xC10013 +#define ATV_TOP_NOISE_TH__W 4 +#define ATV_TOP_NOISE_TH__M 0xF +#define ATV_TOP_NOISE_TH__PRE 0x8 +#define ATV_TOP_NOISE_TH_MN 0x8 + +#define ATV_TOP_EQU0__A 0xC10014 +#define ATV_TOP_EQU0__W 9 +#define ATV_TOP_EQU0__M 0x1FF +#define ATV_TOP_EQU0__PRE 0x1FB + +#define ATV_TOP_EQU0_EQU_C0__B 0 +#define ATV_TOP_EQU0_EQU_C0__W 9 +#define ATV_TOP_EQU0_EQU_C0__M 0x1FF +#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB +#define ATV_TOP_EQU0_EQU_C0_MN 0xFB + +#define ATV_TOP_EQU1__A 0xC10015 +#define ATV_TOP_EQU1__W 9 +#define ATV_TOP_EQU1__M 0x1FF +#define ATV_TOP_EQU1__PRE 0x1CE + +#define ATV_TOP_EQU1_EQU_C1__B 0 +#define ATV_TOP_EQU1_EQU_C1__W 9 +#define ATV_TOP_EQU1_EQU_C1__M 0x1FF +#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE +#define ATV_TOP_EQU1_EQU_C1_MN 0xCE + +#define ATV_TOP_EQU2__A 0xC10016 +#define ATV_TOP_EQU2__W 9 +#define ATV_TOP_EQU2__M 0x1FF +#define ATV_TOP_EQU2__PRE 0xD2 + +#define ATV_TOP_EQU2_EQU_C2__B 0 +#define ATV_TOP_EQU2_EQU_C2__W 9 +#define ATV_TOP_EQU2_EQU_C2__M 0x1FF +#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2 +#define ATV_TOP_EQU2_EQU_C2_MN 0xD2 + +#define ATV_TOP_EQU3__A 0xC10017 +#define ATV_TOP_EQU3__W 9 +#define ATV_TOP_EQU3__M 0x1FF +#define ATV_TOP_EQU3__PRE 0x160 + +#define ATV_TOP_EQU3_EQU_C3__B 0 +#define ATV_TOP_EQU3_EQU_C3__W 9 +#define ATV_TOP_EQU3_EQU_C3__M 0x1FF +#define ATV_TOP_EQU3_EQU_C3__PRE 0x160 +#define ATV_TOP_EQU3_EQU_C3_MN 0x60 + + +#define ATV_TOP_ROT_MODE__A 0xC10018 +#define ATV_TOP_ROT_MODE__W 1 +#define ATV_TOP_ROT_MODE__M 0x1 +#define ATV_TOP_ROT_MODE__PRE 0x0 +#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0 +#define ATV_TOP_ROT_MODE_ALWAYS 0x1 + +#define ATV_TOP_MOD_CONTROL__A 0xC10019 +#define ATV_TOP_MOD_CONTROL__W 12 +#define ATV_TOP_MOD_CONTROL__M 0xFFF +#define ATV_TOP_MOD_CONTROL__PRE 0x5B1 + +#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 +#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 +#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7 +#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 +#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78 +#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80 + +#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 +#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00 +#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0 + +#define ATV_TOP_STD__A 0xC1001A +#define ATV_TOP_STD__W 2 +#define ATV_TOP_STD__M 0x3 +#define ATV_TOP_STD__PRE 0x0 + +#define ATV_TOP_STD_MODE__B 0 +#define ATV_TOP_STD_MODE__W 1 +#define ATV_TOP_STD_MODE__M 0x1 +#define ATV_TOP_STD_MODE__PRE 0x0 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 + +#define ATV_TOP_STD_VID_POL__B 1 +#define ATV_TOP_STD_VID_POL__W 1 +#define ATV_TOP_STD_VID_POL__M 0x2 +#define ATV_TOP_STD_VID_POL__PRE 0x0 +#define ATV_TOP_STD_VID_POL_NEG 0x0 +#define ATV_TOP_STD_VID_POL_POS 0x2 + + +#define ATV_TOP_VID_AMP__A 0xC1001B +#define ATV_TOP_VID_AMP__W 12 +#define ATV_TOP_VID_AMP__M 0xFFF +#define ATV_TOP_VID_AMP__PRE 0x380 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 + + +#define ATV_TOP_VID_PEAK__A 0xC1001C +#define ATV_TOP_VID_PEAK__W 5 +#define ATV_TOP_VID_PEAK__M 0x1F +#define ATV_TOP_VID_PEAK__PRE 0x1 + +#define ATV_TOP_FAGC_TH__A 0xC1001D +#define ATV_TOP_FAGC_TH__W 11 +#define ATV_TOP_FAGC_TH__M 0x7FF +#define ATV_TOP_FAGC_TH__PRE 0x2B2 +#define ATV_TOP_FAGC_TH_MN 0x2B2 + + +#define ATV_TOP_SYNC_SLICE__A 0xC1001E +#define ATV_TOP_SYNC_SLICE__W 11 +#define ATV_TOP_SYNC_SLICE__M 0x7FF +#define ATV_TOP_SYNC_SLICE__PRE 0x243 +#define ATV_TOP_SYNC_SLICE_MN 0x243 + + +#define ATV_TOP_SIF_GAIN__A 0xC1001F +#define ATV_TOP_SIF_GAIN__W 11 +#define ATV_TOP_SIF_GAIN__M 0x7FF +#define ATV_TOP_SIF_GAIN__PRE 0x0 + +#define ATV_TOP_SIF_TP__A 0xC10020 +#define ATV_TOP_SIF_TP__W 6 +#define ATV_TOP_SIF_TP__M 0x3F +#define ATV_TOP_SIF_TP__PRE 0x0 + +#define ATV_TOP_MOD_ACCU__A 0xC10021 +#define ATV_TOP_MOD_ACCU__W 10 +#define ATV_TOP_MOD_ACCU__M 0x3FF +#define ATV_TOP_MOD_ACCU__PRE 0x0 + +#define ATV_TOP_CR_FREQ__A 0xC10022 +#define ATV_TOP_CR_FREQ__W 8 +#define ATV_TOP_CR_FREQ__M 0xFF +#define ATV_TOP_CR_FREQ__PRE 0x0 + +#define ATV_TOP_CR_PHAD__A 0xC10023 +#define ATV_TOP_CR_PHAD__W 12 +#define ATV_TOP_CR_PHAD__M 0xFFF +#define ATV_TOP_CR_PHAD__PRE 0x0 + +#define ATV_TOP_AF_SIF_ATT__A 0xC10024 +#define ATV_TOP_AF_SIF_ATT__W 2 +#define ATV_TOP_AF_SIF_ATT__M 0x3 +#define ATV_TOP_AF_SIF_ATT__PRE 0x0 +#define ATV_TOP_AF_SIF_ATT_0DB 0x0 +#define ATV_TOP_AF_SIF_ATT_M3DB 0x1 +#define ATV_TOP_AF_SIF_ATT_M6DB 0x2 +#define ATV_TOP_AF_SIF_ATT_M9DB 0x3 + +#define ATV_TOP_STDBY__A 0xC10025 +#define ATV_TOP_STDBY__W 2 +#define ATV_TOP_STDBY__M 0x3 +#define ATV_TOP_STDBY__PRE 0x1 + +#define ATV_TOP_STDBY_SIF_STDBY__B 0 +#define ATV_TOP_STDBY_SIF_STDBY__W 1 +#define ATV_TOP_STDBY_SIF_STDBY__M 0x1 +#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1 +#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0 +#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1 + +#define ATV_TOP_STDBY_CVBS_STDBY__B 1 +#define ATV_TOP_STDBY_CVBS_STDBY__W 1 +#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 + + +#define ATV_TOP_OVERRIDE_SFR__A 0xC10026 +#define ATV_TOP_OVERRIDE_SFR__W 1 +#define ATV_TOP_OVERRIDE_SFR__M 0x1 +#define ATV_TOP_OVERRIDE_SFR__PRE 0x0 +#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 +#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 + + +#define ATV_TOP_SFR_VID_GAIN__A 0xC10027 +#define ATV_TOP_SFR_VID_GAIN__W 16 +#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF +#define ATV_TOP_SFR_VID_GAIN__PRE 0x0 + +#define ATV_TOP_SFR_AGC_RES__A 0xC10028 +#define ATV_TOP_SFR_AGC_RES__W 5 +#define ATV_TOP_SFR_AGC_RES__M 0x1F +#define ATV_TOP_SFR_AGC_RES__PRE 0x0 + +#define ATV_TOP_OVM_COMP__A 0xC10029 +#define ATV_TOP_OVM_COMP__W 12 +#define ATV_TOP_OVM_COMP__M 0xFFF +#define ATV_TOP_OVM_COMP__PRE 0x0 +#define ATV_TOP_OUT_CONF__A 0xC1002A +#define ATV_TOP_OUT_CONF__W 5 +#define ATV_TOP_OUT_CONF__M 0x1F +#define ATV_TOP_OUT_CONF__PRE 0x0 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1 + +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2 + +#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8 + +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 + + + +#define ATV_AFT_COMM_EXEC__A 0xFF0000 +#define ATV_AFT_COMM_EXEC__W 2 +#define ATV_AFT_COMM_EXEC__M 0x3 +#define ATV_AFT_COMM_EXEC__PRE 0x0 +#define ATV_AFT_COMM_EXEC_STOP 0x0 +#define ATV_AFT_COMM_EXEC_ACTIVE 0x1 +#define ATV_AFT_COMM_EXEC_HOLD 0x2 + + +#define ATV_AFT_TST__A 0xFF0010 +#define ATV_AFT_TST__W 4 +#define ATV_AFT_TST__M 0xF +#define ATV_AFT_TST__PRE 0x0 + + + + + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC_ACTIVE 0x1 + +#define AUD_COMM_MB__A 0x1000002 +#define AUD_COMM_MB__W 16 +#define AUD_COMM_MB__M 0xFFFF +#define AUD_COMM_MB__PRE 0x0 + + + +#define AUD_TOP_COMM_EXEC__A 0x1010000 +#define AUD_TOP_COMM_EXEC__W 2 +#define AUD_TOP_COMM_EXEC__M 0x3 +#define AUD_TOP_COMM_EXEC__PRE 0x0 +#define AUD_TOP_COMM_EXEC_STOP 0x0 +#define AUD_TOP_COMM_EXEC_ACTIVE 0x1 + +#define AUD_TOP_COMM_MB__A 0x1010002 +#define AUD_TOP_COMM_MB__W 16 +#define AUD_TOP_COMM_MB__M 0xFFFF +#define AUD_TOP_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_MB_CTL__B 0 +#define AUD_TOP_COMM_MB_CTL__W 1 +#define AUD_TOP_COMM_MB_CTL__M 0x1 +#define AUD_TOP_COMM_MB_CTL__PRE 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1 + +#define AUD_TOP_COMM_MB_OBS__B 1 +#define AUD_TOP_COMM_MB_OBS__W 1 +#define AUD_TOP_COMM_MB_OBS__M 0x2 +#define AUD_TOP_COMM_MB_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define AUD_TOP_COMM_MB_MUX_CTRL__B 2 +#define AUD_TOP_COMM_MB_MUX_CTRL__W 4 +#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4 +#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8 +#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10 + +#define AUD_TOP_COMM_MB_MUX_OBS__B 6 +#define AUD_TOP_COMM_MB_MUX_OBS__W 4 +#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40 +#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80 +#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100 + +#define AUD_TOP_TR_MDE__A 0x1010010 +#define AUD_TOP_TR_MDE__W 5 +#define AUD_TOP_TR_MDE__M 0x1F +#define AUD_TOP_TR_MDE__PRE 0x18 + +#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 +#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 +#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF +#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8 + +#define AUD_TOP_TR_MDE_RD_LOCK__B 4 +#define AUD_TOP_TR_MDE_RD_LOCK__W 1 +#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0 +#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10 + +#define AUD_TOP_TR_CTR__A 0x1010011 +#define AUD_TOP_TR_CTR__W 4 +#define AUD_TOP_TR_CTR__M 0xF +#define AUD_TOP_TR_CTR__PRE 0x0 + +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1 + +#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2 + +#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 +#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 +#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4 +#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4 + +#define AUD_TOP_TR_CTR_FIFO_FULL__B 3 +#define AUD_TOP_TR_CTR_FIFO_FULL__W 1 +#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8 +#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8 + +#define AUD_TOP_TR_RD_REG__A 0x1010012 +#define AUD_TOP_TR_RD_REG__W 16 +#define AUD_TOP_TR_RD_REG__M 0xFFFF +#define AUD_TOP_TR_RD_REG__PRE 0x0 + +#define AUD_TOP_TR_RD_REG_RESULT__B 0 +#define AUD_TOP_TR_RD_REG_RESULT__W 16 +#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF +#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0 + +#define AUD_TOP_TR_TIMER__A 0x1010013 +#define AUD_TOP_TR_TIMER__W 16 +#define AUD_TOP_TR_TIMER__M 0xFFFF +#define AUD_TOP_TR_TIMER__PRE 0x0 + +#define AUD_TOP_TR_TIMER_CYCLES__B 0 +#define AUD_TOP_TR_TIMER_CYCLES__W 16 +#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF +#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 + + +#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 +#define AUD_TOP_DEMOD_TBO_SEL__W 5 +#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F +#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 + + + +#define AUD_DEM_WR_MODUS__A 0x1030030 +#define AUD_DEM_WR_MODUS__W 16 +#define AUD_DEM_WR_MODUS__M 0xFFFF +#define AUD_DEM_WR_MODUS__PRE 0x0 + +#define AUD_DEM_WR_MODUS_MOD_ASS__B 0 +#define AUD_DEM_WR_MODUS_MOD_ASS__W 1 +#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1 +#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1 + +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2 + +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4 + +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100 + +#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 +#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200 +#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200 + +#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 +#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400 +#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400 + +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800 + +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000 + +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000 + +#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 +#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 +#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000 +#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000 + +#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020 +#define AUD_DEM_WR_STANDARD_SEL__W 16 +#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF +#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0 + +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 + + + +#define AUD_DEM_RD_STANDARD_RES__A 0x102007E +#define AUD_DEM_RD_STANDARD_RES__W 16 +#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES__PRE 0x0 + +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF + +#define AUD_DEM_RD_STATUS__A 0x1020200 +#define AUD_DEM_RD_STATUS__W 16 +#define AUD_DEM_RD_STATUS__M 0xFFFF +#define AUD_DEM_RD_STATUS__PRE 0x0 + +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1 + +#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2 + +#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4 + +#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 +#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 +#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20 +#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20 + +#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 +#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 +#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40 +#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40 + +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80 + +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100 + +#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 +#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 +#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200 +#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200 + +#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F +#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0 + +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF + + +#define AUD_DEM_RD_RDS_DATA__A 0x1020210 +#define AUD_DEM_RD_RDS_DATA__W 12 +#define AUD_DEM_RD_RDS_DATA__M 0xFFF +#define AUD_DEM_RD_RDS_DATA__PRE 0x0 + + + +#define AUD_DSP_WR_FM_PRESC__A 0x105000E +#define AUD_DSP_WR_FM_PRESC__W 16 +#define AUD_DSP_WR_FM_PRESC__M 0xFFFF +#define AUD_DSP_WR_FM_PRESC__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 + + +#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 +#define AUD_DSP_WR_NICAM_PRESC__W 16 +#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF +#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0 +#define AUD_DSP_WR_VOLUME__A 0x1050000 +#define AUD_DSP_WR_VOLUME__W 16 +#define AUD_DSP_WR_VOLUME__M 0xFFFF +#define AUD_DSP_WR_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038 +#define AUD_DSP_WR_SRC_I2S_MATR__W 16 +#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF +#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400 + +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30 + +#define AUD_DSP_WR_AVC__A 0x1050029 +#define AUD_DSP_WR_AVC__W 16 +#define AUD_DSP_WR_AVC__M 0xFFFF +#define AUD_DSP_WR_AVC__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_ON__B 14 +#define AUD_DSP_WR_AVC_AVC_ON__W 2 +#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000 +#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000 + +#define AUD_DSP_WR_AVC_AVC_DECAY__B 8 +#define AUD_DSP_WR_AVC_AVC_DECAY__W 4 +#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00 +#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800 +#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400 +#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200 +#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100 + +#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8 + +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3 + +#define AUD_DSP_WR_QPEAK__A 0x105000C +#define AUD_DSP_WR_QPEAK__W 16 +#define AUD_DSP_WR_QPEAK__M 0xFFFF +#define AUD_DSP_WR_QPEAK__PRE 0x0 + +#define AUD_DSP_WR_QPEAK_SRC_QP__B 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__W 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00 +#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400 + +#define AUD_DSP_WR_QPEAK_MAT_QP__B 0 +#define AUD_DSP_WR_QPEAK_MAT_QP__W 8 +#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF +#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10 +#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20 +#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30 + + + + +#define AUD_DSP_RD_QPEAK_L__A 0x1040019 +#define AUD_DSP_RD_QPEAK_L__W 16 +#define AUD_DSP_RD_QPEAK_L__M 0xFFFF +#define AUD_DSP_RD_QPEAK_L__PRE 0x0 + +#define AUD_DSP_RD_QPEAK_R__A 0x104001A +#define AUD_DSP_RD_QPEAK_R__W 16 +#define AUD_DSP_RD_QPEAK_R__M 0xFFFF +#define AUD_DSP_RD_QPEAK_R__PRE 0x0 + + + +#define AUD_DSP_WR_BEEPER__A 0x1050014 +#define AUD_DSP_WR_BEEPER__W 16 +#define AUD_DSP_WR_BEEPER__M 0xFFFF +#define AUD_DSP_WR_BEEPER__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F00 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0 + + + +#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050 +#define AUD_DEM_WR_I2S_CONFIG2__W 16 +#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF +#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x40 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x40 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x10 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x10 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x8 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x8 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x4 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1 + + + +#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A +#define AUD_DSP_WR_I2S_OUT_FS__W 16 +#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x0 + +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC__A 0x105002B +#define AUD_DSP_WR_AV_SYNC__W 16 +#define AUD_DSP_WR_AV_SYNC__M 0xFFFF +#define AUD_DSP_WR_AV_SYNC__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15 +#define AUD_DSP_WR_AV_SYNC_AV_ON__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x8000 +#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x8000 + +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x4000 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x4000 + +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x3 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x1 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3 + + + +#define AUD_DSP_RD_STATUS2__A 0x104007B +#define AUD_DSP_RD_STATUS2__W 16 +#define AUD_DSP_RD_STATUS2__M 0xFFFF +#define AUD_DSP_RD_STATUS2__PRE 0x0 + +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x8000 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x8000 + +#define AUD_DSP_RD_XDFP_FW__A 0x104001D +#define AUD_DSP_RD_XDFP_FW__W 16 +#define AUD_DSP_RD_XDFP_FW__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW__PRE 0x344 + +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x344 + +#define AUD_DSP_RD_XFP_FW__A 0x10404B8 +#define AUD_DSP_RD_XFP_FW__W 16 +#define AUD_DSP_RD_XFP_FW__M 0xFFFF +#define AUD_DSP_RD_XFP_FW__PRE 0x42 + +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42 + + + + +#define AUD_DEM_WR_DCO_B_HI__A 0x103009B +#define AUD_DEM_WR_DCO_B_HI__W 16 +#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_B_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_B_LO__A 0x1030093 +#define AUD_DEM_WR_DCO_B_LO__W 16 +#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_B_LO__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB +#define AUD_DEM_WR_DCO_A_HI__W 16 +#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_A_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_LO__A 0x10300A3 +#define AUD_DEM_WR_DCO_A_LO__W 16 +#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_A_LO__PRE 0x0 +#define AUD_DEM_WR_NICAM_THRSHLD__A 0x1030021 +#define AUD_DEM_WR_NICAM_THRSHLD__W 16 +#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC + +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC + +#define AUD_DEM_WR_A2_THRSHLD__A 0x1030022 +#define AUD_DEM_WR_A2_THRSHLD__W 16 +#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_A2_THRSHLD__PRE 0x190 + +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x190 + +#define AUD_DEM_WR_BTSC_THRSHLD__A 0x1030023 +#define AUD_DEM_WR_BTSC_THRSHLD__W 16 +#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC + +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC + +#define AUD_DEM_WR_CM_A_THRSHLD__A 0x1030024 +#define AUD_DEM_WR_CM_A_THRSHLD__W 16 +#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD__A 0x1030025 +#define AUD_DEM_WR_CM_B_THRSHLD__W 16 +#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A + + + +#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023 +#define AUD_DEM_RD_NIC_C_AD_BITS__W 16 +#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF +#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x1 + +#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E +#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE0 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x1020038 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB__A 0x1020038 +#define AUD_DEM_RD_NIC_CIB__W 16 +#define AUD_DEM_RD_NIC_CIB__M 0xFFFF +#define AUD_DEM_RD_NIC_CIB__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB2__B 0 +#define AUD_DEM_RD_NIC_CIB_CIB2__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x1 +#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB1__B 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2 +#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x1020057 +#define AUD_DEM_RD_NIC_ERROR_RATE__W 16 +#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF +#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0 + + + + +#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F +#define AUD_DEM_WR_FM_DEEMPH__W 16 +#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF +#define AUD_DEM_WR_FM_DEEMPH__PRE 0x0 +#define AUD_DEM_WR_FM_DEEMPH_50US 0x0 +#define AUD_DEM_WR_FM_DEEMPH_75US 0x1 +#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F + + +#define AUD_DEM_WR_FM_MATRIX__A 0x103006F +#define AUD_DEM_WR_FM_MATRIX__W 16 +#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF +#define AUD_DEM_WR_FM_MATRIX__PRE 0x0 +#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x0 +#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x1 +#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2 +#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3 +#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4 + + + +#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018 +#define AUD_DSP_RD_FM_IDENT_VALUE__W 16 +#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF +#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x0 + +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF00 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B +#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C +#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0 + + + +#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F + + + + +#define AUD_DSP_WR_SYNC_OUT__A 0x1050026 +#define AUD_DSP_WR_SYNC_OUT__W 16 +#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF +#define AUD_DSP_WR_SYNC_OUT__PRE 0x0 +#define AUD_DSP_WR_SYNC_OUT_OFF 0x0 +#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1 + + + +#define AUD_XFP_DRAM_1K__A 0x1060000 +#define AUD_XFP_DRAM_1K__W 16 +#define AUD_XFP_DRAM_1K__M 0xFFFF +#define AUD_XFP_DRAM_1K__PRE 0x0 +#define AUD_XFP_DRAM_1K_D__B 0 +#define AUD_XFP_DRAM_1K_D__W 16 +#define AUD_XFP_DRAM_1K_D__M 0xFFFF +#define AUD_XFP_DRAM_1K_D__PRE 0x0 + + + +#define AUD_XFP_PRAM_4K__A 0x1070000 +#define AUD_XFP_PRAM_4K__W 16 +#define AUD_XFP_PRAM_4K__M 0xFFFF +#define AUD_XFP_PRAM_4K__PRE 0x0 +#define AUD_XFP_PRAM_4K_D__B 0 +#define AUD_XFP_PRAM_4K_D__W 16 +#define AUD_XFP_PRAM_4K_D__M 0xFFFF +#define AUD_XFP_PRAM_4K_D__PRE 0x0 + + + +#define AUD_XDFP_DRAM_1K__A 0x1080000 +#define AUD_XDFP_DRAM_1K__W 16 +#define AUD_XDFP_DRAM_1K__M 0xFFFF +#define AUD_XDFP_DRAM_1K__PRE 0x0 +#define AUD_XDFP_DRAM_1K_D__B 0 +#define AUD_XDFP_DRAM_1K_D__W 16 +#define AUD_XDFP_DRAM_1K_D__M 0xFFFF +#define AUD_XDFP_DRAM_1K_D__PRE 0x0 + + + +#define AUD_XDFP_PRAM_4K__A 0x1090000 +#define AUD_XDFP_PRAM_4K__W 16 +#define AUD_XDFP_PRAM_4K__M 0xFFFF +#define AUD_XDFP_PRAM_4K__PRE 0x0 +#define AUD_XDFP_PRAM_4K_D__B 0 +#define AUD_XDFP_PRAM_4K_D__W 16 +#define AUD_XDFP_PRAM_4K_D__M 0xFFFF +#define AUD_XDFP_PRAM_4K_D__PRE 0x0 + + + + + +#define FEC_COMM_EXEC__A 0x2400000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x2400002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x2400003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x2400005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x2400006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x2400007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + + + +#define FEC_TOP_COMM_EXEC__A 0x2410000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + + +#define FEC_TOP_ANNEX__A 0x2410010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + + + +#define FEC_DI_COMM_EXEC__A 0x2420000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x2420002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x2420003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x2420005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x2420006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x2420007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + + +#define FEC_DI_STATUS__A 0x2420010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x2420011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + + +#define FEC_DI_CONTROL_WORD__A 0x2420012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x2420013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x2420014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x2420015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + + + +#define FEC_RS_COMM_EXEC__A 0x2430000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x2430002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x2430003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x2430005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x2430006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x2430007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x2430010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x2430011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x2430012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x2430013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x2430014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x2430015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x2430016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x2430017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + + + +#define FEC_OC_COMM_EXEC__A 0x2440000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x2440002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x2440003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x2440005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x2440006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x2440007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x2440010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x2440011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x2440012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + + +#define FEC_OC_DPR_UNLOCK__A 0x2440013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x2440014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + + +#define FEC_OC_DTO_PERIOD__A 0x2440015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x2440016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x2440017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x2440018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x244001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x244001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x2 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x2 + +#define FEC_OC_FCT_OCCUPATION__A 0x244001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x244001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x244001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x2440020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_LO_MARGIN__A 0x2440021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x2440022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x2440023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x2440026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x2440027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x2440028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x2440029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x244002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x180 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x180 + +#define FEC_OC_RCN_GAIN__A 0x244002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x2440030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x2440031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x2440032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x2440033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x2440034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x2440035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x2440036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x2440037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x2440038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x2440039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x2440040 +#define FEC_OC_SNC_MODE__W 4 +#define FEC_OC_SNC_MODE__M 0xF +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x2440041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x2440042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x2440043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x2440044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x2440045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x2440046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x2440047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x2440048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x2440049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x2440050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x2440051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x2440052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x2440053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x2440054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x2440055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x2440056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x2440057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x2440058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x2440059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x244005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + + + +#define FEC_DI_RAM__A 0x2450000 + + + +#define FEC_RS_RAM__A 0x2460000 + + + +#define FEC_OC_RAM__A 0x2470000 + + + + + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_STOP 0x0 +#define IQM_COMM_EXEC_ACTIVE 0x1 +#define IQM_COMM_EXEC_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 2 +#define IQM_COMM_INT_REQ__M 0x3 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 + + + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 2 +#define IQM_FS_COMM_MB__M 0x3 +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 +#define IQM_FS_ADJ_SEL_OFF 0x0 +#define IQM_FS_ADJ_SEL_QAM 0x1 +#define IQM_FS_ADJ_SEL_VSB 0x2 + + + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + + + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 +#define IQM_RC_ADJ_SEL_OFF 0x0 +#define IQM_RC_ADJ_SEL_QAM 0x1 +#define IQM_RC_ADJ_SEL_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 +#define IQM_RC_STRETCH_QAM_B_64 0x1E +#define IQM_RC_STRETCH_QAM_B_256 0x1C +#define IQM_RC_STRETCH_ATV 0xF + + + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 2 +#define IQM_RT_ROT_BP__M 0x3 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + + + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 1 +#define IQM_CF_COMM_INT_STA__M 0x1 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 1 +#define IQM_CF_COMM_INT_MSK__M 0x1 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 1 +#define IQM_CF_COMM_INT_STM__M 0x1 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 2 +#define IQM_CF_MIDTAP__M 0x3 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_VSB__B 2 +#define IQM_CF_OUT_ENA_VSB__W 1 +#define IQM_CF_OUT_ENA_VSB__M 0x4 +#define IQM_CF_OUT_ENA_VSB__PRE 0x0 + + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 +#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x1 +#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x1 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 + + + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 2 +#define IQM_AF_COMM_INT_STA__M 0x3 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 2 +#define IQM_AF_COMM_INT_MSK__M 0x3 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 2 +#define IQM_AF_COMM_INT_STM__M 0x3 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 + + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 1 +#define IQM_AF_FDB_SEL__M 0x1 +#define IQM_AF_FDB_SEL__PRE 0x0 + +#define IQM_AF_INVEXT__A 0x1870011 +#define IQM_AF_INVEXT__W 1 +#define IQM_AF_INVEXT__M 0x1 +#define IQM_AF_INVEXT__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 +#define IQM_AF_CLP_LEN_QAM_B_64 0x400 +#define IQM_AF_CLP_LEN_QAM_B_256 0x400 +#define IQM_AF_CLP_LEN_ATV 0x0 + + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 +#define IQM_AF_CLP_TH_QAM_B_64 0x80 +#define IQM_AF_CLP_TH_QAM_B_256 0x80 +#define IQM_AF_CLP_TH_ATV 0x1C0 + + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 +#define IQM_AF_SNS_LEN_QAM_B_64 0x400 +#define IQM_AF_SNS_LEN_QAM_B_256 0x400 +#define IQM_AF_SNS_LEN_ATV 0x0 + + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PGA_GAIN__A 0x187002A +#define IQM_AF_PGA_GAIN__W 4 +#define IQM_AF_PGA_GAIN__M 0xF +#define IQM_AF_PGA_GAIN__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_PDREF_QAM_B_64 0xF +#define IQM_AF_PDREF_QAM_B_256 0xF +#define IQM_AF_PDREF_ATV 0xF + +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x0 + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0 + + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 2 +#define IQM_AF_AMUX__M 0x3 +#define IQM_AF_AMUX__PRE 0x0 + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + + + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + + + + + +#define ORX_COMM_EXEC__A 0x2000000 +#define ORX_COMM_EXEC__W 2 +#define ORX_COMM_EXEC__M 0x3 +#define ORX_COMM_EXEC__PRE 0x0 +#define ORX_COMM_EXEC_STOP 0x0 +#define ORX_COMM_EXEC_ACTIVE 0x1 +#define ORX_COMM_EXEC_HOLD 0x2 + +#define ORX_COMM_STATE__A 0x2000001 +#define ORX_COMM_STATE__W 16 +#define ORX_COMM_STATE__M 0xFFFF +#define ORX_COMM_STATE__PRE 0x0 +#define ORX_COMM_MB__A 0x2000002 +#define ORX_COMM_MB__W 16 +#define ORX_COMM_MB__M 0xFFFF +#define ORX_COMM_MB__PRE 0x0 +#define ORX_COMM_INT_REQ__A 0x2000003 +#define ORX_COMM_INT_REQ__W 16 +#define ORX_COMM_INT_REQ__M 0xFFFF +#define ORX_COMM_INT_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_EQU_REQ__B 0 +#define ORX_COMM_INT_REQ_EQU_REQ__W 1 +#define ORX_COMM_INT_REQ_EQU_REQ__M 0x1 +#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_DDC_REQ__B 1 +#define ORX_COMM_INT_REQ_DDC_REQ__W 1 +#define ORX_COMM_INT_REQ_DDC_REQ__M 0x2 +#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_FWP_REQ__B 2 +#define ORX_COMM_INT_REQ_FWP_REQ__W 1 +#define ORX_COMM_INT_REQ_FWP_REQ__M 0x4 +#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_CON_REQ__B 3 +#define ORX_COMM_INT_REQ_CON_REQ__W 1 +#define ORX_COMM_INT_REQ_CON_REQ__M 0x8 +#define ORX_COMM_INT_REQ_CON_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_NSU_REQ__B 4 +#define ORX_COMM_INT_REQ_NSU_REQ__W 1 +#define ORX_COMM_INT_REQ_NSU_REQ__M 0x10 +#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0 + + +#define ORX_COMM_INT_STA__A 0x2000005 +#define ORX_COMM_INT_STA__W 16 +#define ORX_COMM_INT_STA__M 0xFFFF +#define ORX_COMM_INT_STA__PRE 0x0 +#define ORX_COMM_INT_MSK__A 0x2000006 +#define ORX_COMM_INT_MSK__W 16 +#define ORX_COMM_INT_MSK__M 0xFFFF +#define ORX_COMM_INT_MSK__PRE 0x0 +#define ORX_COMM_INT_STM__A 0x2000007 +#define ORX_COMM_INT_STM__W 16 +#define ORX_COMM_INT_STM__M 0xFFFF +#define ORX_COMM_INT_STM__PRE 0x0 + + + +#define ORX_TOP_COMM_EXEC__A 0x2010000 +#define ORX_TOP_COMM_EXEC__W 2 +#define ORX_TOP_COMM_EXEC__M 0x3 +#define ORX_TOP_COMM_EXEC__PRE 0x0 +#define ORX_TOP_COMM_EXEC_STOP 0x0 +#define ORX_TOP_COMM_EXEC_ACTIVE 0x1 +#define ORX_TOP_COMM_EXEC_HOLD 0x2 + + +#define ORX_TOP_COMM_KEY__A 0x201000F +#define ORX_TOP_COMM_KEY__W 16 +#define ORX_TOP_COMM_KEY__M 0xFFFF +#define ORX_TOP_COMM_KEY__PRE 0x0 +#define ORX_TOP_COMM_KEY_KEY 0xFABA + +#define ORX_TOP_MDE_W__A 0x2010010 +#define ORX_TOP_MDE_W__W 2 +#define ORX_TOP_MDE_W__M 0x3 +#define ORX_TOP_MDE_W__PRE 0x2 +#define ORX_TOP_MDE_W_RATE_1544KBPS 0x0 +#define ORX_TOP_MDE_W_RATE_3088KBPS 0x1 +#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x2 +#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0x3 + +#define ORX_TOP_AIF_CTRL_W__A 0x2010011 +#define ORX_TOP_AIF_CTRL_W__W 3 +#define ORX_TOP_AIF_CTRL_W__M 0x7 +#define ORX_TOP_AIF_CTRL_W__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0x1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0x1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x2 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__W 1 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0x4 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4 + + + +#define ORX_FWP_COMM_EXEC__A 0x2020000 +#define ORX_FWP_COMM_EXEC__W 2 +#define ORX_FWP_COMM_EXEC__M 0x3 +#define ORX_FWP_COMM_EXEC__PRE 0x0 +#define ORX_FWP_COMM_EXEC_STOP 0x0 +#define ORX_FWP_COMM_EXEC_ACTIVE 0x1 +#define ORX_FWP_COMM_EXEC_HOLD 0x2 + +#define ORX_FWP_COMM_MB__A 0x2020002 +#define ORX_FWP_COMM_MB__W 8 +#define ORX_FWP_COMM_MB__M 0xFF +#define ORX_FWP_COMM_MB__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL__B 0 +#define ORX_FWP_COMM_MB_CTL__W 1 +#define ORX_FWP_COMM_MB_CTL__M 0x1 +#define ORX_FWP_COMM_MB_CTL__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL_OFF 0x0 +#define ORX_FWP_COMM_MB_CTL_ON 0x1 +#define ORX_FWP_COMM_MB_OBS__B 1 +#define ORX_FWP_COMM_MB_OBS__W 1 +#define ORX_FWP_COMM_MB_OBS__M 0x2 +#define ORX_FWP_COMM_MB_OBS__PRE 0x0 +#define ORX_FWP_COMM_MB_OBS_OFF 0x0 +#define ORX_FWP_COMM_MB_OBS_ON 0x2 + +#define ORX_FWP_COMM_MB_CTL_MUX__B 2 +#define ORX_FWP_COMM_MB_CTL_MUX__W 3 +#define ORX_FWP_COMM_MB_CTL_MUX__M 0x1C +#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_FWP_COMM_MB_OBS_MUX__B 5 +#define ORX_FWP_COMM_MB_OBS_MUX__W 3 +#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0 + + +#define ORX_FWP_AAG_LEN_W__A 0x2020010 +#define ORX_FWP_AAG_LEN_W__W 16 +#define ORX_FWP_AAG_LEN_W__M 0xFFFF +#define ORX_FWP_AAG_LEN_W__PRE 0x800 + +#define ORX_FWP_AAG_THR_W__A 0x2020011 +#define ORX_FWP_AAG_THR_W__W 8 +#define ORX_FWP_AAG_THR_W__M 0xFF +#define ORX_FWP_AAG_THR_W__PRE 0x50 + +#define ORX_FWP_AAG_THR_CNT_R__A 0x2020012 +#define ORX_FWP_AAG_THR_CNT_R__W 16 +#define ORX_FWP_AAG_THR_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_THR_CNT_R__PRE 0x0 + +#define ORX_FWP_AAG_SNS_CNT_R__A 0x2020013 +#define ORX_FWP_AAG_SNS_CNT_R__W 16 +#define ORX_FWP_AAG_SNS_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_SNS_CNT_R__PRE 0x0 + +#define ORX_FWP_PFI_A_W__A 0x2020014 +#define ORX_FWP_PFI_A_W__W 8 +#define ORX_FWP_PFI_A_W__M 0xFF +#define ORX_FWP_PFI_A_W__PRE 0xB0 +#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0xB0 +#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4 +#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0 + + +#define ORX_FWP_PFI_B_W__A 0x2020015 +#define ORX_FWP_PFI_B_W__W 8 +#define ORX_FWP_PFI_B_W__M 0xFF +#define ORX_FWP_PFI_B_W__PRE 0x9E +#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0x9E +#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94 +#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0 + + +#define ORX_FWP_PFI_C_W__A 0x2020016 +#define ORX_FWP_PFI_C_W__W 8 +#define ORX_FWP_PFI_C_W__M 0xFF +#define ORX_FWP_PFI_C_W__PRE 0x5C +#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0x5C +#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64 +#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50 + + +#define ORX_FWP_KR1_AMP_R__A 0x2020017 +#define ORX_FWP_KR1_AMP_R__W 9 +#define ORX_FWP_KR1_AMP_R__M 0x1FF +#define ORX_FWP_KR1_AMP_R__PRE 0x0 + +#define ORX_FWP_KR1_LDT_W__A 0x2020018 +#define ORX_FWP_KR1_LDT_W__W 3 +#define ORX_FWP_KR1_LDT_W__M 0x7 +#define ORX_FWP_KR1_LDT_W__PRE 0x2 +#define ORX_FWP_SRC_DGN_W__A 0x2020019 +#define ORX_FWP_SRC_DGN_W__W 16 +#define ORX_FWP_SRC_DGN_W__M 0xFFFF +#define ORX_FWP_SRC_DGN_W__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_MANT__B 0 +#define ORX_FWP_SRC_DGN_W_MANT__W 9 +#define ORX_FWP_SRC_DGN_W_MANT__M 0x1FF +#define ORX_FWP_SRC_DGN_W_MANT__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_EXP__B 12 +#define ORX_FWP_SRC_DGN_W_EXP__W 4 +#define ORX_FWP_SRC_DGN_W_EXP__M 0xF000 +#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0 + + +#define ORX_FWP_NYQ_ADR_W__A 0x202001A +#define ORX_FWP_NYQ_ADR_W__W 5 +#define ORX_FWP_NYQ_ADR_W__M 0x1F +#define ORX_FWP_NYQ_ADR_W__PRE 0x1F + +#define ORX_FWP_NYQ_COF_RW__A 0x202001B +#define ORX_FWP_NYQ_COF_RW__W 10 +#define ORX_FWP_NYQ_COF_RW__M 0x3FF +#define ORX_FWP_NYQ_COF_RW__PRE 0x0 + +#define ORX_FWP_IQM_FRQ_W__A 0x202001C +#define ORX_FWP_IQM_FRQ_W__W 16 +#define ORX_FWP_IQM_FRQ_W__M 0xFFFF +#define ORX_FWP_IQM_FRQ_W__PRE 0x4301 + + + +#define ORX_EQU_COMM_EXEC__A 0x2030000 +#define ORX_EQU_COMM_EXEC__W 2 +#define ORX_EQU_COMM_EXEC__M 0x3 +#define ORX_EQU_COMM_EXEC__PRE 0x0 +#define ORX_EQU_COMM_EXEC_STOP 0x0 +#define ORX_EQU_COMM_EXEC_ACTIVE 0x1 +#define ORX_EQU_COMM_EXEC_HOLD 0x2 + +#define ORX_EQU_COMM_MB__A 0x2030002 +#define ORX_EQU_COMM_MB__W 8 +#define ORX_EQU_COMM_MB__M 0xFF +#define ORX_EQU_COMM_MB__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL__B 0 +#define ORX_EQU_COMM_MB_CTL__W 1 +#define ORX_EQU_COMM_MB_CTL__M 0x1 +#define ORX_EQU_COMM_MB_CTL__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL_OFF 0x0 +#define ORX_EQU_COMM_MB_CTL_ON 0x1 +#define ORX_EQU_COMM_MB_OBS__B 1 +#define ORX_EQU_COMM_MB_OBS__W 1 +#define ORX_EQU_COMM_MB_OBS__M 0x2 +#define ORX_EQU_COMM_MB_OBS__PRE 0x0 +#define ORX_EQU_COMM_MB_OBS_OFF 0x0 +#define ORX_EQU_COMM_MB_OBS_ON 0x2 + +#define ORX_EQU_COMM_MB_CTL_MUX__B 2 +#define ORX_EQU_COMM_MB_CTL_MUX__W 3 +#define ORX_EQU_COMM_MB_CTL_MUX__M 0x1C +#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_EQU_COMM_MB_OBS_MUX__B 5 +#define ORX_EQU_COMM_MB_OBS_MUX__W 3 +#define ORX_EQU_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_EQU_COMM_INT_REQ__A 0x2030003 +#define ORX_EQU_COMM_INT_REQ__W 1 +#define ORX_EQU_COMM_INT_REQ__M 0x1 +#define ORX_EQU_COMM_INT_REQ__PRE 0x0 +#define ORX_EQU_COMM_INT_STA__A 0x2030005 +#define ORX_EQU_COMM_INT_STA__W 2 +#define ORX_EQU_COMM_INT_STA__M 0x3 +#define ORX_EQU_COMM_INT_STA__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STA_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_MSK__A 0x2030006 +#define ORX_EQU_COMM_INT_MSK__W 2 +#define ORX_EQU_COMM_INT_MSK__M 0x3 +#define ORX_EQU_COMM_INT_MSK__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STM__A 0x2030007 +#define ORX_EQU_COMM_INT_STM__W 2 +#define ORX_EQU_COMM_INT_STM__M 0x3 +#define ORX_EQU_COMM_INT_STM__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0 + + +#define ORX_EQU_FFF_SCL_W__A 0x2030010 +#define ORX_EQU_FFF_SCL_W__W 1 +#define ORX_EQU_FFF_SCL_W__M 0x1 +#define ORX_EQU_FFF_SCL_W__PRE 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1 + + +#define ORX_EQU_FFF_UPD_W__A 0x2030011 +#define ORX_EQU_FFF_UPD_W__W 1 +#define ORX_EQU_FFF_UPD_W__M 0x1 +#define ORX_EQU_FFF_UPD_W__PRE 0x0 +#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1 + + +#define ORX_EQU_FFF_STP_W__A 0x2030012 +#define ORX_EQU_FFF_STP_W__W 3 +#define ORX_EQU_FFF_STP_W__M 0x7 +#define ORX_EQU_FFF_STP_W__PRE 0x2 + +#define ORX_EQU_FFF_LEA_W__A 0x2030013 +#define ORX_EQU_FFF_LEA_W__W 4 +#define ORX_EQU_FFF_LEA_W__M 0xF +#define ORX_EQU_FFF_LEA_W__PRE 0x4 + +#define ORX_EQU_FFF_RWT_W__A 0x2030014 +#define ORX_EQU_FFF_RWT_W__W 2 +#define ORX_EQU_FFF_RWT_W__M 0x3 +#define ORX_EQU_FFF_RWT_W__PRE 0x0 + +#define ORX_EQU_FFF_C0RE_RW__A 0x2030015 +#define ORX_EQU_FFF_C0RE_RW__W 12 +#define ORX_EQU_FFF_C0RE_RW__M 0xFFF +#define ORX_EQU_FFF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C0IM_RW__A 0x2030016 +#define ORX_EQU_FFF_C0IM_RW__W 12 +#define ORX_EQU_FFF_C0IM_RW__M 0xFFF +#define ORX_EQU_FFF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1RE_RW__A 0x2030017 +#define ORX_EQU_FFF_C1RE_RW__W 12 +#define ORX_EQU_FFF_C1RE_RW__M 0xFFF +#define ORX_EQU_FFF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1IM_RW__A 0x2030018 +#define ORX_EQU_FFF_C1IM_RW__W 12 +#define ORX_EQU_FFF_C1IM_RW__M 0xFFF +#define ORX_EQU_FFF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2RE_RW__A 0x2030019 +#define ORX_EQU_FFF_C2RE_RW__W 12 +#define ORX_EQU_FFF_C2RE_RW__M 0xFFF +#define ORX_EQU_FFF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2IM_RW__A 0x203001A +#define ORX_EQU_FFF_C2IM_RW__W 12 +#define ORX_EQU_FFF_C2IM_RW__M 0xFFF +#define ORX_EQU_FFF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3RE_RW__A 0x203001B +#define ORX_EQU_FFF_C3RE_RW__W 12 +#define ORX_EQU_FFF_C3RE_RW__M 0xFFF +#define ORX_EQU_FFF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3IM_RW__A 0x203001C +#define ORX_EQU_FFF_C3IM_RW__W 12 +#define ORX_EQU_FFF_C3IM_RW__M 0xFFF +#define ORX_EQU_FFF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C4RE_RW__A 0x203001D +#define ORX_EQU_FFF_C4RE_RW__W 12 +#define ORX_EQU_FFF_C4RE_RW__M 0xFFF +#define ORX_EQU_FFF_C4RE_RW__PRE 0x400 + +#define ORX_EQU_FFF_C4IM_RW__A 0x203001E +#define ORX_EQU_FFF_C4IM_RW__W 12 +#define ORX_EQU_FFF_C4IM_RW__M 0xFFF +#define ORX_EQU_FFF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5RE_RW__A 0x203001F +#define ORX_EQU_FFF_C5RE_RW__W 12 +#define ORX_EQU_FFF_C5RE_RW__M 0xFFF +#define ORX_EQU_FFF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5IM_RW__A 0x2030020 +#define ORX_EQU_FFF_C5IM_RW__W 12 +#define ORX_EQU_FFF_C5IM_RW__M 0xFFF +#define ORX_EQU_FFF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6RE_RW__A 0x2030021 +#define ORX_EQU_FFF_C6RE_RW__W 12 +#define ORX_EQU_FFF_C6RE_RW__M 0xFFF +#define ORX_EQU_FFF_C6RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6IM_RW__A 0x2030022 +#define ORX_EQU_FFF_C6IM_RW__W 12 +#define ORX_EQU_FFF_C6IM_RW__M 0xFFF +#define ORX_EQU_FFF_C6IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7RE_RW__A 0x2030023 +#define ORX_EQU_FFF_C7RE_RW__W 12 +#define ORX_EQU_FFF_C7RE_RW__M 0xFFF +#define ORX_EQU_FFF_C7RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7IM_RW__A 0x2030024 +#define ORX_EQU_FFF_C7IM_RW__W 12 +#define ORX_EQU_FFF_C7IM_RW__M 0xFFF +#define ORX_EQU_FFF_C7IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8RE_RW__A 0x2030025 +#define ORX_EQU_FFF_C8RE_RW__W 12 +#define ORX_EQU_FFF_C8RE_RW__M 0xFFF +#define ORX_EQU_FFF_C8RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8IM_RW__A 0x2030026 +#define ORX_EQU_FFF_C8IM_RW__W 12 +#define ORX_EQU_FFF_C8IM_RW__M 0xFFF +#define ORX_EQU_FFF_C8IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9RE_RW__A 0x2030027 +#define ORX_EQU_FFF_C9RE_RW__W 12 +#define ORX_EQU_FFF_C9RE_RW__M 0xFFF +#define ORX_EQU_FFF_C9RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9IM_RW__A 0x2030028 +#define ORX_EQU_FFF_C9IM_RW__W 12 +#define ORX_EQU_FFF_C9IM_RW__M 0xFFF +#define ORX_EQU_FFF_C9IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10RE_RW__A 0x2030029 +#define ORX_EQU_FFF_C10RE_RW__W 12 +#define ORX_EQU_FFF_C10RE_RW__M 0xFFF +#define ORX_EQU_FFF_C10RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10IM_RW__A 0x203002A +#define ORX_EQU_FFF_C10IM_RW__W 12 +#define ORX_EQU_FFF_C10IM_RW__M 0xFFF +#define ORX_EQU_FFF_C10IM_RW__PRE 0x0 + +#define ORX_EQU_MXB_SEL_W__A 0x203002B +#define ORX_EQU_MXB_SEL_W__W 1 +#define ORX_EQU_MXB_SEL_W__M 0x1 +#define ORX_EQU_MXB_SEL_W__PRE 0x0 +#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0 +#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1 + + +#define ORX_EQU_FBF_UPD_W__A 0x203002C +#define ORX_EQU_FBF_UPD_W__W 1 +#define ORX_EQU_FBF_UPD_W__M 0x1 +#define ORX_EQU_FBF_UPD_W__PRE 0x0 +#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1 + + +#define ORX_EQU_FBF_STP_W__A 0x203002D +#define ORX_EQU_FBF_STP_W__W 3 +#define ORX_EQU_FBF_STP_W__M 0x7 +#define ORX_EQU_FBF_STP_W__PRE 0x2 + +#define ORX_EQU_FBF_LEA_W__A 0x203002E +#define ORX_EQU_FBF_LEA_W__W 4 +#define ORX_EQU_FBF_LEA_W__M 0xF +#define ORX_EQU_FBF_LEA_W__PRE 0x4 + +#define ORX_EQU_FBF_RWT_W__A 0x203002F +#define ORX_EQU_FBF_RWT_W__W 2 +#define ORX_EQU_FBF_RWT_W__M 0x3 +#define ORX_EQU_FBF_RWT_W__PRE 0x0 + +#define ORX_EQU_FBF_C0RE_RW__A 0x2030030 +#define ORX_EQU_FBF_C0RE_RW__W 12 +#define ORX_EQU_FBF_C0RE_RW__M 0xFFF +#define ORX_EQU_FBF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C0IM_RW__A 0x2030031 +#define ORX_EQU_FBF_C0IM_RW__W 12 +#define ORX_EQU_FBF_C0IM_RW__M 0xFFF +#define ORX_EQU_FBF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1RE_RW__A 0x2030032 +#define ORX_EQU_FBF_C1RE_RW__W 12 +#define ORX_EQU_FBF_C1RE_RW__M 0xFFF +#define ORX_EQU_FBF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1IM_RW__A 0x2030033 +#define ORX_EQU_FBF_C1IM_RW__W 12 +#define ORX_EQU_FBF_C1IM_RW__M 0xFFF +#define ORX_EQU_FBF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2RE_RW__A 0x2030034 +#define ORX_EQU_FBF_C2RE_RW__W 12 +#define ORX_EQU_FBF_C2RE_RW__M 0xFFF +#define ORX_EQU_FBF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2IM_RW__A 0x2030035 +#define ORX_EQU_FBF_C2IM_RW__W 12 +#define ORX_EQU_FBF_C2IM_RW__M 0xFFF +#define ORX_EQU_FBF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3RE_RW__A 0x2030036 +#define ORX_EQU_FBF_C3RE_RW__W 12 +#define ORX_EQU_FBF_C3RE_RW__M 0xFFF +#define ORX_EQU_FBF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3IM_RW__A 0x2030037 +#define ORX_EQU_FBF_C3IM_RW__W 12 +#define ORX_EQU_FBF_C3IM_RW__M 0xFFF +#define ORX_EQU_FBF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4RE_RW__A 0x2030038 +#define ORX_EQU_FBF_C4RE_RW__W 12 +#define ORX_EQU_FBF_C4RE_RW__M 0xFFF +#define ORX_EQU_FBF_C4RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4IM_RW__A 0x2030039 +#define ORX_EQU_FBF_C4IM_RW__W 12 +#define ORX_EQU_FBF_C4IM_RW__M 0xFFF +#define ORX_EQU_FBF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5RE_RW__A 0x203003A +#define ORX_EQU_FBF_C5RE_RW__W 12 +#define ORX_EQU_FBF_C5RE_RW__M 0xFFF +#define ORX_EQU_FBF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5IM_RW__A 0x203003B +#define ORX_EQU_FBF_C5IM_RW__W 12 +#define ORX_EQU_FBF_C5IM_RW__M 0xFFF +#define ORX_EQU_FBF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_ERR_SEL_W__A 0x203003C +#define ORX_EQU_ERR_SEL_W__W 1 +#define ORX_EQU_ERR_SEL_W__M 0x1 +#define ORX_EQU_ERR_SEL_W__PRE 0x0 +#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0 +#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1 + + +#define ORX_EQU_ERR_TIS_W__A 0x203003D +#define ORX_EQU_ERR_TIS_W__W 1 +#define ORX_EQU_ERR_TIS_W__M 0x1 +#define ORX_EQU_ERR_TIS_W__PRE 0x0 +#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0 +#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1 + + +#define ORX_EQU_ERR_EDI_R__A 0x203003E +#define ORX_EQU_ERR_EDI_R__W 5 +#define ORX_EQU_ERR_EDI_R__M 0x1F +#define ORX_EQU_ERR_EDI_R__PRE 0xF + +#define ORX_EQU_ERR_EDQ_R__A 0x203003F +#define ORX_EQU_ERR_EDQ_R__W 5 +#define ORX_EQU_ERR_EDQ_R__M 0x1F +#define ORX_EQU_ERR_EDQ_R__PRE 0xF + +#define ORX_EQU_ERR_ECI_R__A 0x2030040 +#define ORX_EQU_ERR_ECI_R__W 5 +#define ORX_EQU_ERR_ECI_R__M 0x1F +#define ORX_EQU_ERR_ECI_R__PRE 0xF + +#define ORX_EQU_ERR_ECQ_R__A 0x2030041 +#define ORX_EQU_ERR_ECQ_R__W 5 +#define ORX_EQU_ERR_ECQ_R__M 0x1F +#define ORX_EQU_ERR_ECQ_R__PRE 0xF + +#define ORX_EQU_MER_MER_R__A 0x2030042 +#define ORX_EQU_MER_MER_R__W 6 +#define ORX_EQU_MER_MER_R__M 0x3F +#define ORX_EQU_MER_MER_R__PRE 0x3F + +#define ORX_EQU_MER_LDT_W__A 0x2030043 +#define ORX_EQU_MER_LDT_W__W 3 +#define ORX_EQU_MER_LDT_W__M 0x7 +#define ORX_EQU_MER_LDT_W__PRE 0x4 + +#define ORX_EQU_SYN_LEN_W__A 0x2030044 +#define ORX_EQU_SYN_LEN_W__W 16 +#define ORX_EQU_SYN_LEN_W__M 0xFFFF +#define ORX_EQU_SYN_LEN_W__PRE 0x0 + + + +#define ORX_DDC_COMM_EXEC__A 0x2040000 +#define ORX_DDC_COMM_EXEC__W 2 +#define ORX_DDC_COMM_EXEC__M 0x3 +#define ORX_DDC_COMM_EXEC__PRE 0x0 +#define ORX_DDC_COMM_EXEC_STOP 0x0 +#define ORX_DDC_COMM_EXEC_ACTIVE 0x1 +#define ORX_DDC_COMM_EXEC_HOLD 0x2 + +#define ORX_DDC_COMM_MB__A 0x2040002 +#define ORX_DDC_COMM_MB__W 6 +#define ORX_DDC_COMM_MB__M 0x3F +#define ORX_DDC_COMM_MB__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL__B 0 +#define ORX_DDC_COMM_MB_CTL__W 1 +#define ORX_DDC_COMM_MB_CTL__M 0x1 +#define ORX_DDC_COMM_MB_CTL__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL_OFF 0x0 +#define ORX_DDC_COMM_MB_CTL_ON 0x1 +#define ORX_DDC_COMM_MB_OBS__B 1 +#define ORX_DDC_COMM_MB_OBS__W 1 +#define ORX_DDC_COMM_MB_OBS__M 0x2 +#define ORX_DDC_COMM_MB_OBS__PRE 0x0 +#define ORX_DDC_COMM_MB_OBS_OFF 0x0 +#define ORX_DDC_COMM_MB_OBS_ON 0x2 + +#define ORX_DDC_COMM_MB_CTL_MUX__B 2 +#define ORX_DDC_COMM_MB_CTL_MUX__W 2 +#define ORX_DDC_COMM_MB_CTL_MUX__M 0xC +#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_DDC_COMM_MB_OBS_MUX__B 4 +#define ORX_DDC_COMM_MB_OBS_MUX__W 2 +#define ORX_DDC_COMM_MB_OBS_MUX__M 0x30 +#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_DDC_COMM_INT_REQ__A 0x2040003 +#define ORX_DDC_COMM_INT_REQ__W 1 +#define ORX_DDC_COMM_INT_REQ__M 0x1 +#define ORX_DDC_COMM_INT_REQ__PRE 0x0 +#define ORX_DDC_COMM_INT_STA__A 0x2040005 +#define ORX_DDC_COMM_INT_STA__W 1 +#define ORX_DDC_COMM_INT_STA__M 0x1 +#define ORX_DDC_COMM_INT_STA__PRE 0x0 +#define ORX_DDC_COMM_INT_MSK__A 0x2040006 +#define ORX_DDC_COMM_INT_MSK__W 1 +#define ORX_DDC_COMM_INT_MSK__M 0x1 +#define ORX_DDC_COMM_INT_MSK__PRE 0x0 +#define ORX_DDC_COMM_INT_STM__A 0x2040007 +#define ORX_DDC_COMM_INT_STM__W 1 +#define ORX_DDC_COMM_INT_STM__M 0x1 +#define ORX_DDC_COMM_INT_STM__PRE 0x0 +#define ORX_DDC_DEC_MAP_W__A 0x2040010 +#define ORX_DDC_DEC_MAP_W__W 9 +#define ORX_DDC_DEC_MAP_W__M 0x1FF +#define ORX_DDC_DEC_MAP_W__PRE 0x178 + +#define ORX_DDC_DEC_MAP_W_QUADR0__B 0 +#define ORX_DDC_DEC_MAP_W_QUADR0__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR0__M 0x3 +#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0x0 + +#define ORX_DDC_DEC_MAP_W_QUADR1__B 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__M 0xC +#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0x4 + +#define ORX_DDC_DEC_MAP_W_QUADR2__B 4 +#define ORX_DDC_DEC_MAP_W_QUADR2__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR2__M 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0x30 + +#define ORX_DDC_DEC_MAP_W_QUADR3__B 6 +#define ORX_DDC_DEC_MAP_W_QUADR3__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR3__M 0xC0 +#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0x80 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 8 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 1 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0x0 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0x100 + +#define ORX_DDC_OFO_SET_W__A 0x2040011 +#define ORX_DDC_OFO_SET_W__W 16 +#define ORX_DDC_OFO_SET_W__M 0xFFFF +#define ORX_DDC_OFO_SET_W__PRE 0x1402 + +#define ORX_DDC_OFO_SET_W_PHASE__B 0 +#define ORX_DDC_OFO_SET_W_PHASE__W 7 +#define ORX_DDC_OFO_SET_W_PHASE__M 0x7F +#define ORX_DDC_OFO_SET_W_PHASE__PRE 0x2 + +#define ORX_DDC_OFO_SET_W_CRXHITIME__B 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__W 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__M 0x3F80 +#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0x1400 + +#define ORX_DDC_OFO_SET_W_CRXINV__B 14 +#define ORX_DDC_OFO_SET_W_CRXINV__W 1 +#define ORX_DDC_OFO_SET_W_CRXINV__M 0x4000 +#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0x0 + +#define ORX_DDC_OFO_SET_W_DISABLE__B 15 +#define ORX_DDC_OFO_SET_W_DISABLE__W 1 +#define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000 +#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0 + + + +#define ORX_CON_COMM_EXEC__A 0x2050000 +#define ORX_CON_COMM_EXEC__W 2 +#define ORX_CON_COMM_EXEC__M 0x3 +#define ORX_CON_COMM_EXEC__PRE 0x0 +#define ORX_CON_COMM_EXEC_STOP 0x0 +#define ORX_CON_COMM_EXEC_ACTIVE 0x1 +#define ORX_CON_COMM_EXEC_HOLD 0x2 + +#define ORX_CON_LDT_W__A 0x2050010 +#define ORX_CON_LDT_W__W 3 +#define ORX_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W__PRE 0x3 + +#define ORX_CON_LDT_W_CON_LDT_W__B 0 +#define ORX_CON_LDT_W_CON_LDT_W__W 3 +#define ORX_CON_LDT_W_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W_CON_LDT_W__PRE 0x3 + +#define ORX_CON_RST_W__A 0x2050011 +#define ORX_CON_RST_W__W 4 +#define ORX_CON_RST_W__M 0xF +#define ORX_CON_RST_W__PRE 0x0 + +#define ORX_CON_RST_W_CPH__B 0 +#define ORX_CON_RST_W_CPH__W 1 +#define ORX_CON_RST_W_CPH__M 0x1 +#define ORX_CON_RST_W_CPH__PRE 0x0 + +#define ORX_CON_RST_W_CTI__B 1 +#define ORX_CON_RST_W_CTI__W 1 +#define ORX_CON_RST_W_CTI__M 0x2 +#define ORX_CON_RST_W_CTI__PRE 0x0 + +#define ORX_CON_RST_W_KRN__B 2 +#define ORX_CON_RST_W_KRN__W 1 +#define ORX_CON_RST_W_KRN__M 0x4 +#define ORX_CON_RST_W_KRN__PRE 0x0 + +#define ORX_CON_RST_W_KRP__B 3 +#define ORX_CON_RST_W_KRP__W 1 +#define ORX_CON_RST_W_KRP__M 0x8 +#define ORX_CON_RST_W_KRP__PRE 0x0 + + +#define ORX_CON_CPH_PHI_R__A 0x2050012 +#define ORX_CON_CPH_PHI_R__W 16 +#define ORX_CON_CPH_PHI_R__M 0xFFFF +#define ORX_CON_CPH_PHI_R__PRE 0x0 + +#define ORX_CON_CPH_FRQ_R__A 0x2050013 +#define ORX_CON_CPH_FRQ_R__W 16 +#define ORX_CON_CPH_FRQ_R__M 0xFFFF +#define ORX_CON_CPH_FRQ_R__PRE 0x0 + +#define ORX_CON_CPH_AMP_R__A 0x2050014 +#define ORX_CON_CPH_AMP_R__W 16 +#define ORX_CON_CPH_AMP_R__M 0xFFFF +#define ORX_CON_CPH_AMP_R__PRE 0x0 + +#define ORX_CON_CPH_KDF_W__A 0x2050015 +#define ORX_CON_CPH_KDF_W__W 4 +#define ORX_CON_CPH_KDF_W__M 0xF +#define ORX_CON_CPH_KDF_W__PRE 0x0 + +#define ORX_CON_CPH_KPF_W__A 0x2050016 +#define ORX_CON_CPH_KPF_W__W 4 +#define ORX_CON_CPH_KPF_W__M 0xF +#define ORX_CON_CPH_KPF_W__PRE 0x0 + +#define ORX_CON_CPH_KIF_W__A 0x2050017 +#define ORX_CON_CPH_KIF_W__W 4 +#define ORX_CON_CPH_KIF_W__M 0xF +#define ORX_CON_CPH_KIF_W__PRE 0x0 +#define ORX_CON_CPH_APT_W__A 0x2050018 +#define ORX_CON_CPH_APT_W__W 16 +#define ORX_CON_CPH_APT_W__M 0xFFFF +#define ORX_CON_CPH_APT_W__PRE 0x804 + +#define ORX_CON_CPH_APT_W_PTH__B 0 +#define ORX_CON_CPH_APT_W_PTH__W 8 +#define ORX_CON_CPH_APT_W_PTH__M 0xFF +#define ORX_CON_CPH_APT_W_PTH__PRE 0x4 + +#define ORX_CON_CPH_APT_W_ATH__B 8 +#define ORX_CON_CPH_APT_W_ATH__W 8 +#define ORX_CON_CPH_APT_W_ATH__M 0xFF00 +#define ORX_CON_CPH_APT_W_ATH__PRE 0x800 + +#define ORX_CON_CPH_WLC_W__A 0x2050019 +#define ORX_CON_CPH_WLC_W__W 8 +#define ORX_CON_CPH_WLC_W__M 0xFF +#define ORX_CON_CPH_WLC_W__PRE 0x81 + +#define ORX_CON_CPH_WLC_W_LATC__B 0 +#define ORX_CON_CPH_WLC_W_LATC__W 4 +#define ORX_CON_CPH_WLC_W_LATC__M 0xF +#define ORX_CON_CPH_WLC_W_LATC__PRE 0x1 + +#define ORX_CON_CPH_WLC_W_WLIM__B 4 +#define ORX_CON_CPH_WLC_W_WLIM__W 4 +#define ORX_CON_CPH_WLC_W_WLIM__M 0xF0 +#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80 + + +#define ORX_CON_CPH_DLY_W__A 0x205001A +#define ORX_CON_CPH_DLY_W__W 3 +#define ORX_CON_CPH_DLY_W__M 0x7 +#define ORX_CON_CPH_DLY_W__PRE 0x4 + +#define ORX_CON_CPH_TCL_W__A 0x205001B +#define ORX_CON_CPH_TCL_W__W 3 +#define ORX_CON_CPH_TCL_W__M 0x7 +#define ORX_CON_CPH_TCL_W__PRE 0x3 + +#define ORX_CON_KRP_AMP_R__A 0x205001C +#define ORX_CON_KRP_AMP_R__W 9 +#define ORX_CON_KRP_AMP_R__M 0x1FF +#define ORX_CON_KRP_AMP_R__PRE 0x0 + +#define ORX_CON_KRN_AMP_R__A 0x205001D +#define ORX_CON_KRN_AMP_R__W 9 +#define ORX_CON_KRN_AMP_R__M 0x1FF +#define ORX_CON_KRN_AMP_R__PRE 0x0 + +#define ORX_CON_CTI_DTI_R__A 0x205001E +#define ORX_CON_CTI_DTI_R__W 16 +#define ORX_CON_CTI_DTI_R__M 0xFFFF +#define ORX_CON_CTI_DTI_R__PRE 0x0 + +#define ORX_CON_CTI_KDT_W__A 0x205001F +#define ORX_CON_CTI_KDT_W__W 4 +#define ORX_CON_CTI_KDT_W__M 0xF +#define ORX_CON_CTI_KDT_W__PRE 0x4 + +#define ORX_CON_CTI_KPT_W__A 0x2050020 +#define ORX_CON_CTI_KPT_W__W 4 +#define ORX_CON_CTI_KPT_W__M 0xF +#define ORX_CON_CTI_KPT_W__PRE 0x3 + +#define ORX_CON_CTI_KIT_W__A 0x2050021 +#define ORX_CON_CTI_KIT_W__W 4 +#define ORX_CON_CTI_KIT_W__M 0xF +#define ORX_CON_CTI_KIT_W__PRE 0xB + +#define ORX_CON_CTI_TAT_W__A 0x2050022 +#define ORX_CON_CTI_TAT_W__W 4 +#define ORX_CON_CTI_TAT_W__M 0xF +#define ORX_CON_CTI_TAT_W__PRE 0x3 + + + +#define ORX_NSU_COMM_EXEC__A 0x2060000 +#define ORX_NSU_COMM_EXEC__W 2 +#define ORX_NSU_COMM_EXEC__M 0x3 +#define ORX_NSU_COMM_EXEC__PRE 0x0 +#define ORX_NSU_COMM_EXEC_STOP 0x0 +#define ORX_NSU_COMM_EXEC_ACTIVE 0x1 +#define ORX_NSU_COMM_EXEC_HOLD 0x2 + +#define ORX_NSU_AOX_STDBY_W__A 0x2060010 +#define ORX_NSU_AOX_STDBY_W__W 8 +#define ORX_NSU_AOX_STDBY_W__M 0xFF +#define ORX_NSU_AOX_STDBY_W__PRE 0x0 + +#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0x1 + +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x2 + +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 2 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0x4 + +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 3 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0x8 + +#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 4 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0x10 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 5 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0x20 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 6 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0x40 + +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 7 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80 + + +#define ORX_NSU_AOX_LOFRQ_W__A 0x2060011 +#define ORX_NSU_AOX_LOFRQ_W__W 16 +#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF +#define ORX_NSU_AOX_LOFRQ_W__PRE 0x0 +#define ORX_NSU_AOX_LOMDE_W__A 0x2060012 +#define ORX_NSU_AOX_LOMDE_W__W 16 +#define ORX_NSU_AOX_LOMDE_W__M 0xFFFF +#define ORX_NSU_AOX_LOMDE_W__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 0 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 8 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0xFF +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 13 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 1 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0x2000 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 14 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 2 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0 + + +#define ORX_NSU_AOX_LOPOW_W__A 0x2060013 +#define ORX_NSU_AOX_LOPOW_W__W 2 +#define ORX_NSU_AOX_LOPOW_W__M 0x3 +#define ORX_NSU_AOX_LOPOW_W__PRE 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0x1 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3 + + +#define ORX_NSU_AOX_STHR_W__A 0x2060014 +#define ORX_NSU_AOX_STHR_W__W 5 +#define ORX_NSU_AOX_STHR_W__M 0x1F +#define ORX_NSU_AOX_STHR_W__PRE 0x0 + +#define ORX_NSU_TUN_RFGAIN_W__A 0x2060015 +#define ORX_NSU_TUN_RFGAIN_W__W 15 +#define ORX_NSU_TUN_RFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_RFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_IFGAIN_W__A 0x2060016 +#define ORX_NSU_TUN_IFGAIN_W__W 15 +#define ORX_NSU_TUN_IFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_IFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_BPF_W__A 0x2060017 +#define ORX_NSU_TUN_BPF_W__W 15 +#define ORX_NSU_TUN_BPF_W__M 0x7FFF +#define ORX_NSU_TUN_BPF_W__PRE 0x1F9 +#define ORX_NSU_NSS_BITSWAP_W__A 0x2060018 +#define ORX_NSU_NSS_BITSWAP_W__W 3 +#define ORX_NSU_NSS_BITSWAP_W__M 0x7 +#define ORX_NSU_NSS_BITSWAP_W__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 0 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0x1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0 + + + +#define ORX_TST_COMM_EXEC__A 0x23F0000 +#define ORX_TST_COMM_EXEC__W 2 +#define ORX_TST_COMM_EXEC__M 0x3 +#define ORX_TST_COMM_EXEC__PRE 0x0 +#define ORX_TST_COMM_EXEC_STOP 0x0 +#define ORX_TST_COMM_EXEC_ACTIVE 0x1 +#define ORX_TST_COMM_EXEC_HOLD 0x2 + + +#define ORX_TST_AOX_TST_W__A 0x23F0010 +#define ORX_TST_AOX_TST_W__W 8 +#define ORX_TST_AOX_TST_W__M 0xFF +#define ORX_TST_AOX_TST_W__PRE 0x0 + + + + + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + + + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x1 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + + + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + + + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0x0 + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x0 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x0 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 + + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0x0 +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x0 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x0 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x0 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0x0 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x0 + + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 + + + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + + + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 3 +#define QAM_LC_MODE__M 0x7 +#define QAM_LC_MODE__PRE 0x7 + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x1 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x8C + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x8C + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x1E + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x1E + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x78 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x78 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x46 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x46 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x1 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x1 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x1 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x1 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x1 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x1 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x1 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x1 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0x1 + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0x1 + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0x1 + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x1 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x1 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x1 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x1 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x199 + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x199 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0x197 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0x1B2 + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + + + +#define QAM_VD_COMM_EXEC__A 0x1460000 +#define QAM_VD_COMM_EXEC__W 2 +#define QAM_VD_COMM_EXEC__M 0x3 +#define QAM_VD_COMM_EXEC__PRE 0x0 +#define QAM_VD_COMM_EXEC_STOP 0x0 +#define QAM_VD_COMM_EXEC_ACTIVE 0x1 +#define QAM_VD_COMM_EXEC_HOLD 0x2 + +#define QAM_VD_COMM_MB__A 0x1460002 +#define QAM_VD_COMM_MB__W 2 +#define QAM_VD_COMM_MB__M 0x3 +#define QAM_VD_COMM_MB__PRE 0x0 +#define QAM_VD_COMM_MB_CTL__B 0 +#define QAM_VD_COMM_MB_CTL__W 1 +#define QAM_VD_COMM_MB_CTL__M 0x1 +#define QAM_VD_COMM_MB_CTL__PRE 0x0 +#define QAM_VD_COMM_MB_CTL_OFF 0x0 +#define QAM_VD_COMM_MB_CTL_ON 0x1 +#define QAM_VD_COMM_MB_OBS__B 1 +#define QAM_VD_COMM_MB_OBS__W 1 +#define QAM_VD_COMM_MB_OBS__M 0x2 +#define QAM_VD_COMM_MB_OBS__PRE 0x0 +#define QAM_VD_COMM_MB_OBS_OFF 0x0 +#define QAM_VD_COMM_MB_OBS_ON 0x2 + +#define QAM_VD_COMM_INT_REQ__A 0x1460003 +#define QAM_VD_COMM_INT_REQ__W 1 +#define QAM_VD_COMM_INT_REQ__M 0x1 +#define QAM_VD_COMM_INT_REQ__PRE 0x0 +#define QAM_VD_COMM_INT_STA__A 0x1460005 +#define QAM_VD_COMM_INT_STA__W 2 +#define QAM_VD_COMM_INT_STA__M 0x3 +#define QAM_VD_COMM_INT_STA__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_MSK__A 0x1460006 +#define QAM_VD_COMM_INT_MSK__W 2 +#define QAM_VD_COMM_INT_MSK__M 0x3 +#define QAM_VD_COMM_INT_MSK__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STM__A 0x1460007 +#define QAM_VD_COMM_INT_STM__W 2 +#define QAM_VD_COMM_INT_STM__M 0x3 +#define QAM_VD_COMM_INT_STM__PRE 0x0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0x0 + +#define QAM_VD_STATUS__A 0x1460010 +#define QAM_VD_STATUS__W 1 +#define QAM_VD_STATUS__M 0x1 +#define QAM_VD_STATUS__PRE 0x0 + +#define QAM_VD_STATUS_LOCK__B 0 +#define QAM_VD_STATUS_LOCK__W 1 +#define QAM_VD_STATUS_LOCK__M 0x1 +#define QAM_VD_STATUS_LOCK__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL__A 0x1460011 +#define QAM_VD_UNLOCK_CONTROL__W 1 +#define QAM_VD_UNLOCK_CONTROL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 0 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0x0 + +#define QAM_VD_MIN_VOTING_ROUNDS__A 0x1460012 +#define QAM_VD_MIN_VOTING_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS__A 0x1460013 +#define QAM_VD_MAX_VOTING_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH__A 0x1460014 +#define QAM_VD_TRACEBACK_DEPTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 0 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10 + + +#define QAM_VD_UNLOCK__A 0x1460015 +#define QAM_VD_UNLOCK__W 1 +#define QAM_VD_UNLOCK__M 0x1 +#define QAM_VD_UNLOCK__PRE 0x0 +#define QAM_VD_MEASUREMENT_PERIOD__A 0x1460016 +#define QAM_VD_MEASUREMENT_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 0 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PRESCALE__A 0x1460017 +#define QAM_VD_MEASUREMENT_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0x4 + +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x4 + +#define QAM_VD_DELTA_PATH_METRIC__A 0x1460018 +#define QAM_VD_DELTA_PATH_METRIC__W 16 +#define QAM_VD_DELTA_PATH_METRIC__M 0xFFFF +#define QAM_VD_DELTA_PATH_METRIC__PRE 0xFFFF + +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 0 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 12 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0xFFF +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_DELTA_PATH_METRIC_EXP__B 12 +#define QAM_VD_DELTA_PATH_METRIC_EXP__W 4 +#define QAM_VD_DELTA_PATH_METRIC_EXP__M 0xF000 +#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0xF000 + +#define QAM_VD_NR_QSYM_ERRORS__A 0x1460019 +#define QAM_VD_NR_QSYM_ERRORS__W 16 +#define QAM_VD_NR_QSYM_ERRORS__M 0xFFFF +#define QAM_VD_NR_QSYM_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_QSYM_ERRORS_EXP__B 12 +#define QAM_VD_NR_QSYM_ERRORS_EXP__W 4 +#define QAM_VD_NR_QSYM_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_NR_SYMBOL_ERRORS__A 0x146001A +#define QAM_VD_NR_SYMBOL_ERRORS__W 16 +#define QAM_VD_NR_SYMBOL_ERRORS__M 0xFFFF +#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 12 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 4 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_RELOCK_COUNT__A 0x146001B +#define QAM_VD_RELOCK_COUNT__W 16 +#define QAM_VD_RELOCK_COUNT__M 0xFFFF +#define QAM_VD_RELOCK_COUNT__PRE 0x0 + +#define QAM_VD_RELOCK_COUNT_COUNT__B 0 +#define QAM_VD_RELOCK_COUNT_COUNT__W 8 +#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF +#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0 + + + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 2 +#define QAM_SY_COMM_MB__M 0x3 +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + + + +#define QAM_VD_ISS_RAM__A 0x1480000 + + + +#define QAM_VD_QSS_RAM__A 0x1490000 + + + +#define QAM_VD_SYM_RAM__A 0x14A0000 + + + + + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + + + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + + + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + + + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + + + + + + +#define SCU_RAM_AGC_RF_MAX__A 0x831E96 +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x0 + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831E97 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831E98 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831E99 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831E9A +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831E9B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831E9C +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0x0 +#define SCU_RAM_AGC_KI__A 0x831E9D +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x0 + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 12 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 1 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0x1000 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_IF_POL__B 13 +#define SCU_RAM_AGC_KI_INV_IF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 +#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_RF_POL__B 14 +#define SCU_RAM_AGC_KI_INV_RF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 +#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED__A 0x831E9E +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831EA0 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831EA1 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831EA2 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831EA3 +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX__A 0x831EA4 +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0 + + +#define SCU_RAM_AGC_CLP_SUM__A 0x831EA5 +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831EA6 +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831EA7 +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831EA8 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831EA9 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831EAA +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831EAB +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831EAC +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831EAD +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831EAE +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831EAF +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831EB0 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831EB1 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831EB2 +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831EB3 +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN__A 0x831EB4 +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831EB5 +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831EB6 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831EB7 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831EB8 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831EB9 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831EBA +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831EBB +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831EBC +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831EBD +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831EBE +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831EBF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831EC1 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC2 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC3 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_MEAS_COUNT__A 0x831EC4 +#define SCU_RAM_FEC_MEAS_COUNT__W 16 +#define SCU_RAM_FEC_MEAS_COUNT__M 0xFFFF +#define SCU_RAM_FEC_MEAS_COUNT__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0x831EC5 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0x831EC6 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 1 +#define SCU_RAM_GPIO__M 0x1 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0 + + +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0x831F02 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 8 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0xFF +#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0x1 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0x40 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0x41 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0x80 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0x81 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1 + + +#define SCU_RAM_ORX_SCU_STATE__A 0x831F03 +#define SCU_RAM_ORX_SCU_STATE__W 8 +#define SCU_RAM_ORX_SCU_STATE__M 0xFF +#define SCU_RAM_ORX_SCU_STATE__PRE 0x0 +#define SCU_RAM_ORX_SCU_STATE_RESET 0x0 +#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0x1 +#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x2 +#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0x3 +#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0x4 +#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0x8 +#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0x10 +#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0x20 +#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30 +#define SCU_RAM_ORX_SCU_STATE_SYNC 0x40 + + +#define SCU_RAM_ORX_SCU_LOCK__A 0x831F04 +#define SCU_RAM_ORX_SCU_LOCK__W 16 +#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF +#define SCU_RAM_ORX_SCU_LOCK__PRE 0x0 + +#define SCU_RAM_ORX_TARGET_MODE__A 0x831F05 +#define SCU_RAM_ORX_TARGET_MODE__W 2 +#define SCU_RAM_ORX_TARGET_MODE__M 0x3 +#define SCU_RAM_ORX_TARGET_MODE__PRE 0x0 +#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0x0 +#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0x1 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3 + + +#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06 +#define SCU_RAM_ORX_MER_MIN_DB__W 8 +#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF +#define SCU_RAM_ORX_MER_MIN_DB__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN__A 0x831F07 +#define SCU_RAM_ORX_RF_GAIN__W 16 +#define SCU_RAM_ORX_RF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MIN__A 0x831F08 +#define SCU_RAM_ORX_RF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_RF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MAX__A 0x831F09 +#define SCU_RAM_ORX_RF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_RF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN__A 0x831F0A +#define SCU_RAM_ORX_IF_GAIN__W 16 +#define SCU_RAM_ORX_IF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MIN__A 0x831F0B +#define SCU_RAM_ORX_IF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_IF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MAX__A 0x831F0C +#define SCU_RAM_ORX_IF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_IF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR__A 0x831F0D +#define SCU_RAM_ORX_AGN_HEADR__W 16 +#define SCU_RAM_ORX_AGN_HEADR__M 0xFFFF +#define SCU_RAM_ORX_AGN_HEADR__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR_STP__A 0x831F0E +#define SCU_RAM_ORX_AGN_HEADR_STP__W 8 +#define SCU_RAM_ORX_AGN_HEADR_STP__M 0xFF +#define SCU_RAM_ORX_AGN_HEADR_STP__PRE 0x0 + +#define SCU_RAM_ORX_AGN_KI__A 0x831F0F +#define SCU_RAM_ORX_AGN_KI__W 8 +#define SCU_RAM_ORX_AGN_KI__M 0xFF +#define SCU_RAM_ORX_AGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TH__A 0x831F10 +#define SCU_RAM_ORX_AGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_WD__A 0x831F11 +#define SCU_RAM_ORX_AGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_AGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A 0x831F12 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A 0x831F13 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TOTH__A 0x831F14 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_MASK__A 0x831F15 +#define SCU_RAM_ORX_AGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_AGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_DGN__A 0x831F16 +#define SCU_RAM_ORX_DGN__W 16 +#define SCU_RAM_ORX_DGN__M 0xFFFF +#define SCU_RAM_ORX_DGN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MIN__A 0x831F17 +#define SCU_RAM_ORX_DGN_MIN__W 16 +#define SCU_RAM_ORX_DGN_MIN__M 0xFFFF +#define SCU_RAM_ORX_DGN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MAX__A 0x831F18 +#define SCU_RAM_ORX_DGN_MAX__W 16 +#define SCU_RAM_ORX_DGN_MAX__M 0xFFFF +#define SCU_RAM_ORX_DGN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMP__A 0x831F19 +#define SCU_RAM_ORX_DGN_AMP__W 16 +#define SCU_RAM_ORX_DGN_AMP__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMP__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMPTARGET__A 0x831F1A +#define SCU_RAM_ORX_DGN_AMPTARGET__W 16 +#define SCU_RAM_ORX_DGN_AMPTARGET__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMPTARGET__PRE 0x0 + +#define SCU_RAM_ORX_DGN_KI__A 0x831F1B +#define SCU_RAM_ORX_DGN_KI__W 8 +#define SCU_RAM_ORX_DGN_KI__M 0xFF +#define SCU_RAM_ORX_DGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TH__A 0x831F1C +#define SCU_RAM_ORX_DGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_WD__A 0x831F1D +#define SCU_RAM_ORX_DGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_DGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A 0x831F1E +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A 0x831F1F +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TOTH__A 0x831F20 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_MASK__A 0x831F21 +#define SCU_RAM_ORX_DGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_DGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FREQ_GAIN_CORR__A 0x831F22 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__W 8 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__M 0xFF +#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE 0x0 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS 0x60 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0 + + +#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23 +#define SCU_RAM_ORX_FRQ_OFFSET__W 16 +#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_FRQ_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A 0x831F24 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W 15 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M 0x7FFF +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_KI__A 0x831F25 +#define SCU_RAM_ORX_FRQ_KI__W 8 +#define SCU_RAM_ORX_FRQ_KI__M 0xFF +#define SCU_RAM_ORX_FRQ_KI__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_DIFF__A 0x831F26 +#define SCU_RAM_ORX_FRQ_DIFF__W 16 +#define SCU_RAM_ORX_FRQ_DIFF__M 0xFFFF +#define SCU_RAM_ORX_FRQ_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TH__A 0x831F27 +#define SCU_RAM_ORX_FRQ_LOCK_TH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_WD__A 0x831F28 +#define SCU_RAM_ORX_FRQ_LOCK_WD__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A 0x831F29 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A 0x831F2A +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A 0x831F2B +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_MASK__A 0x831F2C +#define SCU_RAM_ORX_FRQ_LOCK_MASK__W 8 +#define SCU_RAM_ORX_FRQ_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_PHA_DIFF__A 0x831F2D +#define SCU_RAM_ORX_PHA_DIFF__W 16 +#define SCU_RAM_ORX_PHA_DIFF__M 0xFFFF +#define SCU_RAM_ORX_PHA_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TH__A 0x831F2E +#define SCU_RAM_ORX_PHA_LOCK_TH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_WD__A 0x831F2F +#define SCU_RAM_ORX_PHA_LOCK_WD__W 16 +#define SCU_RAM_ORX_PHA_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A 0x831F30 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A 0x831F31 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TOTH__A 0x831F32 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_MASK__A 0x831F33 +#define SCU_RAM_ORX_PHA_LOCK_MASK__W 8 +#define SCU_RAM_ORX_PHA_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_TIM_OFFSET__A 0x831F34 +#define SCU_RAM_ORX_TIM_OFFSET__W 16 +#define SCU_RAM_ORX_TIM_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_TIM_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_TIM_DIFF__A 0x831F35 +#define SCU_RAM_ORX_TIM_DIFF__W 16 +#define SCU_RAM_ORX_TIM_DIFF__M 0xFFFF +#define SCU_RAM_ORX_TIM_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TH__A 0x831F36 +#define SCU_RAM_ORX_TIM_LOCK_TH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_WD__A 0x831F37 +#define SCU_RAM_ORX_TIM_LOCK_WD__W 16 +#define SCU_RAM_ORX_TIM_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A 0x831F38 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A 0x831F39 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TOTH__A 0x831F3A +#define SCU_RAM_ORX_TIM_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_MASK__A 0x831F3B +#define SCU_RAM_ORX_TIM_LOCK_MASK__W 8 +#define SCU_RAM_ORX_TIM_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_EQU_DIFF__A 0x831F3C +#define SCU_RAM_ORX_EQU_DIFF__W 16 +#define SCU_RAM_ORX_EQU_DIFF__M 0xFFFF +#define SCU_RAM_ORX_EQU_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TH__A 0x831F3D +#define SCU_RAM_ORX_EQU_LOCK_TH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_WD__A 0x831F3E +#define SCU_RAM_ORX_EQU_LOCK_WD__W 16 +#define SCU_RAM_ORX_EQU_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A 0x831F3F +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A 0x831F40 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TOTH__A 0x831F41 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_MASK__A 0x831F42 +#define SCU_RAM_ORX_EQU_LOCK_MASK__W 8 +#define SCU_RAM_ORX_EQU_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FLT_FRQ__A 0x831F43 +#define SCU_RAM_ORX_FLT_FRQ__W 16 +#define SCU_RAM_ORX_FLT_FRQ__M 0xFFFF +#define SCU_RAM_ORX_FLT_FRQ__PRE 0x0 +#define SCU_RAM_ORX_RST_CPH__A 0x831F44 +#define SCU_RAM_ORX_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CPH_RST_CPH__B 0 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI__A 0x831F45 +#define SCU_RAM_ORX_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI_RST_CTI__B 0 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN__A 0x831F46 +#define SCU_RAM_ORX_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN_RST_KRN__B 0 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP__A 0x831F47 +#define SCU_RAM_ORX_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP_RST_KRP__B 0 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP_RST_KRP__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x0 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_05__A 0x831F56 +#define SCU_RAM_ATV_RSV_05__W 16 +#define SCU_RAM_ATV_RSV_05__M 0xFFFF +#define SCU_RAM_ATV_RSV_05__PRE 0x0 + +#define SCU_RAM_ATV_RSV_06__A 0x831F57 +#define SCU_RAM_ATV_RSV_06__W 16 +#define SCU_RAM_ATV_RSV_06__M 0xFFFF +#define SCU_RAM_ATV_RSV_06__PRE 0x0 + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x0 +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE__A 0x831FD7 +#define SCU_RAM_VSB_CTL_MODE__W 2 +#define SCU_RAM_VSB_CTL_MODE__M 0x3 +#define SCU_RAM_VSB_CTL_MODE__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B 0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M 0x1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON 0x1 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x2 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2 + + +#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF +#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE 0x0 + +#define SCU_RAM_VSB_RSV_0__A 0x831FD9 +#define SCU_RAM_VSB_RSV_0__W 16 +#define SCU_RAM_VSB_RSV_0__M 0xFFFF +#define SCU_RAM_VSB_RSV_0__PRE 0x0 + +#define SCU_RAM_VSB_RSV_1__A 0x831FDA +#define SCU_RAM_VSB_RSV_1__W 16 +#define SCU_RAM_VSB_RSV_1__M 0xFFFF +#define SCU_RAM_VSB_RSV_1__PRE 0x0 + +#define SCU_RAM_VSB_RSV_2__A 0x831FDB +#define SCU_RAM_VSB_RSV_2__W 16 +#define SCU_RAM_VSB_RSV_2__M 0xFFFF +#define SCU_RAM_VSB_RSV_2__PRE 0x0 + +#define SCU_RAM_VSB_RSV_3__A 0x831FDC +#define SCU_RAM_VSB_RSV_3__W 16 +#define SCU_RAM_VSB_RSV_3__M 0xFFFF +#define SCU_RAM_VSB_RSV_3__PRE 0x0 + +#define SCU_RAM_VSB_RSV_4__A 0x831FDD +#define SCU_RAM_VSB_RSV_4__W 16 +#define SCU_RAM_VSB_RSV_4__M 0xFFFF +#define SCU_RAM_VSB_RSV_4__PRE 0x0 + +#define SCU_RAM_VSB_RSV_5__A 0x831FDE +#define SCU_RAM_VSB_RSV_5__W 16 +#define SCU_RAM_VSB_RSV_5__M 0xFFFF +#define SCU_RAM_VSB_RSV_5__PRE 0x0 + +#define SCU_RAM_VSB_RSV_6__A 0x831FDF +#define SCU_RAM_VSB_RSV_6__W 16 +#define SCU_RAM_VSB_RSV_6__M 0xFFFF +#define SCU_RAM_VSB_RSV_6__PRE 0x0 + +#define SCU_RAM_VSB_RSV_7__A 0x831FE0 +#define SCU_RAM_VSB_RSV_7__W 16 +#define SCU_RAM_VSB_RSV_7__M 0xFFFF +#define SCU_RAM_VSB_RSV_7__PRE 0x0 + +#define SCU_RAM_VSB_RSV_8__A 0x831FE1 +#define SCU_RAM_VSB_RSV_8__W 16 +#define SCU_RAM_VSB_RSV_8__M 0xFFFF +#define SCU_RAM_VSB_RSV_8__PRE 0x0 + +#define SCU_RAM_VSB_RSV_9__A 0x831FE2 +#define SCU_RAM_VSB_RSV_9__W 16 +#define SCU_RAM_VSB_RSV_9__M 0xFFFF +#define SCU_RAM_VSB_RSV_9__PRE 0x0 + +#define SCU_RAM_VSB_RSV_10__A 0x831FE3 +#define SCU_RAM_VSB_RSV_10__W 16 +#define SCU_RAM_VSB_RSV_10__M 0xFFFF +#define SCU_RAM_VSB_RSV_10__PRE 0x0 + +#define SCU_RAM_VSB_RSV_11__A 0x831FE4 +#define SCU_RAM_VSB_RSV_11__W 16 +#define SCU_RAM_VSB_RSV_11__M 0xFFFF +#define SCU_RAM_VSB_RSV_11__PRE 0x0 + +#define SCU_RAM_VSB_RSV_12__A 0x831FE5 +#define SCU_RAM_VSB_RSV_12__W 16 +#define SCU_RAM_VSB_RSV_12__M 0xFFFF +#define SCU_RAM_VSB_RSV_12__PRE 0x0 + +#define SCU_RAM_VSB_RSV_13__A 0x831FE6 +#define SCU_RAM_VSB_RSV_13__W 16 +#define SCU_RAM_VSB_RSV_13__M 0xFFFF +#define SCU_RAM_VSB_RSV_13__PRE 0x0 + +#define SCU_RAM_VSB_AGC_POW_TGT__A 0x831FE7 +#define SCU_RAM_VSB_AGC_POW_TGT__W 15 +#define SCU_RAM_VSB_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_VSB_AGC_POW_TGT__PRE 0x0 + +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A 0x831FE8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W 8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M 0xFF +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE 0x0 + +#define SCU_RAM_VSB_FIELD_NUMBER__A 0x831FE9 +#define SCU_RAM_VSB_FIELD_NUMBER__W 9 +#define SCU_RAM_VSB_FIELD_NUMBER__M 0x1FF +#define SCU_RAM_VSB_FIELD_NUMBER__PRE 0x0 + +#define SCU_RAM_VSB_SEGMENT_NUMBER__A 0x831FEA +#define SCU_RAM_VSB_SEGMENT_NUMBER__W 10 +#define SCU_RAM_VSB_SEGMENT_NUMBER__M 0x3FF +#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + + + + + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + + + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + + + + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + + + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + + + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + + + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 5 +#define SIO_CC_CLK_MODE__M 0x1F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 3 +#define SIO_CC_PWD_MODE__M 0x7 +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 2 +#define SIO_CC_PWD_MODE_LEVEL__M 0x3 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x1 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x2 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x3 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 2 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x4 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 2 +#define SIO_CC_SOFT_RST__M 0x3 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 0 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x1 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 1 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x2 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + + + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + + + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 2 +#define SIO_PDR_MON_CFG__M 0x3 +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_FDB_CFG__A 0x7F0011 +#define SIO_PDR_FDB_CFG__W 2 +#define SIO_PDR_FDB_CFG__M 0x3 +#define SIO_PDR_FDB_CFG__PRE 0x0 +#define SIO_PDR_FDB_CFG_SEL__B 0 +#define SIO_PDR_FDB_CFG_SEL__W 2 +#define SIO_PDR_FDB_CFG_SEL__M 0x3 +#define SIO_PDR_FDB_CFG_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_SILENT__A 0x7F0013 +#define SIO_PDR_SMA_TX_SILENT__W 1 +#define SIO_PDR_SMA_TX_SILENT__M 0x1 +#define SIO_PDR_SMA_TX_SILENT__PRE 0x0 +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_IRQN_CFG__A 0x7F0022 +#define SIO_PDR_IRQN_CFG__W 9 +#define SIO_PDR_IRQN_CFG__M 0x1FF +#define SIO_PDR_IRQN_CFG__PRE 0x10 +#define SIO_PDR_IRQN_CFG_MODE__B 0 +#define SIO_PDR_IRQN_CFG_MODE__W 3 +#define SIO_PDR_IRQN_CFG_MODE__M 0x7 +#define SIO_PDR_IRQN_CFG_MODE__PRE 0x0 +#define SIO_PDR_IRQN_CFG_DRIVE__B 3 +#define SIO_PDR_IRQN_CFG_DRIVE__W 3 +#define SIO_PDR_IRQN_CFG_DRIVE__M 0x38 +#define SIO_PDR_IRQN_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_IRQN_CFG_KEEP__B 6 +#define SIO_PDR_IRQN_CFG_KEEP__W 2 +#define SIO_PDR_IRQN_CFG_KEEP__M 0xC0 +#define SIO_PDR_IRQN_CFG_KEEP__PRE 0x0 +#define SIO_PDR_IRQN_CFG_UIO__B 8 +#define SIO_PDR_IRQN_CFG_UIO__W 1 +#define SIO_PDR_IRQN_CFG_UIO__M 0x100 +#define SIO_PDR_IRQN_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_CRX_CFG__A 0x7F0023 +#define SIO_PDR_OOB_CRX_CFG__W 9 +#define SIO_PDR_OOB_CRX_CFG__M 0x1FF +#define SIO_PDR_OOB_CRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_CRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_CRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_CRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_CRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_CRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_CRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_CRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_CRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_CRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_DRX_CFG__A 0x7F0024 +#define SIO_PDR_OOB_DRX_CFG__W 9 +#define SIO_PDR_OOB_DRX_CFG__M 0x1FF +#define SIO_PDR_OOB_DRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_DRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_DRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_DRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_DRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_DRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_DRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_DRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_DRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_DRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_IRQN_GPIO_FNC__A 0x7F0051 +#define SIO_PDR_IRQN_GPIO_FNC__W 2 +#define SIO_PDR_IRQN_GPIO_FNC__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC__PRE 0x0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__B 0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__W 2 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + + + + + + +#define VSB_COMM_EXEC__A 0x1C00000 +#define VSB_COMM_EXEC__W 2 +#define VSB_COMM_EXEC__M 0x3 +#define VSB_COMM_EXEC__PRE 0x0 +#define VSB_COMM_EXEC_STOP 0x0 +#define VSB_COMM_EXEC_ACTIVE 0x1 +#define VSB_COMM_EXEC_HOLD 0x2 + + +#define VSB_COMM_MB__A 0x1C00002 +#define VSB_COMM_MB__W 16 +#define VSB_COMM_MB__M 0xFFFF +#define VSB_COMM_MB__PRE 0x0 +#define VSB_COMM_INT_REQ__A 0x1C00003 +#define VSB_COMM_INT_REQ__W 1 +#define VSB_COMM_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_REQ_TOP_INT_REQ__B 0 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__W 1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0 + + +#define VSB_COMM_INT_STA__A 0x1C00005 +#define VSB_COMM_INT_STA__W 16 +#define VSB_COMM_INT_STA__M 0xFFFF +#define VSB_COMM_INT_STA__PRE 0x0 + +#define VSB_COMM_INT_MSK__A 0x1C00006 +#define VSB_COMM_INT_MSK__W 16 +#define VSB_COMM_INT_MSK__M 0xFFFF +#define VSB_COMM_INT_MSK__PRE 0x0 + +#define VSB_COMM_INT_STM__A 0x1C00007 +#define VSB_COMM_INT_STM__W 16 +#define VSB_COMM_INT_STM__M 0xFFFF +#define VSB_COMM_INT_STM__PRE 0x0 + + + + +#define VSB_TOP_COMM_EXEC__A 0x1C10000 +#define VSB_TOP_COMM_EXEC__W 2 +#define VSB_TOP_COMM_EXEC__M 0x3 +#define VSB_TOP_COMM_EXEC__PRE 0x0 +#define VSB_TOP_COMM_EXEC_STOP 0x0 +#define VSB_TOP_COMM_EXEC_ACTIVE 0x1 +#define VSB_TOP_COMM_EXEC_HOLD 0x2 + +#define VSB_TOP_COMM_MB__A 0x1C10002 +#define VSB_TOP_COMM_MB__W 10 +#define VSB_TOP_COMM_MB__M 0x3FF +#define VSB_TOP_COMM_MB__PRE 0x0 + +#define VSB_TOP_COMM_MB_CTL__B 0 +#define VSB_TOP_COMM_MB_CTL__W 1 +#define VSB_TOP_COMM_MB_CTL__M 0x1 +#define VSB_TOP_COMM_MB_CTL__PRE 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_OFF 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_ON 0x1 + +#define VSB_TOP_COMM_MB_OBS__B 1 +#define VSB_TOP_COMM_MB_OBS__W 1 +#define VSB_TOP_COMM_MB_OBS__M 0x2 +#define VSB_TOP_COMM_MB_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define VSB_TOP_COMM_MB_MUX_CTL__B 2 +#define VSB_TOP_COMM_MB_MUX_CTL__W 4 +#define VSB_TOP_COMM_MB_MUX_CTL__M 0x3C +#define VSB_TOP_COMM_MB_MUX_CTL__PRE 0x0 + +#define VSB_TOP_COMM_MB_MUX_OBS__B 6 +#define VSB_TOP_COMM_MB_MUX_OBS__W 4 +#define VSB_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define VSB_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM 0x40 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE 0x80 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1 0xC0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 0x100 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1 0x140 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2 0x180 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200 + + +#define VSB_TOP_COMM_INT_REQ__A 0x1C10003 +#define VSB_TOP_COMM_INT_REQ__W 1 +#define VSB_TOP_COMM_INT_REQ__M 0x1 +#define VSB_TOP_COMM_INT_REQ__PRE 0x0 +#define VSB_TOP_COMM_INT_STA__A 0x1C10005 +#define VSB_TOP_COMM_INT_STA__W 6 +#define VSB_TOP_COMM_INT_STA__M 0x3F +#define VSB_TOP_COMM_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B 0 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W 1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M 0x1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_LOCK_STA__B 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x2 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__B 2 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__M 0x4 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__B 3 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__M 0x8 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B 4 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W 1 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M 0x10 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_MERSER_STA__B 5 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__M 0x20 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK__A 0x1C10006 +#define VSB_TOP_COMM_INT_MSK__W 6 +#define VSB_TOP_COMM_INT_MSK__M 0x3F +#define VSB_TOP_COMM_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B 0 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M 0x1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__B 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x2 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B 2 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M 0x4 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B 3 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M 0x8 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B 4 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M 0x10 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__B 5 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__M 0x20 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM__A 0x1C10007 +#define VSB_TOP_COMM_INT_STM__W 6 +#define VSB_TOP_COMM_INT_STM__M 0x3F +#define VSB_TOP_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B 0 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W 1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M 0x1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_LOCK_STM__B 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x2 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__B 2 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__M 0x4 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__B 3 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__M 0x8 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B 4 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W 1 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M 0x10 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_MERSER_STM__B 5 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0 + + +#define VSB_TOP_CKGN1ACQ__A 0x1C10010 +#define VSB_TOP_CKGN1ACQ__W 8 +#define VSB_TOP_CKGN1ACQ__M 0xFF +#define VSB_TOP_CKGN1ACQ__PRE 0x4 + +#define VSB_TOP_CKGN1TRK__A 0x1C10011 +#define VSB_TOP_CKGN1TRK__W 8 +#define VSB_TOP_CKGN1TRK__M 0xFF +#define VSB_TOP_CKGN1TRK__PRE 0x0 + +#define VSB_TOP_CKGN2ACQ__A 0x1C10012 +#define VSB_TOP_CKGN2ACQ__W 8 +#define VSB_TOP_CKGN2ACQ__M 0xFF +#define VSB_TOP_CKGN2ACQ__PRE 0x2 + +#define VSB_TOP_CKGN2TRK__A 0x1C10013 +#define VSB_TOP_CKGN2TRK__W 8 +#define VSB_TOP_CKGN2TRK__M 0xFF +#define VSB_TOP_CKGN2TRK__PRE 0x1 + +#define VSB_TOP_CKGN3__A 0x1C10014 +#define VSB_TOP_CKGN3__W 8 +#define VSB_TOP_CKGN3__M 0xFF +#define VSB_TOP_CKGN3__PRE 0x5 + +#define VSB_TOP_CYGN1ACQ__A 0x1C10015 +#define VSB_TOP_CYGN1ACQ__W 8 +#define VSB_TOP_CYGN1ACQ__M 0xFF +#define VSB_TOP_CYGN1ACQ__PRE 0x3 + +#define VSB_TOP_CYGN1TRK__A 0x1C10016 +#define VSB_TOP_CYGN1TRK__W 8 +#define VSB_TOP_CYGN1TRK__M 0xFF +#define VSB_TOP_CYGN1TRK__PRE 0x0 + +#define VSB_TOP_CYGN2ACQ__A 0x1C10017 +#define VSB_TOP_CYGN2ACQ__W 8 +#define VSB_TOP_CYGN2ACQ__M 0xFF +#define VSB_TOP_CYGN2ACQ__PRE 0x3 + +#define VSB_TOP_CYGN2TRK__A 0x1C10018 +#define VSB_TOP_CYGN2TRK__W 8 +#define VSB_TOP_CYGN2TRK__M 0xFF +#define VSB_TOP_CYGN2TRK__PRE 0x2 + +#define VSB_TOP_CYGN3__A 0x1C10019 +#define VSB_TOP_CYGN3__W 8 +#define VSB_TOP_CYGN3__M 0xFF +#define VSB_TOP_CYGN3__PRE 0x6 +#define VSB_TOP_SYNCCTRLWORD__A 0x1C1001A +#define VSB_TOP_SYNCCTRLWORD__W 5 +#define VSB_TOP_SYNCCTRLWORD__M 0x1F +#define VSB_TOP_SYNCCTRLWORD__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_PRST__B 0 +#define VSB_TOP_SYNCCTRLWORD_PRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_PRST__M 0x1 +#define VSB_TOP_SYNCCTRLWORD_PRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__B 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__W 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x2 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_INVCNST__B 2 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__W 1 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__M 0x4 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B 3 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M 0x8 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B 4 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W 1 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0 + + +#define VSB_TOP_MAINSMUP__A 0x1C1001B +#define VSB_TOP_MAINSMUP__W 8 +#define VSB_TOP_MAINSMUP__M 0xFF +#define VSB_TOP_MAINSMUP__PRE 0xFF + +#define VSB_TOP_EQSMUP__A 0x1C1001C +#define VSB_TOP_EQSMUP__W 8 +#define VSB_TOP_EQSMUP__M 0xFF +#define VSB_TOP_EQSMUP__PRE 0xFF +#define VSB_TOP_SYSMUXCTRL__A 0x1C1001D +#define VSB_TOP_SYSMUXCTRL__W 13 +#define VSB_TOP_SYSMUXCTRL__M 0x1FFF +#define VSB_TOP_SYSMUXCTRL__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B 0 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M 0x1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x2 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B 2 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M 0x4 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B 3 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M 0x8 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B 4 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M 0x10 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B 5 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M 0x20 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B 6 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M 0x40 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B 7 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M 0x80 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B 8 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W 4 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M 0xF00 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B 12 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M 0x1000 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SNRTH_RCA1__A 0x1C1001E +#define VSB_TOP_SNRTH_RCA1__W 8 +#define VSB_TOP_SNRTH_RCA1__M 0xFF +#define VSB_TOP_SNRTH_RCA1__PRE 0x53 + +#define VSB_TOP_SNRTH_RCA1_DN__B 0 +#define VSB_TOP_SNRTH_RCA1_DN__W 4 +#define VSB_TOP_SNRTH_RCA1_DN__M 0xF +#define VSB_TOP_SNRTH_RCA1_DN__PRE 0x3 + +#define VSB_TOP_SNRTH_RCA1_UP__B 4 +#define VSB_TOP_SNRTH_RCA1_UP__W 4 +#define VSB_TOP_SNRTH_RCA1_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA1_UP__PRE 0x50 + +#define VSB_TOP_SNRTH_RCA2__A 0x1C1001F +#define VSB_TOP_SNRTH_RCA2__W 8 +#define VSB_TOP_SNRTH_RCA2__M 0xFF +#define VSB_TOP_SNRTH_RCA2__PRE 0x75 + +#define VSB_TOP_SNRTH_RCA2_DN__B 0 +#define VSB_TOP_SNRTH_RCA2_DN__W 4 +#define VSB_TOP_SNRTH_RCA2_DN__M 0xF +#define VSB_TOP_SNRTH_RCA2_DN__PRE 0x5 + +#define VSB_TOP_SNRTH_RCA2_UP__B 4 +#define VSB_TOP_SNRTH_RCA2_UP__W 4 +#define VSB_TOP_SNRTH_RCA2_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA2_UP__PRE 0x70 + +#define VSB_TOP_SNRTH_DDM1__A 0x1C10020 +#define VSB_TOP_SNRTH_DDM1__W 8 +#define VSB_TOP_SNRTH_DDM1__M 0xFF +#define VSB_TOP_SNRTH_DDM1__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM1_DN__B 0 +#define VSB_TOP_SNRTH_DDM1_DN__W 4 +#define VSB_TOP_SNRTH_DDM1_DN__M 0xF +#define VSB_TOP_SNRTH_DDM1_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM1_UP__B 4 +#define VSB_TOP_SNRTH_DDM1_UP__W 4 +#define VSB_TOP_SNRTH_DDM1_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM1_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_DDM2__A 0x1C10021 +#define VSB_TOP_SNRTH_DDM2__W 8 +#define VSB_TOP_SNRTH_DDM2__M 0xFF +#define VSB_TOP_SNRTH_DDM2__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM2_DN__B 0 +#define VSB_TOP_SNRTH_DDM2_DN__W 4 +#define VSB_TOP_SNRTH_DDM2_DN__M 0xF +#define VSB_TOP_SNRTH_DDM2_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM2_UP__B 4 +#define VSB_TOP_SNRTH_DDM2_UP__W 4 +#define VSB_TOP_SNRTH_DDM2_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM2_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_PT__A 0x1C10022 +#define VSB_TOP_SNRTH_PT__W 8 +#define VSB_TOP_SNRTH_PT__M 0xFF +#define VSB_TOP_SNRTH_PT__PRE 0xD8 + +#define VSB_TOP_SNRTH_PT_DN__B 0 +#define VSB_TOP_SNRTH_PT_DN__W 4 +#define VSB_TOP_SNRTH_PT_DN__M 0xF +#define VSB_TOP_SNRTH_PT_DN__PRE 0x8 + +#define VSB_TOP_SNRTH_PT_UP__B 4 +#define VSB_TOP_SNRTH_PT_UP__W 4 +#define VSB_TOP_SNRTH_PT_UP__M 0xF0 +#define VSB_TOP_SNRTH_PT_UP__PRE 0xD0 + +#define VSB_TOP_CYSMSTATES__A 0x1C10023 +#define VSB_TOP_CYSMSTATES__W 8 +#define VSB_TOP_CYSMSTATES__M 0xFF +#define VSB_TOP_CYSMSTATES__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_SYSST__B 0 +#define VSB_TOP_CYSMSTATES_SYSST__W 4 +#define VSB_TOP_CYSMSTATES_SYSST__M 0xF +#define VSB_TOP_CYSMSTATES_SYSST__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_EQST__B 4 +#define VSB_TOP_CYSMSTATES_EQST__W 4 +#define VSB_TOP_CYSMSTATES_EQST__M 0xF0 +#define VSB_TOP_CYSMSTATES_EQST__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL__A 0x1C10024 +#define VSB_TOP_SMALL_NOTCH_CONTROL__W 8 +#define VSB_TOP_SMALL_NOTCH_CONTROL__M 0xFF +#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__B 0 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__M 0x1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B 2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M 0x4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B 3 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W 4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M 0x78 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B 7 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0 + + +#define VSB_TOP_TAPREADCYC__A 0x1C10025 +#define VSB_TOP_TAPREADCYC__W 9 +#define VSB_TOP_TAPREADCYC__M 0x1FF +#define VSB_TOP_TAPREADCYC__PRE 0x1 + +#define VSB_TOP_VALIDPKLVL__A 0x1C10026 +#define VSB_TOP_VALIDPKLVL__W 13 +#define VSB_TOP_VALIDPKLVL__M 0x1FFF +#define VSB_TOP_VALIDPKLVL__PRE 0x100 + +#define VSB_TOP_CENTROID_FINE_DELAY__A 0x1C10027 +#define VSB_TOP_CENTROID_FINE_DELAY__W 10 +#define VSB_TOP_CENTROID_FINE_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_FINE_DELAY__PRE 0xFF + +#define VSB_TOP_CENTROID_SMACH_DELAY__A 0x1C10028 +#define VSB_TOP_CENTROID_SMACH_DELAY__W 10 +#define VSB_TOP_CENTROID_SMACH_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_SMACH_DELAY__PRE 0x1FF + +#define VSB_TOP_SNR__A 0x1C10029 +#define VSB_TOP_SNR__W 14 +#define VSB_TOP_SNR__M 0x3FFF +#define VSB_TOP_SNR__PRE 0x0 +#define VSB_TOP_LOCKSTATUS__A 0x1C1002A +#define VSB_TOP_LOCKSTATUS__W 7 +#define VSB_TOP_LOCKSTATUS__M 0x7F +#define VSB_TOP_LOCKSTATUS__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_VSBMODE__B 0 +#define VSB_TOP_LOCKSTATUS_VSBMODE__W 4 +#define VSB_TOP_LOCKSTATUS_VSBMODE__M 0xF +#define VSB_TOP_LOCKSTATUS_VSBMODE__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_FRMLOCK__B 4 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__M 0x10 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_CYLOCK__B 5 +#define VSB_TOP_LOCKSTATUS_CYLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_CYLOCK__M 0x20 +#define VSB_TOP_LOCKSTATUS_CYLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_DDMON__B 6 +#define VSB_TOP_LOCKSTATUS_DDMON__W 1 +#define VSB_TOP_LOCKSTATUS_DDMON__M 0x40 +#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0 + + +#define VSB_TOP_CTST__A 0x1C1002B +#define VSB_TOP_CTST__W 4 +#define VSB_TOP_CTST__M 0xF +#define VSB_TOP_CTST__PRE 0x0 +#define VSB_TOP_EQSMRSTCTRL__A 0x1C1002C +#define VSB_TOP_EQSMRSTCTRL__W 7 +#define VSB_TOP_EQSMRSTCTRL__M 0x7F +#define VSB_TOP_EQSMRSTCTRL__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_RCAON__B 0 +#define VSB_TOP_EQSMRSTCTRL_RCAON__W 1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DFEON__B 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRSTCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL__A 0x1C1002D +#define VSB_TOP_EQSMTRNCTRL__W 7 +#define VSB_TOP_EQSMTRNCTRL__M 0x7F +#define VSB_TOP_EQSMTRNCTRL__PRE 0x40 + +#define VSB_TOP_EQSMTRNCTRL_RCAON__B 0 +#define VSB_TOP_EQSMTRNCTRL_RCAON__W 1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DFEON__B 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMTRNCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE 0x40 + +#define VSB_TOP_EQSMRCA1CTRL__A 0x1C1002E +#define VSB_TOP_EQSMRCA1CTRL__W 7 +#define VSB_TOP_EQSMRCA1CTRL__M 0x7F +#define VSB_TOP_EQSMRCA1CTRL__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL__A 0x1C1002F +#define VSB_TOP_EQSMRCA2CTRL__W 7 +#define VSB_TOP_EQSMRCA2CTRL__M 0x7F +#define VSB_TOP_EQSMRCA2CTRL__PRE 0x3 + +#define VSB_TOP_EQSMRCA2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL__A 0x1C10030 +#define VSB_TOP_EQSMDDM1CTRL__W 7 +#define VSB_TOP_EQSMDDM1CTRL__M 0x7F +#define VSB_TOP_EQSMDDM1CTRL__PRE 0x6 + +#define VSB_TOP_EQSMDDM1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL__A 0x1C10031 +#define VSB_TOP_EQSMDDM2CTRL__W 7 +#define VSB_TOP_EQSMDDM2CTRL__M 0x7F +#define VSB_TOP_EQSMDDM2CTRL__PRE 0x1E + +#define VSB_TOP_EQSMDDM2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE 0x8 + +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE 0x10 + +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL__A 0x1C10032 +#define VSB_TOP_SYSSMRSTCTRL__W 11 +#define VSB_TOP_SYSSMRSTCTRL__M 0x7FF +#define VSB_TOP_SYSSMRSTCTRL__PRE 0x7F9 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMCYCTRL__A 0x1C10033 +#define VSB_TOP_SYSSMCYCTRL__W 11 +#define VSB_TOP_SYSSMCYCTRL__M 0x7FF +#define VSB_TOP_SYSSMCYCTRL__PRE 0x4E9 + +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMTRNCTRL__A 0x1C10034 +#define VSB_TOP_SYSSMTRNCTRL__W 11 +#define VSB_TOP_SYSSMTRNCTRL__M 0x7FF +#define VSB_TOP_SYSSMTRNCTRL__PRE 0x204 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL__A 0x1C10035 +#define VSB_TOP_SYSSMEQCTRL__W 11 +#define VSB_TOP_SYSSMEQCTRL__M 0x7FF +#define VSB_TOP_SYSSMEQCTRL__PRE 0x304 + +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL__A 0x1C10036 +#define VSB_TOP_SYSSMAGCCTRL__W 11 +#define VSB_TOP_SYSSMAGCCTRL__M 0x7FF +#define VSB_TOP_SYSSMAGCCTRL__PRE 0xF9 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL__A 0x1C10037 +#define VSB_TOP_SYSSMCTCTRL__W 11 +#define VSB_TOP_SYSSMCTCTRL__M 0x7FF +#define VSB_TOP_SYSSMCTCTRL__PRE 0x4A + +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x2 + +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL__A 0x1C10038 +#define VSB_TOP_EQCTRL__W 10 +#define VSB_TOP_EQCTRL__M 0x3FF +#define VSB_TOP_EQCTRL__PRE 0x6 + +#define VSB_TOP_EQCTRL_STASSIGNEN__B 0 +#define VSB_TOP_EQCTRL_STASSIGNEN__W 1 +#define VSB_TOP_EQCTRL_STASSIGNEN__M 0x1 +#define VSB_TOP_EQCTRL_STASSIGNEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_ORCANCMAEN__B 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__W 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x2 +#define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x2 + +#define VSB_TOP_EQCTRL_ODAGCGO__B 2 +#define VSB_TOP_EQCTRL_ODAGCGO__W 1 +#define VSB_TOP_EQCTRL_ODAGCGO__M 0x4 +#define VSB_TOP_EQCTRL_ODAGCGO__PRE 0x4 + +#define VSB_TOP_EQCTRL_OPTGAIN__B 3 +#define VSB_TOP_EQCTRL_OPTGAIN__W 3 +#define VSB_TOP_EQCTRL_OPTGAIN__M 0x38 +#define VSB_TOP_EQCTRL_OPTGAIN__PRE 0x0 + +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__B 6 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__W 1 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__M 0x40 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_CMAGAIN__B 7 +#define VSB_TOP_EQCTRL_CMAGAIN__W 3 +#define VSB_TOP_EQCTRL_CMAGAIN__M 0x380 +#define VSB_TOP_EQCTRL_CMAGAIN__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL__A 0x1C10039 +#define VSB_TOP_PREEQAGCCTRL__W 5 +#define VSB_TOP_PREEQAGCCTRL__M 0x1F +#define VSB_TOP_PREEQAGCCTRL__PRE 0x10 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B 0 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M 0xF +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W 1 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10 + + +#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A +#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8 +#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF +#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE 0x0 + +#define VSB_TOP_PREEQAGCPWRREFLVLLO__A 0x1C1003B +#define VSB_TOP_PREEQAGCPWRREFLVLLO__W 16 +#define VSB_TOP_PREEQAGCPWRREFLVLLO__M 0xFFFF +#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE 0x1D66 + +#define VSB_TOP_CORINGSEL__A 0x1C1003C +#define VSB_TOP_CORINGSEL__W 8 +#define VSB_TOP_CORINGSEL__M 0xFF +#define VSB_TOP_CORINGSEL__PRE 0x3 +#define VSB_TOP_BEDETCTRL__A 0x1C1003D +#define VSB_TOP_BEDETCTRL__W 9 +#define VSB_TOP_BEDETCTRL__M 0x1FF +#define VSB_TOP_BEDETCTRL__PRE 0x145 + +#define VSB_TOP_BEDETCTRL_MIXRATIO__B 0 +#define VSB_TOP_BEDETCTRL_MIXRATIO__W 3 +#define VSB_TOP_BEDETCTRL_MIXRATIO__M 0x7 +#define VSB_TOP_BEDETCTRL_MIXRATIO__PRE 0x5 + +#define VSB_TOP_BEDETCTRL_CYOFFSEL__B 3 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__M 0x8 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__B 4 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__M 0x10 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__B 5 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__M 0x20 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__B 6 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__M 0x40 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE 0x40 + +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__B 7 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__M 0x80 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__B 8 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100 + + +#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E +#define VSB_TOP_LBAGCREFLVL__W 12 +#define VSB_TOP_LBAGCREFLVL__M 0xFFF +#define VSB_TOP_LBAGCREFLVL__PRE 0x200 + +#define VSB_TOP_UBAGCREFLVL__A 0x1C1003F +#define VSB_TOP_UBAGCREFLVL__W 12 +#define VSB_TOP_UBAGCREFLVL__M 0xFFF +#define VSB_TOP_UBAGCREFLVL__PRE 0x400 + +#define VSB_TOP_NOTCH1_BIN_NUM__A 0x1C10040 +#define VSB_TOP_NOTCH1_BIN_NUM__W 11 +#define VSB_TOP_NOTCH1_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH1_BIN_NUM__PRE 0xB2 + +#define VSB_TOP_NOTCH2_BIN_NUM__A 0x1C10041 +#define VSB_TOP_NOTCH2_BIN_NUM__W 11 +#define VSB_TOP_NOTCH2_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH2_BIN_NUM__PRE 0x40B + +#define VSB_TOP_NOTCH_START_BIN_NUM__A 0x1C10042 +#define VSB_TOP_NOTCH_START_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_START_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_START_BIN_NUM__PRE 0x7C0 + +#define VSB_TOP_NOTCH_STOP_BIN_NUM__A 0x1C10043 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE 0x43F + +#define VSB_TOP_NOTCH_TEST_DURATION__A 0x1C10044 +#define VSB_TOP_NOTCH_TEST_DURATION__W 11 +#define VSB_TOP_NOTCH_TEST_DURATION__M 0x7FF +#define VSB_TOP_NOTCH_TEST_DURATION__PRE 0x7FF + +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A 0x1C10045 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A 0x1C10046 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A 0x1C10047 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A 0x1C10048 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_NOTCH_SWEEP_RUNNING__A 0x1C10049 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__W 1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__M 0x1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE 0x0 + +#define VSB_TOP_PREEQDAGCRATIO__A 0x1C1004A +#define VSB_TOP_PREEQDAGCRATIO__W 13 +#define VSB_TOP_PREEQDAGCRATIO__M 0x1FFF +#define VSB_TOP_PREEQDAGCRATIO__PRE 0x0 +#define VSB_TOP_AGC_TRUNCCTRL__A 0x1C1004B +#define VSB_TOP_AGC_TRUNCCTRL__W 4 +#define VSB_TOP_AGC_TRUNCCTRL__M 0xF +#define VSB_TOP_AGC_TRUNCCTRL__PRE 0xF + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B 0 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M 0x3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE 0x3 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M 0x4 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE 0x4 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B 3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8 + + +#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C +#define VSB_TOP_BEAGC_DEADZONEINIT__W 8 +#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_BEAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_BEAGC_REFLEVEL__A 0x1C1004D +#define VSB_TOP_BEAGC_REFLEVEL__W 9 +#define VSB_TOP_BEAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_BEAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_BEAGC_GAINSHIFT__A 0x1C1004E +#define VSB_TOP_BEAGC_GAINSHIFT__W 3 +#define VSB_TOP_BEAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_BEAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_BEAGC_REGINIT__A 0x1C1004F +#define VSB_TOP_BEAGC_REGINIT__W 15 +#define VSB_TOP_BEAGC_REGINIT__M 0x7FFF +#define VSB_TOP_BEAGC_REGINIT__PRE 0x40 + +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B 14 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W 1 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0 + + +#define VSB_TOP_BEAGC_SCALE__A 0x1C10050 +#define VSB_TOP_BEAGC_SCALE__W 14 +#define VSB_TOP_BEAGC_SCALE__M 0x3FFF +#define VSB_TOP_BEAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CFAGC_DEADZONEINIT__A 0x1C10051 +#define VSB_TOP_CFAGC_DEADZONEINIT__W 8 +#define VSB_TOP_CFAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_CFAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_CFAGC_REFLEVEL__A 0x1C10052 +#define VSB_TOP_CFAGC_REFLEVEL__W 9 +#define VSB_TOP_CFAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_CFAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_CFAGC_GAINSHIFT__A 0x1C10053 +#define VSB_TOP_CFAGC_GAINSHIFT__W 3 +#define VSB_TOP_CFAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_CFAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_CFAGC_REGINIT__A 0x1C10054 +#define VSB_TOP_CFAGC_REGINIT__W 15 +#define VSB_TOP_CFAGC_REGINIT__M 0x7FFF +#define VSB_TOP_CFAGC_REGINIT__PRE 0x80 + +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B 14 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W 1 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0 + + +#define VSB_TOP_CFAGC_SCALE__A 0x1C10055 +#define VSB_TOP_CFAGC_SCALE__W 14 +#define VSB_TOP_CFAGC_SCALE__M 0x3FFF +#define VSB_TOP_CFAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CKTRKONCTL__A 0x1C10056 +#define VSB_TOP_CKTRKONCTL__W 2 +#define VSB_TOP_CKTRKONCTL__M 0x3 +#define VSB_TOP_CKTRKONCTL__PRE 0x0 + +#define VSB_TOP_CYTRKONCTL__A 0x1C10057 +#define VSB_TOP_CYTRKONCTL__W 2 +#define VSB_TOP_CYTRKONCTL__M 0x3 +#define VSB_TOP_CYTRKONCTL__PRE 0x0 + +#define VSB_TOP_PTONCTL__A 0x1C10058 +#define VSB_TOP_PTONCTL__W 2 +#define VSB_TOP_PTONCTL__M 0x3 +#define VSB_TOP_PTONCTL__PRE 0x0 + +#define VSB_TOP_NOTCH_SCALE_1__A 0x1C10059 +#define VSB_TOP_NOTCH_SCALE_1__W 8 +#define VSB_TOP_NOTCH_SCALE_1__M 0xFF +#define VSB_TOP_NOTCH_SCALE_1__PRE 0xA + +#define VSB_TOP_NOTCH_SCALE_2__A 0x1C1005A +#define VSB_TOP_NOTCH_SCALE_2__W 8 +#define VSB_TOP_NOTCH_SCALE_2__M 0xFF +#define VSB_TOP_NOTCH_SCALE_2__PRE 0xA + +#define VSB_TOP_FIRSTLARGFFETAP__A 0x1C1005B +#define VSB_TOP_FIRSTLARGFFETAP__W 12 +#define VSB_TOP_FIRSTLARGFFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGFFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGFFETAPADDR__A 0x1C1005C +#define VSB_TOP_FIRSTLARGFFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAP__A 0x1C1005D +#define VSB_TOP_SECONDLARGFFETAP__W 12 +#define VSB_TOP_SECONDLARGFFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGFFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAPADDR__A 0x1C1005E +#define VSB_TOP_SECONDLARGFFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAP__A 0x1C1005F +#define VSB_TOP_FIRSTLARGDFETAP__W 12 +#define VSB_TOP_FIRSTLARGDFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGDFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAPADDR__A 0x1C10060 +#define VSB_TOP_FIRSTLARGDFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAP__A 0x1C10061 +#define VSB_TOP_SECONDLARGDFETAP__W 12 +#define VSB_TOP_SECONDLARGDFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGDFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAPADDR__A 0x1C10062 +#define VSB_TOP_SECONDLARGDFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_PARAOWDBUS__A 0x1C10063 +#define VSB_TOP_PARAOWDBUS__W 12 +#define VSB_TOP_PARAOWDBUS__M 0xFFF +#define VSB_TOP_PARAOWDBUS__PRE 0x0 +#define VSB_TOP_PARAOWCTRL__A 0x1C10064 +#define VSB_TOP_PARAOWCTRL__W 7 +#define VSB_TOP_PARAOWCTRL__M 0x7F +#define VSB_TOP_PARAOWCTRL__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__B 0 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__W 6 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__M 0x3F +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWEN__B 6 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__W 1 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0 + + +#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065 +#define VSB_TOP_CURRENTSEGLOCAT__W 10 +#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF +#define VSB_TOP_CURRENTSEGLOCAT__PRE 0x0 + +#define VSB_TOP_MEASUREMENT_PERIOD__A 0x1C10066 +#define VSB_TOP_MEASUREMENT_PERIOD__W 16 +#define VSB_TOP_MEASUREMENT_PERIOD__M 0xFFFF +#define VSB_TOP_MEASUREMENT_PERIOD__PRE 0x0 + +#define VSB_TOP_NR_SYM_ERRS__A 0x1C10067 +#define VSB_TOP_NR_SYM_ERRS__W 16 +#define VSB_TOP_NR_SYM_ERRS__M 0xFFFF +#define VSB_TOP_NR_SYM_ERRS__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_L__A 0x1C10068 +#define VSB_TOP_ERR_ENERGY_L__W 16 +#define VSB_TOP_ERR_ENERGY_L__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_L__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_H__A 0x1C10069 +#define VSB_TOP_ERR_ENERGY_H__W 16 +#define VSB_TOP_ERR_ENERGY_H__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_H__PRE 0xFFFF + +#define VSB_TOP_SLICER_SEL_8LEV__A 0x1C1006A +#define VSB_TOP_SLICER_SEL_8LEV__W 1 +#define VSB_TOP_SLICER_SEL_8LEV__M 0x1 +#define VSB_TOP_SLICER_SEL_8LEV__PRE 0x1 + +#define VSB_TOP_BNFIELD__A 0x1C1006B +#define VSB_TOP_BNFIELD__W 3 +#define VSB_TOP_BNFIELD__M 0x7 +#define VSB_TOP_BNFIELD__PRE 0x3 + +#define VSB_TOP_CLPLASTNUM__A 0x1C1006C +#define VSB_TOP_CLPLASTNUM__W 8 +#define VSB_TOP_CLPLASTNUM__M 0xFF +#define VSB_TOP_CLPLASTNUM__PRE 0x0 + +#define VSB_TOP_BNSQERR__A 0x1C1006D +#define VSB_TOP_BNSQERR__W 16 +#define VSB_TOP_BNSQERR__M 0xFFFF +#define VSB_TOP_BNSQERR__PRE 0x1AD + +#define VSB_TOP_BNTHRESH__A 0x1C1006E +#define VSB_TOP_BNTHRESH__W 9 +#define VSB_TOP_BNTHRESH__M 0x1FF +#define VSB_TOP_BNTHRESH__PRE 0x120 + +#define VSB_TOP_BNCLPNUM__A 0x1C1006F +#define VSB_TOP_BNCLPNUM__W 16 +#define VSB_TOP_BNCLPNUM__M 0xFFFF +#define VSB_TOP_BNCLPNUM__PRE 0x0 +#define VSB_TOP_PHASELOCKCTRL__A 0x1C10070 +#define VSB_TOP_PHASELOCKCTRL__W 7 +#define VSB_TOP_PHASELOCKCTRL__M 0x7F +#define VSB_TOP_PHASELOCKCTRL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B 0 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M 0x1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x2 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B 2 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M 0x4 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B 3 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M 0x8 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B 4 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M 0x10 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B 5 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M 0x20 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__B 6 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__W 1 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0 + + +#define VSB_TOP_DLOCKACCUM__A 0x1C10071 +#define VSB_TOP_DLOCKACCUM__W 16 +#define VSB_TOP_DLOCKACCUM__M 0xFFFF +#define VSB_TOP_DLOCKACCUM__PRE 0x0 + +#define VSB_TOP_PLOCKACCUM__A 0x1C10072 +#define VSB_TOP_PLOCKACCUM__W 16 +#define VSB_TOP_PLOCKACCUM__M 0xFFFF +#define VSB_TOP_PLOCKACCUM__PRE 0x0 + +#define VSB_TOP_CLOCKACCUM__A 0x1C10073 +#define VSB_TOP_CLOCKACCUM__W 16 +#define VSB_TOP_CLOCKACCUM__M 0xFFFF +#define VSB_TOP_CLOCKACCUM__PRE 0x0 + +#define VSB_TOP_DCRMVACUMI__A 0x1C10074 +#define VSB_TOP_DCRMVACUMI__W 10 +#define VSB_TOP_DCRMVACUMI__M 0x3FF +#define VSB_TOP_DCRMVACUMI__PRE 0x0 + +#define VSB_TOP_DCRMVACUMQ__A 0x1C10075 +#define VSB_TOP_DCRMVACUMQ__W 10 +#define VSB_TOP_DCRMVACUMQ__M 0x3FF +#define VSB_TOP_DCRMVACUMQ__PRE 0x0 + + + + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A 0x1C20001 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A 0x1C20002 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A 0x1C20003 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A 0x1C20004 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A 0x1C20005 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A 0x1C20006 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A 0x1C20007 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A 0x1C20008 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A 0x1C20009 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A 0x1C2000A +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A 0x1C2000B +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A 0x1C2000C +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A 0x1C2000D +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A 0x1C2000E +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A 0x1C2000F +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A 0x1C20010 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A 0x1C20011 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A 0x1C20012 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A 0x1C20013 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A 0x1C20014 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A 0x1C20015 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A 0x1C20016 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A 0x1C20017 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A 0x1C20018 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A 0x1C20019 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A 0x1C2001A +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A 0x1C2001B +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A 0x1C2001C +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A 0x1C2001D +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A 0x1C2001E +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A 0x1C2001F +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A 0x1C20020 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A 0x1C20021 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A 0x1C20022 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A 0x1C20023 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A 0x1C20024 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A 0x1C20025 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A 0x1C20026 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A 0x1C20027 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A 0x1C20028 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A 0x1C20029 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A 0x1C2002A +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A 0x1C2002B +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A 0x1C2002C +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A 0x1C2002D +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A 0x1C2002E +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A 0x1C2002F +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A 0x1C20030 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A 0x1C20031 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A 0x1C20032 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A 0x1C20033 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A 0x1C20034 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A 0x1C20035 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A 0x1C20036 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A 0x1C20037 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A 0x1C20038 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A 0x1C20039 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A 0x1C2003A +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A 0x1C2003B +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A 0x1C2003C +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A 0x1C2003D +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A 0x1C2003E +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A 0x1C2003F +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A 0x1C20040 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A 0x1C20041 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A 0x1C20042 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A 0x1C20043 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A 0x1C20044 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A 0x1C20045 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A 0x1C20046 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A 0x1C20047 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A 0x1C20048 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A 0x1C20049 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A 0x1C2004A +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A 0x1C2004B +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A 0x1C2004C +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A 0x1C2004D +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A 0x1C2004E +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A 0x1C2004F +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A 0x1C20050 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A 0x1C20051 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A 0x1C20052 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A 0x1C20053 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A 0x1C20054 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A 0x1C20055 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A 0x1C20056 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A 0x1C20057 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A 0x1C20058 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A 0x1C20059 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A 0x1C2005A +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A 0x1C2005B +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A 0x1C2005C +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A 0x1C2005D +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A 0x1C2005E +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A 0x1C2005F +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A 0x1C20060 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A 0x1C20061 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A 0x1C20062 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A 0x1C20063 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A 0x1C20064 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A 0x1C20065 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A 0x1C20066 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A 0x1C20067 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A 0x1C20068 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A 0x1C20069 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A 0x1C2006A +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A 0x1C2006B +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A 0x1C2006C +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A 0x1C2006D +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A 0x1C2006E +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A 0x1C2006F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A 0x1C20070 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A 0x1C20071 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A 0x1C20072 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A 0x1C20073 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A 0x1C20074 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A 0x1C20075 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A 0x1C20076 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A 0x1C20077 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE 0x0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A 0x1C20078 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A 0x1C20079 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A 0x1C2007A +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A 0x1C2007B +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A 0x1C2007C +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A 0x1C2007D +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A 0x1C2007E +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A 0x1C2007F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0 + + + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A 0x1C30001 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A 0x1C30002 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A 0x1C30003 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A 0x1C30004 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A 0x1C30005 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A 0x1C30006 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A 0x1C30007 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A 0x1C30008 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A 0x1C30009 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A 0x1C3000A +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A 0x1C3000B +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A 0x1C3000C +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A 0x1C3000D +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A 0x1C3000E +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A 0x1C3000F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A 0x1C30010 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A 0x1C30011 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A 0x1C30012 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A 0x1C30013 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A 0x1C30014 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A 0x1C30015 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A 0x1C30016 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A 0x1C30017 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A 0x1C30018 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A 0x1C30019 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A 0x1C3001A +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A 0x1C3001B +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A 0x1C3001C +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A 0x1C3001D +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A 0x1C3001E +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A 0x1C3001F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A 0x1C30020 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A 0x1C30021 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A 0x1C30022 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A 0x1C30023 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A 0x1C30024 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A 0x1C30025 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A 0x1C30026 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A 0x1C30027 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0 + + +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A 0x1C30029 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A 0x1C3002A +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A 0x1C3002B +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A 0x1C3002C +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A 0x1C3002D +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A 0x1C3002E +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A 0x1C3002F +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A 0x1C30030 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A 0x1C30031 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE 0x0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A 0x1C30032 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A 0x1C30033 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A 0x1C30034 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A 0x1C30035 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0 + + + +#define VSB_TCMEQ_RAM__A 0x1C40000 + +#define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__W 16 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF +#define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0 + + + +#define VSB_FCPRE_RAM__A 0x1C50000 + +#define VSB_FCPRE_RAM_FCPRE_RAM__B 0 +#define VSB_FCPRE_RAM_FCPRE_RAM__W 16 +#define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF +#define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0 + + + +#define VSB_EQTAP_RAM__A 0x1C60000 + +#define VSB_EQTAP_RAM_EQTAP_RAM__B 0 +#define VSB_EQTAP_RAM_EQTAP_RAM__W 12 +#define VSB_EQTAP_RAM_EQTAP_RAM__M 0xFFF +#define VSB_EQTAP_RAM_EQTAP_RAM__PRE 0x0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h new file mode 100644 index 000000000000..8be827276a33 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc.h @@ -0,0 +1,3947 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_MAIN_H__ +#define __DRXJ_MC_MAIN_H__ + +#define DRXJ_MC_MAIN ((pu8_t) drxj_mc_main_g) + +const u8_t drxj_mc_main_g[] = { +0x48, 0x4c, 0x00, 0x06, 0x00, 0x00, 0xf3, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x07, +0x00, 0x00, 0x1f, 0xf0, 0x00, 0x01, 0xdd, 0x81, 0x00, 0x40, 0x0a, 0x00, 0xa4, 0x00, 0x00, 0x00, +0x03, 0x00, 0x2c, 0x16, 0xa4, 0x00, 0x00, 0x00, 0xfe, 0x01, 0xef, 0xff, 0xc8, 0x00, 0x00, 0x00, +0x03, 0x00, 0x0c, 0xa6, 0x27, 0x00, 0x00, 0x00, 0x51, 0x90, 0x08, 0x05, 0xff, 0x00, 0x00, 0x00, +0xa4, 0x81, 0x0c, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x9f, 0x3d, 0x0b, 0x00, 0xa4, 0x00, 0x00, 0x00, +0x9d, 0x35, 0xeb, 0x99, 0xb3, 0x00, 0x00, 0x00, 0x9b, 0x2d, 0xcb, 0x19, 0xb3, 0x00, 0x00, 0x00, +0x99, 0x25, 0xab, 0x99, 0xb2, 0x00, 0x00, 0x00, 0x97, 0x1d, 0x8b, 0x19, 0xb2, 0x00, 0x00, 0x00, +0x91, 0x41, 0x2a, 0x99, 0xb0, 0x00, 0x00, 0x00, 0xa5, 0x20, 0x6d, 0x22, 0xd2, 0x00, 0x00, 0x00, +0x33, 0x18, 0x4d, 0xbb, 0xd1, 0x00, 0x00, 0x00, 0x56, 0x00, 0x0f, 0x24, 0xd0, 0x00, 0x00, 0x00, +0xc4, 0x2b, 0x3d, 0x0a, 0xf0, 0x00, 0x00, 0x00, 0xad, 0x02, 0xcd, 0x2a, 0xd0, 0x00, 0x00, 0x00, +0x64, 0x00, 0x3d, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x8c, 0x80, 0x3e, 0x0b, 0xf0, 0x00, 0x00, 0x00, +0x08, 0x19, 0x9d, 0x20, 0xd1, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0a, 0x01, 0xa4, 0x00, 0x00, 0x00, +0x5c, 0x80, 0x3c, 0x0b, 0xf0, 0x00, 0x00, 0x00, 0x83, 0x80, 0x0c, 0x03, 0xa4, 0x00, 0x00, 0x00, +0x00, 0x20, 0x25, 0x1a, 0x51, 0x00, 0x00, 0x00, 0x92, 0x12, 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b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h new file mode 100644 index 000000000000..a117ec1f3ab1 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h @@ -0,0 +1,752 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_VSB_H__ +#define __DRXJ_MC_VSB_H__ + +#define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g) + +const u8_t drxj_mc_vsb_g[] = { +0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, +0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, 0x90, 0x61, 0x19, 0x7b, +0xf0, 0xef, 0xd0, 0xc0, 0xaf, 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0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00 +}; + +#endif /* __DRXJ_MC_VSB_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h new file mode 100644 index 000000000000..4ef0a07b4d3d --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h @@ -0,0 +1,1444 @@ +/*----------------------------------------------------------------------------- +* DESCRIPTION: +* Contains firmware version: 1.0.8 +* +* USAGE: +* Include. +* +* NOTES: +* (c) 2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. +* +----------------------------------------------------------------------------*/ + +#ifndef __DRXJ_MC_VSBQAM_H__ +#define __DRXJ_MC_VSBQAM_H__ + +#define DRXJ_MC_VSBQAM ((pu8_t) drxj_mc_vsbqam_g) + +const u8_t drxj_mc_vsbqam_g[] = { +0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, +0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xc4, 0x4d, 0x55, 0x02, 0xe4, 0xee, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x02, 0x22, 0x4b, 0x23, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0xa8, 0x53, +0x53, 0xfb, 0xef, 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0x00, 0xff, 0x5b, 0xca, 0xff, 0x90, 0xe0, 0x4b, 0x7b, +0x2f, 0x74, 0x90, 0xf0, 0xf2, 0x7e, 0xa3, 0xe0, 0x25, 0xe0, 0x04, 0xe0, 0x7b, 0x90, 0xf0, 0x58, +0x3a, 0x02, 0x7d, 0x9a, 0x7c, 0x16, 0x7f, 0x71, 0x7e, 0x04, 0x12, 0x00, 0xf5, 0x53, 0x18, 0x7d, +0x71, 0x7c, 0x03, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x30, 0xf5, 0xfd, 0x40, 0x40, 0xc2, 0xd3, 0x8e, +0xd2, 0x8f, 0x24, 0xed, 0xff, 0xff, 0x34, 0xec, 0xf5, 0xff, 0x8f, 0xda, 0x22, 0xd9, 0xa9, 0x53, +0x53, 0xe7, 0xf7, 0xab, 0x04, 0x7f, 0x25, 0x12, 0xc2, 0x01, 0xe4, 0x62, 0x7f, 0x90, 0xf0, 0xf8, +0xf0, 0xa3, 0x90, 0x22, 0x66, 0x7f, 0x1f, 0x74, 0xa3, 0xf0, 0x7f, 0x74, 0xe4, 0xf0, 0x7f, 0x90, +0xf0, 0xf8, 0xf0, 0xa3, 0x30, 0x22, 0xfd, 0x40, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, +0x8c, 0xc1, 0x8d, 0xc3, 0x22, 0xc5, 0x7a, 0x90, 0xe0, 0xbd, 0x90, 0x04, 0xe9, 0x7b, 0x60, 0xf0, +0xe0, 0x05, 0x7a, 0x90, 0xf0, 0xbd, 0x12, 0x22, 0x79, 0x00, 0x55, 0x12, 0x12, 0x41, 0xfa, 0x55, +0x4a, 0x12, 0x02, 0x63, 0x5b, 0x48, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, 0x8c, 0xc1, +0x8d, 0xc3, 0x22, 0xc4, 0x90, 0xe4, 0x66, 0x7f, 0xa3, 0xf0, 0x90, 0xf0, 0xf8, 0x7f, 0xa3, 0xf0, +0x22, 0xf0, 0x7a, 0x90, 0xe0, 0xbd, 0x7a, 0x90, 0xf0, 0xbe, 0x90, 0xe4, 0xbd, 0x7a, 0x22, 0xf0, +0x7f, 0x78, 0xf6, 0xe4, 0xfd, 0xd8, 0x81, 0x75, 0x02, 0x3f, 0x3e, 0x24, 0x06, 0x7d, 0x90, 0x7c, +0x02, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x8e, 0xf5, 0x8f, 0x82, 0xa3, 0x83, 0x82, 0xae, 0x83, 0xaf, +0x20, 0x22, 0x00, 0x59, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x74, 0x92, 0x90, 0xff, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, +0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x02, 0x02, 0x4a, +0xef, 0x52, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, 0x10, 0x00, 0x08, 0x00, +0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00 +}; + +#endif /* __DRXJ_MC_VSBQAM_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_options.h b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h new file mode 100644 index 000000000000..9299551a63a1 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_options.h @@ -0,0 +1,68 @@ +/** +* \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $ +* +* \brief DRXJ optional settings +* +* \author Tao Ding +*/ + +/* +* $(c) 2006-2007,2009 Trident Microsystems, Inc. - All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Trident and are copyright of Trident, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Trident. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Trident is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* TRIDENT'S NEGLIGENCE. $ +* +*/ + +/* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */ +#ifndef __DRXJ_OPTIONS_H__ +#define __DRXJ_OPTIONS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* #define DRXJ_DIGITAL_ONLY */ +/* #define DRXJ_VSB_ONLY */ +/* #define DRXJ_SIGNAL_ACCUM_ERR */ +/* #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x03 */ +/* #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x04 */ +/* #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x05 */ +/* #define OOB_CRX_DRIVE_STRENGTH 0x04 */ +/* #define OOB_DRX_DRIVE_STRENGTH 0x05 */ +/* #define DRXJ_QAM_MAX_WAITTIME 1000 */ +/* #define DRXJ_QAM_FEC_LOCK_WAITTIME 200 */ +/* #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 250 */ + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* __DRXJ_OPTIONS_H__ */ diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 1752e7ef6027..ed0edfdb56b5 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -214,6 +214,17 @@ static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_digital[] = { { -1, -1, -1, -1}, }; +/* PCTV HD Mini (80e) GPIOs + 0-5: not used + 6: demod reset, active low + 7: LED on, active high */ +static struct em28xx_reg_seq em2874_pctv_80e_digital[] = { + {EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/ + {EM2874_R80_GPIO_P0_CTRL, 0x80, 0xff, 100},/*Demod reset*/ + {EM2874_R80_GPIO_P0_CTRL, 0xc0, 0xff, 10}, + { -1, -1, -1, -1}, +}; + /* eb1a:2868 Reddo DVB-C USB TV Box GPIO4 - CU1216L NIM Other GPIOs seems to be don't care. */ @@ -2128,6 +2139,13 @@ struct em28xx_board em28xx_boards[] = { .tuner_gpio = default_tuner_gpio, .def_i2c_bus = 1, }, + [EM2874_BOARD_PCTV_HD_MINI_80E] = { + .name = "Pinnacle PCTV HD Mini", + .tuner_type = TUNER_ABSENT, + .has_dvb = 1, + .dvb_gpio = em2874_pctv_80e_digital, + .decoder = EM28XX_NODECODER, + }, /* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam * Empia EM2765 + OmniVision OV2640 */ [EM2765_BOARD_SPEEDLINK_VAD_LAPLACE] = { @@ -2290,6 +2308,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E }, { USB_DEVICE(0x2304, 0x0227), .driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO }, + { USB_DEVICE(0x2304, 0x023f), + .driver_info = EM2874_BOARD_PCTV_HD_MINI_80E }, { USB_DEVICE(0x0413, 0x6023), .driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII }, { USB_DEVICE(0x093b, 0xa003), diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 16c4d58a985b..a63a3a2fbd55 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -41,6 +41,7 @@ #include "mt352.h" #include "mt352_priv.h" /* FIXME */ #include "tda1002x.h" +#include "drx39xyj/drx39xxj.h" #include "tda18271.h" #include "s921.h" #include "drxd.h" @@ -821,6 +822,20 @@ static const struct m88ds3103_config pctv_461e_m88ds3103_config = { .agc = 0x99, }; + +static struct tda18271_std_map drx_j_std_map = { + .atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1, + .rfagc_top = 0x37, }, + .qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1, + .rfagc_top = 0x37, }, +}; + +static struct tda18271_config pinnacle_80e_dvb_config = { + .std_map = &drx_j_std_map, + .gate = TDA18271_GATE_DIGITAL, + .role = TDA18271_MASTER, +}; + /* ------------------------------------------------------------------ */ static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev) @@ -1374,6 +1389,18 @@ static int em28xx_dvb_init(struct em28xx *dev) goto out_free; } break; + case EM2874_BOARD_PCTV_HD_MINI_80E: + dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap[dev->def_i2c_bus]); + if (dvb->fe[0] != NULL) { + dvb->fe[0] = dvb_attach(tda18271_attach, dvb->fe[0], 0x60, + &dev->i2c_adap[dev->def_i2c_bus], + &pinnacle_80e_dvb_config); + if (!dvb->fe[0]) { + result = -EINVAL; + goto out_free; + } + } + break; case EM28178_BOARD_PCTV_461E: { /* demod I2C adapter */ diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 9b02f15485d1..90e7cec389fb 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -104,6 +104,7 @@ #define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56 #define EM2883_BOARD_KWORLD_HYBRID_330U 57 #define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58 +#define EM2874_BOARD_PCTV_HD_MINI_80E 59 #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60 #define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61 #define EM2820_BOARD_GADMEI_TVR200 62 -- 2.30.2