From 383d30e72e682021fdaf0371ade1c58ad2c434a4 Mon Sep 17 00:00:00 2001 From: Jiaxin Yu Date: Tue, 21 May 2019 17:29:38 +0800 Subject: [PATCH] ASoC: Mediatek: MT8183: fix compile error mtk_regmap_update_bits() has been changed to take a shift and warn when reg >= 0 but shift < 0.So the hd_align_mshift must not have shift. Change it from XXX_HD_ALIGN_MASK_SFT to XXX_HD_ALIGN_MASK. Fixes: cf61f5b01531 ("ASoC: Mediatek: MT8183: set data align") Signed-off-by: Jiaxin Yu Signed-off-by: Mark Brown --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c index ab2bce1d9b3d..56c37323bc13 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -439,7 +439,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL1_HD_SFT, - .hd_align_mshift = DL1_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL1_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -460,7 +460,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL2_HD_SFT, - .hd_align_mshift = DL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -481,7 +481,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL3_HD_SFT, - .hd_align_mshift = DL3_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL3_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -502,7 +502,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL2_HD_SFT, - .hd_align_mshift = VUL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -523,7 +523,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB_HD_SFT, - .hd_align_mshift = AWB_HD_ALIGN_MASK_SFT, + .hd_align_mshift = AWB_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -544,7 +544,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB2_HD_SFT, - .hd_align_mshift = AWB2_ALIGN_MASK_SFT, + .hd_align_mshift = AWB2_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -565,7 +565,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL12_HD_SFT, - .hd_align_mshift = VUL12_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL12_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -586,7 +586,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = MOD_DAI_HD_SFT, - .hd_align_mshift = MOD_DAI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -607,7 +607,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = HDMI_HD_SFT, - .hd_align_mshift = HDMI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = HDMI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, -- 2.30.2