From 37495fbdf12d1bce30dbc228c901ef45eba35739 Mon Sep 17 00:00:00 2001 From: Jaehyun Chung Date: Mon, 15 Jul 2019 17:35:56 -0400 Subject: [PATCH] drm/amd/display: Add work-around option to skip DCN20 clock updates [Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround, and it's corresponding enable flag. Signed-off-by: Jaehyun Chung Reviewed-by: Alvin Lee Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 3 +++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 24775ab81216..3e8ac303bd52 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -198,6 +198,9 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, bool force_reset = false; int i; + if (dc->work_arounds.skip_clock_update) + return; + if (clk_mgr_base->clks.dispclk_khz == 0 || dc->debug.force_clock_mode & 0x1) { //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e3d7710b5c54..1866fa71a764 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -122,6 +122,7 @@ struct dc_bug_wa { bool no_connect_phy_config; bool dedcn20_305_wa; struct display_mode_lib alternate_dml; + bool skip_clock_update; }; #endif -- 2.30.2