From 368fb26c1e55a187131a794f95420d96d31d0e5e Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 May 2019 00:43:57 +0200 Subject: [PATCH] MIPS: Decode config3 register on Ingenic SoCs XBurst misses a config2 register, so config3 decode was skipped in decode_configs(). Signed-off-by: Paul Cercueil Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- arch/mips/kernel/cpu-probe.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index fd77dbc29af9..a9c82338396a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1956,9 +1956,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + + /* + * XBurst misses a config2 register, so config3 decode was skipped in + * decode_configs(). + */ + decode_config3(c); + /* XBurst does not implement the CP0 counter. */ c->options &= ~MIPS_CPU_COUNTER; BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_XBURST: c->cputype = CPU_XBURST; -- 2.30.2